# HG changeset patch
# User Christos Kotselidis <christos.kotselidis@oracle.com>
# Date 1370865920 -7200
# Node ID a5adff75cb935d9ab71494f42a61f2089a8de38c
# Parent  8369c5780c7733afce47e5835f5107c7e6502964
Add comments and minor renaming

diff -r 8369c5780c77 -r a5adff75cb93 graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64Move.java
--- a/graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64Move.java	Mon Jun 10 13:04:38 2013 +0200
+++ b/graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64Move.java	Mon Jun 10 14:05:20 2013 +0200
@@ -138,7 +138,7 @@
         public void emitMemAccess(AMD64MacroAssembler masm) {
             Register resRegister = asRegister(result);
             masm.movl(resRegister, address.toAddress());
-            decodeOop(masm, resRegister, narrowOopBase, narrowOopShift, logMinObjAlignment);
+            decodePointer(masm, resRegister, narrowOopBase, narrowOopShift, logMinObjAlignment);
         }
     }
 
@@ -212,7 +212,7 @@
         @Override
         public void emitCode(TargetMethodAssembler tasm, AMD64MacroAssembler masm) {
             masm.movq(asRegister(scratch), asRegister(input));
-            encodeOop(masm, asRegister(scratch), narrowOopBase, narrowOopShift, logMinObjAlignment);
+            encodePointer(masm, asRegister(scratch), narrowOopBase, narrowOopShift, logMinObjAlignment);
             if (state != null) {
                 tasm.recordImplicitException(masm.codeBuffer.position(), state);
             }
@@ -647,34 +647,41 @@
         final Register scratchRegister = asRegister(scratch);
         final Register cmpRegister = asRegister(cmpValue);
         final Register newRegister = asRegister(newValue);
-        encodeOop(masm, cmpRegister, narrowOopBase, narrowOopShift, logMinObjAlignment);
+        encodePointer(masm, cmpRegister, narrowOopBase, narrowOopShift, logMinObjAlignment);
         masm.movq(scratchRegister, newRegister);
-        encodeOop(masm, scratchRegister, narrowOopBase, narrowOopShift, logMinObjAlignment);
+        encodePointer(masm, scratchRegister, narrowOopBase, narrowOopShift, logMinObjAlignment);
         if (tasm.target.isMP) {
             masm.lock();
         }
         masm.cmpxchgl(scratchRegister, address.toAddress());
     }
 
-    private static void encodeOop(AMD64MacroAssembler masm, Register scratchRegister, long narrowOopBase, int narrowOopShift, int logMinObjAlignment) {
+    private static void encodePointer(AMD64MacroAssembler masm, Register scratchRegister, long narrowOopBase, int narrowOopShift, int logMinObjAlignment) {
+        // If the narrowOopBase is zero, the uncompressed address has to be shifted right
+        // in order to be compressed.
         if (narrowOopBase == 0) {
             if (narrowOopShift != 0) {
                 assert logMinObjAlignment == narrowOopShift : "Encode algorithm is wrong";
                 masm.shrq(scratchRegister, logMinObjAlignment);
             }
         } else {
+            // Otherwise the narrow heap base, which resides always in register 12, is subtracted
+            // followed by right shift.
             masm.subq(scratchRegister, AMD64.r12);
             masm.shrq(scratchRegister, logMinObjAlignment);
         }
     }
 
-    private static void decodeOop(AMD64MacroAssembler masm, Register resRegister, long narrowOopBase, int narrowOopShift, int logMinObjAlignment) {
+    private static void decodePointer(AMD64MacroAssembler masm, Register resRegister, long narrowOopBase, int narrowOopShift, int logMinObjAlignment) {
+        // If the narrowOopBase is zero, the compressed address has to be shifted left
+        // in order to be uncompressed.
         if (narrowOopBase == 0) {
             if (narrowOopShift != 0) {
                 assert logMinObjAlignment == narrowOopShift : "Decode algorithm is wrong";
                 masm.shlq(resRegister, logMinObjAlignment);
             }
         } else {
+            // Otherwise the narrow heap base is added to the shifted address.
             masm.shlq(resRegister, logMinObjAlignment);
             masm.addq(resRegister, AMD64.r12);
         }