# HG changeset patch
# User Stefan Anzinger <stefan.anzinger@oracle.com>
# Date 1425039832 -3600
# Node ID b1b887938753935fc5a9c427012d1c59a6fc82ef
# Parent  2819dcd694b971760970e1e7f619a0daca86cb26
[SPARC] Change fcmp

diff -r 2819dcd694b9 -r b1b887938753 graal/com.oracle.graal.asm.sparc/src/com/oracle/graal/asm/sparc/SPARCAssembler.java
--- a/graal/com.oracle.graal.asm.sparc/src/com/oracle/graal/asm/sparc/SPARCAssembler.java	Fri Feb 27 11:52:03 2015 +0100
+++ b/graal/com.oracle.graal.asm.sparc/src/com/oracle/graal/asm/sparc/SPARCAssembler.java	Fri Feb 27 13:23:52 2015 +0100
@@ -88,18 +88,6 @@
     protected static final int D10LO_SHIFT = 5;
     protected static final int D10HI_SHIFT = 19;
 
-    public static class Fmt3f {
-
-        public Fmt3f(SPARCAssembler masm, int op, int op3, int rcond, int rs1, int simm10, int rd) {
-            assert op == 2 || op == 3;
-            assert op3 >= 0 && op3 < 0x40;
-            assert rs1 >= 0 && rs1 < 0x20;
-            assert rd >= 0 && rd < 0x20;
-
-            masm.emitInt(op << 30 | rd << 25 | op3 << 19 | ImmedTrue | rs1 << 14 | rcond << 10 | (simm10 & 0x000003ff));
-        }
-    }
-
     public static class Fmt3n {
         private int op;
         private int op3;
@@ -161,44 +149,6 @@
 
     // @formatter:off
     /**
-     * Instruction format for fcmp.
-     * <pre>
-     * | 10  | --- |cc1|cc0|desc |   rs1   |   opf  | rs2 |
-     * |31 30|29 27|26 |25 |24 19|18     14|13     5|4   0|
-     * </pre>
-     */
-    // @formatter:on
-    public static class Fmt3c {
-        private int op;
-        private int cc;
-        private int desc;
-        private int opf;
-        private int rs1;
-        private int rs2;
-
-        public Fmt3c(Ops op, CC cc, int desc, Opfs opf, Register rs1, Register rs2) {
-            this.op = op.getValue();
-            this.opf = opf.getValue();
-            this.desc = desc;
-            this.rs1 = rs1.encoding();
-            this.rs2 = rs2.encoding();
-            this.cc = cc.getValue();
-        }
-
-        public void emit(SPARCAssembler masm) {
-            assert op == 2 || op == 3;
-            assert cc >= 0 && cc < 0x4;
-            assert opf >= 0 && opf < 0x200;
-            assert rs1 >= 0 && rs1 < 0x20;
-            assert rs2 >= 0 && rs2 < 0x20;
-            assert desc >= 0 && desc < 0x40;
-
-            masm.emitInt(op << 30 | cc << 25 | desc << 19 | rs1 << 14 | opf << 5 | rs2);
-        }
-    }
-
-    // @formatter:off
-    /**
      * Instruction format for Arithmetic, Logical, Moves, Tcc, Prefetch, and Misc.
      * <pre>
      * | 10  |   rd   |   op3   |   rs1   | i|     imm_asi   |   rs2   |
@@ -2833,13 +2783,34 @@
         }
     }
 
-    public static class Fcmp extends Fmt3c {
-
-        public Fcmp(CC cc, Opfs opf, Register r1, Register r2) {
-            super(Ops.ArithOp, cc, 0b110101, opf, r1, r2);
-            assert opf != Opfs.Fcmpd || (isDoubleFloatRegister(r1) && isDoubleFloatRegister(r2));
-            assert opf != Opfs.Fcmps || (isSingleFloatRegister(r1) && isSingleFloatRegister(r2));
-        }
+    // @formatter:off
+    /**
+     * Instruction format for fcmp.
+     * <pre>
+     * | 10  | --- |cc1|cc0|desc |   rs1   |   opf  | rs2 |
+     * |31 30|29 27|26 |25 |24 19|18     14|13     5|4   0|
+     * </pre>
+     */
+    // @formatter:on
+    public void fcmp(CC cc, Opfs opf, Register rs1, Register rs2) {
+        int a = cc.value;
+        int b = opf.value << 5 | rs2.encoding;
+        fmt10(a, Op3s.Fcmp.value, rs1.encoding, b);
+    }
+
+    // @formatter:off
+    /**
+     * Instruction format for most arithmetic stuff.
+     * <pre>
+     * |  10 | rd  | op3 | rs1 |   b   |
+     * |31 30|29 25|24 19|18 14|13    0|
+     * </pre>
+     */
+    // @formatter:on
+    protected void fmt10(int rd, int op3, int rs1, int b) {
+        assert isImm(rd, 5) && isImm(op3, 6) && isImm(b, 14) : String.format("rd: 0x%x op3: 0x%x b: 0x%x", rd, op3, b);
+        int instr = 1 << 31 | rd << 25 | op3 << 19 | rs1 << 14 | b;
+        emitInt(instr);
     }
 
     public void illtrap(int const22) {
@@ -2978,17 +2949,6 @@
         }
     }
 
-    public static class Movr extends Fmt3f {
-
-        public Movr(SPARCAssembler masm, RCondition rc, Register src1, Register src2, Register dst) {
-            super(masm, Ops.ArithOp.getValue(), Op3s.Movr.getValue(), rc.getValue(), src1.encoding(), src2.encoding(), dst.encoding());
-        }
-
-        public Movr(SPARCAssembler masm, RCondition rc, Register src1, int simm10, Register dst) {
-            super(masm, Ops.ArithOp.getValue(), Op3s.Movr.getValue(), rc.getValue(), src1.encoding(), simm10, dst.encoding());
-        }
-    }
-
     @Deprecated
     public static class Mulscc extends Fmt10 {
 
diff -r 2819dcd694b9 -r b1b887938753 graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCArithmetic.java
--- a/graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCArithmetic.java	Fri Feb 27 11:52:03 2015 +0100
+++ b/graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCArithmetic.java	Fri Feb 27 13:23:52 2015 +0100
@@ -28,6 +28,7 @@
 import static com.oracle.graal.asm.sparc.SPARCAssembler.BranchPredict.*;
 import static com.oracle.graal.asm.sparc.SPARCAssembler.CC.*;
 import static com.oracle.graal.asm.sparc.SPARCAssembler.ConditionFlag.*;
+import static com.oracle.graal.asm.sparc.SPARCAssembler.Opfs.*;
 import static com.oracle.graal.lir.LIRInstruction.OperandFlag.*;
 import static com.oracle.graal.sparc.SPARC.*;
 import static com.oracle.graal.sparc.SPARC.CPUFeature.*;
@@ -39,11 +40,9 @@
 import com.oracle.graal.asm.sparc.SPARCAssembler.Add;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Addcc;
 import com.oracle.graal.asm.sparc.SPARCAssembler.And;
-import com.oracle.graal.asm.sparc.SPARCAssembler.CC;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Faddd;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Fadds;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Fandd;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Fcmp;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Fdivd;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Fdivs;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Fdtoi;
@@ -64,7 +63,6 @@
 import com.oracle.graal.asm.sparc.SPARCAssembler.Fxtod;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Fxtos;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Mulx;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Opfs;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Or;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Sdivx;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Sll;
@@ -756,14 +754,14 @@
                 new Fstod(asFloatReg(src), asDoubleReg(dst)).emit(masm);
                 break;
             case F2L:
-                new Fcmp(CC.Fcc0, Opfs.Fcmps, asFloatReg(src), asFloatReg(src)).emit(masm);
+                masm.fcmp(Fcc0, Fcmps, asFloatReg(src), asFloatReg(src));
                 masm.fbpcc(F_Ordered, ANNUL, notOrdered, Fcc0, PREDICT_TAKEN);
                 new Fstox(asFloatReg(src), asDoubleReg(dst)).emit(masm);
                 new Fsubd(asDoubleReg(dst), asDoubleReg(dst), asDoubleReg(dst)).emit(masm);
                 masm.bind(notOrdered);
                 break;
             case F2I:
-                new Fcmp(CC.Fcc0, Opfs.Fcmps, asFloatReg(src), asFloatReg(src)).emit(masm);
+                masm.fcmp(Fcc0, Fcmps, asFloatReg(src), asFloatReg(src));
                 masm.fbpcc(F_Ordered, ANNUL, notOrdered, Fcc0, PREDICT_TAKEN);
                 new Fstoi(asFloatReg(src), asFloatReg(dst)).emit(masm);
                 new Fitos(asFloatReg(dst), asFloatReg(dst)).emit(masm);
@@ -771,7 +769,7 @@
                 masm.bind(notOrdered);
                 break;
             case D2L:
-                new Fcmp(CC.Fcc0, Opfs.Fcmpd, asDoubleReg(src), asDoubleReg(src)).emit(masm);
+                masm.fcmp(Fcc0, Fcmpd, asDoubleReg(src), asDoubleReg(src));
                 masm.fbpcc(F_Ordered, ANNUL, notOrdered, Fcc0, PREDICT_TAKEN);
                 new Fdtox(asDoubleReg(src), asDoubleReg(dst)).emit(masm);
                 new Fxtod(asDoubleReg(dst), asDoubleReg(dst)).emit(masm);
@@ -779,7 +777,7 @@
                 masm.bind(notOrdered);
                 break;
             case D2I:
-                new Fcmp(CC.Fcc0, Opfs.Fcmpd, asDoubleReg(src), asDoubleReg(src)).emit(masm);
+                masm.fcmp(Fcc0, Fcmpd, asDoubleReg(src), asDoubleReg(src));
                 masm.fbpcc(F_Ordered, ANNUL, notOrdered, Fcc0, PREDICT_TAKEN);
                 new Fdtoi(asDoubleReg(src), asFloatReg(dst)).emit(masm);
                 new Fsubs(asFloatReg(dst), asFloatReg(dst), asFloatReg(dst)).emit(masm);
diff -r 2819dcd694b9 -r b1b887938753 graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCCompare.java
--- a/graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCCompare.java	Fri Feb 27 11:52:03 2015 +0100
+++ b/graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCCompare.java	Fri Feb 27 13:23:52 2015 +0100
@@ -24,6 +24,8 @@
 
 import static com.oracle.graal.api.code.ValueUtil.*;
 import static com.oracle.graal.asm.sparc.SPARCAssembler.*;
+import static com.oracle.graal.asm.sparc.SPARCAssembler.CC.*;
+import static com.oracle.graal.asm.sparc.SPARCAssembler.Opfs.*;
 import static com.oracle.graal.lir.LIRInstruction.OperandFlag.*;
 
 import com.oracle.graal.api.meta.*;
@@ -88,10 +90,10 @@
                     new Cmp(asObjectReg(x), asObjectReg(y)).emit(masm);
                     break;
                 case FCMP:
-                    new Fcmp(CC.Fcc0, Opfs.Fcmps, asFloatReg(x), asFloatReg(y)).emit(masm);
+                    masm.fcmp(Fcc0, Fcmps, asFloatReg(x), asFloatReg(y));
                     break;
                 case DCMP:
-                    new Fcmp(CC.Fcc0, Opfs.Fcmpd, asDoubleReg(x), asDoubleReg(y)).emit(masm);
+                    masm.fcmp(Fcc0, Fcmpd, asDoubleReg(x), asDoubleReg(y));
                     break;
                 default:
                     throw GraalInternalError.shouldNotReachHere();
@@ -115,10 +117,10 @@
                         throw GraalInternalError.shouldNotReachHere("Only null object constants are allowed in comparisons");
                     }
                 case FCMP:
-                    new Fcmp(CC.Fcc0, Opfs.Fcmps, asFloatReg(x), asFloatReg(y)).emit(masm);
+                    masm.fcmp(Fcc0, Fcmps, asFloatReg(x), asFloatReg(y));
                     break;
                 case DCMP:
-                    new Fcmp(CC.Fcc0, Opfs.Fcmpd, asDoubleReg(x), asDoubleReg(y)).emit(masm);
+                    masm.fcmp(Fcc0, Fcmpd, asDoubleReg(x), asDoubleReg(y));
                     break;
                 default:
                     throw GraalInternalError.shouldNotReachHere();