# HG changeset patch
# User Stefan Anzinger <stefan.anzinger@oracle.com>
# Date 1425291737 -3600
# Node ID f1b4f2613702b2aae57aef60089cd641bd95fbc1
# Parent  32a5dd091f5fea6461d2c308db4a5be4a25228cc
[SPARC] Change arithmetic ops of SPARC to functions in assembler

diff -r 32a5dd091f5f -r f1b4f2613702 graal/com.oracle.graal.asm.sparc/src/com/oracle/graal/asm/sparc/SPARCAssembler.java
--- a/graal/com.oracle.graal.asm.sparc/src/com/oracle/graal/asm/sparc/SPARCAssembler.java	Fri Feb 27 14:43:40 2015 +0100
+++ b/graal/com.oracle.graal.asm.sparc/src/com/oracle/graal/asm/sparc/SPARCAssembler.java	Mon Mar 02 11:22:17 2015 +0100
@@ -22,6 +22,8 @@
  */
 package com.oracle.graal.asm.sparc;
 
+import static com.oracle.graal.asm.sparc.SPARCAssembler.CC.*;
+import static com.oracle.graal.asm.sparc.SPARCAssembler.ConditionFlag.*;
 import static com.oracle.graal.asm.sparc.SPARCAssembler.Op3s.*;
 import static com.oracle.graal.asm.sparc.SPARCAssembler.Opfs.*;
 import static com.oracle.graal.hotspot.HotSpotGraalRuntime.*;
@@ -52,10 +54,6 @@
         super(target);
     }
 
-    public interface AssemblerEmittable {
-        void emit(SPARCAssembler masm);
-    }
-
     public static final int CCR_ICC_SHIFT = 0;
     public static final int CCR_XCC_SHIFT = 4;
     public static final int CCR_C_SHIFT = 0;
@@ -92,159 +90,6 @@
 
     // @formatter:off
     /**
-     * Instruction format for Arithmetic, Logical, Moves, Tcc, Prefetch, and Misc.
-     * <pre>
-     * | 10  |   rd   |   op3   |   rs1   | i|     imm_asi   |   rs2   |
-     * | 10  |   rd   |   op3   |   rs1   | i|          simm13         |
-     * | 10  |   rd   |   op3   |   rs1   | i| x|            |   rs2   |
-     * | 10  |   rd   |   op3   |   rs1   | i| x|            | shcnt32 |
-     * | 10  |   rd   |   op3   |   rs1   | i| x|            | shcnt64 |
-     * |31 30|29    25|24     19|18     14|13|12|11         5|4       0|
-     * </pre>
-     */
-    // @formatter:on
-    public static class Fmt10 implements AssemblerEmittable {
-
-        private static final int RD_SHIFT = 25;
-        private static final int OP3_SHIFT = 19;
-        private static final int RS1_SHIFT = 14;
-        private static final int I_SHIFT = 13;
-        private static final int X_SHIFT = 12;
-        private static final int IMM_ASI_SHIFT = 5;
-        private static final int RS2_SHIFT = 0;
-        private static final int SIMM13_SHIFT = 0;
-
-        // @formatter:off
-        private static final int RD_MASK      = 0b00111110000000000000000000000000;
-        private static final int OP3_MASK     = 0b00000001111110000000000000000000;
-        private static final int RS1_MASK     = 0b00000000000001111100000000000000;
-        private static final int I_MASK       = 0b00000000000000000010000000000000;
-        private static final int X_MASK       = 0b00000000000000000001000000000000;
-        private static final int IMM_ASI_MASK = 0b00000000000000000001111111100000;
-        private static final int RS2_MASK     = 0b00000000000000000000000000011111;
-        private static final int SIMM13_MASK  = 0b00000000000000000001111111111111;
-        // @formatter:on
-
-        private int rd;
-        private int op3;
-        private int rs1;
-        private int i;
-        private int x;
-        private int immAsi;
-        private int rs2;
-        private int simm13;
-
-        private Fmt10(int rd, int op3, int rs1, int i, int x, int immAsi, int rs2, int simm13) {
-            this.rd = rd;
-            this.op3 = op3;
-            this.rs1 = rs1;
-            this.i = i;
-            this.x = x;
-            this.immAsi = immAsi;
-            this.rs2 = rs2;
-            this.simm13 = simm13;
-            verify();
-        }
-
-        public Fmt10(Op3s op3, Register rs1, Register rs2, Register rd) {
-            this(rd.encoding(), op3.getValue(), rs1.encoding(), 0, getXBit(op3), 0, rs2.encoding(), 0);
-        }
-
-        public Fmt10(Op3s op3, Register rs1, int simm13, Register rd) {
-            this(rd.encoding(), op3.getValue(), rs1.encoding(), 1, getXBit(op3), 0, 0, simm13);
-        }
-
-        /**
-         * Used for trap on Integer Condition Codes (Tcc).
-         *
-         * @param op3
-         * @param rs1
-         * @param simm13
-         * @param cf
-         */
-        public Fmt10(Op3s op3, Register rs1, int simm13, ConditionFlag cf) {
-            this(cf.getValue(), op3.getValue(), rs1.encoding(), 1, getXBit(op3), 0, 0, simm13);
-        }
-
-        public Fmt10(Op3s op3) {
-            this(0, op3.getValue(), 0, 0, getXBit(op3), 0, 0, 0);
-        }
-
-        public Fmt10(Op3s op3, Register rs1, Register rd) {
-            this(rd.encoding(), op3.getValue(), rs1.encoding(), 0, getXBit(op3), 0, 0, 0);
-        }
-
-        /**
-         * Helper method to determine if the instruction needs the X bit set.
-         */
-        private static int getXBit(Op3s op3) {
-            switch (op3) {
-                case Sllx:
-                case Srax:
-                case Srlx:
-                    return 1;
-                default:
-                    return 0;
-            }
-        }
-
-        private int getInstructionBits() {
-            if (i == 0) {
-                return Ops.ArithOp.getValue() << OP_SHIFT | rd << RD_SHIFT | op3 << OP3_SHIFT | rs1 << RS1_SHIFT | i << I_SHIFT | x << X_SHIFT | immAsi << IMM_ASI_SHIFT | rs2 << RS2_SHIFT;
-            } else {
-                return Ops.ArithOp.getValue() << OP_SHIFT | rd << RD_SHIFT | op3 << OP3_SHIFT | rs1 << RS1_SHIFT | i << I_SHIFT | x << X_SHIFT | ((simm13 << SIMM13_SHIFT) & SIMM13_MASK);
-            }
-        }
-
-        public static Fmt10 read(SPARCAssembler masm, int pos) {
-            final int inst = masm.getInt(pos);
-
-            // Make sure it's the right instruction:
-            final int op = (inst & OP_MASK) >> OP_SHIFT;
-            assert op == Ops.ArithOp.getValue();
-
-            // Get the instruction fields:
-            final int rd = (inst & RD_MASK) >> RD_SHIFT;
-            final int op3 = (inst & OP3_MASK) >> OP3_SHIFT;
-            final int rs1 = (inst & RS1_MASK) >> RS1_SHIFT;
-            final int i = (inst & I_MASK) >> I_SHIFT;
-            final int x = (inst & X_MASK) >> X_SHIFT;
-            final int immAsi = (inst & IMM_ASI_MASK) >> IMM_ASI_SHIFT;
-            final int rs2 = (inst & RS2_MASK) >> RS2_SHIFT;
-            final int simm13 = (inst & SIMM13_MASK) >> SIMM13_SHIFT;
-
-            return new Fmt10(rd, op3, rs1, i, x, immAsi, rs2, simm13);
-        }
-
-        public void write(SPARCAssembler masm, int pos) {
-            verify();
-            masm.emitInt(getInstructionBits(), pos);
-        }
-
-        public void emit(SPARCAssembler masm) {
-            verify();
-            masm.emitInt(getInstructionBits());
-        }
-
-        public void verify() {
-            assert ((rd << RD_SHIFT) & RD_MASK) == (rd << RD_SHIFT) : this;
-            assert ((op3 << OP3_SHIFT) & OP3_MASK) == (op3 << OP3_SHIFT) : this;
-            assert ((rs1 << RS1_SHIFT) & RS1_MASK) == (rs1 << RS1_SHIFT) : this;
-            assert ((i << I_SHIFT) & I_MASK) == (i << I_SHIFT) : this;
-            assert ((x << X_SHIFT) & X_MASK) == (x << X_SHIFT) : this;
-            assert ((immAsi << IMM_ASI_SHIFT) & IMM_ASI_MASK) == (immAsi << IMM_ASI_SHIFT) : this;
-            assert ((rs2 << RS2_SHIFT) & RS2_MASK) == (rs2 << RS2_SHIFT) : this;
-            assert isSimm13(simm13) : this;
-        }
-
-        @Override
-        public String toString() {
-            return String.format("%s: [rd: 0x%x, op3: 0x%x, rs1: 0x%x, i: 0x%x, x: 0x%x, immAsi: 0x%x, rs2: 0x%x, simm13: 0x%x", getClass().getName(), rd, op3, rs1, i, x, immAsi, rs2, simm13);
-        }
-    }
-
-    // @formatter:off
-    /**
      * Instruction format for Loads, Stores and Misc.
      * <pre>
      * | 11  |   rd   |   op3   |   rs1   | i|   imm_asi   |   rs2   |
@@ -519,7 +364,7 @@
      * </pre>
      */
     // @formatter:on
-    public static class Fmt10d implements AssemblerEmittable {
+    public static class Fmt10d {
 
         private static final int RD_SHIFT = 25;
         private static final int OP3_SHIFT = 19;
@@ -1594,92 +1439,68 @@
         return 0;
     }
 
-    public static class Add extends Fmt10 {
+    public void add(Register rs1, Register rs2, Register rd) {
+        op3(Add, rs1, rs2, rd);
+    }
 
-        public Add(Register src1, int simm13, Register dst) {
-            super(Add, src1, simm13, dst);
-        }
+    public void add(Register rs1, int simm13, Register rd) {
+        op3(Add, rs1, simm13, rd);
+    }
 
-        public Add(Register src1, Register src2, Register dst) {
-            super(Add, src1, src2, dst);
-        }
+    public void addc(Register rs1, Register rs2, Register rd) {
+        op3(Addc, rs1, rs2, rd);
     }
 
-    public static class Addc extends Fmt10 {
-
-        public Addc(Register src1, int simm13, Register dst) {
-            super(Addc, src1, simm13, dst);
-        }
-
-        public Addc(Register src1, Register src2, Register dst) {
-            super(Addc, src1, src2, dst);
-        }
+    public void addc(Register rs1, int simm13, Register rd) {
+        op3(Addc, rs1, simm13, rd);
     }
 
-    public static class Addcc extends Fmt10 {
+    public void addcc(Register rs1, Register rs2, Register rd) {
+        op3(Addcc, rs1, rs2, rd);
+    }
 
-        public Addcc(Register src1, int simm13, Register dst) {
-            super(Addcc, src1, simm13, dst);
-        }
+    public void addcc(Register rs1, int simm13, Register rd) {
+        op3(Addcc, rs1, simm13, rd);
+    }
 
-        public Addcc(Register src1, Register src2, Register dst) {
-            super(Addcc, src1, src2, dst);
-        }
+    public void addccc(Register rs1, Register rs2, Register rd) {
+        op3(Addccc, rs1, rs2, rd);
     }
 
-    public static class Addccc extends Fmt10 {
-
-        public Addccc(Register src1, int simm13, Register dst) {
-            super(Addccc, src1, simm13, dst);
-        }
-
-        public Addccc(Register src1, Register src2, Register dst) {
-            super(Addccc, src1, src2, dst);
-        }
+    public void addccc(Register rs1, int simm13, Register rd) {
+        op3(Addccc, rs1, simm13, rd);
     }
 
-    public static class And extends Fmt10 {
+    public void and(Register rs1, Register rs2, Register rd) {
+        op3(And, rs1, rs2, rd);
+    }
 
-        public And(Register src1, int simm13, Register dst) {
-            super(And, src1, simm13, dst);
-        }
+    public void and(Register rs1, int simm13, Register rd) {
+        op3(And, rs1, simm13, rd);
+    }
 
-        public And(Register src1, Register src2, Register dst) {
-            super(And, src1, src2, dst);
-        }
+    public void andcc(Register rs1, Register rs2, Register rd) {
+        op3(Andcc, rs1, rs2, rd);
     }
 
-    public static class Andcc extends Fmt10 {
+    public void andcc(Register rs1, int simm13, Register rd) {
+        op3(Andcc, rs1, simm13, rd);
+    }
 
-        public Andcc(Register src1, int simm13, Register dst) {
-            super(Andcc, src1, simm13, dst);
-        }
-
-        public Andcc(Register src1, Register src2, Register dst) {
-            super(Andcc, src1, src2, dst);
-        }
+    public void andn(Register rs1, Register rs2, Register rd) {
+        op3(Andn, rs1, rs2, rd);
     }
 
-    public static class Andn extends Fmt10 {
-
-        public Andn(Register src1, int simm13, Register dst) {
-            super(Andn, src1, simm13, dst);
-        }
-
-        public Andn(Register src1, Register src2, Register dst) {
-            super(Andn, src1, src2, dst);
-        }
+    public void andn(Register rs1, int simm13, Register rd) {
+        op3(Andn, rs1, simm13, rd);
     }
 
-    public static class Andncc extends Fmt10 {
+    public void andncc(Register rs1, Register rs2, Register rd) {
+        op3(Andncc, rs1, rs2, rd);
+    }
 
-        public Andncc(Register src1, int simm13, Register dst) {
-            super(Andncc, src1, simm13, dst);
-        }
-
-        public Andncc(Register src1, Register src2, Register dst) {
-            super(Andncc, src1, src2, dst);
-        }
+    public void andncc(Register rs1, int simm13, Register rd) {
+        op3(Andncc, rs1, simm13, rd);
     }
 
     public void movwtos(Register rs2, Register rd) {
@@ -1824,6 +1645,33 @@
         fmt10(rd.encoding, op3.value, rs1 == null ? 0 : rs1.encoding, b);
     }
 
+    protected void op3(Op3s op3, Register rs1, Register rs2, Register rd) {
+        int b = rs2 == null ? 0 : rs2.encoding;
+        int xBit = getXBit(op3);
+        fmt10(rd.encoding, op3.value, rs1 == null ? 0 : rs1.encoding, b | xBit);
+    }
+
+    protected void op3(Op3s op3, Register rs1, int simm13, Register rd) {
+        assert isSimm13(simm13);
+        int i = 1 << 13;
+        int simm13WithX = simm13 | getXBit(op3);
+        fmt10(rd.encoding, op3.value, rs1.encoding, i | simm13WithX & ((1 << 13) - 1));
+    }
+
+    /**
+     * Helper method to determine if the instruction needs the X bit set.
+     */
+    private static int getXBit(Op3s op3) {
+        switch (op3) {
+            case Sllx:
+            case Srax:
+            case Srlx:
+                return 1 << 12;
+            default:
+                return 0;
+        }
+    }
+
     public void fstoi(Register rs2, Register rd) {
         op3(Fpop1, Fstoi, null, rs2, rd);
     }
@@ -1868,14 +1716,8 @@
         op3(Impdep1, Fzerod, null, null, rd);
     }
 
-    /**
-     * Flush register windows.
-     */
-    public static class Flushw extends Fmt10 {
-
-        public Flushw() {
-            super(Flushw);
-        }
+    public void flushw() {
+        op3(Flushw, g0, g0, g0);
     }
 
     public void fsqrtd(Register rs2, Register rd) {
@@ -1936,15 +1778,12 @@
         fmt00(0, Op2s.Illtrap.value, const22);
     }
 
-    public static class Jmpl extends Fmt10 {
+    public void jmpl(Register rs1, Register rs2, Register rd) {
+        op3(Jmpl, rs1, rs2, rd);
+    }
 
-        public Jmpl(Register src, int simm13, Register dst) {
-            super(Jmpl, src, simm13, dst);
-        }
-
-        public Jmpl(Register src1, Register src2, Register dst) {
-            super(Jmpl, src1, src2, dst);
-        }
+    public void jmpl(Register rs1, int simm13, Register rd) {
+        op3(Jmpl, rs1, simm13, rd);
     }
 
     public static class Lddf extends Fmt11 {
@@ -2036,11 +1875,8 @@
         }
     }
 
-    public static class Membar extends Fmt10 {
-
-        public Membar(int barriers) {
-            super(Membar, r15, barriers, r0);
-        }
+    public void membar(int barriers) {
+        op3(Membar, r15, barriers, g0);
     }
 
     public static class Fmovscc extends Fmt10d {
@@ -2068,95 +1904,28 @@
         }
     }
 
-    @Deprecated
-    public static class Mulscc extends Fmt10 {
-
-        @Deprecated
-        public Mulscc(Register src1, int simm13, Register dst) {
-            super(Mulscc, src1, simm13, dst);
-        }
-
-        @Deprecated
-        public Mulscc(Register src1, Register src2, Register dst) {
-            super(Mulscc, src1, src2, dst);
-        }
+    public void mulx(Register rs1, Register rs2, Register rd) {
+        op3(Mulx, rs1, rs2, rd);
     }
 
-    public static class Mulx extends Fmt10 {
-
-        public Mulx(Register src1, int simm13, Register dst) {
-            super(Mulx, src1, simm13, dst);
-        }
-
-        public Mulx(Register src1, Register src2, Register dst) {
-            super(Mulx, src1, src2, dst);
-        }
-    }
-
-    public static class SMulcc extends Fmt10 {
-
-        public SMulcc(Register src1, int simm13, Register dst) {
-            super(Smulcc, src1, simm13, dst);
-        }
-
-        public SMulcc(Register src1, Register src2, Register dst) {
-            super(Smulcc, src1, src2, dst);
-        }
+    public void mulx(Register rs1, int simm13, Register rd) {
+        op3(Mulx, rs1, simm13, rd);
     }
 
-    public static class Or extends Fmt10 {
-
-        public Or(Register src1, int simm13, Register dst) {
-            super(Or, src1, simm13, dst);
-        }
-
-        public Or(Register src1, Register src2, Register dst) {
-            super(Or, src1, src2, dst);
-        }
-    }
-
-    public static class Orcc extends Fmt10 {
-
-        public Orcc(Register src1, int simm13, Register dst) {
-            super(Orcc, src1, simm13, dst);
-        }
-
-        public Orcc(Register src1, Register src2, Register dst) {
-            super(Orcc, src1, src2, dst);
-        }
+    public void or(Register rs1, Register rs2, Register rd) {
+        op3(Or, rs1, rs2, rd);
     }
 
-    public static class Orn extends Fmt10 {
-
-        public Orn(Register src1, int simm13, Register dst) {
-            super(Orn, src1, simm13, dst);
-        }
-
-        public Orn(Register src1, Register src2, Register dst) {
-            super(Orn, src1, src2, dst);
-        }
+    public void or(Register rs1, int simm13, Register rd) {
+        op3(Or, rs1, simm13, rd);
     }
 
-    public static class Orncc extends Fmt10 {
-
-        public Orncc(Register src1, int simm13, Register dst) {
-            super(Orncc, src1, simm13, dst);
-        }
-
-        public Orncc(Register src1, Register src2, Register dst) {
-            super(Orncc, src1, src2, dst);
-        }
+    public void popc(Register rs2, Register rd) {
+        op3(Popc, g0, rs2, rd);
     }
 
-    public static class Popc extends Fmt10 {
-
-        public Popc(int simm13, Register dst) {
-            super(Popc, r0, simm13, dst);
-        }
-
-        public Popc(Register src2, Register dst) {
-            super(Popc, r0, src2, dst);
-        }
+    public void popc(int simm13, Register rd) {
+        op3(Popc, g0, simm13, rd);
     }
 
     public static class Prefetch extends Fmt11 {
@@ -2191,208 +1960,86 @@
 
     // A.44 Read State Register
 
-    @Deprecated
-    public static class Rdy extends Fmt10 {
-
-        public Rdy(Register dst) {
-            super(Rdreg, r0, dst);
-        }
-    }
-
-    public static class Rdccr extends Fmt10 {
-
-        public Rdccr(Register dst) {
-            super(Rdreg, r2, dst);
-        }
-    }
-
-    public static class Rdasi extends Fmt10 {
-
-        public Rdasi(Register dst) {
-            super(Rdreg, r3, dst);
-        }
+    public void rdpc(Register rd) {
+        op3(Rdreg, r5, g0, rd);
     }
 
-    public static class Rdtick extends Fmt10 {
-
-        public Rdtick(Register dst) {
-            super(Rdreg, r4, dst);
-        }
-    }
-
-    public static class Rdpc extends Fmt10 {
-
-        public Rdpc(Register dst) {
-            super(Rdreg, r5, dst);
-        }
-    }
-
-    public static class Rdfprs extends Fmt10 {
-
-        public Rdfprs(Register dst) {
-            super(Rdreg, r6, dst);
-        }
-    }
-
-    public static class Restore extends Fmt10 {
-
-        public Restore(Register src1, Register src2, Register dst) {
-            super(Restore, src1, src2, dst);
-        }
-    }
-
-    public static class Restored extends Fmt10 {
-
-        public Restored() {
-            super(Saved, r0, r0, r1);
-        }
+    public void restore(Register rs1, Register rs2, Register rd) {
+        op3(Restore, rs1, rs2, rd);
     }
 
-    public static class Return extends Fmt10 {
-
-        public Return(Register src1, int simm13) {
-            super(Rett, src1, simm13, r0);
-        }
-
-        public Return(Register src1, Register src2) {
-            super(Rett, src1, src2, r0);
-        }
-
-        public static final int PC_RETURN_OFFSET = 8;
-    }
-
-    public static class Save extends Fmt10 {
+    public static final int PC_RETURN_OFFSET = 8;
 
-        public Save(Register src1, Register src2, Register dst) {
-            super(Save, src1, src2, dst);
-        }
-
-        public Save(Register src1, int simm13, Register dst) {
-            super(Save, src1, simm13, dst);
-        }
-    }
-
-    public static class Saved extends Fmt10 {
-
-        public Saved() {
-            super(Saved, r0, r0, r0);
-        }
+    public void save(Register rs1, Register rs2, Register rd) {
+        op3(Save, rs1, rs2, rd);
     }
 
-    @Deprecated
-    public static class Sdiv extends Fmt10 {
-
-        @Deprecated
-        public Sdiv(Register src1, int simm13, Register dst) {
-            super(Sdiv, src1, simm13, dst);
-        }
-
-        @Deprecated
-        public Sdiv(Register src1, Register src2, Register dst) {
-            super(Sdiv, src1, src2, dst);
-        }
+    public void save(Register rs1, int simm13, Register rd) {
+        op3(Save, rs1, simm13, rd);
     }
 
-    @Deprecated
-    public static class Sdivcc extends Fmt10 {
-
-        @Deprecated
-        public Sdivcc(Register src1, int simm13, Register dst) {
-            super(Sdivcc, src1, simm13, dst);
-        }
-
-        @Deprecated
-        public Sdivcc(Register src1, Register src2, Register dst) {
-            super(Sdivcc, src1, src2, dst);
-        }
+    public void sdivx(Register rs1, Register rs2, Register rd) {
+        op3(Sdivx, rs1, rs2, rd);
     }
 
-    public static class Sdivx extends Fmt10 {
-
-        public Sdivx(Register src1, int simm13, Register dst) {
-            super(Sdivx, src1, simm13, dst);
-        }
-
-        public Sdivx(Register src1, Register src2, Register dst) {
-            super(Sdivx, src1, src2, dst);
-        }
+    public void sdivx(Register rs1, int simm13, Register rd) {
+        op3(Sdivx, rs1, simm13, rd);
     }
 
     public void sethi(int imm22, Register dst) {
         fmt00(dst.encoding, Op2s.Sethi.value, imm22);
     }
 
-    public static class Sir extends Fmt10 {
+    public void sll(Register rs1, Register rs2, Register rd) {
+        op3(Sll, rs1, rs2, rd);
+    }
 
-        public Sir(int simm13) {
-            super(Sir, r0, simm13, r15);
-        }
+    public void sll(Register rs1, int shcnt32, Register rd) {
+        assert isImm(shcnt32, 5);
+        op3(Sll, rs1, shcnt32, rd);
     }
 
-    public static class Sll extends Fmt10 {
-
-        public Sll(Register src1, int shcnt32, Register dst) {
-            super(Sll, src1, shcnt32, dst);
-        }
-
-        public Sll(Register src1, Register src2, Register dst) {
-            super(Sll, src1, src2, dst);
-        }
+    public void sllx(Register rs1, Register rs2, Register rd) {
+        op3(Sllx, rs1, rs2, rd);
     }
 
-    public static class Sllx extends Fmt10 {
+    public void sllx(Register rs1, int shcnt64, Register rd) {
+        assert isImm(shcnt64, 6);
+        op3(Sllx, rs1, shcnt64, rd);
+    }
 
-        public Sllx(Register src1, int shcnt64, Register dst) {
-            super(Sllx, src1, shcnt64, dst);
-        }
-
-        public Sllx(Register src1, Register src2, Register dst) {
-            super(Sllx, src1, src2, dst);
-        }
+    public void sra(Register rs1, Register rs2, Register rd) {
+        op3(Sra, rs1, rs2, rd);
     }
 
-    public static class Sra extends Fmt10 {
+    public void sra(Register rs1, int simm13, Register rd) {
+        op3(Sra, rs1, simm13, rd);
+    }
 
-        public Sra(Register src1, int shcnt32, Register dst) {
-            super(Sra, src1, shcnt32, dst);
-        }
+    public void srax(Register rs1, Register rs2, Register rd) {
+        op3(Srax, rs1, rs2, rd);
+    }
 
-        public Sra(Register src1, Register src2, Register dst) {
-            super(Sra, src1, src2, dst);
-        }
+    public void srax(Register rs1, int shcnt64, Register rd) {
+        assert isImm(shcnt64, 6);
+        op3(Srax, rs1, shcnt64, rd);
     }
 
-    public static class Srax extends Fmt10 {
+    public void srl(Register rs1, Register rs2, Register rd) {
+        op3(Srl, rs1, rs2, rd);
+    }
 
-        public Srax(Register src1, int shcnt64, Register dst) {
-            super(Srax, src1, shcnt64, dst);
-        }
-
-        public Srax(Register src1, Register src2, Register dst) {
-            super(Srax, src1, src2, dst);
-        }
+    public void srl(Register rs1, int simm13, Register rd) {
+        op3(Srl, rs1, simm13, rd);
     }
 
-    public static class Srl extends Fmt10 {
-
-        public Srl(Register src1, int shcnt32, Register dst) {
-            super(Srl, src1, shcnt32, dst);
-        }
-
-        public Srl(Register src1, Register src2, Register dst) {
-            super(Srl, src1, src2, dst);
-        }
+    public void srlx(Register rs1, Register rs2, Register rd) {
+        op3(Srlx, rs1, rs2, rd);
     }
 
-    public static class Srlx extends Fmt10 {
-
-        public Srlx(Register src1, int shcnt64, Register dst) {
-            super(Srlx, src1, shcnt64, dst);
-        }
-
-        public Srlx(Register src1, Register src2, Register dst) {
-            super(Srlx, src1, src2, dst);
-        }
+    public void srlx(Register rs1, int shcnt64, Register rd) {
+        assert isImm(shcnt64, 6);
+        op3(Srlx, rs1, shcnt64, rd);
     }
 
     public void fandd(Register rs1, Register rs2, Register rd) {
@@ -2441,185 +2088,94 @@
         }
     }
 
-    public static class Sub extends Fmt10 {
+    public void sub(Register rs1, Register rs2, Register rd) {
+        op3(Sub, rs1, rs2, rd);
+    }
 
-        public Sub(Register src1, int simm13, Register dst) {
-            super(Sub, src1, simm13, dst);
-        }
-
-        public Sub(Register src1, Register src2, Register dst) {
-            super(Sub, src1, src2, dst);
-        }
+    public void sub(Register rs1, int simm13, Register rd) {
+        op3(Sub, rs1, simm13, rd);
     }
 
-    public static class Subc extends Fmt10 {
-
-        public Subc(Register src1, int simm13, Register dst) {
-            super(Subc, src1, simm13, dst);
-        }
-
-        public Subc(Register src1, Register src2, Register dst) {
-            super(Subc, src1, src2, dst);
-        }
+    public void subc(Register rs1, Register rs2, Register rd) {
+        op3(Subc, rs1, rs2, rd);
     }
 
-    public static class Subcc extends Fmt10 {
-
-        public Subcc(Register src1, int simm13, Register dst) {
-            super(Subcc, src1, simm13, dst);
-        }
-
-        public Subcc(Register src1, Register src2, Register dst) {
-            super(Subcc, src1, src2, dst);
-        }
+    public void subc(Register rs1, int simm13, Register rd) {
+        op3(Subc, rs1, simm13, rd);
     }
 
-    public static class Subccc extends Fmt10 {
-
-        public Subccc(Register src1, int simm13, Register dst) {
-            super(Subccc, src1, simm13, dst);
-        }
-
-        public Subccc(Register src1, Register src2, Register dst) {
-            super(Subccc, src1, src2, dst);
-        }
+    public void subcc(Register rs1, Register rs2, Register rd) {
+        op3(Subcc, rs1, rs2, rd);
     }
 
-    public static class Ta extends Fmt10 {
-
-        public Ta(int trap) {
-            super(Trap, g0, trap, ConditionFlag.Always);
-        }
+    public void subcc(Register rs1, int simm13, Register rd) {
+        op3(Subcc, rs1, simm13, rd);
     }
 
-    public static class Tcc extends Fmt10 {
-
-        public Tcc(ConditionFlag flag, int trap) {
-            super(Trap, g0, trap, flag);
-        }
+    public void subccc(Register rs1, Register rs2, Register rd) {
+        op3(Subccc, rs1, rs2, rd);
     }
 
-    public static class Taddcc extends Fmt10 {
-
-        public Taddcc(Register src1, int simm13, Register dst) {
-            super(Taddcc, src1, simm13, dst);
-        }
-
-        public Taddcc(Register src1, Register src2, Register dst) {
-            super(Taddcc, src1, src2, dst);
-        }
+    public void subccc(Register rs1, int simm13, Register rd) {
+        op3(Subccc, rs1, simm13, rd);
     }
 
-    public static class Tsubcc extends Fmt10 {
-
-        public Tsubcc(Register src1, int simm13, Register dst) {
-            super(Tsubcc, src1, simm13, dst);
-        }
-
-        public Tsubcc(Register src1, Register src2, Register dst) {
-            super(Tsubcc, src1, src2, dst);
-        }
+    public void ta(int trap) {
+        tcc(Icc, Always, trap);
     }
 
-    public static class Udivx extends Fmt10 {
-
-        public Udivx(Register src1, int simm13, Register dst) {
-            super(Udivx, src1, simm13, dst);
-        }
-
-        public Udivx(Register src1, Register src2, Register dst) {
-            super(Udivx, src1, src2, dst);
-        }
+    public void tcc(CC cc, ConditionFlag flag, int trap) {
+        assert isImm(trap, 8);
+        int b = cc.value << 11;
+        b |= trap;
+        fmt10(flag.value, trap, 0, b);
     }
 
-    @Deprecated
-    public static class Wry extends Fmt10 {
+    public void udivx(Register rs1, Register rs2, Register rd) {
+        op3(Udivx, rs1, rs2, rd);
+    }
 
-        @Deprecated
-        public Wry(Register src1, int simm13) {
-            super(Wrreg, src1, simm13, r0);
-        }
-
-        @Deprecated
-        public Wry(Register src1, Register src2) {
-            super(Wrreg, src1, src2, r0);
-        }
+    public void udivx(Register rs1, int simm13, Register rd) {
+        op3(Udivx, rs1, simm13, rd);
     }
 
-    public static class Wrccr extends Fmt10 {
-
-        public Wrccr(Register src1, int simm13) {
-            super(Wrreg, src1, simm13, r2);
-        }
-
-        public Wrccr(Register src1, Register src2) {
-            super(Wrreg, src1, src2, r2);
-        }
+    public void wrccr(Register rs1, Register rs2) {
+        op3(Wrreg, rs1, rs2, r2);
     }
 
-    public static class Wrasi extends Fmt10 {
+    public void wrccr(Register rs1, int simm13) {
+        op3(Wrreg, rs1, simm13, r2);
+    }
 
-        public Wrasi(Register src1, int simm13) {
-            super(Wrreg, src1, simm13, r3);
-        }
+    public void xor(Register rs1, Register rs2, Register rd) {
+        op3(Xor, rs1, rs2, rd);
+    }
 
-        public Wrasi(Register src1, Register src2) {
-            super(Wrreg, src1, src2, r3);
-        }
+    public void xor(Register rs1, int simm13, Register rd) {
+        op3(Xor, rs1, simm13, rd);
     }
 
-    public static class Wrfprs extends Fmt10 {
-
-        public Wrfprs(Register src1, int simm13) {
-            super(Wrreg, src1, simm13, r6);
-        }
-
-        public Wrfprs(Register src1, Register src2) {
-            super(Wrreg, src1, src2, r6);
-        }
+    public void xorcc(Register rs1, Register rs2, Register rd) {
+        op3(Xorcc, rs1, rs2, rd);
     }
 
-    public static class Xor extends Fmt10 {
+    public void xorcc(Register rs1, int simm13, Register rd) {
+        op3(Xorcc, rs1, simm13, rd);
+    }
 
-        public Xor(Register src1, int simm13, Register dst) {
-            super(Xor, src1, simm13, dst);
-        }
-
-        public Xor(Register src1, Register src2, Register dst) {
-            super(Xor, src1, src2, dst);
-        }
+    public void xnor(Register rs1, Register rs2, Register rd) {
+        op3(Xnor, rs1, rs2, rd);
     }
 
-    public static class Xorcc extends Fmt10 {
-
-        public Xorcc(Register src1, int simm13, Register dst) {
-            super(Xorcc, src1, simm13, dst);
-        }
-
-        public Xorcc(Register src1, Register src2, Register dst) {
-            super(Xorcc, src1, src2, dst);
-        }
+    public void xnor(Register rs1, int simm13, Register rd) {
+        op3(Xnor, rs1, simm13, rd);
     }
 
-    public static class Xnor extends Fmt10 {
-
-        public Xnor(Register src1, int simm13, Register dst) {
-            super(Xnor, src1, simm13, dst);
-        }
-
-        public Xnor(Register src1, Register src2, Register dst) {
-            super(Xnor, src1, src2, dst);
-        }
+    public void xnorcc(Register rs1, Register rs2, Register rd) {
+        op3(Xnorcc, rs1, rs2, rd);
     }
 
-    public static class Xnorcc extends Fmt10 {
-
-        public Xnorcc(Register src1, int simm13, Register dst) {
-            super(Xnorcc, src1, simm13, dst);
-        }
-
-        public Xnorcc(Register src1, Register src2, Register dst) {
-            super(Xnorcc, src1, src2, dst);
-        }
+    public void xnorcc(Register rs1, int simm13, Register rd) {
+        op3(Xnorcc, rs1, simm13, rd);
     }
 }
diff -r 32a5dd091f5f -r f1b4f2613702 graal/com.oracle.graal.asm.sparc/src/com/oracle/graal/asm/sparc/SPARCMacroAssembler.java
--- a/graal/com.oracle.graal.asm.sparc/src/com/oracle/graal/asm/sparc/SPARCMacroAssembler.java	Fri Feb 27 14:43:40 2015 +0100
+++ b/graal/com.oracle.graal.asm.sparc/src/com/oracle/graal/asm/sparc/SPARCMacroAssembler.java	Mon Mar 02 11:22:17 2015 +0100
@@ -122,39 +122,6 @@
         nop();
     }
 
-    public static class Bclr extends Andn {
-
-        public Bclr(Register src, Register dst) {
-            super(dst, src, dst);
-        }
-
-        public Bclr(int simm13, Register dst) {
-            super(dst, simm13, dst);
-        }
-    }
-
-    public static class Bset extends Or {
-
-        public Bset(Register src, Register dst) {
-            super(dst, src, dst);
-        }
-
-        public Bset(int simm13, Register dst) {
-            super(dst, simm13, dst);
-        }
-    }
-
-    public static class Btst extends Andcc {
-
-        public Btst(Register src1, Register src2) {
-            super(src1, src2, g0);
-        }
-
-        public Btst(Register src1, int simm13) {
-            super(src1, simm13, g0);
-        }
-    }
-
     public static class Cas extends Casa {
 
         public Cas(Register src1, Register src2, Register dst) {
@@ -169,11 +136,8 @@
         }
     }
 
-    public static class Clr extends Or {
-
-        public Clr(Register dst) {
-            super(g0, g0, dst);
-        }
+    public void clr(Register dst) {
+        or(g0, g0, dst);
     }
 
     public static class Clrb extends Stb {
@@ -197,163 +161,60 @@
         }
     }
 
-    public static class Clruw extends Srl {
-
-        public Clruw(Register src1, Register dst) {
-            super(src1, g0, dst);
-            assert src1.encoding() != dst.encoding();
-        }
-
-        public Clruw(Register dst) {
-            super(dst, g0, dst);
-        }
+    public void cmp(Register rs1, Register rs2) {
+        subcc(rs1, rs2, g0);
     }
 
-    public static class Cmp extends Subcc {
-
-        public Cmp(Register a, Register b) {
-            super(a, b, g0);
-        }
-
-        public Cmp(Register a, int simm13) {
-            super(a, simm13, g0);
-        }
-    }
-
-    public static class Dec extends Sub {
-
-        public Dec(Register dst) {
-            super(dst, 1, dst);
-        }
-
-        public Dec(int simm13, Register dst) {
-            super(dst, simm13, dst);
-        }
+    public void cmp(Register rs1, int simm13) {
+        subcc(rs1, simm13, g0);
     }
 
-    public static class Deccc extends Subcc {
-
-        public Deccc(Register dst) {
-            super(dst, 1, dst);
-        }
-
-        public Deccc(int simm13, Register dst) {
-            super(dst, simm13, dst);
-        }
+    public void dec(Register rd) {
+        sub(rd, 1, rd);
     }
 
-    @SuppressWarnings("unused")
-    public static class Inc {
-
-        public Inc(Register dst) {
-            new Add(dst, 1, dst);
-        }
-
-        public Inc(int simm13, Register dst) {
-            new Add(dst, simm13, dst);
-        }
+    public void dec(int simm13, Register rd) {
+        sub(rd, simm13, rd);
     }
 
-    @SuppressWarnings("unused")
-    public static class Inccc {
+    public void jmp(SPARCAddress address) {
+        jmpl(address.getBase(), address.getDisplacement(), g0);
+    }
 
-        public Inccc(Register dst) {
-            new Addcc(dst, 1, dst);
-        }
-
-        public Inccc(int simm13, Register dst) {
-            new Addcc(dst, simm13, dst);
-        }
+    public void jmp(Register rd) {
+        jmpl(rd, 0, g0);
     }
 
-    public static class Jmp extends Jmpl {
-
-        public Jmp(SPARCAddress address) {
-            super(address.getBase(), address.getDisplacement(), g0);
-        }
-
-        public Jmp(Register reg) {
-            super(reg, 0, g0);
-        }
+    public void neg(Register rs1, Register rd) {
+        sub(g0, rs1, rd);
     }
 
-    public static class Neg extends Sub {
-
-        public Neg(Register src2, Register dst) {
-            super(g0, src2, dst);
-        }
-
-        public Neg(Register dst) {
-            super(g0, dst, dst);
-        }
+    public void neg(Register rd) {
+        sub(g0, rd, rd);
     }
 
-    public static class Mov extends Or {
-
-        public Mov(Register src1, Register dst) {
-            super(g0, src1, dst);
-            assert src1.encoding() != dst.encoding();
-        }
-
-        public Mov(int simm13, Register dst) {
-            super(g0, simm13, dst);
-        }
+    public void mov(Register rs, Register rd) {
+        or(g0, rs, rd);
     }
 
-    public static class Not extends Xnor {
-
-        public Not(Register src1, Register dst) {
-            super(src1, g0, dst);
-        }
-
-        public Not(Register dst) {
-            super(dst, g0, dst);
-        }
+    public void mov(int simm13, Register rd) {
+        or(g0, simm13, rd);
     }
 
-    public static class RestoreWindow extends Restore {
-
-        public RestoreWindow() {
-            super(g0, g0, g0);
-        }
-    }
-
-    public static class Ret extends Jmpl {
-
-        public Ret() {
-            super(i7, 8, g0);
-        }
+    public void not(Register rs1, Register rd) {
+        xnor(rs1, g0, rd);
     }
 
-    public static class SaveWindow extends Save {
-
-        public SaveWindow() {
-            super(g0, g0, g0);
-        }
+    public void not(Register rd) {
+        xnor(rd, g0, rd);
     }
 
-    public static class Setuw {
-
-        private int value;
-        private Register dst;
-
-        public Setuw(int value, Register dst) {
-            this.value = value;
-            this.dst = dst;
-        }
+    public void restoreWindow() {
+        restore(g0, g0, g0);
+    }
 
-        public void emit(SPARCMacroAssembler masm) {
-            if (value == 0) {
-                new Clr(dst).emit(masm);
-            } else if (isSimm13(value)) {
-                new Or(g0, value, dst).emit(masm);
-            } else if (value >= 0 && ((value & 0x3FFF) == 0)) {
-                masm.sethi(hi22(value), dst);
-            } else {
-                masm.sethi(hi22(value), dst);
-                new Or(dst, lo10(value), dst).emit(masm);
-            }
-        }
+    public void ret() {
+        jmpl(i7, 8, g0);
     }
 
     /**
@@ -394,12 +255,6 @@
             } else {
                 cb.accept(masm);
             }
-
-        }
-
-        private void emitInstruction(final AssemblerEmittable insn, SPARCMacroAssembler masm) {
-            Consumer<SPARCAssembler> cb = eMasm -> insn.emit(eMasm);
-            emitInstruction(cb, masm);
         }
 
         public void emit(SPARCMacroAssembler masm) {
@@ -415,38 +270,47 @@
             } else if (hi == -1) {
                 Consumer<SPARCAssembler> cb = eMasm -> eMasm.sethi(hi22(~lo), dst);
                 emitInstruction(cb, masm);
-                emitInstruction(new Xor(dst, ~lo10(~0), dst), masm);
+                cb = eMasm -> eMasm.xor(dst, ~lo10(~0), dst);
+                emitInstruction(cb, masm);
             } else {
-                int shiftcnt = 0;
+                final int shiftcnt;
+                final int shiftcnt2;
                 Consumer<SPARCAssembler> cb = eMasm -> eMasm.sethi(hi22(hi), dst);
                 emitInstruction(cb, masm);
                 if ((hi & 0x3ff) != 0) {                                  // Any bits?
                     // msb 32-bits are now in lsb 32
-                    emitInstruction(new Or(dst, hi & 0x3ff, dst), masm);
+                    cb = eMasm -> eMasm.or(dst, hi & 0x3ff, dst);
+                    emitInstruction(cb, masm);
                 }
                 if ((lo & 0xFFFFFC00) != 0) {                             // done?
                     if (((lo >> 20) & 0xfff) != 0) {                      // Any bits set?
                         // Make room for next 12 bits
-                        emitInstruction(new Sllx(dst, 12, dst), masm);
+                        cb = eMasm -> eMasm.sllx(dst, 12, dst);
+                        emitInstruction(cb, masm);
                         // Or in next 12
-                        emitInstruction(new Or(dst, (lo >> 20) & 0xfff, dst), masm);
+                        cb = eMasm -> eMasm.or(dst, (lo >> 20) & 0xfff, dst);
+                        emitInstruction(cb, masm);
                         shiftcnt = 0;                                     // We already shifted
                     } else {
                         shiftcnt = 12;
                     }
                     if (((lo >> 10) & 0x3ff) != 0) {
                         // Make room for last 10 bits
-                        emitInstruction(new Sllx(dst, shiftcnt + 10, dst), masm);
+                        cb = eMasm -> eMasm.sllx(dst, shiftcnt + 10, dst);
+                        emitInstruction(cb, masm);
                         // Or in next 10
-                        emitInstruction(new Or(dst, (lo >> 10) & 0x3ff, dst), masm);
-                        shiftcnt = 0;
+                        cb = eMasm -> eMasm.or(dst, (lo >> 10) & 0x3ff, dst);
+                        emitInstruction(cb, masm);
+                        shiftcnt2 = 0;
                     } else {
-                        shiftcnt = 10;
+                        shiftcnt2 = 10;
                     }
                     // Shift leaving disp field 0'd
-                    emitInstruction(new Sllx(dst, shiftcnt + 10, dst), masm);
+                    cb = eMasm -> eMasm.sllx(dst, shiftcnt2 + 10, dst);
+                    emitInstruction(cb, masm);
                 } else {
-                    emitInstruction(new Sllx(dst, 32, dst), masm);
+                    cb = eMasm -> eMasm.sllx(dst, 32, dst);
+                    emitInstruction(cb, masm);
                 }
             }
             // Pad out the instruction sequence so it can be patched later.
@@ -472,7 +336,7 @@
         private boolean delayed = false;
         private boolean delayedFirstEmitted = false;
         private Sethix sethix;
-        private AssemblerEmittable delayedAdd;
+        private Consumer<SPARCMacroAssembler> delayedAdd;
 
         public Setx(long value, Register dst, boolean forceRelocatable, boolean delayed) {
             assert !(forceRelocatable && delayed) : "Cannot use relocatable setx as delayable";
@@ -500,14 +364,14 @@
             sethix.emit(masm);
             int lo = (int) (value & ~0);
             if (lo10(lo) != 0 || forceRelocatable) {
-                Add add = new Add(dst, lo10(lo), dst);
+                Consumer<SPARCMacroAssembler> add = eMasm -> eMasm.add(dst, lo10(lo), dst);
                 if (delayed) {
                     sethix.emitDelayed(masm);
                     sethix = null;
                     delayedAdd = add;
                 } else {
                     sethix = null;
-                    add.emit(masm);
+                    add.accept(masm);
                 }
             }
         }
@@ -525,7 +389,7 @@
             assert delayedFirstEmitted : "First part has not been emitted so far.";
             assert delayedAdd == null && sethix != null || delayedAdd != null && sethix == null : "Either add or sethix must be set";
             if (delayedAdd != null) {
-                delayedAdd.emit(masm);
+                delayedAdd.accept(masm);
             } else {
                 sethix.emitDelayed(masm);
             }
@@ -533,14 +397,11 @@
         }
     }
 
-    public static class Signx extends Sra {
+    public void signx(Register rs, Register rd) {
+        sra(rs, g0, rd);
+    }
 
-        public Signx(Register src1, Register dst) {
-            super(src1, g0, dst);
-        }
-
-        public Signx(Register dst) {
-            super(dst, g0, dst);
-        }
+    public void signx(Register rd) {
+        sra(rd, g0, rd);
     }
 }
diff -r 32a5dd091f5f -r f1b4f2613702 graal/com.oracle.graal.hotspot.sparc/src/com/oracle/graal/hotspot/sparc/SPARCHotSpotBackend.java
--- a/graal/com.oracle.graal.hotspot.sparc/src/com/oracle/graal/hotspot/sparc/SPARCHotSpotBackend.java	Fri Feb 27 14:43:40 2015 +0100
+++ b/graal/com.oracle.graal.hotspot.sparc/src/com/oracle/graal/hotspot/sparc/SPARCHotSpotBackend.java	Mon Mar 02 11:22:17 2015 +0100
@@ -39,10 +39,7 @@
 import com.oracle.graal.asm.*;
 import com.oracle.graal.asm.sparc.*;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Ldx;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Save;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Stx;
-import com.oracle.graal.asm.sparc.SPARCMacroAssembler.Cmp;
-import com.oracle.graal.asm.sparc.SPARCMacroAssembler.RestoreWindow;
 import com.oracle.graal.asm.sparc.SPARCMacroAssembler.Setx;
 import com.oracle.graal.compiler.common.cfg.*;
 import com.oracle.graal.hotspot.*;
@@ -151,12 +148,12 @@
             }
 
             if (SPARCAssembler.isSimm13(stackpoinerChange)) {
-                new Save(sp, stackpoinerChange, sp).emit(masm);
+                masm.save(sp, stackpoinerChange, sp);
             } else {
                 try (SPARCScratchRegister sc = SPARCScratchRegister.get()) {
                     Register scratch = sc.getRegister();
                     new Setx(stackpoinerChange, scratch).emit(masm);
-                    new Save(sp, scratch, sp).emit(masm);
+                    masm.save(sp, scratch, sp);
                 }
             }
 
@@ -172,7 +169,7 @@
         @Override
         public void leave(CompilationResultBuilder crb) {
             SPARCMacroAssembler masm = (SPARCMacroAssembler) crb.asm;
-            new RestoreWindow().emit(masm);
+            masm.restoreWindow();
         }
     }
 
@@ -238,7 +235,7 @@
                     SPARCAddress src = new SPARCAddress(receiver, config.hubOffset);
 
                     new Ldx(src, scratch).emit(masm);
-                    new Cmp(scratch, inlineCacheKlass).emit(masm);
+                    masm.cmp(scratch, inlineCacheKlass);
                 }
                 masm.bpcc(NotEqual, NOT_ANNUL, unverifiedStub, Xcc, PREDICT_NOT_TAKEN);
                 masm.nop();  // delay slot
diff -r 32a5dd091f5f -r f1b4f2613702 graal/com.oracle.graal.hotspot.sparc/src/com/oracle/graal/hotspot/sparc/SPARCHotSpotCRuntimeCallPrologueOp.java
--- a/graal/com.oracle.graal.hotspot.sparc/src/com/oracle/graal/hotspot/sparc/SPARCHotSpotCRuntimeCallPrologueOp.java	Fri Feb 27 14:43:40 2015 +0100
+++ b/graal/com.oracle.graal.hotspot.sparc/src/com/oracle/graal/hotspot/sparc/SPARCHotSpotCRuntimeCallPrologueOp.java	Mon Mar 02 11:22:17 2015 +0100
@@ -28,7 +28,6 @@
 import com.oracle.graal.api.code.*;
 import com.oracle.graal.api.meta.*;
 import com.oracle.graal.asm.sparc.*;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Add;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Stx;
 import com.oracle.graal.lir.*;
 import com.oracle.graal.lir.asm.*;
@@ -52,7 +51,7 @@
     @Override
     public void emitCode(CompilationResultBuilder crb, SPARCMacroAssembler masm) {
         // Save last Java frame.
-        new Add(stackPointer, STACK_BIAS, g4).emit(masm);
+        masm.add(stackPointer, STACK_BIAS, g4);
         new Stx(g4, new SPARCAddress(thread, threadLastJavaSpOffset)).emit(masm);
 
         // Save the thread register when calling out to the runtime.
diff -r 32a5dd091f5f -r f1b4f2613702 graal/com.oracle.graal.hotspot.sparc/src/com/oracle/graal/hotspot/sparc/SPARCHotSpotEnterUnpackFramesStackFrameOp.java
--- a/graal/com.oracle.graal.hotspot.sparc/src/com/oracle/graal/hotspot/sparc/SPARCHotSpotEnterUnpackFramesStackFrameOp.java	Fri Feb 27 14:43:40 2015 +0100
+++ b/graal/com.oracle.graal.hotspot.sparc/src/com/oracle/graal/hotspot/sparc/SPARCHotSpotEnterUnpackFramesStackFrameOp.java	Mon Mar 02 11:22:17 2015 +0100
@@ -66,22 +66,22 @@
         Register scratchRegister = asRegister(scratch);
 
         // Save final sender SP to O5_savedSP.
-        new Mov(senderSpRegister, o5).emit(masm);
+        masm.mov(senderSpRegister, o5);
 
         // Load final frame PC.
-        new Mov(framePcRegister, o7).emit(masm);
+        masm.mov(framePcRegister, o7);
 
         // Allocate a full sized frame.
-        new Save(sp, -totalFrameSize, sp).emit(masm);
+        masm.save(sp, -totalFrameSize, sp);
 
-        new Mov(i0, o0).emit(masm);
-        new Mov(i1, o1).emit(masm);
-        new Mov(i2, o2).emit(masm);
-        new Mov(i3, o3).emit(masm);
-        new Mov(i4, o4).emit(masm);
+        masm.mov(i0, o0);
+        masm.mov(i1, o1);
+        masm.mov(i2, o2);
+        masm.mov(i3, o3);
+        masm.mov(i4, o4);
 
         // Set up last Java values.
-        new Add(sp, STACK_BIAS, scratchRegister).emit(masm);
+        masm.add(sp, STACK_BIAS, scratchRegister);
         new Stx(scratchRegister, new SPARCAddress(thread, threadLastJavaSpOffset)).emit(masm);
 
         // Clear last Java PC.
@@ -91,7 +91,7 @@
          * Safe thread register manually since we are not using LEAF_SP for {@link
          * DeoptimizationStub#UNPACK_FRAMES}.
          */
-        new Mov(thread, l7).emit(masm);
+        masm.mov(thread, l7);
     }
 
     @Override
diff -r 32a5dd091f5f -r f1b4f2613702 graal/com.oracle.graal.hotspot.sparc/src/com/oracle/graal/hotspot/sparc/SPARCHotSpotJumpToExceptionHandlerInCallerOp.java
--- a/graal/com.oracle.graal.hotspot.sparc/src/com/oracle/graal/hotspot/sparc/SPARCHotSpotJumpToExceptionHandlerInCallerOp.java	Fri Feb 27 14:43:40 2015 +0100
+++ b/graal/com.oracle.graal.hotspot.sparc/src/com/oracle/graal/hotspot/sparc/SPARCHotSpotJumpToExceptionHandlerInCallerOp.java	Mon Mar 02 11:22:17 2015 +0100
@@ -31,10 +31,8 @@
 import com.oracle.graal.asm.sparc.*;
 import com.oracle.graal.asm.sparc.SPARCAssembler.CC;
 import com.oracle.graal.asm.sparc.SPARCAssembler.ConditionFlag;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Jmpl;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Lduw;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Movcc;
-import com.oracle.graal.asm.sparc.SPARCMacroAssembler.Cmp;
 import com.oracle.graal.lir.*;
 import com.oracle.graal.lir.asm.*;
 import com.oracle.graal.sparc.*;
@@ -63,9 +61,9 @@
     @Override
     public void emitCode(CompilationResultBuilder crb, SPARCMacroAssembler masm) {
         // Move the values up one level to be the input for the next call.
-        new SPARCMacroAssembler.Mov(asRegister(handlerInCallerPc), i2).emit(masm);
-        new SPARCMacroAssembler.Mov(asRegister(exception), i0).emit(masm);
-        new SPARCMacroAssembler.Mov(asRegister(exceptionPc), i1).emit(masm);
+        masm.mov(asRegister(handlerInCallerPc), i2);
+        masm.mov(asRegister(exception), i0);
+        masm.mov(asRegister(exceptionPc), i1);
         leaveFrame(crb);
 
         // Restore SP from L7 if the exception PC is a method handle call site.
@@ -73,11 +71,11 @@
         try (SPARCScratchRegister scratch = SPARCScratchRegister.get()) {
             Register scratchReg = scratch.getRegister();
             new Lduw(dst, scratchReg).emit(masm);
-            new Cmp(scratchReg, scratchReg).emit(masm);
+            masm.cmp(scratchReg, scratchReg);
             new Movcc(ConditionFlag.NotZero, CC.Icc, l7, sp).emit(masm);
         }
 
-        new Jmpl(asRegister(handlerInCallerPc), 0, g0).emit(masm);
+        masm.jmpl(asRegister(handlerInCallerPc), 0, g0);
         masm.nop();
     }
 }
diff -r 32a5dd091f5f -r f1b4f2613702 graal/com.oracle.graal.hotspot.sparc/src/com/oracle/graal/hotspot/sparc/SPARCHotSpotLeaveCurrentStackFrameOp.java
--- a/graal/com.oracle.graal.hotspot.sparc/src/com/oracle/graal/hotspot/sparc/SPARCHotSpotLeaveCurrentStackFrameOp.java	Fri Feb 27 14:43:40 2015 +0100
+++ b/graal/com.oracle.graal.hotspot.sparc/src/com/oracle/graal/hotspot/sparc/SPARCHotSpotLeaveCurrentStackFrameOp.java	Mon Mar 02 11:22:17 2015 +0100
@@ -25,7 +25,6 @@
 import static com.oracle.graal.sparc.SPARC.*;
 
 import com.oracle.graal.asm.sparc.*;
-import com.oracle.graal.asm.sparc.SPARCMacroAssembler.*;
 import com.oracle.graal.lir.*;
 import com.oracle.graal.lir.asm.*;
 import com.oracle.graal.lir.sparc.*;
@@ -42,11 +41,11 @@
     @Override
     public void emitCode(CompilationResultBuilder crb, SPARCMacroAssembler masm) {
         // Save O registers over restore.
-        new Mov(o0, i0).emit(masm);
-        new Mov(o1, i1).emit(masm);
-        new Mov(o2, i2).emit(masm);
-        new Mov(o3, i3).emit(masm);
-        new Mov(o4, i4).emit(masm);
+        masm.mov(o0, i0);
+        masm.mov(o1, i1);
+        masm.mov(o2, i2);
+        masm.mov(o3, i3);
+        masm.mov(o4, i4);
 
         crb.frameContext.leave(crb);
     }
diff -r 32a5dd091f5f -r f1b4f2613702 graal/com.oracle.graal.hotspot.sparc/src/com/oracle/graal/hotspot/sparc/SPARCHotSpotLeaveDeoptimizedStackFrameOp.java
--- a/graal/com.oracle.graal.hotspot.sparc/src/com/oracle/graal/hotspot/sparc/SPARCHotSpotLeaveDeoptimizedStackFrameOp.java	Fri Feb 27 14:43:40 2015 +0100
+++ b/graal/com.oracle.graal.hotspot.sparc/src/com/oracle/graal/hotspot/sparc/SPARCHotSpotLeaveDeoptimizedStackFrameOp.java	Mon Mar 02 11:22:17 2015 +0100
@@ -22,7 +22,6 @@
  */
 package com.oracle.graal.hotspot.sparc;
 
-import static com.oracle.graal.asm.sparc.SPARCMacroAssembler.*;
 import static com.oracle.graal.sparc.SPARC.*;
 
 import com.oracle.graal.asm.sparc.*;
@@ -39,13 +38,13 @@
     @Override
     public void emitCode(CompilationResultBuilder crb, SPARCMacroAssembler masm) {
         // Save O registers over restore.
-        new Mov(o0, i0).emit(masm);
-        new Mov(o1, i1).emit(masm);
-        new Mov(o2, i2).emit(masm);
-        new Mov(o3, i3).emit(masm);
-        new Mov(o4, i4).emit(masm);
+        masm.mov(o0, i0);
+        masm.mov(o1, i1);
+        masm.mov(o2, i2);
+        masm.mov(o3, i3);
+        masm.mov(o4, i4);
 
-        new RestoreWindow().emit(masm);
+        masm.restoreWindow();
     }
 
     @Override
diff -r 32a5dd091f5f -r f1b4f2613702 graal/com.oracle.graal.hotspot.sparc/src/com/oracle/graal/hotspot/sparc/SPARCHotSpotLeaveUnpackFramesStackFrameOp.java
--- a/graal/com.oracle.graal.hotspot.sparc/src/com/oracle/graal/hotspot/sparc/SPARCHotSpotLeaveUnpackFramesStackFrameOp.java	Fri Feb 27 14:43:40 2015 +0100
+++ b/graal/com.oracle.graal.hotspot.sparc/src/com/oracle/graal/hotspot/sparc/SPARCHotSpotLeaveUnpackFramesStackFrameOp.java	Mon Mar 02 11:22:17 2015 +0100
@@ -22,15 +22,18 @@
  */
 package com.oracle.graal.hotspot.sparc;
 
-import static com.oracle.graal.asm.sparc.SPARCMacroAssembler.*;
 import static com.oracle.graal.sparc.SPARC.*;
 
 import com.oracle.graal.api.code.*;
 import com.oracle.graal.asm.sparc.*;
+import com.oracle.graal.asm.sparc.SPARCAssembler.Ldx;
+import com.oracle.graal.asm.sparc.SPARCAssembler.Stdf;
+import com.oracle.graal.asm.sparc.SPARCAssembler.Stw;
+import com.oracle.graal.asm.sparc.SPARCAssembler.Stx;
 import com.oracle.graal.hotspot.*;
 import com.oracle.graal.lir.*;
+import com.oracle.graal.lir.asm.*;
 import com.oracle.graal.lir.sparc.*;
-import com.oracle.graal.lir.asm.*;
 
 /**
  * Emits code that leaves a stack frame which is tailored to call the C++ method
@@ -57,7 +60,7 @@
          * Safe thread register manually since we are not using LEAF_SP for {@link
          * DeoptimizationStub#UNPACK_FRAMES}.
          */
-        new Mov(l7, thread).emit(masm);
+        masm.mov(l7, thread);
 
         SPARCAddress lastJavaPc = new SPARCAddress(thread, threadLastJavaPcOffset);
 
diff -r 32a5dd091f5f -r f1b4f2613702 graal/com.oracle.graal.hotspot.sparc/src/com/oracle/graal/hotspot/sparc/SPARCHotSpotPatchReturnAddressOp.java
--- a/graal/com.oracle.graal.hotspot.sparc/src/com/oracle/graal/hotspot/sparc/SPARCHotSpotPatchReturnAddressOp.java	Fri Feb 27 14:43:40 2015 +0100
+++ b/graal/com.oracle.graal.hotspot.sparc/src/com/oracle/graal/hotspot/sparc/SPARCHotSpotPatchReturnAddressOp.java	Mon Mar 02 11:22:17 2015 +0100
@@ -22,14 +22,13 @@
  */
 package com.oracle.graal.hotspot.sparc;
 
+import static com.oracle.graal.api.code.ValueUtil.*;
 import static com.oracle.graal.lir.LIRInstruction.OperandFlag.*;
 import static com.oracle.graal.sparc.SPARC.*;
-import static com.oracle.graal.api.code.ValueUtil.*;
 
 import com.oracle.graal.api.code.*;
 import com.oracle.graal.api.meta.*;
 import com.oracle.graal.asm.sparc.*;
-import com.oracle.graal.asm.sparc.SPARCAssembler.*;
 import com.oracle.graal.lir.*;
 import com.oracle.graal.lir.asm.*;
 import com.oracle.graal.lir.sparc.*;
@@ -49,6 +48,6 @@
     @Override
     public void emitCode(CompilationResultBuilder crb, SPARCMacroAssembler masm) {
         Register addrRegister = asLongReg(address);
-        new Sub(addrRegister, Return.PC_RETURN_OFFSET, i7).emit(masm);
+        masm.sub(addrRegister, SPARCAssembler.PC_RETURN_OFFSET, i7);
     }
 }
diff -r 32a5dd091f5f -r f1b4f2613702 graal/com.oracle.graal.hotspot.sparc/src/com/oracle/graal/hotspot/sparc/SPARCHotSpotPushInterpreterFrameOp.java
--- a/graal/com.oracle.graal.hotspot.sparc/src/com/oracle/graal/hotspot/sparc/SPARCHotSpotPushInterpreterFrameOp.java	Fri Feb 27 14:43:40 2015 +0100
+++ b/graal/com.oracle.graal.hotspot.sparc/src/com/oracle/graal/hotspot/sparc/SPARCHotSpotPushInterpreterFrameOp.java	Mon Mar 02 11:22:17 2015 +0100
@@ -22,17 +22,16 @@
  */
 package com.oracle.graal.hotspot.sparc;
 
-import static com.oracle.graal.asm.sparc.SPARCMacroAssembler.*;
-import static com.oracle.graal.sparc.SPARC.*;
 import static com.oracle.graal.api.code.ValueUtil.*;
 import static com.oracle.graal.lir.LIRInstruction.OperandFlag.*;
+import static com.oracle.graal.sparc.SPARC.*;
 
 import com.oracle.graal.api.code.*;
 import com.oracle.graal.api.meta.*;
 import com.oracle.graal.asm.sparc.*;
 import com.oracle.graal.lir.*;
+import com.oracle.graal.lir.asm.*;
 import com.oracle.graal.lir.sparc.*;
-import com.oracle.graal.lir.asm.*;
 
 /**
  * Pushes an interpreter frame to the stack.
@@ -59,21 +58,21 @@
         final Register senderSpRegister = asRegister(senderSp);
 
         // Save sender SP to O5_savedSP.
-        new Mov(senderSpRegister, o5).emit(masm);
+        masm.mov(senderSpRegister, o5);
 
-        new Neg(frameSizeRegister).emit(masm);
-        new Save(sp, frameSizeRegister, sp).emit(masm);
+        masm.neg(frameSizeRegister);
+        masm.save(sp, frameSizeRegister, sp);
 
-        new Mov(i0, o0).emit(masm);
-        new Mov(i1, o1).emit(masm);
-        new Mov(i2, o2).emit(masm);
-        new Mov(i3, o3).emit(masm);
-        new Mov(i4, o4).emit(masm);
+        masm.mov(i0, o0);
+        masm.mov(i1, o1);
+        masm.mov(i2, o2);
+        masm.mov(i3, o3);
+        masm.mov(i4, o4);
 
         // NOTE: Don't touch I5 as it contains valuable saved SP!
 
         // Move frame's new PC into i7
-        new Mov(framePcRegister, i7).emit(masm);
+        masm.mov(framePcRegister, i7);
     }
 
     @Override
diff -r 32a5dd091f5f -r f1b4f2613702 graal/com.oracle.graal.hotspot.sparc/src/com/oracle/graal/hotspot/sparc/SPARCHotSpotUnwindOp.java
--- a/graal/com.oracle.graal.hotspot.sparc/src/com/oracle/graal/hotspot/sparc/SPARCHotSpotUnwindOp.java	Fri Feb 27 14:43:40 2015 +0100
+++ b/graal/com.oracle.graal.hotspot.sparc/src/com/oracle/graal/hotspot/sparc/SPARCHotSpotUnwindOp.java	Mon Mar 02 11:22:17 2015 +0100
@@ -28,9 +28,7 @@
 import static com.oracle.graal.sparc.SPARC.*;
 
 import com.oracle.graal.api.code.*;
-import com.oracle.graal.asm.sparc.SPARCAssembler.*;
 import com.oracle.graal.asm.sparc.*;
-import com.oracle.graal.asm.sparc.SPARCMacroAssembler.Mov;
 import com.oracle.graal.hotspot.stubs.*;
 import com.oracle.graal.lir.*;
 import com.oracle.graal.lir.asm.*;
@@ -52,7 +50,7 @@
     public void emitCode(CompilationResultBuilder crb, SPARCMacroAssembler masm) {
         // This Frame is left but the called unwind (which is sibling) method needs the exception as
         // input in i0
-        new Mov(o0, i0).emit(masm);
+        masm.mov(o0, i0);
         leaveFrame(crb);
 
         ForeignCallLinkage linkage = crb.foreignCalls.lookupForeignCall(UNWIND_EXCEPTION_TO_CALLER);
@@ -62,7 +60,7 @@
 
         // Get return address (is in o7 after leave).
         Register returnAddress = asRegister(cc.getArgument(1));
-        new Add(o7, Return.PC_RETURN_OFFSET, returnAddress).emit(masm);
+        masm.add(o7, SPARCAssembler.PC_RETURN_OFFSET, returnAddress);
         Register scratch = g5;
         SPARCCall.indirectJmp(crb, masm, scratch, linkage);
     }
diff -r 32a5dd091f5f -r f1b4f2613702 graal/com.oracle.graal.hotspot/src/com/oracle/graal/hotspot/meta/HotSpotCodeCacheProvider.java
--- a/graal/com.oracle.graal.hotspot/src/com/oracle/graal/hotspot/meta/HotSpotCodeCacheProvider.java	Fri Feb 27 14:43:40 2015 +0100
+++ b/graal/com.oracle.graal.hotspot/src/com/oracle/graal/hotspot/meta/HotSpotCodeCacheProvider.java	Mon Mar 02 11:22:17 2015 +0100
@@ -169,14 +169,14 @@
         }
 
         public static String tryDisassemble(String hcfEmbeddedString) {
-            if (processMethod != null) {
-                try {
-                    return (String) processMethod.invoke(null, hcfEmbeddedString);
-                } catch (IllegalAccessException | IllegalArgumentException | InvocationTargetException e) {
-                    // If the tool is available, for now let's be noisy when it fails
-                    throw new GraalInternalError(e);
-                }
-            }
+// if (processMethod != null) {
+// try {
+// return (String) processMethod.invoke(null, hcfEmbeddedString);
+// } catch (IllegalAccessException | IllegalArgumentException | InvocationTargetException e) {
+// // If the tool is available, for now let's be noisy when it fails
+// throw new GraalInternalError(e);
+// }
+// }
             return hcfEmbeddedString;
         }
     }
diff -r 32a5dd091f5f -r f1b4f2613702 graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCArithmetic.java
--- a/graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCArithmetic.java	Fri Feb 27 14:43:40 2015 +0100
+++ b/graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCArithmetic.java	Mon Mar 02 11:22:17 2015 +0100
@@ -37,29 +37,7 @@
 import com.oracle.graal.api.meta.*;
 import com.oracle.graal.asm.*;
 import com.oracle.graal.asm.sparc.*;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Add;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Addcc;
-import com.oracle.graal.asm.sparc.SPARCAssembler.And;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Mulx;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Or;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Sdivx;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Sll;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Sllx;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Sra;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Srax;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Srl;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Srlx;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Sub;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Subcc;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Udivx;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Wrccr;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Xor;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Xorcc;
-import com.oracle.graal.asm.sparc.SPARCMacroAssembler.Cmp;
-import com.oracle.graal.asm.sparc.SPARCMacroAssembler.Neg;
-import com.oracle.graal.asm.sparc.SPARCMacroAssembler.Not;
 import com.oracle.graal.asm.sparc.SPARCMacroAssembler.Setx;
-import com.oracle.graal.asm.sparc.SPARCMacroAssembler.Signx;
 import com.oracle.graal.compiler.common.*;
 import com.oracle.graal.lir.*;
 import com.oracle.graal.lir.asm.*;
@@ -229,24 +207,24 @@
         @Override
         public void emitCode(CompilationResultBuilder crb, SPARCMacroAssembler masm) {
             Label noOverflow = new Label();
-            new Mulx(asLongReg(x), asLongReg(y), asLongReg(result)).emit(masm);
+            masm.mulx(asLongReg(x), asLongReg(y), asLongReg(result));
 
             // Calculate the upper 64 bit signed := (umulxhi product - (x{63}&y + y{63}&x))
             masm.umulxhi(asLongReg(x), asLongReg(y), asLongReg(scratch1));
-            new Srax(asLongReg(x), 63, asLongReg(scratch2)).emit(masm);
-            new And(asLongReg(scratch2), asLongReg(y), asLongReg(scratch2)).emit(masm);
-            new Sub(asLongReg(scratch1), asLongReg(scratch2), asLongReg(scratch1)).emit(masm);
+            masm.srax(asLongReg(x), 63, asLongReg(scratch2));
+            masm.and(asLongReg(scratch2), asLongReg(y), asLongReg(scratch2));
+            masm.sub(asLongReg(scratch1), asLongReg(scratch2), asLongReg(scratch1));
 
-            new Srax(asLongReg(y), 63, asLongReg(scratch2)).emit(masm);
-            new And(asLongReg(scratch2), asLongReg(x), asLongReg(scratch2)).emit(masm);
-            new Sub(asLongReg(scratch1), asLongReg(scratch2), asLongReg(scratch1)).emit(masm);
+            masm.srax(asLongReg(y), 63, asLongReg(scratch2));
+            masm.and(asLongReg(scratch2), asLongReg(x), asLongReg(scratch2));
+            masm.sub(asLongReg(scratch1), asLongReg(scratch2), asLongReg(scratch1));
 
             // Now construct the lower half and compare
-            new Srax(asLongReg(result), 63, asLongReg(scratch2)).emit(masm);
-            new Cmp(asLongReg(scratch1), asLongReg(scratch2)).emit(masm);
+            masm.srax(asLongReg(result), 63, asLongReg(scratch2));
+            masm.cmp(asLongReg(scratch1), asLongReg(scratch2));
             masm.bpcc(Equal, NOT_ANNUL, noOverflow, Xcc, PREDICT_TAKEN);
             masm.nop();
-            new Wrccr(g0, 1 << (CCR_XCC_SHIFT + CCR_V_SHIFT)).emit(masm);
+            masm.wrccr(g0, 1 << (CCR_XCC_SHIFT + CCR_V_SHIFT));
             masm.bind(noOverflow);
         }
     }
@@ -259,86 +237,86 @@
         delaySlotLir.emitControlTransfer(crb, masm);
         switch (opcode) {
             case IADD:
-                new Add(asIntReg(src1), constant, asIntReg(dst)).emit(masm);
+                masm.add(asIntReg(src1), constant, asIntReg(dst));
                 break;
             case IADDCC:
-                new Addcc(asIntReg(src1), constant, asIntReg(dst)).emit(masm);
+                masm.addcc(asIntReg(src1), constant, asIntReg(dst));
                 break;
             case ISUB:
-                new Sub(asIntReg(src1), constant, asIntReg(dst)).emit(masm);
+                masm.sub(asIntReg(src1), constant, asIntReg(dst));
                 break;
             case ISUBCC:
-                new Subcc(asIntReg(src1), constant, asIntReg(dst)).emit(masm);
+                masm.subcc(asIntReg(src1), constant, asIntReg(dst));
                 break;
             case IMUL:
-                new Mulx(asIntReg(src1), constant, asIntReg(dst)).emit(masm);
+                masm.mulx(asIntReg(src1), constant, asIntReg(dst));
                 break;
             case IMULCC:
                 throw GraalInternalError.unimplemented();
             case IDIV:
-                new Sdivx(asIntReg(src1), constant, asIntReg(dst)).emit(masm);
+                masm.sdivx(asIntReg(src1), constant, asIntReg(dst));
                 break;
             case IUDIV:
-                new Udivx(asIntReg(src1), constant, asIntReg(dst)).emit(masm);
+                masm.udivx(asIntReg(src1), constant, asIntReg(dst));
                 break;
             case IAND:
-                new And(asIntReg(src1), constant, asIntReg(dst)).emit(masm);
+                masm.and(asIntReg(src1), constant, asIntReg(dst));
                 break;
             case ISHL:
-                new Sll(asIntReg(src1), constant, asIntReg(dst)).emit(masm);
+                masm.sll(asIntReg(src1), constant, asIntReg(dst));
                 break;
             case ISHR:
-                new Sra(asIntReg(src1), constant, asIntReg(dst)).emit(masm);
+                masm.sra(asIntReg(src1), constant, asIntReg(dst));
                 break;
             case IUSHR:
-                new Srl(asIntReg(src1), constant, asIntReg(dst)).emit(masm);
+                masm.srl(asIntReg(src1), constant, asIntReg(dst));
                 break;
             case IOR:
-                new Or(asIntReg(src1), constant, asIntReg(dst)).emit(masm);
+                masm.or(asIntReg(src1), constant, asIntReg(dst));
                 break;
             case IXOR:
-                new Xor(asIntReg(src1), constant, asIntReg(dst)).emit(masm);
+                masm.xor(asIntReg(src1), constant, asIntReg(dst));
                 break;
             case LADD:
-                new Add(asLongReg(src1), constant, asLongReg(dst)).emit(masm);
+                masm.add(asLongReg(src1), constant, asLongReg(dst));
                 break;
             case LADDCC:
-                new Addcc(asLongReg(src1), constant, asLongReg(dst)).emit(masm);
+                masm.addcc(asLongReg(src1), constant, asLongReg(dst));
                 break;
             case LSUB:
-                new Sub(asLongReg(src1), constant, asLongReg(dst)).emit(masm);
+                masm.sub(asLongReg(src1), constant, asLongReg(dst));
                 break;
             case LSUBCC:
-                new Subcc(asLongReg(src1), constant, asLongReg(dst)).emit(masm);
+                masm.subcc(asLongReg(src1), constant, asLongReg(dst));
                 break;
             case LMUL:
-                new Mulx(asLongReg(src1), constant, asLongReg(dst)).emit(masm);
+                masm.mulx(asLongReg(src1), constant, asLongReg(dst));
                 break;
             case LDIV:
                 exceptionOffset = masm.position();
-                new Sdivx(asLongReg(src1), constant, asLongReg(dst)).emit(masm);
+                masm.sdivx(asLongReg(src1), constant, asLongReg(dst));
                 break;
             case LUDIV:
                 exceptionOffset = masm.position();
-                new Udivx(asLongReg(src1), constant, asLongReg(dst)).emit(masm);
+                masm.udivx(asLongReg(src1), constant, asLongReg(dst));
                 break;
             case LAND:
-                new And(asLongReg(src1), constant, asLongReg(dst)).emit(masm);
+                masm.and(asLongReg(src1), constant, asLongReg(dst));
                 break;
             case LOR:
-                new Or(asLongReg(src1), constant, asLongReg(dst)).emit(masm);
+                masm.or(asLongReg(src1), constant, asLongReg(dst));
                 break;
             case LXOR:
-                new Xor(asLongReg(src1), constant, asLongReg(dst)).emit(masm);
+                masm.xor(asLongReg(src1), constant, asLongReg(dst));
                 break;
             case LSHL:
-                new Sllx(asLongReg(src1), constant, asLongReg(dst)).emit(masm);
+                masm.sllx(asLongReg(src1), constant, asLongReg(dst));
                 break;
             case LSHR:
-                new Srax(asLongReg(src1), constant, asLongReg(dst)).emit(masm);
+                masm.srax(asLongReg(src1), constant, asLongReg(dst));
                 break;
             case LUSHR:
-                new Srlx(asLongReg(src1), constant, asLongReg(dst)).emit(masm);
+                masm.srlx(asLongReg(src1), constant, asLongReg(dst));
                 break;
             case DAND: // Has no constant implementation in SPARC
             case FADD:
@@ -364,139 +342,139 @@
         switch (opcode) {
             case IADD:
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Add(asIntReg(src1), asIntReg(src2), asIntReg(dst)).emit(masm);
+                masm.add(asIntReg(src1), asIntReg(src2), asIntReg(dst));
                 break;
             case IADDCC:
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Addcc(asIntReg(src1), asIntReg(src2), asIntReg(dst)).emit(masm);
+                masm.addcc(asIntReg(src1), asIntReg(src2), asIntReg(dst));
                 break;
             case ISUB:
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Sub(asIntReg(src1), asIntReg(src2), asIntReg(dst)).emit(masm);
+                masm.sub(asIntReg(src1), asIntReg(src2), asIntReg(dst));
                 break;
             case ISUBCC:
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Subcc(asIntReg(src1), asIntReg(src2), asIntReg(dst)).emit(masm);
+                masm.subcc(asIntReg(src1), asIntReg(src2), asIntReg(dst));
                 break;
             case IMUL:
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Mulx(asIntReg(src1), asIntReg(src2), asIntReg(dst)).emit(masm);
+                masm.mulx(asIntReg(src1), asIntReg(src2), asIntReg(dst));
                 break;
             case IMULCC:
                 try (SPARCScratchRegister tmpScratch = SPARCScratchRegister.get()) {
                     Register tmp = tmpScratch.getRegister();
-                    new Mulx(asIntReg(src1), asIntReg(src2), asIntReg(dst)).emit(masm);
+                    masm.mulx(asIntReg(src1), asIntReg(src2), asIntReg(dst));
                     Label noOverflow = new Label();
-                    new Sra(asIntReg(dst), 0, tmp).emit(masm);
-                    new Xorcc(SPARC.g0, SPARC.g0, SPARC.g0).emit(masm);
+                    masm.sra(asIntReg(dst), 0, tmp);
+                    masm.xorcc(SPARC.g0, SPARC.g0, SPARC.g0);
                     if (masm.hasFeature(CBCOND)) {
                         masm.cbcondx(Equal, tmp, asIntReg(dst), noOverflow);
                         // Is necessary, otherwise we will have a penalty of 5 cycles in S3
                         masm.nop();
                     } else {
-                        new Cmp(tmp, asIntReg(dst)).emit(masm);
+                        masm.cmp(tmp, asIntReg(dst));
                         masm.bpcc(Equal, NOT_ANNUL, noOverflow, Xcc, PREDICT_TAKEN);
                         masm.nop();
                     }
-                    new Wrccr(SPARC.g0, 1 << (SPARCAssembler.CCR_ICC_SHIFT + SPARCAssembler.CCR_V_SHIFT)).emit(masm);
+                    masm.wrccr(SPARC.g0, 1 << (SPARCAssembler.CCR_ICC_SHIFT + SPARCAssembler.CCR_V_SHIFT));
                     masm.bind(noOverflow);
                 }
                 break;
             case IDIV:
-                new Signx(asIntReg(src1), asIntReg(src1)).emit(masm);
-                new Signx(asIntReg(src2), asIntReg(src2)).emit(masm);
+                masm.signx(asIntReg(src1), asIntReg(src1));
+                masm.signx(asIntReg(src2), asIntReg(src2));
                 delaySlotLir.emitControlTransfer(crb, masm);
                 exceptionOffset = masm.position();
-                new Sdivx(asIntReg(src1), asIntReg(src2), asIntReg(dst)).emit(masm);
+                masm.sdivx(asIntReg(src1), asIntReg(src2), asIntReg(dst));
                 break;
             case IUDIV:
-                new Signx(asIntReg(src1), asIntReg(src1)).emit(masm);
-                new Signx(asIntReg(src2), asIntReg(src2)).emit(masm);
+                masm.signx(asIntReg(src1), asIntReg(src1));
+                masm.signx(asIntReg(src2), asIntReg(src2));
                 delaySlotLir.emitControlTransfer(crb, masm);
                 exceptionOffset = masm.position();
-                new Udivx(asIntReg(src1), asIntReg(src2), asIntReg(dst)).emit(masm);
+                masm.udivx(asIntReg(src1), asIntReg(src2), asIntReg(dst));
                 break;
             case IAND:
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new And(asIntReg(src1), asIntReg(src2), asIntReg(dst)).emit(masm);
+                masm.and(asIntReg(src1), asIntReg(src2), asIntReg(dst));
                 break;
             case IOR:
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Or(asIntReg(src1), asIntReg(src2), asIntReg(dst)).emit(masm);
+                masm.or(asIntReg(src1), asIntReg(src2), asIntReg(dst));
                 break;
             case IXOR:
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Xor(asIntReg(src1), asIntReg(src2), asIntReg(dst)).emit(masm);
+                masm.xor(asIntReg(src1), asIntReg(src2), asIntReg(dst));
                 break;
             case ISHL:
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Sll(asIntReg(src1), asIntReg(src2), asIntReg(dst)).emit(masm);
+                masm.sll(asIntReg(src1), asIntReg(src2), asIntReg(dst));
                 break;
             case ISHR:
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Sra(asIntReg(src1), asIntReg(src2), asIntReg(dst)).emit(masm);
+                masm.sra(asIntReg(src1), asIntReg(src2), asIntReg(dst));
                 break;
             case IUSHR:
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Srl(asIntReg(src1), asIntReg(src2), asIntReg(dst)).emit(masm);
+                masm.srl(asIntReg(src1), asIntReg(src2), asIntReg(dst));
                 break;
             case IREM:
                 throw GraalInternalError.unimplemented();
             case LADD:
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Add(asLongReg(src1), asLongReg(src2), asLongReg(dst)).emit(masm);
+                masm.add(asLongReg(src1), asLongReg(src2), asLongReg(dst));
                 break;
             case LADDCC:
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Addcc(asLongReg(src1), asLongReg(src2), asLongReg(dst)).emit(masm);
+                masm.addcc(asLongReg(src1), asLongReg(src2), asLongReg(dst));
                 break;
             case LSUB:
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Sub(asLongReg(src1), asLongReg(src2), asLongReg(dst)).emit(masm);
+                masm.sub(asLongReg(src1), asLongReg(src2), asLongReg(dst));
                 break;
             case LSUBCC:
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Subcc(asLongReg(src1), asLongReg(src2), asLongReg(dst)).emit(masm);
+                masm.subcc(asLongReg(src1), asLongReg(src2), asLongReg(dst));
                 break;
             case LMUL:
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Mulx(asLongReg(src1), asLongReg(src2), asLongReg(dst)).emit(masm);
+                masm.mulx(asLongReg(src1), asLongReg(src2), asLongReg(dst));
                 break;
             case LMULCC:
                 throw GraalInternalError.unimplemented();
             case LDIV:
                 delaySlotLir.emitControlTransfer(crb, masm);
                 exceptionOffset = masm.position();
-                new Sdivx(asLongReg(src1), asLongReg(src2), asLongReg(dst)).emit(masm);
+                masm.sdivx(asLongReg(src1), asLongReg(src2), asLongReg(dst));
                 break;
             case LUDIV:
                 delaySlotLir.emitControlTransfer(crb, masm);
                 exceptionOffset = masm.position();
-                new Udivx(asLongReg(src1), asLongReg(src2), asLongReg(dst)).emit(masm);
+                masm.udivx(asLongReg(src1), asLongReg(src2), asLongReg(dst));
                 break;
             case LAND:
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new And(asLongReg(src1), asLongReg(src2), asLongReg(dst)).emit(masm);
+                masm.and(asLongReg(src1), asLongReg(src2), asLongReg(dst));
                 break;
             case LOR:
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Or(asLongReg(src1), asLongReg(src2), asLongReg(dst)).emit(masm);
+                masm.or(asLongReg(src1), asLongReg(src2), asLongReg(dst));
                 break;
             case LXOR:
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Xor(asLongReg(src1), asLongReg(src2), asLongReg(dst)).emit(masm);
+                masm.xor(asLongReg(src1), asLongReg(src2), asLongReg(dst));
                 break;
             case LSHL:
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Sllx(asLongReg(src1), asIntReg(src2), asLongReg(dst)).emit(masm);
+                masm.sllx(asLongReg(src1), asIntReg(src2), asLongReg(dst));
                 break;
             case LSHR:
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Srax(asLongReg(src1), asIntReg(src2), asLongReg(dst)).emit(masm);
+                masm.srax(asLongReg(src1), asIntReg(src2), asLongReg(dst));
                 break;
             case LUSHR:
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Srlx(asLongReg(src1), asIntReg(src2), asLongReg(dst)).emit(masm);
+                masm.srlx(asLongReg(src1), asIntReg(src2), asLongReg(dst));
                 break;
             case FADD:
                 delaySlotLir.emitControlTransfer(crb, masm);
@@ -563,26 +541,26 @@
             assert !src2.equals(scratch1);
             switch (opcode) {
                 case IREM:
-                    new Sra(asIntReg(src1), 0, asIntReg(dst)).emit(masm);
+                    masm.sra(asIntReg(src1), 0, asIntReg(dst));
                     exceptionOffset = masm.position();
-                    new Sdivx(asIntReg(dst), crb.asIntConst(src2), asIntReg(scratch1)).emit(masm);
-                    new Mulx(asIntReg(scratch1), crb.asIntConst(src2), asIntReg(scratch2)).emit(masm);
+                    masm.sdivx(asIntReg(dst), crb.asIntConst(src2), asIntReg(scratch1));
+                    masm.mulx(asIntReg(scratch1), crb.asIntConst(src2), asIntReg(scratch2));
                     delaySlotLir.emitControlTransfer(crb, masm);
-                    new Sub(asIntReg(dst), asIntReg(scratch2), asIntReg(dst)).emit(masm);
+                    masm.sub(asIntReg(dst), asIntReg(scratch2), asIntReg(dst));
                     break;
                 case LREM:
                     exceptionOffset = masm.position();
-                    new Sdivx(asLongReg(src1), crb.asIntConst(src2), asLongReg(scratch1)).emit(masm);
-                    new Mulx(asLongReg(scratch1), crb.asIntConst(src2), asLongReg(scratch2)).emit(masm);
+                    masm.sdivx(asLongReg(src1), crb.asIntConst(src2), asLongReg(scratch1));
+                    masm.mulx(asLongReg(scratch1), crb.asIntConst(src2), asLongReg(scratch2));
                     delaySlotLir.emitControlTransfer(crb, masm);
-                    new Sub(asLongReg(src1), asLongReg(scratch2), asLongReg(dst)).emit(masm);
+                    masm.sub(asLongReg(src1), asLongReg(scratch2), asLongReg(dst));
                     break;
                 case LUREM:
                     exceptionOffset = masm.position();
-                    new Udivx(asLongReg(src1), crb.asIntConst(src2), asLongReg(scratch1)).emit(masm);
-                    new Mulx(asLongReg(scratch1), crb.asIntConst(src2), asLongReg(scratch2)).emit(masm);
+                    masm.udivx(asLongReg(src1), crb.asIntConst(src2), asLongReg(scratch1));
+                    masm.mulx(asLongReg(scratch1), crb.asIntConst(src2), asLongReg(scratch2));
                     delaySlotLir.emitControlTransfer(crb, masm);
-                    new Sub(asLongReg(src1), asLongReg(scratch2), asLongReg(dst)).emit(masm);
+                    masm.sub(asLongReg(src1), asLongReg(scratch2), asLongReg(dst));
                     break;
                 case IUREM:
                     GraalInternalError.unimplemented();
@@ -602,10 +580,10 @@
                     assert !asLongReg(src2).equals(asLongReg(scratch1));
                     // But src2 can be scratch2
                     exceptionOffset = masm.position();
-                    new Sdivx(asLongReg(srcLeft), asLongReg(src2), asLongReg(scratch1)).emit(masm);
-                    new Mulx(asLongReg(scratch1), asLongReg(src2), asLongReg(scratch1)).emit(masm);
+                    masm.sdivx(asLongReg(srcLeft), asLongReg(src2), asLongReg(scratch1));
+                    masm.mulx(asLongReg(scratch1), asLongReg(src2), asLongReg(scratch1));
                     delaySlotLir.emitControlTransfer(crb, masm);
-                    new Sub(asLongReg(srcLeft), asLongReg(scratch1), asLongReg(dst)).emit(masm);
+                    masm.sub(asLongReg(srcLeft), asLongReg(scratch1), asLongReg(dst));
                     break;
                 case LUREM:
                     if (isConstant(src1)) {
@@ -615,10 +593,10 @@
                     assert !asLongReg(srcLeft).equals(asLongReg(scratch1));
                     assert !asLongReg(src2).equals(asLongReg(scratch1));
                     exceptionOffset = masm.position();
-                    new Udivx(asLongReg(srcLeft), asLongReg(src2), asLongReg(scratch1)).emit(masm);
-                    new Mulx(asLongReg(scratch1), asLongReg(src2), asLongReg(scratch1)).emit(masm);
+                    masm.udivx(asLongReg(srcLeft), asLongReg(src2), asLongReg(scratch1));
+                    masm.mulx(asLongReg(scratch1), asLongReg(src2), asLongReg(scratch1));
                     delaySlotLir.emitControlTransfer(crb, masm);
-                    new Sub(asLongReg(srcLeft), asLongReg(scratch1), asLongReg(dst)).emit(masm);
+                    masm.sub(asLongReg(srcLeft), asLongReg(scratch1), asLongReg(dst));
                     break;
                 case IREM:
                     if (isConstant(src1)) {
@@ -627,24 +605,24 @@
                     }
                     assert !asIntReg(srcLeft).equals(asIntReg(scratch1));
                     assert !asIntReg(src2).equals(asIntReg(scratch1));
-                    new Sra(asIntReg(src1), 0, asIntReg(scratch1)).emit(masm);
-                    new Sra(asIntReg(src2), 0, asIntReg(scratch2)).emit(masm);
+                    masm.sra(asIntReg(src1), 0, asIntReg(scratch1));
+                    masm.sra(asIntReg(src2), 0, asIntReg(scratch2));
                     exceptionOffset = masm.position();
-                    new Sdivx(asIntReg(scratch1), asIntReg(scratch2), asIntReg(dst)).emit(masm);
-                    new Mulx(asIntReg(dst), asIntReg(scratch2), asIntReg(dst)).emit(masm);
+                    masm.sdivx(asIntReg(scratch1), asIntReg(scratch2), asIntReg(dst));
+                    masm.mulx(asIntReg(dst), asIntReg(scratch2), asIntReg(dst));
                     delaySlotLir.emitControlTransfer(crb, masm);
-                    new Sub(asIntReg(scratch1), asIntReg(dst), asIntReg(dst)).emit(masm);
+                    masm.sub(asIntReg(scratch1), asIntReg(dst), asIntReg(dst));
                     break;
                 case IUREM:
                     assert !asIntReg(dst).equals(asIntReg(scratch1));
                     assert !asIntReg(dst).equals(asIntReg(scratch2));
-                    new Srl(asIntReg(src1), 0, asIntReg(scratch1)).emit(masm);
-                    new Srl(asIntReg(src2), 0, asIntReg(dst)).emit(masm);
+                    masm.srl(asIntReg(src1), 0, asIntReg(scratch1));
+                    masm.srl(asIntReg(src2), 0, asIntReg(dst));
                     exceptionOffset = masm.position();
-                    new Udivx(asIntReg(scratch1), asIntReg(dst), asIntReg(scratch2)).emit(masm);
-                    new Mulx(asIntReg(scratch2), asIntReg(dst), asIntReg(dst)).emit(masm);
+                    masm.udivx(asIntReg(scratch1), asIntReg(dst), asIntReg(scratch2));
+                    masm.mulx(asIntReg(scratch2), asIntReg(dst), asIntReg(dst));
                     delaySlotLir.emitControlTransfer(crb, masm);
-                    new Sub(asIntReg(scratch1), asIntReg(dst), asIntReg(dst)).emit(masm);
+                    masm.sub(asIntReg(scratch1), asIntReg(dst), asIntReg(dst));
                     break;
                 default:
                     throw GraalInternalError.shouldNotReachHere();
@@ -664,19 +642,19 @@
         switch (opcode) {
             case INEG:
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Neg(asIntReg(src), asIntReg(dst)).emit(masm);
+                masm.neg(asIntReg(src), asIntReg(dst));
                 break;
             case LNEG:
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Neg(asLongReg(src), asLongReg(dst)).emit(masm);
+                masm.neg(asLongReg(src), asLongReg(dst));
                 break;
             case INOT:
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Not(asIntReg(src), asIntReg(dst)).emit(masm);
+                masm.not(asIntReg(src), asIntReg(dst));
                 break;
             case LNOT:
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Not(asLongReg(src), asLongReg(dst)).emit(masm);
+                masm.not(asLongReg(src), asLongReg(dst));
                 break;
             case D2F:
                 delaySlotLir.emitControlTransfer(crb, masm);
@@ -696,31 +674,31 @@
                 break;
             case I2L:
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Signx(asIntReg(src), asLongReg(dst)).emit(masm);
+                masm.signx(asIntReg(src), asLongReg(dst));
                 break;
             case L2I:
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Signx(asLongReg(src), asIntReg(dst)).emit(masm);
+                masm.signx(asLongReg(src), asIntReg(dst));
                 break;
             case B2L:
-                new Sll(asIntReg(src), 24, asLongReg(dst)).emit(masm);
+                masm.sll(asIntReg(src), 24, asLongReg(dst));
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Sra(asLongReg(dst), 24, asLongReg(dst)).emit(masm);
+                masm.sra(asLongReg(dst), 24, asLongReg(dst));
                 break;
             case B2I:
-                new Sll(asIntReg(src), 24, asIntReg(dst)).emit(masm);
+                masm.sll(asIntReg(src), 24, asIntReg(dst));
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Sra(asIntReg(dst), 24, asIntReg(dst)).emit(masm);
+                masm.sra(asIntReg(dst), 24, asIntReg(dst));
                 break;
             case S2L:
-                new Sll(asIntReg(src), 16, asLongReg(dst)).emit(masm);
+                masm.sll(asIntReg(src), 16, asLongReg(dst));
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Sra(asLongReg(dst), 16, asLongReg(dst)).emit(masm);
+                masm.sra(asLongReg(dst), 16, asLongReg(dst));
                 break;
             case S2I:
-                new Sll(asIntReg(src), 16, asIntReg(dst)).emit(masm);
+                masm.sll(asIntReg(src), 16, asIntReg(dst));
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Sra(asIntReg(dst), 16, asIntReg(dst)).emit(masm);
+                masm.sra(asIntReg(dst), 16, asIntReg(dst));
                 break;
             case I2F:
                 delaySlotLir.emitControlTransfer(crb, masm);
@@ -884,27 +862,27 @@
             assert isRegister(x) && isRegister(y) && isRegister(result) && isRegister(scratch);
             switch (opcode) {
                 case IMUL:
-                    new Mulx(asIntReg(x), asIntReg(y), asIntReg(result)).emit(masm);
-                    new Srax(asIntReg(result), 32, asIntReg(result)).emit(masm);
+                    masm.mulx(asIntReg(x), asIntReg(y), asIntReg(result));
+                    masm.srax(asIntReg(result), 32, asIntReg(result));
                     break;
                 case IUMUL:
                     assert !asIntReg(scratch).equals(asIntReg(result));
-                    new Srl(asIntReg(x), 0, asIntReg(scratch)).emit(masm);
-                    new Srl(asIntReg(y), 0, asIntReg(result)).emit(masm);
-                    new Mulx(asIntReg(result), asIntReg(scratch), asIntReg(result)).emit(masm);
-                    new Srlx(asIntReg(result), 32, asIntReg(result)).emit(masm);
+                    masm.srl(asIntReg(x), 0, asIntReg(scratch));
+                    masm.srl(asIntReg(y), 0, asIntReg(result));
+                    masm.mulx(asIntReg(result), asIntReg(scratch), asIntReg(result));
+                    masm.srlx(asIntReg(result), 32, asIntReg(result));
                     break;
                 case LMUL:
                     assert !asLongReg(scratch).equals(asLongReg(result));
                     masm.umulxhi(asLongReg(x), asLongReg(y), asLongReg(result));
 
-                    new Srlx(asLongReg(x), 63, asLongReg(scratch)).emit(masm);
-                    new Mulx(asLongReg(scratch), asLongReg(y), asLongReg(scratch)).emit(masm);
-                    new Sub(asLongReg(result), asLongReg(scratch), asLongReg(result)).emit(masm);
+                    masm.srlx(asLongReg(x), 63, asLongReg(scratch));
+                    masm.mulx(asLongReg(scratch), asLongReg(y), asLongReg(scratch));
+                    masm.sub(asLongReg(result), asLongReg(scratch), asLongReg(result));
 
-                    new Srlx(asLongReg(y), 63, asLongReg(scratch)).emit(masm);
-                    new Mulx(asLongReg(scratch), asLongReg(x), asLongReg(scratch)).emit(masm);
-                    new Sub(asLongReg(result), asLongReg(scratch), asLongReg(result)).emit(masm);
+                    masm.srlx(asLongReg(y), 63, asLongReg(scratch));
+                    masm.mulx(asLongReg(scratch), asLongReg(x), asLongReg(scratch));
+                    masm.sub(asLongReg(result), asLongReg(scratch), asLongReg(result));
                     break;
                 case LUMUL:
                     masm.umulxhi(asLongReg(x), asLongReg(y), asLongReg(result));
diff -r 32a5dd091f5f -r f1b4f2613702 graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCArrayEqualsOp.java
--- a/graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCArrayEqualsOp.java	Fri Feb 27 14:43:40 2015 +0100
+++ b/graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCArrayEqualsOp.java	Mon Mar 02 11:22:17 2015 +0100
@@ -23,16 +23,15 @@
 package com.oracle.graal.lir.sparc;
 
 import static com.oracle.graal.api.code.ValueUtil.*;
-import static com.oracle.graal.compiler.common.UnsafeAccess.*;
-import static com.oracle.graal.lir.LIRInstruction.OperandFlag.*;
-import static com.oracle.graal.sparc.SPARC.*;
-import static com.oracle.graal.sparc.SPARC.CPUFeature.*;
-import static com.oracle.graal.asm.sparc.SPARCAssembler.*;
 import static com.oracle.graal.asm.sparc.SPARCAssembler.Annul.*;
 import static com.oracle.graal.asm.sparc.SPARCAssembler.BranchPredict.*;
 import static com.oracle.graal.asm.sparc.SPARCAssembler.CC.*;
 import static com.oracle.graal.asm.sparc.SPARCAssembler.ConditionFlag.*;
 import static com.oracle.graal.asm.sparc.SPARCAssembler.RCondition.*;
+import static com.oracle.graal.compiler.common.UnsafeAccess.*;
+import static com.oracle.graal.lir.LIRInstruction.OperandFlag.*;
+import static com.oracle.graal.sparc.SPARC.*;
+import static com.oracle.graal.sparc.SPARC.CPUFeature.*;
 
 import java.lang.reflect.*;
 
@@ -40,11 +39,16 @@
 import com.oracle.graal.api.meta.*;
 import com.oracle.graal.asm.*;
 import com.oracle.graal.asm.sparc.*;
-import com.oracle.graal.asm.sparc.SPARCMacroAssembler.Cmp;
-import com.oracle.graal.asm.sparc.SPARCMacroAssembler.Mov;
+import com.oracle.graal.asm.sparc.SPARCAssembler.CC;
+import com.oracle.graal.asm.sparc.SPARCAssembler.ConditionFlag;
+import com.oracle.graal.asm.sparc.SPARCAssembler.Ldub;
+import com.oracle.graal.asm.sparc.SPARCAssembler.Lduh;
+import com.oracle.graal.asm.sparc.SPARCAssembler.Lduw;
+import com.oracle.graal.asm.sparc.SPARCAssembler.Ldx;
 import com.oracle.graal.lir.*;
 import com.oracle.graal.lir.asm.*;
 import com.oracle.graal.lir.gen.*;
+import com.oracle.graal.sparc.SPARC.CPUFeature;
 
 /**
  * Emits code which compares two arrays of the same length.
@@ -98,25 +102,25 @@
         Label done = new Label();
 
         // Load array base addresses.
-        new Add(asObjectReg(array1Value), arrayBaseOffset, array1).emit(masm);
-        new Add(asObjectReg(array2Value), arrayBaseOffset, array2).emit(masm);
+        masm.add(asObjectReg(array1Value), arrayBaseOffset, array1);
+        masm.add(asObjectReg(array2Value), arrayBaseOffset, array2);
 
         // Get array length in bytes.
-        new Mulx(asIntReg(lengthValue), arrayIndexScale, length).emit(masm);
-        new Mov(length, result).emit(masm); // copy
+        masm.mulx(asIntReg(lengthValue), arrayIndexScale, length);
+        masm.mov(length, result); // copy
 
         emit8ByteCompare(masm, result, array1, array2, length, trueLabel, falseLabel);
         emitTailCompares(masm, result, array1, array2, trueLabel, falseLabel);
 
         // Return true
         masm.bind(trueLabel);
-        new Mov(1, result).emit(masm);
+        masm.mov(1, result);
         masm.bicc(Always, ANNUL, done);
         masm.nop();
 
         // Return false
         masm.bind(falseLabel);
-        new Mov(g0, result).emit(masm);
+        masm.mov(g0, result);
 
         // That's it
         masm.bind(done);
@@ -140,14 +144,14 @@
 
         boolean hasCBcond = masm.hasFeature(CPUFeature.CBCOND);
 
-        new And(result, VECTOR_SIZE - 1, result).emit(masm); // tail count (in bytes)
-        new Andcc(length, ~(VECTOR_SIZE - 1), length).emit(masm);  // vector count (in bytes)
+        masm.and(result, VECTOR_SIZE - 1, result); // tail count (in bytes)
+        masm.andcc(length, ~(VECTOR_SIZE - 1), length);  // vector count (in bytes)
         masm.bpcc(ConditionFlag.Equal, NOT_ANNUL, compareTail, CC.Xcc, PREDICT_NOT_TAKEN);
 
-        new Sub(length, VECTOR_SIZE, length).emit(masm); // Delay slot
-        new Add(array1, length, array1).emit(masm);
-        new Add(array2, length, array2).emit(masm);
-        new Sub(g0, length, length).emit(masm);
+        masm.sub(length, VECTOR_SIZE, length); // Delay slot
+        masm.add(array1, length, array1);
+        masm.add(array2, length, array2);
+        masm.sub(g0, length, length);
 
         // Compare the last element first
         new Ldx(new SPARCAddress(array1, 0), tempReg1).emit(masm);
@@ -158,7 +162,7 @@
             masm.cbcondx(Equal, length, 0, compareTailCorrectVectorEnd);
             masm.nop(); // for optimal performance (see manual)
         } else {
-            new Cmp(tempReg1, tempReg2).emit(masm);
+            masm.cmp(tempReg1, tempReg2);
             masm.bpcc(NotEqual, NOT_ANNUL, falseLabel, Xcc, PREDICT_NOT_TAKEN);
             masm.nop();
             masm.bpr(Rc_z, NOT_ANNUL, compareTailCorrectVectorEnd, PREDICT_NOT_TAKEN, length);
@@ -169,10 +173,10 @@
         new Ldx(new SPARCAddress(array1, length), tempReg1).emit(masm);
         masm.bind(loop);
         new Ldx(new SPARCAddress(array2, length), tempReg2).emit(masm);
-        new Cmp(tempReg1, tempReg2).emit(masm);
+        masm.cmp(tempReg1, tempReg2);
         masm.bpcc(NotEqual, NOT_ANNUL, falseLabel, Xcc, PREDICT_NOT_TAKEN);
         // Delay slot, not annul, add for next iteration
-        new Addcc(length, VECTOR_SIZE, length).emit(masm);
+        masm.addcc(length, VECTOR_SIZE, length);
         // Annul, to prevent access past the array
         masm.bpcc(NotEqual, ANNUL, loop, Xcc, PREDICT_TAKEN);
         new Ldx(new SPARCAddress(array1, length), tempReg1).emit(masm); // Load in delay slot
@@ -187,8 +191,8 @@
 
         masm.bind(compareTailCorrectVectorEnd);
         // Correct the array pointers
-        new Add(array1, VECTOR_SIZE, array1).emit(masm);
-        new Add(array2, VECTOR_SIZE, array2).emit(masm);
+        masm.add(array1, VECTOR_SIZE, array1);
+        masm.add(array2, VECTOR_SIZE, array2);
 
         masm.bind(compareTail);
     }
@@ -209,7 +213,7 @@
             if (hasCBcond) {
                 masm.cbcondx(Less, result, 4, compare2Bytes);
             } else {
-                new Cmp(result, 4).emit(masm);
+                masm.cmp(result, 4);
                 masm.bpcc(Less, NOT_ANNUL, compare2Bytes, Xcc, PREDICT_NOT_TAKEN);
                 masm.nop();
             }
@@ -220,16 +224,16 @@
             if (hasCBcond) {
                 masm.cbcondx(NotEqual, tempReg1, tempReg2, falseLabel);
             } else {
-                new Cmp(tempReg1, tempReg2).emit(masm);
+                masm.cmp(tempReg1, tempReg2);
                 masm.bpcc(NotEqual, NOT_ANNUL, falseLabel, Xcc, PREDICT_NOT_TAKEN);
                 masm.nop();
             }
 
             if (kind.getByteCount() <= 2) {
                 // Move array pointers forward.
-                new Add(array1, 4, array1).emit(masm);
-                new Add(array2, 4, array2).emit(masm);
-                new Sub(result, 4, result).emit(masm);
+                masm.add(array1, 4, array1);
+                masm.add(array2, 4, array2);
+                masm.sub(result, 4, result);
 
                 // Compare trailing 2 bytes, if any.
                 masm.bind(compare2Bytes);
@@ -237,7 +241,7 @@
                 if (hasCBcond) {
                     masm.cbcondx(Less, result, 2, compare1Byte);
                 } else {
-                    new Cmp(result, 2).emit(masm);
+                    masm.cmp(result, 2);
                     masm.bpcc(Less, NOT_ANNUL, compare1Byte, Xcc, PREDICT_TAKEN);
                     masm.nop();
                 }
@@ -248,7 +252,7 @@
                 if (hasCBcond) {
                     masm.cbcondx(NotEqual, tempReg1, tempReg2, falseLabel);
                 } else {
-                    new Cmp(tempReg1, tempReg2).emit(masm);
+                    masm.cmp(tempReg1, tempReg2);
                     masm.bpcc(NotEqual, NOT_ANNUL, falseLabel, Xcc, PREDICT_TAKEN);
                     masm.nop();
                 }
@@ -256,16 +260,16 @@
                 // The one-byte tail compare is only required for boolean and byte arrays.
                 if (kind.getByteCount() <= 1) {
                     // Move array pointers forward before we compare the last trailing byte.
-                    new Add(array1, 2, array1).emit(masm);
-                    new Add(array2, 2, array2).emit(masm);
-                    new Sub(result, 2, result).emit(masm);
+                    masm.add(array1, 2, array1);
+                    masm.add(array2, 2, array2);
+                    masm.sub(result, 2, result);
 
                     // Compare trailing byte, if any.
                     masm.bind(compare1Byte);
                     if (hasCBcond) {
                         masm.cbcondx(NotEqual, result, 1, trueLabel);
                     } else {
-                        new Cmp(result, 1).emit(masm);
+                        masm.cmp(result, 1);
                         masm.bpcc(NotEqual, NOT_ANNUL, trueLabel, Xcc, PREDICT_TAKEN);
                         masm.nop();
                     }
@@ -274,7 +278,7 @@
                     if (hasCBcond) {
                         masm.cbcondx(NotEqual, tempReg1, tempReg2, falseLabel);
                     } else {
-                        new Cmp(tempReg1, tempReg2).emit(masm);
+                        masm.cmp(tempReg1, tempReg2);
                         masm.bpcc(NotEqual, NOT_ANNUL, falseLabel, Xcc, PREDICT_TAKEN);
                         masm.nop();
                     }
diff -r 32a5dd091f5f -r f1b4f2613702 graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCBitManipulationOp.java
--- a/graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCBitManipulationOp.java	Fri Feb 27 14:43:40 2015 +0100
+++ b/graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCBitManipulationOp.java	Mon Mar 02 11:22:17 2015 +0100
@@ -29,12 +29,6 @@
 
 import com.oracle.graal.api.code.*;
 import com.oracle.graal.api.meta.*;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Andn;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Or;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Popc;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Srl;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Srlx;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Sub;
 import com.oracle.graal.asm.sparc.*;
 import com.oracle.graal.compiler.common.*;
 import com.oracle.graal.lir.*;
@@ -71,23 +65,23 @@
             switch (opcode) {
                 case IPOPCNT:
                     // clear upper word for 64 bit POPC
-                    new Srl(src, g0, dst).emit(masm);
-                    new Popc(dst, dst).emit(masm);
+                    masm.srl(src, g0, dst);
+                    masm.popc(dst, dst);
                     break;
                 case LPOPCNT:
-                    new Popc(src, dst).emit(masm);
+                    masm.popc(src, dst);
                     break;
                 case BSF:
                     Kind tkind = input.getKind();
                     if (tkind == Kind.Int) {
-                        new Sub(src, 1, dst).emit(masm);
-                        new Andn(dst, src, dst).emit(masm);
-                        new Srl(dst, g0, dst).emit(masm);
-                        new Popc(dst, dst).emit(masm);
+                        masm.sub(src, 1, dst);
+                        masm.andn(dst, src, dst);
+                        masm.srl(dst, g0, dst);
+                        masm.popc(dst, dst);
                     } else if (tkind == Kind.Long) {
-                        new Sub(src, 1, dst).emit(masm);
-                        new Andn(dst, src, dst).emit(masm);
-                        new Popc(dst, dst).emit(masm);
+                        masm.sub(src, 1, dst);
+                        masm.andn(dst, src, dst);
+                        masm.popc(dst, dst);
                     } else {
                         throw GraalInternalError.shouldNotReachHere("missing: " + tkind);
                     }
@@ -97,19 +91,19 @@
                     assert ikind == Kind.Int;
                     Register tmp = asRegister(scratch);
                     assert !tmp.equals(dst);
-                    new Srl(src, 1, tmp).emit(masm);
-                    new Srl(src, 0, dst).emit(masm);
-                    new Or(dst, tmp, dst).emit(masm);
-                    new Srl(dst, 2, tmp).emit(masm);
-                    new Or(dst, tmp, dst).emit(masm);
-                    new Srl(dst, 4, tmp).emit(masm);
-                    new Or(dst, tmp, dst).emit(masm);
-                    new Srl(dst, 8, tmp).emit(masm);
-                    new Or(dst, tmp, dst).emit(masm);
-                    new Srl(dst, 16, tmp).emit(masm);
-                    new Or(dst, tmp, dst).emit(masm);
-                    new Popc(dst, dst).emit(masm);
-                    new Sub(dst, 1, dst).emit(masm);
+                    masm.srl(src, 1, tmp);
+                    masm.srl(src, 0, dst);
+                    masm.or(dst, tmp, dst);
+                    masm.srl(dst, 2, tmp);
+                    masm.or(dst, tmp, dst);
+                    masm.srl(dst, 4, tmp);
+                    masm.or(dst, tmp, dst);
+                    masm.srl(dst, 8, tmp);
+                    masm.or(dst, tmp, dst);
+                    masm.srl(dst, 16, tmp);
+                    masm.or(dst, tmp, dst);
+                    masm.popc(dst, dst);
+                    masm.sub(dst, 1, dst);
                     break;
                 }
                 case LBSR: {
@@ -117,20 +111,20 @@
                     assert lkind == Kind.Long;
                     Register tmp = asRegister(scratch);
                     assert !tmp.equals(dst);
-                    new Srlx(src, 1, tmp).emit(masm);
-                    new Or(src, tmp, dst).emit(masm);
-                    new Srlx(dst, 2, tmp).emit(masm);
-                    new Or(dst, tmp, dst).emit(masm);
-                    new Srlx(dst, 4, tmp).emit(masm);
-                    new Or(dst, tmp, dst).emit(masm);
-                    new Srlx(dst, 8, tmp).emit(masm);
-                    new Or(dst, tmp, dst).emit(masm);
-                    new Srlx(dst, 16, tmp).emit(masm);
-                    new Or(dst, tmp, dst).emit(masm);
-                    new Srlx(dst, 32, tmp).emit(masm);
-                    new Or(dst, tmp, dst).emit(masm);
-                    new Popc(dst, dst).emit(masm);
-                    new Sub(dst, 1, dst).emit(masm); // This is required to fit the given structure.
+                    masm.srlx(src, 1, tmp);
+                    masm.or(src, tmp, dst);
+                    masm.srlx(dst, 2, tmp);
+                    masm.or(dst, tmp, dst);
+                    masm.srlx(dst, 4, tmp);
+                    masm.or(dst, tmp, dst);
+                    masm.srlx(dst, 8, tmp);
+                    masm.or(dst, tmp, dst);
+                    masm.srlx(dst, 16, tmp);
+                    masm.or(dst, tmp, dst);
+                    masm.srlx(dst, 32, tmp);
+                    masm.or(dst, tmp, dst);
+                    masm.popc(dst, dst);
+                    masm.sub(dst, 1, dst); // This is required to fit the given structure.
                     break;
                 }
                 default:
@@ -140,55 +134,16 @@
         } else if (isConstant(input) && isSimm13(crb.asIntConst(input))) {
             switch (opcode) {
                 case IPOPCNT:
-                    new Popc(crb.asIntConst(input), dst).emit(masm);
+                    masm.popc(crb.asIntConst(input), dst);
                     break;
                 case LPOPCNT:
-                    new Popc(crb.asIntConst(input), dst).emit(masm);
+                    masm.popc(crb.asIntConst(input), dst);
                     break;
                 default:
                     throw GraalInternalError.shouldNotReachHere();
             }
         } else {
             throw GraalInternalError.shouldNotReachHere();
-            // SPARCAddress src = (SPARCAddress) crb.asAddress(input);
-            // switch (opcode) {
-            // case IPOPCNT:
-            // new Ldsw(src, tmp).emit(masm);
-            // // clear upper word for 64 bit POPC
-            // new Srl(tmp, g0, dst).emit(masm);
-            // new Popc(tmp, dst).emit(masm);
-            // break;
-            // case LPOPCNT:
-            // new Ldx(src, tmp).emit(masm);
-            // new Popc(tmp, dst).emit(masm);
-            // break;
-            // case BSF:
-            // assert input.getKind() == Kind.Int;
-            // new Ldsw(src, tmp).emit(masm);
-            // new Srl(tmp, 1, tmp).emit(masm);
-            // new Srl(tmp, 0, dst).emit(masm);
-            // new Or(tmp, tmp, dst).emit(masm);
-            // new Srl(dst, 2, tmp).emit(masm);
-            // new Or(dst, tmp, dst).emit(masm);
-            // new Srl(dst, 4, tmp).emit(masm);
-            // new Or(dst, tmp, dst).emit(masm);
-            // new Srl(dst, 8, tmp).emit(masm);
-            // new Or(dst, tmp, dst).emit(masm);
-            // new Srl(dst, 16, tmp).emit(masm);
-            // new Or(dst, tmp, dst).emit(masm);
-            // new Popc(dst, dst).emit(masm);
-            // new Mov(Kind.Int.getBitCount(), tmp).emit(masm);
-            // new Sub(tmp, dst, dst).emit(masm);
-            // break;
-            // case IBSR:
-            // // masm.bsrl(dst, src);
-            // // countLeadingZerosI_bsr masm.bsrq(dst, src);
-            // // masm.bsrl(dst, src);
-            // case LBSR:
-            // // masm.bsrq(dst, src);
-            // default:
-            // throw GraalInternalError.shouldNotReachHere("missing: " + opcode);
-            // }
         }
     }
 
diff -r 32a5dd091f5f -r f1b4f2613702 graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCBreakpointOp.java
--- a/graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCBreakpointOp.java	Fri Feb 27 14:43:40 2015 +0100
+++ b/graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCBreakpointOp.java	Mon Mar 02 11:22:17 2015 +0100
@@ -25,7 +25,6 @@
 import static com.oracle.graal.lir.LIRInstruction.OperandFlag.*;
 
 import com.oracle.graal.api.meta.*;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Ta;
 import com.oracle.graal.asm.sparc.*;
 import com.oracle.graal.lir.*;
 import com.oracle.graal.lir.asm.*;
@@ -52,6 +51,6 @@
 
     @Override
     public void emitCode(CompilationResultBuilder crb, SPARCMacroAssembler masm) {
-        new Ta(ST_RESERVED_FOR_USER_0).emit(masm);
+        masm.ta(ST_RESERVED_FOR_USER_0);
     }
 }
diff -r 32a5dd091f5f -r f1b4f2613702 graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCCall.java
--- a/graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCCall.java	Fri Feb 27 14:43:40 2015 +0100
+++ b/graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCCall.java	Mon Mar 02 11:22:17 2015 +0100
@@ -29,8 +29,6 @@
 import com.oracle.graal.api.code.*;
 import com.oracle.graal.api.meta.*;
 import com.oracle.graal.asm.sparc.*;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Jmpl;
-import com.oracle.graal.asm.sparc.SPARCMacroAssembler.Jmp;
 import com.oracle.graal.asm.sparc.SPARCMacroAssembler.Sethix;
 import com.oracle.graal.compiler.common.*;
 import com.oracle.graal.lir.*;
@@ -191,7 +189,7 @@
             // offset might not fit a 30-bit displacement, generate an
             // indirect call with a 64-bit immediate
             new Sethix(0L, scratch, true).emit(masm);
-            new Jmpl(scratch, 0, o7).emit(masm);
+            masm.jmpl(scratch, 0, o7);
         } else {
             masm.call(0);
         }
@@ -205,7 +203,7 @@
     public static void indirectJmp(CompilationResultBuilder crb, SPARCMacroAssembler masm, Register dst, InvokeTarget target) {
         int before = masm.position();
         new Sethix(0L, dst, true).emit(masm);
-        new Jmp(new SPARCAddress(dst, 0)).emit(masm);
+        masm.jmp(new SPARCAddress(dst, 0));
         masm.nop();  // delay slot
         int after = masm.position();
         crb.recordIndirectCall(before, after, target, null);
@@ -214,7 +212,7 @@
 
     public static void indirectCall(CompilationResultBuilder crb, SPARCMacroAssembler masm, Register dst, InvokeTarget callTarget, LIRFrameState info) {
         int before = masm.position();
-        new Jmpl(dst, 0, o7).emit(masm);
+        masm.jmpl(dst, 0, o7);
         masm.nop();  // delay slot
         int after = masm.position();
         crb.recordIndirectCall(before, after, callTarget, info);
diff -r 32a5dd091f5f -r f1b4f2613702 graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCCompare.java
--- a/graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCCompare.java	Fri Feb 27 14:43:40 2015 +0100
+++ b/graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCCompare.java	Mon Mar 02 11:22:17 2015 +0100
@@ -30,7 +30,6 @@
 
 import com.oracle.graal.api.meta.*;
 import com.oracle.graal.asm.sparc.*;
-import com.oracle.graal.asm.sparc.SPARCMacroAssembler.Cmp;
 import com.oracle.graal.compiler.common.*;
 import com.oracle.graal.lir.*;
 import com.oracle.graal.lir.asm.*;
@@ -81,13 +80,13 @@
         if (isRegister(y)) {
             switch (opcode) {
                 case ICMP:
-                    new Cmp(asIntReg(x), asIntReg(y)).emit(masm);
+                    masm.cmp(asIntReg(x), asIntReg(y));
                     break;
                 case LCMP:
-                    new Cmp(asLongReg(x), asLongReg(y)).emit(masm);
+                    masm.cmp(asLongReg(x), asLongReg(y));
                     break;
                 case ACMP:
-                    new Cmp(asObjectReg(x), asObjectReg(y)).emit(masm);
+                    masm.cmp(asObjectReg(x), asObjectReg(y));
                     break;
                 case FCMP:
                     masm.fcmp(Fcc0, Fcmps, asFloatReg(x), asFloatReg(y));
@@ -103,15 +102,15 @@
             switch (opcode) {
                 case LCMP:
                     assert isSimm13(crb.asLongConst(y));
-                    new Cmp(asLongReg(x), (int) crb.asLongConst(y)).emit(masm);
+                    masm.cmp(asLongReg(x), (int) crb.asLongConst(y));
                     break;
                 case ICMP:
                     assert isSimm13(crb.asIntConst(y));
-                    new Cmp(asIntReg(x), crb.asIntConst(y)).emit(masm);
+                    masm.cmp(asIntReg(x), crb.asIntConst(y));
                     break;
                 case ACMP:
                     if (((JavaConstant) y).isNull()) {
-                        new Cmp(asObjectReg(x), 0).emit(masm);
+                        masm.cmp(asObjectReg(x), 0);
                         break;
                     } else {
                         throw GraalInternalError.shouldNotReachHere("Only null object constants are allowed in comparisons");
diff -r 32a5dd091f5f -r f1b4f2613702 graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCControlFlow.java
--- a/graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCControlFlow.java	Fri Feb 27 14:43:40 2015 +0100
+++ b/graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCControlFlow.java	Mon Mar 02 11:22:17 2015 +0100
@@ -23,25 +23,33 @@
 package com.oracle.graal.lir.sparc;
 
 import static com.oracle.graal.api.code.ValueUtil.*;
-import static com.oracle.graal.lir.LIRInstruction.OperandFlag.*;
-import static com.oracle.graal.sparc.SPARC.*;
 import static com.oracle.graal.asm.sparc.SPARCAssembler.*;
 import static com.oracle.graal.asm.sparc.SPARCAssembler.Annul.*;
 import static com.oracle.graal.asm.sparc.SPARCAssembler.BranchPredict.*;
 import static com.oracle.graal.asm.sparc.SPARCAssembler.CC.*;
 import static com.oracle.graal.asm.sparc.SPARCAssembler.ConditionFlag.*;
+import static com.oracle.graal.lir.LIRInstruction.OperandFlag.*;
+import static com.oracle.graal.sparc.SPARC.*;
 
 import com.oracle.graal.api.code.*;
 import com.oracle.graal.api.meta.*;
 import com.oracle.graal.asm.*;
+import com.oracle.graal.asm.Assembler.LabelHint;
 import com.oracle.graal.asm.sparc.*;
-import com.oracle.graal.asm.sparc.SPARCMacroAssembler.*;
+import com.oracle.graal.asm.sparc.SPARCAssembler.BranchPredict;
+import com.oracle.graal.asm.sparc.SPARCAssembler.CC;
+import com.oracle.graal.asm.sparc.SPARCAssembler.ConditionFlag;
+import com.oracle.graal.asm.sparc.SPARCAssembler.Fmovdcc;
+import com.oracle.graal.asm.sparc.SPARCAssembler.Fmovscc;
+import com.oracle.graal.asm.sparc.SPARCAssembler.Movcc;
+import com.oracle.graal.asm.sparc.SPARCMacroAssembler.Setx;
 import com.oracle.graal.compiler.common.*;
 import com.oracle.graal.compiler.common.calc.*;
 import com.oracle.graal.lir.*;
-import com.oracle.graal.lir.StandardOp.*;
+import com.oracle.graal.lir.StandardOp.BlockEndOp;
 import com.oracle.graal.lir.SwitchStrategy.BaseSwitchClosure;
 import com.oracle.graal.lir.asm.*;
+import com.oracle.graal.sparc.SPARC.CPUFeature;
 import com.oracle.graal.sparc.*;
 
 public class SPARCControlFlow {
@@ -60,7 +68,7 @@
         }
 
         public static void emitCodeHelper(CompilationResultBuilder crb, SPARCMacroAssembler masm) {
-            new Ret().emit(masm);
+            masm.ret();
             // On SPARC we always leave the frame (in the delay slot).
             crb.frameContext.leave(crb);
         }
@@ -429,7 +437,7 @@
                             throw new GraalInternalError("switch only supported for int, long and object");
                     }
                     ConditionFlag conditionFlag = ConditionFlag.fromCondtition(conditionCode, condition, false);
-                    new Cmp(keyRegister, scratchRegister).emit(masm);
+                    masm.cmp(keyRegister, scratchRegister);
                     masm.bpcc(conditionFlag, NOT_ANNUL, target, conditionCode, PREDICT_TAKEN);
                     masm.nop();  // delay slot
                 }
@@ -464,22 +472,22 @@
 
             // subtract the low value from the switch value
             if (isSimm13(lowKey)) {
-                new Sub(value, lowKey, scratchReg).emit(masm);
+                masm.sub(value, lowKey, scratchReg);
             } else {
                 try (SPARCScratchRegister sc = SPARCScratchRegister.get()) {
                     Register scratch2 = sc.getRegister();
                     new Setx(lowKey, scratch2).emit(masm);
-                    new Sub(value, scratch2, scratchReg).emit(masm);
+                    masm.sub(value, scratch2, scratchReg);
                 }
             }
             int upperLimit = highKey - lowKey;
             try (SPARCScratchRegister sc = SPARCScratchRegister.get()) {
                 Register scratch2 = sc.getRegister();
                 if (isSimm13(upperLimit)) {
-                    new Cmp(scratchReg, upperLimit).emit(masm);
+                    masm.cmp(scratchReg, upperLimit);
                 } else {
                     new Setx(upperLimit, scratch2).emit(masm);
-                    new Cmp(scratchReg, upperLimit).emit(masm);
+                    masm.cmp(scratchReg, upperLimit);
                 }
 
                 // Jump to default target if index is not within the jump table
@@ -489,14 +497,14 @@
                 }
 
                 // Load jump table entry into scratch and jump to it
-                new Sll(scratchReg, 3, scratchReg).emit(masm); // Multiply by 8
+                masm.sll(scratchReg, 3, scratchReg); // Multiply by 8
                 // Zero the left bits sll with shcnt>0 does not mask upper 32 bits
-                new Srl(scratchReg, 0, scratchReg).emit(masm);
-                new Rdpc(scratch2).emit(masm);
+                masm.srl(scratchReg, 0, scratchReg);
+                masm.rdpc(scratch2);
 
                 // The jump table follows four instructions after rdpc
-                new Add(scratchReg, 4 * 4, scratchReg).emit(masm);
-                new Jmpl(scratch2, scratchReg, g0).emit(masm);
+                masm.add(scratchReg, 4 * 4, scratchReg);
+                masm.jmpl(scratch2, scratchReg, g0);
             }
             masm.nop();
 
diff -r 32a5dd091f5f -r f1b4f2613702 graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCMove.java
--- a/graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCMove.java	Fri Feb 27 14:43:40 2015 +0100
+++ b/graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCMove.java	Mon Mar 02 11:22:17 2015 +0100
@@ -31,7 +31,6 @@
 import com.oracle.graal.api.code.*;
 import com.oracle.graal.api.meta.*;
 import com.oracle.graal.asm.sparc.*;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Add;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Lddf;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Ldf;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Ldsb;
@@ -39,8 +38,6 @@
 import com.oracle.graal.asm.sparc.SPARCAssembler.Ldsw;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Lduh;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Ldx;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Membar;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Or;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Stb;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Stdf;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Stf;
@@ -49,8 +46,6 @@
 import com.oracle.graal.asm.sparc.SPARCAssembler.Stx;
 import com.oracle.graal.asm.sparc.SPARCMacroAssembler.Cas;
 import com.oracle.graal.asm.sparc.SPARCMacroAssembler.Casx;
-import com.oracle.graal.asm.sparc.SPARCMacroAssembler.Clr;
-import com.oracle.graal.asm.sparc.SPARCMacroAssembler.Mov;
 import com.oracle.graal.asm.sparc.SPARCMacroAssembler.Setx;
 import com.oracle.graal.compiler.common.*;
 import com.oracle.graal.lir.*;
@@ -394,7 +389,7 @@
 
         @Override
         public void emitCode(CompilationResultBuilder crb, SPARCMacroAssembler masm) {
-            new Membar(barriers).emit(masm);
+            masm.membar(barriers);
         }
     }
 
@@ -467,17 +462,17 @@
         if (address.getIndex().equals(Register.None)) {
             if (isSimm13(address.getDisplacement())) {
                 delaySlotHolder.emitControlTransfer(crb, masm);
-                new Add(address.getBase(), address.getDisplacement(), result).emit(masm);
+                masm.add(address.getBase(), address.getDisplacement(), result);
             } else {
                 assert result.encoding() != address.getBase().encoding();
                 new Setx(address.getDisplacement(), result).emit(masm);
                 // No relocation, therefore, the add can be delayed as well
                 delaySlotHolder.emitControlTransfer(crb, masm);
-                new Add(address.getBase(), result, result).emit(masm);
+                masm.add(address.getBase(), result, result);
             }
         } else {
             delaySlotHolder.emitControlTransfer(crb, masm);
-            new Add(address.getBase(), address.getIndex(), result).emit(masm);
+            masm.add(address.getBase(), address.getIndex(), result);
         }
     }
 
@@ -605,7 +600,7 @@
                         Register scratch = sc.getRegister();
                         long value = constant.asLong();
                         if (isSimm13(value)) {
-                            new Or(g0, (int) value, scratch).emit(masm);
+                            masm.or(g0, (int) value, scratch);
                         } else {
                             new Setx(value, scratch).emit(masm);
                         }
@@ -635,7 +630,7 @@
             case Long:
             case Object:
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Mov(src, dst).emit(masm);
+                masm.mov(src, dst);
                 break;
             case Float:
                 if (result.getPlatformKind() == Kind.Float) {
@@ -756,10 +751,10 @@
                 case Int:
                     if (input.isDefaultForKind()) {
                         delaySlotLir.emitControlTransfer(crb, masm);
-                        new Clr(asIntReg(result)).emit(masm);
+                        masm.clr(asIntReg(result));
                     } else if (isSimm13(input.asLong())) {
                         delaySlotLir.emitControlTransfer(crb, masm);
-                        new Or(g0, input.asInt(), asIntReg(result)).emit(masm);
+                        masm.or(g0, input.asInt(), asIntReg(result));
                     } else {
                         Setx set = new Setx(input.asLong(), asIntReg(result), false, true);
                         set.emitFirstPartOfDelayed(masm);
@@ -770,10 +765,10 @@
                 case Long:
                     if (input.isDefaultForKind()) {
                         delaySlotLir.emitControlTransfer(crb, masm);
-                        new Clr(asLongReg(result)).emit(masm);
+                        masm.clr(asLongReg(result));
                     } else if (isSimm13(input.asLong())) {
                         delaySlotLir.emitControlTransfer(crb, masm);
-                        new Or(g0, (int) input.asLong(), asLongReg(result)).emit(masm);
+                        masm.or(g0, (int) input.asLong(), asLongReg(result));
                     } else {
                         Setx setx = new Setx(input.asLong(), asLongReg(result), false, true);
                         setx.emitFirstPartOfDelayed(masm);
@@ -790,7 +785,7 @@
                     } else {
                         if (hasVIS3) {
                             if (isSimm13(constantBits)) {
-                                new Or(g0, constantBits, scratch).emit(masm);
+                                masm.or(g0, constantBits, scratch);
                             } else {
                                 new Setx(constantBits, scratch, false).emit(masm);
                             }
@@ -817,7 +812,7 @@
                     } else {
                         if (hasVIS3) {
                             if (isSimm13(constantBits)) {
-                                new Or(g0, (int) constantBits, scratch).emit(masm);
+                                masm.or(g0, (int) constantBits, scratch);
                             } else {
                                 new Setx(constantBits, scratch, false).emit(masm);
                             }
@@ -838,7 +833,7 @@
                 case Object:
                     if (input.isNull()) {
                         delaySlotLir.emitControlTransfer(crb, masm);
-                        new Clr(asRegister(result)).emit(masm);
+                        masm.clr(asRegister(result));
                     } else if (crb.target.inlineObjects) {
                         crb.recordInlineDataInCode(input); // relocatable cannot be delayed
                         new Setx(0xDEADDEADDEADDEADL, asRegister(result), true).emit(masm);
diff -r 32a5dd091f5f -r f1b4f2613702 graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCTestOp.java
--- a/graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCTestOp.java	Fri Feb 27 14:43:40 2015 +0100
+++ b/graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCTestOp.java	Mon Mar 02 11:22:17 2015 +0100
@@ -24,7 +24,6 @@
 
 import static com.oracle.graal.api.code.ValueUtil.*;
 import static com.oracle.graal.lir.LIRInstruction.OperandFlag.*;
-import static com.oracle.graal.asm.sparc.SPARCAssembler.*;
 import static com.oracle.graal.sparc.SPARC.*;
 
 import com.oracle.graal.api.meta.*;
@@ -51,10 +50,10 @@
                 case Char:
                 case Boolean:
                 case Int:
-                    new Andcc(asIntReg(x), asIntReg(y), g0).emit(masm);
+                    masm.andcc(asIntReg(x), asIntReg(y), g0);
                     break;
                 case Long:
-                    new Andcc(asLongReg(x), asLongReg(y), g0).emit(masm);
+                    masm.andcc(asLongReg(x), asLongReg(y), g0);
                     break;
                 default:
                     throw GraalInternalError.shouldNotReachHere();
@@ -66,10 +65,10 @@
                 case Char:
                 case Boolean:
                 case Int:
-                    new Andcc(asIntReg(x), crb.asIntConst(y), g0).emit(masm);
+                    masm.andcc(asIntReg(x), crb.asIntConst(y), g0);
                     break;
                 case Long:
-                    new Andcc(asLongReg(x), crb.asIntConst(y), g0).emit(masm);
+                    masm.andcc(asLongReg(x), crb.asIntConst(y), g0);
                     break;
                 default:
                     throw GraalInternalError.shouldNotReachHere();
diff -r 32a5dd091f5f -r f1b4f2613702 graal/com.oracle.graal.truffle.hotspot.sparc/src/com/oracle/graal/truffle/hotspot/sparc/SPARCOptimizedCallTargetInstumentationFactory.java
--- a/graal/com.oracle.graal.truffle.hotspot.sparc/src/com/oracle/graal/truffle/hotspot/sparc/SPARCOptimizedCallTargetInstumentationFactory.java	Fri Feb 27 14:43:40 2015 +0100
+++ b/graal/com.oracle.graal.truffle.hotspot.sparc/src/com/oracle/graal/truffle/hotspot/sparc/SPARCOptimizedCallTargetInstumentationFactory.java	Mon Mar 02 11:22:17 2015 +0100
@@ -36,8 +36,6 @@
 import com.oracle.graal.asm.*;
 import com.oracle.graal.asm.sparc.*;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Ldx;
-import com.oracle.graal.asm.sparc.SPARCMacroAssembler.Cmp;
-import com.oracle.graal.asm.sparc.SPARCMacroAssembler.Jmp;
 import com.oracle.graal.hotspot.*;
 import com.oracle.graal.hotspot.meta.*;
 import com.oracle.graal.lir.asm.*;
@@ -67,12 +65,12 @@
                     if (asm.hasFeature(CBCOND)) {
                         asm.cbcondx(Equal, spillRegister, 0, doProlog);
                     } else {
-                        new Cmp(spillRegister, 0).emit(asm);
+                        asm.cmp(spillRegister, 0);
                         asm.bpcc(Equal, NOT_ANNUL, doProlog, Xcc, PREDICT_NOT_TAKEN);
                         asm.nop();
                     }
                     new Ldx(verifiedEntryPointAddress, spillRegister).emit(asm); // in delay slot
-                    new Jmp(spillRegister).emit(asm);
+                    asm.jmp(spillRegister);
                     asm.nop();
                     asm.bind(doProlog);
                 }