# HG changeset patch
# User Roland Schatz <roland.schatz@oracle.com>
# Date 1432722202 -7200
# Node ID f73ffccf4240dc75418f13c89cfcc393182d9561
# Parent  93d486d51ab48f91d8697d94793e208e01e44559
[AMD64] Use shorter encoding of zero-extend opcodes.

diff -r 93d486d51ab4 -r f73ffccf4240 graal/com.oracle.graal.compiler.amd64/src/com/oracle/graal/compiler/amd64/AMD64LIRGenerator.java
--- a/graal/com.oracle.graal.compiler.amd64/src/com/oracle/graal/compiler/amd64/AMD64LIRGenerator.java	Wed May 27 10:57:21 2015 +0200
+++ b/graal/com.oracle.graal.compiler.amd64/src/com/oracle/graal/compiler/amd64/AMD64LIRGenerator.java	Wed May 27 12:23:22 2015 +0200
@@ -1269,20 +1269,23 @@
             assert inputVal.getKind().getStackKind() == Kind.Int;
 
             LIRKind resultKind = LIRKind.derive(inputVal);
-            OperandSize resultSize;
             if (toBits > 32) {
                 resultKind = resultKind.changeType(Kind.Long);
-                resultSize = QWORD;
             } else {
                 resultKind = resultKind.changeType(Kind.Int);
-                resultSize = DWORD;
             }
 
+            /*
+             * Always emit DWORD operations, even if the resultKind is Long. On AMD64, all DWORD
+             * operations implicitly set the upper half of the register to 0, which is what we want
+             * anyway. Compared to the QWORD oparations, the encoding of the DWORD operations is
+             * sometimes one byte shorter.
+             */
             switch (fromBits) {
                 case 8:
-                    return emitConvertOp(resultKind, MOVZXB, resultSize, inputVal);
+                    return emitConvertOp(resultKind, MOVZXB, DWORD, inputVal);
                 case 16:
-                    return emitConvertOp(resultKind, MOVZX, resultSize, inputVal);
+                    return emitConvertOp(resultKind, MOVZX, DWORD, inputVal);
                 case 32:
                     return emitConvertOp(resultKind, MOV, DWORD, inputVal);
             }