Mercurial > hg > truffle
changeset 10959:109747b3b337
AMD64 cleanups
| author | twisti |
|---|---|
| date | Sun, 04 Aug 2013 11:17:49 -0700 |
| parents | e2c63a0b799c |
| children | 8aba11322f4e |
| files | graal/com.oracle.graal.hotspot.amd64/src/com/oracle/graal/hotspot/amd64/AMD64HotSpotGraalRuntime.java graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64Arithmetic.java graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64ControlFlow.java |
| diffstat | 3 files changed, 387 insertions(+), 134 deletions(-) [+] |
line wrap: on
line diff
--- a/graal/com.oracle.graal.hotspot.amd64/src/com/oracle/graal/hotspot/amd64/AMD64HotSpotGraalRuntime.java Sun Aug 04 11:16:01 2013 -0700 +++ b/graal/com.oracle.graal.hotspot.amd64/src/com/oracle/graal/hotspot/amd64/AMD64HotSpotGraalRuntime.java Sun Aug 04 11:17:49 2013 -0700 @@ -58,7 +58,8 @@ protected TargetDescription createTarget() { final int stackFrameAlignment = 16; final int implicitNullCheckLimit = 4096; - return new TargetDescription(createArchitecture(), true, stackFrameAlignment, implicitNullCheckLimit, true); + final boolean inlineObjects = true; + return new TargetDescription(createArchitecture(), true, stackFrameAlignment, implicitNullCheckLimit, inlineObjects); } @Override
--- a/graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64Arithmetic.java Sun Aug 04 11:16:01 2013 -0700 +++ b/graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64Arithmetic.java Sun Aug 04 11:17:49 2013 -0700 @@ -34,8 +34,10 @@ import com.oracle.graal.lir.*; import com.oracle.graal.lir.asm.*; -// @formatter:off public enum AMD64Arithmetic { + + // @formatter:off + IADD, ISUB, IMUL, IDIV, IDIVREM, IREM, IUDIV, IUREM, IAND, IOR, IXOR, ISHL, ISHR, IUSHR, LADD, LSUB, LMUL, LDIV, LDIVREM, LREM, LUDIV, LUREM, LAND, LOR, LXOR, LSHL, LSHR, LUSHR, FADD, FSUB, FMUL, FDIV, FREM, FAND, FOR, FXOR, @@ -53,10 +55,13 @@ */ F2I, D2I, F2L, D2L; + // @formatter:on + /** - * Unary operation with separate source and destination operand. + * Unary operation with separate source and destination operand. */ public static class Unary2Op extends AMD64LIRInstruction { + @Opcode private final AMD64Arithmetic opcode; @Def({REG}) protected AllocatableValue result; @Use({REG, STACK}) protected AllocatableValue x; @@ -74,9 +79,10 @@ } /** - * Unary operation with single operand for source and destination. + * Unary operation with single operand for source and destination. */ public static class Unary1Op extends AMD64LIRInstruction { + @Opcode private final AMD64Arithmetic opcode; @Def({REG, HINT}) protected AllocatableValue result; @Use({REG, STACK}) protected AllocatableValue x; @@ -95,10 +101,11 @@ } /** - * Binary operation with two operands. The first source operand is combined with the destination. - * The second source operand may be a stack slot. + * Binary operation with two operands. The first source operand is combined with the + * destination. The second source operand may be a stack slot. */ public static class BinaryRegStack extends AMD64LIRInstruction { + @Opcode private final AMD64Arithmetic opcode; @Def({REG, HINT}) protected AllocatableValue result; @Use({REG, STACK}) protected AllocatableValue x; @@ -126,10 +133,11 @@ } /** - * Binary operation with two operands. The first source operand is combined with the destination. - * The second source operand must be a register. + * Binary operation with two operands. The first source operand is combined with the + * destination. The second source operand must be a register. */ public static class BinaryRegReg extends AMD64LIRInstruction { + @Opcode private final AMD64Arithmetic opcode; @Def({REG, HINT}) protected AllocatableValue result; @Use({REG, STACK}) protected AllocatableValue x; @@ -160,6 +168,7 @@ * Binary operation with single source/destination operand and one constant. */ public static class BinaryRegConst extends AMD64LIRInstruction { + @Opcode private final AMD64Arithmetic opcode; @Def({REG, HINT}) protected AllocatableValue result; @Use({REG, STACK}) protected AllocatableValue x; @@ -186,9 +195,11 @@ } /** - * Commutative binary operation with two operands. One of the operands is combined with the result. + * Commutative binary operation with two operands. One of the operands is combined with the + * result. */ public static class BinaryCommutative extends AMD64LIRInstruction { + @Opcode private final AMD64Arithmetic opcode; @Def({REG, HINT}) protected AllocatableValue result; @Use({REG, STACK}) protected AllocatableValue x; @@ -222,6 +233,7 @@ * Binary operation with separate source and destination and one constant operand. */ public static class BinaryRegStackConst extends AMD64LIRInstruction { + @Opcode private final AMD64Arithmetic opcode; @Def({REG}) protected AllocatableValue result; @Use({REG, STACK}) protected AllocatableValue x; @@ -248,6 +260,7 @@ } public static class DivRemOp extends AMD64LIRInstruction { + @Opcode private final AMD64Arithmetic opcode; @Def protected AllocatableValue divResult; @Def protected AllocatableValue remResult; @@ -272,7 +285,8 @@ @Override protected void verify() { super.verify(); - // left input in rax, right input in any register but rax and rdx, result quotient in rax, result remainder in rdx + // left input in rax, right input in any register but rax and rdx, result quotient in + // rax, result remainder in rdx assert asRegister(x).equals(AMD64.rax); assert differentRegisters(y, AMD64.rax.asValue(), AMD64.rdx.asValue()); verifyKind(opcode, divResult, x, y); @@ -281,6 +295,7 @@ } public static class FPDivRemOp extends AMD64LIRInstruction { + @Opcode private final AMD64Arithmetic opcode; @Def protected AllocatableValue result; @Use protected AllocatableValue x; @@ -342,11 +357,20 @@ @SuppressWarnings("unused") protected static void emit(TargetMethodAssembler tasm, AMD64MacroAssembler masm, AMD64Arithmetic opcode, AllocatableValue result) { switch (opcode) { - case INEG: masm.negl(asIntReg(result)); break; - case LNEG: masm.negq(asLongReg(result)); break; - case L2I: masm.andl(asIntReg(result), 0xFFFFFFFF); break; - case I2C: masm.andl(asIntReg(result), 0xFFFF); break; - default: throw GraalInternalError.shouldNotReachHere(); + case INEG: + masm.negl(asIntReg(result)); + break; + case LNEG: + masm.negq(asLongReg(result)); + break; + case L2I: + masm.andl(asIntReg(result), 0xFFFFFFFF); + break; + case I2C: + masm.andl(asIntReg(result), 0xFFFF); + break; + default: + throw GraalInternalError.shouldNotReachHere(); } } @@ -354,51 +378,139 @@ int exceptionOffset = -1; if (isRegister(src)) { switch (opcode) { - case IADD: masm.addl(asIntReg(dst), asIntReg(src)); break; - case ISUB: masm.subl(asIntReg(dst), asIntReg(src)); break; - case IAND: masm.andl(asIntReg(dst), asIntReg(src)); break; - case IMUL: masm.imull(asIntReg(dst), asIntReg(src)); break; - case IOR: masm.orl(asIntReg(dst), asIntReg(src)); break; - case IXOR: masm.xorl(asIntReg(dst), asIntReg(src)); break; - case ISHL: assert asIntReg(src).equals(AMD64.rcx); masm.shll(asIntReg(dst)); break; - case ISHR: assert asIntReg(src).equals(AMD64.rcx); masm.sarl(asIntReg(dst)); break; - case IUSHR: assert asIntReg(src).equals(AMD64.rcx); masm.shrl(asIntReg(dst)); break; + case IADD: + masm.addl(asIntReg(dst), asIntReg(src)); + break; + case ISUB: + masm.subl(asIntReg(dst), asIntReg(src)); + break; + case IAND: + masm.andl(asIntReg(dst), asIntReg(src)); + break; + case IMUL: + masm.imull(asIntReg(dst), asIntReg(src)); + break; + case IOR: + masm.orl(asIntReg(dst), asIntReg(src)); + break; + case IXOR: + masm.xorl(asIntReg(dst), asIntReg(src)); + break; + case ISHL: + assert asIntReg(src).equals(AMD64.rcx); + masm.shll(asIntReg(dst)); + break; + case ISHR: + assert asIntReg(src).equals(AMD64.rcx); + masm.sarl(asIntReg(dst)); + break; + case IUSHR: + assert asIntReg(src).equals(AMD64.rcx); + masm.shrl(asIntReg(dst)); + break; - case LADD: masm.addq(asLongReg(dst), asLongReg(src)); break; - case LSUB: masm.subq(asLongReg(dst), asLongReg(src)); break; - case LMUL: masm.imulq(asLongReg(dst), asLongReg(src)); break; - case LAND: masm.andq(asLongReg(dst), asLongReg(src)); break; - case LOR: masm.orq(asLongReg(dst), asLongReg(src)); break; - case LXOR: masm.xorq(asLongReg(dst), asLongReg(src)); break; - case LSHL: assert asIntReg(src).equals(AMD64.rcx); masm.shlq(asLongReg(dst)); break; - case LSHR: assert asIntReg(src).equals(AMD64.rcx); masm.sarq(asLongReg(dst)); break; - case LUSHR: assert asIntReg(src).equals(AMD64.rcx); masm.shrq(asLongReg(dst)); break; + case LADD: + masm.addq(asLongReg(dst), asLongReg(src)); + break; + case LSUB: + masm.subq(asLongReg(dst), asLongReg(src)); + break; + case LMUL: + masm.imulq(asLongReg(dst), asLongReg(src)); + break; + case LAND: + masm.andq(asLongReg(dst), asLongReg(src)); + break; + case LOR: + masm.orq(asLongReg(dst), asLongReg(src)); + break; + case LXOR: + masm.xorq(asLongReg(dst), asLongReg(src)); + break; + case LSHL: + assert asIntReg(src).equals(AMD64.rcx); + masm.shlq(asLongReg(dst)); + break; + case LSHR: + assert asIntReg(src).equals(AMD64.rcx); + masm.sarq(asLongReg(dst)); + break; + case LUSHR: + assert asIntReg(src).equals(AMD64.rcx); + masm.shrq(asLongReg(dst)); + break; - case FADD: masm.addss(asFloatReg(dst), asFloatReg(src)); break; - case FSUB: masm.subss(asFloatReg(dst), asFloatReg(src)); break; - case FMUL: masm.mulss(asFloatReg(dst), asFloatReg(src)); break; - case FDIV: masm.divss(asFloatReg(dst), asFloatReg(src)); break; - case FAND: masm.andps(asFloatReg(dst), asFloatReg(src)); break; - case FOR: masm.orps(asFloatReg(dst), asFloatReg(src)); break; - case FXOR: masm.xorps(asFloatReg(dst), asFloatReg(src)); break; + case FADD: + masm.addss(asFloatReg(dst), asFloatReg(src)); + break; + case FSUB: + masm.subss(asFloatReg(dst), asFloatReg(src)); + break; + case FMUL: + masm.mulss(asFloatReg(dst), asFloatReg(src)); + break; + case FDIV: + masm.divss(asFloatReg(dst), asFloatReg(src)); + break; + case FAND: + masm.andps(asFloatReg(dst), asFloatReg(src)); + break; + case FOR: + masm.orps(asFloatReg(dst), asFloatReg(src)); + break; + case FXOR: + masm.xorps(asFloatReg(dst), asFloatReg(src)); + break; - case DADD: masm.addsd(asDoubleReg(dst), asDoubleReg(src)); break; - case DSUB: masm.subsd(asDoubleReg(dst), asDoubleReg(src)); break; - case DMUL: masm.mulsd(asDoubleReg(dst), asDoubleReg(src)); break; - case DDIV: masm.divsd(asDoubleReg(dst), asDoubleReg(src)); break; - case DAND: masm.andpd(asDoubleReg(dst), asDoubleReg(src)); break; - case DOR: masm.orpd(asDoubleReg(dst), asDoubleReg(src)); break; - case DXOR: masm.xorpd(asDoubleReg(dst), asDoubleReg(src)); break; + case DADD: + masm.addsd(asDoubleReg(dst), asDoubleReg(src)); + break; + case DSUB: + masm.subsd(asDoubleReg(dst), asDoubleReg(src)); + break; + case DMUL: + masm.mulsd(asDoubleReg(dst), asDoubleReg(src)); + break; + case DDIV: + masm.divsd(asDoubleReg(dst), asDoubleReg(src)); + break; + case DAND: + masm.andpd(asDoubleReg(dst), asDoubleReg(src)); + break; + case DOR: + masm.orpd(asDoubleReg(dst), asDoubleReg(src)); + break; + case DXOR: + masm.xorpd(asDoubleReg(dst), asDoubleReg(src)); + break; - case I2B: masm.movsxb(asIntReg(dst), asIntReg(src)); break; - case I2S: masm.movsxw(asIntReg(dst), asIntReg(src)); break; - case I2L: masm.movslq(asLongReg(dst), asIntReg(src)); break; - case F2D: masm.cvtss2sd(asDoubleReg(dst), asFloatReg(src)); break; - case D2F: masm.cvtsd2ss(asFloatReg(dst), asDoubleReg(src)); break; - case I2F: masm.cvtsi2ssl(asFloatReg(dst), asIntReg(src)); break; - case I2D: masm.cvtsi2sdl(asDoubleReg(dst), asIntReg(src)); break; - case L2F: masm.cvtsi2ssq(asFloatReg(dst), asLongReg(src)); break; - case L2D: masm.cvtsi2sdq(asDoubleReg(dst), asLongReg(src)); break; + case I2B: + masm.movsxb(asIntReg(dst), asIntReg(src)); + break; + case I2S: + masm.movsxw(asIntReg(dst), asIntReg(src)); + break; + case I2L: + masm.movslq(asLongReg(dst), asIntReg(src)); + break; + case F2D: + masm.cvtss2sd(asDoubleReg(dst), asFloatReg(src)); + break; + case D2F: + masm.cvtsd2ss(asFloatReg(dst), asDoubleReg(src)); + break; + case I2F: + masm.cvtsi2ssl(asFloatReg(dst), asIntReg(src)); + break; + case I2D: + masm.cvtsi2sdl(asDoubleReg(dst), asIntReg(src)); + break; + case L2F: + masm.cvtsi2ssq(asFloatReg(dst), asLongReg(src)); + break; + case L2D: + masm.cvtsi2sdq(asDoubleReg(dst), asLongReg(src)); + break; case F2I: masm.cvttss2sil(asIntReg(dst), asFloatReg(src)); break; @@ -411,10 +523,18 @@ case D2L: masm.cvttsd2siq(asLongReg(dst), asDoubleReg(src)); break; - case MOV_I2F: masm.movdl(asFloatReg(dst), asIntReg(src)); break; - case MOV_L2D: masm.movdq(asDoubleReg(dst), asLongReg(src)); break; - case MOV_F2I: masm.movdl(asIntReg(dst), asFloatReg(src)); break; - case MOV_D2L: masm.movdq(asLongReg(dst), asDoubleReg(src)); break; + case MOV_I2F: + masm.movdl(asFloatReg(dst), asIntReg(src)); + break; + case MOV_L2D: + masm.movdq(asDoubleReg(dst), asLongReg(src)); + break; + case MOV_F2I: + masm.movdl(asIntReg(dst), asFloatReg(src)); + break; + case MOV_D2L: + masm.movdq(asLongReg(dst), asDoubleReg(src)); + break; case IDIVREM: case IDIV: @@ -452,78 +572,201 @@ } } else if (isConstant(src)) { switch (opcode) { - case IADD: masm.incrementl(asIntReg(dst), tasm.asIntConst(src)); break; - case ISUB: masm.decrementl(asIntReg(dst), tasm.asIntConst(src)); break; - case IMUL: masm.imull(asIntReg(dst), asIntReg(dst), tasm.asIntConst(src)); break; - case IAND: masm.andl(asIntReg(dst), tasm.asIntConst(src)); break; - case IOR: masm.orl(asIntReg(dst), tasm.asIntConst(src)); break; - case IXOR: masm.xorl(asIntReg(dst), tasm.asIntConst(src)); break; - case ISHL: masm.shll(asIntReg(dst), tasm.asIntConst(src) & 31); break; - case ISHR: masm.sarl(asIntReg(dst), tasm.asIntConst(src) & 31); break; - case IUSHR:masm.shrl(asIntReg(dst), tasm.asIntConst(src) & 31); break; + case IADD: + masm.incrementl(asIntReg(dst), tasm.asIntConst(src)); + break; + case ISUB: + masm.decrementl(asIntReg(dst), tasm.asIntConst(src)); + break; + case IMUL: + masm.imull(asIntReg(dst), asIntReg(dst), tasm.asIntConst(src)); + break; + case IAND: + masm.andl(asIntReg(dst), tasm.asIntConst(src)); + break; + case IOR: + masm.orl(asIntReg(dst), tasm.asIntConst(src)); + break; + case IXOR: + masm.xorl(asIntReg(dst), tasm.asIntConst(src)); + break; + case ISHL: + masm.shll(asIntReg(dst), tasm.asIntConst(src) & 31); + break; + case ISHR: + masm.sarl(asIntReg(dst), tasm.asIntConst(src) & 31); + break; + case IUSHR: + masm.shrl(asIntReg(dst), tasm.asIntConst(src) & 31); + break; - case LADD: masm.addq(asLongReg(dst), tasm.asIntConst(src)); break; - case LSUB: masm.subq(asLongReg(dst), tasm.asIntConst(src)); break; - case LMUL: masm.imulq(asLongReg(dst), asLongReg(dst), tasm.asIntConst(src)); break; - case LAND: masm.andq(asLongReg(dst), tasm.asIntConst(src)); break; - case LOR: masm.orq(asLongReg(dst), tasm.asIntConst(src)); break; - case LXOR: masm.xorq(asLongReg(dst), tasm.asIntConst(src)); break; - case LSHL: masm.shlq(asLongReg(dst), tasm.asIntConst(src) & 63); break; - case LSHR: masm.sarq(asLongReg(dst), tasm.asIntConst(src) & 63); break; - case LUSHR:masm.shrq(asLongReg(dst), tasm.asIntConst(src) & 63); break; + case LADD: + masm.addq(asLongReg(dst), tasm.asIntConst(src)); + break; + case LSUB: + masm.subq(asLongReg(dst), tasm.asIntConst(src)); + break; + case LMUL: + masm.imulq(asLongReg(dst), asLongReg(dst), tasm.asIntConst(src)); + break; + case LAND: + masm.andq(asLongReg(dst), tasm.asIntConst(src)); + break; + case LOR: + masm.orq(asLongReg(dst), tasm.asIntConst(src)); + break; + case LXOR: + masm.xorq(asLongReg(dst), tasm.asIntConst(src)); + break; + case LSHL: + masm.shlq(asLongReg(dst), tasm.asIntConst(src) & 63); + break; + case LSHR: + masm.sarq(asLongReg(dst), tasm.asIntConst(src) & 63); + break; + case LUSHR: + masm.shrq(asLongReg(dst), tasm.asIntConst(src) & 63); + break; - case FADD: masm.addss(asFloatReg(dst), (AMD64Address) tasm.asFloatConstRef(src)); break; - case FSUB: masm.subss(asFloatReg(dst), (AMD64Address) tasm.asFloatConstRef(src)); break; - case FMUL: masm.mulss(asFloatReg(dst), (AMD64Address) tasm.asFloatConstRef(src)); break; - case FAND: masm.andps(asFloatReg(dst), (AMD64Address) tasm.asFloatConstRef(src, 16)); break; - case FOR: masm.orps(asFloatReg(dst), (AMD64Address) tasm.asFloatConstRef(src, 16)); break; - case FXOR: masm.xorps(asFloatReg(dst), (AMD64Address) tasm.asFloatConstRef(src, 16)); break; - case FDIV: masm.divss(asFloatReg(dst), (AMD64Address) tasm.asFloatConstRef(src)); break; + case FADD: + masm.addss(asFloatReg(dst), (AMD64Address) tasm.asFloatConstRef(src)); + break; + case FSUB: + masm.subss(asFloatReg(dst), (AMD64Address) tasm.asFloatConstRef(src)); + break; + case FMUL: + masm.mulss(asFloatReg(dst), (AMD64Address) tasm.asFloatConstRef(src)); + break; + case FAND: + masm.andps(asFloatReg(dst), (AMD64Address) tasm.asFloatConstRef(src, 16)); + break; + case FOR: + masm.orps(asFloatReg(dst), (AMD64Address) tasm.asFloatConstRef(src, 16)); + break; + case FXOR: + masm.xorps(asFloatReg(dst), (AMD64Address) tasm.asFloatConstRef(src, 16)); + break; + case FDIV: + masm.divss(asFloatReg(dst), (AMD64Address) tasm.asFloatConstRef(src)); + break; - case DADD: masm.addsd(asDoubleReg(dst), (AMD64Address) tasm.asDoubleConstRef(src)); break; - case DSUB: masm.subsd(asDoubleReg(dst), (AMD64Address) tasm.asDoubleConstRef(src)); break; - case DMUL: masm.mulsd(asDoubleReg(dst), (AMD64Address) tasm.asDoubleConstRef(src)); break; - case DDIV: masm.divsd(asDoubleReg(dst), (AMD64Address) tasm.asDoubleConstRef(src)); break; - case DAND: masm.andpd(asDoubleReg(dst), (AMD64Address) tasm.asDoubleConstRef(src, 16)); break; - case DOR: masm.orpd(asDoubleReg(dst), (AMD64Address) tasm.asDoubleConstRef(src, 16)); break; - case DXOR: masm.xorpd(asDoubleReg(dst), (AMD64Address) tasm.asDoubleConstRef(src, 16)); break; - default: throw GraalInternalError.shouldNotReachHere(); + case DADD: + masm.addsd(asDoubleReg(dst), (AMD64Address) tasm.asDoubleConstRef(src)); + break; + case DSUB: + masm.subsd(asDoubleReg(dst), (AMD64Address) tasm.asDoubleConstRef(src)); + break; + case DMUL: + masm.mulsd(asDoubleReg(dst), (AMD64Address) tasm.asDoubleConstRef(src)); + break; + case DDIV: + masm.divsd(asDoubleReg(dst), (AMD64Address) tasm.asDoubleConstRef(src)); + break; + case DAND: + masm.andpd(asDoubleReg(dst), (AMD64Address) tasm.asDoubleConstRef(src, 16)); + break; + case DOR: + masm.orpd(asDoubleReg(dst), (AMD64Address) tasm.asDoubleConstRef(src, 16)); + break; + case DXOR: + masm.xorpd(asDoubleReg(dst), (AMD64Address) tasm.asDoubleConstRef(src, 16)); + break; + default: + throw GraalInternalError.shouldNotReachHere(); } } else { switch (opcode) { - case IADD: masm.addl(asIntReg(dst), (AMD64Address) tasm.asIntAddr(src)); break; - case ISUB: masm.subl(asIntReg(dst), (AMD64Address) tasm.asIntAddr(src)); break; - case IAND: masm.andl(asIntReg(dst), (AMD64Address) tasm.asIntAddr(src)); break; - case IMUL: masm.imull(asIntReg(dst), (AMD64Address) tasm.asIntAddr(src)); break; - case IOR: masm.orl(asIntReg(dst), (AMD64Address) tasm.asIntAddr(src)); break; - case IXOR: masm.xorl(asIntReg(dst), (AMD64Address) tasm.asIntAddr(src)); break; + case IADD: + masm.addl(asIntReg(dst), (AMD64Address) tasm.asIntAddr(src)); + break; + case ISUB: + masm.subl(asIntReg(dst), (AMD64Address) tasm.asIntAddr(src)); + break; + case IAND: + masm.andl(asIntReg(dst), (AMD64Address) tasm.asIntAddr(src)); + break; + case IMUL: + masm.imull(asIntReg(dst), (AMD64Address) tasm.asIntAddr(src)); + break; + case IOR: + masm.orl(asIntReg(dst), (AMD64Address) tasm.asIntAddr(src)); + break; + case IXOR: + masm.xorl(asIntReg(dst), (AMD64Address) tasm.asIntAddr(src)); + break; - case LADD: masm.addq(asLongReg(dst), (AMD64Address) tasm.asLongAddr(src)); break; - case LSUB: masm.subq(asLongReg(dst), (AMD64Address) tasm.asLongAddr(src)); break; - case LMUL: masm.imulq(asLongReg(dst), (AMD64Address) tasm.asLongAddr(src)); break; - case LAND: masm.andq(asLongReg(dst), (AMD64Address) tasm.asLongAddr(src)); break; - case LOR: masm.orq(asLongReg(dst), (AMD64Address) tasm.asLongAddr(src)); break; - case LXOR: masm.xorq(asLongReg(dst), (AMD64Address) tasm.asLongAddr(src)); break; + case LADD: + masm.addq(asLongReg(dst), (AMD64Address) tasm.asLongAddr(src)); + break; + case LSUB: + masm.subq(asLongReg(dst), (AMD64Address) tasm.asLongAddr(src)); + break; + case LMUL: + masm.imulq(asLongReg(dst), (AMD64Address) tasm.asLongAddr(src)); + break; + case LAND: + masm.andq(asLongReg(dst), (AMD64Address) tasm.asLongAddr(src)); + break; + case LOR: + masm.orq(asLongReg(dst), (AMD64Address) tasm.asLongAddr(src)); + break; + case LXOR: + masm.xorq(asLongReg(dst), (AMD64Address) tasm.asLongAddr(src)); + break; - case FADD: masm.addss(asFloatReg(dst), (AMD64Address) tasm.asFloatAddr(src)); break; - case FSUB: masm.subss(asFloatReg(dst), (AMD64Address) tasm.asFloatAddr(src)); break; - case FMUL: masm.mulss(asFloatReg(dst), (AMD64Address) tasm.asFloatAddr(src)); break; - case FDIV: masm.divss(asFloatReg(dst), (AMD64Address) tasm.asFloatAddr(src)); break; + case FADD: + masm.addss(asFloatReg(dst), (AMD64Address) tasm.asFloatAddr(src)); + break; + case FSUB: + masm.subss(asFloatReg(dst), (AMD64Address) tasm.asFloatAddr(src)); + break; + case FMUL: + masm.mulss(asFloatReg(dst), (AMD64Address) tasm.asFloatAddr(src)); + break; + case FDIV: + masm.divss(asFloatReg(dst), (AMD64Address) tasm.asFloatAddr(src)); + break; - case DADD: masm.addsd(asDoubleReg(dst), (AMD64Address) tasm.asDoubleAddr(src)); break; - case DSUB: masm.subsd(asDoubleReg(dst), (AMD64Address) tasm.asDoubleAddr(src)); break; - case DMUL: masm.mulsd(asDoubleReg(dst), (AMD64Address) tasm.asDoubleAddr(src)); break; - case DDIV: masm.divsd(asDoubleReg(dst), (AMD64Address) tasm.asDoubleAddr(src)); break; + case DADD: + masm.addsd(asDoubleReg(dst), (AMD64Address) tasm.asDoubleAddr(src)); + break; + case DSUB: + masm.subsd(asDoubleReg(dst), (AMD64Address) tasm.asDoubleAddr(src)); + break; + case DMUL: + masm.mulsd(asDoubleReg(dst), (AMD64Address) tasm.asDoubleAddr(src)); + break; + case DDIV: + masm.divsd(asDoubleReg(dst), (AMD64Address) tasm.asDoubleAddr(src)); + break; - case I2B: masm.movsxb(asIntReg(dst), (AMD64Address) tasm.asIntAddr(src)); break; - case I2S: masm.movsxw(asIntReg(dst), (AMD64Address) tasm.asIntAddr(src)); break; - case I2L: masm.movslq(asLongReg(dst), (AMD64Address) tasm.asIntAddr(src)); break; - case F2D: masm.cvtss2sd(asDoubleReg(dst), (AMD64Address) tasm.asFloatAddr(src)); break; - case D2F: masm.cvtsd2ss(asFloatReg(dst), (AMD64Address) tasm.asDoubleAddr(src)); break; - case I2F: masm.cvtsi2ssl(asFloatReg(dst), (AMD64Address) tasm.asIntAddr(src)); break; - case I2D: masm.cvtsi2sdl(asDoubleReg(dst), (AMD64Address) tasm.asIntAddr(src)); break; - case L2F: masm.cvtsi2ssq(asFloatReg(dst), (AMD64Address) tasm.asLongAddr(src)); break; - case L2D: masm.cvtsi2sdq(asDoubleReg(dst), (AMD64Address) tasm.asLongAddr(src)); break; + case I2B: + masm.movsxb(asIntReg(dst), (AMD64Address) tasm.asIntAddr(src)); + break; + case I2S: + masm.movsxw(asIntReg(dst), (AMD64Address) tasm.asIntAddr(src)); + break; + case I2L: + masm.movslq(asLongReg(dst), (AMD64Address) tasm.asIntAddr(src)); + break; + case F2D: + masm.cvtss2sd(asDoubleReg(dst), (AMD64Address) tasm.asFloatAddr(src)); + break; + case D2F: + masm.cvtsd2ss(asFloatReg(dst), (AMD64Address) tasm.asDoubleAddr(src)); + break; + case I2F: + masm.cvtsi2ssl(asFloatReg(dst), (AMD64Address) tasm.asIntAddr(src)); + break; + case I2D: + masm.cvtsi2sdl(asDoubleReg(dst), (AMD64Address) tasm.asIntAddr(src)); + break; + case L2F: + masm.cvtsi2ssq(asFloatReg(dst), (AMD64Address) tasm.asLongAddr(src)); + break; + case L2D: + masm.cvtsi2sdq(asDoubleReg(dst), (AMD64Address) tasm.asLongAddr(src)); + break; case F2I: masm.cvttss2sil(asIntReg(dst), (AMD64Address) tasm.asFloatAddr(src)); break; @@ -536,12 +779,21 @@ case D2L: masm.cvttsd2siq(asLongReg(dst), (AMD64Address) tasm.asDoubleAddr(src)); break; - case MOV_I2F: masm.movss(asFloatReg(dst), (AMD64Address) tasm.asIntAddr(src)); break; - case MOV_L2D: masm.movsd(asDoubleReg(dst), (AMD64Address) tasm.asLongAddr(src)); break; - case MOV_F2I: masm.movl(asIntReg(dst), (AMD64Address) tasm.asFloatAddr(src)); break; - case MOV_D2L: masm.movq(asLongReg(dst), (AMD64Address) tasm.asDoubleAddr(src)); break; + case MOV_I2F: + masm.movss(asFloatReg(dst), (AMD64Address) tasm.asIntAddr(src)); + break; + case MOV_L2D: + masm.movsd(asDoubleReg(dst), (AMD64Address) tasm.asLongAddr(src)); + break; + case MOV_F2I: + masm.movl(asIntReg(dst), (AMD64Address) tasm.asFloatAddr(src)); + break; + case MOV_D2L: + masm.movq(asLongReg(dst), (AMD64Address) tasm.asDoubleAddr(src)); + break; - default: throw GraalInternalError.shouldNotReachHere(); + default: + throw GraalInternalError.shouldNotReachHere(); } } @@ -552,10 +804,10 @@ } private static void verifyKind(AMD64Arithmetic opcode, Value result, Value x, Value y) { - assert (opcode.name().startsWith("I") && result.getKind() == Kind.Int && x.getKind().getStackKind() == Kind.Int && y.getKind().getStackKind() == Kind.Int) - || (opcode.name().startsWith("L") && result.getKind() == Kind.Long && x.getKind() == Kind.Long && y.getKind() == Kind.Long) - || (opcode.name().startsWith("F") && result.getKind() == Kind.Float && x.getKind() == Kind.Float && y.getKind() == Kind.Float) - || (opcode.name().startsWith("D") && result.getKind() == Kind.Double && x.getKind() == Kind.Double && y.getKind() == Kind.Double) - || (opcode.name().matches(".U?SH.") && result.getKind() == x.getKind() && y.getKind() == Kind.Int && (isConstant(y) || asRegister(y).equals(AMD64.rcx))); + assert (opcode.name().startsWith("I") && result.getKind() == Kind.Int && x.getKind().getStackKind() == Kind.Int && y.getKind().getStackKind() == Kind.Int) || + (opcode.name().startsWith("L") && result.getKind() == Kind.Long && x.getKind() == Kind.Long && y.getKind() == Kind.Long) || + (opcode.name().startsWith("F") && result.getKind() == Kind.Float && x.getKind() == Kind.Float && y.getKind() == Kind.Float) || + (opcode.name().startsWith("D") && result.getKind() == Kind.Double && x.getKind() == Kind.Double && y.getKind() == Kind.Double) || + (opcode.name().matches(".U?SH.") && result.getKind() == x.getKind() && y.getKind() == Kind.Int && (isConstant(y) || asRegister(y).equals(AMD64.rcx))); } }
--- a/graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64ControlFlow.java Sun Aug 04 11:16:01 2013 -0700 +++ b/graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64ControlFlow.java Sun Aug 04 11:17:49 2013 -0700 @@ -168,11 +168,11 @@ masm.jcc(ConditionFlag.Equal, keyTargets[i].label()); } } else if (key.getKind() == Kind.Object) { - Register intKey = asObjectReg(key); + Register objectKey = asObjectReg(key); Register temp = asObjectReg(scratch); for (int i = 0; i < keyConstants.length; i++) { AMD64Move.move(tasm, masm, temp.asValue(Kind.Object), keyConstants[i]); - masm.cmpptr(intKey, temp); + masm.cmpptr(objectKey, temp); masm.jcc(ConditionFlag.Equal, keyTargets[i].label()); } } else {