Mercurial > hg > truffle

changeset 7905:38a597987357

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Common base class for Load and Store.
author Roland Schatz <roland.schatz@oracle.com>
date Thu, 28 Feb 2013 14:15:24 +0100
parents c8f2002d2194
children 0c7615691812
files graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64Move.java
diffstat 1 files changed, 25 insertions(+), 24 deletions(-) [+]
line wrap: on
line diff
--- a/graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64Move.java	Thu Feb 28 12:07:59 2013 +0100
+++ b/graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64Move.java	Thu Feb 28 14:15:24 2013 +0100
@@ -122,23 +122,38 @@
         }
     }
 
-    public static class LoadOp extends AMD64LIRInstruction {
+    public abstract static class MemOp extends AMD64LIRInstruction {
 
-        @Def({REG}) protected Value result;
         @Use({ADDR}) protected AMD64Address address;
         @State protected LIRFrameState state;
 
-        public LoadOp(Value result, AMD64Address address, LIRFrameState state) {
-            this.result = result;
+        public MemOp(AMD64Address address, LIRFrameState state) {
             this.address = address;
             this.state = state;
         }
 
+        protected abstract void emitMemAccess(AMD64MacroAssembler masm);
+
         @Override
         public void emitCode(TargetMethodAssembler tasm, AMD64MacroAssembler masm) {
             if (state != null) {
                 tasm.recordImplicitException(masm.codeBuffer.position(), state);
             }
+            emitMemAccess(masm);
+        }
+    }
+
+    public static class LoadOp extends MemOp {
+
+        @Def({REG}) protected Value result;
+
+        public LoadOp(Value result, AMD64Address address, LIRFrameState state) {
+            super(address, state);
+            this.result = result;
+        }
+
+        @Override
+        public void emitMemAccess(AMD64MacroAssembler masm) {
             switch (address.getKind()) {
                 case Boolean:
                 case Byte:
@@ -171,24 +186,17 @@
         }
     }
 
-    public static class StoreOp extends AMD64LIRInstruction {
+    public static class StoreOp extends MemOp {
 
-        @Use({ADDR}) protected AMD64Address address;
         @Use({REG}) protected Value input;
-        @State protected LIRFrameState state;
 
         public StoreOp(AMD64Address address, Value input, LIRFrameState state) {
-            this.address = address;
+            super(address, state);
             this.input = input;
-            this.state = state;
         }
 
         @Override
-        public void emitCode(TargetMethodAssembler tasm, AMD64MacroAssembler masm) {
-            if (state != null) {
-                tasm.recordImplicitException(masm.codeBuffer.position(), state);
-            }
-
+        public void emitMemAccess(AMD64MacroAssembler masm) {
             assert isRegister(input);
             switch (address.getKind()) {
                 case Boolean:
@@ -220,24 +228,17 @@
         }
     }
 
-    public static class StoreConstantOp extends AMD64LIRInstruction {
+    public static class StoreConstantOp extends MemOp {
 
-        @Use({ADDR}) protected AMD64Address address;
         @Use({CONST}) protected Constant input;
-        @State protected LIRFrameState state;
 
         public StoreConstantOp(AMD64Address address, Constant input, LIRFrameState state) {
-            this.address = address;
+            super(address, state);
             this.input = input;
-            this.state = state;
         }
 
         @Override
-        public void emitCode(TargetMethodAssembler tasm, AMD64MacroAssembler masm) {
-            if (state != null) {
-                tasm.recordImplicitException(masm.codeBuffer.position(), state);
-            }
-
+        public void emitMemAccess(AMD64MacroAssembler masm) {
             switch (address.getKind()) {
                 case Boolean:
                 case Byte: