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changeset 8194:75e8020ed0f5

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Merge.
author Roland Schatz <roland.schatz@oracle.com>
date Mon, 11 Mar 2013 12:07:28 +0100
parents 44f79360793e (diff) 3c74a32bb262 (current diff)
children 5619aa66aec1 60a90f433459
files
diffstat 6 files changed, 214 insertions(+), 34 deletions(-) [+]
line wrap: on
line diff
--- a/graal/com.oracle.graal.asm.amd64/src/com/oracle/graal/asm/amd64/AMD64Assembler.java	Mon Mar 11 11:25:00 2013 +0100
+++ b/graal/com.oracle.graal.asm.amd64/src/com/oracle/graal/asm/amd64/AMD64Assembler.java	Mon Mar 11 12:07:28 2013 +0100
@@ -439,7 +439,7 @@
     }
 
     public final void bsfq(Register dst, AMD64Address src) {
-        emitByte(Prefix.REXW);
+        prefixq(src, dst);
         emitByte(0x0F);
         emitByte(0xBC);
         emitOperandHelper(dst, src);
@@ -453,7 +453,7 @@
     }
 
     public final void bsrq(Register dst, AMD64Address src) {
-        emitByte(Prefix.REXW);
+        prefixq(src, dst);
         emitByte(0x0F);
         emitByte(0xBD);
         emitOperandHelper(dst, src);
@@ -539,6 +539,15 @@
         }
     }
 
+    public final void cvtsd2ss(Register dst, AMD64Address src) {
+        assert dst.isFpu();
+        emitByte(0xF2);
+        prefix(src, dst);
+        emitByte(0x0F);
+        emitByte(0x5A);
+        emitOperandHelper(dst, src);
+    }
+
     public final void cvtsd2ss(Register dst, Register src) {
         assert dst.isFpu();
         assert src.isFpu();
@@ -549,6 +558,15 @@
         emitByte(0xC0 | encode);
     }
 
+    public final void cvtsi2sdl(Register dst, AMD64Address src) {
+        assert dst.isFpu();
+        emitByte(0xF2);
+        prefix(src, dst);
+        emitByte(0x0F);
+        emitByte(0x2A);
+        emitOperandHelper(dst, src);
+    }
+
     public final void cvtsi2sdl(Register dst, Register src) {
         assert dst.isFpu();
         emitByte(0xF2);
@@ -558,6 +576,15 @@
         emitByte(0xC0 | encode);
     }
 
+    public final void cvtsi2ssl(Register dst, AMD64Address src) {
+        assert dst.isFpu();
+        emitByte(0xF3);
+        prefix(src, dst);
+        emitByte(0x0F);
+        emitByte(0x2A);
+        emitOperandHelper(dst, src);
+    }
+
     public final void cvtsi2ssl(Register dst, Register src) {
         assert dst.isFpu();
         emitByte(0xF3);
@@ -567,6 +594,15 @@
         emitByte(0xC0 | encode);
     }
 
+    public final void cvtss2sd(Register dst, AMD64Address src) {
+        assert dst.isFpu();
+        emitByte(0xF3);
+        prefix(src, dst);
+        emitByte(0x0F);
+        emitByte(0x5A);
+        emitOperandHelper(dst, src);
+    }
+
     public final void cvtss2sd(Register dst, Register src) {
         assert dst.isFpu();
         assert src.isFpu();
@@ -577,6 +613,14 @@
         emitByte(0xC0 | encode);
     }
 
+    public final void cvttsd2sil(Register dst, AMD64Address src) {
+        emitByte(0xF2);
+        prefix(src, dst);
+        emitByte(0x0F);
+        emitByte(0x2C);
+        emitOperandHelper(dst, src);
+    }
+
     public final void cvttsd2sil(Register dst, Register src) {
         assert src.isFpu();
         emitByte(0xF2);
@@ -586,6 +630,14 @@
         emitByte(0xC0 | encode);
     }
 
+    public final void cvttss2sil(Register dst, AMD64Address src) {
+        emitByte(0xF3);
+        prefix(src, dst);
+        emitByte(0x0F);
+        emitByte(0x2C);
+        emitOperandHelper(dst, src);
+    }
+
     public final void cvttss2sil(Register dst, Register src) {
         assert src.isFpu();
         emitByte(0xF3);
@@ -1055,6 +1107,13 @@
         emitByte(0xC0 | encode);
     }
 
+    public final void movsxw(Register dst, AMD64Address src) {
+        prefix(src, dst);
+        emitByte(0x0F);
+        emitByte(0xBF);
+        emitOperandHelper(dst, src);
+    }
+
     public final void movw(AMD64Address dst, int imm16) {
         emitByte(0x66); // switch to 16-bit mode
         prefix(dst);
@@ -1954,6 +2013,15 @@
         emitOperandHelper(reg, adr);
     }
 
+    public final void cvtsi2sdq(Register dst, AMD64Address src) {
+        assert dst.isFpu();
+        emitByte(0xF2);
+        prefixq(src, dst);
+        emitByte(0x0F);
+        emitByte(0x2A);
+        emitOperandHelper(dst, src);
+    }
+
     public final void cvtsi2sdq(Register dst, Register src) {
         assert dst.isFpu();
         emitByte(0xF2);
@@ -1963,6 +2031,15 @@
         emitByte(0xC0 | encode);
     }
 
+    public final void cvtsi2ssq(Register dst, AMD64Address src) {
+        assert dst.isFpu();
+        emitByte(0xF3);
+        prefixq(src, dst);
+        emitByte(0x0F);
+        emitByte(0x2A);
+        emitOperandHelper(dst, src);
+    }
+
     public final void cvtsi2ssq(Register dst, Register src) {
         assert dst.isFpu();
         emitByte(0xF3);
@@ -1972,6 +2049,14 @@
         emitByte(0xC0 | encode);
     }
 
+    public final void cvttsd2siq(Register dst, AMD64Address src) {
+        emitByte(0xF2);
+        prefixq(src, dst);
+        emitByte(0x0F);
+        emitByte(0x2C);
+        emitOperandHelper(dst, src);
+    }
+
     public final void cvttsd2siq(Register dst, Register src) {
         assert src.isFpu();
         emitByte(0xF2);
@@ -1981,6 +2066,14 @@
         emitByte(0xC0 | encode);
     }
 
+    public final void cvttss2siq(Register dst, AMD64Address src) {
+        emitByte(0xF3);
+        prefixq(src, dst);
+        emitByte(0x0F);
+        emitByte(0x2C);
+        emitOperandHelper(dst, src);
+    }
+
     public final void cvttss2siq(Register dst, Register src) {
         assert src.isFpu();
         emitByte(0xF3);
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/graal/com.oracle.graal.compiler.amd64.test/src/com/oracle/graal/compiler/amd64/test/AMD64AllocatorTest.java	Mon Mar 11 12:07:28 2013 +0100
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2013, Oracle and/or its affiliates. All rights reserved.
+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+ *
+ * This code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 only, as
+ * published by the Free Software Foundation.
+ *
+ * This code is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * version 2 for more details (a copy is included in the LICENSE file that
+ * accompanied this code).
+ *
+ * You should have received a copy of the GNU General Public License version
+ * 2 along with this work; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
+ * or visit www.oracle.com if you need additional information or have any
+ * questions.
+ */
+package com.oracle.graal.compiler.amd64.test;
+
+import org.junit.*;
+
+import com.oracle.graal.compiler.test.backend.*;
+
+public class AMD64AllocatorTest extends AllocatorTest {
+
+    @Test
+    public void test1() {
+        test("test1snippet", 2, 1, 0);
+    }
+
+    public static long test1snippet(long x) {
+        return x + 5;
+    }
+
+    @Ignore
+    @Test
+    public void test2() {
+        test("test2snippet", 2, 0, 0);
+    }
+
+    public static long test2snippet(long x) {
+        return x * 5;
+    }
+
+    @Ignore
+    @Test
+    public void test3() {
+        test("test3snippet", 4, 1, 0);
+    }
+
+    public static long test3snippet(long x) {
+        return x / 3 + x % 3;
+    }
+
+}
--- a/graal/com.oracle.graal.compiler.test/src/com/oracle/graal/compiler/test/backend/AllocatorTest.java	Mon Mar 11 11:25:00 2013 +0100
+++ b/graal/com.oracle.graal.compiler.test/src/com/oracle/graal/compiler/test/backend/AllocatorTest.java	Mon Mar 11 12:07:28 2013 +0100
@@ -41,36 +41,7 @@
 
 public class AllocatorTest extends GraalCompilerTest {
 
-    @Test
-    public void test1() {
-        test("test1snippet", 2, 1, 0);
-    }
-
-    public static long test1snippet(long x) {
-        return x + 5;
-    }
-
-    @Ignore
-    @Test
-    public void test2() {
-        test("test2snippet", 2, 0, 0);
-    }
-
-    public static long test2snippet(long x) {
-        return x * 5;
-    }
-
-    @Ignore
-    @Test
-    public void test3() {
-        test("test3snippet", 4, 1, 0);
-    }
-
-    public static long test3snippet(long x) {
-        return x / 3 + x % 3;
-    }
-
-    private void test(String snippet, final int expectedRegisters, final int expectedRegRegMoves, final int expectedSpillMoves) {
+    protected void test(String snippet, final int expectedRegisters, final int expectedRegRegMoves, final int expectedSpillMoves) {
         final StructuredGraph graph = parse(snippet);
         Debug.scope("AllocatorTest", new Object[]{graph, graph.method(), backend.target}, new Runnable() {
 
@@ -91,7 +62,7 @@
         });
     }
 
-    class RegisterStats {
+    private class RegisterStats {
 
         public final LIR lir;
         public HashSet<Register> registers = new HashSet<>();
--- a/graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64Arithmetic.java	Mon Mar 11 11:25:00 2013 +0100
+++ b/graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64Arithmetic.java	Mon Mar 11 12:07:28 2013 +0100
@@ -58,7 +58,7 @@
     public static class Unary2Op extends AMD64LIRInstruction {
         @Opcode private final AMD64Arithmetic opcode;
         @Def({REG}) protected AllocatableValue result;
-        @Use({REG}) protected AllocatableValue x;
+        @Use({REG, STACK}) protected AllocatableValue x;
 
         public Unary2Op(AMD64Arithmetic opcode, AllocatableValue result, AllocatableValue x) {
             this.opcode = opcode;
@@ -455,6 +455,33 @@
                 case DSUB: masm.subsd(asDoubleReg(dst), (AMD64Address) tasm.asDoubleAddr(src)); break;
                 case DMUL: masm.mulsd(asDoubleReg(dst), (AMD64Address) tasm.asDoubleAddr(src)); break;
                 case DDIV: masm.divsd(asDoubleReg(dst), (AMD64Address) tasm.asDoubleAddr(src)); break;
+
+                case I2B: masm.movsxb(asIntReg(dst), (AMD64Address) tasm.asIntAddr(src)); break;
+                case I2S: masm.movsxw(asIntReg(dst), (AMD64Address) tasm.asIntAddr(src)); break;
+                case I2L: masm.movslq(asLongReg(dst), (AMD64Address) tasm.asIntAddr(src)); break;
+                case F2D: masm.cvtss2sd(asDoubleReg(dst), (AMD64Address) tasm.asFloatAddr(src)); break;
+                case D2F: masm.cvtsd2ss(asFloatReg(dst), (AMD64Address) tasm.asDoubleAddr(src)); break;
+                case I2F: masm.cvtsi2ssl(asFloatReg(dst), (AMD64Address) tasm.asIntAddr(src)); break;
+                case I2D: masm.cvtsi2sdl(asDoubleReg(dst), (AMD64Address) tasm.asIntAddr(src)); break;
+                case L2F: masm.cvtsi2ssq(asFloatReg(dst), (AMD64Address) tasm.asLongAddr(src)); break;
+                case L2D: masm.cvtsi2sdq(asDoubleReg(dst), (AMD64Address) tasm.asLongAddr(src)); break;
+                case F2I:
+                    masm.cvttss2sil(asIntReg(dst), (AMD64Address) tasm.asFloatAddr(src));
+                    break;
+                case D2I:
+                    masm.cvttsd2sil(asIntReg(dst), (AMD64Address) tasm.asDoubleAddr(src));
+                    break;
+                case F2L:
+                    masm.cvttss2siq(asLongReg(dst), (AMD64Address) tasm.asFloatAddr(src));
+                    break;
+                case D2L:
+                    masm.cvttsd2siq(asLongReg(dst), (AMD64Address) tasm.asDoubleAddr(src));
+                    break;
+                case MOV_I2F: masm.movss(asFloatReg(dst), (AMD64Address) tasm.asIntAddr(src)); break;
+                case MOV_L2D: masm.movsd(asDoubleReg(dst), (AMD64Address) tasm.asLongAddr(src)); break;
+                case MOV_F2I: masm.movl(asIntReg(dst), (AMD64Address) tasm.asFloatAddr(src)); break;
+                case MOV_D2L: masm.movq(asLongReg(dst), (AMD64Address) tasm.asDoubleAddr(src)); break;
+
                 default:   throw GraalInternalError.shouldNotReachHere();
             }
         }
--- a/graal/com.oracle.graal.lir/src/com/oracle/graal/lir/LIRIntrospection.java	Mon Mar 11 11:25:00 2013 +0100
+++ b/graal/com.oracle.graal.lir/src/com/oracle/graal/lir/LIRIntrospection.java	Mon Mar 11 12:07:28 2013 +0100
@@ -22,11 +22,14 @@
  */
 package com.oracle.graal.lir;
 
+import static com.oracle.graal.lir.LIRInstruction.OperandFlag.*;
+
 import java.lang.annotation.*;
 import java.lang.reflect.*;
 import java.util.*;
 import java.util.Map.Entry;
 
+import com.oracle.graal.api.code.*;
 import com.oracle.graal.api.meta.*;
 import com.oracle.graal.graph.*;
 import com.oracle.graal.lir.LIRInstruction.OperandFlag;
@@ -37,6 +40,8 @@
 
     private static final Class<Value> VALUE_CLASS = Value.class;
     private static final Class<Constant> CONSTANT_CLASS = Constant.class;
+    private static final Class<RegisterValue> REGISTER_VALUE_CLASS = RegisterValue.class;
+    private static final Class<StackSlot> STACK_SLOT_CLASS = StackSlot.class;
     private static final Class<Value[]> VALUE_ARRAY_CLASS = Value[].class;
 
     public LIRIntrospection(Class<?> clazz) {
@@ -82,11 +87,15 @@
                 OperandModeAnnotation annotation = getOperandModeAnnotation(field);
                 assert annotation != null : "Field must have operand mode annotation: " + field;
                 annotation.scalarOffsets.add(offset);
+                EnumSet<OperandFlag> flags = getFlags(field);
+                assert verifyFlags(field, type, flags);
                 annotation.flags.put(offset, getFlags(field));
             } else if (VALUE_ARRAY_CLASS.isAssignableFrom(type)) {
                 OperandModeAnnotation annotation = getOperandModeAnnotation(field);
                 assert annotation != null : "Field must have operand mode annotation: " + field;
                 annotation.arrayOffsets.add(offset);
+                EnumSet<OperandFlag> flags = getFlags(field);
+                assert verifyFlags(field, type.getComponentType(), flags);
                 annotation.flags.put(offset, getFlags(field));
             } else {
                 assert getOperandModeAnnotation(field) == null : "Field must not have operand mode annotation: " + field;
@@ -94,6 +103,19 @@
                 dataOffsets.add(offset);
             }
         }
+
+        private static boolean verifyFlags(Field field, Class<?> type, EnumSet<OperandFlag> flags) {
+            if (flags.contains(REG)) {
+                assert type.isAssignableFrom(REGISTER_VALUE_CLASS) : "Cannot assign RegisterValue to field with REG flag:" + field;
+            }
+            if (flags.contains(STACK)) {
+                assert type.isAssignableFrom(STACK_SLOT_CLASS) : "Cannot assign StackSlot to field with STACK flag:" + field;
+            }
+            if (flags.contains(CONST)) {
+                assert type.isAssignableFrom(CONSTANT_CLASS) : "Cannot assign Constant to field with CONST flag:" + field;
+            }
+            return true;
+        }
     }
 
     protected static void forEach(Object obj, int directCount, long[] offsets, OperandMode mode, EnumSet<OperandFlag>[] flags, ValueProcedure proc) {
--- a/mx/projects	Mon Mar 11 11:25:00 2013 +0100
+++ b/mx/projects	Mon Mar 11 12:07:28 2013 +0100
@@ -238,6 +238,13 @@
 project@com.oracle.graal.compiler.amd64@checkstyle=com.oracle.graal.graph
 project@com.oracle.graal.compiler.amd64@javaCompliance=1.7
 
+# graal.compiler.amd64.test
+project@com.oracle.graal.compiler.amd64.test@subDir=graal
+project@com.oracle.graal.compiler.amd64.test@sourceDirs=src
+project@com.oracle.graal.compiler.amd64.test@dependencies=com.oracle.graal.compiler.test
+project@com.oracle.graal.compiler.amd64.test@checkstyle=com.oracle.graal.graph
+project@com.oracle.graal.compiler.amd64.test@javaCompliance=1.7
+
 # graal.compiler.ptx
 project@com.oracle.graal.compiler.ptx@subDir=graal
 project@com.oracle.graal.compiler.ptx@sourceDirs=src