Mercurial > hg > truffle
changeset 17167:b8f54c5ec73a
Merge
| author | Stefan Anzinger <stefan.anzinger@oracle.com> |
|---|---|
| date | Fri, 19 Sep 2014 09:27:01 -0700 |
| parents | 9df38e5fbed6 (diff) 4a955509b98a (current diff) |
| children | 65c75f0bfc7b |
| files | src/share/vm/graal/graalRuntime.cpp |
| diffstat | 4 files changed, 51 insertions(+), 60 deletions(-) [+] |
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--- a/graal/com.oracle.graal.asm.sparc/src/com/oracle/graal/asm/sparc/SPARCAssembler.java Fri Sep 19 14:29:28 2014 +0200 +++ b/graal/com.oracle.graal.asm.sparc/src/com/oracle/graal/asm/sparc/SPARCAssembler.java Fri Sep 19 09:27:01 2014 -0700 @@ -655,16 +655,17 @@ public void setDisp10(int disp10) { this.disp10 = disp10 >> 2; + assert isSimm10(this.disp10) : this.disp10; } public void emit(SPARCAssembler masm) { assert masm.hasFeature(CPUFeature.CBCOND); if (label != null) { - final int pos = label.isBound() ? label.position() : patchUnbound(masm, label); if (label.isBound()) { - final int disp = pos - masm.position(); + final int disp = label.position() - masm.position(); setDisp10(disp); } else { + patchUnbound(masm, label); setDisp10(0); } } @@ -685,7 +686,12 @@ int d10Split = 0; d10Split |= (disp10 & 0b11_0000_0000) << D10HI_SHIFT - 8; d10Split |= (disp10 & 0b00_1111_1111) << D10LO_SHIFT; - return super.getInstructionBits() | 1 << 28 | cSplit | cc2 << CC2_SHIFT | d10Split | rs1 << RS1_SHIFT | i << I_SHIFT | regOrImmediate << RS2_SHIFT; + int bits = super.getInstructionBits() | 1 << 28 | cSplit | cc2 << CC2_SHIFT | d10Split | rs1 << RS1_SHIFT | i << I_SHIFT | (regOrImmediate & 0b1_1111) << RS2_SHIFT; + int hibits = (bits & 0xFF000000); + if (hibits == 0xFF000000 || hibits == 0) { + throw GraalInternalError.shouldNotReachHere(); + } + return bits; } public static Fmt00e read(SPARCAssembler masm, int pos) { @@ -707,9 +713,12 @@ final int rs1 = (inst & RS1_MASK) >> RS1_SHIFT; final int i = (inst & I_MASK) >> I_SHIFT; final int d10lo = (inst & D10LO_MASK) >> D10LO_SHIFT; - final int regOrImmediate = (inst & RS2_MASK) >> RS2_SHIFT; + int regOrImmediate = (inst & RS2_MASK) >> RS2_SHIFT; // @formatter:on - + if (i == 1) { // if immediate, we do sign extend + int shiftcnt = 31 - 4; + regOrImmediate = (regOrImmediate << shiftcnt) >> shiftcnt; + } int c = chi << 3 | clo; assert (d10lo & ~((1 << 8) - 1)) == 0; @@ -1644,7 +1653,7 @@ Fandd(0b0_0111_0000, "fandd"), Fands(0b0_0111_0001, "fands"), Fxord(0b0_0110_1100, "fxord"), - Fxors(0b0_0110_1101, "fxord"), + Fxors(0b0_0110_1101, "fxors"), // end VIS1 // start VIS2 @@ -1884,34 +1893,44 @@ // for integers Never(0, "never"), - Equal(1, "equal"), + Equal(1, "equal", true), Zero(1, "zero"), - LessEqual(2, "lessEqual"), - Less(3, "less"), - LessEqualUnsigned(4, "lessEqualUnsigned"), - LessUnsigned(5, "lessUnsigned"), + LessEqual(2, "lessEqual", true), + Less(3, "less", true), + LessEqualUnsigned(4, "lessEqualUnsigned", true), + LessUnsigned(5, "lessUnsigned", true), CarrySet(5, "carrySet"), - Negative(6, "negative"), - OverflowSet(7, "overflowSet"), + Negative(6, "negative", true), + OverflowSet(7, "overflowSet", true), Always(8, "always"), - NotEqual(9, "notEqual"), + NotEqual(9, "notEqual", true), NotZero(9, "notZero"), - Greater(10, "greater"), - GreaterEqual(11, "greaterEqual"), - GreaterUnsigned(12, "greaterUnsigned"), - GreaterEqualUnsigned(13, "greaterEqualUnsigned"), + Greater(10, "greater", true), + GreaterEqual(11, "greaterEqual", true), + GreaterUnsigned(12, "greaterUnsigned", true), + GreaterEqualUnsigned(13, "greaterEqualUnsigned", true), CarryClear(13, "carryClear"), - Positive(14, "positive"), - OverflowClear(15, "overflowClear"); + Positive(14, "positive", true), + OverflowClear(15, "overflowClear", true); // @formatter:on private final int value; private final String operator; + private boolean forCBcond = false; private ConditionFlag(int value, String op) { + this(value, op, false); + } + + private ConditionFlag(int value, String op, boolean cbcond) { this.value = value; this.operator = op; + this.forCBcond = cbcond; + } + + public boolean isCBCond() { + return forCBcond; } public int getValue() { @@ -2046,6 +2065,10 @@ return minSimm(nbits) <= imm && imm <= maxSimm(nbits); } + public static boolean isSimm10(long imm) { + return isSimm(imm, 10); + } + public static boolean isSimm11(int imm) { return isSimm(imm, 11); } @@ -3307,7 +3330,7 @@ public Fzeros(Register dst) { /* VIS1 only */ - super(Ops.ArithOp.getValue(), Op3s.Fpop1.getValue(), Opfs.Fzeros.getValue(), 0, dst.encoding()); + super(Ops.ArithOp.getValue(), Op3s.Impdep1.getValue(), Opfs.Fzeros.getValue(), 0, dst.encoding()); assert isSingleFloatRegister(dst); } } @@ -3316,7 +3339,7 @@ public Fzerod(Register dst) { /* VIS1 only */ - super(Ops.ArithOp.getValue(), Op3s.Fpop1.getValue(), Opfs.Fzerod.getValue(), 0, dst.encoding()); + super(Ops.ArithOp.getValue(), Op3s.Impdep1.getValue(), Opfs.Fzerod.getValue(), 0, dst.encoding()); assert isDoubleFloatRegister(dst); } }
--- a/graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCMove.java Fri Sep 19 14:29:28 2014 +0200 +++ b/graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCMove.java Fri Sep 19 09:27:01 2014 -0700 @@ -27,47 +27,15 @@ import static com.oracle.graal.asm.sparc.SPARCAssembler.*; import static com.oracle.graal.lir.LIRInstruction.OperandFlag.*; import static com.oracle.graal.sparc.SPARC.*; +import static com.oracle.graal.asm.sparc.SPARCMacroAssembler.*; +import static com.oracle.graal.lir.StandardOp.*; import com.oracle.graal.api.code.CompilationResult.RawData; import com.oracle.graal.api.code.*; import com.oracle.graal.api.meta.*; import com.oracle.graal.asm.sparc.*; -import com.oracle.graal.asm.sparc.SPARCAssembler.Add; -import com.oracle.graal.asm.sparc.SPARCAssembler.Fmovd; -import com.oracle.graal.asm.sparc.SPARCAssembler.Fmovs; -import com.oracle.graal.asm.sparc.SPARCAssembler.Fxord; -import com.oracle.graal.asm.sparc.SPARCAssembler.Fxors; -import com.oracle.graal.asm.sparc.SPARCAssembler.Lddf; -import com.oracle.graal.asm.sparc.SPARCAssembler.Ldf; -import com.oracle.graal.asm.sparc.SPARCAssembler.Ldsb; -import com.oracle.graal.asm.sparc.SPARCAssembler.Ldsh; -import com.oracle.graal.asm.sparc.SPARCAssembler.Ldsw; -import com.oracle.graal.asm.sparc.SPARCAssembler.Lduh; -import com.oracle.graal.asm.sparc.SPARCAssembler.Ldx; -import com.oracle.graal.asm.sparc.SPARCAssembler.Membar; -import com.oracle.graal.asm.sparc.SPARCAssembler.Movdtox; -import com.oracle.graal.asm.sparc.SPARCAssembler.Movstosw; -import com.oracle.graal.asm.sparc.SPARCAssembler.Movstouw; -import com.oracle.graal.asm.sparc.SPARCAssembler.Movwtos; -import com.oracle.graal.asm.sparc.SPARCAssembler.Movxtod; -import com.oracle.graal.asm.sparc.SPARCAssembler.Or; -import com.oracle.graal.asm.sparc.SPARCAssembler.Rdpc; -import com.oracle.graal.asm.sparc.SPARCAssembler.Stb; -import com.oracle.graal.asm.sparc.SPARCAssembler.Stdf; -import com.oracle.graal.asm.sparc.SPARCAssembler.Stf; -import com.oracle.graal.asm.sparc.SPARCAssembler.Sth; -import com.oracle.graal.asm.sparc.SPARCAssembler.Stw; -import com.oracle.graal.asm.sparc.SPARCAssembler.Stx; -import com.oracle.graal.asm.sparc.SPARCMacroAssembler.Cas; -import com.oracle.graal.asm.sparc.SPARCMacroAssembler.Casx; -import com.oracle.graal.asm.sparc.SPARCMacroAssembler.Clr; -import com.oracle.graal.asm.sparc.SPARCMacroAssembler.Mov; -import com.oracle.graal.asm.sparc.SPARCMacroAssembler.Setx; import com.oracle.graal.compiler.common.*; import com.oracle.graal.lir.*; -import com.oracle.graal.lir.StandardOp.ImplicitNullCheck; -import com.oracle.graal.lir.StandardOp.MoveOp; -import com.oracle.graal.lir.StandardOp.NullCheck; import com.oracle.graal.lir.asm.*; import com.oracle.graal.sparc.*; import com.oracle.graal.sparc.SPARC.CPUFeature; @@ -766,7 +734,7 @@ float constant = input.asFloat(); int constantBits = java.lang.Float.floatToIntBits(constant); if (constantBits == 0) { - new Fxors(asFloatReg(result), asFloatReg(result), asFloatReg(result)).emit(masm); + new Fzeros(asFloatReg(result)).emit(masm); } else { if (hasVIS3) { if (isSimm13(constantBits)) { @@ -790,7 +758,7 @@ double constant = input.asDouble(); long constantBits = java.lang.Double.doubleToLongBits(constant); if (constantBits == 0) { - new Fxord(asDoubleReg(result), asDoubleReg(result), asDoubleReg(result)).emit(masm); + new Fzerod(asDoubleReg(result)).emit(masm); } else { if (hasVIS3) { if (isSimm13(constantBits)) {
--- a/src/share/vm/compiler/compileBroker.cpp Fri Sep 19 14:29:28 2014 +0200 +++ b/src/share/vm/compiler/compileBroker.cpp Fri Sep 19 09:27:01 2014 -0700 @@ -812,7 +812,7 @@ if (FLAG_IS_DEFAULT(GraalThreads)) { if (!TieredCompilation && FLAG_IS_DEFAULT(BootstrapGraal) || BootstrapGraal) { // Graal will bootstrap so give it more threads - c2_count = os::active_processor_count(); + c2_count = MIN2(32, os::active_processor_count()); } } else { c2_count = GraalThreads;