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changeset 19673:4be296f6eeac

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[SPARC] Change part of the fpop assembler
author Stefan Anzinger <stefan.anzinger@oracle.com>
date Fri, 27 Feb 2015 13:55:38 +0100
parents b1b887938753
children 32a5dd091f5f
files graal/com.oracle.graal.asm.sparc/src/com/oracle/graal/asm/sparc/SPARCAssembler.java graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCArithmetic.java graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCMove.java
diffstat 3 files changed, 51 insertions(+), 177 deletions(-) [+]
line wrap: on
line diff
--- a/graal/com.oracle.graal.asm.sparc/src/com/oracle/graal/asm/sparc/SPARCAssembler.java	Fri Feb 27 13:23:52 2015 +0100
+++ b/graal/com.oracle.graal.asm.sparc/src/com/oracle/graal/asm/sparc/SPARCAssembler.java	Fri Feb 27 13:55:38 2015 +0100
@@ -88,35 +88,6 @@
     protected static final int D10LO_SHIFT = 5;
     protected static final int D10HI_SHIFT = 19;
 
-    public static class Fmt3n {
-        private int op;
-        private int op3;
-        private int opf;
-        private int rs2;
-        private int rd;
-
-        public Fmt3n(int op, int op3, int opf, int rs2, int rd) {
-            this.op = op;
-            this.op3 = op3;
-            this.opf = opf;
-            this.rs2 = rs2;
-            this.rd = rd;
-        }
-
-        public void emit(SPARCAssembler masm) {
-            verify();
-            masm.emitInt(op << 30 | rd << 25 | op3 << 19 | opf << 5 | rs2);
-        }
-
-        public void verify() {
-            assert op == 2 || op == 3;
-            assert op3 >= 0 && op3 < 0x40;
-            assert opf >= 0 && opf < 0x200;
-            assert rs2 >= 0 && rs2 < 0x20;
-            assert rd >= 0 && rd < 0x20;
-        }
-    }
-
     public static class Fmt3p {
 
         private int op;
@@ -1980,27 +1951,6 @@
         }
     }
 
-    public static class Cmask8 extends Fmt3n {
-
-        public Cmask8(Register src2) {
-            super(Ops.ArithOp.getValue(), Op3s.Impdep1.getValue(), Opfs.Cmask8.getValue(), src2.encoding(), 0);
-        }
-    }
-
-    public static class Cmask16 extends Fmt3n {
-
-        public Cmask16(Register src2) {
-            super(Ops.ArithOp.getValue(), Op3s.Impdep1.getValue(), Opfs.Cmask16.getValue(), src2.encoding(), 0);
-        }
-    }
-
-    public static class Cmask32 extends Fmt3n {
-
-        public Cmask32(Register src2) {
-            super(Ops.ArithOp.getValue(), Op3s.Impdep1.getValue(), Opfs.Cmask32.getValue(), src2.encoding(), 0);
-        }
-    }
-
     public static class Crc32c extends Fmt3p {
 
         public Crc32c(Register src1, Register src2, Register dst) {
@@ -2343,22 +2293,17 @@
         }
     }
 
-    public static class Fnegs extends Fmt3n {
-
-        public Fnegs(Register src2, Register dst) {
-            super(Ops.ArithOp.getValue(), Op3s.Fpop1.getValue(), Opfs.Fnegs.getValue(), src2.encoding(), dst.encoding());
-            assert isSingleFloatRegister(src2);
-            assert isSingleFloatRegister(dst);
-        }
+    public void fnegs(Register rs2, Register rd) {
+        op3(Op3s.Fpop1, Opfs.Fnegs, null, rs2, rd);
     }
 
-    public static class Fnegd extends Fmt3n {
-
-        public Fnegd(Register src2, Register dst) {
-            super(Ops.ArithOp.getValue(), Op3s.Fpop1.getValue(), Opfs.Fnegd.getValue(), src2.encoding(), dst.encoding());
-            assert isDoubleFloatRegister(src2);
-            assert isDoubleFloatRegister(dst);
-        }
+    public void fnegd(Register rs2, Register rd) {
+        op3(Op3s.Fpop1, Opfs.Fnegd, null, rs2, rd);
+    }
+
+    private void op3(Op3s op3, Opfs opf, Register rs1, Register rs2, Register rd) {
+        int b = opf.value << 5 | (rs2 == null ? 0 : rs2.encoding);
+        fmt10(rd.encoding, op3.value, rs1 == null ? 0 : rs1.encoding, b);
     }
 
     public static class Fnhadds extends Fmt3p {
@@ -2460,88 +2405,48 @@
         }
     }
 
-    public static class Fstoi extends Fmt3n {
-
-        public Fstoi(Register src2, Register dst) {
-            super(Ops.ArithOp.getValue(), Op3s.Fpop1.getValue(), Opfs.Fstoi.getValue(), src2.encoding(), dst.encoding());
-            assert isSingleFloatRegister(dst);
-            assert isSingleFloatRegister(src2);
-        }
+    public void fstoi(Register rs2, Register rd) {
+        op3(Op3s.Fpop1, Opfs.Fstoi, null, rs2, rd);
     }
 
-    public static class Fstox extends Fmt3n {
-
-        public Fstox(Register src2, Register dst) {
-            super(Ops.ArithOp.getValue(), Op3s.Fpop1.getValue(), Opfs.Fstox.getValue(), src2.encoding(), dst.encoding());
-            assert isDoubleFloatRegister(dst);
-            assert isSingleFloatRegister(src2);
-        }
+    public void fstox(Register rs2, Register rd) {
+        op3(Op3s.Fpop1, Opfs.Fstox, null, rs2, rd);
     }
 
-    public static class Fdtox extends Fmt3n {
-
-        public Fdtox(Register src2, Register dst) {
-            super(Ops.ArithOp.getValue(), Op3s.Fpop1.getValue(), Opfs.Fdtox.getValue(), src2.encoding(), dst.encoding());
-            assert isDoubleFloatRegister(src2);
-            assert isDoubleFloatRegister(dst);
-        }
+    public void fdtox(Register rs2, Register rd) {
+        op3(Op3s.Fpop1, Opfs.Fdtox, null, rs2, rd);
     }
 
-    public static class Fstod extends Fmt3n {
-
-        public Fstod(Register src2, Register dst) {
-            super(Ops.ArithOp.getValue(), Op3s.Fpop1.getValue(), Opfs.Fstod.getValue(), src2.encoding(), dst.encoding());
-            assert isDoubleFloatRegister(dst);
-            assert isSingleFloatRegister(src2);
-        }
+    public void fstod(Register rs2, Register rd) {
+        op3(Op3s.Fpop1, Opfs.Fstod, null, rs2, rd);
+    }
+
+    public void fdtoi(Register rs2, Register rd) {
+        op3(Op3s.Fpop1, Opfs.Fdtoi, null, rs2, rd);
     }
 
-    /**
-     * Convert Double to 32-bit Integer.
-     */
-    public static class Fdtoi extends Fmt3n {
-
-        public Fdtoi(Register src2, Register dst) {
-            super(Ops.ArithOp.getValue(), Op3s.Fpop1.getValue(), Opfs.Fdtoi.getValue(), src2.encoding(), dst.encoding());
-            assert isDoubleFloatRegister(src2);
-            assert isSingleFloatRegister(dst);
-        }
+    public void fitos(Register rs2, Register rd) {
+        op3(Op3s.Fpop1, Opfs.Fitos, null, rs2, rd);
     }
 
-    public static class Fitos extends Fmt3n {
-
-        public Fitos(Register src2, Register dst) {
-            super(Ops.ArithOp.getValue(), Op3s.Fpop1.getValue(), Opfs.Fitos.getValue(), src2.encoding(), dst.encoding());
-            assert isSingleFloatRegister(src2);
-            assert isSingleFloatRegister(dst);
-        }
+    public void fitod(Register rs2, Register rd) {
+        op3(Op3s.Fpop1, Opfs.Fitod, null, rs2, rd);
+    }
+
+    public void fxtos(Register rs2, Register rd) {
+        op3(Op3s.Fpop1, Opfs.Fxtos, null, rs2, rd);
     }
 
-    public static class Fitod extends Fmt3n {
-
-        public Fitod(Register src2, Register dst) {
-            super(Ops.ArithOp.getValue(), Op3s.Fpop1.getValue(), Opfs.Fitod.getValue(), src2.encoding(), dst.encoding());
-            assert isSingleFloatRegister(src2);
-            assert isDoubleFloatRegister(dst);
-        }
+    public void fxtod(Register rs2, Register rd) {
+        op3(Op3s.Fpop1, Opfs.Fxtod, null, rs2, rd);
     }
 
-    public static class Fxtos extends Fmt3n {
-
-        public Fxtos(Register src2, Register dst) {
-            super(Ops.ArithOp.getValue(), Op3s.Fpop1.getValue(), Opfs.Fxtos.getValue(), src2.encoding(), dst.encoding());
-            assert isDoubleFloatRegister(src2);
-            assert isSingleFloatRegister(dst);
-        }
+    public void fzeros(Register rd) {
+        op3(Op3s.Impdep1, Opfs.Fzeros, null, null, rd);
     }
 
-    public static class Fxtod extends Fmt3n {
-
-        public Fxtod(Register src2, Register dst) {
-            super(Ops.ArithOp.getValue(), Op3s.Fpop1.getValue(), Opfs.Fxtod.getValue(), src2.encoding(), dst.encoding());
-            assert isDoubleFloatRegister(src2);
-            assert isDoubleFloatRegister(dst);
-        }
+    public void fzerod(Register rd) {
+        op3(Op3s.Impdep1, Opfs.Fzerod, null, null, rd);
     }
 
     /**
@@ -2765,24 +2670,6 @@
         }
     }
 
-    public static class Fzeros extends Fmt3n {
-
-        public Fzeros(Register dst) {
-            /* VIS1 only */
-            super(Ops.ArithOp.getValue(), Op3s.Impdep1.getValue(), Opfs.Fzeros.getValue(), 0, dst.encoding());
-            assert isSingleFloatRegister(dst);
-        }
-    }
-
-    public static class Fzerod extends Fmt3n {
-
-        public Fzerod(Register dst) {
-            /* VIS1 only */
-            super(Ops.ArithOp.getValue(), Op3s.Impdep1.getValue(), Opfs.Fzerod.getValue(), 0, dst.encoding());
-            assert isDoubleFloatRegister(dst);
-        }
-    }
-
     // @formatter:off
     /**
      * Instruction format for fcmp.
--- a/graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCArithmetic.java	Fri Feb 27 13:23:52 2015 +0100
+++ b/graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCArithmetic.java	Fri Feb 27 13:55:38 2015 +0100
@@ -45,23 +45,12 @@
 import com.oracle.graal.asm.sparc.SPARCAssembler.Fandd;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Fdivd;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Fdivs;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Fdtoi;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Fdtos;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Fdtox;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Fitod;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Fitos;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Fmuld;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Fmuls;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Fnegd;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Fnegs;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Fsmuld;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Fstod;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Fstoi;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Fstox;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Fsubd;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Fsubs;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Fxtod;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Fxtos;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Mulx;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Or;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Sdivx;
@@ -707,15 +696,15 @@
                 break;
             case L2D:
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Fxtod(asDoubleReg(src), asDoubleReg(dst)).emit(masm);
+                masm.fxtod(asDoubleReg(src), asDoubleReg(dst));
                 break;
             case L2F:
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Fxtos(asDoubleReg(src), asFloatReg(dst)).emit(masm);
+                masm.fxtos(asDoubleReg(src), asFloatReg(dst));
                 break;
             case I2D:
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Fitod(asFloatReg(src), asDoubleReg(dst)).emit(masm);
+                masm.fitod(asFloatReg(src), asDoubleReg(dst));
                 break;
             case I2L:
                 delaySlotLir.emitControlTransfer(crb, masm);
@@ -747,50 +736,50 @@
                 break;
             case I2F:
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Fitos(asFloatReg(src), asFloatReg(dst)).emit(masm);
+                masm.fitos(asFloatReg(src), asFloatReg(dst));
                 break;
             case F2D:
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Fstod(asFloatReg(src), asDoubleReg(dst)).emit(masm);
+                masm.fstod(asFloatReg(src), asDoubleReg(dst));
                 break;
             case F2L:
                 masm.fcmp(Fcc0, Fcmps, asFloatReg(src), asFloatReg(src));
                 masm.fbpcc(F_Ordered, ANNUL, notOrdered, Fcc0, PREDICT_TAKEN);
-                new Fstox(asFloatReg(src), asDoubleReg(dst)).emit(masm);
+                masm.fstox(asFloatReg(src), asDoubleReg(dst));
                 new Fsubd(asDoubleReg(dst), asDoubleReg(dst), asDoubleReg(dst)).emit(masm);
                 masm.bind(notOrdered);
                 break;
             case F2I:
                 masm.fcmp(Fcc0, Fcmps, asFloatReg(src), asFloatReg(src));
                 masm.fbpcc(F_Ordered, ANNUL, notOrdered, Fcc0, PREDICT_TAKEN);
-                new Fstoi(asFloatReg(src), asFloatReg(dst)).emit(masm);
-                new Fitos(asFloatReg(dst), asFloatReg(dst)).emit(masm);
+                masm.fstoi(asFloatReg(src), asFloatReg(dst));
+                masm.fitos(asFloatReg(dst), asFloatReg(dst));
                 new Fsubs(asFloatReg(dst), asFloatReg(dst), asFloatReg(dst)).emit(masm);
                 masm.bind(notOrdered);
                 break;
             case D2L:
                 masm.fcmp(Fcc0, Fcmpd, asDoubleReg(src), asDoubleReg(src));
                 masm.fbpcc(F_Ordered, ANNUL, notOrdered, Fcc0, PREDICT_TAKEN);
-                new Fdtox(asDoubleReg(src), asDoubleReg(dst)).emit(masm);
-                new Fxtod(asDoubleReg(dst), asDoubleReg(dst)).emit(masm);
+                masm.fdtox(asDoubleReg(src), asDoubleReg(dst));
+                masm.fxtod(asDoubleReg(dst), asDoubleReg(dst));
                 new Fsubd(asDoubleReg(dst), asDoubleReg(dst), asDoubleReg(dst)).emit(masm);
                 masm.bind(notOrdered);
                 break;
             case D2I:
                 masm.fcmp(Fcc0, Fcmpd, asDoubleReg(src), asDoubleReg(src));
                 masm.fbpcc(F_Ordered, ANNUL, notOrdered, Fcc0, PREDICT_TAKEN);
-                new Fdtoi(asDoubleReg(src), asFloatReg(dst)).emit(masm);
+                masm.fdtoi(asDoubleReg(src), asFloatReg(dst));
                 new Fsubs(asFloatReg(dst), asFloatReg(dst), asFloatReg(dst)).emit(masm);
-                new Fstoi(asFloatReg(dst), asFloatReg(dst)).emit(masm);
+                masm.fstoi(asFloatReg(dst), asFloatReg(dst));
                 masm.bind(notOrdered);
                 break;
             case FNEG:
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Fnegs(asFloatReg(src), asFloatReg(dst)).emit(masm);
+                masm.fnegs(asFloatReg(src), asFloatReg(dst));
                 break;
             case DNEG:
                 delaySlotLir.emitControlTransfer(crb, masm);
-                new Fnegd(asDoubleReg(src), asDoubleReg(dst)).emit(masm);
+                masm.fnegd(asDoubleReg(src), asDoubleReg(dst));
                 break;
             default:
                 throw GraalInternalError.shouldNotReachHere("missing: " + opcode);
--- a/graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCMove.java	Fri Feb 27 13:23:52 2015 +0100
+++ b/graal/com.oracle.graal.lir.sparc/src/com/oracle/graal/lir/sparc/SPARCMove.java	Fri Feb 27 13:55:38 2015 +0100
@@ -34,8 +34,6 @@
 import com.oracle.graal.asm.sparc.SPARCAssembler.Add;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Fmovd;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Fmovs;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Fzerod;
-import com.oracle.graal.asm.sparc.SPARCAssembler.Fzeros;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Lddf;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Ldf;
 import com.oracle.graal.asm.sparc.SPARCAssembler.Ldsb;
@@ -795,7 +793,7 @@
                     int constantBits = java.lang.Float.floatToIntBits(constant);
                     if (constantBits == 0) {
                         delaySlotLir.emitControlTransfer(crb, masm);
-                        new Fzeros(asFloatReg(result)).emit(masm);
+                        masm.fzeros(asFloatReg(result));
                     } else {
                         if (hasVIS3) {
                             if (isSimm13(constantBits)) {
@@ -822,7 +820,7 @@
                     long constantBits = java.lang.Double.doubleToLongBits(constant);
                     if (constantBits == 0) {
                         delaySlotLir.emitControlTransfer(crb, masm);
-                        new Fzerod(asDoubleReg(result)).emit(masm);
+                        masm.fzerod(asDoubleReg(result));
                     } else {
                         if (hasVIS3) {
                             if (isSimm13(constantBits)) {