Mercurial > hg > truffle
changeset 7910:748cb57f53cb
Cleanup Op1 in AMD64 backend.
author | Roland Schatz <roland.schatz@oracle.com> |
---|---|
date | Thu, 28 Feb 2013 16:41:44 +0100 |
parents | afb56ecdb083 |
children | 983f7bdb85ff 8fa2eed07f81 |
files | graal/com.oracle.graal.compiler.amd64/src/com/oracle/graal/compiler/amd64/AMD64LIRGenerator.java graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64Arithmetic.java |
diffstat | 2 files changed, 44 insertions(+), 42 deletions(-) [+] |
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--- a/graal/com.oracle.graal.compiler.amd64/src/com/oracle/graal/compiler/amd64/AMD64LIRGenerator.java Thu Feb 28 15:29:46 2013 +0100 +++ b/graal/com.oracle.graal.compiler.amd64/src/com/oracle/graal/compiler/amd64/AMD64LIRGenerator.java Thu Feb 28 16:41:44 2013 +0100 @@ -42,11 +42,11 @@ import com.oracle.graal.lir.StandardOp.JumpOp; import com.oracle.graal.lir.amd64.AMD64Arithmetic.DivOp; import com.oracle.graal.lir.amd64.AMD64Arithmetic.DivRemOp; -import com.oracle.graal.lir.amd64.AMD64Arithmetic.Op1Reg; -import com.oracle.graal.lir.amd64.AMD64Arithmetic.Op1Stack; import com.oracle.graal.lir.amd64.AMD64Arithmetic.Op2Reg; import com.oracle.graal.lir.amd64.AMD64Arithmetic.Op2Stack; import com.oracle.graal.lir.amd64.AMD64Arithmetic.ShiftOp; +import com.oracle.graal.lir.amd64.AMD64Arithmetic.Unary1Op; +import com.oracle.graal.lir.amd64.AMD64Arithmetic.Unary2Op; import com.oracle.graal.lir.amd64.*; import com.oracle.graal.lir.amd64.AMD64Call.DirectCallOp; import com.oracle.graal.lir.amd64.AMD64Call.IndirectCallOp; @@ -354,14 +354,15 @@ } @Override - public Variable emitNegate(Value input) { + public Variable emitNegate(Value inputVal) { + AllocatableValue input = asAllocatable(inputVal); Variable result = newVariable(input.getKind()); switch (input.getKind()) { case Int: - append(new Op1Stack(INEG, result, input)); + append(new Unary1Op(INEG, result, input)); break; case Long: - append(new Op1Stack(LNEG, result, input)); + append(new Unary1Op(LNEG, result, input)); break; case Float: append(new Op2Reg(FXOR, result, input, Constant.forFloat(Float.intBitsToFloat(0x80000000)))); @@ -676,61 +677,61 @@ Variable result = newVariable(opcode.to); switch (opcode) { case I2L: - append(new Op1Reg(I2L, result, input)); + append(new Unary2Op(I2L, result, input)); break; case L2I: - append(new Op1Stack(L2I, result, input)); + append(new Unary1Op(L2I, result, input)); break; case I2B: - append(new Op1Stack(I2B, result, input)); + append(new Unary2Op(I2B, result, input)); break; case I2C: - append(new Op1Stack(I2C, result, input)); + append(new Unary1Op(I2C, result, input)); break; case I2S: - append(new Op1Stack(I2S, result, input)); + append(new Unary2Op(I2S, result, input)); break; case F2D: - append(new Op1Reg(F2D, result, input)); + append(new Unary2Op(F2D, result, input)); break; case D2F: - append(new Op1Reg(D2F, result, input)); + append(new Unary2Op(D2F, result, input)); break; case I2F: - append(new Op1Reg(I2F, result, input)); + append(new Unary2Op(I2F, result, input)); break; case I2D: - append(new Op1Reg(I2D, result, input)); + append(new Unary2Op(I2D, result, input)); break; case F2I: - append(new Op1Reg(F2I, result, input)); + append(new Unary2Op(F2I, result, input)); break; case D2I: - append(new Op1Reg(D2I, result, input)); + append(new Unary2Op(D2I, result, input)); break; case L2F: - append(new Op1Reg(L2F, result, input)); + append(new Unary2Op(L2F, result, input)); break; case L2D: - append(new Op1Reg(L2D, result, input)); + append(new Unary2Op(L2D, result, input)); break; case F2L: - append(new Op1Reg(F2L, result, input)); + append(new Unary2Op(F2L, result, input)); break; case D2L: - append(new Op1Reg(D2L, result, input)); + append(new Unary2Op(D2L, result, input)); break; case MOV_I2F: - append(new Op1Reg(MOV_I2F, result, input)); + append(new Unary2Op(MOV_I2F, result, input)); break; case MOV_L2D: - append(new Op1Reg(MOV_L2D, result, input)); + append(new Unary2Op(MOV_L2D, result, input)); break; case MOV_F2I: - append(new Op1Reg(MOV_F2I, result, input)); + append(new Unary2Op(MOV_F2I, result, input)); break; case MOV_D2L: - append(new Op1Reg(MOV_D2L, result, input)); + append(new Unary2Op(MOV_D2L, result, input)); break; case UNSIGNED_I2L: // Instructions that move or generate 32-bit register values also set the upper 32
--- a/graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64Arithmetic.java Thu Feb 28 15:29:46 2013 +0100 +++ b/graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64Arithmetic.java Thu Feb 28 16:41:44 2013 +0100 @@ -26,10 +26,11 @@ import static com.oracle.graal.lir.LIRInstruction.OperandFlag.*; import com.oracle.graal.amd64.*; +import com.oracle.graal.api.code.*; import com.oracle.graal.api.meta.*; import com.oracle.graal.asm.*; +import com.oracle.graal.asm.amd64.AMD64Assembler.ConditionFlag; import com.oracle.graal.asm.amd64.*; -import com.oracle.graal.asm.amd64.AMD64Assembler.*; import com.oracle.graal.graph.*; import com.oracle.graal.lir.*; import com.oracle.graal.lir.asm.*; @@ -48,12 +49,12 @@ MOV_I2F, MOV_L2D, MOV_F2I, MOV_D2L; - public static class Op1Reg extends AMD64LIRInstruction { + public static class Unary2Op extends AMD64LIRInstruction { @Opcode private final AMD64Arithmetic opcode; - @Def({REG, HINT}) protected Value result; - @Use({REG}) protected Value x; + @Def({REG}) protected AllocatableValue result; + @Use({REG}) protected AllocatableValue x; - public Op1Reg(AMD64Arithmetic opcode, Value result, Value x) { + public Unary2Op(AMD64Arithmetic opcode, AllocatableValue result, AllocatableValue x) { this.opcode = opcode; this.result = result; this.x = x; @@ -65,12 +66,12 @@ } } - public static class Op1Stack extends AMD64LIRInstruction { + public static class Unary1Op extends AMD64LIRInstruction { @Opcode private final AMD64Arithmetic opcode; - @Def({REG, HINT}) protected Value result; - @Use({REG, STACK, CONST}) protected Value x; + @Def({REG, HINT}) protected AllocatableValue result; + @Use({REG, STACK}) protected AllocatableValue x; - public Op1Stack(AMD64Arithmetic opcode, Value result, Value x) { + public Unary1Op(AMD64Arithmetic opcode, AllocatableValue result, AllocatableValue x) { this.opcode = opcode; this.result = result; this.x = x; @@ -264,14 +265,12 @@ @SuppressWarnings("unused") - protected static void emit(TargetMethodAssembler tasm, AMD64MacroAssembler masm, AMD64Arithmetic opcode, Value result) { + protected static void emit(TargetMethodAssembler tasm, AMD64MacroAssembler masm, AMD64Arithmetic opcode, AllocatableValue result) { switch (opcode) { case INEG: masm.negl(asIntReg(result)); break; case LNEG: masm.negq(asLongReg(result)); break; case L2I: masm.andl(asIntReg(result), 0xFFFFFFFF); break; - case I2B: masm.signExtendByte(asIntReg(result)); break; case I2C: masm.andl(asIntReg(result), 0xFFFF); break; - case I2S: masm.signExtendShort(asIntReg(result)); break; default: throw GraalInternalError.shouldNotReachHere(); } } @@ -286,9 +285,9 @@ case IMUL: masm.imull(asIntReg(dst), asIntReg(src)); break; case IOR: masm.orl(asIntReg(dst), asIntReg(src)); break; case IXOR: masm.xorl(asIntReg(dst), asIntReg(src)); break; - case ISHL: masm.shll(asIntReg(dst)); break; - case ISHR: masm.sarl(asIntReg(dst)); break; - case IUSHR:masm.shrl(asIntReg(dst)); break; + case ISHL: assert asIntReg(src) == AMD64.rcx; masm.shll(asIntReg(dst)); break; + case ISHR: assert asIntReg(src) == AMD64.rcx; masm.sarl(asIntReg(dst)); break; + case IUSHR: assert asIntReg(src) == AMD64.rcx; masm.shrl(asIntReg(dst)); break; case LADD: masm.addq(asLongReg(dst), asLongReg(src)); break; case LSUB: masm.subq(asLongReg(dst), asLongReg(src)); break; @@ -296,9 +295,9 @@ case LAND: masm.andq(asLongReg(dst), asLongReg(src)); break; case LOR: masm.orq(asLongReg(dst), asLongReg(src)); break; case LXOR: masm.xorq(asLongReg(dst), asLongReg(src)); break; - case LSHL: masm.shlq(asLongReg(dst)); break; - case LSHR: masm.sarq(asLongReg(dst)); break; - case LUSHR:masm.shrq(asLongReg(dst)); break; + case LSHL: assert asIntReg(src) == AMD64.rcx; masm.shlq(asLongReg(dst)); break; + case LSHR: assert asIntReg(src) == AMD64.rcx; masm.sarq(asLongReg(dst)); break; + case LUSHR: assert asIntReg(src) == AMD64.rcx; masm.shrq(asLongReg(dst)); break; case FADD: masm.addss(asFloatReg(dst), asFloatReg(src)); break; case FSUB: masm.subss(asFloatReg(dst), asFloatReg(src)); break; @@ -316,6 +315,8 @@ case DOR: masm.orpd(asDoubleReg(dst), asDoubleReg(src)); break; case DXOR: masm.xorpd(asDoubleReg(dst), asDoubleReg(src)); break; + case I2B: masm.movsxb(asIntReg(dst), asIntReg(src)); break; + case I2S: masm.movsxw(asIntReg(dst), asIntReg(src)); break; case I2L: masm.movslq(asLongReg(dst), asIntReg(src)); break; case F2D: masm.cvtss2sd(asDoubleReg(dst), asFloatReg(src)); break; case D2F: masm.cvtsd2ss(asFloatReg(dst), asDoubleReg(src)); break;