Mercurial > hg > truffle
changeset 11004:87a6f2df28e2
8002160: Compilation issue with adlc using latest SunStudio compilers
Summary: modify declaration of 'swap' overloading; dodge optimizer bug in c1_LIR.cpp
Reviewed-by: kvn, jrose
| author | drchase |
|---|---|
| date | Mon, 17 Jun 2013 12:35:53 -0400 |
| parents | ac91879aa56f |
| children | 08d35fd1b599 |
| files | src/cpu/sparc/vm/macroAssembler_sparc.hpp src/cpu/sparc/vm/macroAssembler_sparc.inline.hpp src/share/vm/c1/c1_LIR.cpp |
| diffstat | 3 files changed, 13 insertions(+), 12 deletions(-) [+] |
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--- a/src/cpu/sparc/vm/macroAssembler_sparc.hpp Fri Jun 14 16:33:34 2013 -0700 +++ b/src/cpu/sparc/vm/macroAssembler_sparc.hpp Mon Jun 17 12:35:53 2013 -0400 @@ -1,5 +1,5 @@ /* - * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -963,7 +963,7 @@ inline void sub(Register s1, RegisterOrConstant s2, Register d, int offset = 0); using Assembler::swap; - inline void swap(Address& a, Register d, int offset = 0); + inline void swap(const Address& a, Register d, int offset = 0); // address pseudos: make these names unlike instruction names to avoid confusion inline intptr_t load_pc_address( Register reg, int bytes_to_skip );
--- a/src/cpu/sparc/vm/macroAssembler_sparc.inline.hpp Fri Jun 14 16:33:34 2013 -0700 +++ b/src/cpu/sparc/vm/macroAssembler_sparc.inline.hpp Mon Jun 17 12:35:53 2013 -0400 @@ -1,5 +1,5 @@ /* - * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -719,7 +719,7 @@ if (offset != 0) sub(d, offset, d); } -inline void MacroAssembler::swap(Address& a, Register d, int offset) { +inline void MacroAssembler::swap(const Address& a, Register d, int offset) { relocate(a.rspec(offset)); if (a.has_index()) { assert(offset == 0, ""); swap(a.base(), a.index(), d ); } else { swap(a.base(), a.disp() + offset, d); }
--- a/src/share/vm/c1/c1_LIR.cpp Fri Jun 14 16:33:34 2013 -0700 +++ b/src/share/vm/c1/c1_LIR.cpp Mon Jun 17 12:35:53 2013 -0400 @@ -201,23 +201,24 @@ #ifdef ASSERT if (!is_pointer() && !is_illegal()) { + OprKind kindfield = kind_field(); // Factored out because of compiler bug, see 8002160 switch (as_BasicType(type_field())) { case T_LONG: - assert((kind_field() == cpu_register || kind_field() == stack_value) && + assert((kindfield == cpu_register || kindfield == stack_value) && size_field() == double_size, "must match"); break; case T_FLOAT: // FP return values can be also in CPU registers on ARM and PPC (softfp ABI) - assert((kind_field() == fpu_register || kind_field() == stack_value - ARM_ONLY(|| kind_field() == cpu_register) - PPC_ONLY(|| kind_field() == cpu_register) ) && + assert((kindfield == fpu_register || kindfield == stack_value + ARM_ONLY(|| kindfield == cpu_register) + PPC_ONLY(|| kindfield == cpu_register) ) && size_field() == single_size, "must match"); break; case T_DOUBLE: // FP return values can be also in CPU registers on ARM and PPC (softfp ABI) - assert((kind_field() == fpu_register || kind_field() == stack_value - ARM_ONLY(|| kind_field() == cpu_register) - PPC_ONLY(|| kind_field() == cpu_register) ) && + assert((kindfield == fpu_register || kindfield == stack_value + ARM_ONLY(|| kindfield == cpu_register) + PPC_ONLY(|| kindfield == cpu_register) ) && size_field() == double_size, "must match"); break; case T_BOOLEAN: @@ -229,7 +230,7 @@ case T_OBJECT: case T_METADATA: case T_ARRAY: - assert((kind_field() == cpu_register || kind_field() == stack_value) && + assert((kindfield == cpu_register || kindfield == stack_value) && size_field() == single_size, "must match"); break;