Mercurial > hg > truffle
changeset 15277:87ce885d0b83
add rotate instructions and make the shift encodings more uniform
author | Tom Rodriguez <tom.rodriguez@oracle.com> |
---|---|
date | Tue, 22 Apr 2014 17:25:27 -0700 |
parents | c2f715edadec |
children | 3ef4196cf8e5 |
files | graal/com.oracle.graal.asm.amd64/src/com/oracle/graal/asm/amd64/AMD64Assembler.java |
diffstat | 1 files changed, 92 insertions(+), 6 deletions(-) [+] |
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--- a/graal/com.oracle.graal.asm.amd64/src/com/oracle/graal/asm/amd64/AMD64Assembler.java Tue Apr 22 17:25:24 2014 -0700 +++ b/graal/com.oracle.graal.asm.amd64/src/com/oracle/graal/asm/amd64/AMD64Assembler.java Tue Apr 22 17:25:27 2014 -0700 @@ -1647,9 +1647,14 @@ public final void shrl(Register dst, int imm8) { assert isShiftCount(imm8) : "illegal shift count"; int encode = prefixAndEncode(dst.encoding); - emitByte(0xC1); - emitByte(0xE8 | encode); - emitByte(imm8); + if (imm8 == 1) { + emitByte(0xD1); + emitByte(0xE8 | encode); + } else { + emitByte(0xC1); + emitByte(0xE8 | encode); + emitByte(imm8); + } } public final void shrl(Register dst) { @@ -1658,6 +1663,82 @@ emitByte(0xE8 | encode); } + public final void roll(Register dst, int imm8) { + assert isShiftCount(imm8) : "illegal shift count"; + int encode = prefixAndEncode(dst.encoding); + if (imm8 == 1) { + emitByte(0xD1); + emitByte(0xC0 | encode); + } else { + emitByte(0xC1); + emitByte(0xC0 | encode); + emitByte(imm8); + } + } + + public final void roll(Register dst) { + int encode = prefixAndEncode(dst.encoding); + emitByte(0xD3); + emitByte(0xC0 | encode); + } + + public final void rorl(Register dst, int imm8) { + assert isShiftCount(imm8) : "illegal shift count"; + int encode = prefixAndEncode(dst.encoding); + if (imm8 == 1) { + emitByte(0xD1); + emitByte(0xC8 | encode); + } else { + emitByte(0xC1); + emitByte(0xC8 | encode); + emitByte(imm8); + } + } + + public final void rorl(Register dst) { + int encode = prefixAndEncode(dst.encoding); + emitByte(0xD3); + emitByte(0xC8 | encode); + } + + public final void rolq(Register dst, int imm8) { + assert isShiftCount(imm8) : "illegal shift count"; + int encode = prefixqAndEncode(dst.encoding); + if (imm8 == 1) { + emitByte(0xD1); + emitByte(0xC0 | encode); + } else { + emitByte(0xC1); + emitByte(0xC0 | encode); + emitByte(imm8); + } + } + + public final void rolq(Register dst) { + int encode = prefixqAndEncode(dst.encoding); + emitByte(0xD3); + emitByte(0xC0 | encode); + } + + public final void rorq(Register dst, int imm8) { + assert isShiftCount(imm8) : "illegal shift count"; + int encode = prefixqAndEncode(dst.encoding); + if (imm8 == 1) { + emitByte(0xD1); + emitByte(0xC8 | encode); + } else { + emitByte(0xC1); + emitByte(0xC8 | encode); + emitByte(imm8); + } + } + + public final void rorq(Register dst) { + int encode = prefixqAndEncode(dst.encoding); + emitByte(0xD3); + emitByte(0xC8 | encode); + } + public final void sqrtsd(Register dst, AMD64Address src) { assert dst.getRegisterCategory() == AMD64.XMM; emitByte(0xF2); @@ -2442,9 +2523,14 @@ public final void shrq(Register dst, int imm8) { assert isShiftCount(imm8 >> 1) : "illegal shift count"; int encode = prefixqAndEncode(dst.encoding); - emitByte(0xC1); - emitByte(0xE8 | encode); - emitByte(imm8); + if (imm8 == 1) { + emitByte(0xD1); + emitByte(0xE8 | encode); + } else { + emitByte(0xC1); + emitByte(0xE8 | encode); + emitByte(imm8); + } } public final void shrq(Register dst) {