Mercurial > hg > truffle
changeset 8192:b1d5f203c57d
Allow STACK argument in conversion ops.
author | Roland Schatz <roland.schatz@oracle.com> |
---|---|
date | Mon, 11 Mar 2013 11:07:56 +0100 |
parents | 0e583eb213f1 |
children | 44f79360793e |
files | graal/com.oracle.graal.asm.amd64/src/com/oracle/graal/asm/amd64/AMD64Assembler.java graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64Arithmetic.java |
diffstat | 2 files changed, 121 insertions(+), 1 deletions(-) [+] |
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--- a/graal/com.oracle.graal.asm.amd64/src/com/oracle/graal/asm/amd64/AMD64Assembler.java Mon Mar 11 10:13:44 2013 +0100 +++ b/graal/com.oracle.graal.asm.amd64/src/com/oracle/graal/asm/amd64/AMD64Assembler.java Mon Mar 11 11:07:56 2013 +0100 @@ -539,6 +539,15 @@ } } + public final void cvtsd2ss(Register dst, AMD64Address src) { + assert dst.isFpu(); + emitByte(0xF2); + prefix(src, dst); + emitByte(0x0F); + emitByte(0x5A); + emitOperandHelper(dst, src); + } + public final void cvtsd2ss(Register dst, Register src) { assert dst.isFpu(); assert src.isFpu(); @@ -549,6 +558,15 @@ emitByte(0xC0 | encode); } + public final void cvtsi2sdl(Register dst, AMD64Address src) { + assert dst.isFpu(); + emitByte(0xF2); + prefix(src, dst); + emitByte(0x0F); + emitByte(0x2A); + emitOperandHelper(dst, src); + } + public final void cvtsi2sdl(Register dst, Register src) { assert dst.isFpu(); emitByte(0xF2); @@ -558,6 +576,15 @@ emitByte(0xC0 | encode); } + public final void cvtsi2ssl(Register dst, AMD64Address src) { + assert dst.isFpu(); + emitByte(0xF3); + prefix(src, dst); + emitByte(0x0F); + emitByte(0x2A); + emitOperandHelper(dst, src); + } + public final void cvtsi2ssl(Register dst, Register src) { assert dst.isFpu(); emitByte(0xF3); @@ -567,6 +594,15 @@ emitByte(0xC0 | encode); } + public final void cvtss2sd(Register dst, AMD64Address src) { + assert dst.isFpu(); + emitByte(0xF3); + prefix(src, dst); + emitByte(0x0F); + emitByte(0x5A); + emitOperandHelper(dst, src); + } + public final void cvtss2sd(Register dst, Register src) { assert dst.isFpu(); assert src.isFpu(); @@ -577,6 +613,14 @@ emitByte(0xC0 | encode); } + public final void cvttsd2sil(Register dst, AMD64Address src) { + emitByte(0xF2); + prefix(src, dst); + emitByte(0x0F); + emitByte(0x2C); + emitOperandHelper(dst, src); + } + public final void cvttsd2sil(Register dst, Register src) { assert src.isFpu(); emitByte(0xF2); @@ -586,6 +630,14 @@ emitByte(0xC0 | encode); } + public final void cvttss2sil(Register dst, AMD64Address src) { + emitByte(0xF3); + prefix(src, dst); + emitByte(0x0F); + emitByte(0x2C); + emitOperandHelper(dst, src); + } + public final void cvttss2sil(Register dst, Register src) { assert src.isFpu(); emitByte(0xF3); @@ -1055,6 +1107,13 @@ emitByte(0xC0 | encode); } + public final void movsxw(Register dst, AMD64Address src) { + prefix(src, dst); + emitByte(0x0F); + emitByte(0xBF); + emitOperandHelper(dst, src); + } + public final void movw(AMD64Address dst, int imm16) { emitByte(0x66); // switch to 16-bit mode prefix(dst); @@ -1954,6 +2013,15 @@ emitOperandHelper(reg, adr); } + public final void cvtsi2sdq(Register dst, AMD64Address src) { + assert dst.isFpu(); + emitByte(0xF2); + prefixq(src, dst); + emitByte(0x0F); + emitByte(0x2A); + emitOperandHelper(dst, src); + } + public final void cvtsi2sdq(Register dst, Register src) { assert dst.isFpu(); emitByte(0xF2); @@ -1963,6 +2031,15 @@ emitByte(0xC0 | encode); } + public final void cvtsi2ssq(Register dst, AMD64Address src) { + assert dst.isFpu(); + emitByte(0xF3); + prefixq(src, dst); + emitByte(0x0F); + emitByte(0x2A); + emitOperandHelper(dst, src); + } + public final void cvtsi2ssq(Register dst, Register src) { assert dst.isFpu(); emitByte(0xF3); @@ -1972,6 +2049,14 @@ emitByte(0xC0 | encode); } + public final void cvttsd2siq(Register dst, AMD64Address src) { + emitByte(0xF2); + prefixq(src, dst); + emitByte(0x0F); + emitByte(0x2C); + emitOperandHelper(dst, src); + } + public final void cvttsd2siq(Register dst, Register src) { assert src.isFpu(); emitByte(0xF2); @@ -1981,6 +2066,14 @@ emitByte(0xC0 | encode); } + public final void cvttss2siq(Register dst, AMD64Address src) { + emitByte(0xF3); + prefixq(src, dst); + emitByte(0x0F); + emitByte(0x2C); + emitOperandHelper(dst, src); + } + public final void cvttss2siq(Register dst, Register src) { assert src.isFpu(); emitByte(0xF3);
--- a/graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64Arithmetic.java Mon Mar 11 10:13:44 2013 +0100 +++ b/graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64Arithmetic.java Mon Mar 11 11:07:56 2013 +0100 @@ -58,7 +58,7 @@ public static class Unary2Op extends AMD64LIRInstruction { @Opcode private final AMD64Arithmetic opcode; @Def({REG}) protected AllocatableValue result; - @Use({REG}) protected AllocatableValue x; + @Use({REG, STACK}) protected AllocatableValue x; public Unary2Op(AMD64Arithmetic opcode, AllocatableValue result, AllocatableValue x) { this.opcode = opcode; @@ -455,6 +455,33 @@ case DSUB: masm.subsd(asDoubleReg(dst), (AMD64Address) tasm.asDoubleAddr(src)); break; case DMUL: masm.mulsd(asDoubleReg(dst), (AMD64Address) tasm.asDoubleAddr(src)); break; case DDIV: masm.divsd(asDoubleReg(dst), (AMD64Address) tasm.asDoubleAddr(src)); break; + + case I2B: masm.movsxb(asIntReg(dst), (AMD64Address) tasm.asIntAddr(src)); break; + case I2S: masm.movsxw(asIntReg(dst), (AMD64Address) tasm.asIntAddr(src)); break; + case I2L: masm.movslq(asLongReg(dst), (AMD64Address) tasm.asIntAddr(src)); break; + case F2D: masm.cvtss2sd(asDoubleReg(dst), (AMD64Address) tasm.asFloatAddr(src)); break; + case D2F: masm.cvtsd2ss(asFloatReg(dst), (AMD64Address) tasm.asDoubleAddr(src)); break; + case I2F: masm.cvtsi2ssl(asFloatReg(dst), (AMD64Address) tasm.asIntAddr(src)); break; + case I2D: masm.cvtsi2sdl(asDoubleReg(dst), (AMD64Address) tasm.asIntAddr(src)); break; + case L2F: masm.cvtsi2ssq(asFloatReg(dst), (AMD64Address) tasm.asLongAddr(src)); break; + case L2D: masm.cvtsi2sdq(asDoubleReg(dst), (AMD64Address) tasm.asLongAddr(src)); break; + case F2I: + masm.cvttss2sil(asIntReg(dst), (AMD64Address) tasm.asFloatAddr(src)); + break; + case D2I: + masm.cvttsd2sil(asIntReg(dst), (AMD64Address) tasm.asDoubleAddr(src)); + break; + case F2L: + masm.cvttss2siq(asLongReg(dst), (AMD64Address) tasm.asFloatAddr(src)); + break; + case D2L: + masm.cvttsd2siq(asLongReg(dst), (AMD64Address) tasm.asDoubleAddr(src)); + break; + case MOV_I2F: masm.movss(asFloatReg(dst), (AMD64Address) tasm.asIntAddr(src)); break; + case MOV_L2D: masm.movsd(asDoubleReg(dst), (AMD64Address) tasm.asLongAddr(src)); break; + case MOV_F2I: masm.movl(asIntReg(dst), (AMD64Address) tasm.asFloatAddr(src)); break; + case MOV_D2L: masm.movq(asLongReg(dst), (AMD64Address) tasm.asDoubleAddr(src)); break; + default: throw GraalInternalError.shouldNotReachHere(); } }