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changeset 11273:b5e95841d366

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Move SQRT from AMD64MathIntrinsicOp to AMD64Arithmetic.
author Roland Schatz <roland.schatz@oracle.com>
date Fri, 09 Aug 2013 11:47:41 +0200
parents 1e07d9303420
children 3209552fdb4e af358daf4f41
files graal/com.oracle.graal.asm.amd64/src/com/oracle/graal/asm/amd64/AMD64Assembler.java graal/com.oracle.graal.compiler.amd64/src/com/oracle/graal/compiler/amd64/AMD64LIRGenerator.java graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64Arithmetic.java graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64MathIntrinsicOp.java
diffstat 4 files changed, 19 insertions(+), 3 deletions(-) [+]
line wrap: on
line diff
--- a/graal/com.oracle.graal.asm.amd64/src/com/oracle/graal/asm/amd64/AMD64Assembler.java	Fri Aug 09 11:38:40 2013 +0200
+++ b/graal/com.oracle.graal.asm.amd64/src/com/oracle/graal/asm/amd64/AMD64Assembler.java	Fri Aug 09 11:47:41 2013 +0200
@@ -1518,6 +1518,15 @@
         emitByte(0xE8 | encode);
     }
 
+    public final void sqrtsd(Register dst, AMD64Address src) {
+        assert dst.getRegisterCategory() == AMD64.XMM;
+        emitByte(0xF2);
+        prefix(src, dst);
+        emitByte(0x0F);
+        emitByte(0x51);
+        emitOperandHelper(dst, src);
+    }
+
     public final void sqrtsd(Register dst, Register src) {
         assert dst.getRegisterCategory() == AMD64.XMM;
         assert src.getRegisterCategory() == AMD64.XMM;
--- a/graal/com.oracle.graal.compiler.amd64/src/com/oracle/graal/compiler/amd64/AMD64LIRGenerator.java	Fri Aug 09 11:38:40 2013 +0200
+++ b/graal/com.oracle.graal.compiler.amd64/src/com/oracle/graal/compiler/amd64/AMD64LIRGenerator.java	Fri Aug 09 11:47:41 2013 +0200
@@ -800,7 +800,7 @@
 
     @Override
     public void emitMathSqrt(Variable result, Variable input) {
-        append(new AMD64MathIntrinsicOp(SQRT, result, input));
+        append(new Unary2Op(SQRT, result, input));
     }
 
     @Override
--- a/graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64Arithmetic.java	Fri Aug 09 11:38:40 2013 +0200
+++ b/graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64Arithmetic.java	Fri Aug 09 11:47:41 2013 +0200
@@ -43,6 +43,7 @@
     FADD, FSUB, FMUL, FDIV, FREM, FAND, FOR, FXOR,
     DADD, DSUB, DMUL, DDIV, DREM, DAND, DOR, DXOR,
     INEG, LNEG,
+    SQRT,
     I2L, L2I, I2B, I2C, I2S,
     F2D, D2F,
     I2F, I2D,
@@ -484,6 +485,10 @@
                     masm.xorpd(asDoubleReg(dst), asDoubleReg(src));
                     break;
 
+                case SQRT:
+                    masm.sqrtsd(asDoubleReg(dst), asDoubleReg(src));
+                    break;
+
                 case I2B:
                     masm.movsxb(asIntReg(dst), asIntReg(src));
                     break;
@@ -740,6 +745,10 @@
                     masm.divsd(asDoubleReg(dst), (AMD64Address) tasm.asDoubleAddr(src));
                     break;
 
+                case SQRT:
+                    masm.sqrtsd(asDoubleReg(dst), (AMD64Address) tasm.asDoubleAddr(src));
+                    break;
+
                 case I2B:
                     masm.movsxb(asIntReg(dst), (AMD64Address) tasm.asIntAddr(src));
                     break;
--- a/graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64MathIntrinsicOp.java	Fri Aug 09 11:38:40 2013 +0200
+++ b/graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64MathIntrinsicOp.java	Fri Aug 09 11:47:41 2013 +0200
@@ -33,7 +33,6 @@
 // @formatter:off
 public class AMD64MathIntrinsicOp extends AMD64LIRInstruction {
     public enum IntrinsicOpcode  {
-        SQRT,
         SIN, COS, TAN,
         LOG, LOG10
     }
@@ -51,7 +50,6 @@
     @Override
     public void emitCode(TargetMethodAssembler tasm, AMD64MacroAssembler masm) {
         switch (opcode) {
-            case SQRT:  masm.sqrtsd(asDoubleReg(result), asDoubleReg(input)); break;
             case LOG:   masm.flog(asDoubleReg(result), asDoubleReg(input), false); break;
             case LOG10: masm.flog(asDoubleReg(result), asDoubleReg(input), true); break;
             case SIN:   masm.fsin(asDoubleReg(result), asDoubleReg(input)); break;