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changeset 21447:f172a195a8a9

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mx gate: bootstrap with -G:+SSA_LIR.
author Josef Eisl <josef.eisl@jku.at>
date Thu, 07 May 2015 14:47:27 +0200
parents 43462ed89797
children 545cd6b3b377
files mx/mx_graal.py
diffstat 1 files changed, 6 insertions(+), 0 deletions(-) [+]
line wrap: on
line diff
--- a/mx/mx_graal.py	Thu May 21 11:54:22 2015 +0200
+++ b/mx/mx_graal.py	Thu May 07 14:47:27 2015 +0200
@@ -1686,6 +1686,12 @@
                 vm(['-XX:-TieredCompilation', '-G:RegisterPressure=' + registers, '-esa', '-version'])
 
     with VM('graal', 'product'):
+        with Task('BootstrapSSAWithRegisterPressure:product', tasks) as t:
+            if t:
+                registers = 'o0,o1,o2,o3,f8,f9,d32,d34' if platform.processor() == 'sparc' else 'rbx,r11,r10,r14,xmm3,xmm11,xmm14'
+                vm(['-XX:-TieredCompilation', '-G:+SSA_LIR', '-G:RegisterPressure=' + registers, '-esa', '-version'])
+
+    with VM('graal', 'product'):
         with Task('BootstrapWithImmutableCode:product', tasks) as t:
             if t: vm(['-XX:-TieredCompilation', '-G:+ImmutableCode', '-G:+VerifyPhases', '-esa', '-version'])