001/*
002 * Copyright (c) 2015, 2015, Oracle and/or its affiliates. All rights reserved.
003 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
004 *
005 * This code is free software; you can redistribute it and/or modify it
006 * under the terms of the GNU General Public License version 2 only, as
007 * published by the Free Software Foundation.
008 *
009 * This code is distributed in the hope that it will be useful, but WITHOUT
010 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
011 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
012 * version 2 for more details (a copy is included in the LICENSE file that
013 * accompanied this code).
014 *
015 * You should have received a copy of the GNU General Public License version
016 * 2 along with this work; if not, write to the Free Software Foundation,
017 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
018 *
019 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
020 * or visit www.oracle.com if you need additional information or have any
021 * questions.
022 */
023package com.oracle.graal.lir.amd64;
024
025import jdk.internal.jvmci.meta.*;
026import static com.oracle.graal.asm.amd64.AMD64Assembler.AMD64BinaryArithmetic.*;
027import static com.oracle.graal.lir.LIRInstruction.OperandFlag.*;
028import static jdk.internal.jvmci.code.ValueUtil.*;
029
030import com.oracle.graal.asm.amd64.*;
031import com.oracle.graal.asm.amd64.AMD64Assembler.*;
032import com.oracle.graal.lir.*;
033import com.oracle.graal.lir.asm.*;
034
035public class AMD64ClearRegisterOp extends AMD64LIRInstruction {
036    public static final LIRInstructionClass<AMD64ClearRegisterOp> TYPE = LIRInstructionClass.create(AMD64ClearRegisterOp.class);
037
038    @Opcode private final AMD64RMOp op;
039    private final OperandSize size;
040
041    @Def({REG}) protected AllocatableValue result;
042
043    public AMD64ClearRegisterOp(OperandSize size, AllocatableValue result) {
044        super(TYPE);
045        this.op = XOR.getRMOpcode(size);
046        this.size = size;
047        this.result = result;
048    }
049
050    @Override
051    public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
052        op.emit(masm, size, asRegister(result), asRegister(result));
053    }
054}