001/*
002 * Copyright (c) 2015, 2015, Oracle and/or its affiliates. All rights reserved.
003 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
004 *
005 * This code is free software; you can redistribute it and/or modify it
006 * under the terms of the GNU General Public License version 2 only, as
007 * published by the Free Software Foundation.
008 *
009 * This code is distributed in the hope that it will be useful, but WITHOUT
010 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
011 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
012 * version 2 for more details (a copy is included in the LICENSE file that
013 * accompanied this code).
014 *
015 * You should have received a copy of the GNU General Public License version
016 * 2 along with this work; if not, write to the Free Software Foundation,
017 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
018 *
019 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
020 * or visit www.oracle.com if you need additional information or have any
021 * questions.
022 */
023package com.oracle.graal.lir.amd64;
024
025import jdk.internal.jvmci.amd64.*;
026import jdk.internal.jvmci.meta.*;
027import static com.oracle.graal.asm.amd64.AMD64Assembler.AMD64MOp.*;
028import static com.oracle.graal.lir.LIRInstruction.OperandFlag.*;
029import static jdk.internal.jvmci.code.ValueUtil.*;
030
031import com.oracle.graal.asm.amd64.*;
032import com.oracle.graal.asm.amd64.AMD64Assembler.*;
033import com.oracle.graal.lir.*;
034import com.oracle.graal.lir.asm.*;
035
036/**
037 * AMD64 mul/div operation. This operation has a single operand for the second input. The first
038 * input must be in RAX for mul and in RDX:RAX for div. The result is in RDX:RAX.
039 */
040public class AMD64MulDivOp extends AMD64LIRInstruction {
041    public static final LIRInstructionClass<AMD64MulDivOp> TYPE = LIRInstructionClass.create(AMD64MulDivOp.class);
042
043    @Opcode private final AMD64MOp opcode;
044    private final OperandSize size;
045
046    @Def({REG}) protected AllocatableValue highResult;
047    @Def({REG}) protected AllocatableValue lowResult;
048
049    @Use({REG, ILLEGAL}) protected AllocatableValue highX;
050    @Use({REG}) protected AllocatableValue lowX;
051
052    @Use({REG, STACK}) protected AllocatableValue y;
053
054    @State protected LIRFrameState state;
055
056    public AMD64MulDivOp(AMD64MOp opcode, OperandSize size, LIRKind resultKind, AllocatableValue x, AllocatableValue y) {
057        this(opcode, size, resultKind, Value.ILLEGAL, x, y, null);
058    }
059
060    public AMD64MulDivOp(AMD64MOp opcode, OperandSize size, LIRKind resultKind, AllocatableValue highX, AllocatableValue lowX, AllocatableValue y, LIRFrameState state) {
061        super(TYPE);
062        this.opcode = opcode;
063        this.size = size;
064
065        this.highResult = AMD64.rdx.asValue(resultKind);
066        this.lowResult = AMD64.rax.asValue(resultKind);
067
068        this.highX = highX;
069        this.lowX = lowX;
070
071        this.y = y;
072
073        this.state = state;
074    }
075
076    public AllocatableValue getHighResult() {
077        return highResult;
078    }
079
080    public AllocatableValue getLowResult() {
081        return lowResult;
082    }
083
084    public AllocatableValue getQuotient() {
085        return lowResult;
086    }
087
088    public AllocatableValue getRemainder() {
089        return highResult;
090    }
091
092    @Override
093    public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
094        if (state != null) {
095            crb.recordImplicitException(masm.position(), state);
096        }
097        if (isRegister(y)) {
098            opcode.emit(masm, size, asRegister(y));
099        } else {
100            assert isStackSlot(y);
101            opcode.emit(masm, size, (AMD64Address) crb.asAddress(y));
102        }
103    }
104
105    @Override
106    public void verify() {
107        assert asRegister(highResult).equals(AMD64.rdx);
108        assert asRegister(lowResult).equals(AMD64.rax);
109
110        assert asRegister(lowX).equals(AMD64.rax);
111        if (opcode == DIV || opcode == IDIV) {
112            assert asRegister(highX).equals(AMD64.rdx);
113        } else if (opcode == MUL || opcode == IMUL) {
114            assert isIllegal(highX);
115        }
116    }
117}