001/*
002 * Copyright (c) 2015, 2015, Oracle and/or its affiliates. All rights reserved.
003 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
004 *
005 * This code is free software; you can redistribute it and/or modify it
006 * under the terms of the GNU General Public License version 2 only, as
007 * published by the Free Software Foundation.
008 *
009 * This code is distributed in the hope that it will be useful, but WITHOUT
010 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
011 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
012 * version 2 for more details (a copy is included in the LICENSE file that
013 * accompanied this code).
014 *
015 * You should have received a copy of the GNU General Public License version
016 * 2 along with this work; if not, write to the Free Software Foundation,
017 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
018 *
019 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
020 * or visit www.oracle.com if you need additional information or have any
021 * questions.
022 */
023package com.oracle.graal.lir.amd64;
024
025import jdk.internal.jvmci.amd64.*;
026import jdk.internal.jvmci.meta.*;
027import static com.oracle.graal.lir.LIRInstruction.OperandFlag.*;
028import static jdk.internal.jvmci.code.ValueUtil.*;
029
030import com.oracle.graal.asm.amd64.*;
031import com.oracle.graal.asm.amd64.AMD64Assembler.*;
032import com.oracle.graal.lir.*;
033import com.oracle.graal.lir.asm.*;
034
035/**
036 * AMD64 shift/rotate operation. This operation has a single operand for the first input and output.
037 * The second input must be in the RCX register.
038 */
039public class AMD64ShiftOp extends AMD64LIRInstruction {
040    public static final LIRInstructionClass<AMD64ShiftOp> TYPE = LIRInstructionClass.create(AMD64ShiftOp.class);
041
042    @Opcode private final AMD64MOp opcode;
043    private final OperandSize size;
044
045    @Def({REG, HINT}) protected AllocatableValue result;
046    @Use({REG, STACK}) protected AllocatableValue x;
047    @Alive({REG}) protected AllocatableValue y;
048
049    public AMD64ShiftOp(AMD64MOp opcode, OperandSize size, AllocatableValue result, AllocatableValue x, AllocatableValue y) {
050        super(TYPE);
051        this.opcode = opcode;
052        this.size = size;
053
054        this.result = result;
055        this.x = x;
056        this.y = y;
057    }
058
059    @Override
060    public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
061        AMD64Move.move(crb, masm, result, x);
062        opcode.emit(masm, size, asRegister(result));
063    }
064
065    @Override
066    public void verify() {
067        assert asRegister(y).equals(AMD64.rcx);
068    }
069}