001/*
002 * Copyright (c) 2015, 2015, Oracle and/or its affiliates. All rights reserved.
003 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
004 *
005 * This code is free software; you can redistribute it and/or modify it
006 * under the terms of the GNU General Public License version 2 only, as
007 * published by the Free Software Foundation.
008 *
009 * This code is distributed in the hope that it will be useful, but WITHOUT
010 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
011 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
012 * version 2 for more details (a copy is included in the LICENSE file that
013 * accompanied this code).
014 *
015 * You should have received a copy of the GNU General Public License version
016 * 2 along with this work; if not, write to the Free Software Foundation,
017 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
018 *
019 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
020 * or visit www.oracle.com if you need additional information or have any
021 * questions.
022 */
023package com.oracle.graal.lir.amd64;
024
025import jdk.internal.jvmci.amd64.*;
026import jdk.internal.jvmci.meta.*;
027import static com.oracle.graal.asm.amd64.AMD64Assembler.OperandSize.*;
028import static com.oracle.graal.lir.LIRInstruction.OperandFlag.*;
029import static jdk.internal.jvmci.code.ValueUtil.*;
030
031import com.oracle.graal.asm.amd64.*;
032import com.oracle.graal.asm.amd64.AMD64Assembler.*;
033import com.oracle.graal.lir.*;
034import com.oracle.graal.lir.asm.*;
035
036@Opcode("CDQ")
037public class AMD64SignExtendOp extends AMD64LIRInstruction {
038    public static final LIRInstructionClass<AMD64SignExtendOp> TYPE = LIRInstructionClass.create(AMD64SignExtendOp.class);
039
040    private final OperandSize size;
041
042    @Def({REG}) protected AllocatableValue highResult;
043    @Def({REG}) protected AllocatableValue lowResult;
044
045    @Use({REG}) protected AllocatableValue input;
046
047    public AMD64SignExtendOp(OperandSize size, LIRKind resultKind, AllocatableValue input) {
048        super(TYPE);
049        this.size = size;
050
051        this.highResult = AMD64.rdx.asValue(resultKind);
052        this.lowResult = AMD64.rax.asValue(resultKind);
053        this.input = input;
054    }
055
056    public AllocatableValue getHighResult() {
057        return highResult;
058    }
059
060    public AllocatableValue getLowResult() {
061        return lowResult;
062    }
063
064    @Override
065    public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
066        if (size == DWORD) {
067            masm.cdql();
068        } else {
069            assert size == QWORD;
070            masm.cdqq();
071        }
072    }
073
074    @Override
075    public void verify() {
076        assert asRegister(highResult).equals(AMD64.rdx);
077        assert asRegister(lowResult).equals(AMD64.rax);
078        assert asRegister(input).equals(AMD64.rax);
079    }
080}