Mercurial > hg > graal-compiler
annotate src/share/vm/c1/c1_LIR.cpp @ 1681:126ea7725993
6953477: Increase portability and flexibility of building Hotspot
Summary: A collection of portability improvements including shared code support for PPC, ARM platforms, software floating point, cross compilation support and improvements in error crash detail.
Reviewed-by: phh, never, coleenp, dholmes
| author | bobv |
|---|---|
| date | Tue, 03 Aug 2010 08:13:38 -0400 |
| parents | e9ff18c4ace7 |
| children | d5d065957597 |
| rev | line source |
|---|---|
| 0 | 1 /* |
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2 * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 25 # include "incls/_precompiled.incl" | |
| 26 # include "incls/_c1_LIR.cpp.incl" | |
| 27 | |
| 28 Register LIR_OprDesc::as_register() const { | |
| 29 return FrameMap::cpu_rnr2reg(cpu_regnr()); | |
| 30 } | |
| 31 | |
| 32 Register LIR_OprDesc::as_register_lo() const { | |
| 33 return FrameMap::cpu_rnr2reg(cpu_regnrLo()); | |
| 34 } | |
| 35 | |
| 36 Register LIR_OprDesc::as_register_hi() const { | |
| 37 return FrameMap::cpu_rnr2reg(cpu_regnrHi()); | |
| 38 } | |
| 39 | |
| 304 | 40 #if defined(X86) |
| 0 | 41 |
| 42 XMMRegister LIR_OprDesc::as_xmm_float_reg() const { | |
| 43 return FrameMap::nr2xmmreg(xmm_regnr()); | |
| 44 } | |
| 45 | |
| 46 XMMRegister LIR_OprDesc::as_xmm_double_reg() const { | |
| 47 assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation"); | |
| 48 return FrameMap::nr2xmmreg(xmm_regnrLo()); | |
| 49 } | |
| 50 | |
| 304 | 51 #endif // X86 |
| 0 | 52 |
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53 #if defined(SPARC) || defined(PPC) |
| 0 | 54 |
| 55 FloatRegister LIR_OprDesc::as_float_reg() const { | |
| 56 return FrameMap::nr2floatreg(fpu_regnr()); | |
| 57 } | |
| 58 | |
| 59 FloatRegister LIR_OprDesc::as_double_reg() const { | |
| 60 return FrameMap::nr2floatreg(fpu_regnrHi()); | |
| 61 } | |
| 62 | |
| 63 #endif | |
| 64 | |
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65 #ifdef ARM |
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66 |
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67 FloatRegister LIR_OprDesc::as_float_reg() const { |
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68 return as_FloatRegister(fpu_regnr()); |
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69 } |
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70 |
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71 FloatRegister LIR_OprDesc::as_double_reg() const { |
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72 return as_FloatRegister(fpu_regnrLo()); |
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73 } |
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74 |
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75 #endif |
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76 |
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77 |
| 0 | 78 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal(); |
| 79 | |
| 80 LIR_Opr LIR_OprFact::value_type(ValueType* type) { | |
| 81 ValueTag tag = type->tag(); | |
| 82 switch (tag) { | |
| 83 case objectTag : { | |
| 84 ClassConstant* c = type->as_ClassConstant(); | |
| 85 if (c != NULL && !c->value()->is_loaded()) { | |
| 86 return LIR_OprFact::oopConst(NULL); | |
| 87 } else { | |
| 88 return LIR_OprFact::oopConst(type->as_ObjectType()->encoding()); | |
| 89 } | |
| 90 } | |
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91 case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value()); |
| 0 | 92 case intTag : return LIR_OprFact::intConst(type->as_IntConstant()->value()); |
| 93 case floatTag : return LIR_OprFact::floatConst(type->as_FloatConstant()->value()); | |
| 94 case longTag : return LIR_OprFact::longConst(type->as_LongConstant()->value()); | |
| 95 case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value()); | |
| 304 | 96 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1); |
| 0 | 97 } |
| 98 } | |
| 99 | |
| 100 | |
| 101 LIR_Opr LIR_OprFact::dummy_value_type(ValueType* type) { | |
| 102 switch (type->tag()) { | |
| 103 case objectTag: return LIR_OprFact::oopConst(NULL); | |
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104 case addressTag:return LIR_OprFact::addressConst(0); |
| 0 | 105 case intTag: return LIR_OprFact::intConst(0); |
| 106 case floatTag: return LIR_OprFact::floatConst(0.0); | |
| 107 case longTag: return LIR_OprFact::longConst(0); | |
| 108 case doubleTag: return LIR_OprFact::doubleConst(0.0); | |
| 304 | 109 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1); |
| 0 | 110 } |
| 111 return illegalOpr; | |
| 112 } | |
| 113 | |
| 114 | |
| 115 | |
| 116 //--------------------------------------------------- | |
| 117 | |
| 118 | |
| 119 LIR_Address::Scale LIR_Address::scale(BasicType type) { | |
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120 int elem_size = type2aelembytes(type); |
| 0 | 121 switch (elem_size) { |
| 122 case 1: return LIR_Address::times_1; | |
| 123 case 2: return LIR_Address::times_2; | |
| 124 case 4: return LIR_Address::times_4; | |
| 125 case 8: return LIR_Address::times_8; | |
| 126 } | |
| 127 ShouldNotReachHere(); | |
| 128 return LIR_Address::times_1; | |
| 129 } | |
| 130 | |
| 131 | |
| 132 #ifndef PRODUCT | |
| 133 void LIR_Address::verify() const { | |
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134 #if defined(SPARC) || defined(PPC) |
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135 assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used"); |
| 0 | 136 assert(disp() == 0 || index()->is_illegal(), "can't have both"); |
| 137 #endif | |
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138 #ifdef ARM |
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139 assert(disp() == 0 || index()->is_illegal(), "can't have both"); |
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140 assert(-4096 < disp() && disp() < 4096, "architecture constraint"); |
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141 #endif |
| 0 | 142 #ifdef _LP64 |
| 143 assert(base()->is_cpu_register(), "wrong base operand"); | |
| 144 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand"); | |
| 145 assert(base()->type() == T_OBJECT || base()->type() == T_LONG, | |
| 146 "wrong type for addresses"); | |
| 147 #else | |
| 148 assert(base()->is_single_cpu(), "wrong base operand"); | |
| 149 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand"); | |
| 150 assert(base()->type() == T_OBJECT || base()->type() == T_INT, | |
| 151 "wrong type for addresses"); | |
| 152 #endif | |
| 153 } | |
| 154 #endif | |
| 155 | |
| 156 | |
| 157 //--------------------------------------------------- | |
| 158 | |
| 159 char LIR_OprDesc::type_char(BasicType t) { | |
| 160 switch (t) { | |
| 161 case T_ARRAY: | |
| 162 t = T_OBJECT; | |
| 163 case T_BOOLEAN: | |
| 164 case T_CHAR: | |
| 165 case T_FLOAT: | |
| 166 case T_DOUBLE: | |
| 167 case T_BYTE: | |
| 168 case T_SHORT: | |
| 169 case T_INT: | |
| 170 case T_LONG: | |
| 171 case T_OBJECT: | |
| 172 case T_ADDRESS: | |
| 173 case T_VOID: | |
| 174 return ::type2char(t); | |
| 175 | |
| 176 case T_ILLEGAL: | |
| 177 return '?'; | |
| 178 | |
| 179 default: | |
| 180 ShouldNotReachHere(); | |
| 304 | 181 return '?'; |
| 0 | 182 } |
| 183 } | |
| 184 | |
| 185 #ifndef PRODUCT | |
| 186 void LIR_OprDesc::validate_type() const { | |
| 187 | |
| 188 #ifdef ASSERT | |
| 189 if (!is_pointer() && !is_illegal()) { | |
| 190 switch (as_BasicType(type_field())) { | |
| 191 case T_LONG: | |
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192 assert((kind_field() == cpu_register || kind_field() == stack_value) && |
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193 size_field() == double_size, "must match"); |
| 0 | 194 break; |
| 195 case T_FLOAT: | |
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196 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI) |
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197 assert((kind_field() == fpu_register || kind_field() == stack_value |
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198 ARM_ONLY(|| kind_field() == cpu_register) |
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199 PPC_ONLY(|| kind_field() == cpu_register) ) && |
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200 size_field() == single_size, "must match"); |
| 0 | 201 break; |
| 202 case T_DOUBLE: | |
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203 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI) |
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204 assert((kind_field() == fpu_register || kind_field() == stack_value |
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205 ARM_ONLY(|| kind_field() == cpu_register) |
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206 PPC_ONLY(|| kind_field() == cpu_register) ) && |
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207 size_field() == double_size, "must match"); |
| 0 | 208 break; |
| 209 case T_BOOLEAN: | |
| 210 case T_CHAR: | |
| 211 case T_BYTE: | |
| 212 case T_SHORT: | |
| 213 case T_INT: | |
| 214 case T_OBJECT: | |
| 215 case T_ARRAY: | |
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216 assert((kind_field() == cpu_register || kind_field() == stack_value) && |
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217 size_field() == single_size, "must match"); |
| 0 | 218 break; |
| 219 | |
| 220 case T_ILLEGAL: | |
| 221 // XXX TKR also means unknown right now | |
| 222 // assert(is_illegal(), "must match"); | |
| 223 break; | |
| 224 | |
| 225 default: | |
| 226 ShouldNotReachHere(); | |
| 227 } | |
| 228 } | |
| 229 #endif | |
| 230 | |
| 231 } | |
| 232 #endif // PRODUCT | |
| 233 | |
| 234 | |
| 235 bool LIR_OprDesc::is_oop() const { | |
| 236 if (is_pointer()) { | |
| 237 return pointer()->is_oop_pointer(); | |
| 238 } else { | |
| 239 OprType t= type_field(); | |
| 240 assert(t != unknown_type, "not set"); | |
| 241 return t == object_type; | |
| 242 } | |
| 243 } | |
| 244 | |
| 245 | |
| 246 | |
| 247 void LIR_Op2::verify() const { | |
| 248 #ifdef ASSERT | |
| 249 switch (code()) { | |
| 250 case lir_cmove: | |
| 251 break; | |
| 252 | |
| 253 default: | |
| 254 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(), | |
| 255 "can't produce oops from arith"); | |
| 256 } | |
| 257 | |
| 258 if (TwoOperandLIRForm) { | |
| 259 switch (code()) { | |
| 260 case lir_add: | |
| 261 case lir_sub: | |
| 262 case lir_mul: | |
| 263 case lir_mul_strictfp: | |
| 264 case lir_div: | |
| 265 case lir_div_strictfp: | |
| 266 case lir_rem: | |
| 267 case lir_logic_and: | |
| 268 case lir_logic_or: | |
| 269 case lir_logic_xor: | |
| 270 case lir_shl: | |
| 271 case lir_shr: | |
| 272 assert(in_opr1() == result_opr(), "opr1 and result must match"); | |
| 273 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid"); | |
| 274 break; | |
| 275 | |
| 276 // special handling for lir_ushr because of write barriers | |
| 277 case lir_ushr: | |
| 278 assert(in_opr1() == result_opr() || in_opr2()->is_constant(), "opr1 and result must match or shift count is constant"); | |
| 279 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid"); | |
| 280 break; | |
| 281 | |
| 282 } | |
| 283 } | |
| 284 #endif | |
| 285 } | |
| 286 | |
| 287 | |
| 288 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block) | |
| 289 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) | |
| 290 , _cond(cond) | |
| 291 , _type(type) | |
| 292 , _label(block->label()) | |
| 293 , _block(block) | |
| 294 , _ublock(NULL) | |
| 295 , _stub(NULL) { | |
| 296 } | |
| 297 | |
| 298 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) : | |
| 299 LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) | |
| 300 , _cond(cond) | |
| 301 , _type(type) | |
| 302 , _label(stub->entry()) | |
| 303 , _block(NULL) | |
| 304 , _ublock(NULL) | |
| 305 , _stub(stub) { | |
| 306 } | |
| 307 | |
| 308 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock) | |
| 309 : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) | |
| 310 , _cond(cond) | |
| 311 , _type(type) | |
| 312 , _label(block->label()) | |
| 313 , _block(block) | |
| 314 , _ublock(ublock) | |
| 315 , _stub(NULL) | |
| 316 { | |
| 317 } | |
| 318 | |
| 319 void LIR_OpBranch::change_block(BlockBegin* b) { | |
| 320 assert(_block != NULL, "must have old block"); | |
| 321 assert(_block->label() == label(), "must be equal"); | |
| 322 | |
| 323 _block = b; | |
| 324 _label = b->label(); | |
| 325 } | |
| 326 | |
| 327 void LIR_OpBranch::change_ublock(BlockBegin* b) { | |
| 328 assert(_ublock != NULL, "must have old block"); | |
| 329 _ublock = b; | |
| 330 } | |
| 331 | |
| 332 void LIR_OpBranch::negate_cond() { | |
| 333 switch (_cond) { | |
| 334 case lir_cond_equal: _cond = lir_cond_notEqual; break; | |
| 335 case lir_cond_notEqual: _cond = lir_cond_equal; break; | |
| 336 case lir_cond_less: _cond = lir_cond_greaterEqual; break; | |
| 337 case lir_cond_lessEqual: _cond = lir_cond_greater; break; | |
| 338 case lir_cond_greaterEqual: _cond = lir_cond_less; break; | |
| 339 case lir_cond_greater: _cond = lir_cond_lessEqual; break; | |
| 340 default: ShouldNotReachHere(); | |
| 341 } | |
| 342 } | |
| 343 | |
| 344 | |
| 345 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass, | |
| 346 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, | |
| 347 bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, | |
| 348 CodeStub* stub, | |
| 349 ciMethod* profiled_method, | |
| 350 int profiled_bci) | |
| 351 : LIR_Op(code, result, NULL) | |
| 352 , _object(object) | |
| 353 , _array(LIR_OprFact::illegalOpr) | |
| 354 , _klass(klass) | |
| 355 , _tmp1(tmp1) | |
| 356 , _tmp2(tmp2) | |
| 357 , _tmp3(tmp3) | |
| 358 , _fast_check(fast_check) | |
| 359 , _stub(stub) | |
| 360 , _info_for_patch(info_for_patch) | |
| 361 , _info_for_exception(info_for_exception) | |
| 362 , _profiled_method(profiled_method) | |
| 363 , _profiled_bci(profiled_bci) { | |
| 364 if (code == lir_checkcast) { | |
| 365 assert(info_for_exception != NULL, "checkcast throws exceptions"); | |
| 366 } else if (code == lir_instanceof) { | |
| 367 assert(info_for_exception == NULL, "instanceof throws no exceptions"); | |
| 368 } else { | |
| 369 ShouldNotReachHere(); | |
| 370 } | |
| 371 } | |
| 372 | |
| 373 | |
| 374 | |
| 375 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) | |
| 376 : LIR_Op(code, LIR_OprFact::illegalOpr, NULL) | |
| 377 , _object(object) | |
| 378 , _array(array) | |
| 379 , _klass(NULL) | |
| 380 , _tmp1(tmp1) | |
| 381 , _tmp2(tmp2) | |
| 382 , _tmp3(tmp3) | |
| 383 , _fast_check(false) | |
| 384 , _stub(NULL) | |
| 385 , _info_for_patch(NULL) | |
| 386 , _info_for_exception(info_for_exception) | |
| 387 , _profiled_method(profiled_method) | |
| 388 , _profiled_bci(profiled_bci) { | |
| 389 if (code == lir_store_check) { | |
| 390 _stub = new ArrayStoreExceptionStub(info_for_exception); | |
| 391 assert(info_for_exception != NULL, "store_check throws exceptions"); | |
| 392 } else { | |
| 393 ShouldNotReachHere(); | |
| 394 } | |
| 395 } | |
| 396 | |
| 397 | |
| 398 LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length, | |
| 399 LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info) | |
| 400 : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info) | |
| 401 , _tmp(tmp) | |
| 402 , _src(src) | |
| 403 , _src_pos(src_pos) | |
| 404 , _dst(dst) | |
| 405 , _dst_pos(dst_pos) | |
| 406 , _flags(flags) | |
| 407 , _expected_type(expected_type) | |
| 408 , _length(length) { | |
| 409 _stub = new ArrayCopyStub(this); | |
| 410 } | |
| 411 | |
| 412 | |
| 413 //-------------------verify-------------------------- | |
| 414 | |
| 415 void LIR_Op1::verify() const { | |
| 416 switch(code()) { | |
| 417 case lir_move: | |
| 418 assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be"); | |
| 419 break; | |
| 420 case lir_null_check: | |
| 421 assert(in_opr()->is_register(), "must be"); | |
| 422 break; | |
| 423 case lir_return: | |
| 424 assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be"); | |
| 425 break; | |
| 426 } | |
| 427 } | |
| 428 | |
| 429 void LIR_OpRTCall::verify() const { | |
| 430 assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function"); | |
| 431 } | |
| 432 | |
| 433 //-------------------visits-------------------------- | |
| 434 | |
| 435 // complete rework of LIR instruction visitor. | |
| 436 // The virtual calls for each instruction type is replaced by a big | |
| 437 // switch that adds the operands for each instruction | |
| 438 | |
| 439 void LIR_OpVisitState::visit(LIR_Op* op) { | |
| 440 // copy information from the LIR_Op | |
| 441 reset(); | |
| 442 set_op(op); | |
| 443 | |
| 444 switch (op->code()) { | |
| 445 | |
| 446 // LIR_Op0 | |
| 447 case lir_word_align: // result and info always invalid | |
| 448 case lir_backwardbranch_target: // result and info always invalid | |
| 449 case lir_build_frame: // result and info always invalid | |
| 450 case lir_fpop_raw: // result and info always invalid | |
| 451 case lir_24bit_FPU: // result and info always invalid | |
| 452 case lir_reset_FPU: // result and info always invalid | |
| 453 case lir_breakpoint: // result and info always invalid | |
| 454 case lir_membar: // result and info always invalid | |
| 455 case lir_membar_acquire: // result and info always invalid | |
| 456 case lir_membar_release: // result and info always invalid | |
| 457 { | |
| 458 assert(op->as_Op0() != NULL, "must be"); | |
| 459 assert(op->_info == NULL, "info not used by this instruction"); | |
| 460 assert(op->_result->is_illegal(), "not used"); | |
| 461 break; | |
| 462 } | |
| 463 | |
| 464 case lir_nop: // may have info, result always invalid | |
| 465 case lir_std_entry: // may have result, info always invalid | |
| 466 case lir_osr_entry: // may have result, info always invalid | |
| 467 case lir_get_thread: // may have result, info always invalid | |
| 468 { | |
| 469 assert(op->as_Op0() != NULL, "must be"); | |
| 470 if (op->_info != NULL) do_info(op->_info); | |
| 471 if (op->_result->is_valid()) do_output(op->_result); | |
| 472 break; | |
| 473 } | |
| 474 | |
| 475 | |
| 476 // LIR_OpLabel | |
| 477 case lir_label: // result and info always invalid | |
| 478 { | |
| 479 assert(op->as_OpLabel() != NULL, "must be"); | |
| 480 assert(op->_info == NULL, "info not used by this instruction"); | |
| 481 assert(op->_result->is_illegal(), "not used"); | |
| 482 break; | |
| 483 } | |
| 484 | |
| 485 | |
| 486 // LIR_Op1 | |
| 487 case lir_fxch: // input always valid, result and info always invalid | |
| 488 case lir_fld: // input always valid, result and info always invalid | |
| 489 case lir_ffree: // input always valid, result and info always invalid | |
| 490 case lir_push: // input always valid, result and info always invalid | |
| 491 case lir_pop: // input always valid, result and info always invalid | |
| 492 case lir_return: // input always valid, result and info always invalid | |
| 493 case lir_leal: // input and result always valid, info always invalid | |
| 494 case lir_neg: // input and result always valid, info always invalid | |
| 495 case lir_monaddr: // input and result always valid, info always invalid | |
| 496 case lir_null_check: // input and info always valid, result always invalid | |
| 497 case lir_move: // input and result always valid, may have info | |
| 498 case lir_prefetchr: // input always valid, result and info always invalid | |
| 499 case lir_prefetchw: // input always valid, result and info always invalid | |
| 500 { | |
| 501 assert(op->as_Op1() != NULL, "must be"); | |
| 502 LIR_Op1* op1 = (LIR_Op1*)op; | |
| 503 | |
| 504 if (op1->_info) do_info(op1->_info); | |
| 505 if (op1->_opr->is_valid()) do_input(op1->_opr); | |
| 506 if (op1->_result->is_valid()) do_output(op1->_result); | |
| 507 | |
| 508 break; | |
| 509 } | |
| 510 | |
| 511 case lir_safepoint: | |
| 512 { | |
| 513 assert(op->as_Op1() != NULL, "must be"); | |
| 514 LIR_Op1* op1 = (LIR_Op1*)op; | |
| 515 | |
| 516 assert(op1->_info != NULL, ""); do_info(op1->_info); | |
| 517 if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register | |
| 518 assert(op1->_result->is_illegal(), "safepoint does not produce value"); | |
| 519 | |
| 520 break; | |
| 521 } | |
| 522 | |
| 523 // LIR_OpConvert; | |
| 524 case lir_convert: // input and result always valid, info always invalid | |
| 525 { | |
| 526 assert(op->as_OpConvert() != NULL, "must be"); | |
| 527 LIR_OpConvert* opConvert = (LIR_OpConvert*)op; | |
| 528 | |
| 529 assert(opConvert->_info == NULL, "must be"); | |
| 530 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr); | |
| 531 if (opConvert->_result->is_valid()) do_output(opConvert->_result); | |
|
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532 #ifdef PPC |
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533 if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1); |
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534 if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2); |
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535 #endif |
| 0 | 536 do_stub(opConvert->_stub); |
| 537 | |
| 538 break; | |
| 539 } | |
| 540 | |
| 541 // LIR_OpBranch; | |
| 542 case lir_branch: // may have info, input and result register always invalid | |
| 543 case lir_cond_float_branch: // may have info, input and result register always invalid | |
| 544 { | |
| 545 assert(op->as_OpBranch() != NULL, "must be"); | |
| 546 LIR_OpBranch* opBranch = (LIR_OpBranch*)op; | |
| 547 | |
| 548 if (opBranch->_info != NULL) do_info(opBranch->_info); | |
| 549 assert(opBranch->_result->is_illegal(), "not used"); | |
| 550 if (opBranch->_stub != NULL) opBranch->stub()->visit(this); | |
| 551 | |
| 552 break; | |
| 553 } | |
| 554 | |
| 555 | |
| 556 // LIR_OpAllocObj | |
| 557 case lir_alloc_object: | |
| 558 { | |
| 559 assert(op->as_OpAllocObj() != NULL, "must be"); | |
| 560 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op; | |
| 561 | |
| 562 if (opAllocObj->_info) do_info(opAllocObj->_info); | |
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563 if (opAllocObj->_opr->is_valid()) { do_input(opAllocObj->_opr); |
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564 do_temp(opAllocObj->_opr); |
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565 } |
| 0 | 566 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1); |
| 567 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2); | |
| 568 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3); | |
| 569 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4); | |
| 570 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result); | |
| 571 do_stub(opAllocObj->_stub); | |
| 572 break; | |
| 573 } | |
| 574 | |
| 575 | |
| 576 // LIR_OpRoundFP; | |
| 577 case lir_roundfp: { | |
| 578 assert(op->as_OpRoundFP() != NULL, "must be"); | |
| 579 LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op; | |
| 580 | |
| 581 assert(op->_info == NULL, "info not used by this instruction"); | |
| 582 assert(opRoundFP->_tmp->is_illegal(), "not used"); | |
| 583 do_input(opRoundFP->_opr); | |
| 584 do_output(opRoundFP->_result); | |
| 585 | |
| 586 break; | |
| 587 } | |
| 588 | |
| 589 | |
| 590 // LIR_Op2 | |
| 591 case lir_cmp: | |
| 592 case lir_cmp_l2i: | |
| 593 case lir_ucmp_fd2i: | |
| 594 case lir_cmp_fd2i: | |
| 595 case lir_add: | |
| 596 case lir_sub: | |
| 597 case lir_mul: | |
| 598 case lir_div: | |
| 599 case lir_rem: | |
| 600 case lir_sqrt: | |
| 601 case lir_abs: | |
| 602 case lir_logic_and: | |
| 603 case lir_logic_or: | |
| 604 case lir_logic_xor: | |
| 605 case lir_shl: | |
| 606 case lir_shr: | |
| 607 case lir_ushr: | |
| 608 { | |
| 609 assert(op->as_Op2() != NULL, "must be"); | |
| 610 LIR_Op2* op2 = (LIR_Op2*)op; | |
| 611 | |
| 612 if (op2->_info) do_info(op2->_info); | |
| 613 if (op2->_opr1->is_valid()) do_input(op2->_opr1); | |
| 614 if (op2->_opr2->is_valid()) do_input(op2->_opr2); | |
| 615 if (op2->_tmp->is_valid()) do_temp(op2->_tmp); | |
| 616 if (op2->_result->is_valid()) do_output(op2->_result); | |
| 617 | |
| 618 break; | |
| 619 } | |
| 620 | |
| 621 // special handling for cmove: right input operand must not be equal | |
| 622 // to the result operand, otherwise the backend fails | |
| 623 case lir_cmove: | |
| 624 { | |
| 625 assert(op->as_Op2() != NULL, "must be"); | |
| 626 LIR_Op2* op2 = (LIR_Op2*)op; | |
| 627 | |
| 628 assert(op2->_info == NULL && op2->_tmp->is_illegal(), "not used"); | |
| 629 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used"); | |
| 630 | |
| 631 do_input(op2->_opr1); | |
| 632 do_input(op2->_opr2); | |
| 633 do_temp(op2->_opr2); | |
| 634 do_output(op2->_result); | |
| 635 | |
| 636 break; | |
| 637 } | |
| 638 | |
| 639 // vspecial handling for strict operations: register input operands | |
| 640 // as temp to guarantee that they do not overlap with other | |
| 641 // registers | |
| 642 case lir_mul_strictfp: | |
| 643 case lir_div_strictfp: | |
| 644 { | |
| 645 assert(op->as_Op2() != NULL, "must be"); | |
| 646 LIR_Op2* op2 = (LIR_Op2*)op; | |
| 647 | |
| 648 assert(op2->_info == NULL, "not used"); | |
| 649 assert(op2->_opr1->is_valid(), "used"); | |
| 650 assert(op2->_opr2->is_valid(), "used"); | |
| 651 assert(op2->_result->is_valid(), "used"); | |
| 652 | |
| 653 do_input(op2->_opr1); do_temp(op2->_opr1); | |
| 654 do_input(op2->_opr2); do_temp(op2->_opr2); | |
| 655 if (op2->_tmp->is_valid()) do_temp(op2->_tmp); | |
| 656 do_output(op2->_result); | |
| 657 | |
| 658 break; | |
| 659 } | |
| 660 | |
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661 case lir_throw: { |
| 0 | 662 assert(op->as_Op2() != NULL, "must be"); |
| 663 LIR_Op2* op2 = (LIR_Op2*)op; | |
| 664 | |
| 665 if (op2->_info) do_info(op2->_info); | |
| 666 if (op2->_opr1->is_valid()) do_temp(op2->_opr1); | |
| 667 if (op2->_opr2->is_valid()) do_input(op2->_opr2); // exception object is input parameter | |
| 668 assert(op2->_result->is_illegal(), "no result"); | |
| 669 | |
| 670 break; | |
| 671 } | |
| 672 | |
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673 case lir_unwind: { |
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674 assert(op->as_Op1() != NULL, "must be"); |
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675 LIR_Op1* op1 = (LIR_Op1*)op; |
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676 |
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677 assert(op1->_info == NULL, "no info"); |
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678 assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr); |
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679 assert(op1->_result->is_illegal(), "no result"); |
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680 |
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681 break; |
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682 } |
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683 |
| 0 | 684 |
| 685 case lir_tan: | |
| 686 case lir_sin: | |
|
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687 case lir_cos: |
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688 case lir_log: |
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689 case lir_log10: { |
| 0 | 690 assert(op->as_Op2() != NULL, "must be"); |
| 691 LIR_Op2* op2 = (LIR_Op2*)op; | |
| 692 | |
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693 // On x86 tan/sin/cos need two temporary fpu stack slots and |
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694 // log/log10 need one so handle opr2 and tmp as temp inputs. |
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695 // Register input operand as temp to guarantee that it doesn't |
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696 // overlap with the input. |
| 0 | 697 assert(op2->_info == NULL, "not used"); |
| 698 assert(op2->_opr1->is_valid(), "used"); | |
| 699 do_input(op2->_opr1); do_temp(op2->_opr1); | |
| 700 | |
| 701 if (op2->_opr2->is_valid()) do_temp(op2->_opr2); | |
| 702 if (op2->_tmp->is_valid()) do_temp(op2->_tmp); | |
| 703 if (op2->_result->is_valid()) do_output(op2->_result); | |
| 704 | |
| 705 break; | |
| 706 } | |
| 707 | |
| 708 | |
| 709 // LIR_Op3 | |
| 710 case lir_idiv: | |
| 711 case lir_irem: { | |
| 712 assert(op->as_Op3() != NULL, "must be"); | |
| 713 LIR_Op3* op3= (LIR_Op3*)op; | |
| 714 | |
| 715 if (op3->_info) do_info(op3->_info); | |
| 716 if (op3->_opr1->is_valid()) do_input(op3->_opr1); | |
| 717 | |
| 718 // second operand is input and temp, so ensure that second operand | |
| 719 // and third operand get not the same register | |
| 720 if (op3->_opr2->is_valid()) do_input(op3->_opr2); | |
| 721 if (op3->_opr2->is_valid()) do_temp(op3->_opr2); | |
| 722 if (op3->_opr3->is_valid()) do_temp(op3->_opr3); | |
| 723 | |
| 724 if (op3->_result->is_valid()) do_output(op3->_result); | |
| 725 | |
| 726 break; | |
| 727 } | |
| 728 | |
| 729 | |
| 730 // LIR_OpJavaCall | |
| 731 case lir_static_call: | |
| 732 case lir_optvirtual_call: | |
| 733 case lir_icvirtual_call: | |
| 1295 | 734 case lir_virtual_call: |
| 735 case lir_dynamic_call: { | |
| 736 LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall(); | |
| 737 assert(opJavaCall != NULL, "must be"); | |
| 0 | 738 |
| 739 if (opJavaCall->_receiver->is_valid()) do_input(opJavaCall->_receiver); | |
| 740 | |
| 741 // only visit register parameters | |
| 742 int n = opJavaCall->_arguments->length(); | |
| 743 for (int i = 0; i < n; i++) { | |
| 744 if (!opJavaCall->_arguments->at(i)->is_pointer()) { | |
| 745 do_input(*opJavaCall->_arguments->adr_at(i)); | |
| 746 } | |
| 747 } | |
| 748 | |
| 749 if (opJavaCall->_info) do_info(opJavaCall->_info); | |
| 1564 | 750 if (opJavaCall->is_method_handle_invoke()) { |
| 751 opJavaCall->_method_handle_invoke_SP_save_opr = FrameMap::method_handle_invoke_SP_save_opr(); | |
| 752 do_temp(opJavaCall->_method_handle_invoke_SP_save_opr); | |
| 753 } | |
| 0 | 754 do_call(); |
| 755 if (opJavaCall->_result->is_valid()) do_output(opJavaCall->_result); | |
| 756 | |
| 757 break; | |
| 758 } | |
| 759 | |
| 760 | |
| 761 // LIR_OpRTCall | |
| 762 case lir_rtcall: { | |
| 763 assert(op->as_OpRTCall() != NULL, "must be"); | |
| 764 LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op; | |
| 765 | |
| 766 // only visit register parameters | |
| 767 int n = opRTCall->_arguments->length(); | |
| 768 for (int i = 0; i < n; i++) { | |
| 769 if (!opRTCall->_arguments->at(i)->is_pointer()) { | |
| 770 do_input(*opRTCall->_arguments->adr_at(i)); | |
| 771 } | |
| 772 } | |
| 773 if (opRTCall->_info) do_info(opRTCall->_info); | |
| 774 if (opRTCall->_tmp->is_valid()) do_temp(opRTCall->_tmp); | |
| 775 do_call(); | |
| 776 if (opRTCall->_result->is_valid()) do_output(opRTCall->_result); | |
| 777 | |
| 778 break; | |
| 779 } | |
| 780 | |
| 781 | |
| 782 // LIR_OpArrayCopy | |
| 783 case lir_arraycopy: { | |
| 784 assert(op->as_OpArrayCopy() != NULL, "must be"); | |
| 785 LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op; | |
| 786 | |
| 787 assert(opArrayCopy->_result->is_illegal(), "unused"); | |
| 788 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src); | |
| 789 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos); | |
| 790 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst); | |
| 791 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos); | |
| 792 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length); | |
| 793 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp); | |
| 794 if (opArrayCopy->_info) do_info(opArrayCopy->_info); | |
| 795 | |
| 796 // the implementation of arraycopy always has a call into the runtime | |
| 797 do_call(); | |
| 798 | |
| 799 break; | |
| 800 } | |
| 801 | |
| 802 | |
| 803 // LIR_OpLock | |
| 804 case lir_lock: | |
| 805 case lir_unlock: { | |
| 806 assert(op->as_OpLock() != NULL, "must be"); | |
| 807 LIR_OpLock* opLock = (LIR_OpLock*)op; | |
| 808 | |
| 809 if (opLock->_info) do_info(opLock->_info); | |
| 810 | |
| 811 // TODO: check if these operands really have to be temp | |
| 812 // (or if input is sufficient). This may have influence on the oop map! | |
| 813 assert(opLock->_lock->is_valid(), "used"); do_temp(opLock->_lock); | |
| 814 assert(opLock->_hdr->is_valid(), "used"); do_temp(opLock->_hdr); | |
| 815 assert(opLock->_obj->is_valid(), "used"); do_temp(opLock->_obj); | |
| 816 | |
| 817 if (opLock->_scratch->is_valid()) do_temp(opLock->_scratch); | |
| 818 assert(opLock->_result->is_illegal(), "unused"); | |
| 819 | |
| 820 do_stub(opLock->_stub); | |
| 821 | |
| 822 break; | |
| 823 } | |
| 824 | |
| 825 | |
| 826 // LIR_OpDelay | |
| 827 case lir_delay_slot: { | |
| 828 assert(op->as_OpDelay() != NULL, "must be"); | |
| 829 LIR_OpDelay* opDelay = (LIR_OpDelay*)op; | |
| 830 | |
| 831 visit(opDelay->delay_op()); | |
| 832 break; | |
| 833 } | |
| 834 | |
| 835 // LIR_OpTypeCheck | |
| 836 case lir_instanceof: | |
| 837 case lir_checkcast: | |
| 838 case lir_store_check: { | |
| 839 assert(op->as_OpTypeCheck() != NULL, "must be"); | |
| 840 LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op; | |
| 841 | |
| 842 if (opTypeCheck->_info_for_exception) do_info(opTypeCheck->_info_for_exception); | |
| 843 if (opTypeCheck->_info_for_patch) do_info(opTypeCheck->_info_for_patch); | |
| 844 if (opTypeCheck->_object->is_valid()) do_input(opTypeCheck->_object); | |
| 845 if (opTypeCheck->_array->is_valid()) do_input(opTypeCheck->_array); | |
| 846 if (opTypeCheck->_tmp1->is_valid()) do_temp(opTypeCheck->_tmp1); | |
| 847 if (opTypeCheck->_tmp2->is_valid()) do_temp(opTypeCheck->_tmp2); | |
| 848 if (opTypeCheck->_tmp3->is_valid()) do_temp(opTypeCheck->_tmp3); | |
| 849 if (opTypeCheck->_result->is_valid()) do_output(opTypeCheck->_result); | |
| 850 do_stub(opTypeCheck->_stub); | |
| 851 break; | |
| 852 } | |
| 853 | |
| 854 // LIR_OpCompareAndSwap | |
| 855 case lir_cas_long: | |
| 856 case lir_cas_obj: | |
| 857 case lir_cas_int: { | |
| 858 assert(op->as_OpCompareAndSwap() != NULL, "must be"); | |
| 859 LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op; | |
| 860 | |
|
1681
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861 assert(opCompareAndSwap->_addr->is_valid(), "used"); |
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862 assert(opCompareAndSwap->_cmp_value->is_valid(), "used"); |
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863 assert(opCompareAndSwap->_new_value->is_valid(), "used"); |
| 0 | 864 if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info); |
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865 do_input(opCompareAndSwap->_addr); |
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866 do_temp(opCompareAndSwap->_addr); |
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867 do_input(opCompareAndSwap->_cmp_value); |
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868 do_temp(opCompareAndSwap->_cmp_value); |
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869 do_input(opCompareAndSwap->_new_value); |
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870 do_temp(opCompareAndSwap->_new_value); |
| 0 | 871 if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1); |
| 872 if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2); | |
| 873 if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result); | |
| 874 | |
| 875 break; | |
| 876 } | |
| 877 | |
| 878 | |
| 879 // LIR_OpAllocArray; | |
| 880 case lir_alloc_array: { | |
| 881 assert(op->as_OpAllocArray() != NULL, "must be"); | |
| 882 LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op; | |
| 883 | |
| 884 if (opAllocArray->_info) do_info(opAllocArray->_info); | |
| 885 if (opAllocArray->_klass->is_valid()) do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass); | |
| 886 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len); | |
| 887 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1); | |
| 888 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2); | |
| 889 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3); | |
| 890 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4); | |
| 891 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result); | |
| 892 do_stub(opAllocArray->_stub); | |
| 893 break; | |
| 894 } | |
| 895 | |
| 896 // LIR_OpProfileCall: | |
| 897 case lir_profile_call: { | |
| 898 assert(op->as_OpProfileCall() != NULL, "must be"); | |
| 899 LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op; | |
| 900 | |
| 901 if (opProfileCall->_recv->is_valid()) do_temp(opProfileCall->_recv); | |
| 902 assert(opProfileCall->_mdo->is_valid(), "used"); do_temp(opProfileCall->_mdo); | |
| 903 assert(opProfileCall->_tmp1->is_valid(), "used"); do_temp(opProfileCall->_tmp1); | |
| 904 break; | |
| 905 } | |
| 906 | |
| 907 default: | |
| 908 ShouldNotReachHere(); | |
| 909 } | |
| 910 } | |
| 911 | |
| 912 | |
| 913 void LIR_OpVisitState::do_stub(CodeStub* stub) { | |
| 914 if (stub != NULL) { | |
| 915 stub->visit(this); | |
| 916 } | |
| 917 } | |
| 918 | |
| 919 XHandlers* LIR_OpVisitState::all_xhandler() { | |
| 920 XHandlers* result = NULL; | |
| 921 | |
| 922 int i; | |
| 923 for (i = 0; i < info_count(); i++) { | |
| 924 if (info_at(i)->exception_handlers() != NULL) { | |
| 925 result = info_at(i)->exception_handlers(); | |
| 926 break; | |
| 927 } | |
| 928 } | |
| 929 | |
| 930 #ifdef ASSERT | |
| 931 for (i = 0; i < info_count(); i++) { | |
| 932 assert(info_at(i)->exception_handlers() == NULL || | |
| 933 info_at(i)->exception_handlers() == result, | |
| 934 "only one xhandler list allowed per LIR-operation"); | |
| 935 } | |
| 936 #endif | |
| 937 | |
| 938 if (result != NULL) { | |
| 939 return result; | |
| 940 } else { | |
| 941 return new XHandlers(); | |
| 942 } | |
| 943 | |
| 944 return result; | |
| 945 } | |
| 946 | |
| 947 | |
| 948 #ifdef ASSERT | |
| 949 bool LIR_OpVisitState::no_operands(LIR_Op* op) { | |
| 950 visit(op); | |
| 951 | |
| 952 return opr_count(inputMode) == 0 && | |
| 953 opr_count(outputMode) == 0 && | |
| 954 opr_count(tempMode) == 0 && | |
| 955 info_count() == 0 && | |
| 956 !has_call() && | |
| 957 !has_slow_case(); | |
| 958 } | |
| 959 #endif | |
| 960 | |
| 961 //--------------------------------------------------- | |
| 962 | |
| 963 | |
| 964 void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) { | |
| 965 masm->emit_call(this); | |
| 966 } | |
| 967 | |
| 968 void LIR_OpRTCall::emit_code(LIR_Assembler* masm) { | |
| 969 masm->emit_rtcall(this); | |
| 970 } | |
| 971 | |
| 972 void LIR_OpLabel::emit_code(LIR_Assembler* masm) { | |
| 973 masm->emit_opLabel(this); | |
| 974 } | |
| 975 | |
| 976 void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) { | |
| 977 masm->emit_arraycopy(this); | |
| 978 masm->emit_code_stub(stub()); | |
| 979 } | |
| 980 | |
| 981 void LIR_Op0::emit_code(LIR_Assembler* masm) { | |
| 982 masm->emit_op0(this); | |
| 983 } | |
| 984 | |
| 985 void LIR_Op1::emit_code(LIR_Assembler* masm) { | |
| 986 masm->emit_op1(this); | |
| 987 } | |
| 988 | |
| 989 void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) { | |
| 990 masm->emit_alloc_obj(this); | |
| 991 masm->emit_code_stub(stub()); | |
| 992 } | |
| 993 | |
| 994 void LIR_OpBranch::emit_code(LIR_Assembler* masm) { | |
| 995 masm->emit_opBranch(this); | |
| 996 if (stub()) { | |
| 997 masm->emit_code_stub(stub()); | |
| 998 } | |
| 999 } | |
| 1000 | |
| 1001 void LIR_OpConvert::emit_code(LIR_Assembler* masm) { | |
| 1002 masm->emit_opConvert(this); | |
| 1003 if (stub() != NULL) { | |
| 1004 masm->emit_code_stub(stub()); | |
| 1005 } | |
| 1006 } | |
| 1007 | |
| 1008 void LIR_Op2::emit_code(LIR_Assembler* masm) { | |
| 1009 masm->emit_op2(this); | |
| 1010 } | |
| 1011 | |
| 1012 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) { | |
| 1013 masm->emit_alloc_array(this); | |
| 1014 masm->emit_code_stub(stub()); | |
| 1015 } | |
| 1016 | |
| 1017 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) { | |
| 1018 masm->emit_opTypeCheck(this); | |
| 1019 if (stub()) { | |
| 1020 masm->emit_code_stub(stub()); | |
| 1021 } | |
| 1022 } | |
| 1023 | |
| 1024 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) { | |
| 1025 masm->emit_compare_and_swap(this); | |
| 1026 } | |
| 1027 | |
| 1028 void LIR_Op3::emit_code(LIR_Assembler* masm) { | |
| 1029 masm->emit_op3(this); | |
| 1030 } | |
| 1031 | |
| 1032 void LIR_OpLock::emit_code(LIR_Assembler* masm) { | |
| 1033 masm->emit_lock(this); | |
| 1034 if (stub()) { | |
| 1035 masm->emit_code_stub(stub()); | |
| 1036 } | |
| 1037 } | |
| 1038 | |
| 1039 | |
| 1040 void LIR_OpDelay::emit_code(LIR_Assembler* masm) { | |
| 1041 masm->emit_delay(this); | |
| 1042 } | |
| 1043 | |
| 1044 | |
| 1045 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) { | |
| 1046 masm->emit_profile_call(this); | |
| 1047 } | |
| 1048 | |
| 1049 | |
| 1050 // LIR_List | |
| 1051 LIR_List::LIR_List(Compilation* compilation, BlockBegin* block) | |
| 1052 : _operations(8) | |
| 1053 , _compilation(compilation) | |
| 1054 #ifndef PRODUCT | |
| 1055 , _block(block) | |
| 1056 #endif | |
| 1057 #ifdef ASSERT | |
| 1058 , _file(NULL) | |
| 1059 , _line(0) | |
| 1060 #endif | |
| 1061 { } | |
| 1062 | |
| 1063 | |
| 1064 #ifdef ASSERT | |
| 1065 void LIR_List::set_file_and_line(const char * file, int line) { | |
| 1066 const char * f = strrchr(file, '/'); | |
| 1067 if (f == NULL) f = strrchr(file, '\\'); | |
| 1068 if (f == NULL) { | |
| 1069 f = file; | |
| 1070 } else { | |
| 1071 f++; | |
| 1072 } | |
| 1073 _file = f; | |
| 1074 _line = line; | |
| 1075 } | |
| 1076 #endif | |
| 1077 | |
| 1078 | |
| 1079 void LIR_List::append(LIR_InsertionBuffer* buffer) { | |
| 1080 assert(this == buffer->lir_list(), "wrong lir list"); | |
| 1081 const int n = _operations.length(); | |
| 1082 | |
| 1083 if (buffer->number_of_ops() > 0) { | |
| 1084 // increase size of instructions list | |
| 1085 _operations.at_grow(n + buffer->number_of_ops() - 1, NULL); | |
| 1086 // insert ops from buffer into instructions list | |
| 1087 int op_index = buffer->number_of_ops() - 1; | |
| 1088 int ip_index = buffer->number_of_insertion_points() - 1; | |
| 1089 int from_index = n - 1; | |
| 1090 int to_index = _operations.length() - 1; | |
| 1091 for (; ip_index >= 0; ip_index --) { | |
| 1092 int index = buffer->index_at(ip_index); | |
| 1093 // make room after insertion point | |
| 1094 while (index < from_index) { | |
| 1095 _operations.at_put(to_index --, _operations.at(from_index --)); | |
| 1096 } | |
| 1097 // insert ops from buffer | |
| 1098 for (int i = buffer->count_at(ip_index); i > 0; i --) { | |
| 1099 _operations.at_put(to_index --, buffer->op_at(op_index --)); | |
| 1100 } | |
| 1101 } | |
| 1102 } | |
| 1103 | |
| 1104 buffer->finish(); | |
| 1105 } | |
| 1106 | |
| 1107 | |
| 1108 void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) { | |
| 1109 append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg, T_OBJECT, lir_patch_normal, info)); | |
| 1110 } | |
| 1111 | |
| 1112 | |
| 1113 void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) { | |
| 1114 append(new LIR_Op1( | |
| 1115 lir_move, | |
| 1116 LIR_OprFact::address(addr), | |
| 1117 src, | |
| 1118 addr->type(), | |
| 1119 patch_code, | |
| 1120 info)); | |
| 1121 } | |
| 1122 | |
| 1123 | |
| 1124 void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) { | |
| 1125 append(new LIR_Op1( | |
| 1126 lir_move, | |
| 1127 LIR_OprFact::address(address), | |
| 1128 dst, | |
| 1129 address->type(), | |
| 1130 patch_code, | |
| 1131 info, lir_move_volatile)); | |
| 1132 } | |
| 1133 | |
| 1134 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { | |
| 1135 append(new LIR_Op1( | |
| 1136 lir_move, | |
| 1137 LIR_OprFact::address(new LIR_Address(base, offset, type)), | |
| 1138 dst, | |
| 1139 type, | |
| 1140 patch_code, | |
| 1141 info, lir_move_volatile)); | |
| 1142 } | |
| 1143 | |
| 1144 | |
| 1145 void LIR_List::prefetch(LIR_Address* addr, bool is_store) { | |
| 1146 append(new LIR_Op1( | |
| 1147 is_store ? lir_prefetchw : lir_prefetchr, | |
| 1148 LIR_OprFact::address(addr))); | |
| 1149 } | |
| 1150 | |
| 1151 | |
| 1152 void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { | |
| 1153 append(new LIR_Op1( | |
| 1154 lir_move, | |
| 1155 LIR_OprFact::intConst(v), | |
| 1156 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)), | |
| 1157 type, | |
| 1158 patch_code, | |
| 1159 info)); | |
| 1160 } | |
| 1161 | |
| 1162 | |
| 1163 void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { | |
| 1164 append(new LIR_Op1( | |
| 1165 lir_move, | |
| 1166 LIR_OprFact::oopConst(o), | |
| 1167 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)), | |
| 1168 type, | |
| 1169 patch_code, | |
| 1170 info)); | |
| 1171 } | |
| 1172 | |
| 1173 | |
| 1174 void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) { | |
| 1175 append(new LIR_Op1( | |
| 1176 lir_move, | |
| 1177 src, | |
| 1178 LIR_OprFact::address(addr), | |
| 1179 addr->type(), | |
| 1180 patch_code, | |
| 1181 info)); | |
| 1182 } | |
| 1183 | |
| 1184 | |
| 1185 void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) { | |
| 1186 append(new LIR_Op1( | |
| 1187 lir_move, | |
| 1188 src, | |
| 1189 LIR_OprFact::address(addr), | |
| 1190 addr->type(), | |
| 1191 patch_code, | |
| 1192 info, | |
| 1193 lir_move_volatile)); | |
| 1194 } | |
| 1195 | |
| 1196 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { | |
| 1197 append(new LIR_Op1( | |
| 1198 lir_move, | |
| 1199 src, | |
| 1200 LIR_OprFact::address(new LIR_Address(base, offset, type)), | |
| 1201 type, | |
| 1202 patch_code, | |
| 1203 info, lir_move_volatile)); | |
| 1204 } | |
| 1205 | |
| 1206 | |
| 1207 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { | |
| 1208 append(new LIR_Op3( | |
| 1209 lir_idiv, | |
| 1210 left, | |
| 1211 right, | |
| 1212 tmp, | |
| 1213 res, | |
| 1214 info)); | |
| 1215 } | |
| 1216 | |
| 1217 | |
| 1218 void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { | |
| 1219 append(new LIR_Op3( | |
| 1220 lir_idiv, | |
| 1221 left, | |
| 1222 LIR_OprFact::intConst(right), | |
| 1223 tmp, | |
| 1224 res, | |
| 1225 info)); | |
| 1226 } | |
| 1227 | |
| 1228 | |
| 1229 void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { | |
| 1230 append(new LIR_Op3( | |
| 1231 lir_irem, | |
| 1232 left, | |
| 1233 right, | |
| 1234 tmp, | |
| 1235 res, | |
| 1236 info)); | |
| 1237 } | |
| 1238 | |
| 1239 | |
| 1240 void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { | |
| 1241 append(new LIR_Op3( | |
| 1242 lir_irem, | |
| 1243 left, | |
| 1244 LIR_OprFact::intConst(right), | |
| 1245 tmp, | |
| 1246 res, | |
| 1247 info)); | |
| 1248 } | |
| 1249 | |
| 1250 | |
| 1251 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) { | |
| 1252 append(new LIR_Op2( | |
| 1253 lir_cmp, | |
| 1254 condition, | |
| 1255 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)), | |
| 1256 LIR_OprFact::intConst(c), | |
| 1257 info)); | |
| 1258 } | |
| 1259 | |
| 1260 | |
| 1261 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) { | |
| 1262 append(new LIR_Op2( | |
| 1263 lir_cmp, | |
| 1264 condition, | |
| 1265 reg, | |
| 1266 LIR_OprFact::address(addr), | |
| 1267 info)); | |
| 1268 } | |
| 1269 | |
| 1270 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4, | |
| 1271 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) { | |
| 1272 append(new LIR_OpAllocObj( | |
| 1273 klass, | |
| 1274 dst, | |
| 1275 t1, | |
| 1276 t2, | |
| 1277 t3, | |
| 1278 t4, | |
| 1279 header_size, | |
| 1280 object_size, | |
| 1281 init_check, | |
| 1282 stub)); | |
| 1283 } | |
| 1284 | |
| 1285 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) { | |
| 1286 append(new LIR_OpAllocArray( | |
| 1287 klass, | |
| 1288 len, | |
| 1289 dst, | |
| 1290 t1, | |
| 1291 t2, | |
| 1292 t3, | |
| 1293 t4, | |
| 1294 type, | |
| 1295 stub)); | |
| 1296 } | |
| 1297 | |
| 1298 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { | |
| 1299 append(new LIR_Op2( | |
| 1300 lir_shl, | |
| 1301 value, | |
| 1302 count, | |
| 1303 dst, | |
| 1304 tmp)); | |
| 1305 } | |
| 1306 | |
| 1307 void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { | |
| 1308 append(new LIR_Op2( | |
| 1309 lir_shr, | |
| 1310 value, | |
| 1311 count, | |
| 1312 dst, | |
| 1313 tmp)); | |
| 1314 } | |
| 1315 | |
| 1316 | |
| 1317 void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { | |
| 1318 append(new LIR_Op2( | |
| 1319 lir_ushr, | |
| 1320 value, | |
| 1321 count, | |
| 1322 dst, | |
| 1323 tmp)); | |
| 1324 } | |
| 1325 | |
| 1326 void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) { | |
| 1327 append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i, | |
| 1328 left, | |
| 1329 right, | |
| 1330 dst)); | |
| 1331 } | |
| 1332 | |
| 1333 void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) { | |
| 1334 append(new LIR_OpLock( | |
| 1335 lir_lock, | |
| 1336 hdr, | |
| 1337 obj, | |
| 1338 lock, | |
| 1339 scratch, | |
| 1340 stub, | |
| 1341 info)); | |
| 1342 } | |
| 1343 | |
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1344 void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub) { |
| 0 | 1345 append(new LIR_OpLock( |
| 1346 lir_unlock, | |
| 1347 hdr, | |
| 1348 obj, | |
| 1349 lock, | |
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1350 scratch, |
| 0 | 1351 stub, |
| 1352 NULL)); | |
| 1353 } | |
| 1354 | |
| 1355 | |
| 1356 void check_LIR() { | |
| 1357 // cannot do the proper checking as PRODUCT and other modes return different results | |
| 1358 // guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table"); | |
| 1359 } | |
| 1360 | |
| 1361 | |
| 1362 | |
| 1363 void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass, | |
| 1364 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, | |
| 1365 CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub, | |
| 1366 ciMethod* profiled_method, int profiled_bci) { | |
| 1367 append(new LIR_OpTypeCheck(lir_checkcast, result, object, klass, | |
| 1368 tmp1, tmp2, tmp3, fast_check, info_for_exception, info_for_patch, stub, | |
| 1369 profiled_method, profiled_bci)); | |
| 1370 } | |
| 1371 | |
| 1372 | |
| 1373 void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch) { | |
| 1374 append(new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, NULL, info_for_patch, NULL, NULL, 0)); | |
| 1375 } | |
| 1376 | |
| 1377 | |
| 1378 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception) { | |
| 1379 append(new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception, NULL, 0)); | |
| 1380 } | |
| 1381 | |
| 1382 | |
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1383 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, |
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1384 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { |
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1385 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result)); |
| 0 | 1386 } |
| 1387 | |
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1388 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, |
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1389 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { |
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1390 append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result)); |
| 0 | 1391 } |
| 1392 | |
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1393 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, |
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1394 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { |
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1395 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result)); |
| 0 | 1396 } |
| 1397 | |
| 1398 | |
| 1399 #ifdef PRODUCT | |
| 1400 | |
| 1401 void print_LIR(BlockList* blocks) { | |
| 1402 } | |
| 1403 | |
| 1404 #else | |
| 1405 // LIR_OprDesc | |
| 1406 void LIR_OprDesc::print() const { | |
| 1407 print(tty); | |
| 1408 } | |
| 1409 | |
| 1410 void LIR_OprDesc::print(outputStream* out) const { | |
| 1411 if (is_illegal()) { | |
| 1412 return; | |
| 1413 } | |
| 1414 | |
| 1415 out->print("["); | |
| 1416 if (is_pointer()) { | |
| 1417 pointer()->print_value_on(out); | |
| 1418 } else if (is_single_stack()) { | |
| 1419 out->print("stack:%d", single_stack_ix()); | |
| 1420 } else if (is_double_stack()) { | |
| 1421 out->print("dbl_stack:%d",double_stack_ix()); | |
| 1422 } else if (is_virtual()) { | |
| 1423 out->print("R%d", vreg_number()); | |
| 1424 } else if (is_single_cpu()) { | |
| 1425 out->print(as_register()->name()); | |
| 1426 } else if (is_double_cpu()) { | |
| 1427 out->print(as_register_hi()->name()); | |
| 1428 out->print(as_register_lo()->name()); | |
| 304 | 1429 #if defined(X86) |
| 0 | 1430 } else if (is_single_xmm()) { |
| 1431 out->print(as_xmm_float_reg()->name()); | |
| 1432 } else if (is_double_xmm()) { | |
| 1433 out->print(as_xmm_double_reg()->name()); | |
| 1434 } else if (is_single_fpu()) { | |
| 1435 out->print("fpu%d", fpu_regnr()); | |
| 1436 } else if (is_double_fpu()) { | |
| 1437 out->print("fpu%d", fpu_regnrLo()); | |
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1438 #elif defined(ARM) |
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1439 } else if (is_single_fpu()) { |
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1440 out->print("s%d", fpu_regnr()); |
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1441 } else if (is_double_fpu()) { |
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1442 out->print("d%d", fpu_regnrLo() >> 1); |
| 0 | 1443 #else |
| 1444 } else if (is_single_fpu()) { | |
| 1445 out->print(as_float_reg()->name()); | |
| 1446 } else if (is_double_fpu()) { | |
| 1447 out->print(as_double_reg()->name()); | |
| 1448 #endif | |
| 1449 | |
| 1450 } else if (is_illegal()) { | |
| 1451 out->print("-"); | |
| 1452 } else { | |
| 1453 out->print("Unknown Operand"); | |
| 1454 } | |
| 1455 if (!is_illegal()) { | |
| 1456 out->print("|%c", type_char()); | |
| 1457 } | |
| 1458 if (is_register() && is_last_use()) { | |
| 1459 out->print("(last_use)"); | |
| 1460 } | |
| 1461 out->print("]"); | |
| 1462 } | |
| 1463 | |
| 1464 | |
| 1465 // LIR_Address | |
| 1466 void LIR_Const::print_value_on(outputStream* out) const { | |
| 1467 switch (type()) { | |
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1468 case T_ADDRESS:out->print("address:%d",as_jint()); break; |
| 0 | 1469 case T_INT: out->print("int:%d", as_jint()); break; |
| 1470 case T_LONG: out->print("lng:%lld", as_jlong()); break; | |
| 1471 case T_FLOAT: out->print("flt:%f", as_jfloat()); break; | |
| 1472 case T_DOUBLE: out->print("dbl:%f", as_jdouble()); break; | |
| 1473 case T_OBJECT: out->print("obj:0x%x", as_jobject()); break; | |
| 1474 default: out->print("%3d:0x%x",type(), as_jdouble()); break; | |
| 1475 } | |
| 1476 } | |
| 1477 | |
| 1478 // LIR_Address | |
| 1479 void LIR_Address::print_value_on(outputStream* out) const { | |
| 1480 out->print("Base:"); _base->print(out); | |
| 1481 if (!_index->is_illegal()) { | |
| 1482 out->print(" Index:"); _index->print(out); | |
| 1483 switch (scale()) { | |
| 1484 case times_1: break; | |
| 1485 case times_2: out->print(" * 2"); break; | |
| 1486 case times_4: out->print(" * 4"); break; | |
| 1487 case times_8: out->print(" * 8"); break; | |
| 1488 } | |
| 1489 } | |
| 1490 out->print(" Disp: %d", _disp); | |
| 1491 } | |
| 1492 | |
| 1493 // debug output of block header without InstructionPrinter | |
| 1494 // (because phi functions are not necessary for LIR) | |
| 1495 static void print_block(BlockBegin* x) { | |
| 1496 // print block id | |
| 1497 BlockEnd* end = x->end(); | |
| 1498 tty->print("B%d ", x->block_id()); | |
| 1499 | |
| 1500 // print flags | |
| 1501 if (x->is_set(BlockBegin::std_entry_flag)) tty->print("std "); | |
| 1502 if (x->is_set(BlockBegin::osr_entry_flag)) tty->print("osr "); | |
| 1503 if (x->is_set(BlockBegin::exception_entry_flag)) tty->print("ex "); | |
| 1504 if (x->is_set(BlockBegin::subroutine_entry_flag)) tty->print("jsr "); | |
| 1505 if (x->is_set(BlockBegin::backward_branch_target_flag)) tty->print("bb "); | |
| 1506 if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh "); | |
| 1507 if (x->is_set(BlockBegin::linear_scan_loop_end_flag)) tty->print("le "); | |
| 1508 | |
| 1509 // print block bci range | |
| 1510 tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->bci())); | |
| 1511 | |
| 1512 // print predecessors and successors | |
| 1513 if (x->number_of_preds() > 0) { | |
| 1514 tty->print("preds: "); | |
| 1515 for (int i = 0; i < x->number_of_preds(); i ++) { | |
| 1516 tty->print("B%d ", x->pred_at(i)->block_id()); | |
| 1517 } | |
| 1518 } | |
| 1519 | |
| 1520 if (x->number_of_sux() > 0) { | |
| 1521 tty->print("sux: "); | |
| 1522 for (int i = 0; i < x->number_of_sux(); i ++) { | |
| 1523 tty->print("B%d ", x->sux_at(i)->block_id()); | |
| 1524 } | |
| 1525 } | |
| 1526 | |
| 1527 // print exception handlers | |
| 1528 if (x->number_of_exception_handlers() > 0) { | |
| 1529 tty->print("xhandler: "); | |
| 1530 for (int i = 0; i < x->number_of_exception_handlers(); i++) { | |
| 1531 tty->print("B%d ", x->exception_handler_at(i)->block_id()); | |
| 1532 } | |
| 1533 } | |
| 1534 | |
| 1535 tty->cr(); | |
| 1536 } | |
| 1537 | |
| 1538 void print_LIR(BlockList* blocks) { | |
| 1539 tty->print_cr("LIR:"); | |
| 1540 int i; | |
| 1541 for (i = 0; i < blocks->length(); i++) { | |
| 1542 BlockBegin* bb = blocks->at(i); | |
| 1543 print_block(bb); | |
| 1544 tty->print("__id_Instruction___________________________________________"); tty->cr(); | |
| 1545 bb->lir()->print_instructions(); | |
| 1546 } | |
| 1547 } | |
| 1548 | |
| 1549 void LIR_List::print_instructions() { | |
| 1550 for (int i = 0; i < _operations.length(); i++) { | |
| 1551 _operations.at(i)->print(); tty->cr(); | |
| 1552 } | |
| 1553 tty->cr(); | |
| 1554 } | |
| 1555 | |
| 1556 // LIR_Ops printing routines | |
| 1557 // LIR_Op | |
| 1558 void LIR_Op::print_on(outputStream* out) const { | |
| 1559 if (id() != -1 || PrintCFGToFile) { | |
| 1560 out->print("%4d ", id()); | |
| 1561 } else { | |
| 1562 out->print(" "); | |
| 1563 } | |
| 1564 out->print(name()); out->print(" "); | |
| 1565 print_instr(out); | |
| 1566 if (info() != NULL) out->print(" [bci:%d]", info()->bci()); | |
| 1567 #ifdef ASSERT | |
| 1568 if (Verbose && _file != NULL) { | |
| 1569 out->print(" (%s:%d)", _file, _line); | |
| 1570 } | |
| 1571 #endif | |
| 1572 } | |
| 1573 | |
| 1574 const char * LIR_Op::name() const { | |
| 1575 const char* s = NULL; | |
| 1576 switch(code()) { | |
| 1577 // LIR_Op0 | |
| 1578 case lir_membar: s = "membar"; break; | |
| 1579 case lir_membar_acquire: s = "membar_acquire"; break; | |
| 1580 case lir_membar_release: s = "membar_release"; break; | |
| 1581 case lir_word_align: s = "word_align"; break; | |
| 1582 case lir_label: s = "label"; break; | |
| 1583 case lir_nop: s = "nop"; break; | |
| 1584 case lir_backwardbranch_target: s = "backbranch"; break; | |
| 1585 case lir_std_entry: s = "std_entry"; break; | |
| 1586 case lir_osr_entry: s = "osr_entry"; break; | |
| 1587 case lir_build_frame: s = "build_frm"; break; | |
| 1588 case lir_fpop_raw: s = "fpop_raw"; break; | |
| 1589 case lir_24bit_FPU: s = "24bit_FPU"; break; | |
| 1590 case lir_reset_FPU: s = "reset_FPU"; break; | |
| 1591 case lir_breakpoint: s = "breakpoint"; break; | |
| 1592 case lir_get_thread: s = "get_thread"; break; | |
| 1593 // LIR_Op1 | |
| 1594 case lir_fxch: s = "fxch"; break; | |
| 1595 case lir_fld: s = "fld"; break; | |
| 1596 case lir_ffree: s = "ffree"; break; | |
| 1597 case lir_push: s = "push"; break; | |
| 1598 case lir_pop: s = "pop"; break; | |
| 1599 case lir_null_check: s = "null_check"; break; | |
| 1600 case lir_return: s = "return"; break; | |
| 1601 case lir_safepoint: s = "safepoint"; break; | |
| 1602 case lir_neg: s = "neg"; break; | |
| 1603 case lir_leal: s = "leal"; break; | |
| 1604 case lir_branch: s = "branch"; break; | |
| 1605 case lir_cond_float_branch: s = "flt_cond_br"; break; | |
| 1606 case lir_move: s = "move"; break; | |
| 1607 case lir_roundfp: s = "roundfp"; break; | |
| 1608 case lir_rtcall: s = "rtcall"; break; | |
| 1609 case lir_throw: s = "throw"; break; | |
| 1610 case lir_unwind: s = "unwind"; break; | |
| 1611 case lir_convert: s = "convert"; break; | |
| 1612 case lir_alloc_object: s = "alloc_obj"; break; | |
| 1613 case lir_monaddr: s = "mon_addr"; break; | |
| 1614 // LIR_Op2 | |
| 1615 case lir_cmp: s = "cmp"; break; | |
| 1616 case lir_cmp_l2i: s = "cmp_l2i"; break; | |
| 1617 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break; | |
| 1618 case lir_cmp_fd2i: s = "comp_fd2i"; break; | |
| 1619 case lir_cmove: s = "cmove"; break; | |
| 1620 case lir_add: s = "add"; break; | |
| 1621 case lir_sub: s = "sub"; break; | |
| 1622 case lir_mul: s = "mul"; break; | |
| 1623 case lir_mul_strictfp: s = "mul_strictfp"; break; | |
| 1624 case lir_div: s = "div"; break; | |
| 1625 case lir_div_strictfp: s = "div_strictfp"; break; | |
| 1626 case lir_rem: s = "rem"; break; | |
| 1627 case lir_abs: s = "abs"; break; | |
| 1628 case lir_sqrt: s = "sqrt"; break; | |
| 1629 case lir_sin: s = "sin"; break; | |
| 1630 case lir_cos: s = "cos"; break; | |
| 1631 case lir_tan: s = "tan"; break; | |
| 1632 case lir_log: s = "log"; break; | |
| 1633 case lir_log10: s = "log10"; break; | |
| 1634 case lir_logic_and: s = "logic_and"; break; | |
| 1635 case lir_logic_or: s = "logic_or"; break; | |
| 1636 case lir_logic_xor: s = "logic_xor"; break; | |
| 1637 case lir_shl: s = "shift_left"; break; | |
| 1638 case lir_shr: s = "shift_right"; break; | |
| 1639 case lir_ushr: s = "ushift_right"; break; | |
| 1640 case lir_alloc_array: s = "alloc_array"; break; | |
| 1641 // LIR_Op3 | |
| 1642 case lir_idiv: s = "idiv"; break; | |
| 1643 case lir_irem: s = "irem"; break; | |
| 1644 // LIR_OpJavaCall | |
| 1645 case lir_static_call: s = "static"; break; | |
| 1646 case lir_optvirtual_call: s = "optvirtual"; break; | |
| 1647 case lir_icvirtual_call: s = "icvirtual"; break; | |
| 1648 case lir_virtual_call: s = "virtual"; break; | |
| 1295 | 1649 case lir_dynamic_call: s = "dynamic"; break; |
| 0 | 1650 // LIR_OpArrayCopy |
| 1651 case lir_arraycopy: s = "arraycopy"; break; | |
| 1652 // LIR_OpLock | |
| 1653 case lir_lock: s = "lock"; break; | |
| 1654 case lir_unlock: s = "unlock"; break; | |
| 1655 // LIR_OpDelay | |
| 1656 case lir_delay_slot: s = "delay"; break; | |
| 1657 // LIR_OpTypeCheck | |
| 1658 case lir_instanceof: s = "instanceof"; break; | |
| 1659 case lir_checkcast: s = "checkcast"; break; | |
| 1660 case lir_store_check: s = "store_check"; break; | |
| 1661 // LIR_OpCompareAndSwap | |
| 1662 case lir_cas_long: s = "cas_long"; break; | |
| 1663 case lir_cas_obj: s = "cas_obj"; break; | |
| 1664 case lir_cas_int: s = "cas_int"; break; | |
| 1665 // LIR_OpProfileCall | |
| 1666 case lir_profile_call: s = "profile_call"; break; | |
| 1667 | |
| 1668 case lir_none: ShouldNotReachHere();break; | |
| 1669 default: s = "illegal_op"; break; | |
| 1670 } | |
| 1671 return s; | |
| 1672 } | |
| 1673 | |
| 1674 // LIR_OpJavaCall | |
| 1675 void LIR_OpJavaCall::print_instr(outputStream* out) const { | |
| 1676 out->print("call: "); | |
| 1677 out->print("[addr: 0x%x]", address()); | |
| 1678 if (receiver()->is_valid()) { | |
| 1679 out->print(" [recv: "); receiver()->print(out); out->print("]"); | |
| 1680 } | |
| 1681 if (result_opr()->is_valid()) { | |
| 1682 out->print(" [result: "); result_opr()->print(out); out->print("]"); | |
| 1683 } | |
| 1684 } | |
| 1685 | |
| 1686 // LIR_OpLabel | |
| 1687 void LIR_OpLabel::print_instr(outputStream* out) const { | |
| 1688 out->print("[label:0x%x]", _label); | |
| 1689 } | |
| 1690 | |
| 1691 // LIR_OpArrayCopy | |
| 1692 void LIR_OpArrayCopy::print_instr(outputStream* out) const { | |
| 1693 src()->print(out); out->print(" "); | |
| 1694 src_pos()->print(out); out->print(" "); | |
| 1695 dst()->print(out); out->print(" "); | |
| 1696 dst_pos()->print(out); out->print(" "); | |
| 1697 length()->print(out); out->print(" "); | |
| 1698 tmp()->print(out); out->print(" "); | |
| 1699 } | |
| 1700 | |
| 1701 // LIR_OpCompareAndSwap | |
| 1702 void LIR_OpCompareAndSwap::print_instr(outputStream* out) const { | |
| 1703 addr()->print(out); out->print(" "); | |
| 1704 cmp_value()->print(out); out->print(" "); | |
| 1705 new_value()->print(out); out->print(" "); | |
| 1706 tmp1()->print(out); out->print(" "); | |
| 1707 tmp2()->print(out); out->print(" "); | |
| 1708 | |
| 1709 } | |
| 1710 | |
| 1711 // LIR_Op0 | |
| 1712 void LIR_Op0::print_instr(outputStream* out) const { | |
| 1713 result_opr()->print(out); | |
| 1714 } | |
| 1715 | |
| 1716 // LIR_Op1 | |
| 1717 const char * LIR_Op1::name() const { | |
| 1718 if (code() == lir_move) { | |
| 1719 switch (move_kind()) { | |
| 1720 case lir_move_normal: | |
| 1721 return "move"; | |
| 1722 case lir_move_unaligned: | |
| 1723 return "unaligned move"; | |
| 1724 case lir_move_volatile: | |
| 1725 return "volatile_move"; | |
| 1726 default: | |
| 1727 ShouldNotReachHere(); | |
| 1728 return "illegal_op"; | |
| 1729 } | |
| 1730 } else { | |
| 1731 return LIR_Op::name(); | |
| 1732 } | |
| 1733 } | |
| 1734 | |
| 1735 | |
| 1736 void LIR_Op1::print_instr(outputStream* out) const { | |
| 1737 _opr->print(out); out->print(" "); | |
| 1738 result_opr()->print(out); out->print(" "); | |
| 1739 print_patch_code(out, patch_code()); | |
| 1740 } | |
| 1741 | |
| 1742 | |
| 1743 // LIR_Op1 | |
| 1744 void LIR_OpRTCall::print_instr(outputStream* out) const { | |
| 1745 intx a = (intx)addr(); | |
| 1746 out->print(Runtime1::name_for_address(addr())); | |
| 1747 out->print(" "); | |
| 1748 tmp()->print(out); | |
| 1749 } | |
| 1750 | |
| 1751 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) { | |
| 1752 switch(code) { | |
| 1753 case lir_patch_none: break; | |
| 1754 case lir_patch_low: out->print("[patch_low]"); break; | |
| 1755 case lir_patch_high: out->print("[patch_high]"); break; | |
| 1756 case lir_patch_normal: out->print("[patch_normal]"); break; | |
| 1757 default: ShouldNotReachHere(); | |
| 1758 } | |
| 1759 } | |
| 1760 | |
| 1761 // LIR_OpBranch | |
| 1762 void LIR_OpBranch::print_instr(outputStream* out) const { | |
| 1763 print_condition(out, cond()); out->print(" "); | |
| 1764 if (block() != NULL) { | |
| 1765 out->print("[B%d] ", block()->block_id()); | |
| 1766 } else if (stub() != NULL) { | |
| 1767 out->print("["); | |
| 1768 stub()->print_name(out); | |
| 1769 out->print(": 0x%x]", stub()); | |
| 1770 if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->bci()); | |
| 1771 } else { | |
| 1772 out->print("[label:0x%x] ", label()); | |
| 1773 } | |
| 1774 if (ublock() != NULL) { | |
| 1775 out->print("unordered: [B%d] ", ublock()->block_id()); | |
| 1776 } | |
| 1777 } | |
| 1778 | |
| 1779 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) { | |
| 1780 switch(cond) { | |
| 1781 case lir_cond_equal: out->print("[EQ]"); break; | |
| 1782 case lir_cond_notEqual: out->print("[NE]"); break; | |
| 1783 case lir_cond_less: out->print("[LT]"); break; | |
| 1784 case lir_cond_lessEqual: out->print("[LE]"); break; | |
| 1785 case lir_cond_greaterEqual: out->print("[GE]"); break; | |
| 1786 case lir_cond_greater: out->print("[GT]"); break; | |
| 1787 case lir_cond_belowEqual: out->print("[BE]"); break; | |
| 1788 case lir_cond_aboveEqual: out->print("[AE]"); break; | |
| 1789 case lir_cond_always: out->print("[AL]"); break; | |
| 1790 default: out->print("[%d]",cond); break; | |
| 1791 } | |
| 1792 } | |
| 1793 | |
| 1794 // LIR_OpConvert | |
| 1795 void LIR_OpConvert::print_instr(outputStream* out) const { | |
| 1796 print_bytecode(out, bytecode()); | |
| 1797 in_opr()->print(out); out->print(" "); | |
| 1798 result_opr()->print(out); out->print(" "); | |
|
1681
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1799 #ifdef PPC |
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1800 if(tmp1()->is_valid()) { |
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1801 tmp1()->print(out); out->print(" "); |
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1802 tmp2()->print(out); out->print(" "); |
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1803 } |
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1804 #endif |
| 0 | 1805 } |
| 1806 | |
| 1807 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) { | |
| 1808 switch(code) { | |
| 1809 case Bytecodes::_d2f: out->print("[d2f] "); break; | |
| 1810 case Bytecodes::_d2i: out->print("[d2i] "); break; | |
| 1811 case Bytecodes::_d2l: out->print("[d2l] "); break; | |
| 1812 case Bytecodes::_f2d: out->print("[f2d] "); break; | |
| 1813 case Bytecodes::_f2i: out->print("[f2i] "); break; | |
| 1814 case Bytecodes::_f2l: out->print("[f2l] "); break; | |
| 1815 case Bytecodes::_i2b: out->print("[i2b] "); break; | |
| 1816 case Bytecodes::_i2c: out->print("[i2c] "); break; | |
| 1817 case Bytecodes::_i2d: out->print("[i2d] "); break; | |
| 1818 case Bytecodes::_i2f: out->print("[i2f] "); break; | |
| 1819 case Bytecodes::_i2l: out->print("[i2l] "); break; | |
| 1820 case Bytecodes::_i2s: out->print("[i2s] "); break; | |
| 1821 case Bytecodes::_l2i: out->print("[l2i] "); break; | |
| 1822 case Bytecodes::_l2f: out->print("[l2f] "); break; | |
| 1823 case Bytecodes::_l2d: out->print("[l2d] "); break; | |
| 1824 default: | |
| 1825 out->print("[?%d]",code); | |
| 1826 break; | |
| 1827 } | |
| 1828 } | |
| 1829 | |
| 1830 void LIR_OpAllocObj::print_instr(outputStream* out) const { | |
| 1831 klass()->print(out); out->print(" "); | |
| 1832 obj()->print(out); out->print(" "); | |
| 1833 tmp1()->print(out); out->print(" "); | |
| 1834 tmp2()->print(out); out->print(" "); | |
| 1835 tmp3()->print(out); out->print(" "); | |
| 1836 tmp4()->print(out); out->print(" "); | |
| 1837 out->print("[hdr:%d]", header_size()); out->print(" "); | |
| 1838 out->print("[obj:%d]", object_size()); out->print(" "); | |
| 1839 out->print("[lbl:0x%x]", stub()->entry()); | |
| 1840 } | |
| 1841 | |
| 1842 void LIR_OpRoundFP::print_instr(outputStream* out) const { | |
| 1843 _opr->print(out); out->print(" "); | |
| 1844 tmp()->print(out); out->print(" "); | |
| 1845 result_opr()->print(out); out->print(" "); | |
| 1846 } | |
| 1847 | |
| 1848 // LIR_Op2 | |
| 1849 void LIR_Op2::print_instr(outputStream* out) const { | |
| 1850 if (code() == lir_cmove) { | |
| 1851 print_condition(out, condition()); out->print(" "); | |
| 1852 } | |
| 1853 in_opr1()->print(out); out->print(" "); | |
| 1854 in_opr2()->print(out); out->print(" "); | |
| 1855 if (tmp_opr()->is_valid()) { tmp_opr()->print(out); out->print(" "); } | |
| 1856 result_opr()->print(out); | |
| 1857 } | |
| 1858 | |
| 1859 void LIR_OpAllocArray::print_instr(outputStream* out) const { | |
| 1860 klass()->print(out); out->print(" "); | |
| 1861 len()->print(out); out->print(" "); | |
| 1862 obj()->print(out); out->print(" "); | |
| 1863 tmp1()->print(out); out->print(" "); | |
| 1864 tmp2()->print(out); out->print(" "); | |
| 1865 tmp3()->print(out); out->print(" "); | |
| 1866 tmp4()->print(out); out->print(" "); | |
| 1867 out->print("[type:0x%x]", type()); out->print(" "); | |
| 1868 out->print("[label:0x%x]", stub()->entry()); | |
| 1869 } | |
| 1870 | |
| 1871 | |
| 1872 void LIR_OpTypeCheck::print_instr(outputStream* out) const { | |
| 1873 object()->print(out); out->print(" "); | |
| 1874 if (code() == lir_store_check) { | |
| 1875 array()->print(out); out->print(" "); | |
| 1876 } | |
| 1877 if (code() != lir_store_check) { | |
| 1878 klass()->print_name_on(out); out->print(" "); | |
| 1879 if (fast_check()) out->print("fast_check "); | |
| 1880 } | |
| 1881 tmp1()->print(out); out->print(" "); | |
| 1882 tmp2()->print(out); out->print(" "); | |
| 1883 tmp3()->print(out); out->print(" "); | |
| 1884 result_opr()->print(out); out->print(" "); | |
| 1885 if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->bci()); | |
| 1886 } | |
| 1887 | |
| 1888 | |
| 1889 // LIR_Op3 | |
| 1890 void LIR_Op3::print_instr(outputStream* out) const { | |
| 1891 in_opr1()->print(out); out->print(" "); | |
| 1892 in_opr2()->print(out); out->print(" "); | |
| 1893 in_opr3()->print(out); out->print(" "); | |
| 1894 result_opr()->print(out); | |
| 1895 } | |
| 1896 | |
| 1897 | |
| 1898 void LIR_OpLock::print_instr(outputStream* out) const { | |
| 1899 hdr_opr()->print(out); out->print(" "); | |
| 1900 obj_opr()->print(out); out->print(" "); | |
| 1901 lock_opr()->print(out); out->print(" "); | |
| 1902 if (_scratch->is_valid()) { | |
| 1903 _scratch->print(out); out->print(" "); | |
| 1904 } | |
| 1905 out->print("[lbl:0x%x]", stub()->entry()); | |
| 1906 } | |
| 1907 | |
| 1908 | |
| 1909 void LIR_OpDelay::print_instr(outputStream* out) const { | |
| 1910 _op->print_on(out); | |
| 1911 } | |
| 1912 | |
| 1913 | |
| 1914 // LIR_OpProfileCall | |
| 1915 void LIR_OpProfileCall::print_instr(outputStream* out) const { | |
| 1916 profiled_method()->name()->print_symbol_on(out); | |
| 1917 out->print("."); | |
| 1918 profiled_method()->holder()->name()->print_symbol_on(out); | |
| 1919 out->print(" @ %d ", profiled_bci()); | |
| 1920 mdo()->print(out); out->print(" "); | |
| 1921 recv()->print(out); out->print(" "); | |
| 1922 tmp1()->print(out); out->print(" "); | |
| 1923 } | |
| 1924 | |
| 1925 | |
| 1926 #endif // PRODUCT | |
| 1927 | |
| 1928 // Implementation of LIR_InsertionBuffer | |
| 1929 | |
| 1930 void LIR_InsertionBuffer::append(int index, LIR_Op* op) { | |
| 1931 assert(_index_and_count.length() % 2 == 0, "must have a count for each index"); | |
| 1932 | |
| 1933 int i = number_of_insertion_points() - 1; | |
| 1934 if (i < 0 || index_at(i) < index) { | |
| 1935 append_new(index, 1); | |
| 1936 } else { | |
| 1937 assert(index_at(i) == index, "can append LIR_Ops in ascending order only"); | |
| 1938 assert(count_at(i) > 0, "check"); | |
| 1939 set_count_at(i, count_at(i) + 1); | |
| 1940 } | |
| 1941 _ops.push(op); | |
| 1942 | |
| 1943 DEBUG_ONLY(verify()); | |
| 1944 } | |
| 1945 | |
| 1946 #ifdef ASSERT | |
| 1947 void LIR_InsertionBuffer::verify() { | |
| 1948 int sum = 0; | |
| 1949 int prev_idx = -1; | |
| 1950 | |
| 1951 for (int i = 0; i < number_of_insertion_points(); i++) { | |
| 1952 assert(prev_idx < index_at(i), "index must be ordered ascending"); | |
| 1953 sum += count_at(i); | |
| 1954 } | |
| 1955 assert(sum == number_of_ops(), "wrong total sum"); | |
| 1956 } | |
| 1957 #endif |