Mercurial > hg > graal-compiler
annotate src/cpu/sparc/vm/c1_LIRAssembler_sparc.cpp @ 989:148e5441d916
6863023: need non-perm oops in code cache for JSR 292
Summary: Make a special root-list for those few nmethods which might contain non-perm oops.
Reviewed-by: twisti, kvn, never, jmasa, ysr
| author | jrose |
|---|---|
| date | Tue, 15 Sep 2009 21:53:47 -0700 |
| parents | c96bf21b756f |
| children | 323bd24c6520 |
| rev | line source |
|---|---|
| 0 | 1 /* |
|
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
644
diff
changeset
|
2 * Copyright 2000-2009 Sun Microsystems, Inc. All Rights Reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
| 19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 20 * CA 95054 USA or visit www.sun.com if you need additional information or | |
| 21 * have any questions. | |
| 22 * | |
| 23 */ | |
| 24 | |
| 25 # include "incls/_precompiled.incl" | |
| 26 # include "incls/_c1_LIRAssembler_sparc.cpp.incl" | |
| 27 | |
| 28 #define __ _masm-> | |
| 29 | |
| 30 | |
| 31 //------------------------------------------------------------ | |
| 32 | |
| 33 | |
| 34 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { | |
| 35 if (opr->is_constant()) { | |
| 36 LIR_Const* constant = opr->as_constant_ptr(); | |
| 37 switch (constant->type()) { | |
| 38 case T_INT: { | |
| 39 jint value = constant->as_jint(); | |
| 40 return Assembler::is_simm13(value); | |
| 41 } | |
| 42 | |
| 43 default: | |
| 44 return false; | |
| 45 } | |
| 46 } | |
| 47 return false; | |
| 48 } | |
| 49 | |
| 50 | |
| 51 bool LIR_Assembler::is_single_instruction(LIR_Op* op) { | |
| 52 switch (op->code()) { | |
| 53 case lir_null_check: | |
| 54 return true; | |
| 55 | |
| 56 | |
| 57 case lir_add: | |
| 58 case lir_ushr: | |
| 59 case lir_shr: | |
| 60 case lir_shl: | |
| 61 // integer shifts and adds are always one instruction | |
| 62 return op->result_opr()->is_single_cpu(); | |
| 63 | |
| 64 | |
| 65 case lir_move: { | |
| 66 LIR_Op1* op1 = op->as_Op1(); | |
| 67 LIR_Opr src = op1->in_opr(); | |
| 68 LIR_Opr dst = op1->result_opr(); | |
| 69 | |
| 70 if (src == dst) { | |
| 71 NEEDS_CLEANUP; | |
| 72 // this works around a problem where moves with the same src and dst | |
| 73 // end up in the delay slot and then the assembler swallows the mov | |
| 74 // since it has no effect and then it complains because the delay slot | |
| 75 // is empty. returning false stops the optimizer from putting this in | |
| 76 // the delay slot | |
| 77 return false; | |
| 78 } | |
| 79 | |
| 80 // don't put moves involving oops into the delay slot since the VerifyOops code | |
| 81 // will make it much larger than a single instruction. | |
| 82 if (VerifyOops) { | |
| 83 return false; | |
| 84 } | |
| 85 | |
| 86 if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none || | |
| 87 ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) { | |
| 88 return false; | |
| 89 } | |
| 90 | |
| 91 if (dst->is_register()) { | |
| 92 if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) { | |
| 93 return !PatchALot; | |
| 94 } else if (src->is_single_stack()) { | |
| 95 return true; | |
| 96 } | |
| 97 } | |
| 98 | |
| 99 if (src->is_register()) { | |
| 100 if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) { | |
| 101 return !PatchALot; | |
| 102 } else if (dst->is_single_stack()) { | |
| 103 return true; | |
| 104 } | |
| 105 } | |
| 106 | |
| 107 if (dst->is_register() && | |
| 108 ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) || | |
| 109 (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) { | |
| 110 return true; | |
| 111 } | |
| 112 | |
| 113 return false; | |
| 114 } | |
| 115 | |
| 116 default: | |
| 117 return false; | |
| 118 } | |
| 119 ShouldNotReachHere(); | |
| 120 } | |
| 121 | |
| 122 | |
| 123 LIR_Opr LIR_Assembler::receiverOpr() { | |
| 124 return FrameMap::O0_oop_opr; | |
| 125 } | |
| 126 | |
| 127 | |
| 128 LIR_Opr LIR_Assembler::incomingReceiverOpr() { | |
| 129 return FrameMap::I0_oop_opr; | |
| 130 } | |
| 131 | |
| 132 | |
| 133 LIR_Opr LIR_Assembler::osrBufferPointer() { | |
| 134 return FrameMap::I0_opr; | |
| 135 } | |
| 136 | |
| 137 | |
| 138 int LIR_Assembler::initial_frame_size_in_bytes() { | |
| 139 return in_bytes(frame_map()->framesize_in_bytes()); | |
| 140 } | |
| 141 | |
| 142 | |
| 143 // inline cache check: the inline cached class is in G5_inline_cache_reg(G5); | |
| 144 // we fetch the class of the receiver (O0) and compare it with the cached class. | |
| 145 // If they do not match we jump to slow case. | |
| 146 int LIR_Assembler::check_icache() { | |
| 147 int offset = __ offset(); | |
| 148 __ inline_cache_check(O0, G5_inline_cache_reg); | |
| 149 return offset; | |
| 150 } | |
| 151 | |
| 152 | |
| 153 void LIR_Assembler::osr_entry() { | |
| 154 // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp): | |
| 155 // | |
| 156 // 1. Create a new compiled activation. | |
| 157 // 2. Initialize local variables in the compiled activation. The expression stack must be empty | |
| 158 // at the osr_bci; it is not initialized. | |
| 159 // 3. Jump to the continuation address in compiled code to resume execution. | |
| 160 | |
| 161 // OSR entry point | |
| 162 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); | |
| 163 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); | |
| 164 ValueStack* entry_state = osr_entry->end()->state(); | |
| 165 int number_of_locks = entry_state->locks_size(); | |
| 166 | |
| 167 // Create a frame for the compiled activation. | |
| 168 __ build_frame(initial_frame_size_in_bytes()); | |
| 169 | |
| 170 // OSR buffer is | |
| 171 // | |
| 172 // locals[nlocals-1..0] | |
| 173 // monitors[number_of_locks-1..0] | |
| 174 // | |
| 175 // locals is a direct copy of the interpreter frame so in the osr buffer | |
| 176 // so first slot in the local array is the last local from the interpreter | |
| 177 // and last slot is local[0] (receiver) from the interpreter | |
| 178 // | |
| 179 // Similarly with locks. The first lock slot in the osr buffer is the nth lock | |
| 180 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock | |
| 181 // in the interpreter frame (the method lock if a sync method) | |
| 182 | |
| 183 // Initialize monitors in the compiled activation. | |
| 184 // I0: pointer to osr buffer | |
| 185 // | |
| 186 // All other registers are dead at this point and the locals will be | |
| 187 // copied into place by code emitted in the IR. | |
| 188 | |
| 189 Register OSR_buf = osrBufferPointer()->as_register(); | |
| 190 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); | |
| 191 int monitor_offset = BytesPerWord * method()->max_locals() + | |
| 192 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1); | |
| 193 for (int i = 0; i < number_of_locks; i++) { | |
| 194 int slot_offset = monitor_offset - ((i * BasicObjectLock::size()) * BytesPerWord); | |
| 195 #ifdef ASSERT | |
| 196 // verify the interpreter's monitor has a non-null object | |
| 197 { | |
| 198 Label L; | |
| 727 | 199 __ ld_ptr(OSR_buf, slot_offset + BasicObjectLock::obj_offset_in_bytes(), O7); |
| 0 | 200 __ cmp(G0, O7); |
| 201 __ br(Assembler::notEqual, false, Assembler::pt, L); | |
| 202 __ delayed()->nop(); | |
| 203 __ stop("locked object is NULL"); | |
| 204 __ bind(L); | |
| 205 } | |
| 206 #endif // ASSERT | |
| 207 // Copy the lock field into the compiled activation. | |
| 727 | 208 __ ld_ptr(OSR_buf, slot_offset + BasicObjectLock::lock_offset_in_bytes(), O7); |
| 0 | 209 __ st_ptr(O7, frame_map()->address_for_monitor_lock(i)); |
| 727 | 210 __ ld_ptr(OSR_buf, slot_offset + BasicObjectLock::obj_offset_in_bytes(), O7); |
| 0 | 211 __ st_ptr(O7, frame_map()->address_for_monitor_object(i)); |
| 212 } | |
| 213 } | |
| 214 } | |
| 215 | |
| 216 | |
| 217 // Optimized Library calls | |
| 218 // This is the fast version of java.lang.String.compare; it has not | |
| 219 // OSR-entry and therefore, we generate a slow version for OSR's | |
| 220 void LIR_Assembler::emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst, CodeEmitInfo* info) { | |
| 221 Register str0 = left->as_register(); | |
| 222 Register str1 = right->as_register(); | |
| 223 | |
| 224 Label Ldone; | |
| 225 | |
| 226 Register result = dst->as_register(); | |
| 227 { | |
| 228 // Get a pointer to the first character of string0 in tmp0 and get string0.count in str0 | |
| 229 // Get a pointer to the first character of string1 in tmp1 and get string1.count in str1 | |
| 230 // Also, get string0.count-string1.count in o7 and get the condition code set | |
| 231 // Note: some instructions have been hoisted for better instruction scheduling | |
| 232 | |
| 233 Register tmp0 = L0; | |
| 234 Register tmp1 = L1; | |
| 235 Register tmp2 = L2; | |
| 236 | |
| 237 int value_offset = java_lang_String:: value_offset_in_bytes(); // char array | |
| 238 int offset_offset = java_lang_String::offset_offset_in_bytes(); // first character position | |
| 239 int count_offset = java_lang_String:: count_offset_in_bytes(); | |
| 240 | |
| 727 | 241 __ ld_ptr(str0, value_offset, tmp0); |
| 242 __ ld(str0, offset_offset, tmp2); | |
| 0 | 243 __ add(tmp0, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp0); |
| 727 | 244 __ ld(str0, count_offset, str0); |
| 0 | 245 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2); |
| 246 | |
| 247 // str1 may be null | |
| 248 add_debug_info_for_null_check_here(info); | |
| 249 | |
| 727 | 250 __ ld_ptr(str1, value_offset, tmp1); |
| 0 | 251 __ add(tmp0, tmp2, tmp0); |
| 252 | |
| 727 | 253 __ ld(str1, offset_offset, tmp2); |
| 0 | 254 __ add(tmp1, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1); |
| 727 | 255 __ ld(str1, count_offset, str1); |
| 0 | 256 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2); |
| 257 __ subcc(str0, str1, O7); | |
| 258 __ add(tmp1, tmp2, tmp1); | |
| 259 } | |
| 260 | |
| 261 { | |
| 262 // Compute the minimum of the string lengths, scale it and store it in limit | |
| 263 Register count0 = I0; | |
| 264 Register count1 = I1; | |
| 265 Register limit = L3; | |
| 266 | |
| 267 Label Lskip; | |
| 268 __ sll(count0, exact_log2(sizeof(jchar)), limit); // string0 is shorter | |
| 269 __ br(Assembler::greater, true, Assembler::pt, Lskip); | |
| 270 __ delayed()->sll(count1, exact_log2(sizeof(jchar)), limit); // string1 is shorter | |
| 271 __ bind(Lskip); | |
| 272 | |
| 273 // If either string is empty (or both of them) the result is the difference in lengths | |
| 274 __ cmp(limit, 0); | |
| 275 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
| 276 __ delayed()->mov(O7, result); // result is difference in lengths | |
| 277 } | |
| 278 | |
| 279 { | |
| 280 // Neither string is empty | |
| 281 Label Lloop; | |
| 282 | |
| 283 Register base0 = L0; | |
| 284 Register base1 = L1; | |
| 285 Register chr0 = I0; | |
| 286 Register chr1 = I1; | |
| 287 Register limit = L3; | |
| 288 | |
| 289 // Shift base0 and base1 to the end of the arrays, negate limit | |
| 290 __ add(base0, limit, base0); | |
| 291 __ add(base1, limit, base1); | |
| 292 __ neg(limit); // limit = -min{string0.count, strin1.count} | |
| 293 | |
| 294 __ lduh(base0, limit, chr0); | |
| 295 __ bind(Lloop); | |
| 296 __ lduh(base1, limit, chr1); | |
| 297 __ subcc(chr0, chr1, chr0); | |
| 298 __ br(Assembler::notZero, false, Assembler::pn, Ldone); | |
| 299 assert(chr0 == result, "result must be pre-placed"); | |
| 300 __ delayed()->inccc(limit, sizeof(jchar)); | |
| 301 __ br(Assembler::notZero, true, Assembler::pt, Lloop); | |
| 302 __ delayed()->lduh(base0, limit, chr0); | |
| 303 } | |
| 304 | |
| 305 // If strings are equal up to min length, return the length difference. | |
| 306 __ mov(O7, result); | |
| 307 | |
| 308 // Otherwise, return the difference between the first mismatched chars. | |
| 309 __ bind(Ldone); | |
| 310 } | |
| 311 | |
| 312 | |
| 313 // -------------------------------------------------------------------------------------------- | |
| 314 | |
| 315 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no) { | |
| 316 if (!GenerateSynchronizationCode) return; | |
| 317 | |
| 318 Register obj_reg = obj_opr->as_register(); | |
| 319 Register lock_reg = lock_opr->as_register(); | |
| 320 | |
| 321 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no); | |
| 322 Register reg = mon_addr.base(); | |
| 323 int offset = mon_addr.disp(); | |
| 324 // compute pointer to BasicLock | |
| 325 if (mon_addr.is_simm13()) { | |
| 326 __ add(reg, offset, lock_reg); | |
| 327 } | |
| 328 else { | |
| 329 __ set(offset, lock_reg); | |
| 330 __ add(reg, lock_reg, lock_reg); | |
| 331 } | |
| 332 // unlock object | |
| 333 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, UseFastLocking, monitor_no); | |
| 334 // _slow_case_stubs->append(slow_case); | |
| 335 // temporary fix: must be created after exceptionhandler, therefore as call stub | |
| 336 _slow_case_stubs->append(slow_case); | |
| 337 if (UseFastLocking) { | |
| 338 // try inlined fast unlocking first, revert to slow locking if it fails | |
| 339 // note: lock_reg points to the displaced header since the displaced header offset is 0! | |
| 340 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); | |
| 341 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry()); | |
| 342 } else { | |
| 343 // always do slow unlocking | |
| 344 // note: the slow unlocking code could be inlined here, however if we use | |
| 345 // slow unlocking, speed doesn't matter anyway and this solution is | |
| 346 // simpler and requires less duplicated code - additionally, the | |
| 347 // slow unlocking code is the same in either case which simplifies | |
| 348 // debugging | |
| 349 __ br(Assembler::always, false, Assembler::pt, *slow_case->entry()); | |
| 350 __ delayed()->nop(); | |
| 351 } | |
| 352 // done | |
| 353 __ bind(*slow_case->continuation()); | |
| 354 } | |
| 355 | |
| 356 | |
| 357 void LIR_Assembler::emit_exception_handler() { | |
| 358 // if the last instruction is a call (typically to do a throw which | |
| 359 // is coming at the end after block reordering) the return address | |
| 360 // must still point into the code area in order to avoid assertion | |
| 361 // failures when searching for the corresponding bci => add a nop | |
| 362 // (was bug 5/14/1999 - gri) | |
| 363 __ nop(); | |
| 364 | |
| 365 // generate code for exception handler | |
| 366 ciMethod* method = compilation()->method(); | |
| 367 | |
| 368 address handler_base = __ start_a_stub(exception_handler_size); | |
| 369 | |
| 370 if (handler_base == NULL) { | |
| 371 // not enough space left for the handler | |
| 372 bailout("exception handler overflow"); | |
| 373 return; | |
| 374 } | |
| 375 #ifdef ASSERT | |
| 376 int offset = code_offset(); | |
| 377 #endif // ASSERT | |
| 378 compilation()->offsets()->set_value(CodeOffsets::Exceptions, code_offset()); | |
| 379 | |
| 380 | |
|
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c96bf21b756f
6788527: Server vm intermittently fails with assertion "live value must not be garbage" with fastdebug bits
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parents:
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381 if (compilation()->has_exception_handlers() || compilation()->env()->jvmti_can_post_exceptions()) { |
| 0 | 382 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type); |
| 383 __ delayed()->nop(); | |
| 384 } | |
| 385 | |
| 386 __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type); | |
| 387 __ delayed()->nop(); | |
| 388 debug_only(__ stop("should have gone to the caller");) | |
| 389 assert(code_offset() - offset <= exception_handler_size, "overflow"); | |
| 390 | |
| 391 __ end_a_stub(); | |
| 392 } | |
| 393 | |
| 394 void LIR_Assembler::emit_deopt_handler() { | |
| 395 // if the last instruction is a call (typically to do a throw which | |
| 396 // is coming at the end after block reordering) the return address | |
| 397 // must still point into the code area in order to avoid assertion | |
| 398 // failures when searching for the corresponding bci => add a nop | |
| 399 // (was bug 5/14/1999 - gri) | |
| 400 __ nop(); | |
| 401 | |
| 402 // generate code for deopt handler | |
| 403 ciMethod* method = compilation()->method(); | |
| 404 address handler_base = __ start_a_stub(deopt_handler_size); | |
| 405 if (handler_base == NULL) { | |
| 406 // not enough space left for the handler | |
| 407 bailout("deopt handler overflow"); | |
| 408 return; | |
| 409 } | |
| 410 #ifdef ASSERT | |
| 411 int offset = code_offset(); | |
| 412 #endif // ASSERT | |
| 413 compilation()->offsets()->set_value(CodeOffsets::Deopt, code_offset()); | |
| 414 | |
| 727 | 415 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); |
| 416 | |
| 417 __ JUMP(deopt_blob, G3_scratch, 0); // sethi;jmp | |
| 0 | 418 __ delayed()->nop(); |
| 419 | |
| 420 assert(code_offset() - offset <= deopt_handler_size, "overflow"); | |
| 421 | |
| 422 debug_only(__ stop("should have gone to the caller");) | |
| 423 | |
| 424 __ end_a_stub(); | |
| 425 } | |
| 426 | |
| 427 | |
| 428 void LIR_Assembler::jobject2reg(jobject o, Register reg) { | |
| 429 if (o == NULL) { | |
| 430 __ set(NULL_WORD, reg); | |
| 431 } else { | |
| 432 int oop_index = __ oop_recorder()->find_index(o); | |
| 433 RelocationHolder rspec = oop_Relocation::spec(oop_index); | |
| 434 __ set(NULL_WORD, reg, rspec); // Will be set when the nmethod is created | |
| 435 } | |
| 436 } | |
| 437 | |
| 438 | |
| 439 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) { | |
| 440 // Allocate a new index in oop table to hold the oop once it's been patched | |
| 441 int oop_index = __ oop_recorder()->allocate_index((jobject)NULL); | |
| 442 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, oop_index); | |
| 443 | |
| 727 | 444 AddressLiteral addrlit(NULL, oop_Relocation::spec(oop_index)); |
| 445 assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc"); | |
| 0 | 446 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the |
| 447 // NULL will be dynamically patched later and the patched value may be large. We must | |
| 448 // therefore generate the sethi/add as a placeholders | |
| 727 | 449 __ patchable_set(addrlit, reg); |
| 0 | 450 |
| 451 patching_epilog(patch, lir_patch_normal, reg, info); | |
| 452 } | |
| 453 | |
| 454 | |
| 455 void LIR_Assembler::emit_op3(LIR_Op3* op) { | |
| 456 Register Rdividend = op->in_opr1()->as_register(); | |
| 457 Register Rdivisor = noreg; | |
| 458 Register Rscratch = op->in_opr3()->as_register(); | |
| 459 Register Rresult = op->result_opr()->as_register(); | |
| 460 int divisor = -1; | |
| 461 | |
| 462 if (op->in_opr2()->is_register()) { | |
| 463 Rdivisor = op->in_opr2()->as_register(); | |
| 464 } else { | |
| 465 divisor = op->in_opr2()->as_constant_ptr()->as_jint(); | |
| 466 assert(Assembler::is_simm13(divisor), "can only handle simm13"); | |
| 467 } | |
| 468 | |
| 469 assert(Rdividend != Rscratch, ""); | |
| 470 assert(Rdivisor != Rscratch, ""); | |
| 471 assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv"); | |
| 472 | |
| 473 if (Rdivisor == noreg && is_power_of_2(divisor)) { | |
| 474 // convert division by a power of two into some shifts and logical operations | |
| 475 if (op->code() == lir_idiv) { | |
| 476 if (divisor == 2) { | |
| 477 __ srl(Rdividend, 31, Rscratch); | |
| 478 } else { | |
| 479 __ sra(Rdividend, 31, Rscratch); | |
| 480 __ and3(Rscratch, divisor - 1, Rscratch); | |
| 481 } | |
| 482 __ add(Rdividend, Rscratch, Rscratch); | |
| 483 __ sra(Rscratch, log2_intptr(divisor), Rresult); | |
| 484 return; | |
| 485 } else { | |
| 486 if (divisor == 2) { | |
| 487 __ srl(Rdividend, 31, Rscratch); | |
| 488 } else { | |
| 489 __ sra(Rdividend, 31, Rscratch); | |
| 490 __ and3(Rscratch, divisor - 1,Rscratch); | |
| 491 } | |
| 492 __ add(Rdividend, Rscratch, Rscratch); | |
| 493 __ andn(Rscratch, divisor - 1,Rscratch); | |
| 494 __ sub(Rdividend, Rscratch, Rresult); | |
| 495 return; | |
| 496 } | |
| 497 } | |
| 498 | |
| 499 __ sra(Rdividend, 31, Rscratch); | |
| 500 __ wry(Rscratch); | |
| 501 if (!VM_Version::v9_instructions_work()) { | |
| 502 // v9 doesn't require these nops | |
| 503 __ nop(); | |
| 504 __ nop(); | |
| 505 __ nop(); | |
| 506 __ nop(); | |
| 507 } | |
| 508 | |
| 509 add_debug_info_for_div0_here(op->info()); | |
| 510 | |
| 511 if (Rdivisor != noreg) { | |
| 512 __ sdivcc(Rdividend, Rdivisor, (op->code() == lir_idiv ? Rresult : Rscratch)); | |
| 513 } else { | |
| 514 assert(Assembler::is_simm13(divisor), "can only handle simm13"); | |
| 515 __ sdivcc(Rdividend, divisor, (op->code() == lir_idiv ? Rresult : Rscratch)); | |
| 516 } | |
| 517 | |
| 518 Label skip; | |
| 519 __ br(Assembler::overflowSet, true, Assembler::pn, skip); | |
| 520 __ delayed()->Assembler::sethi(0x80000000, (op->code() == lir_idiv ? Rresult : Rscratch)); | |
| 521 __ bind(skip); | |
| 522 | |
| 523 if (op->code() == lir_irem) { | |
| 524 if (Rdivisor != noreg) { | |
| 525 __ smul(Rscratch, Rdivisor, Rscratch); | |
| 526 } else { | |
| 527 __ smul(Rscratch, divisor, Rscratch); | |
| 528 } | |
| 529 __ sub(Rdividend, Rscratch, Rresult); | |
| 530 } | |
| 531 } | |
| 532 | |
| 533 | |
| 534 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { | |
| 535 #ifdef ASSERT | |
| 536 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); | |
| 537 if (op->block() != NULL) _branch_target_blocks.append(op->block()); | |
| 538 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); | |
| 539 #endif | |
| 540 assert(op->info() == NULL, "shouldn't have CodeEmitInfo"); | |
| 541 | |
| 542 if (op->cond() == lir_cond_always) { | |
| 543 __ br(Assembler::always, false, Assembler::pt, *(op->label())); | |
| 544 } else if (op->code() == lir_cond_float_branch) { | |
| 545 assert(op->ublock() != NULL, "must have unordered successor"); | |
| 546 bool is_unordered = (op->ublock() == op->block()); | |
| 547 Assembler::Condition acond; | |
| 548 switch (op->cond()) { | |
| 549 case lir_cond_equal: acond = Assembler::f_equal; break; | |
| 550 case lir_cond_notEqual: acond = Assembler::f_notEqual; break; | |
| 551 case lir_cond_less: acond = (is_unordered ? Assembler::f_unorderedOrLess : Assembler::f_less); break; | |
| 552 case lir_cond_greater: acond = (is_unordered ? Assembler::f_unorderedOrGreater : Assembler::f_greater); break; | |
| 553 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::f_unorderedOrLessOrEqual : Assembler::f_lessOrEqual); break; | |
| 554 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::f_unorderedOrGreaterOrEqual: Assembler::f_greaterOrEqual); break; | |
| 555 default : ShouldNotReachHere(); | |
| 556 }; | |
| 557 | |
| 558 if (!VM_Version::v9_instructions_work()) { | |
| 559 __ nop(); | |
| 560 } | |
| 561 __ fb( acond, false, Assembler::pn, *(op->label())); | |
| 562 } else { | |
| 563 assert (op->code() == lir_branch, "just checking"); | |
| 564 | |
| 565 Assembler::Condition acond; | |
| 566 switch (op->cond()) { | |
| 567 case lir_cond_equal: acond = Assembler::equal; break; | |
| 568 case lir_cond_notEqual: acond = Assembler::notEqual; break; | |
| 569 case lir_cond_less: acond = Assembler::less; break; | |
| 570 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; | |
| 571 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break; | |
| 572 case lir_cond_greater: acond = Assembler::greater; break; | |
| 573 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break; | |
| 574 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break; | |
| 575 default: ShouldNotReachHere(); | |
| 576 }; | |
| 577 | |
| 578 // sparc has different condition codes for testing 32-bit | |
| 579 // vs. 64-bit values. We could always test xcc is we could | |
| 580 // guarantee that 32-bit loads always sign extended but that isn't | |
| 581 // true and since sign extension isn't free, it would impose a | |
| 582 // slight cost. | |
| 583 #ifdef _LP64 | |
| 584 if (op->type() == T_INT) { | |
| 585 __ br(acond, false, Assembler::pn, *(op->label())); | |
| 586 } else | |
| 587 #endif | |
| 588 __ brx(acond, false, Assembler::pn, *(op->label())); | |
| 589 } | |
| 590 // The peephole pass fills the delay slot | |
| 591 } | |
| 592 | |
| 593 | |
| 594 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { | |
| 595 Bytecodes::Code code = op->bytecode(); | |
| 596 LIR_Opr dst = op->result_opr(); | |
| 597 | |
| 598 switch(code) { | |
| 599 case Bytecodes::_i2l: { | |
| 600 Register rlo = dst->as_register_lo(); | |
| 601 Register rhi = dst->as_register_hi(); | |
| 602 Register rval = op->in_opr()->as_register(); | |
| 603 #ifdef _LP64 | |
| 604 __ sra(rval, 0, rlo); | |
| 605 #else | |
| 606 __ mov(rval, rlo); | |
| 607 __ sra(rval, BitsPerInt-1, rhi); | |
| 608 #endif | |
| 609 break; | |
| 610 } | |
| 611 case Bytecodes::_i2d: | |
| 612 case Bytecodes::_i2f: { | |
| 613 bool is_double = (code == Bytecodes::_i2d); | |
| 614 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg(); | |
| 615 FloatRegisterImpl::Width w = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S; | |
| 616 FloatRegister rsrc = op->in_opr()->as_float_reg(); | |
| 617 if (rsrc != rdst) { | |
| 618 __ fmov(FloatRegisterImpl::S, rsrc, rdst); | |
| 619 } | |
| 620 __ fitof(w, rdst, rdst); | |
| 621 break; | |
| 622 } | |
| 623 case Bytecodes::_f2i:{ | |
| 624 FloatRegister rsrc = op->in_opr()->as_float_reg(); | |
| 625 Address addr = frame_map()->address_for_slot(dst->single_stack_ix()); | |
| 626 Label L; | |
| 627 // result must be 0 if value is NaN; test by comparing value to itself | |
| 628 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc); | |
| 629 if (!VM_Version::v9_instructions_work()) { | |
| 630 __ nop(); | |
| 631 } | |
| 632 __ fb(Assembler::f_unordered, true, Assembler::pn, L); | |
| 633 __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN | |
| 634 __ ftoi(FloatRegisterImpl::S, rsrc, rsrc); | |
| 635 // move integer result from float register to int register | |
| 636 __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp()); | |
| 637 __ bind (L); | |
| 638 break; | |
| 639 } | |
| 640 case Bytecodes::_l2i: { | |
| 641 Register rlo = op->in_opr()->as_register_lo(); | |
| 642 Register rhi = op->in_opr()->as_register_hi(); | |
| 643 Register rdst = dst->as_register(); | |
| 644 #ifdef _LP64 | |
| 645 __ sra(rlo, 0, rdst); | |
| 646 #else | |
| 647 __ mov(rlo, rdst); | |
| 648 #endif | |
| 649 break; | |
| 650 } | |
| 651 case Bytecodes::_d2f: | |
| 652 case Bytecodes::_f2d: { | |
| 653 bool is_double = (code == Bytecodes::_f2d); | |
| 654 assert((!is_double && dst->is_single_fpu()) || (is_double && dst->is_double_fpu()), "check"); | |
| 655 LIR_Opr val = op->in_opr(); | |
| 656 FloatRegister rval = (code == Bytecodes::_d2f) ? val->as_double_reg() : val->as_float_reg(); | |
| 657 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg(); | |
| 658 FloatRegisterImpl::Width vw = is_double ? FloatRegisterImpl::S : FloatRegisterImpl::D; | |
| 659 FloatRegisterImpl::Width dw = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S; | |
| 660 __ ftof(vw, dw, rval, rdst); | |
| 661 break; | |
| 662 } | |
| 663 case Bytecodes::_i2s: | |
| 664 case Bytecodes::_i2b: { | |
| 665 Register rval = op->in_opr()->as_register(); | |
| 666 Register rdst = dst->as_register(); | |
| 667 int shift = (code == Bytecodes::_i2b) ? (BitsPerInt - T_BYTE_aelem_bytes * BitsPerByte) : (BitsPerInt - BitsPerShort); | |
| 668 __ sll (rval, shift, rdst); | |
| 669 __ sra (rdst, shift, rdst); | |
| 670 break; | |
| 671 } | |
| 672 case Bytecodes::_i2c: { | |
| 673 Register rval = op->in_opr()->as_register(); | |
| 674 Register rdst = dst->as_register(); | |
| 675 int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte; | |
| 676 __ sll (rval, shift, rdst); | |
| 677 __ srl (rdst, shift, rdst); | |
| 678 break; | |
| 679 } | |
| 680 | |
| 681 default: ShouldNotReachHere(); | |
| 682 } | |
| 683 } | |
| 684 | |
| 685 | |
| 686 void LIR_Assembler::align_call(LIR_Code) { | |
| 687 // do nothing since all instructions are word aligned on sparc | |
| 688 } | |
| 689 | |
| 690 | |
| 691 void LIR_Assembler::call(address entry, relocInfo::relocType rtype, CodeEmitInfo* info) { | |
| 692 __ call(entry, rtype); | |
| 693 // the peephole pass fills the delay slot | |
| 694 } | |
| 695 | |
| 696 | |
| 697 void LIR_Assembler::ic_call(address entry, CodeEmitInfo* info) { | |
| 698 RelocationHolder rspec = virtual_call_Relocation::spec(pc()); | |
| 699 __ set_oop((jobject)Universe::non_oop_word(), G5_inline_cache_reg); | |
| 700 __ relocate(rspec); | |
| 701 __ call(entry, relocInfo::none); | |
| 702 // the peephole pass fills the delay slot | |
| 703 } | |
| 704 | |
| 705 | |
| 706 void LIR_Assembler::vtable_call(int vtable_offset, CodeEmitInfo* info) { | |
| 707 add_debug_info_for_null_check_here(info); | |
| 727 | 708 __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), G3_scratch); |
| 0 | 709 if (__ is_simm13(vtable_offset) ) { |
| 710 __ ld_ptr(G3_scratch, vtable_offset, G5_method); | |
| 711 } else { | |
| 712 // This will generate 2 instructions | |
| 713 __ set(vtable_offset, G5_method); | |
| 714 // ld_ptr, set_hi, set | |
| 715 __ ld_ptr(G3_scratch, G5_method, G5_method); | |
| 716 } | |
| 727 | 717 __ ld_ptr(G5_method, methodOopDesc::from_compiled_offset(), G3_scratch); |
| 0 | 718 __ callr(G3_scratch, G0); |
| 719 // the peephole pass fills the delay slot | |
| 720 } | |
| 721 | |
| 722 | |
| 723 // load with 32-bit displacement | |
| 724 int LIR_Assembler::load(Register s, int disp, Register d, BasicType ld_type, CodeEmitInfo *info) { | |
| 725 int load_offset = code_offset(); | |
| 726 if (Assembler::is_simm13(disp)) { | |
| 727 if (info != NULL) add_debug_info_for_null_check_here(info); | |
| 728 switch(ld_type) { | |
| 729 case T_BOOLEAN: // fall through | |
| 730 case T_BYTE : __ ldsb(s, disp, d); break; | |
| 731 case T_CHAR : __ lduh(s, disp, d); break; | |
| 732 case T_SHORT : __ ldsh(s, disp, d); break; | |
| 733 case T_INT : __ ld(s, disp, d); break; | |
| 734 case T_ADDRESS:// fall through | |
| 735 case T_ARRAY : // fall through | |
| 736 case T_OBJECT: __ ld_ptr(s, disp, d); break; | |
| 737 default : ShouldNotReachHere(); | |
| 738 } | |
| 739 } else { | |
| 727 | 740 __ set(disp, O7); |
| 0 | 741 if (info != NULL) add_debug_info_for_null_check_here(info); |
| 742 load_offset = code_offset(); | |
| 743 switch(ld_type) { | |
| 744 case T_BOOLEAN: // fall through | |
| 745 case T_BYTE : __ ldsb(s, O7, d); break; | |
| 746 case T_CHAR : __ lduh(s, O7, d); break; | |
| 747 case T_SHORT : __ ldsh(s, O7, d); break; | |
| 748 case T_INT : __ ld(s, O7, d); break; | |
| 749 case T_ADDRESS:// fall through | |
| 750 case T_ARRAY : // fall through | |
| 751 case T_OBJECT: __ ld_ptr(s, O7, d); break; | |
| 752 default : ShouldNotReachHere(); | |
| 753 } | |
| 754 } | |
| 755 if (ld_type == T_ARRAY || ld_type == T_OBJECT) __ verify_oop(d); | |
| 756 return load_offset; | |
| 757 } | |
| 758 | |
| 759 | |
| 760 // store with 32-bit displacement | |
| 761 void LIR_Assembler::store(Register value, Register base, int offset, BasicType type, CodeEmitInfo *info) { | |
| 762 if (Assembler::is_simm13(offset)) { | |
| 763 if (info != NULL) add_debug_info_for_null_check_here(info); | |
| 764 switch (type) { | |
| 765 case T_BOOLEAN: // fall through | |
| 766 case T_BYTE : __ stb(value, base, offset); break; | |
| 767 case T_CHAR : __ sth(value, base, offset); break; | |
| 768 case T_SHORT : __ sth(value, base, offset); break; | |
| 769 case T_INT : __ stw(value, base, offset); break; | |
| 770 case T_ADDRESS:// fall through | |
| 771 case T_ARRAY : // fall through | |
| 772 case T_OBJECT: __ st_ptr(value, base, offset); break; | |
| 773 default : ShouldNotReachHere(); | |
| 774 } | |
| 775 } else { | |
| 727 | 776 __ set(offset, O7); |
| 0 | 777 if (info != NULL) add_debug_info_for_null_check_here(info); |
| 778 switch (type) { | |
| 779 case T_BOOLEAN: // fall through | |
| 780 case T_BYTE : __ stb(value, base, O7); break; | |
| 781 case T_CHAR : __ sth(value, base, O7); break; | |
| 782 case T_SHORT : __ sth(value, base, O7); break; | |
| 783 case T_INT : __ stw(value, base, O7); break; | |
| 784 case T_ADDRESS:// fall through | |
| 785 case T_ARRAY : //fall through | |
| 786 case T_OBJECT: __ st_ptr(value, base, O7); break; | |
| 787 default : ShouldNotReachHere(); | |
| 788 } | |
| 789 } | |
| 790 // Note: Do the store before verification as the code might be patched! | |
| 791 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(value); | |
| 792 } | |
| 793 | |
| 794 | |
| 795 // load float with 32-bit displacement | |
| 796 void LIR_Assembler::load(Register s, int disp, FloatRegister d, BasicType ld_type, CodeEmitInfo *info) { | |
| 797 FloatRegisterImpl::Width w; | |
| 798 switch(ld_type) { | |
| 799 case T_FLOAT : w = FloatRegisterImpl::S; break; | |
| 800 case T_DOUBLE: w = FloatRegisterImpl::D; break; | |
| 801 default : ShouldNotReachHere(); | |
| 802 } | |
| 803 | |
| 804 if (Assembler::is_simm13(disp)) { | |
| 805 if (info != NULL) add_debug_info_for_null_check_here(info); | |
| 806 if (disp % BytesPerLong != 0 && w == FloatRegisterImpl::D) { | |
| 807 __ ldf(FloatRegisterImpl::S, s, disp + BytesPerWord, d->successor()); | |
| 808 __ ldf(FloatRegisterImpl::S, s, disp , d); | |
| 809 } else { | |
| 810 __ ldf(w, s, disp, d); | |
| 811 } | |
| 812 } else { | |
| 727 | 813 __ set(disp, O7); |
| 0 | 814 if (info != NULL) add_debug_info_for_null_check_here(info); |
| 815 __ ldf(w, s, O7, d); | |
| 816 } | |
| 817 } | |
| 818 | |
| 819 | |
| 820 // store float with 32-bit displacement | |
| 821 void LIR_Assembler::store(FloatRegister value, Register base, int offset, BasicType type, CodeEmitInfo *info) { | |
| 822 FloatRegisterImpl::Width w; | |
| 823 switch(type) { | |
| 824 case T_FLOAT : w = FloatRegisterImpl::S; break; | |
| 825 case T_DOUBLE: w = FloatRegisterImpl::D; break; | |
| 826 default : ShouldNotReachHere(); | |
| 827 } | |
| 828 | |
| 829 if (Assembler::is_simm13(offset)) { | |
| 830 if (info != NULL) add_debug_info_for_null_check_here(info); | |
| 831 if (w == FloatRegisterImpl::D && offset % BytesPerLong != 0) { | |
| 832 __ stf(FloatRegisterImpl::S, value->successor(), base, offset + BytesPerWord); | |
| 833 __ stf(FloatRegisterImpl::S, value , base, offset); | |
| 834 } else { | |
| 835 __ stf(w, value, base, offset); | |
| 836 } | |
| 837 } else { | |
| 727 | 838 __ set(offset, O7); |
| 0 | 839 if (info != NULL) add_debug_info_for_null_check_here(info); |
| 840 __ stf(w, value, O7, base); | |
| 841 } | |
| 842 } | |
| 843 | |
| 844 | |
| 845 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool unaligned) { | |
| 846 int store_offset; | |
| 847 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) { | |
| 848 assert(!unaligned, "can't handle this"); | |
| 849 // for offsets larger than a simm13 we setup the offset in O7 | |
| 727 | 850 __ set(offset, O7); |
| 0 | 851 store_offset = store(from_reg, base, O7, type); |
| 852 } else { | |
| 853 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(from_reg->as_register()); | |
| 854 store_offset = code_offset(); | |
| 855 switch (type) { | |
| 856 case T_BOOLEAN: // fall through | |
| 857 case T_BYTE : __ stb(from_reg->as_register(), base, offset); break; | |
| 858 case T_CHAR : __ sth(from_reg->as_register(), base, offset); break; | |
| 859 case T_SHORT : __ sth(from_reg->as_register(), base, offset); break; | |
| 860 case T_INT : __ stw(from_reg->as_register(), base, offset); break; | |
| 861 case T_LONG : | |
| 862 #ifdef _LP64 | |
| 863 if (unaligned || PatchALot) { | |
| 864 __ srax(from_reg->as_register_lo(), 32, O7); | |
| 865 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes); | |
| 866 __ stw(O7, base, offset + hi_word_offset_in_bytes); | |
| 867 } else { | |
| 868 __ stx(from_reg->as_register_lo(), base, offset); | |
| 869 } | |
| 870 #else | |
| 871 assert(Assembler::is_simm13(offset + 4), "must be"); | |
| 872 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes); | |
| 873 __ stw(from_reg->as_register_hi(), base, offset + hi_word_offset_in_bytes); | |
| 874 #endif | |
| 875 break; | |
| 876 case T_ADDRESS:// fall through | |
| 877 case T_ARRAY : // fall through | |
| 878 case T_OBJECT: __ st_ptr(from_reg->as_register(), base, offset); break; | |
| 879 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break; | |
| 880 case T_DOUBLE: | |
| 881 { | |
| 882 FloatRegister reg = from_reg->as_double_reg(); | |
| 883 // split unaligned stores | |
| 884 if (unaligned || PatchALot) { | |
| 885 assert(Assembler::is_simm13(offset + 4), "must be"); | |
| 886 __ stf(FloatRegisterImpl::S, reg->successor(), base, offset + 4); | |
| 887 __ stf(FloatRegisterImpl::S, reg, base, offset); | |
| 888 } else { | |
| 889 __ stf(FloatRegisterImpl::D, reg, base, offset); | |
| 890 } | |
| 891 break; | |
| 892 } | |
| 893 default : ShouldNotReachHere(); | |
| 894 } | |
| 895 } | |
| 896 return store_offset; | |
| 897 } | |
| 898 | |
| 899 | |
| 900 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type) { | |
| 901 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(from_reg->as_register()); | |
| 902 int store_offset = code_offset(); | |
| 903 switch (type) { | |
| 904 case T_BOOLEAN: // fall through | |
| 905 case T_BYTE : __ stb(from_reg->as_register(), base, disp); break; | |
| 906 case T_CHAR : __ sth(from_reg->as_register(), base, disp); break; | |
| 907 case T_SHORT : __ sth(from_reg->as_register(), base, disp); break; | |
| 908 case T_INT : __ stw(from_reg->as_register(), base, disp); break; | |
| 909 case T_LONG : | |
| 910 #ifdef _LP64 | |
| 911 __ stx(from_reg->as_register_lo(), base, disp); | |
| 912 #else | |
| 913 assert(from_reg->as_register_hi()->successor() == from_reg->as_register_lo(), "must match"); | |
| 914 __ std(from_reg->as_register_hi(), base, disp); | |
| 915 #endif | |
| 916 break; | |
| 917 case T_ADDRESS:// fall through | |
| 918 case T_ARRAY : // fall through | |
| 919 case T_OBJECT: __ st_ptr(from_reg->as_register(), base, disp); break; | |
| 920 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break; | |
| 921 case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break; | |
| 922 default : ShouldNotReachHere(); | |
| 923 } | |
| 924 return store_offset; | |
| 925 } | |
| 926 | |
| 927 | |
| 928 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool unaligned) { | |
| 929 int load_offset; | |
| 930 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) { | |
| 931 assert(base != O7, "destroying register"); | |
| 932 assert(!unaligned, "can't handle this"); | |
| 933 // for offsets larger than a simm13 we setup the offset in O7 | |
| 727 | 934 __ set(offset, O7); |
| 0 | 935 load_offset = load(base, O7, to_reg, type); |
| 936 } else { | |
| 937 load_offset = code_offset(); | |
| 938 switch(type) { | |
| 939 case T_BOOLEAN: // fall through | |
| 940 case T_BYTE : __ ldsb(base, offset, to_reg->as_register()); break; | |
| 941 case T_CHAR : __ lduh(base, offset, to_reg->as_register()); break; | |
| 942 case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break; | |
| 943 case T_INT : __ ld(base, offset, to_reg->as_register()); break; | |
| 944 case T_LONG : | |
| 945 if (!unaligned) { | |
| 946 #ifdef _LP64 | |
| 947 __ ldx(base, offset, to_reg->as_register_lo()); | |
| 948 #else | |
| 949 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(), | |
| 950 "must be sequential"); | |
| 951 __ ldd(base, offset, to_reg->as_register_hi()); | |
| 952 #endif | |
| 953 } else { | |
| 954 #ifdef _LP64 | |
| 955 assert(base != to_reg->as_register_lo(), "can't handle this"); | |
| 956 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo()); | |
| 957 __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo()); | |
| 958 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo()); | |
| 959 #else | |
| 960 if (base == to_reg->as_register_lo()) { | |
| 961 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi()); | |
| 962 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo()); | |
| 963 } else { | |
| 964 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo()); | |
| 965 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi()); | |
| 966 } | |
| 967 #endif | |
| 968 } | |
| 969 break; | |
| 970 case T_ADDRESS:// fall through | |
| 971 case T_ARRAY : // fall through | |
| 972 case T_OBJECT: __ ld_ptr(base, offset, to_reg->as_register()); break; | |
| 973 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break; | |
| 974 case T_DOUBLE: | |
| 975 { | |
| 976 FloatRegister reg = to_reg->as_double_reg(); | |
| 977 // split unaligned loads | |
| 978 if (unaligned || PatchALot) { | |
| 979 __ ldf(FloatRegisterImpl::S, base, offset + BytesPerWord, reg->successor()); | |
| 980 __ ldf(FloatRegisterImpl::S, base, offset, reg); | |
| 981 } else { | |
| 982 __ ldf(FloatRegisterImpl::D, base, offset, to_reg->as_double_reg()); | |
| 983 } | |
| 984 break; | |
| 985 } | |
| 986 default : ShouldNotReachHere(); | |
| 987 } | |
| 988 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(to_reg->as_register()); | |
| 989 } | |
| 990 return load_offset; | |
| 991 } | |
| 992 | |
| 993 | |
| 994 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type) { | |
| 995 int load_offset = code_offset(); | |
| 996 switch(type) { | |
| 997 case T_BOOLEAN: // fall through | |
| 998 case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break; | |
| 999 case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break; | |
| 1000 case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break; | |
| 1001 case T_INT : __ ld(base, disp, to_reg->as_register()); break; | |
| 1002 case T_ADDRESS:// fall through | |
| 1003 case T_ARRAY : // fall through | |
| 1004 case T_OBJECT: __ ld_ptr(base, disp, to_reg->as_register()); break; | |
| 1005 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break; | |
| 1006 case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break; | |
| 1007 case T_LONG : | |
| 1008 #ifdef _LP64 | |
| 1009 __ ldx(base, disp, to_reg->as_register_lo()); | |
| 1010 #else | |
| 1011 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(), | |
| 1012 "must be sequential"); | |
| 1013 __ ldd(base, disp, to_reg->as_register_hi()); | |
| 1014 #endif | |
| 1015 break; | |
| 1016 default : ShouldNotReachHere(); | |
| 1017 } | |
| 1018 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(to_reg->as_register()); | |
| 1019 return load_offset; | |
| 1020 } | |
| 1021 | |
| 1022 | |
| 1023 // load/store with an Address | |
| 1024 void LIR_Assembler::load(const Address& a, Register d, BasicType ld_type, CodeEmitInfo *info, int offset) { | |
| 1025 load(a.base(), a.disp() + offset, d, ld_type, info); | |
| 1026 } | |
| 1027 | |
| 1028 | |
| 1029 void LIR_Assembler::store(Register value, const Address& dest, BasicType type, CodeEmitInfo *info, int offset) { | |
| 1030 store(value, dest.base(), dest.disp() + offset, type, info); | |
| 1031 } | |
| 1032 | |
| 1033 | |
| 1034 // loadf/storef with an Address | |
| 1035 void LIR_Assembler::load(const Address& a, FloatRegister d, BasicType ld_type, CodeEmitInfo *info, int offset) { | |
| 1036 load(a.base(), a.disp() + offset, d, ld_type, info); | |
| 1037 } | |
| 1038 | |
| 1039 | |
| 1040 void LIR_Assembler::store(FloatRegister value, const Address& dest, BasicType type, CodeEmitInfo *info, int offset) { | |
| 1041 store(value, dest.base(), dest.disp() + offset, type, info); | |
| 1042 } | |
| 1043 | |
| 1044 | |
| 1045 // load/store with an Address | |
| 1046 void LIR_Assembler::load(LIR_Address* a, Register d, BasicType ld_type, CodeEmitInfo *info) { | |
| 1047 load(as_Address(a), d, ld_type, info); | |
| 1048 } | |
| 1049 | |
| 1050 | |
| 1051 void LIR_Assembler::store(Register value, LIR_Address* dest, BasicType type, CodeEmitInfo *info) { | |
| 1052 store(value, as_Address(dest), type, info); | |
| 1053 } | |
| 1054 | |
| 1055 | |
| 1056 // loadf/storef with an Address | |
| 1057 void LIR_Assembler::load(LIR_Address* a, FloatRegister d, BasicType ld_type, CodeEmitInfo *info) { | |
| 1058 load(as_Address(a), d, ld_type, info); | |
| 1059 } | |
| 1060 | |
| 1061 | |
| 1062 void LIR_Assembler::store(FloatRegister value, LIR_Address* dest, BasicType type, CodeEmitInfo *info) { | |
| 1063 store(value, as_Address(dest), type, info); | |
| 1064 } | |
| 1065 | |
| 1066 | |
| 1067 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { | |
| 1068 LIR_Const* c = src->as_constant_ptr(); | |
| 1069 switch (c->type()) { | |
| 1070 case T_INT: | |
| 1071 case T_FLOAT: { | |
| 1072 Register src_reg = O7; | |
| 1073 int value = c->as_jint_bits(); | |
| 1074 if (value == 0) { | |
| 1075 src_reg = G0; | |
| 1076 } else { | |
| 1077 __ set(value, O7); | |
| 1078 } | |
| 1079 Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); | |
| 1080 __ stw(src_reg, addr.base(), addr.disp()); | |
| 1081 break; | |
| 1082 } | |
| 1083 case T_OBJECT: { | |
| 1084 Register src_reg = O7; | |
| 1085 jobject2reg(c->as_jobject(), src_reg); | |
| 1086 Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); | |
| 1087 __ st_ptr(src_reg, addr.base(), addr.disp()); | |
| 1088 break; | |
| 1089 } | |
| 1090 case T_LONG: | |
| 1091 case T_DOUBLE: { | |
| 1092 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix()); | |
| 1093 | |
| 1094 Register tmp = O7; | |
| 1095 int value_lo = c->as_jint_lo_bits(); | |
| 1096 if (value_lo == 0) { | |
| 1097 tmp = G0; | |
| 1098 } else { | |
| 1099 __ set(value_lo, O7); | |
| 1100 } | |
| 1101 __ stw(tmp, addr.base(), addr.disp() + lo_word_offset_in_bytes); | |
| 1102 int value_hi = c->as_jint_hi_bits(); | |
| 1103 if (value_hi == 0) { | |
| 1104 tmp = G0; | |
| 1105 } else { | |
| 1106 __ set(value_hi, O7); | |
| 1107 } | |
| 1108 __ stw(tmp, addr.base(), addr.disp() + hi_word_offset_in_bytes); | |
| 1109 break; | |
| 1110 } | |
| 1111 default: | |
| 1112 Unimplemented(); | |
| 1113 } | |
| 1114 } | |
| 1115 | |
| 1116 | |
| 1117 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info ) { | |
| 1118 LIR_Const* c = src->as_constant_ptr(); | |
| 1119 LIR_Address* addr = dest->as_address_ptr(); | |
| 1120 Register base = addr->base()->as_pointer_register(); | |
| 1121 | |
| 1122 if (info != NULL) { | |
| 1123 add_debug_info_for_null_check_here(info); | |
| 1124 } | |
| 1125 switch (c->type()) { | |
| 1126 case T_INT: | |
| 1127 case T_FLOAT: { | |
| 1128 LIR_Opr tmp = FrameMap::O7_opr; | |
| 1129 int value = c->as_jint_bits(); | |
| 1130 if (value == 0) { | |
| 1131 tmp = FrameMap::G0_opr; | |
| 1132 } else if (Assembler::is_simm13(value)) { | |
| 1133 __ set(value, O7); | |
| 1134 } | |
| 1135 if (addr->index()->is_valid()) { | |
| 1136 assert(addr->disp() == 0, "must be zero"); | |
| 1137 store(tmp, base, addr->index()->as_pointer_register(), type); | |
| 1138 } else { | |
| 1139 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses"); | |
| 1140 store(tmp, base, addr->disp(), type); | |
| 1141 } | |
| 1142 break; | |
| 1143 } | |
| 1144 case T_LONG: | |
| 1145 case T_DOUBLE: { | |
| 1146 assert(!addr->index()->is_valid(), "can't handle reg reg address here"); | |
| 1147 assert(Assembler::is_simm13(addr->disp()) && | |
| 1148 Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses"); | |
| 1149 | |
| 1150 Register tmp = O7; | |
| 1151 int value_lo = c->as_jint_lo_bits(); | |
| 1152 if (value_lo == 0) { | |
| 1153 tmp = G0; | |
| 1154 } else { | |
| 1155 __ set(value_lo, O7); | |
| 1156 } | |
| 1157 store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT); | |
| 1158 int value_hi = c->as_jint_hi_bits(); | |
| 1159 if (value_hi == 0) { | |
| 1160 tmp = G0; | |
| 1161 } else { | |
| 1162 __ set(value_hi, O7); | |
| 1163 } | |
| 1164 store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT); | |
| 1165 break; | |
| 1166 } | |
| 1167 case T_OBJECT: { | |
| 1168 jobject obj = c->as_jobject(); | |
| 1169 LIR_Opr tmp; | |
| 1170 if (obj == NULL) { | |
| 1171 tmp = FrameMap::G0_opr; | |
| 1172 } else { | |
| 1173 tmp = FrameMap::O7_opr; | |
| 1174 jobject2reg(c->as_jobject(), O7); | |
| 1175 } | |
| 1176 // handle either reg+reg or reg+disp address | |
| 1177 if (addr->index()->is_valid()) { | |
| 1178 assert(addr->disp() == 0, "must be zero"); | |
| 1179 store(tmp, base, addr->index()->as_pointer_register(), type); | |
| 1180 } else { | |
| 1181 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses"); | |
| 1182 store(tmp, base, addr->disp(), type); | |
| 1183 } | |
| 1184 | |
| 1185 break; | |
| 1186 } | |
| 1187 default: | |
| 1188 Unimplemented(); | |
| 1189 } | |
| 1190 } | |
| 1191 | |
| 1192 | |
| 1193 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { | |
| 1194 LIR_Const* c = src->as_constant_ptr(); | |
| 1195 LIR_Opr to_reg = dest; | |
| 1196 | |
| 1197 switch (c->type()) { | |
| 1198 case T_INT: | |
| 1199 { | |
| 1200 jint con = c->as_jint(); | |
| 1201 if (to_reg->is_single_cpu()) { | |
| 1202 assert(patch_code == lir_patch_none, "no patching handled here"); | |
| 1203 __ set(con, to_reg->as_register()); | |
| 1204 } else { | |
| 1205 ShouldNotReachHere(); | |
| 1206 assert(to_reg->is_single_fpu(), "wrong register kind"); | |
| 1207 | |
| 1208 __ set(con, O7); | |
| 727 | 1209 Address temp_slot(SP, (frame::register_save_words * wordSize) + STACK_BIAS); |
| 0 | 1210 __ st(O7, temp_slot); |
| 1211 __ ldf(FloatRegisterImpl::S, temp_slot, to_reg->as_float_reg()); | |
| 1212 } | |
| 1213 } | |
| 1214 break; | |
| 1215 | |
| 1216 case T_LONG: | |
| 1217 { | |
| 1218 jlong con = c->as_jlong(); | |
| 1219 | |
| 1220 if (to_reg->is_double_cpu()) { | |
| 1221 #ifdef _LP64 | |
| 1222 __ set(con, to_reg->as_register_lo()); | |
| 1223 #else | |
| 1224 __ set(low(con), to_reg->as_register_lo()); | |
| 1225 __ set(high(con), to_reg->as_register_hi()); | |
| 1226 #endif | |
| 1227 #ifdef _LP64 | |
| 1228 } else if (to_reg->is_single_cpu()) { | |
| 1229 __ set(con, to_reg->as_register()); | |
| 1230 #endif | |
| 1231 } else { | |
| 1232 ShouldNotReachHere(); | |
| 1233 assert(to_reg->is_double_fpu(), "wrong register kind"); | |
| 727 | 1234 Address temp_slot_lo(SP, ((frame::register_save_words ) * wordSize) + STACK_BIAS); |
| 1235 Address temp_slot_hi(SP, ((frame::register_save_words) * wordSize) + (longSize/2) + STACK_BIAS); | |
| 0 | 1236 __ set(low(con), O7); |
| 1237 __ st(O7, temp_slot_lo); | |
| 1238 __ set(high(con), O7); | |
| 1239 __ st(O7, temp_slot_hi); | |
| 1240 __ ldf(FloatRegisterImpl::D, temp_slot_lo, to_reg->as_double_reg()); | |
| 1241 } | |
| 1242 } | |
| 1243 break; | |
| 1244 | |
| 1245 case T_OBJECT: | |
| 1246 { | |
| 1247 if (patch_code == lir_patch_none) { | |
| 1248 jobject2reg(c->as_jobject(), to_reg->as_register()); | |
| 1249 } else { | |
| 1250 jobject2reg_with_patching(to_reg->as_register(), info); | |
| 1251 } | |
| 1252 } | |
| 1253 break; | |
| 1254 | |
| 1255 case T_FLOAT: | |
| 1256 { | |
| 1257 address const_addr = __ float_constant(c->as_jfloat()); | |
| 1258 if (const_addr == NULL) { | |
| 1259 bailout("const section overflow"); | |
| 1260 break; | |
| 1261 } | |
| 1262 RelocationHolder rspec = internal_word_Relocation::spec(const_addr); | |
| 727 | 1263 AddressLiteral const_addrlit(const_addr, rspec); |
| 0 | 1264 if (to_reg->is_single_fpu()) { |
| 727 | 1265 __ patchable_sethi(const_addrlit, O7); |
| 0 | 1266 __ relocate(rspec); |
| 727 | 1267 __ ldf(FloatRegisterImpl::S, O7, const_addrlit.low10(), to_reg->as_float_reg()); |
| 0 | 1268 |
| 1269 } else { | |
| 1270 assert(to_reg->is_single_cpu(), "Must be a cpu register."); | |
| 1271 | |
| 727 | 1272 __ set(const_addrlit, O7); |
| 0 | 1273 load(O7, 0, to_reg->as_register(), T_INT); |
| 1274 } | |
| 1275 } | |
| 1276 break; | |
| 1277 | |
| 1278 case T_DOUBLE: | |
| 1279 { | |
| 1280 address const_addr = __ double_constant(c->as_jdouble()); | |
| 1281 if (const_addr == NULL) { | |
| 1282 bailout("const section overflow"); | |
| 1283 break; | |
| 1284 } | |
| 1285 RelocationHolder rspec = internal_word_Relocation::spec(const_addr); | |
| 1286 | |
| 1287 if (to_reg->is_double_fpu()) { | |
| 727 | 1288 AddressLiteral const_addrlit(const_addr, rspec); |
| 1289 __ patchable_sethi(const_addrlit, O7); | |
| 0 | 1290 __ relocate(rspec); |
| 727 | 1291 __ ldf (FloatRegisterImpl::D, O7, const_addrlit.low10(), to_reg->as_double_reg()); |
| 0 | 1292 } else { |
| 1293 assert(to_reg->is_double_cpu(), "Must be a long register."); | |
| 1294 #ifdef _LP64 | |
| 1295 __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo()); | |
| 1296 #else | |
| 1297 __ set(low(jlong_cast(c->as_jdouble())), to_reg->as_register_lo()); | |
| 1298 __ set(high(jlong_cast(c->as_jdouble())), to_reg->as_register_hi()); | |
| 1299 #endif | |
| 1300 } | |
| 1301 | |
| 1302 } | |
| 1303 break; | |
| 1304 | |
| 1305 default: | |
| 1306 ShouldNotReachHere(); | |
| 1307 } | |
| 1308 } | |
| 1309 | |
| 1310 Address LIR_Assembler::as_Address(LIR_Address* addr) { | |
| 1311 Register reg = addr->base()->as_register(); | |
| 727 | 1312 return Address(reg, addr->disp()); |
| 0 | 1313 } |
| 1314 | |
| 1315 | |
| 1316 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { | |
| 1317 switch (type) { | |
| 1318 case T_INT: | |
| 1319 case T_FLOAT: { | |
| 1320 Register tmp = O7; | |
| 1321 Address from = frame_map()->address_for_slot(src->single_stack_ix()); | |
| 1322 Address to = frame_map()->address_for_slot(dest->single_stack_ix()); | |
| 1323 __ lduw(from.base(), from.disp(), tmp); | |
| 1324 __ stw(tmp, to.base(), to.disp()); | |
| 1325 break; | |
| 1326 } | |
| 1327 case T_OBJECT: { | |
| 1328 Register tmp = O7; | |
| 1329 Address from = frame_map()->address_for_slot(src->single_stack_ix()); | |
| 1330 Address to = frame_map()->address_for_slot(dest->single_stack_ix()); | |
| 1331 __ ld_ptr(from.base(), from.disp(), tmp); | |
| 1332 __ st_ptr(tmp, to.base(), to.disp()); | |
| 1333 break; | |
| 1334 } | |
| 1335 case T_LONG: | |
| 1336 case T_DOUBLE: { | |
| 1337 Register tmp = O7; | |
| 1338 Address from = frame_map()->address_for_double_slot(src->double_stack_ix()); | |
| 1339 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix()); | |
| 1340 __ lduw(from.base(), from.disp(), tmp); | |
| 1341 __ stw(tmp, to.base(), to.disp()); | |
| 1342 __ lduw(from.base(), from.disp() + 4, tmp); | |
| 1343 __ stw(tmp, to.base(), to.disp() + 4); | |
| 1344 break; | |
| 1345 } | |
| 1346 | |
| 1347 default: | |
| 1348 ShouldNotReachHere(); | |
| 1349 } | |
| 1350 } | |
| 1351 | |
| 1352 | |
| 1353 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { | |
| 1354 Address base = as_Address(addr); | |
| 727 | 1355 return Address(base.base(), base.disp() + hi_word_offset_in_bytes); |
| 0 | 1356 } |
| 1357 | |
| 1358 | |
| 1359 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { | |
| 1360 Address base = as_Address(addr); | |
| 727 | 1361 return Address(base.base(), base.disp() + lo_word_offset_in_bytes); |
| 0 | 1362 } |
| 1363 | |
| 1364 | |
| 1365 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type, | |
| 1366 LIR_PatchCode patch_code, CodeEmitInfo* info, bool unaligned) { | |
| 1367 | |
| 1368 LIR_Address* addr = src_opr->as_address_ptr(); | |
| 1369 LIR_Opr to_reg = dest; | |
| 1370 | |
| 1371 Register src = addr->base()->as_pointer_register(); | |
| 1372 Register disp_reg = noreg; | |
| 1373 int disp_value = addr->disp(); | |
| 1374 bool needs_patching = (patch_code != lir_patch_none); | |
| 1375 | |
| 1376 if (addr->base()->type() == T_OBJECT) { | |
| 1377 __ verify_oop(src); | |
| 1378 } | |
| 1379 | |
| 1380 PatchingStub* patch = NULL; | |
| 1381 if (needs_patching) { | |
| 1382 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
| 1383 assert(!to_reg->is_double_cpu() || | |
| 1384 patch_code == lir_patch_none || | |
| 1385 patch_code == lir_patch_normal, "patching doesn't match register"); | |
| 1386 } | |
| 1387 | |
| 1388 if (addr->index()->is_illegal()) { | |
| 1389 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) { | |
| 1390 if (needs_patching) { | |
| 727 | 1391 __ patchable_set(0, O7); |
| 0 | 1392 } else { |
| 1393 __ set(disp_value, O7); | |
| 1394 } | |
| 1395 disp_reg = O7; | |
| 1396 } | |
| 1397 } else if (unaligned || PatchALot) { | |
| 1398 __ add(src, addr->index()->as_register(), O7); | |
| 1399 src = O7; | |
| 1400 } else { | |
| 1401 disp_reg = addr->index()->as_pointer_register(); | |
| 1402 assert(disp_value == 0, "can't handle 3 operand addresses"); | |
| 1403 } | |
| 1404 | |
| 1405 // remember the offset of the load. The patching_epilog must be done | |
| 1406 // before the call to add_debug_info, otherwise the PcDescs don't get | |
| 1407 // entered in increasing order. | |
| 1408 int offset = code_offset(); | |
| 1409 | |
| 1410 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up"); | |
| 1411 if (disp_reg == noreg) { | |
| 1412 offset = load(src, disp_value, to_reg, type, unaligned); | |
| 1413 } else { | |
| 1414 assert(!unaligned, "can't handle this"); | |
| 1415 offset = load(src, disp_reg, to_reg, type); | |
| 1416 } | |
| 1417 | |
| 1418 if (patch != NULL) { | |
| 1419 patching_epilog(patch, patch_code, src, info); | |
| 1420 } | |
| 1421 | |
| 1422 if (info != NULL) add_debug_info_for_null_check(offset, info); | |
| 1423 } | |
| 1424 | |
| 1425 | |
| 1426 void LIR_Assembler::prefetchr(LIR_Opr src) { | |
| 1427 LIR_Address* addr = src->as_address_ptr(); | |
| 1428 Address from_addr = as_Address(addr); | |
| 1429 | |
| 1430 if (VM_Version::has_v9()) { | |
| 1431 __ prefetch(from_addr, Assembler::severalReads); | |
| 1432 } | |
| 1433 } | |
| 1434 | |
| 1435 | |
| 1436 void LIR_Assembler::prefetchw(LIR_Opr src) { | |
| 1437 LIR_Address* addr = src->as_address_ptr(); | |
| 1438 Address from_addr = as_Address(addr); | |
| 1439 | |
| 1440 if (VM_Version::has_v9()) { | |
| 1441 __ prefetch(from_addr, Assembler::severalWritesAndPossiblyReads); | |
| 1442 } | |
| 1443 } | |
| 1444 | |
| 1445 | |
| 1446 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { | |
| 1447 Address addr; | |
| 1448 if (src->is_single_word()) { | |
| 1449 addr = frame_map()->address_for_slot(src->single_stack_ix()); | |
| 1450 } else if (src->is_double_word()) { | |
| 1451 addr = frame_map()->address_for_double_slot(src->double_stack_ix()); | |
| 1452 } | |
| 1453 | |
| 1454 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0; | |
| 1455 load(addr.base(), addr.disp(), dest, dest->type(), unaligned); | |
| 1456 } | |
| 1457 | |
| 1458 | |
| 1459 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { | |
| 1460 Address addr; | |
| 1461 if (dest->is_single_word()) { | |
| 1462 addr = frame_map()->address_for_slot(dest->single_stack_ix()); | |
| 1463 } else if (dest->is_double_word()) { | |
| 1464 addr = frame_map()->address_for_slot(dest->double_stack_ix()); | |
| 1465 } | |
| 1466 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0; | |
| 1467 store(from_reg, addr.base(), addr.disp(), from_reg->type(), unaligned); | |
| 1468 } | |
| 1469 | |
| 1470 | |
| 1471 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) { | |
| 1472 if (from_reg->is_float_kind() && to_reg->is_float_kind()) { | |
| 1473 if (from_reg->is_double_fpu()) { | |
| 1474 // double to double moves | |
| 1475 assert(to_reg->is_double_fpu(), "should match"); | |
| 1476 __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg()); | |
| 1477 } else { | |
| 1478 // float to float moves | |
| 1479 assert(to_reg->is_single_fpu(), "should match"); | |
| 1480 __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg()); | |
| 1481 } | |
| 1482 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) { | |
| 1483 if (from_reg->is_double_cpu()) { | |
| 1484 #ifdef _LP64 | |
| 1485 __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register()); | |
| 1486 #else | |
| 1487 assert(to_reg->is_double_cpu() && | |
| 1488 from_reg->as_register_hi() != to_reg->as_register_lo() && | |
| 1489 from_reg->as_register_lo() != to_reg->as_register_hi(), | |
| 1490 "should both be long and not overlap"); | |
| 1491 // long to long moves | |
| 1492 __ mov(from_reg->as_register_hi(), to_reg->as_register_hi()); | |
| 1493 __ mov(from_reg->as_register_lo(), to_reg->as_register_lo()); | |
| 1494 #endif | |
| 1495 #ifdef _LP64 | |
| 1496 } else if (to_reg->is_double_cpu()) { | |
| 1497 // int to int moves | |
| 1498 __ mov(from_reg->as_register(), to_reg->as_register_lo()); | |
| 1499 #endif | |
| 1500 } else { | |
| 1501 // int to int moves | |
| 1502 __ mov(from_reg->as_register(), to_reg->as_register()); | |
| 1503 } | |
| 1504 } else { | |
| 1505 ShouldNotReachHere(); | |
| 1506 } | |
| 1507 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) { | |
| 1508 __ verify_oop(to_reg->as_register()); | |
| 1509 } | |
| 1510 } | |
| 1511 | |
| 1512 | |
| 1513 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type, | |
| 1514 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, | |
| 1515 bool unaligned) { | |
| 1516 LIR_Address* addr = dest->as_address_ptr(); | |
| 1517 | |
| 1518 Register src = addr->base()->as_pointer_register(); | |
| 1519 Register disp_reg = noreg; | |
| 1520 int disp_value = addr->disp(); | |
| 1521 bool needs_patching = (patch_code != lir_patch_none); | |
| 1522 | |
| 1523 if (addr->base()->is_oop_register()) { | |
| 1524 __ verify_oop(src); | |
| 1525 } | |
| 1526 | |
| 1527 PatchingStub* patch = NULL; | |
| 1528 if (needs_patching) { | |
| 1529 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
| 1530 assert(!from_reg->is_double_cpu() || | |
| 1531 patch_code == lir_patch_none || | |
| 1532 patch_code == lir_patch_normal, "patching doesn't match register"); | |
| 1533 } | |
| 1534 | |
| 1535 if (addr->index()->is_illegal()) { | |
| 1536 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) { | |
| 1537 if (needs_patching) { | |
| 727 | 1538 __ patchable_set(0, O7); |
| 0 | 1539 } else { |
| 1540 __ set(disp_value, O7); | |
| 1541 } | |
| 1542 disp_reg = O7; | |
| 1543 } | |
| 1544 } else if (unaligned || PatchALot) { | |
| 1545 __ add(src, addr->index()->as_register(), O7); | |
| 1546 src = O7; | |
| 1547 } else { | |
| 1548 disp_reg = addr->index()->as_pointer_register(); | |
| 1549 assert(disp_value == 0, "can't handle 3 operand addresses"); | |
| 1550 } | |
| 1551 | |
| 1552 // remember the offset of the store. The patching_epilog must be done | |
| 1553 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get | |
| 1554 // entered in increasing order. | |
| 1555 int offset; | |
| 1556 | |
| 1557 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up"); | |
| 1558 if (disp_reg == noreg) { | |
| 1559 offset = store(from_reg, src, disp_value, type, unaligned); | |
| 1560 } else { | |
| 1561 assert(!unaligned, "can't handle this"); | |
| 1562 offset = store(from_reg, src, disp_reg, type); | |
| 1563 } | |
| 1564 | |
| 1565 if (patch != NULL) { | |
| 1566 patching_epilog(patch, patch_code, src, info); | |
| 1567 } | |
| 1568 | |
| 1569 if (info != NULL) add_debug_info_for_null_check(offset, info); | |
| 1570 } | |
| 1571 | |
| 1572 | |
| 1573 void LIR_Assembler::return_op(LIR_Opr result) { | |
| 1574 // the poll may need a register so just pick one that isn't the return register | |
| 1575 #ifdef TIERED | |
| 1576 if (result->type_field() == LIR_OprDesc::long_type) { | |
| 1577 // Must move the result to G1 | |
| 1578 // Must leave proper result in O0,O1 and G1 (TIERED only) | |
| 1579 __ sllx(I0, 32, G1); // Shift bits into high G1 | |
| 1580 __ srl (I1, 0, I1); // Zero extend O1 (harmless?) | |
| 1581 __ or3 (I1, G1, G1); // OR 64 bits into G1 | |
| 1582 } | |
| 1583 #endif // TIERED | |
| 1584 __ set((intptr_t)os::get_polling_page(), L0); | |
| 1585 __ relocate(relocInfo::poll_return_type); | |
| 1586 __ ld_ptr(L0, 0, G0); | |
| 1587 __ ret(); | |
| 1588 __ delayed()->restore(); | |
| 1589 } | |
| 1590 | |
| 1591 | |
| 1592 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { | |
| 1593 __ set((intptr_t)os::get_polling_page(), tmp->as_register()); | |
| 1594 if (info != NULL) { | |
| 1595 add_debug_info_for_branch(info); | |
| 1596 } else { | |
| 1597 __ relocate(relocInfo::poll_type); | |
| 1598 } | |
| 1599 | |
| 1600 int offset = __ offset(); | |
| 1601 __ ld_ptr(tmp->as_register(), 0, G0); | |
| 1602 | |
| 1603 return offset; | |
| 1604 } | |
| 1605 | |
| 1606 | |
| 1607 void LIR_Assembler::emit_static_call_stub() { | |
| 1608 address call_pc = __ pc(); | |
| 1609 address stub = __ start_a_stub(call_stub_size); | |
| 1610 if (stub == NULL) { | |
| 1611 bailout("static call stub overflow"); | |
| 1612 return; | |
| 1613 } | |
| 1614 | |
| 1615 int start = __ offset(); | |
| 1616 __ relocate(static_stub_Relocation::spec(call_pc)); | |
| 1617 | |
| 1618 __ set_oop(NULL, G5); | |
| 1619 // must be set to -1 at code generation time | |
| 727 | 1620 AddressLiteral addrlit(-1); |
| 1621 __ jump_to(addrlit, G3); | |
| 0 | 1622 __ delayed()->nop(); |
| 1623 | |
| 1624 assert(__ offset() - start <= call_stub_size, "stub too big"); | |
| 1625 __ end_a_stub(); | |
| 1626 } | |
| 1627 | |
| 1628 | |
| 1629 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { | |
| 1630 if (opr1->is_single_fpu()) { | |
| 1631 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, opr1->as_float_reg(), opr2->as_float_reg()); | |
| 1632 } else if (opr1->is_double_fpu()) { | |
| 1633 __ fcmp(FloatRegisterImpl::D, Assembler::fcc0, opr1->as_double_reg(), opr2->as_double_reg()); | |
| 1634 } else if (opr1->is_single_cpu()) { | |
| 1635 if (opr2->is_constant()) { | |
| 1636 switch (opr2->as_constant_ptr()->type()) { | |
| 1637 case T_INT: | |
| 1638 { jint con = opr2->as_constant_ptr()->as_jint(); | |
| 1639 if (Assembler::is_simm13(con)) { | |
| 1640 __ cmp(opr1->as_register(), con); | |
| 1641 } else { | |
| 1642 __ set(con, O7); | |
| 1643 __ cmp(opr1->as_register(), O7); | |
| 1644 } | |
| 1645 } | |
| 1646 break; | |
| 1647 | |
| 1648 case T_OBJECT: | |
| 1649 // there are only equal/notequal comparisions on objects | |
| 1650 { jobject con = opr2->as_constant_ptr()->as_jobject(); | |
| 1651 if (con == NULL) { | |
| 1652 __ cmp(opr1->as_register(), 0); | |
| 1653 } else { | |
| 1654 jobject2reg(con, O7); | |
| 1655 __ cmp(opr1->as_register(), O7); | |
| 1656 } | |
| 1657 } | |
| 1658 break; | |
| 1659 | |
| 1660 default: | |
| 1661 ShouldNotReachHere(); | |
| 1662 break; | |
| 1663 } | |
| 1664 } else { | |
| 1665 if (opr2->is_address()) { | |
| 1666 LIR_Address * addr = opr2->as_address_ptr(); | |
| 1667 BasicType type = addr->type(); | |
| 1668 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7); | |
| 1669 else __ ld(as_Address(addr), O7); | |
| 1670 __ cmp(opr1->as_register(), O7); | |
| 1671 } else { | |
| 1672 __ cmp(opr1->as_register(), opr2->as_register()); | |
| 1673 } | |
| 1674 } | |
| 1675 } else if (opr1->is_double_cpu()) { | |
| 1676 Register xlo = opr1->as_register_lo(); | |
| 1677 Register xhi = opr1->as_register_hi(); | |
| 1678 if (opr2->is_constant() && opr2->as_jlong() == 0) { | |
| 1679 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles these cases"); | |
| 1680 #ifdef _LP64 | |
| 1681 __ orcc(xhi, G0, G0); | |
| 1682 #else | |
| 1683 __ orcc(xhi, xlo, G0); | |
| 1684 #endif | |
| 1685 } else if (opr2->is_register()) { | |
| 1686 Register ylo = opr2->as_register_lo(); | |
| 1687 Register yhi = opr2->as_register_hi(); | |
| 1688 #ifdef _LP64 | |
| 1689 __ cmp(xlo, ylo); | |
| 1690 #else | |
| 1691 __ subcc(xlo, ylo, xlo); | |
| 1692 __ subccc(xhi, yhi, xhi); | |
| 1693 if (condition == lir_cond_equal || condition == lir_cond_notEqual) { | |
| 1694 __ orcc(xhi, xlo, G0); | |
| 1695 } | |
| 1696 #endif | |
| 1697 } else { | |
| 1698 ShouldNotReachHere(); | |
| 1699 } | |
| 1700 } else if (opr1->is_address()) { | |
| 1701 LIR_Address * addr = opr1->as_address_ptr(); | |
| 1702 BasicType type = addr->type(); | |
| 1703 assert (opr2->is_constant(), "Checking"); | |
| 1704 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7); | |
| 1705 else __ ld(as_Address(addr), O7); | |
| 1706 __ cmp(O7, opr2->as_constant_ptr()->as_jint()); | |
| 1707 } else { | |
| 1708 ShouldNotReachHere(); | |
| 1709 } | |
| 1710 } | |
| 1711 | |
| 1712 | |
| 1713 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){ | |
| 1714 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { | |
| 1715 bool is_unordered_less = (code == lir_ucmp_fd2i); | |
| 1716 if (left->is_single_fpu()) { | |
| 1717 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register()); | |
| 1718 } else if (left->is_double_fpu()) { | |
| 1719 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register()); | |
| 1720 } else { | |
| 1721 ShouldNotReachHere(); | |
| 1722 } | |
| 1723 } else if (code == lir_cmp_l2i) { | |
| 1724 __ lcmp(left->as_register_hi(), left->as_register_lo(), | |
| 1725 right->as_register_hi(), right->as_register_lo(), | |
| 1726 dst->as_register()); | |
| 1727 } else { | |
| 1728 ShouldNotReachHere(); | |
| 1729 } | |
| 1730 } | |
| 1731 | |
| 1732 | |
| 1733 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result) { | |
| 1734 | |
| 1735 Assembler::Condition acond; | |
| 1736 switch (condition) { | |
| 1737 case lir_cond_equal: acond = Assembler::equal; break; | |
| 1738 case lir_cond_notEqual: acond = Assembler::notEqual; break; | |
| 1739 case lir_cond_less: acond = Assembler::less; break; | |
| 1740 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; | |
| 1741 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break; | |
| 1742 case lir_cond_greater: acond = Assembler::greater; break; | |
| 1743 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break; | |
| 1744 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break; | |
| 1745 default: ShouldNotReachHere(); | |
| 1746 }; | |
| 1747 | |
| 1748 if (opr1->is_constant() && opr1->type() == T_INT) { | |
| 1749 Register dest = result->as_register(); | |
| 1750 // load up first part of constant before branch | |
| 1751 // and do the rest in the delay slot. | |
| 1752 if (!Assembler::is_simm13(opr1->as_jint())) { | |
| 1753 __ sethi(opr1->as_jint(), dest); | |
| 1754 } | |
| 1755 } else if (opr1->is_constant()) { | |
| 1756 const2reg(opr1, result, lir_patch_none, NULL); | |
| 1757 } else if (opr1->is_register()) { | |
| 1758 reg2reg(opr1, result); | |
| 1759 } else if (opr1->is_stack()) { | |
| 1760 stack2reg(opr1, result, result->type()); | |
| 1761 } else { | |
| 1762 ShouldNotReachHere(); | |
| 1763 } | |
| 1764 Label skip; | |
| 1765 __ br(acond, false, Assembler::pt, skip); | |
| 1766 if (opr1->is_constant() && opr1->type() == T_INT) { | |
| 1767 Register dest = result->as_register(); | |
| 1768 if (Assembler::is_simm13(opr1->as_jint())) { | |
| 1769 __ delayed()->or3(G0, opr1->as_jint(), dest); | |
| 1770 } else { | |
| 1771 // the sethi has been done above, so just put in the low 10 bits | |
| 1772 __ delayed()->or3(dest, opr1->as_jint() & 0x3ff, dest); | |
| 1773 } | |
| 1774 } else { | |
| 1775 // can't do anything useful in the delay slot | |
| 1776 __ delayed()->nop(); | |
| 1777 } | |
| 1778 if (opr2->is_constant()) { | |
| 1779 const2reg(opr2, result, lir_patch_none, NULL); | |
| 1780 } else if (opr2->is_register()) { | |
| 1781 reg2reg(opr2, result); | |
| 1782 } else if (opr2->is_stack()) { | |
| 1783 stack2reg(opr2, result, result->type()); | |
| 1784 } else { | |
| 1785 ShouldNotReachHere(); | |
| 1786 } | |
| 1787 __ bind(skip); | |
| 1788 } | |
| 1789 | |
| 1790 | |
| 1791 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { | |
| 1792 assert(info == NULL, "unused on this code path"); | |
| 1793 assert(left->is_register(), "wrong items state"); | |
| 1794 assert(dest->is_register(), "wrong items state"); | |
| 1795 | |
| 1796 if (right->is_register()) { | |
| 1797 if (dest->is_float_kind()) { | |
| 1798 | |
| 1799 FloatRegister lreg, rreg, res; | |
| 1800 FloatRegisterImpl::Width w; | |
| 1801 if (right->is_single_fpu()) { | |
| 1802 w = FloatRegisterImpl::S; | |
| 1803 lreg = left->as_float_reg(); | |
| 1804 rreg = right->as_float_reg(); | |
| 1805 res = dest->as_float_reg(); | |
| 1806 } else { | |
| 1807 w = FloatRegisterImpl::D; | |
| 1808 lreg = left->as_double_reg(); | |
| 1809 rreg = right->as_double_reg(); | |
| 1810 res = dest->as_double_reg(); | |
| 1811 } | |
| 1812 | |
| 1813 switch (code) { | |
| 1814 case lir_add: __ fadd(w, lreg, rreg, res); break; | |
| 1815 case lir_sub: __ fsub(w, lreg, rreg, res); break; | |
| 1816 case lir_mul: // fall through | |
| 1817 case lir_mul_strictfp: __ fmul(w, lreg, rreg, res); break; | |
| 1818 case lir_div: // fall through | |
| 1819 case lir_div_strictfp: __ fdiv(w, lreg, rreg, res); break; | |
| 1820 default: ShouldNotReachHere(); | |
| 1821 } | |
| 1822 | |
| 1823 } else if (dest->is_double_cpu()) { | |
| 1824 #ifdef _LP64 | |
| 1825 Register dst_lo = dest->as_register_lo(); | |
| 1826 Register op1_lo = left->as_pointer_register(); | |
| 1827 Register op2_lo = right->as_pointer_register(); | |
| 1828 | |
| 1829 switch (code) { | |
| 1830 case lir_add: | |
| 1831 __ add(op1_lo, op2_lo, dst_lo); | |
| 1832 break; | |
| 1833 | |
| 1834 case lir_sub: | |
| 1835 __ sub(op1_lo, op2_lo, dst_lo); | |
| 1836 break; | |
| 1837 | |
| 1838 default: ShouldNotReachHere(); | |
| 1839 } | |
| 1840 #else | |
| 1841 Register op1_lo = left->as_register_lo(); | |
| 1842 Register op1_hi = left->as_register_hi(); | |
| 1843 Register op2_lo = right->as_register_lo(); | |
| 1844 Register op2_hi = right->as_register_hi(); | |
| 1845 Register dst_lo = dest->as_register_lo(); | |
| 1846 Register dst_hi = dest->as_register_hi(); | |
| 1847 | |
| 1848 switch (code) { | |
| 1849 case lir_add: | |
| 1850 __ addcc(op1_lo, op2_lo, dst_lo); | |
| 1851 __ addc (op1_hi, op2_hi, dst_hi); | |
| 1852 break; | |
| 1853 | |
| 1854 case lir_sub: | |
| 1855 __ subcc(op1_lo, op2_lo, dst_lo); | |
| 1856 __ subc (op1_hi, op2_hi, dst_hi); | |
| 1857 break; | |
| 1858 | |
| 1859 default: ShouldNotReachHere(); | |
| 1860 } | |
| 1861 #endif | |
| 1862 } else { | |
| 1863 assert (right->is_single_cpu(), "Just Checking"); | |
| 1864 | |
| 1865 Register lreg = left->as_register(); | |
| 1866 Register res = dest->as_register(); | |
| 1867 Register rreg = right->as_register(); | |
| 1868 switch (code) { | |
| 1869 case lir_add: __ add (lreg, rreg, res); break; | |
| 1870 case lir_sub: __ sub (lreg, rreg, res); break; | |
| 1871 case lir_mul: __ mult (lreg, rreg, res); break; | |
| 1872 default: ShouldNotReachHere(); | |
| 1873 } | |
| 1874 } | |
| 1875 } else { | |
| 1876 assert (right->is_constant(), "must be constant"); | |
| 1877 | |
| 1878 if (dest->is_single_cpu()) { | |
| 1879 Register lreg = left->as_register(); | |
| 1880 Register res = dest->as_register(); | |
| 1881 int simm13 = right->as_constant_ptr()->as_jint(); | |
| 1882 | |
| 1883 switch (code) { | |
| 1884 case lir_add: __ add (lreg, simm13, res); break; | |
| 1885 case lir_sub: __ sub (lreg, simm13, res); break; | |
| 1886 case lir_mul: __ mult (lreg, simm13, res); break; | |
| 1887 default: ShouldNotReachHere(); | |
| 1888 } | |
| 1889 } else { | |
| 1890 Register lreg = left->as_pointer_register(); | |
| 1891 Register res = dest->as_register_lo(); | |
| 1892 long con = right->as_constant_ptr()->as_jlong(); | |
| 1893 assert(Assembler::is_simm13(con), "must be simm13"); | |
| 1894 | |
| 1895 switch (code) { | |
| 1896 case lir_add: __ add (lreg, (int)con, res); break; | |
| 1897 case lir_sub: __ sub (lreg, (int)con, res); break; | |
| 1898 case lir_mul: __ mult (lreg, (int)con, res); break; | |
| 1899 default: ShouldNotReachHere(); | |
| 1900 } | |
| 1901 } | |
| 1902 } | |
| 1903 } | |
| 1904 | |
| 1905 | |
| 1906 void LIR_Assembler::fpop() { | |
| 1907 // do nothing | |
| 1908 } | |
| 1909 | |
| 1910 | |
| 1911 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) { | |
| 1912 switch (code) { | |
| 1913 case lir_sin: | |
| 1914 case lir_tan: | |
| 1915 case lir_cos: { | |
| 1916 assert(thread->is_valid(), "preserve the thread object for performance reasons"); | |
| 1917 assert(dest->as_double_reg() == F0, "the result will be in f0/f1"); | |
| 1918 break; | |
| 1919 } | |
| 1920 case lir_sqrt: { | |
| 1921 assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt"); | |
| 1922 FloatRegister src_reg = value->as_double_reg(); | |
| 1923 FloatRegister dst_reg = dest->as_double_reg(); | |
| 1924 __ fsqrt(FloatRegisterImpl::D, src_reg, dst_reg); | |
| 1925 break; | |
| 1926 } | |
| 1927 case lir_abs: { | |
| 1928 assert(!thread->is_valid(), "there is no need for a thread_reg for fabs"); | |
| 1929 FloatRegister src_reg = value->as_double_reg(); | |
| 1930 FloatRegister dst_reg = dest->as_double_reg(); | |
| 1931 __ fabs(FloatRegisterImpl::D, src_reg, dst_reg); | |
| 1932 break; | |
| 1933 } | |
| 1934 default: { | |
| 1935 ShouldNotReachHere(); | |
| 1936 break; | |
| 1937 } | |
| 1938 } | |
| 1939 } | |
| 1940 | |
| 1941 | |
| 1942 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) { | |
| 1943 if (right->is_constant()) { | |
| 1944 if (dest->is_single_cpu()) { | |
| 1945 int simm13 = right->as_constant_ptr()->as_jint(); | |
| 1946 switch (code) { | |
| 1947 case lir_logic_and: __ and3 (left->as_register(), simm13, dest->as_register()); break; | |
| 1948 case lir_logic_or: __ or3 (left->as_register(), simm13, dest->as_register()); break; | |
| 1949 case lir_logic_xor: __ xor3 (left->as_register(), simm13, dest->as_register()); break; | |
| 1950 default: ShouldNotReachHere(); | |
| 1951 } | |
| 1952 } else { | |
| 1953 long c = right->as_constant_ptr()->as_jlong(); | |
| 1954 assert(c == (int)c && Assembler::is_simm13(c), "out of range"); | |
| 1955 int simm13 = (int)c; | |
| 1956 switch (code) { | |
| 1957 case lir_logic_and: | |
| 1958 #ifndef _LP64 | |
| 1959 __ and3 (left->as_register_hi(), 0, dest->as_register_hi()); | |
| 1960 #endif | |
| 1961 __ and3 (left->as_register_lo(), simm13, dest->as_register_lo()); | |
| 1962 break; | |
| 1963 | |
| 1964 case lir_logic_or: | |
| 1965 #ifndef _LP64 | |
| 1966 __ or3 (left->as_register_hi(), 0, dest->as_register_hi()); | |
| 1967 #endif | |
| 1968 __ or3 (left->as_register_lo(), simm13, dest->as_register_lo()); | |
| 1969 break; | |
| 1970 | |
| 1971 case lir_logic_xor: | |
| 1972 #ifndef _LP64 | |
| 1973 __ xor3 (left->as_register_hi(), 0, dest->as_register_hi()); | |
| 1974 #endif | |
| 1975 __ xor3 (left->as_register_lo(), simm13, dest->as_register_lo()); | |
| 1976 break; | |
| 1977 | |
| 1978 default: ShouldNotReachHere(); | |
| 1979 } | |
| 1980 } | |
| 1981 } else { | |
| 1982 assert(right->is_register(), "right should be in register"); | |
| 1983 | |
| 1984 if (dest->is_single_cpu()) { | |
| 1985 switch (code) { | |
| 1986 case lir_logic_and: __ and3 (left->as_register(), right->as_register(), dest->as_register()); break; | |
| 1987 case lir_logic_or: __ or3 (left->as_register(), right->as_register(), dest->as_register()); break; | |
| 1988 case lir_logic_xor: __ xor3 (left->as_register(), right->as_register(), dest->as_register()); break; | |
| 1989 default: ShouldNotReachHere(); | |
| 1990 } | |
| 1991 } else { | |
| 1992 #ifdef _LP64 | |
| 1993 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() : | |
| 1994 left->as_register_lo(); | |
| 1995 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() : | |
| 1996 right->as_register_lo(); | |
| 1997 | |
| 1998 switch (code) { | |
| 1999 case lir_logic_and: __ and3 (l, r, dest->as_register_lo()); break; | |
| 2000 case lir_logic_or: __ or3 (l, r, dest->as_register_lo()); break; | |
| 2001 case lir_logic_xor: __ xor3 (l, r, dest->as_register_lo()); break; | |
| 2002 default: ShouldNotReachHere(); | |
| 2003 } | |
| 2004 #else | |
| 2005 switch (code) { | |
| 2006 case lir_logic_and: | |
| 2007 __ and3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi()); | |
| 2008 __ and3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo()); | |
| 2009 break; | |
| 2010 | |
| 2011 case lir_logic_or: | |
| 2012 __ or3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi()); | |
| 2013 __ or3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo()); | |
| 2014 break; | |
| 2015 | |
| 2016 case lir_logic_xor: | |
| 2017 __ xor3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi()); | |
| 2018 __ xor3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo()); | |
| 2019 break; | |
| 2020 | |
| 2021 default: ShouldNotReachHere(); | |
| 2022 } | |
| 2023 #endif | |
| 2024 } | |
| 2025 } | |
| 2026 } | |
| 2027 | |
| 2028 | |
| 2029 int LIR_Assembler::shift_amount(BasicType t) { | |
|
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2030 int elem_size = type2aelembytes(t); |
| 0 | 2031 switch (elem_size) { |
| 2032 case 1 : return 0; | |
| 2033 case 2 : return 1; | |
| 2034 case 4 : return 2; | |
| 2035 case 8 : return 3; | |
| 2036 } | |
| 2037 ShouldNotReachHere(); | |
| 2038 return -1; | |
| 2039 } | |
| 2040 | |
| 2041 | |
| 2042 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info, bool unwind) { | |
| 2043 assert(exceptionOop->as_register() == Oexception, "should match"); | |
| 2044 assert(unwind || exceptionPC->as_register() == Oissuing_pc, "should match"); | |
| 2045 | |
| 2046 info->add_register_oop(exceptionOop); | |
| 2047 | |
| 2048 if (unwind) { | |
| 2049 __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type); | |
| 2050 __ delayed()->nop(); | |
| 2051 } else { | |
| 2052 // reuse the debug info from the safepoint poll for the throw op itself | |
| 2053 address pc_for_athrow = __ pc(); | |
| 2054 int pc_for_athrow_offset = __ offset(); | |
| 2055 RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow); | |
| 727 | 2056 __ set(pc_for_athrow, Oissuing_pc, rspec); |
| 0 | 2057 add_call_info(pc_for_athrow_offset, info); // for exception handler |
| 2058 | |
| 2059 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type); | |
| 2060 __ delayed()->nop(); | |
| 2061 } | |
| 2062 } | |
| 2063 | |
| 2064 | |
| 2065 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { | |
| 2066 Register src = op->src()->as_register(); | |
| 2067 Register dst = op->dst()->as_register(); | |
| 2068 Register src_pos = op->src_pos()->as_register(); | |
| 2069 Register dst_pos = op->dst_pos()->as_register(); | |
| 2070 Register length = op->length()->as_register(); | |
| 2071 Register tmp = op->tmp()->as_register(); | |
| 2072 Register tmp2 = O7; | |
| 2073 | |
| 2074 int flags = op->flags(); | |
| 2075 ciArrayKlass* default_type = op->expected_type(); | |
| 2076 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; | |
| 2077 if (basic_type == T_ARRAY) basic_type = T_OBJECT; | |
| 2078 | |
| 2079 // set up the arraycopy stub information | |
| 2080 ArrayCopyStub* stub = op->stub(); | |
| 2081 | |
| 2082 // always do stub if no type information is available. it's ok if | |
| 2083 // the known type isn't loaded since the code sanity checks | |
| 2084 // in debug mode and the type isn't required when we know the exact type | |
| 2085 // also check that the type is an array type. | |
|
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2086 // We also, for now, always call the stub if the barrier set requires a |
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2087 // write_ref_pre barrier (which the stub does, but none of the optimized |
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2088 // cases currently does). |
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2089 if (op->expected_type() == NULL || |
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2090 Universe::heap()->barrier_set()->has_write_ref_pre_barrier()) { |
| 0 | 2091 __ mov(src, O0); |
| 2092 __ mov(src_pos, O1); | |
| 2093 __ mov(dst, O2); | |
| 2094 __ mov(dst_pos, O3); | |
| 2095 __ mov(length, O4); | |
| 2096 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::arraycopy)); | |
| 2097 | |
| 2098 __ br_zero(Assembler::less, false, Assembler::pn, O0, *stub->entry()); | |
| 2099 __ delayed()->nop(); | |
| 2100 __ bind(*stub->continuation()); | |
| 2101 return; | |
| 2102 } | |
| 2103 | |
| 2104 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point"); | |
| 2105 | |
| 2106 // make sure src and dst are non-null and load array length | |
| 2107 if (flags & LIR_OpArrayCopy::src_null_check) { | |
| 2108 __ tst(src); | |
| 2109 __ br(Assembler::equal, false, Assembler::pn, *stub->entry()); | |
| 2110 __ delayed()->nop(); | |
| 2111 } | |
| 2112 | |
| 2113 if (flags & LIR_OpArrayCopy::dst_null_check) { | |
| 2114 __ tst(dst); | |
| 2115 __ br(Assembler::equal, false, Assembler::pn, *stub->entry()); | |
| 2116 __ delayed()->nop(); | |
| 2117 } | |
| 2118 | |
| 2119 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { | |
| 2120 // test src_pos register | |
| 2121 __ tst(src_pos); | |
| 2122 __ br(Assembler::less, false, Assembler::pn, *stub->entry()); | |
| 2123 __ delayed()->nop(); | |
| 2124 } | |
| 2125 | |
| 2126 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { | |
| 2127 // test dst_pos register | |
| 2128 __ tst(dst_pos); | |
| 2129 __ br(Assembler::less, false, Assembler::pn, *stub->entry()); | |
| 2130 __ delayed()->nop(); | |
| 2131 } | |
| 2132 | |
| 2133 if (flags & LIR_OpArrayCopy::length_positive_check) { | |
| 2134 // make sure length isn't negative | |
| 2135 __ tst(length); | |
| 2136 __ br(Assembler::less, false, Assembler::pn, *stub->entry()); | |
| 2137 __ delayed()->nop(); | |
| 2138 } | |
| 2139 | |
| 2140 if (flags & LIR_OpArrayCopy::src_range_check) { | |
| 2141 __ ld(src, arrayOopDesc::length_offset_in_bytes(), tmp2); | |
| 2142 __ add(length, src_pos, tmp); | |
| 2143 __ cmp(tmp2, tmp); | |
| 2144 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry()); | |
| 2145 __ delayed()->nop(); | |
| 2146 } | |
| 2147 | |
| 2148 if (flags & LIR_OpArrayCopy::dst_range_check) { | |
| 2149 __ ld(dst, arrayOopDesc::length_offset_in_bytes(), tmp2); | |
| 2150 __ add(length, dst_pos, tmp); | |
| 2151 __ cmp(tmp2, tmp); | |
| 2152 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry()); | |
| 2153 __ delayed()->nop(); | |
| 2154 } | |
| 2155 | |
| 2156 if (flags & LIR_OpArrayCopy::type_check) { | |
| 2157 __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp); | |
| 2158 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2); | |
| 2159 __ cmp(tmp, tmp2); | |
| 2160 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry()); | |
| 2161 __ delayed()->nop(); | |
| 2162 } | |
| 2163 | |
| 2164 #ifdef ASSERT | |
| 2165 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { | |
| 2166 // Sanity check the known type with the incoming class. For the | |
| 2167 // primitive case the types must match exactly with src.klass and | |
| 2168 // dst.klass each exactly matching the default type. For the | |
| 2169 // object array case, if no type check is needed then either the | |
| 2170 // dst type is exactly the expected type and the src type is a | |
| 2171 // subtype which we can't check or src is the same array as dst | |
| 2172 // but not necessarily exactly of type default_type. | |
| 2173 Label known_ok, halt; | |
|
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2174 jobject2reg(op->expected_type()->constant_encoding(), tmp); |
| 0 | 2175 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2); |
| 2176 if (basic_type != T_OBJECT) { | |
| 2177 __ cmp(tmp, tmp2); | |
| 2178 __ br(Assembler::notEqual, false, Assembler::pn, halt); | |
| 2179 __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2); | |
| 2180 __ cmp(tmp, tmp2); | |
| 2181 __ br(Assembler::equal, false, Assembler::pn, known_ok); | |
| 2182 __ delayed()->nop(); | |
| 2183 } else { | |
| 2184 __ cmp(tmp, tmp2); | |
| 2185 __ br(Assembler::equal, false, Assembler::pn, known_ok); | |
| 2186 __ delayed()->cmp(src, dst); | |
| 2187 __ br(Assembler::equal, false, Assembler::pn, known_ok); | |
| 2188 __ delayed()->nop(); | |
| 2189 } | |
| 2190 __ bind(halt); | |
| 2191 __ stop("incorrect type information in arraycopy"); | |
| 2192 __ bind(known_ok); | |
| 2193 } | |
| 2194 #endif | |
| 2195 | |
| 2196 int shift = shift_amount(basic_type); | |
| 2197 | |
| 2198 Register src_ptr = O0; | |
| 2199 Register dst_ptr = O1; | |
| 2200 Register len = O2; | |
| 2201 | |
| 2202 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr); | |
| 2203 if (shift == 0) { | |
| 2204 __ add(src_ptr, src_pos, src_ptr); | |
| 2205 } else { | |
| 2206 __ sll(src_pos, shift, tmp); | |
| 2207 __ add(src_ptr, tmp, src_ptr); | |
| 2208 } | |
| 2209 | |
| 2210 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr); | |
| 2211 if (shift == 0) { | |
| 2212 __ add(dst_ptr, dst_pos, dst_ptr); | |
| 2213 } else { | |
| 2214 __ sll(dst_pos, shift, tmp); | |
| 2215 __ add(dst_ptr, tmp, dst_ptr); | |
| 2216 } | |
| 2217 | |
| 2218 if (basic_type != T_OBJECT) { | |
| 2219 if (shift == 0) { | |
| 2220 __ mov(length, len); | |
| 2221 } else { | |
| 2222 __ sll(length, shift, len); | |
| 2223 } | |
| 2224 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::primitive_arraycopy)); | |
| 2225 } else { | |
| 2226 // oop_arraycopy takes a length in number of elements, so don't scale it. | |
| 2227 __ mov(length, len); | |
| 2228 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy)); | |
| 2229 } | |
| 2230 | |
| 2231 __ bind(*stub->continuation()); | |
| 2232 } | |
| 2233 | |
| 2234 | |
| 2235 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { | |
| 2236 if (dest->is_single_cpu()) { | |
| 2237 #ifdef _LP64 | |
| 2238 if (left->type() == T_OBJECT) { | |
| 2239 switch (code) { | |
| 2240 case lir_shl: __ sllx (left->as_register(), count->as_register(), dest->as_register()); break; | |
| 2241 case lir_shr: __ srax (left->as_register(), count->as_register(), dest->as_register()); break; | |
| 2242 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break; | |
| 2243 default: ShouldNotReachHere(); | |
| 2244 } | |
| 2245 } else | |
| 2246 #endif | |
| 2247 switch (code) { | |
| 2248 case lir_shl: __ sll (left->as_register(), count->as_register(), dest->as_register()); break; | |
| 2249 case lir_shr: __ sra (left->as_register(), count->as_register(), dest->as_register()); break; | |
| 2250 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break; | |
| 2251 default: ShouldNotReachHere(); | |
| 2252 } | |
| 2253 } else { | |
| 2254 #ifdef _LP64 | |
| 2255 switch (code) { | |
| 2256 case lir_shl: __ sllx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break; | |
| 2257 case lir_shr: __ srax (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break; | |
| 2258 case lir_ushr: __ srlx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break; | |
| 2259 default: ShouldNotReachHere(); | |
| 2260 } | |
| 2261 #else | |
| 2262 switch (code) { | |
| 2263 case lir_shl: __ lshl (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break; | |
| 2264 case lir_shr: __ lshr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break; | |
| 2265 case lir_ushr: __ lushr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break; | |
| 2266 default: ShouldNotReachHere(); | |
| 2267 } | |
| 2268 #endif | |
| 2269 } | |
| 2270 } | |
| 2271 | |
| 2272 | |
| 2273 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { | |
| 2274 #ifdef _LP64 | |
| 2275 if (left->type() == T_OBJECT) { | |
| 2276 count = count & 63; // shouldn't shift by more than sizeof(intptr_t) | |
| 2277 Register l = left->as_register(); | |
| 2278 Register d = dest->as_register_lo(); | |
| 2279 switch (code) { | |
| 2280 case lir_shl: __ sllx (l, count, d); break; | |
| 2281 case lir_shr: __ srax (l, count, d); break; | |
| 2282 case lir_ushr: __ srlx (l, count, d); break; | |
| 2283 default: ShouldNotReachHere(); | |
| 2284 } | |
| 2285 return; | |
| 2286 } | |
| 2287 #endif | |
| 2288 | |
| 2289 if (dest->is_single_cpu()) { | |
| 2290 count = count & 0x1F; // Java spec | |
| 2291 switch (code) { | |
| 2292 case lir_shl: __ sll (left->as_register(), count, dest->as_register()); break; | |
| 2293 case lir_shr: __ sra (left->as_register(), count, dest->as_register()); break; | |
| 2294 case lir_ushr: __ srl (left->as_register(), count, dest->as_register()); break; | |
| 2295 default: ShouldNotReachHere(); | |
| 2296 } | |
| 2297 } else if (dest->is_double_cpu()) { | |
| 2298 count = count & 63; // Java spec | |
| 2299 switch (code) { | |
| 2300 case lir_shl: __ sllx (left->as_pointer_register(), count, dest->as_pointer_register()); break; | |
| 2301 case lir_shr: __ srax (left->as_pointer_register(), count, dest->as_pointer_register()); break; | |
| 2302 case lir_ushr: __ srlx (left->as_pointer_register(), count, dest->as_pointer_register()); break; | |
| 2303 default: ShouldNotReachHere(); | |
| 2304 } | |
| 2305 } else { | |
| 2306 ShouldNotReachHere(); | |
| 2307 } | |
| 2308 } | |
| 2309 | |
| 2310 | |
| 2311 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { | |
| 2312 assert(op->tmp1()->as_register() == G1 && | |
| 2313 op->tmp2()->as_register() == G3 && | |
| 2314 op->tmp3()->as_register() == G4 && | |
| 2315 op->obj()->as_register() == O0 && | |
| 2316 op->klass()->as_register() == G5, "must be"); | |
| 2317 if (op->init_check()) { | |
| 2318 __ ld(op->klass()->as_register(), | |
| 2319 instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc), | |
| 2320 op->tmp1()->as_register()); | |
| 2321 add_debug_info_for_null_check_here(op->stub()->info()); | |
| 2322 __ cmp(op->tmp1()->as_register(), instanceKlass::fully_initialized); | |
| 2323 __ br(Assembler::notEqual, false, Assembler::pn, *op->stub()->entry()); | |
| 2324 __ delayed()->nop(); | |
| 2325 } | |
| 2326 __ allocate_object(op->obj()->as_register(), | |
| 2327 op->tmp1()->as_register(), | |
| 2328 op->tmp2()->as_register(), | |
| 2329 op->tmp3()->as_register(), | |
| 2330 op->header_size(), | |
| 2331 op->object_size(), | |
| 2332 op->klass()->as_register(), | |
| 2333 *op->stub()->entry()); | |
| 2334 __ bind(*op->stub()->continuation()); | |
| 2335 __ verify_oop(op->obj()->as_register()); | |
| 2336 } | |
| 2337 | |
| 2338 | |
| 2339 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { | |
| 2340 assert(op->tmp1()->as_register() == G1 && | |
| 2341 op->tmp2()->as_register() == G3 && | |
| 2342 op->tmp3()->as_register() == G4 && | |
| 2343 op->tmp4()->as_register() == O1 && | |
| 2344 op->klass()->as_register() == G5, "must be"); | |
| 2345 if (UseSlowPath || | |
| 2346 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || | |
| 2347 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { | |
| 2348 __ br(Assembler::always, false, Assembler::pn, *op->stub()->entry()); | |
| 2349 __ delayed()->nop(); | |
| 2350 } else { | |
| 2351 __ allocate_array(op->obj()->as_register(), | |
| 2352 op->len()->as_register(), | |
| 2353 op->tmp1()->as_register(), | |
| 2354 op->tmp2()->as_register(), | |
| 2355 op->tmp3()->as_register(), | |
| 2356 arrayOopDesc::header_size(op->type()), | |
|
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2357 type2aelembytes(op->type()), |
| 0 | 2358 op->klass()->as_register(), |
| 2359 *op->stub()->entry()); | |
| 2360 } | |
| 2361 __ bind(*op->stub()->continuation()); | |
| 2362 } | |
| 2363 | |
| 2364 | |
| 2365 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { | |
| 2366 LIR_Code code = op->code(); | |
| 2367 if (code == lir_store_check) { | |
| 2368 Register value = op->object()->as_register(); | |
| 2369 Register array = op->array()->as_register(); | |
| 2370 Register k_RInfo = op->tmp1()->as_register(); | |
| 2371 Register klass_RInfo = op->tmp2()->as_register(); | |
| 2372 Register Rtmp1 = op->tmp3()->as_register(); | |
| 2373 | |
| 2374 __ verify_oop(value); | |
| 2375 | |
| 2376 CodeStub* stub = op->stub(); | |
| 2377 Label done; | |
| 2378 __ cmp(value, 0); | |
| 2379 __ br(Assembler::equal, false, Assembler::pn, done); | |
| 2380 __ delayed()->nop(); | |
| 2381 load(array, oopDesc::klass_offset_in_bytes(), k_RInfo, T_OBJECT, op->info_for_exception()); | |
| 2382 load(value, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL); | |
| 2383 | |
| 2384 // get instance klass | |
| 2385 load(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc), k_RInfo, T_OBJECT, NULL); | |
|
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2386 // perform the fast part of the checking logic |
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2387 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, &done, stub->entry(), NULL); |
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2388 |
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2389 // call out-of-line instance of __ check_klass_subtype_slow_path(...): |
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2390 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup"); |
| 0 | 2391 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); |
| 2392 __ delayed()->nop(); | |
| 2393 __ cmp(G3, 0); | |
| 2394 __ br(Assembler::equal, false, Assembler::pn, *stub->entry()); | |
| 2395 __ delayed()->nop(); | |
| 2396 __ bind(done); | |
| 2397 } else if (op->code() == lir_checkcast) { | |
| 2398 // we always need a stub for the failure case. | |
| 2399 CodeStub* stub = op->stub(); | |
| 2400 Register obj = op->object()->as_register(); | |
| 2401 Register k_RInfo = op->tmp1()->as_register(); | |
| 2402 Register klass_RInfo = op->tmp2()->as_register(); | |
| 2403 Register dst = op->result_opr()->as_register(); | |
| 2404 Register Rtmp1 = op->tmp3()->as_register(); | |
| 2405 ciKlass* k = op->klass(); | |
| 2406 | |
| 2407 if (obj == k_RInfo) { | |
| 2408 k_RInfo = klass_RInfo; | |
| 2409 klass_RInfo = obj; | |
| 2410 } | |
| 2411 if (op->profiled_method() != NULL) { | |
| 2412 ciMethod* method = op->profiled_method(); | |
| 2413 int bci = op->profiled_bci(); | |
| 2414 | |
| 2415 // We need two temporaries to perform this operation on SPARC, | |
| 2416 // so to keep things simple we perform a redundant test here | |
| 2417 Label profile_done; | |
| 2418 __ cmp(obj, 0); | |
| 2419 __ br(Assembler::notEqual, false, Assembler::pn, profile_done); | |
| 2420 __ delayed()->nop(); | |
| 2421 // Object is null; update methodDataOop | |
| 2422 ciMethodData* md = method->method_data(); | |
| 2423 if (md == NULL) { | |
| 2424 bailout("out of memory building methodDataOop"); | |
| 2425 return; | |
| 2426 } | |
| 2427 ciProfileData* data = md->bci_to_data(bci); | |
| 2428 assert(data != NULL, "need data for checkcast"); | |
| 2429 assert(data->is_BitData(), "need BitData for checkcast"); | |
| 2430 Register mdo = k_RInfo; | |
| 2431 Register data_val = Rtmp1; | |
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2432 jobject2reg(md->constant_encoding(), mdo); |
| 0 | 2433 |
| 2434 int mdo_offset_bias = 0; | |
| 2435 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) { | |
| 2436 // The offset is large so bias the mdo by the base of the slot so | |
| 2437 // that the ld can use simm13s to reference the slots of the data | |
| 2438 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset()); | |
| 2439 __ set(mdo_offset_bias, data_val); | |
| 2440 __ add(mdo, data_val, mdo); | |
| 2441 } | |
| 2442 | |
| 2443 | |
| 727 | 2444 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias); |
| 0 | 2445 __ ldub(flags_addr, data_val); |
| 2446 __ or3(data_val, BitData::null_seen_byte_constant(), data_val); | |
| 2447 __ stb(data_val, flags_addr); | |
| 2448 __ bind(profile_done); | |
| 2449 } | |
| 2450 | |
| 2451 Label done; | |
| 2452 // patching may screw with our temporaries on sparc, | |
| 2453 // so let's do it before loading the class | |
| 2454 if (k->is_loaded()) { | |
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2455 jobject2reg(k->constant_encoding(), k_RInfo); |
| 0 | 2456 } else { |
| 2457 jobject2reg_with_patching(k_RInfo, op->info_for_patch()); | |
| 2458 } | |
| 2459 assert(obj != k_RInfo, "must be different"); | |
| 2460 __ cmp(obj, 0); | |
| 2461 __ br(Assembler::equal, false, Assembler::pn, done); | |
| 2462 __ delayed()->nop(); | |
| 2463 | |
| 2464 // get object class | |
| 2465 // not a safepoint as obj null check happens earlier | |
| 2466 load(obj, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL); | |
| 2467 if (op->fast_check()) { | |
| 2468 assert_different_registers(klass_RInfo, k_RInfo); | |
| 2469 __ cmp(k_RInfo, klass_RInfo); | |
| 2470 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry()); | |
| 2471 __ delayed()->nop(); | |
| 2472 __ bind(done); | |
| 2473 } else { | |
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2474 bool need_slow_path = true; |
| 0 | 2475 if (k->is_loaded()) { |
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2476 if (k->super_check_offset() != sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes()) |
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2477 need_slow_path = false; |
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2478 // perform the fast part of the checking logic |
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2479 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, noreg, |
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2480 (need_slow_path ? &done : NULL), |
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2481 stub->entry(), NULL, |
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2482 RegisterOrConstant(k->super_check_offset())); |
| 0 | 2483 } else { |
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2484 // perform the fast part of the checking logic |
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2485 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, |
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2486 &done, stub->entry(), NULL); |
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2487 } |
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2488 if (need_slow_path) { |
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2489 // call out-of-line instance of __ check_klass_subtype_slow_path(...): |
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2490 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup"); |
| 0 | 2491 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); |
| 2492 __ delayed()->nop(); | |
| 2493 __ cmp(G3, 0); | |
| 2494 __ br(Assembler::equal, false, Assembler::pn, *stub->entry()); | |
| 2495 __ delayed()->nop(); | |
| 2496 } | |
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2497 __ bind(done); |
| 0 | 2498 } |
| 2499 __ mov(obj, dst); | |
| 2500 } else if (code == lir_instanceof) { | |
| 2501 Register obj = op->object()->as_register(); | |
| 2502 Register k_RInfo = op->tmp1()->as_register(); | |
| 2503 Register klass_RInfo = op->tmp2()->as_register(); | |
| 2504 Register dst = op->result_opr()->as_register(); | |
| 2505 Register Rtmp1 = op->tmp3()->as_register(); | |
| 2506 ciKlass* k = op->klass(); | |
| 2507 | |
| 2508 Label done; | |
| 2509 if (obj == k_RInfo) { | |
| 2510 k_RInfo = klass_RInfo; | |
| 2511 klass_RInfo = obj; | |
| 2512 } | |
| 2513 // patching may screw with our temporaries on sparc, | |
| 2514 // so let's do it before loading the class | |
| 2515 if (k->is_loaded()) { | |
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2516 jobject2reg(k->constant_encoding(), k_RInfo); |
| 0 | 2517 } else { |
| 2518 jobject2reg_with_patching(k_RInfo, op->info_for_patch()); | |
| 2519 } | |
| 2520 assert(obj != k_RInfo, "must be different"); | |
| 2521 __ cmp(obj, 0); | |
| 2522 __ br(Assembler::equal, true, Assembler::pn, done); | |
| 2523 __ delayed()->set(0, dst); | |
| 2524 | |
| 2525 // get object class | |
| 2526 // not a safepoint as obj null check happens earlier | |
| 2527 load(obj, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL); | |
| 2528 if (op->fast_check()) { | |
| 2529 __ cmp(k_RInfo, klass_RInfo); | |
| 2530 __ br(Assembler::equal, true, Assembler::pt, done); | |
| 2531 __ delayed()->set(1, dst); | |
| 2532 __ set(0, dst); | |
| 2533 __ bind(done); | |
| 2534 } else { | |
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2535 bool need_slow_path = true; |
| 0 | 2536 if (k->is_loaded()) { |
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2537 if (k->super_check_offset() != sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes()) |
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2538 need_slow_path = false; |
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2539 // perform the fast part of the checking logic |
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2540 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, O7, noreg, |
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2541 (need_slow_path ? &done : NULL), |
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2542 (need_slow_path ? &done : NULL), NULL, |
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2543 RegisterOrConstant(k->super_check_offset()), |
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2544 dst); |
| 0 | 2545 } else { |
| 2546 assert(dst != klass_RInfo && dst != k_RInfo, "need 3 registers"); | |
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2547 // perform the fast part of the checking logic |
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2548 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, O7, dst, |
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2549 &done, &done, NULL, |
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2550 RegisterOrConstant(-1), |
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2551 dst); |
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2552 } |
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2553 if (need_slow_path) { |
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2554 // call out-of-line instance of __ check_klass_subtype_slow_path(...): |
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2555 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup"); |
| 0 | 2556 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); |
| 2557 __ delayed()->nop(); | |
| 2558 __ mov(G3, dst); | |
| 2559 } | |
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2560 __ bind(done); |
| 0 | 2561 } |
| 2562 } else { | |
| 2563 ShouldNotReachHere(); | |
| 2564 } | |
| 2565 | |
| 2566 } | |
| 2567 | |
| 2568 | |
| 2569 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { | |
| 2570 if (op->code() == lir_cas_long) { | |
| 2571 assert(VM_Version::supports_cx8(), "wrong machine"); | |
| 2572 Register addr = op->addr()->as_pointer_register(); | |
| 2573 Register cmp_value_lo = op->cmp_value()->as_register_lo(); | |
| 2574 Register cmp_value_hi = op->cmp_value()->as_register_hi(); | |
| 2575 Register new_value_lo = op->new_value()->as_register_lo(); | |
| 2576 Register new_value_hi = op->new_value()->as_register_hi(); | |
| 2577 Register t1 = op->tmp1()->as_register(); | |
| 2578 Register t2 = op->tmp2()->as_register(); | |
| 2579 #ifdef _LP64 | |
| 2580 __ mov(cmp_value_lo, t1); | |
| 2581 __ mov(new_value_lo, t2); | |
| 2582 #else | |
| 2583 // move high and low halves of long values into single registers | |
| 2584 __ sllx(cmp_value_hi, 32, t1); // shift high half into temp reg | |
| 2585 __ srl(cmp_value_lo, 0, cmp_value_lo); // clear upper 32 bits of low half | |
| 2586 __ or3(t1, cmp_value_lo, t1); // t1 holds 64-bit compare value | |
| 2587 __ sllx(new_value_hi, 32, t2); | |
| 2588 __ srl(new_value_lo, 0, new_value_lo); | |
| 2589 __ or3(t2, new_value_lo, t2); // t2 holds 64-bit value to swap | |
| 2590 #endif | |
| 2591 // perform the compare and swap operation | |
| 2592 __ casx(addr, t1, t2); | |
| 2593 // generate condition code - if the swap succeeded, t2 ("new value" reg) was | |
| 2594 // overwritten with the original value in "addr" and will be equal to t1. | |
| 2595 __ cmp(t1, t2); | |
| 2596 | |
| 2597 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) { | |
| 2598 Register addr = op->addr()->as_pointer_register(); | |
| 2599 Register cmp_value = op->cmp_value()->as_register(); | |
| 2600 Register new_value = op->new_value()->as_register(); | |
| 2601 Register t1 = op->tmp1()->as_register(); | |
| 2602 Register t2 = op->tmp2()->as_register(); | |
| 2603 __ mov(cmp_value, t1); | |
| 2604 __ mov(new_value, t2); | |
| 2605 #ifdef _LP64 | |
| 2606 if (op->code() == lir_cas_obj) { | |
| 2607 __ casx(addr, t1, t2); | |
| 2608 } else | |
| 2609 #endif | |
| 2610 { | |
| 2611 __ cas(addr, t1, t2); | |
| 2612 } | |
| 2613 __ cmp(t1, t2); | |
| 2614 } else { | |
| 2615 Unimplemented(); | |
| 2616 } | |
| 2617 } | |
| 2618 | |
| 2619 void LIR_Assembler::set_24bit_FPU() { | |
| 2620 Unimplemented(); | |
| 2621 } | |
| 2622 | |
| 2623 | |
| 2624 void LIR_Assembler::reset_FPU() { | |
| 2625 Unimplemented(); | |
| 2626 } | |
| 2627 | |
| 2628 | |
| 2629 void LIR_Assembler::breakpoint() { | |
| 2630 __ breakpoint_trap(); | |
| 2631 } | |
| 2632 | |
| 2633 | |
| 2634 void LIR_Assembler::push(LIR_Opr opr) { | |
| 2635 Unimplemented(); | |
| 2636 } | |
| 2637 | |
| 2638 | |
| 2639 void LIR_Assembler::pop(LIR_Opr opr) { | |
| 2640 Unimplemented(); | |
| 2641 } | |
| 2642 | |
| 2643 | |
| 2644 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) { | |
| 2645 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no); | |
| 2646 Register dst = dst_opr->as_register(); | |
| 2647 Register reg = mon_addr.base(); | |
| 2648 int offset = mon_addr.disp(); | |
| 2649 // compute pointer to BasicLock | |
| 2650 if (mon_addr.is_simm13()) { | |
| 2651 __ add(reg, offset, dst); | |
| 2652 } else { | |
| 2653 __ set(offset, dst); | |
| 2654 __ add(dst, reg, dst); | |
| 2655 } | |
| 2656 } | |
| 2657 | |
| 2658 | |
| 2659 void LIR_Assembler::emit_lock(LIR_OpLock* op) { | |
| 2660 Register obj = op->obj_opr()->as_register(); | |
| 2661 Register hdr = op->hdr_opr()->as_register(); | |
| 2662 Register lock = op->lock_opr()->as_register(); | |
| 2663 | |
| 2664 // obj may not be an oop | |
| 2665 if (op->code() == lir_lock) { | |
| 2666 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub(); | |
| 2667 if (UseFastLocking) { | |
| 2668 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); | |
| 2669 // add debug info for NullPointerException only if one is possible | |
| 2670 if (op->info() != NULL) { | |
| 2671 add_debug_info_for_null_check_here(op->info()); | |
| 2672 } | |
| 2673 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry()); | |
| 2674 } else { | |
| 2675 // always do slow locking | |
| 2676 // note: the slow locking code could be inlined here, however if we use | |
| 2677 // slow locking, speed doesn't matter anyway and this solution is | |
| 2678 // simpler and requires less duplicated code - additionally, the | |
| 2679 // slow locking code is the same in either case which simplifies | |
| 2680 // debugging | |
| 2681 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry()); | |
| 2682 __ delayed()->nop(); | |
| 2683 } | |
| 2684 } else { | |
| 2685 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock"); | |
| 2686 if (UseFastLocking) { | |
| 2687 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); | |
| 2688 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); | |
| 2689 } else { | |
| 2690 // always do slow unlocking | |
| 2691 // note: the slow unlocking code could be inlined here, however if we use | |
| 2692 // slow unlocking, speed doesn't matter anyway and this solution is | |
| 2693 // simpler and requires less duplicated code - additionally, the | |
| 2694 // slow unlocking code is the same in either case which simplifies | |
| 2695 // debugging | |
| 2696 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry()); | |
| 2697 __ delayed()->nop(); | |
| 2698 } | |
| 2699 } | |
| 2700 __ bind(*op->stub()->continuation()); | |
| 2701 } | |
| 2702 | |
| 2703 | |
| 2704 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { | |
| 2705 ciMethod* method = op->profiled_method(); | |
| 2706 int bci = op->profiled_bci(); | |
| 2707 | |
| 2708 // Update counter for all call types | |
| 2709 ciMethodData* md = method->method_data(); | |
| 2710 if (md == NULL) { | |
| 2711 bailout("out of memory building methodDataOop"); | |
| 2712 return; | |
| 2713 } | |
| 2714 ciProfileData* data = md->bci_to_data(bci); | |
| 2715 assert(data->is_CounterData(), "need CounterData for calls"); | |
| 2716 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); | |
| 2717 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated"); | |
| 2718 Register mdo = op->mdo()->as_register(); | |
| 2719 Register tmp1 = op->tmp1()->as_register(); | |
|
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|
2720 jobject2reg(md->constant_encoding(), mdo); |
| 0 | 2721 int mdo_offset_bias = 0; |
| 2722 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, CounterData::count_offset()) + | |
| 2723 data->size_in_bytes())) { | |
| 2724 // The offset is large so bias the mdo by the base of the slot so | |
| 2725 // that the ld can use simm13s to reference the slots of the data | |
| 2726 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset()); | |
| 2727 __ set(mdo_offset_bias, O7); | |
| 2728 __ add(mdo, O7, mdo); | |
| 2729 } | |
| 2730 | |
| 727 | 2731 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias); |
| 0 | 2732 __ lduw(counter_addr, tmp1); |
| 2733 __ add(tmp1, DataLayout::counter_increment, tmp1); | |
| 2734 __ stw(tmp1, counter_addr); | |
| 2735 Bytecodes::Code bc = method->java_code_at_bci(bci); | |
| 2736 // Perform additional virtual call profiling for invokevirtual and | |
| 2737 // invokeinterface bytecodes | |
| 2738 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) && | |
| 2739 Tier1ProfileVirtualCalls) { | |
| 2740 assert(op->recv()->is_single_cpu(), "recv must be allocated"); | |
| 2741 Register recv = op->recv()->as_register(); | |
| 2742 assert_different_registers(mdo, tmp1, recv); | |
| 2743 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); | |
| 2744 ciKlass* known_klass = op->known_holder(); | |
| 2745 if (Tier1OptimizeVirtualCallProfiling && known_klass != NULL) { | |
| 2746 // We know the type that will be seen at this call site; we can | |
| 2747 // statically update the methodDataOop rather than needing to do | |
| 2748 // dynamic tests on the receiver type | |
| 2749 | |
| 2750 // NOTE: we should probably put a lock around this search to | |
| 2751 // avoid collisions by concurrent compilations | |
| 2752 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; | |
| 2753 uint i; | |
| 2754 for (i = 0; i < VirtualCallData::row_limit(); i++) { | |
| 2755 ciKlass* receiver = vc_data->receiver(i); | |
| 2756 if (known_klass->equals(receiver)) { | |
| 727 | 2757 Address data_addr(mdo, md->byte_offset_of_slot(data, |
| 2758 VirtualCallData::receiver_count_offset(i)) - | |
| 0 | 2759 mdo_offset_bias); |
| 2760 __ lduw(data_addr, tmp1); | |
| 2761 __ add(tmp1, DataLayout::counter_increment, tmp1); | |
| 2762 __ stw(tmp1, data_addr); | |
| 2763 return; | |
| 2764 } | |
| 2765 } | |
| 2766 | |
| 2767 // Receiver type not found in profile data; select an empty slot | |
| 2768 | |
| 2769 // Note that this is less efficient than it should be because it | |
| 2770 // always does a write to the receiver part of the | |
| 2771 // VirtualCallData rather than just the first time | |
| 2772 for (i = 0; i < VirtualCallData::row_limit(); i++) { | |
| 2773 ciKlass* receiver = vc_data->receiver(i); | |
| 2774 if (receiver == NULL) { | |
| 727 | 2775 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - |
| 0 | 2776 mdo_offset_bias); |
|
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diff
changeset
|
2777 jobject2reg(known_klass->constant_encoding(), tmp1); |
| 0 | 2778 __ st_ptr(tmp1, recv_addr); |
| 727 | 2779 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - |
| 0 | 2780 mdo_offset_bias); |
| 2781 __ lduw(data_addr, tmp1); | |
| 2782 __ add(tmp1, DataLayout::counter_increment, tmp1); | |
| 2783 __ stw(tmp1, data_addr); | |
| 2784 return; | |
| 2785 } | |
| 2786 } | |
| 2787 } else { | |
| 727 | 2788 load(Address(recv, oopDesc::klass_offset_in_bytes()), recv, T_OBJECT); |
| 0 | 2789 Label update_done; |
| 2790 uint i; | |
| 2791 for (i = 0; i < VirtualCallData::row_limit(); i++) { | |
| 2792 Label next_test; | |
| 2793 // See if the receiver is receiver[n]. | |
| 727 | 2794 Address receiver_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - |
| 0 | 2795 mdo_offset_bias); |
| 2796 __ ld_ptr(receiver_addr, tmp1); | |
| 2797 __ verify_oop(tmp1); | |
| 2798 __ cmp(recv, tmp1); | |
| 2799 __ brx(Assembler::notEqual, false, Assembler::pt, next_test); | |
| 2800 __ delayed()->nop(); | |
| 727 | 2801 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - |
| 0 | 2802 mdo_offset_bias); |
| 2803 __ lduw(data_addr, tmp1); | |
| 2804 __ add(tmp1, DataLayout::counter_increment, tmp1); | |
| 2805 __ stw(tmp1, data_addr); | |
| 2806 __ br(Assembler::always, false, Assembler::pt, update_done); | |
| 2807 __ delayed()->nop(); | |
| 2808 __ bind(next_test); | |
| 2809 } | |
| 2810 | |
| 2811 // Didn't find receiver; find next empty slot and fill it in | |
| 2812 for (i = 0; i < VirtualCallData::row_limit(); i++) { | |
| 2813 Label next_test; | |
| 727 | 2814 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - |
| 0 | 2815 mdo_offset_bias); |
| 2816 load(recv_addr, tmp1, T_OBJECT); | |
| 2817 __ tst(tmp1); | |
| 2818 __ brx(Assembler::notEqual, false, Assembler::pt, next_test); | |
| 2819 __ delayed()->nop(); | |
| 2820 __ st_ptr(recv, recv_addr); | |
| 2821 __ set(DataLayout::counter_increment, tmp1); | |
| 727 | 2822 __ st_ptr(tmp1, mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - |
| 2823 mdo_offset_bias); | |
| 0 | 2824 if (i < (VirtualCallData::row_limit() - 1)) { |
| 2825 __ br(Assembler::always, false, Assembler::pt, update_done); | |
| 2826 __ delayed()->nop(); | |
| 2827 } | |
| 2828 __ bind(next_test); | |
| 2829 } | |
| 2830 | |
| 2831 __ bind(update_done); | |
| 2832 } | |
| 2833 } | |
| 2834 } | |
| 2835 | |
| 2836 | |
| 2837 void LIR_Assembler::align_backward_branch_target() { | |
| 2838 __ align(16); | |
| 2839 } | |
| 2840 | |
| 2841 | |
| 2842 void LIR_Assembler::emit_delay(LIR_OpDelay* op) { | |
| 2843 // make sure we are expecting a delay | |
| 2844 // this has the side effect of clearing the delay state | |
| 2845 // so we can use _masm instead of _masm->delayed() to do the | |
| 2846 // code generation. | |
| 2847 __ delayed(); | |
| 2848 | |
| 2849 // make sure we only emit one instruction | |
| 2850 int offset = code_offset(); | |
| 2851 op->delay_op()->emit_code(this); | |
| 2852 #ifdef ASSERT | |
| 2853 if (code_offset() - offset != NativeInstruction::nop_instruction_size) { | |
| 2854 op->delay_op()->print(); | |
| 2855 } | |
| 2856 assert(code_offset() - offset == NativeInstruction::nop_instruction_size, | |
| 2857 "only one instruction can go in a delay slot"); | |
| 2858 #endif | |
| 2859 | |
| 2860 // we may also be emitting the call info for the instruction | |
| 2861 // which we are the delay slot of. | |
| 2862 CodeEmitInfo * call_info = op->call_info(); | |
| 2863 if (call_info) { | |
| 2864 add_call_info(code_offset(), call_info); | |
| 2865 } | |
| 2866 | |
| 2867 if (VerifyStackAtCalls) { | |
| 2868 _masm->sub(FP, SP, O7); | |
| 2869 _masm->cmp(O7, initial_frame_size_in_bytes()); | |
| 2870 _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 ); | |
| 2871 } | |
| 2872 } | |
| 2873 | |
| 2874 | |
| 2875 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { | |
| 2876 assert(left->is_register(), "can only handle registers"); | |
| 2877 | |
| 2878 if (left->is_single_cpu()) { | |
| 2879 __ neg(left->as_register(), dest->as_register()); | |
| 2880 } else if (left->is_single_fpu()) { | |
| 2881 __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg()); | |
| 2882 } else if (left->is_double_fpu()) { | |
| 2883 __ fneg(FloatRegisterImpl::D, left->as_double_reg(), dest->as_double_reg()); | |
| 2884 } else { | |
| 2885 assert (left->is_double_cpu(), "Must be a long"); | |
| 2886 Register Rlow = left->as_register_lo(); | |
| 2887 Register Rhi = left->as_register_hi(); | |
| 2888 #ifdef _LP64 | |
| 2889 __ sub(G0, Rlow, dest->as_register_lo()); | |
| 2890 #else | |
| 2891 __ subcc(G0, Rlow, dest->as_register_lo()); | |
| 2892 __ subc (G0, Rhi, dest->as_register_hi()); | |
| 2893 #endif | |
| 2894 } | |
| 2895 } | |
| 2896 | |
| 2897 | |
| 2898 void LIR_Assembler::fxch(int i) { | |
| 2899 Unimplemented(); | |
| 2900 } | |
| 2901 | |
| 2902 void LIR_Assembler::fld(int i) { | |
| 2903 Unimplemented(); | |
| 2904 } | |
| 2905 | |
| 2906 void LIR_Assembler::ffree(int i) { | |
| 2907 Unimplemented(); | |
| 2908 } | |
| 2909 | |
| 2910 void LIR_Assembler::rt_call(LIR_Opr result, address dest, | |
| 2911 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { | |
| 2912 | |
| 2913 // if tmp is invalid, then the function being called doesn't destroy the thread | |
| 2914 if (tmp->is_valid()) { | |
| 2915 __ save_thread(tmp->as_register()); | |
| 2916 } | |
| 2917 __ call(dest, relocInfo::runtime_call_type); | |
| 2918 __ delayed()->nop(); | |
| 2919 if (info != NULL) { | |
| 2920 add_call_info_here(info); | |
| 2921 } | |
| 2922 if (tmp->is_valid()) { | |
| 2923 __ restore_thread(tmp->as_register()); | |
| 2924 } | |
| 2925 | |
| 2926 #ifdef ASSERT | |
| 2927 __ verify_thread(); | |
| 2928 #endif // ASSERT | |
| 2929 } | |
| 2930 | |
| 2931 | |
| 2932 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { | |
| 2933 #ifdef _LP64 | |
| 2934 ShouldNotReachHere(); | |
| 2935 #endif | |
| 2936 | |
| 2937 NEEDS_CLEANUP; | |
| 2938 if (type == T_LONG) { | |
| 2939 LIR_Address* mem_addr = dest->is_address() ? dest->as_address_ptr() : src->as_address_ptr(); | |
| 2940 | |
| 2941 // (extended to allow indexed as well as constant displaced for JSR-166) | |
| 2942 Register idx = noreg; // contains either constant offset or index | |
| 2943 | |
| 2944 int disp = mem_addr->disp(); | |
| 2945 if (mem_addr->index() == LIR_OprFact::illegalOpr) { | |
| 2946 if (!Assembler::is_simm13(disp)) { | |
| 2947 idx = O7; | |
| 2948 __ set(disp, idx); | |
| 2949 } | |
| 2950 } else { | |
| 2951 assert(disp == 0, "not both indexed and disp"); | |
| 2952 idx = mem_addr->index()->as_register(); | |
| 2953 } | |
| 2954 | |
| 2955 int null_check_offset = -1; | |
| 2956 | |
| 2957 Register base = mem_addr->base()->as_register(); | |
| 2958 if (src->is_register() && dest->is_address()) { | |
| 2959 // G4 is high half, G5 is low half | |
| 2960 if (VM_Version::v9_instructions_work()) { | |
| 2961 // clear the top bits of G5, and scale up G4 | |
| 2962 __ srl (src->as_register_lo(), 0, G5); | |
| 2963 __ sllx(src->as_register_hi(), 32, G4); | |
| 2964 // combine the two halves into the 64 bits of G4 | |
| 2965 __ or3(G4, G5, G4); | |
| 2966 null_check_offset = __ offset(); | |
| 2967 if (idx == noreg) { | |
| 2968 __ stx(G4, base, disp); | |
| 2969 } else { | |
| 2970 __ stx(G4, base, idx); | |
| 2971 } | |
| 2972 } else { | |
| 2973 __ mov (src->as_register_hi(), G4); | |
| 2974 __ mov (src->as_register_lo(), G5); | |
| 2975 null_check_offset = __ offset(); | |
| 2976 if (idx == noreg) { | |
| 2977 __ std(G4, base, disp); | |
| 2978 } else { | |
| 2979 __ std(G4, base, idx); | |
| 2980 } | |
| 2981 } | |
| 2982 } else if (src->is_address() && dest->is_register()) { | |
| 2983 null_check_offset = __ offset(); | |
| 2984 if (VM_Version::v9_instructions_work()) { | |
| 2985 if (idx == noreg) { | |
| 2986 __ ldx(base, disp, G5); | |
| 2987 } else { | |
| 2988 __ ldx(base, idx, G5); | |
| 2989 } | |
| 2990 __ srax(G5, 32, dest->as_register_hi()); // fetch the high half into hi | |
| 2991 __ mov (G5, dest->as_register_lo()); // copy low half into lo | |
| 2992 } else { | |
| 2993 if (idx == noreg) { | |
| 2994 __ ldd(base, disp, G4); | |
| 2995 } else { | |
| 2996 __ ldd(base, idx, G4); | |
| 2997 } | |
| 2998 // G4 is high half, G5 is low half | |
| 2999 __ mov (G4, dest->as_register_hi()); | |
| 3000 __ mov (G5, dest->as_register_lo()); | |
| 3001 } | |
| 3002 } else { | |
| 3003 Unimplemented(); | |
| 3004 } | |
| 3005 if (info != NULL) { | |
| 3006 add_debug_info_for_null_check(null_check_offset, info); | |
| 3007 } | |
| 3008 | |
| 3009 } else { | |
| 3010 // use normal move for all other volatiles since they don't need | |
| 3011 // special handling to remain atomic. | |
| 3012 move_op(src, dest, type, lir_patch_none, info, false, false); | |
| 3013 } | |
| 3014 } | |
| 3015 | |
| 3016 void LIR_Assembler::membar() { | |
| 3017 // only StoreLoad membars are ever explicitly needed on sparcs in TSO mode | |
| 3018 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); | |
| 3019 } | |
| 3020 | |
| 3021 void LIR_Assembler::membar_acquire() { | |
| 3022 // no-op on TSO | |
| 3023 } | |
| 3024 | |
| 3025 void LIR_Assembler::membar_release() { | |
| 3026 // no-op on TSO | |
| 3027 } | |
| 3028 | |
| 3029 // Macro to Pack two sequential registers containing 32 bit values | |
| 3030 // into a single 64 bit register. | |
| 3031 // rs and rs->successor() are packed into rd | |
| 3032 // rd and rs may be the same register. | |
| 3033 // Note: rs and rs->successor() are destroyed. | |
| 3034 void LIR_Assembler::pack64( Register rs, Register rd ) { | |
| 3035 __ sllx(rs, 32, rs); | |
| 3036 __ srl(rs->successor(), 0, rs->successor()); | |
| 3037 __ or3(rs, rs->successor(), rd); | |
| 3038 } | |
| 3039 | |
| 3040 // Macro to unpack a 64 bit value in a register into | |
| 3041 // two sequential registers. | |
| 3042 // rd is unpacked into rd and rd->successor() | |
| 3043 void LIR_Assembler::unpack64( Register rd ) { | |
| 3044 __ mov(rd, rd->successor()); | |
| 3045 __ srax(rd, 32, rd); | |
| 3046 __ sra(rd->successor(), 0, rd->successor()); | |
| 3047 } | |
| 3048 | |
| 3049 | |
| 3050 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) { | |
| 3051 LIR_Address* addr = addr_opr->as_address_ptr(); | |
| 3052 assert(addr->index()->is_illegal() && addr->scale() == LIR_Address::times_1 && Assembler::is_simm13(addr->disp()), "can't handle complex addresses yet"); | |
| 3053 __ add(addr->base()->as_register(), addr->disp(), dest->as_register()); | |
| 3054 } | |
| 3055 | |
| 3056 | |
| 3057 void LIR_Assembler::get_thread(LIR_Opr result_reg) { | |
| 3058 assert(result_reg->is_register(), "check"); | |
| 3059 __ mov(G2_thread, result_reg->as_register()); | |
| 3060 } | |
| 3061 | |
| 3062 | |
| 3063 void LIR_Assembler::peephole(LIR_List* lir) { | |
| 3064 LIR_OpList* inst = lir->instructions_list(); | |
| 3065 for (int i = 0; i < inst->length(); i++) { | |
| 3066 LIR_Op* op = inst->at(i); | |
| 3067 switch (op->code()) { | |
| 3068 case lir_cond_float_branch: | |
| 3069 case lir_branch: { | |
| 3070 LIR_OpBranch* branch = op->as_OpBranch(); | |
| 3071 assert(branch->info() == NULL, "shouldn't be state on branches anymore"); | |
| 3072 LIR_Op* delay_op = NULL; | |
| 3073 // we'd like to be able to pull following instructions into | |
| 3074 // this slot but we don't know enough to do it safely yet so | |
| 3075 // only optimize block to block control flow. | |
| 3076 if (LIRFillDelaySlots && branch->block()) { | |
| 3077 LIR_Op* prev = inst->at(i - 1); | |
| 3078 if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) { | |
| 3079 // swap previous instruction into delay slot | |
| 3080 inst->at_put(i - 1, op); | |
| 3081 inst->at_put(i, new LIR_OpDelay(prev, op->info())); | |
| 3082 #ifndef PRODUCT | |
| 3083 if (LIRTracePeephole) { | |
| 3084 tty->print_cr("delayed"); | |
| 3085 inst->at(i - 1)->print(); | |
| 3086 inst->at(i)->print(); | |
| 3087 } | |
| 3088 #endif | |
| 3089 continue; | |
| 3090 } | |
| 3091 } | |
| 3092 | |
| 3093 if (!delay_op) { | |
| 3094 delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL); | |
| 3095 } | |
| 3096 inst->insert_before(i + 1, delay_op); | |
| 3097 break; | |
| 3098 } | |
| 3099 case lir_static_call: | |
| 3100 case lir_virtual_call: | |
| 3101 case lir_icvirtual_call: | |
| 3102 case lir_optvirtual_call: { | |
| 3103 LIR_Op* delay_op = NULL; | |
| 3104 LIR_Op* prev = inst->at(i - 1); | |
| 3105 if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL && | |
| 3106 (op->code() != lir_virtual_call || | |
| 3107 !prev->result_opr()->is_single_cpu() || | |
| 3108 prev->result_opr()->as_register() != O0) && | |
| 3109 LIR_Assembler::is_single_instruction(prev)) { | |
| 3110 // Only moves without info can be put into the delay slot. | |
| 3111 // Also don't allow the setup of the receiver in the delay | |
| 3112 // slot for vtable calls. | |
| 3113 inst->at_put(i - 1, op); | |
| 3114 inst->at_put(i, new LIR_OpDelay(prev, op->info())); | |
| 3115 #ifndef PRODUCT | |
| 3116 if (LIRTracePeephole) { | |
| 3117 tty->print_cr("delayed"); | |
| 3118 inst->at(i - 1)->print(); | |
| 3119 inst->at(i)->print(); | |
| 3120 } | |
| 3121 #endif | |
| 3122 continue; | |
| 3123 } | |
| 3124 | |
| 3125 if (!delay_op) { | |
| 3126 delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info()); | |
| 3127 inst->insert_before(i + 1, delay_op); | |
| 3128 } | |
| 3129 break; | |
| 3130 } | |
| 3131 } | |
| 3132 } | |
| 3133 } | |
| 3134 | |
| 3135 | |
| 3136 | |
| 3137 | |
| 3138 #undef __ |