Mercurial > hg > graal-compiler
annotate src/cpu/x86/vm/assembler_x86.hpp @ 3451:38fa55e5e792
7055355: JSR 292: crash while throwing WrongMethodTypeException
Reviewed-by: jrose, twisti, bdelsart
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date | Thu, 16 Jun 2011 13:46:55 -0700 |
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0 | 1 /* |
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2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #ifndef CPU_X86_VM_ASSEMBLER_X86_HPP |
26 #define CPU_X86_VM_ASSEMBLER_X86_HPP | |
27 | |
0 | 28 class BiasedLockingCounters; |
29 | |
30 // Contains all the definitions needed for x86 assembly code generation. | |
31 | |
32 // Calling convention | |
33 class Argument VALUE_OBJ_CLASS_SPEC { | |
34 public: | |
35 enum { | |
36 #ifdef _LP64 | |
37 #ifdef _WIN64 | |
38 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...) | |
39 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... ) | |
40 #else | |
41 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...) | |
42 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... ) | |
43 #endif // _WIN64 | |
44 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ... | |
45 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ... | |
46 #else | |
47 n_register_parameters = 0 // 0 registers used to pass arguments | |
48 #endif // _LP64 | |
49 }; | |
50 }; | |
51 | |
52 | |
53 #ifdef _LP64 | |
54 // Symbolically name the register arguments used by the c calling convention. | |
55 // Windows is different from linux/solaris. So much for standards... | |
56 | |
57 #ifdef _WIN64 | |
58 | |
59 REGISTER_DECLARATION(Register, c_rarg0, rcx); | |
60 REGISTER_DECLARATION(Register, c_rarg1, rdx); | |
61 REGISTER_DECLARATION(Register, c_rarg2, r8); | |
62 REGISTER_DECLARATION(Register, c_rarg3, r9); | |
63 | |
304 | 64 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); |
65 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); | |
66 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); | |
67 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); | |
0 | 68 |
69 #else | |
70 | |
71 REGISTER_DECLARATION(Register, c_rarg0, rdi); | |
72 REGISTER_DECLARATION(Register, c_rarg1, rsi); | |
73 REGISTER_DECLARATION(Register, c_rarg2, rdx); | |
74 REGISTER_DECLARATION(Register, c_rarg3, rcx); | |
75 REGISTER_DECLARATION(Register, c_rarg4, r8); | |
76 REGISTER_DECLARATION(Register, c_rarg5, r9); | |
77 | |
304 | 78 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); |
79 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); | |
80 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); | |
81 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); | |
82 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4); | |
83 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5); | |
84 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6); | |
85 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7); | |
0 | 86 |
87 #endif // _WIN64 | |
88 | |
89 // Symbolically name the register arguments used by the Java calling convention. | |
90 // We have control over the convention for java so we can do what we please. | |
91 // What pleases us is to offset the java calling convention so that when | |
92 // we call a suitable jni method the arguments are lined up and we don't | |
93 // have to do little shuffling. A suitable jni method is non-static and a | |
94 // small number of arguments (two fewer args on windows) | |
95 // | |
96 // |-------------------------------------------------------| | |
97 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 | | |
98 // |-------------------------------------------------------| | |
99 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg) | |
100 // | rdi rsi rdx rcx r8 r9 | solaris/linux | |
101 // |-------------------------------------------------------| | |
102 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 | | |
103 // |-------------------------------------------------------| | |
104 | |
105 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1); | |
106 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2); | |
107 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3); | |
108 // Windows runs out of register args here | |
109 #ifdef _WIN64 | |
110 REGISTER_DECLARATION(Register, j_rarg3, rdi); | |
111 REGISTER_DECLARATION(Register, j_rarg4, rsi); | |
112 #else | |
113 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4); | |
114 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5); | |
115 #endif /* _WIN64 */ | |
116 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0); | |
117 | |
304 | 118 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0); |
119 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1); | |
120 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2); | |
121 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3); | |
122 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4); | |
123 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5); | |
124 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6); | |
125 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7); | |
0 | 126 |
127 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile | |
128 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile | |
129 | |
304 | 130 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved |
0 | 131 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved |
132 | |
304 | 133 #else |
134 // rscratch1 will apear in 32bit code that is dead but of course must compile | |
135 // Using noreg ensures if the dead code is incorrectly live and executed it | |
136 // will cause an assertion failure | |
137 #define rscratch1 noreg | |
2002 | 138 #define rscratch2 noreg |
304 | 139 |
0 | 140 #endif // _LP64 |
141 | |
1564 | 142 // JSR 292 fixed register usages: |
143 REGISTER_DECLARATION(Register, rbp_mh_SP_save, rbp); | |
144 | |
0 | 145 // Address is an abstraction used to represent a memory location |
146 // using any of the amd64 addressing modes with one object. | |
147 // | |
148 // Note: A register location is represented via a Register, not | |
149 // via an address for efficiency & simplicity reasons. | |
150 | |
151 class ArrayAddress; | |
152 | |
153 class Address VALUE_OBJ_CLASS_SPEC { | |
154 public: | |
155 enum ScaleFactor { | |
156 no_scale = -1, | |
157 times_1 = 0, | |
158 times_2 = 1, | |
159 times_4 = 2, | |
304 | 160 times_8 = 3, |
161 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4) | |
0 | 162 }; |
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163 static ScaleFactor times(int size) { |
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164 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size"); |
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165 if (size == 8) return times_8; |
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166 if (size == 4) return times_4; |
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167 if (size == 2) return times_2; |
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168 return times_1; |
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169 } |
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170 static int scale_size(ScaleFactor scale) { |
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171 assert(scale != no_scale, ""); |
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172 assert(((1 << (int)times_1) == 1 && |
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173 (1 << (int)times_2) == 2 && |
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174 (1 << (int)times_4) == 4 && |
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175 (1 << (int)times_8) == 8), ""); |
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176 return (1 << (int)scale); |
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177 } |
0 | 178 |
179 private: | |
180 Register _base; | |
181 Register _index; | |
182 ScaleFactor _scale; | |
183 int _disp; | |
184 RelocationHolder _rspec; | |
185 | |
304 | 186 // Easily misused constructors make them private |
187 // %%% can we make these go away? | |
188 NOT_LP64(Address(address loc, RelocationHolder spec);) | |
189 Address(int disp, address loc, relocInfo::relocType rtype); | |
190 Address(int disp, address loc, RelocationHolder spec); | |
0 | 191 |
192 public: | |
304 | 193 |
194 int disp() { return _disp; } | |
0 | 195 // creation |
196 Address() | |
197 : _base(noreg), | |
198 _index(noreg), | |
199 _scale(no_scale), | |
200 _disp(0) { | |
201 } | |
202 | |
203 // No default displacement otherwise Register can be implicitly | |
204 // converted to 0(Register) which is quite a different animal. | |
205 | |
206 Address(Register base, int disp) | |
207 : _base(base), | |
208 _index(noreg), | |
209 _scale(no_scale), | |
210 _disp(disp) { | |
211 } | |
212 | |
213 Address(Register base, Register index, ScaleFactor scale, int disp = 0) | |
214 : _base (base), | |
215 _index(index), | |
216 _scale(scale), | |
217 _disp (disp) { | |
218 assert(!index->is_valid() == (scale == Address::no_scale), | |
219 "inconsistent address"); | |
220 } | |
221 | |
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222 Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0) |
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223 : _base (base), |
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224 _index(index.register_or_noreg()), |
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225 _scale(scale), |
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226 _disp (disp + (index.constant_or_zero() * scale_size(scale))) { |
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227 if (!index.is_register()) scale = Address::no_scale; |
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228 assert(!_index->is_valid() == (scale == Address::no_scale), |
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229 "inconsistent address"); |
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230 } |
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231 |
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232 Address plus_disp(int disp) const { |
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233 Address a = (*this); |
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234 a._disp += disp; |
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235 return a; |
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236 } |
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237 Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const { |
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238 Address a = (*this); |
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239 a._disp += disp.constant_or_zero() * scale_size(scale); |
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240 if (disp.is_register()) { |
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241 assert(!a.index()->is_valid(), "competing indexes"); |
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242 a._index = disp.as_register(); |
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243 a._scale = scale; |
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244 } |
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245 return a; |
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246 } |
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247 bool is_same_address(Address a) const { |
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248 // disregard _rspec |
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249 return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale; |
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250 } |
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251 |
0 | 252 // The following two overloads are used in connection with the |
253 // ByteSize type (see sizes.hpp). They simplify the use of | |
254 // ByteSize'd arguments in assembly code. Note that their equivalent | |
255 // for the optimized build are the member functions with int disp | |
256 // argument since ByteSize is mapped to an int type in that case. | |
257 // | |
258 // Note: DO NOT introduce similar overloaded functions for WordSize | |
259 // arguments as in the optimized mode, both ByteSize and WordSize | |
260 // are mapped to the same type and thus the compiler cannot make a | |
261 // distinction anymore (=> compiler errors). | |
262 | |
263 #ifdef ASSERT | |
264 Address(Register base, ByteSize disp) | |
265 : _base(base), | |
266 _index(noreg), | |
267 _scale(no_scale), | |
268 _disp(in_bytes(disp)) { | |
269 } | |
270 | |
271 Address(Register base, Register index, ScaleFactor scale, ByteSize disp) | |
272 : _base(base), | |
273 _index(index), | |
274 _scale(scale), | |
275 _disp(in_bytes(disp)) { | |
276 assert(!index->is_valid() == (scale == Address::no_scale), | |
277 "inconsistent address"); | |
278 } | |
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279 |
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280 Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp) |
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281 : _base (base), |
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282 _index(index.register_or_noreg()), |
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283 _scale(scale), |
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284 _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) { |
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285 if (!index.is_register()) scale = Address::no_scale; |
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286 assert(!_index->is_valid() == (scale == Address::no_scale), |
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287 "inconsistent address"); |
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288 } |
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289 |
0 | 290 #endif // ASSERT |
291 | |
292 // accessors | |
342
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293 bool uses(Register reg) const { return _base == reg || _index == reg; } |
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294 Register base() const { return _base; } |
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295 Register index() const { return _index; } |
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296 ScaleFactor scale() const { return _scale; } |
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297 int disp() const { return _disp; } |
0 | 298 |
299 // Convert the raw encoding form into the form expected by the constructor for | |
300 // Address. An index of 4 (rsp) corresponds to having no index, so convert | |
301 // that to noreg for the Address constructor. | |
624 | 302 static Address make_raw(int base, int index, int scale, int disp, bool disp_is_oop); |
0 | 303 |
304 static Address make_array(ArrayAddress); | |
305 | |
306 private: | |
307 bool base_needs_rex() const { | |
308 return _base != noreg && _base->encoding() >= 8; | |
309 } | |
310 | |
311 bool index_needs_rex() const { | |
312 return _index != noreg &&_index->encoding() >= 8; | |
313 } | |
314 | |
315 relocInfo::relocType reloc() const { return _rspec.type(); } | |
316 | |
317 friend class Assembler; | |
318 friend class MacroAssembler; | |
319 friend class LIR_Assembler; // base/index/scale/disp | |
320 }; | |
321 | |
322 // | |
323 // AddressLiteral has been split out from Address because operands of this type | |
324 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out | |
325 // the few instructions that need to deal with address literals are unique and the | |
326 // MacroAssembler does not have to implement every instruction in the Assembler | |
327 // in order to search for address literals that may need special handling depending | |
328 // on the instruction and the platform. As small step on the way to merging i486/amd64 | |
329 // directories. | |
330 // | |
331 class AddressLiteral VALUE_OBJ_CLASS_SPEC { | |
332 friend class ArrayAddress; | |
333 RelocationHolder _rspec; | |
334 // Typically we use AddressLiterals we want to use their rval | |
335 // However in some situations we want the lval (effect address) of the item. | |
336 // We provide a special factory for making those lvals. | |
337 bool _is_lval; | |
338 | |
339 // If the target is far we'll need to load the ea of this to | |
340 // a register to reach it. Otherwise if near we can do rip | |
341 // relative addressing. | |
342 | |
343 address _target; | |
344 | |
345 protected: | |
346 // creation | |
347 AddressLiteral() | |
348 : _is_lval(false), | |
349 _target(NULL) | |
350 {} | |
351 | |
352 public: | |
353 | |
354 | |
355 AddressLiteral(address target, relocInfo::relocType rtype); | |
356 | |
357 AddressLiteral(address target, RelocationHolder const& rspec) | |
358 : _rspec(rspec), | |
359 _is_lval(false), | |
360 _target(target) | |
361 {} | |
362 | |
363 AddressLiteral addr() { | |
364 AddressLiteral ret = *this; | |
365 ret._is_lval = true; | |
366 return ret; | |
367 } | |
368 | |
369 | |
370 private: | |
371 | |
372 address target() { return _target; } | |
373 bool is_lval() { return _is_lval; } | |
374 | |
375 relocInfo::relocType reloc() const { return _rspec.type(); } | |
376 const RelocationHolder& rspec() const { return _rspec; } | |
377 | |
378 friend class Assembler; | |
379 friend class MacroAssembler; | |
380 friend class Address; | |
381 friend class LIR_Assembler; | |
382 }; | |
383 | |
384 // Convience classes | |
385 class RuntimeAddress: public AddressLiteral { | |
386 | |
387 public: | |
388 | |
389 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {} | |
390 | |
391 }; | |
392 | |
393 class OopAddress: public AddressLiteral { | |
394 | |
395 public: | |
396 | |
397 OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){} | |
398 | |
399 }; | |
400 | |
401 class ExternalAddress: public AddressLiteral { | |
2455
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402 private: |
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403 static relocInfo::relocType reloc_for_target(address target) { |
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404 // Sometimes ExternalAddress is used for values which aren't |
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405 // exactly addresses, like the card table base. |
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406 // external_word_type can't be used for values in the first page |
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407 // so just skip the reloc in that case. |
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408 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none; |
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409 } |
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410 |
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411 public: |
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412 |
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413 ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {} |
0 | 414 |
415 }; | |
416 | |
417 class InternalAddress: public AddressLiteral { | |
418 | |
419 public: | |
420 | |
421 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {} | |
422 | |
423 }; | |
424 | |
425 // x86 can do array addressing as a single operation since disp can be an absolute | |
426 // address amd64 can't. We create a class that expresses the concept but does extra | |
427 // magic on amd64 to get the final result | |
428 | |
429 class ArrayAddress VALUE_OBJ_CLASS_SPEC { | |
430 private: | |
431 | |
432 AddressLiteral _base; | |
433 Address _index; | |
434 | |
435 public: | |
436 | |
437 ArrayAddress() {}; | |
438 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {}; | |
439 AddressLiteral base() { return _base; } | |
440 Address index() { return _index; } | |
441 | |
442 }; | |
443 | |
304 | 444 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize); |
0 | 445 |
446 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction | |
447 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write | |
448 // is what you get. The Assembler is generating code into a CodeBuffer. | |
449 | |
450 class Assembler : public AbstractAssembler { | |
451 friend class AbstractAssembler; // for the non-virtual hack | |
452 friend class LIR_Assembler; // as_Address() | |
304 | 453 friend class StubGenerator; |
0 | 454 |
455 public: | |
456 enum Condition { // The x86 condition codes used for conditional jumps/moves. | |
457 zero = 0x4, | |
458 notZero = 0x5, | |
459 equal = 0x4, | |
460 notEqual = 0x5, | |
461 less = 0xc, | |
462 lessEqual = 0xe, | |
463 greater = 0xf, | |
464 greaterEqual = 0xd, | |
465 below = 0x2, | |
466 belowEqual = 0x6, | |
467 above = 0x7, | |
468 aboveEqual = 0x3, | |
469 overflow = 0x0, | |
470 noOverflow = 0x1, | |
471 carrySet = 0x2, | |
472 carryClear = 0x3, | |
473 negative = 0x8, | |
474 positive = 0x9, | |
475 parity = 0xa, | |
476 noParity = 0xb | |
477 }; | |
478 | |
479 enum Prefix { | |
480 // segment overrides | |
481 CS_segment = 0x2e, | |
482 SS_segment = 0x36, | |
483 DS_segment = 0x3e, | |
484 ES_segment = 0x26, | |
485 FS_segment = 0x64, | |
486 GS_segment = 0x65, | |
487 | |
488 REX = 0x40, | |
489 | |
490 REX_B = 0x41, | |
491 REX_X = 0x42, | |
492 REX_XB = 0x43, | |
493 REX_R = 0x44, | |
494 REX_RB = 0x45, | |
495 REX_RX = 0x46, | |
496 REX_RXB = 0x47, | |
497 | |
498 REX_W = 0x48, | |
499 | |
500 REX_WB = 0x49, | |
501 REX_WX = 0x4A, | |
502 REX_WXB = 0x4B, | |
503 REX_WR = 0x4C, | |
504 REX_WRB = 0x4D, | |
505 REX_WRX = 0x4E, | |
506 REX_WRXB = 0x4F | |
507 }; | |
508 | |
509 enum WhichOperand { | |
510 // input to locate_operand, and format code for relocations | |
304 | 511 imm_operand = 0, // embedded 32-bit|64-bit immediate operand |
0 | 512 disp32_operand = 1, // embedded 32-bit displacement or address |
513 call32_operand = 2, // embedded 32-bit self-relative displacement | |
304 | 514 #ifndef _LP64 |
0 | 515 _WhichOperand_limit = 3 |
304 | 516 #else |
517 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop | |
518 _WhichOperand_limit = 4 | |
519 #endif | |
0 | 520 }; |
521 | |
304 | 522 |
523 | |
524 // NOTE: The general philopsophy of the declarations here is that 64bit versions | |
525 // of instructions are freely declared without the need for wrapping them an ifdef. | |
526 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.) | |
527 // In the .cpp file the implementations are wrapped so that they are dropped out | |
528 // of the resulting jvm. This is done mostly to keep the footprint of KERNEL | |
529 // to the size it was prior to merging up the 32bit and 64bit assemblers. | |
530 // | |
531 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction | |
532 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down. | |
533 | |
534 private: | |
535 | |
536 | |
537 // 64bit prefixes | |
538 int prefix_and_encode(int reg_enc, bool byteinst = false); | |
539 int prefixq_and_encode(int reg_enc); | |
540 | |
541 int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false); | |
542 int prefixq_and_encode(int dst_enc, int src_enc); | |
543 | |
544 void prefix(Register reg); | |
545 void prefix(Address adr); | |
546 void prefixq(Address adr); | |
547 | |
548 void prefix(Address adr, Register reg, bool byteinst = false); | |
549 void prefixq(Address adr, Register reg); | |
550 | |
551 void prefix(Address adr, XMMRegister reg); | |
552 | |
553 void prefetch_prefix(Address src); | |
554 | |
555 // Helper functions for groups of instructions | |
556 void emit_arith_b(int op1, int op2, Register dst, int imm8); | |
557 | |
558 void emit_arith(int op1, int op2, Register dst, int32_t imm32); | |
559 // only 32bit?? | |
560 void emit_arith(int op1, int op2, Register dst, jobject obj); | |
561 void emit_arith(int op1, int op2, Register dst, Register src); | |
562 | |
563 void emit_operand(Register reg, | |
564 Register base, Register index, Address::ScaleFactor scale, | |
565 int disp, | |
566 RelocationHolder const& rspec, | |
567 int rip_relative_correction = 0); | |
568 | |
569 void emit_operand(Register reg, Address adr, int rip_relative_correction = 0); | |
570 | |
571 // operands that only take the original 32bit registers | |
572 void emit_operand32(Register reg, Address adr); | |
573 | |
574 void emit_operand(XMMRegister reg, | |
575 Register base, Register index, Address::ScaleFactor scale, | |
576 int disp, | |
577 RelocationHolder const& rspec); | |
578 | |
579 void emit_operand(XMMRegister reg, Address adr); | |
580 | |
581 void emit_operand(MMXRegister reg, Address adr); | |
582 | |
583 // workaround gcc (3.2.1-7) bug | |
584 void emit_operand(Address adr, MMXRegister reg); | |
585 | |
586 | |
587 // Immediate-to-memory forms | |
588 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32); | |
589 | |
590 void emit_farith(int b1, int b2, int i); | |
591 | |
592 | |
593 protected: | |
594 #ifdef ASSERT | |
595 void check_relocation(RelocationHolder const& rspec, int format); | |
596 #endif | |
597 | |
598 inline void emit_long64(jlong x); | |
599 | |
600 void emit_data(jint data, relocInfo::relocType rtype, int format); | |
601 void emit_data(jint data, RelocationHolder const& rspec, int format); | |
602 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0); | |
603 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0); | |
604 | |
605 bool reachable(AddressLiteral adr) NOT_LP64({ return true;}); | |
606 | |
607 // These are all easily abused and hence protected | |
608 | |
609 // 32BIT ONLY SECTION | |
610 #ifndef _LP64 | |
611 // Make these disappear in 64bit mode since they would never be correct | |
612 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY | |
613 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY | |
614 | |
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615 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
304 | 616 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY |
617 | |
618 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY | |
619 #else | |
620 // 64BIT ONLY SECTION | |
621 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY | |
642
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622 |
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623 void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec); |
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624 void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec); |
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625 |
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626 void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec); |
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627 void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec); |
304 | 628 #endif // _LP64 |
629 | |
630 // These are unique in that we are ensured by the caller that the 32bit | |
631 // relative in these instructions will always be able to reach the potentially | |
632 // 64bit address described by entry. Since they can take a 64bit address they | |
633 // don't have the 32 suffix like the other instructions in this class. | |
634 | |
635 void call_literal(address entry, RelocationHolder const& rspec); | |
636 void jmp_literal(address entry, RelocationHolder const& rspec); | |
637 | |
638 // Avoid using directly section | |
639 // Instructions in this section are actually usable by anyone without danger | |
640 // of failure but have performance issues that are addressed my enhanced | |
641 // instructions which will do the proper thing base on the particular cpu. | |
642 // We protect them because we don't trust you... | |
643 | |
644 // Don't use next inc() and dec() methods directly. INC & DEC instructions | |
645 // could cause a partial flag stall since they don't set CF flag. | |
646 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods | |
647 // which call inc() & dec() or add() & sub() in accordance with | |
648 // the product flag UseIncDec value. | |
649 | |
650 void decl(Register dst); | |
651 void decl(Address dst); | |
652 void decq(Register dst); | |
653 void decq(Address dst); | |
654 | |
655 void incl(Register dst); | |
656 void incl(Address dst); | |
657 void incq(Register dst); | |
658 void incq(Address dst); | |
659 | |
660 // New cpus require use of movsd and movss to avoid partial register stall | |
661 // when loading from memory. But for old Opteron use movlpd instead of movsd. | |
662 // The selection is done in MacroAssembler::movdbl() and movflt(). | |
663 | |
664 // Move Scalar Single-Precision Floating-Point Values | |
665 void movss(XMMRegister dst, Address src); | |
666 void movss(XMMRegister dst, XMMRegister src); | |
667 void movss(Address dst, XMMRegister src); | |
668 | |
669 // Move Scalar Double-Precision Floating-Point Values | |
670 void movsd(XMMRegister dst, Address src); | |
671 void movsd(XMMRegister dst, XMMRegister src); | |
672 void movsd(Address dst, XMMRegister src); | |
673 void movlpd(XMMRegister dst, Address src); | |
674 | |
675 // New cpus require use of movaps and movapd to avoid partial register stall | |
676 // when moving between registers. | |
677 void movaps(XMMRegister dst, XMMRegister src); | |
678 void movapd(XMMRegister dst, XMMRegister src); | |
679 | |
680 // End avoid using directly | |
681 | |
682 | |
683 // Instruction prefixes | |
684 void prefix(Prefix p); | |
685 | |
0 | 686 public: |
687 | |
688 // Creation | |
689 Assembler(CodeBuffer* code) : AbstractAssembler(code) {} | |
690 | |
691 // Decoding | |
692 static address locate_operand(address inst, WhichOperand which); | |
693 static address locate_next_instruction(address inst); | |
694 | |
304 | 695 // Utilities |
696 | |
697 #ifdef _LP64 | |
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698 static bool is_simm(int64_t x, int nbits) { return -(CONST64(1) << (nbits-1)) <= x && |
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699 x < (CONST64(1) << (nbits-1)); } |
304 | 700 static bool is_simm32(int64_t x) { return x == (int64_t)(int32_t)x; } |
701 #else | |
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702 static bool is_simm(int32_t x, int nbits) { return -(1 << (nbits-1)) <= x && |
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703 x < (1 << (nbits-1)); } |
304 | 704 static bool is_simm32(int32_t x) { return true; } |
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705 #endif // _LP64 |
304 | 706 |
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707 static bool is_polling_page_far() NOT_LP64({ return false;}); |
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708 |
304 | 709 // Generic instructions |
710 // Does 32bit or 64bit as needed for the platform. In some sense these | |
711 // belong in macro assembler but there is no need for both varieties to exist | |
712 | |
713 void lea(Register dst, Address src); | |
714 | |
715 void mov(Register dst, Register src); | |
716 | |
717 void pusha(); | |
718 void popa(); | |
719 | |
720 void pushf(); | |
721 void popf(); | |
722 | |
723 void push(int32_t imm32); | |
724 | |
725 void push(Register src); | |
726 | |
727 void pop(Register dst); | |
728 | |
729 // These are dummies to prevent surprise implicit conversions to Register | |
730 void push(void* v); | |
731 void pop(void* v); | |
732 | |
733 // These do register sized moves/scans | |
734 void rep_mov(); | |
735 void rep_set(); | |
736 void repne_scan(); | |
737 #ifdef _LP64 | |
738 void repne_scanl(); | |
739 #endif | |
740 | |
741 // Vanilla instructions in lexical order | |
742 | |
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743 void adcl(Address dst, int32_t imm32); |
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744 void adcl(Address dst, Register src); |
304 | 745 void adcl(Register dst, int32_t imm32); |
0 | 746 void adcl(Register dst, Address src); |
747 void adcl(Register dst, Register src); | |
748 | |
304 | 749 void adcq(Register dst, int32_t imm32); |
750 void adcq(Register dst, Address src); | |
751 void adcq(Register dst, Register src); | |
752 | |
753 void addl(Address dst, int32_t imm32); | |
0 | 754 void addl(Address dst, Register src); |
304 | 755 void addl(Register dst, int32_t imm32); |
0 | 756 void addl(Register dst, Address src); |
757 void addl(Register dst, Register src); | |
758 | |
304 | 759 void addq(Address dst, int32_t imm32); |
760 void addq(Address dst, Register src); | |
761 void addq(Register dst, int32_t imm32); | |
762 void addq(Register dst, Address src); | |
763 void addq(Register dst, Register src); | |
764 | |
0 | 765 void addr_nop_4(); |
766 void addr_nop_5(); | |
767 void addr_nop_7(); | |
768 void addr_nop_8(); | |
769 | |
304 | 770 // Add Scalar Double-Precision Floating-Point Values |
771 void addsd(XMMRegister dst, Address src); | |
772 void addsd(XMMRegister dst, XMMRegister src); | |
773 | |
774 // Add Scalar Single-Precision Floating-Point Values | |
775 void addss(XMMRegister dst, Address src); | |
776 void addss(XMMRegister dst, XMMRegister src); | |
777 | |
778 void andl(Register dst, int32_t imm32); | |
779 void andl(Register dst, Address src); | |
780 void andl(Register dst, Register src); | |
781 | |
782 void andq(Register dst, int32_t imm32); | |
783 void andq(Register dst, Address src); | |
784 void andq(Register dst, Register src); | |
785 | |
786 // Bitwise Logical AND of Packed Double-Precision Floating-Point Values | |
787 void andpd(XMMRegister dst, Address src); | |
788 void andpd(XMMRegister dst, XMMRegister src); | |
789 | |
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790 void bsfl(Register dst, Register src); |
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791 void bsrl(Register dst, Register src); |
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792 |
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793 #ifdef _LP64 |
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794 void bsfq(Register dst, Register src); |
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795 void bsrq(Register dst, Register src); |
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796 #endif |
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797 |
304 | 798 void bswapl(Register reg); |
799 | |
800 void bswapq(Register reg); | |
801 | |
0 | 802 void call(Label& L, relocInfo::relocType rtype); |
803 void call(Register reg); // push pc; pc <- reg | |
804 void call(Address adr); // push pc; pc <- adr | |
805 | |
304 | 806 void cdql(); |
807 | |
808 void cdqq(); | |
809 | |
810 void cld() { emit_byte(0xfc); } | |
811 | |
812 void clflush(Address adr); | |
813 | |
814 void cmovl(Condition cc, Register dst, Register src); | |
815 void cmovl(Condition cc, Register dst, Address src); | |
816 | |
817 void cmovq(Condition cc, Register dst, Register src); | |
818 void cmovq(Condition cc, Register dst, Address src); | |
819 | |
820 | |
821 void cmpb(Address dst, int imm8); | |
822 | |
823 void cmpl(Address dst, int32_t imm32); | |
824 | |
825 void cmpl(Register dst, int32_t imm32); | |
826 void cmpl(Register dst, Register src); | |
827 void cmpl(Register dst, Address src); | |
828 | |
829 void cmpq(Address dst, int32_t imm32); | |
830 void cmpq(Address dst, Register src); | |
831 | |
832 void cmpq(Register dst, int32_t imm32); | |
833 void cmpq(Register dst, Register src); | |
834 void cmpq(Register dst, Address src); | |
835 | |
836 // these are dummies used to catch attempting to convert NULL to Register | |
837 void cmpl(Register dst, void* junk); // dummy | |
838 void cmpq(Register dst, void* junk); // dummy | |
839 | |
840 void cmpw(Address dst, int imm16); | |
841 | |
842 void cmpxchg8 (Address adr); | |
843 | |
844 void cmpxchgl(Register reg, Address adr); | |
845 | |
846 void cmpxchgq(Register reg, Address adr); | |
847 | |
848 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS | |
849 void comisd(XMMRegister dst, Address src); | |
850 | |
851 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS | |
852 void comiss(XMMRegister dst, Address src); | |
853 | |
854 // Identify processor type and features | |
855 void cpuid() { | |
856 emit_byte(0x0F); | |
857 emit_byte(0xA2); | |
858 } | |
859 | |
860 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value | |
861 void cvtsd2ss(XMMRegister dst, XMMRegister src); | |
862 | |
863 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value | |
864 void cvtsi2sdl(XMMRegister dst, Register src); | |
865 void cvtsi2sdq(XMMRegister dst, Register src); | |
866 | |
867 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value | |
868 void cvtsi2ssl(XMMRegister dst, Register src); | |
869 void cvtsi2ssq(XMMRegister dst, Register src); | |
870 | |
871 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value | |
872 void cvtdq2pd(XMMRegister dst, XMMRegister src); | |
873 | |
874 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value | |
875 void cvtdq2ps(XMMRegister dst, XMMRegister src); | |
876 | |
877 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value | |
878 void cvtss2sd(XMMRegister dst, XMMRegister src); | |
879 | |
880 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer | |
881 void cvttsd2sil(Register dst, Address src); | |
882 void cvttsd2sil(Register dst, XMMRegister src); | |
883 void cvttsd2siq(Register dst, XMMRegister src); | |
884 | |
885 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer | |
886 void cvttss2sil(Register dst, XMMRegister src); | |
887 void cvttss2siq(Register dst, XMMRegister src); | |
888 | |
889 // Divide Scalar Double-Precision Floating-Point Values | |
890 void divsd(XMMRegister dst, Address src); | |
891 void divsd(XMMRegister dst, XMMRegister src); | |
892 | |
893 // Divide Scalar Single-Precision Floating-Point Values | |
894 void divss(XMMRegister dst, Address src); | |
895 void divss(XMMRegister dst, XMMRegister src); | |
896 | |
897 void emms(); | |
898 | |
899 void fabs(); | |
900 | |
901 void fadd(int i); | |
902 | |
903 void fadd_d(Address src); | |
904 void fadd_s(Address src); | |
905 | |
906 // "Alternate" versions of x87 instructions place result down in FPU | |
907 // stack instead of on TOS | |
908 | |
909 void fadda(int i); // "alternate" fadd | |
910 void faddp(int i = 1); | |
911 | |
912 void fchs(); | |
913 | |
914 void fcom(int i); | |
915 | |
916 void fcomp(int i = 1); | |
917 void fcomp_d(Address src); | |
918 void fcomp_s(Address src); | |
919 | |
920 void fcompp(); | |
921 | |
922 void fcos(); | |
923 | |
924 void fdecstp(); | |
925 | |
926 void fdiv(int i); | |
927 void fdiv_d(Address src); | |
928 void fdivr_s(Address src); | |
929 void fdiva(int i); // "alternate" fdiv | |
930 void fdivp(int i = 1); | |
931 | |
932 void fdivr(int i); | |
933 void fdivr_d(Address src); | |
934 void fdiv_s(Address src); | |
935 | |
936 void fdivra(int i); // "alternate" reversed fdiv | |
937 | |
938 void fdivrp(int i = 1); | |
939 | |
940 void ffree(int i = 0); | |
941 | |
942 void fild_d(Address adr); | |
943 void fild_s(Address adr); | |
944 | |
945 void fincstp(); | |
946 | |
947 void finit(); | |
948 | |
949 void fist_s (Address adr); | |
950 void fistp_d(Address adr); | |
951 void fistp_s(Address adr); | |
952 | |
953 void fld1(); | |
954 | |
955 void fld_d(Address adr); | |
956 void fld_s(Address adr); | |
957 void fld_s(int index); | |
958 void fld_x(Address adr); // extended-precision (80-bit) format | |
959 | |
960 void fldcw(Address src); | |
961 | |
962 void fldenv(Address src); | |
963 | |
964 void fldlg2(); | |
965 | |
966 void fldln2(); | |
967 | |
968 void fldz(); | |
969 | |
970 void flog(); | |
971 void flog10(); | |
972 | |
973 void fmul(int i); | |
974 | |
975 void fmul_d(Address src); | |
976 void fmul_s(Address src); | |
977 | |
978 void fmula(int i); // "alternate" fmul | |
979 | |
980 void fmulp(int i = 1); | |
981 | |
982 void fnsave(Address dst); | |
983 | |
984 void fnstcw(Address src); | |
985 | |
986 void fnstsw_ax(); | |
987 | |
988 void fprem(); | |
989 void fprem1(); | |
990 | |
991 void frstor(Address src); | |
992 | |
993 void fsin(); | |
994 | |
995 void fsqrt(); | |
996 | |
997 void fst_d(Address adr); | |
998 void fst_s(Address adr); | |
999 | |
1000 void fstp_d(Address adr); | |
1001 void fstp_d(int index); | |
1002 void fstp_s(Address adr); | |
1003 void fstp_x(Address adr); // extended-precision (80-bit) format | |
1004 | |
1005 void fsub(int i); | |
1006 void fsub_d(Address src); | |
1007 void fsub_s(Address src); | |
1008 | |
1009 void fsuba(int i); // "alternate" fsub | |
1010 | |
1011 void fsubp(int i = 1); | |
1012 | |
1013 void fsubr(int i); | |
1014 void fsubr_d(Address src); | |
1015 void fsubr_s(Address src); | |
1016 | |
1017 void fsubra(int i); // "alternate" reversed fsub | |
1018 | |
1019 void fsubrp(int i = 1); | |
1020 | |
1021 void ftan(); | |
1022 | |
1023 void ftst(); | |
1024 | |
1025 void fucomi(int i = 1); | |
1026 void fucomip(int i = 1); | |
1027 | |
1028 void fwait(); | |
1029 | |
1030 void fxch(int i = 1); | |
1031 | |
1032 void fxrstor(Address src); | |
1033 | |
1034 void fxsave(Address dst); | |
1035 | |
1036 void fyl2x(); | |
1037 | |
1038 void hlt(); | |
1039 | |
1040 void idivl(Register src); | |
1920 | 1041 void divl(Register src); // Unsigned division |
304 | 1042 |
1043 void idivq(Register src); | |
1044 | |
1045 void imull(Register dst, Register src); | |
1046 void imull(Register dst, Register src, int value); | |
1047 | |
1048 void imulq(Register dst, Register src); | |
1049 void imulq(Register dst, Register src, int value); | |
1050 | |
0 | 1051 |
1052 // jcc is the generic conditional branch generator to run- | |
1053 // time routines, jcc is used for branches to labels. jcc | |
1054 // takes a branch opcode (cc) and a label (L) and generates | |
1055 // either a backward branch or a forward branch and links it | |
1056 // to the label fixup chain. Usage: | |
1057 // | |
1058 // Label L; // unbound label | |
1059 // jcc(cc, L); // forward branch to unbound label | |
1060 // bind(L); // bind label to the current pc | |
1061 // jcc(cc, L); // backward branch to bound label | |
1062 // bind(L); // illegal: a label may be bound only once | |
1063 // | |
1064 // Note: The same Label can be used for forward and backward branches | |
1065 // but it may be bound only once. | |
1066 | |
1067 void jcc(Condition cc, Label& L, | |
1068 relocInfo::relocType rtype = relocInfo::none); | |
1069 | |
1070 // Conditional jump to a 8-bit offset to L. | |
1071 // WARNING: be very careful using this for forward jumps. If the label is | |
1072 // not bound within an 8-bit offset of this instruction, a run-time error | |
1073 // will occur. | |
1074 void jccb(Condition cc, Label& L); | |
1075 | |
304 | 1076 void jmp(Address entry); // pc <- entry |
1077 | |
1078 // Label operations & relative jumps (PPUM Appendix D) | |
1079 void jmp(Label& L, relocInfo::relocType rtype = relocInfo::none); // unconditional jump to L | |
1080 | |
1081 void jmp(Register entry); // pc <- entry | |
1082 | |
1083 // Unconditional 8-bit offset jump to L. | |
1084 // WARNING: be very careful using this for forward jumps. If the label is | |
1085 // not bound within an 8-bit offset of this instruction, a run-time error | |
1086 // will occur. | |
1087 void jmpb(Label& L); | |
1088 | |
1089 void ldmxcsr( Address src ); | |
1090 | |
1091 void leal(Register dst, Address src); | |
1092 | |
1093 void leaq(Register dst, Address src); | |
1094 | |
1095 void lfence() { | |
1096 emit_byte(0x0F); | |
1097 emit_byte(0xAE); | |
1098 emit_byte(0xE8); | |
1099 } | |
1100 | |
1101 void lock(); | |
1102 | |
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1103 void lzcntl(Register dst, Register src); |
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1104 |
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1105 #ifdef _LP64 |
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1106 void lzcntq(Register dst, Register src); |
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1107 #endif |
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1108 |
304 | 1109 enum Membar_mask_bits { |
1110 StoreStore = 1 << 3, | |
1111 LoadStore = 1 << 2, | |
1112 StoreLoad = 1 << 1, | |
1113 LoadLoad = 1 << 0 | |
1114 }; | |
1115 | |
671
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1116 // Serializes memory and blows flags |
304 | 1117 void membar(Membar_mask_bits order_constraint) { |
671
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1118 if (os::is_MP()) { |
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1119 // We only have to handle StoreLoad |
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1120 if (order_constraint & StoreLoad) { |
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1121 // All usable chips support "locked" instructions which suffice |
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1122 // as barriers, and are much faster than the alternative of |
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1123 // using cpuid instruction. We use here a locked add [esp],0. |
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1124 // This is conveniently otherwise a no-op except for blowing |
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1125 // flags. |
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1126 // Any change to this code may need to revisit other places in |
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1127 // the code where this idiom is used, in particular the |
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1128 // orderAccess code. |
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1129 lock(); |
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1130 addl(Address(rsp, 0), 0);// Assert the lock# signal here |
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1131 } |
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1132 } |
304 | 1133 } |
1134 | |
1135 void mfence(); | |
1136 | |
1137 // Moves | |
1138 | |
1139 void mov64(Register dst, int64_t imm64); | |
1140 | |
1141 void movb(Address dst, Register src); | |
1142 void movb(Address dst, int imm8); | |
1143 void movb(Register dst, Address src); | |
1144 | |
1145 void movdl(XMMRegister dst, Register src); | |
1146 void movdl(Register dst, XMMRegister src); | |
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1147 void movdl(XMMRegister dst, Address src); |
304 | 1148 |
1149 // Move Double Quadword | |
1150 void movdq(XMMRegister dst, Register src); | |
1151 void movdq(Register dst, XMMRegister src); | |
1152 | |
1153 // Move Aligned Double Quadword | |
1154 void movdqa(Address dst, XMMRegister src); | |
1155 void movdqa(XMMRegister dst, Address src); | |
1156 void movdqa(XMMRegister dst, XMMRegister src); | |
1157 | |
405 | 1158 // Move Unaligned Double Quadword |
1159 void movdqu(Address dst, XMMRegister src); | |
1160 void movdqu(XMMRegister dst, Address src); | |
1161 void movdqu(XMMRegister dst, XMMRegister src); | |
1162 | |
304 | 1163 void movl(Register dst, int32_t imm32); |
1164 void movl(Address dst, int32_t imm32); | |
1165 void movl(Register dst, Register src); | |
1166 void movl(Register dst, Address src); | |
1167 void movl(Address dst, Register src); | |
1168 | |
1169 // These dummies prevent using movl from converting a zero (like NULL) into Register | |
1170 // by giving the compiler two choices it can't resolve | |
1171 | |
1172 void movl(Address dst, void* junk); | |
1173 void movl(Register dst, void* junk); | |
1174 | |
1175 #ifdef _LP64 | |
1176 void movq(Register dst, Register src); | |
1177 void movq(Register dst, Address src); | |
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1178 void movq(Address dst, Register src); |
304 | 1179 #endif |
1180 | |
1181 void movq(Address dst, MMXRegister src ); | |
1182 void movq(MMXRegister dst, Address src ); | |
1183 | |
1184 #ifdef _LP64 | |
1185 // These dummies prevent using movq from converting a zero (like NULL) into Register | |
1186 // by giving the compiler two choices it can't resolve | |
1187 | |
1188 void movq(Address dst, void* dummy); | |
1189 void movq(Register dst, void* dummy); | |
1190 #endif | |
1191 | |
1192 // Move Quadword | |
1193 void movq(Address dst, XMMRegister src); | |
1194 void movq(XMMRegister dst, Address src); | |
1195 | |
1196 void movsbl(Register dst, Address src); | |
1197 void movsbl(Register dst, Register src); | |
1198 | |
1199 #ifdef _LP64 | |
624 | 1200 void movsbq(Register dst, Address src); |
1201 void movsbq(Register dst, Register src); | |
1202 | |
304 | 1203 // Move signed 32bit immediate to 64bit extending sign |
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1204 void movslq(Address dst, int32_t imm64); |
304 | 1205 void movslq(Register dst, int32_t imm64); |
1206 | |
1207 void movslq(Register dst, Address src); | |
1208 void movslq(Register dst, Register src); | |
1209 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous | |
1210 #endif | |
1211 | |
1212 void movswl(Register dst, Address src); | |
1213 void movswl(Register dst, Register src); | |
1214 | |
624 | 1215 #ifdef _LP64 |
1216 void movswq(Register dst, Address src); | |
1217 void movswq(Register dst, Register src); | |
1218 #endif | |
1219 | |
304 | 1220 void movw(Address dst, int imm16); |
1221 void movw(Register dst, Address src); | |
1222 void movw(Address dst, Register src); | |
1223 | |
1224 void movzbl(Register dst, Address src); | |
1225 void movzbl(Register dst, Register src); | |
1226 | |
624 | 1227 #ifdef _LP64 |
1228 void movzbq(Register dst, Address src); | |
1229 void movzbq(Register dst, Register src); | |
1230 #endif | |
1231 | |
304 | 1232 void movzwl(Register dst, Address src); |
1233 void movzwl(Register dst, Register src); | |
1234 | |
624 | 1235 #ifdef _LP64 |
1236 void movzwq(Register dst, Address src); | |
1237 void movzwq(Register dst, Register src); | |
1238 #endif | |
1239 | |
304 | 1240 void mull(Address src); |
1241 void mull(Register src); | |
1242 | |
1243 // Multiply Scalar Double-Precision Floating-Point Values | |
1244 void mulsd(XMMRegister dst, Address src); | |
1245 void mulsd(XMMRegister dst, XMMRegister src); | |
1246 | |
1247 // Multiply Scalar Single-Precision Floating-Point Values | |
1248 void mulss(XMMRegister dst, Address src); | |
1249 void mulss(XMMRegister dst, XMMRegister src); | |
1250 | |
1251 void negl(Register dst); | |
1252 | |
1253 #ifdef _LP64 | |
1254 void negq(Register dst); | |
1255 #endif | |
1256 | |
1257 void nop(int i = 1); | |
1258 | |
1259 void notl(Register dst); | |
1260 | |
1261 #ifdef _LP64 | |
1262 void notq(Register dst); | |
1263 #endif | |
1264 | |
1265 void orl(Address dst, int32_t imm32); | |
1266 void orl(Register dst, int32_t imm32); | |
1267 void orl(Register dst, Address src); | |
1268 void orl(Register dst, Register src); | |
1269 | |
1270 void orq(Address dst, int32_t imm32); | |
1271 void orq(Register dst, int32_t imm32); | |
1272 void orq(Register dst, Address src); | |
1273 void orq(Register dst, Register src); | |
1274 | |
681 | 1275 // SSE4.2 string instructions |
1276 void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8); | |
1277 void pcmpestri(XMMRegister xmm1, Address src, int imm8); | |
1278 | |
1060 | 1279 #ifndef _LP64 // no 32bit push/pop on amd64 |
304 | 1280 void popl(Address dst); |
1060 | 1281 #endif |
304 | 1282 |
1283 #ifdef _LP64 | |
1284 void popq(Address dst); | |
1285 #endif | |
1286 | |
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1287 void popcntl(Register dst, Address src); |
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1288 void popcntl(Register dst, Register src); |
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1289 |
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1290 #ifdef _LP64 |
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1291 void popcntq(Register dst, Address src); |
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1292 void popcntq(Register dst, Register src); |
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1293 #endif |
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1294 |
304 | 1295 // Prefetches (SSE, SSE2, 3DNOW only) |
1296 | |
1297 void prefetchnta(Address src); | |
1298 void prefetchr(Address src); | |
1299 void prefetcht0(Address src); | |
1300 void prefetcht1(Address src); | |
1301 void prefetcht2(Address src); | |
1302 void prefetchw(Address src); | |
1303 | |
2262 | 1304 // POR - Bitwise logical OR |
1305 void por(XMMRegister dst, XMMRegister src); | |
1306 | |
304 | 1307 // Shuffle Packed Doublewords |
1308 void pshufd(XMMRegister dst, XMMRegister src, int mode); | |
1309 void pshufd(XMMRegister dst, Address src, int mode); | |
1310 | |
1311 // Shuffle Packed Low Words | |
1312 void pshuflw(XMMRegister dst, XMMRegister src, int mode); | |
1313 void pshuflw(XMMRegister dst, Address src, int mode); | |
1314 | |
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1315 // Shift Right by bits Logical Quadword Immediate |
304 | 1316 void psrlq(XMMRegister dst, int shift); |
1317 | |
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1318 // Shift Right by bytes Logical DoubleQuadword Immediate |
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1319 void psrldq(XMMRegister dst, int shift); |
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1320 |
681 | 1321 // Logical Compare Double Quadword |
1322 void ptest(XMMRegister dst, XMMRegister src); | |
1323 void ptest(XMMRegister dst, Address src); | |
1324 | |
304 | 1325 // Interleave Low Bytes |
1326 void punpcklbw(XMMRegister dst, XMMRegister src); | |
1327 | |
1060 | 1328 #ifndef _LP64 // no 32bit push/pop on amd64 |
304 | 1329 void pushl(Address src); |
1060 | 1330 #endif |
304 | 1331 |
1332 void pushq(Address src); | |
1333 | |
1334 // Xor Packed Byte Integer Values | |
1335 void pxor(XMMRegister dst, Address src); | |
1336 void pxor(XMMRegister dst, XMMRegister src); | |
1337 | |
1338 void rcll(Register dst, int imm8); | |
1339 | |
1340 void rclq(Register dst, int imm8); | |
1341 | |
1342 void ret(int imm16); | |
0 | 1343 |
1344 void sahf(); | |
1345 | |
304 | 1346 void sarl(Register dst, int imm8); |
1347 void sarl(Register dst); | |
1348 | |
1349 void sarq(Register dst, int imm8); | |
1350 void sarq(Register dst); | |
1351 | |
1352 void sbbl(Address dst, int32_t imm32); | |
1353 void sbbl(Register dst, int32_t imm32); | |
1354 void sbbl(Register dst, Address src); | |
1355 void sbbl(Register dst, Register src); | |
1356 | |
1357 void sbbq(Address dst, int32_t imm32); | |
1358 void sbbq(Register dst, int32_t imm32); | |
1359 void sbbq(Register dst, Address src); | |
1360 void sbbq(Register dst, Register src); | |
1361 | |
1362 void setb(Condition cc, Register dst); | |
1363 | |
1364 void shldl(Register dst, Register src); | |
1365 | |
1366 void shll(Register dst, int imm8); | |
1367 void shll(Register dst); | |
1368 | |
1369 void shlq(Register dst, int imm8); | |
1370 void shlq(Register dst); | |
1371 | |
1372 void shrdl(Register dst, Register src); | |
1373 | |
1374 void shrl(Register dst, int imm8); | |
1375 void shrl(Register dst); | |
1376 | |
1377 void shrq(Register dst, int imm8); | |
1378 void shrq(Register dst); | |
1379 | |
1380 void smovl(); // QQQ generic? | |
1381 | |
1382 // Compute Square Root of Scalar Double-Precision Floating-Point Value | |
1383 void sqrtsd(XMMRegister dst, Address src); | |
1384 void sqrtsd(XMMRegister dst, XMMRegister src); | |
1385 | |
2008 | 1386 // Compute Square Root of Scalar Single-Precision Floating-Point Value |
1387 void sqrtss(XMMRegister dst, Address src); | |
1388 void sqrtss(XMMRegister dst, XMMRegister src); | |
1389 | |
304 | 1390 void std() { emit_byte(0xfd); } |
1391 | |
1392 void stmxcsr( Address dst ); | |
1393 | |
1394 void subl(Address dst, int32_t imm32); | |
1395 void subl(Address dst, Register src); | |
1396 void subl(Register dst, int32_t imm32); | |
1397 void subl(Register dst, Address src); | |
1398 void subl(Register dst, Register src); | |
1399 | |
1400 void subq(Address dst, int32_t imm32); | |
1401 void subq(Address dst, Register src); | |
1402 void subq(Register dst, int32_t imm32); | |
1403 void subq(Register dst, Address src); | |
1404 void subq(Register dst, Register src); | |
1405 | |
1406 | |
1407 // Subtract Scalar Double-Precision Floating-Point Values | |
1408 void subsd(XMMRegister dst, Address src); | |
0 | 1409 void subsd(XMMRegister dst, XMMRegister src); |
1410 | |
304 | 1411 // Subtract Scalar Single-Precision Floating-Point Values |
1412 void subss(XMMRegister dst, Address src); | |
1413 void subss(XMMRegister dst, XMMRegister src); | |
1414 | |
1415 void testb(Register dst, int imm8); | |
1416 | |
1417 void testl(Register dst, int32_t imm32); | |
1418 void testl(Register dst, Register src); | |
1419 void testl(Register dst, Address src); | |
1420 | |
1421 void testq(Register dst, int32_t imm32); | |
1422 void testq(Register dst, Register src); | |
1423 | |
1424 | |
1425 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS | |
1426 void ucomisd(XMMRegister dst, Address src); | |
0 | 1427 void ucomisd(XMMRegister dst, XMMRegister src); |
1428 | |
304 | 1429 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS |
1430 void ucomiss(XMMRegister dst, Address src); | |
1431 void ucomiss(XMMRegister dst, XMMRegister src); | |
1432 | |
1433 void xaddl(Address dst, Register src); | |
1434 | |
1435 void xaddq(Address dst, Register src); | |
1436 | |
1437 void xchgl(Register reg, Address adr); | |
1438 void xchgl(Register dst, Register src); | |
1439 | |
1440 void xchgq(Register reg, Address adr); | |
1441 void xchgq(Register dst, Register src); | |
1442 | |
1443 void xorl(Register dst, int32_t imm32); | |
1444 void xorl(Register dst, Address src); | |
1445 void xorl(Register dst, Register src); | |
1446 | |
1447 void xorq(Register dst, Address src); | |
1448 void xorq(Register dst, Register src); | |
1449 | |
1450 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values | |
1451 void xorpd(XMMRegister dst, Address src); | |
1452 void xorpd(XMMRegister dst, XMMRegister src); | |
1453 | |
1454 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values | |
1455 void xorps(XMMRegister dst, Address src); | |
0 | 1456 void xorps(XMMRegister dst, XMMRegister src); |
304 | 1457 |
1458 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0 | |
0 | 1459 }; |
1460 | |
1461 | |
1462 // MacroAssembler extends Assembler by frequently used macros. | |
1463 // | |
1464 // Instructions for which a 'better' code sequence exists depending | |
1465 // on arguments should also go in here. | |
1466 | |
1467 class MacroAssembler: public Assembler { | |
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1468 friend class LIR_Assembler; |
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1469 friend class Runtime1; // as_Address() |
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1470 |
0 | 1471 protected: |
1472 | |
1473 Address as_Address(AddressLiteral adr); | |
1474 Address as_Address(ArrayAddress adr); | |
1475 | |
1476 // Support for VM calls | |
1477 // | |
1478 // This is the base routine called by the different versions of call_VM_leaf. The interpreter | |
1479 // may customize this version by overriding it for its purposes (e.g., to save/restore | |
1480 // additional registers when doing a VM call). | |
1481 #ifdef CC_INTERP | |
1482 // c++ interpreter never wants to use interp_masm version of call_VM | |
1483 #define VIRTUAL | |
1484 #else | |
1485 #define VIRTUAL virtual | |
1486 #endif | |
1487 | |
1488 VIRTUAL void call_VM_leaf_base( | |
1489 address entry_point, // the entry point | |
1490 int number_of_arguments // the number of arguments to pop after the call | |
1491 ); | |
1492 | |
1493 // This is the base routine called by the different versions of call_VM. The interpreter | |
1494 // may customize this version by overriding it for its purposes (e.g., to save/restore | |
1495 // additional registers when doing a VM call). | |
1496 // | |
1497 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base | |
1498 // returns the register which contains the thread upon return. If a thread register has been | |
1499 // specified, the return value will correspond to that register. If no last_java_sp is specified | |
1500 // (noreg) than rsp will be used instead. | |
1501 VIRTUAL void call_VM_base( // returns the register containing the thread upon return | |
1502 Register oop_result, // where an oop-result ends up if any; use noreg otherwise | |
1503 Register java_thread, // the thread if computed before ; use noreg otherwise | |
1504 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise | |
1505 address entry_point, // the entry point | |
1506 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call | |
1507 bool check_exceptions // whether to check for pending exceptions after return | |
1508 ); | |
1509 | |
1510 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code. | |
1511 // The implementation is only non-empty for the InterpreterMacroAssembler, | |
1512 // as only the interpreter handles PopFrame and ForceEarlyReturn requests. | |
1513 virtual void check_and_handle_popframe(Register java_thread); | |
1514 virtual void check_and_handle_earlyret(Register java_thread); | |
1515 | |
1516 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true); | |
1517 | |
1518 // helpers for FPU flag access | |
1519 // tmp is a temporary register, if none is available use noreg | |
1520 void save_rax (Register tmp); | |
1521 void restore_rax(Register tmp); | |
1522 | |
1523 public: | |
1524 MacroAssembler(CodeBuffer* code) : Assembler(code) {} | |
1525 | |
1526 // Support for NULL-checks | |
1527 // | |
1528 // Generates code that causes a NULL OS exception if the content of reg is NULL. | |
1529 // If the accessed location is M[reg + offset] and the offset is known, provide the | |
1530 // offset. No explicit code generation is needed if the offset is within a certain | |
1531 // range (0 <= offset <= page_size). | |
1532 | |
1533 void null_check(Register reg, int offset = -1); | |
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1534 static bool needs_explicit_null_check(intptr_t offset); |
0 | 1535 |
1536 // Required platform-specific helpers for Label::patch_instructions. | |
1537 // They _shadow_ the declarations in AbstractAssembler, which are undefined. | |
1538 void pd_patch_instruction(address branch, address target); | |
1539 #ifndef PRODUCT | |
1540 static void pd_print_patched_instruction(address branch); | |
1541 #endif | |
1542 | |
1543 // The following 4 methods return the offset of the appropriate move instruction | |
1544 | |
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1545 // Support for fast byte/short loading with zero extension (depending on particular CPU) |
0 | 1546 int load_unsigned_byte(Register dst, Address src); |
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1547 int load_unsigned_short(Register dst, Address src); |
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1548 |
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1549 // Support for fast byte/short loading with sign extension (depending on particular CPU) |
0 | 1550 int load_signed_byte(Register dst, Address src); |
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1551 int load_signed_short(Register dst, Address src); |
0 | 1552 |
1553 // Support for sign-extension (hi:lo = extend_sign(lo)) | |
1554 void extend_sign(Register hi, Register lo); | |
1555 | |
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1556 // Load and store values by size and signed-ness |
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1557 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg); |
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1558 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg); |
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1559 |
0 | 1560 // Support for inc/dec with optimal instruction selection depending on value |
304 | 1561 |
1562 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; } | |
1563 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; } | |
1564 | |
1565 void decrementl(Address dst, int value = 1); | |
1566 void decrementl(Register reg, int value = 1); | |
1567 | |
1568 void decrementq(Register reg, int value = 1); | |
1569 void decrementq(Address dst, int value = 1); | |
1570 | |
1571 void incrementl(Address dst, int value = 1); | |
1572 void incrementl(Register reg, int value = 1); | |
1573 | |
1574 void incrementq(Register reg, int value = 1); | |
1575 void incrementq(Address dst, int value = 1); | |
1576 | |
0 | 1577 |
1578 // Support optimal SSE move instructions. | |
1579 void movflt(XMMRegister dst, XMMRegister src) { | |
1580 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; } | |
1581 else { movss (dst, src); return; } | |
1582 } | |
1583 void movflt(XMMRegister dst, Address src) { movss(dst, src); } | |
1584 void movflt(XMMRegister dst, AddressLiteral src); | |
1585 void movflt(Address dst, XMMRegister src) { movss(dst, src); } | |
1586 | |
1587 void movdbl(XMMRegister dst, XMMRegister src) { | |
1588 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; } | |
1589 else { movsd (dst, src); return; } | |
1590 } | |
1591 | |
1592 void movdbl(XMMRegister dst, AddressLiteral src); | |
1593 | |
1594 void movdbl(XMMRegister dst, Address src) { | |
1595 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; } | |
1596 else { movlpd(dst, src); return; } | |
1597 } | |
1598 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); } | |
1599 | |
304 | 1600 void incrementl(AddressLiteral dst); |
1601 void incrementl(ArrayAddress dst); | |
0 | 1602 |
1603 // Alignment | |
1604 void align(int modulus); | |
1605 | |
1606 // Misc | |
1607 void fat_nop(); // 5 byte nop | |
1608 | |
1609 // Stack frame creation/removal | |
1610 void enter(); | |
1611 void leave(); | |
1612 | |
1613 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information) | |
1614 // The pointer will be loaded into the thread register. | |
1615 void get_thread(Register thread); | |
1616 | |
362 | 1617 |
0 | 1618 // Support for VM calls |
1619 // | |
1620 // It is imperative that all calls into the VM are handled via the call_VM macros. | |
1621 // They make sure that the stack linkage is setup correctly. call_VM's correspond | |
1622 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points. | |
1623 | |
304 | 1624 |
1625 void call_VM(Register oop_result, | |
1626 address entry_point, | |
1627 bool check_exceptions = true); | |
1628 void call_VM(Register oop_result, | |
1629 address entry_point, | |
1630 Register arg_1, | |
1631 bool check_exceptions = true); | |
1632 void call_VM(Register oop_result, | |
1633 address entry_point, | |
1634 Register arg_1, Register arg_2, | |
1635 bool check_exceptions = true); | |
1636 void call_VM(Register oop_result, | |
1637 address entry_point, | |
1638 Register arg_1, Register arg_2, Register arg_3, | |
1639 bool check_exceptions = true); | |
1640 | |
1641 // Overloadings with last_Java_sp | |
1642 void call_VM(Register oop_result, | |
1643 Register last_java_sp, | |
1644 address entry_point, | |
1645 int number_of_arguments = 0, | |
1646 bool check_exceptions = true); | |
1647 void call_VM(Register oop_result, | |
1648 Register last_java_sp, | |
1649 address entry_point, | |
1650 Register arg_1, bool | |
1651 check_exceptions = true); | |
1652 void call_VM(Register oop_result, | |
1653 Register last_java_sp, | |
1654 address entry_point, | |
1655 Register arg_1, Register arg_2, | |
1656 bool check_exceptions = true); | |
1657 void call_VM(Register oop_result, | |
1658 Register last_java_sp, | |
1659 address entry_point, | |
1660 Register arg_1, Register arg_2, Register arg_3, | |
1661 bool check_exceptions = true); | |
1662 | |
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1663 // These always tightly bind to MacroAssembler::call_VM_base |
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1664 // bypassing the virtual implementation |
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1665 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true); |
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1666 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true); |
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1667 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); |
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1668 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); |
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1669 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true); |
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1670 |
304 | 1671 void call_VM_leaf(address entry_point, |
1672 int number_of_arguments = 0); | |
1673 void call_VM_leaf(address entry_point, | |
1674 Register arg_1); | |
1675 void call_VM_leaf(address entry_point, | |
1676 Register arg_1, Register arg_2); | |
1677 void call_VM_leaf(address entry_point, | |
1678 Register arg_1, Register arg_2, Register arg_3); | |
0 | 1679 |
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1680 // These always tightly bind to MacroAssembler::call_VM_leaf_base |
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1681 // bypassing the virtual implementation |
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1682 void super_call_VM_leaf(address entry_point); |
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1683 void super_call_VM_leaf(address entry_point, Register arg_1); |
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1684 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2); |
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1685 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3); |
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1686 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4); |
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1687 |
0 | 1688 // last Java Frame (fills frame anchor) |
304 | 1689 void set_last_Java_frame(Register thread, |
1690 Register last_java_sp, | |
1691 Register last_java_fp, | |
1692 address last_java_pc); | |
1693 | |
1694 // thread in the default location (r15_thread on 64bit) | |
1695 void set_last_Java_frame(Register last_java_sp, | |
1696 Register last_java_fp, | |
1697 address last_java_pc); | |
1698 | |
0 | 1699 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc); |
1700 | |
304 | 1701 // thread in the default location (r15_thread on 64bit) |
1702 void reset_last_Java_frame(bool clear_fp, bool clear_pc); | |
1703 | |
0 | 1704 // Stores |
1705 void store_check(Register obj); // store check for obj - register is destroyed afterwards | |
1706 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed) | |
1707 | |
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1708 #ifndef SERIALGC |
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1709 |
362 | 1710 void g1_write_barrier_pre(Register obj, |
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1711 Register pre_val, |
362 | 1712 Register thread, |
1713 Register tmp, | |
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1714 bool tosca_live, |
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1715 bool expand_call); |
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1716 |
362 | 1717 void g1_write_barrier_post(Register store_addr, |
1718 Register new_val, | |
1719 Register thread, | |
1720 Register tmp, | |
1721 Register tmp2); | |
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1722 |
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1723 #endif // SERIALGC |
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1724 |
0 | 1725 // split store_check(Register obj) to enhance instruction interleaving |
1726 void store_check_part_1(Register obj); | |
1727 void store_check_part_2(Register obj); | |
1728 | |
1729 // C 'boolean' to Java boolean: x == 0 ? 0 : 1 | |
1730 void c2bool(Register x); | |
1731 | |
1732 // C++ bool manipulation | |
1733 | |
1734 void movbool(Register dst, Address src); | |
1735 void movbool(Address dst, bool boolconst); | |
1736 void movbool(Address dst, Register src); | |
1737 void testbool(Register dst); | |
1738 | |
304 | 1739 // oop manipulations |
1740 void load_klass(Register dst, Register src); | |
1741 void store_klass(Register dst, Register src); | |
1742 | |
1846 | 1743 void load_heap_oop(Register dst, Address src); |
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1744 void load_heap_oop_not_null(Register dst, Address src); |
1846 | 1745 void store_heap_oop(Address dst, Register src); |
1746 | |
1747 // Used for storing NULL. All other oop constants should be | |
1748 // stored using routines that take a jobject. | |
1749 void store_heap_oop_null(Address dst); | |
1750 | |
304 | 1751 void load_prototype_header(Register dst, Register src); |
1752 | |
1753 #ifdef _LP64 | |
1754 void store_klass_gap(Register dst, Register src); | |
1755 | |
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1756 // This dummy is to prevent a call to store_heap_oop from |
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1757 // converting a zero (like NULL) into a Register by giving |
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1758 // the compiler two choices it can't resolve |
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1759 |
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1760 void store_heap_oop(Address dst, void* dummy); |
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1761 |
304 | 1762 void encode_heap_oop(Register r); |
1763 void decode_heap_oop(Register r); | |
1764 void encode_heap_oop_not_null(Register r); | |
1765 void decode_heap_oop_not_null(Register r); | |
1766 void encode_heap_oop_not_null(Register dst, Register src); | |
1767 void decode_heap_oop_not_null(Register dst, Register src); | |
1768 | |
1769 void set_narrow_oop(Register dst, jobject obj); | |
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1770 void set_narrow_oop(Address dst, jobject obj); |
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1771 void cmp_narrow_oop(Register dst, jobject obj); |
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1772 void cmp_narrow_oop(Address dst, jobject obj); |
304 | 1773 |
1774 // if heap base register is used - reinit it with the correct value | |
1775 void reinit_heapbase(); | |
1684
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1776 |
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1777 DEBUG_ONLY(void verify_heapbase(const char* msg);) |
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1778 |
304 | 1779 #endif // _LP64 |
1780 | |
1781 // Int division/remainder for Java | |
0 | 1782 // (as idivl, but checks for special case as described in JVM spec.) |
1783 // returns idivl instruction offset for implicit exception handling | |
1784 int corrected_idivl(Register reg); | |
1785 | |
304 | 1786 // Long division/remainder for Java |
1787 // (as idivq, but checks for special case as described in JVM spec.) | |
1788 // returns idivq instruction offset for implicit exception handling | |
1789 int corrected_idivq(Register reg); | |
1790 | |
0 | 1791 void int3(); |
1792 | |
304 | 1793 // Long operation macros for a 32bit cpu |
0 | 1794 // Long negation for Java |
1795 void lneg(Register hi, Register lo); | |
1796 | |
1797 // Long multiplication for Java | |
304 | 1798 // (destroys contents of eax, ebx, ecx and edx) |
0 | 1799 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y |
1800 | |
1801 // Long shifts for Java | |
1802 // (semantics as described in JVM spec.) | |
1803 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f) | |
1804 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f) | |
1805 | |
1806 // Long compare for Java | |
1807 // (semantics as described in JVM spec.) | |
1808 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y) | |
1809 | |
304 | 1810 |
1811 // misc | |
1812 | |
1813 // Sign extension | |
1814 void sign_extend_short(Register reg); | |
1815 void sign_extend_byte(Register reg); | |
1816 | |
1817 // Division by power of 2, rounding towards 0 | |
1818 void division_with_shift(Register reg, int shift_value); | |
1819 | |
0 | 1820 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows: |
1821 // | |
1822 // CF (corresponds to C0) if x < y | |
1823 // PF (corresponds to C2) if unordered | |
1824 // ZF (corresponds to C3) if x = y | |
1825 // | |
1826 // The arguments are in reversed order on the stack (i.e., top of stack is first argument). | |
1827 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code) | |
1828 void fcmp(Register tmp); | |
1829 // Variant of the above which allows y to be further down the stack | |
1830 // and which only pops x and y if specified. If pop_right is | |
1831 // specified then pop_left must also be specified. | |
1832 void fcmp(Register tmp, int index, bool pop_left, bool pop_right); | |
1833 | |
1834 // Floating-point comparison for Java | |
1835 // Compares the top-most stack entries on the FPU stack and stores the result in dst. | |
1836 // The arguments are in reversed order on the stack (i.e., top of stack is first argument). | |
1837 // (semantics as described in JVM spec.) | |
1838 void fcmp2int(Register dst, bool unordered_is_less); | |
1839 // Variant of the above which allows y to be further down the stack | |
1840 // and which only pops x and y if specified. If pop_right is | |
1841 // specified then pop_left must also be specified. | |
1842 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right); | |
1843 | |
1844 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards) | |
1845 // tmp is a temporary register, if none is available use noreg | |
1846 void fremr(Register tmp); | |
1847 | |
1848 | |
1849 // same as fcmp2int, but using SSE2 | |
1850 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); | |
1851 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); | |
1852 | |
1853 // Inlined sin/cos generator for Java; must not use CPU instruction | |
1854 // directly on Intel as it does not have high enough precision | |
1855 // outside of the range [-pi/4, pi/4]. Extra argument indicate the | |
1856 // number of FPU stack slots in use; all but the topmost will | |
1857 // require saving if a slow case is necessary. Assumes argument is | |
1858 // on FP TOS; result is on FP TOS. No cpu registers are changed by | |
1859 // this code. | |
1860 void trigfunc(char trig, int num_fpu_regs_in_use = 1); | |
1861 | |
1862 // branch to L if FPU flag C2 is set/not set | |
1863 // tmp is a temporary register, if none is available use noreg | |
1864 void jC2 (Register tmp, Label& L); | |
1865 void jnC2(Register tmp, Label& L); | |
1866 | |
1867 // Pop ST (ffree & fincstp combined) | |
1868 void fpop(); | |
1869 | |
1870 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack | |
1871 void push_fTOS(); | |
1872 | |
1873 // pops double TOS element from CPU stack and pushes on FPU stack | |
1874 void pop_fTOS(); | |
1875 | |
1876 void empty_FPU_stack(); | |
1877 | |
1878 void push_IU_state(); | |
1879 void pop_IU_state(); | |
1880 | |
1881 void push_FPU_state(); | |
1882 void pop_FPU_state(); | |
1883 | |
1884 void push_CPU_state(); | |
1885 void pop_CPU_state(); | |
1886 | |
1887 // Round up to a power of two | |
1888 void round_to(Register reg, int modulus); | |
1889 | |
1890 // Callee saved registers handling | |
1891 void push_callee_saved_registers(); | |
1892 void pop_callee_saved_registers(); | |
1893 | |
1894 // allocation | |
1895 void eden_allocate( | |
1896 Register obj, // result: pointer to object after successful allocation | |
1897 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise | |
1898 int con_size_in_bytes, // object size in bytes if known at compile time | |
1899 Register t1, // temp register | |
1900 Label& slow_case // continuation point if fast allocation fails | |
1901 ); | |
1902 void tlab_allocate( | |
1903 Register obj, // result: pointer to object after successful allocation | |
1904 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise | |
1905 int con_size_in_bytes, // object size in bytes if known at compile time | |
1906 Register t1, // temp register | |
1907 Register t2, // temp register | |
1908 Label& slow_case // continuation point if fast allocation fails | |
1909 ); | |
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1910 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address |
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1911 void incr_allocated_bytes(Register thread, |
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1912 Register var_size_in_bytes, int con_size_in_bytes, |
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1913 Register t1 = noreg); |
0 | 1914 |
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1915 // interface method calling |
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1916 void lookup_interface_method(Register recv_klass, |
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1917 Register intf_klass, |
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1918 RegisterOrConstant itable_index, |
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1919 Register method_result, |
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1920 Register scan_temp, |
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1921 Label& no_such_interface); |
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1922 |
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1923 // Test sub_klass against super_klass, with fast and slow paths. |
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1924 |
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1925 // The fast path produces a tri-state answer: yes / no / maybe-slow. |
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1926 // One of the three labels can be NULL, meaning take the fall-through. |
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1927 // If super_check_offset is -1, the value is loaded up from super_klass. |
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1928 // No registers are killed, except temp_reg. |
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1929 void check_klass_subtype_fast_path(Register sub_klass, |
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1930 Register super_klass, |
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1931 Register temp_reg, |
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1932 Label* L_success, |
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1933 Label* L_failure, |
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1934 Label* L_slow_path, |
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1935 RegisterOrConstant super_check_offset = RegisterOrConstant(-1)); |
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1936 |
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1937 // The rest of the type check; must be wired to a corresponding fast path. |
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1938 // It does not repeat the fast path logic, so don't use it standalone. |
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1939 // The temp_reg and temp2_reg can be noreg, if no temps are available. |
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1940 // Updates the sub's secondary super cache as necessary. |
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1941 // If set_cond_codes, condition codes will be Z on success, NZ on failure. |
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1942 void check_klass_subtype_slow_path(Register sub_klass, |
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1943 Register super_klass, |
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1944 Register temp_reg, |
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1945 Register temp2_reg, |
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1946 Label* L_success, |
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1947 Label* L_failure, |
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1948 bool set_cond_codes = false); |
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1949 |
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1950 // Simplified, combined version, good for typical uses. |
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1951 // Falls through on failure. |
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1952 void check_klass_subtype(Register sub_klass, |
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1953 Register super_klass, |
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1954 Register temp_reg, |
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1955 Label& L_success); |
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1956 |
710 | 1957 // method handles (JSR 292) |
1958 void check_method_handle_type(Register mtype_reg, Register mh_reg, | |
1959 Register temp_reg, | |
1960 Label& wrong_method_type); | |
1961 void load_method_handle_vmslots(Register vmslots_reg, Register mh_reg, | |
1962 Register temp_reg); | |
1963 void jump_to_method_handle_entry(Register mh_reg, Register temp_reg); | |
1964 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0); | |
1965 | |
1966 | |
0 | 1967 //---- |
1968 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0 | |
1969 | |
1970 // Debugging | |
304 | 1971 |
1972 // only if +VerifyOops | |
1973 void verify_oop(Register reg, const char* s = "broken oop"); | |
0 | 1974 void verify_oop_addr(Address addr, const char * s = "broken oop addr"); |
1975 | |
304 | 1976 // only if +VerifyFPU |
1977 void verify_FPU(int stack_depth, const char* s = "illegal FPU state"); | |
1978 | |
1979 // prints msg, dumps registers and stops execution | |
1980 void stop(const char* msg); | |
1981 | |
1982 // prints msg and continues | |
1983 void warn(const char* msg); | |
1984 | |
1985 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg); | |
1986 static void debug64(char* msg, int64_t pc, int64_t regs[]); | |
1987 | |
0 | 1988 void os_breakpoint(); |
304 | 1989 |
0 | 1990 void untested() { stop("untested"); } |
304 | 1991 |
1846 | 1992 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); } |
304 | 1993 |
0 | 1994 void should_not_reach_here() { stop("should not reach here"); } |
304 | 1995 |
0 | 1996 void print_CPU_state(); |
1997 | |
1998 // Stack overflow checking | |
1999 void bang_stack_with_offset(int offset) { | |
2000 // stack grows down, caller passes positive offset | |
2001 assert(offset > 0, "must bang with negative offset"); | |
2002 movl(Address(rsp, (-offset)), rax); | |
2003 } | |
2004 | |
2005 // Writes to stack successive pages until offset reached to check for | |
2006 // stack overflow + shadow pages. Also, clobbers tmp | |
2007 void bang_stack_size(Register size, Register tmp); | |
2008 | |
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2009 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, |
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2010 Register tmp, |
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2011 int offset); |
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2012 |
0 | 2013 // Support for serializing memory accesses between threads |
2014 void serialize_memory(Register thread, Register tmp); | |
2015 | |
2016 void verify_tlab(); | |
2017 | |
2018 // Biased locking support | |
2019 // lock_reg and obj_reg must be loaded up with the appropriate values. | |
2020 // swap_reg must be rax, and is killed. | |
2021 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will | |
2022 // be killed; if not supplied, push/pop will be used internally to | |
2023 // allocate a temporary (inefficient, avoid if possible). | |
2024 // Optional slow case is for implementations (interpreter and C1) which branch to | |
2025 // slow case directly. Leaves condition codes set for C2's Fast_Lock node. | |
2026 // Returns offset of first potentially-faulting instruction for null | |
2027 // check info (currently consumed only by C1). If | |
2028 // swap_reg_contains_mark is true then returns -1 as it is assumed | |
2029 // the calling code has already passed any potential faults. | |
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2030 int biased_locking_enter(Register lock_reg, Register obj_reg, |
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2031 Register swap_reg, Register tmp_reg, |
0 | 2032 bool swap_reg_contains_mark, |
2033 Label& done, Label* slow_case = NULL, | |
2034 BiasedLockingCounters* counters = NULL); | |
2035 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done); | |
2036 | |
2037 | |
2038 Condition negate_condition(Condition cond); | |
2039 | |
2040 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit | |
2041 // operands. In general the names are modified to avoid hiding the instruction in Assembler | |
2042 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers | |
2043 // here in MacroAssembler. The major exception to this rule is call | |
2044 | |
2045 // Arithmetics | |
2046 | |
304 | 2047 |
2048 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; } | |
2049 void addptr(Address dst, Register src); | |
2050 | |
2051 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); } | |
2052 void addptr(Register dst, int32_t src); | |
2053 void addptr(Register dst, Register src); | |
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2054 void addptr(Register dst, RegisterOrConstant src) { |
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2055 if (src.is_constant()) addptr(dst, (int) src.as_constant()); |
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2056 else addptr(dst, src.as_register()); |
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2057 } |
304 | 2058 |
2059 void andptr(Register dst, int32_t src); | |
2060 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; } | |
2061 | |
2062 void cmp8(AddressLiteral src1, int imm); | |
2063 | |
2064 // renamed to drag out the casting of address to int32_t/intptr_t | |
0 | 2065 void cmp32(Register src1, int32_t imm); |
2066 | |
2067 void cmp32(AddressLiteral src1, int32_t imm); | |
2068 // compare reg - mem, or reg - &mem | |
2069 void cmp32(Register src1, AddressLiteral src2); | |
2070 | |
2071 void cmp32(Register src1, Address src2); | |
2072 | |
304 | 2073 #ifndef _LP64 |
2074 void cmpoop(Address dst, jobject obj); | |
2075 void cmpoop(Register dst, jobject obj); | |
2076 #endif // _LP64 | |
2077 | |
0 | 2078 // NOTE src2 must be the lval. This is NOT an mem-mem compare |
2079 void cmpptr(Address src1, AddressLiteral src2); | |
2080 | |
2081 void cmpptr(Register src1, AddressLiteral src2); | |
2082 | |
304 | 2083 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } |
2084 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } | |
2085 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } | |
2086 | |
2087 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } | |
2088 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } | |
2089 | |
2090 // cmp64 to avoild hiding cmpq | |
2091 void cmp64(Register src1, AddressLiteral src); | |
2092 | |
2093 void cmpxchgptr(Register reg, Address adr); | |
2094 | |
2095 void locked_cmpxchgptr(Register reg, AddressLiteral adr); | |
2096 | |
2097 | |
2098 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); } | |
2099 | |
2100 | |
2101 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); } | |
2102 | |
2103 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); } | |
2104 | |
2105 void shlptr(Register dst, int32_t shift); | |
2106 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); } | |
2107 | |
2108 void shrptr(Register dst, int32_t shift); | |
2109 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); } | |
2110 | |
2111 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); } | |
2112 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); } | |
2113 | |
2114 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); } | |
2115 | |
2116 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); } | |
2117 void subptr(Register dst, int32_t src); | |
2118 void subptr(Register dst, Register src); | |
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2119 void subptr(Register dst, RegisterOrConstant src) { |
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2120 if (src.is_constant()) subptr(dst, (int) src.as_constant()); |
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2121 else subptr(dst, src.as_register()); |
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2122 } |
304 | 2123 |
2124 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); } | |
2125 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); } | |
2126 | |
2127 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; } | |
2128 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; } | |
2129 | |
2130 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; } | |
2131 | |
2132 | |
0 | 2133 |
2134 // Helper functions for statistics gathering. | |
2135 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes. | |
2136 void cond_inc32(Condition cond, AddressLiteral counter_addr); | |
2137 // Unconditional atomic increment. | |
2138 void atomic_incl(AddressLiteral counter_addr); | |
2139 | |
2140 void lea(Register dst, AddressLiteral adr); | |
2141 void lea(Address dst, AddressLiteral adr); | |
304 | 2142 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); } |
2143 | |
2144 void leal32(Register dst, Address src) { leal(dst, src); } | |
2145 | |
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2146 // Import other testl() methods from the parent class or else |
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2147 // they will be hidden by the following overriding declaration. |
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2148 using Assembler::testl; |
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2149 void testl(Register dst, AddressLiteral src); |
304 | 2150 |
2151 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } | |
2152 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } | |
2153 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } | |
2154 | |
2155 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); } | |
2156 void testptr(Register src1, Register src2); | |
2157 | |
2158 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); } | |
2159 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); } | |
0 | 2160 |
2161 // Calls | |
2162 | |
2163 void call(Label& L, relocInfo::relocType rtype); | |
2164 void call(Register entry); | |
2165 | |
2166 // NOTE: this call tranfers to the effective address of entry NOT | |
2167 // the address contained by entry. This is because this is more natural | |
2168 // for jumps/calls. | |
2169 void call(AddressLiteral entry); | |
2170 | |
2171 // Jumps | |
2172 | |
2173 // NOTE: these jumps tranfer to the effective address of dst NOT | |
2174 // the address contained by dst. This is because this is more natural | |
2175 // for jumps/calls. | |
2176 void jump(AddressLiteral dst); | |
2177 void jump_cc(Condition cc, AddressLiteral dst); | |
2178 | |
2179 // 32bit can do a case table jump in one instruction but we no longer allow the base | |
2180 // to be installed in the Address class. This jump will tranfers to the address | |
2181 // contained in the location described by entry (not the address of entry) | |
2182 void jump(ArrayAddress entry); | |
2183 | |
2184 // Floating | |
2185 | |
2186 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); } | |
2187 void andpd(XMMRegister dst, AddressLiteral src); | |
2188 | |
2189 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); } | |
2190 void comiss(XMMRegister dst, AddressLiteral src); | |
2191 | |
2192 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); } | |
2193 void comisd(XMMRegister dst, AddressLiteral src); | |
2194 | |
2008 | 2195 void fadd_s(Address src) { Assembler::fadd_s(src); } |
2196 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); } | |
2197 | |
0 | 2198 void fldcw(Address src) { Assembler::fldcw(src); } |
2199 void fldcw(AddressLiteral src); | |
2200 | |
2201 void fld_s(int index) { Assembler::fld_s(index); } | |
2202 void fld_s(Address src) { Assembler::fld_s(src); } | |
2203 void fld_s(AddressLiteral src); | |
2204 | |
2205 void fld_d(Address src) { Assembler::fld_d(src); } | |
2206 void fld_d(AddressLiteral src); | |
2207 | |
2208 void fld_x(Address src) { Assembler::fld_x(src); } | |
2209 void fld_x(AddressLiteral src); | |
2210 | |
2008 | 2211 void fmul_s(Address src) { Assembler::fmul_s(src); } |
2212 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); } | |
2213 | |
0 | 2214 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); } |
2215 void ldmxcsr(AddressLiteral src); | |
2216 | |
304 | 2217 private: |
2218 // these are private because users should be doing movflt/movdbl | |
2219 | |
0 | 2220 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); } |
2221 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); } | |
2222 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); } | |
2223 void movss(XMMRegister dst, AddressLiteral src); | |
2224 | |
304 | 2225 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); } |
2226 void movlpd(XMMRegister dst, AddressLiteral src); | |
2227 | |
2228 public: | |
2229 | |
2008 | 2230 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); } |
2231 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); } | |
2232 void addsd(XMMRegister dst, AddressLiteral src) { Assembler::addsd(dst, as_Address(src)); } | |
2233 | |
2234 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); } | |
2235 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); } | |
2236 void addss(XMMRegister dst, AddressLiteral src) { Assembler::addss(dst, as_Address(src)); } | |
2237 | |
2238 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); } | |
2239 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); } | |
2240 void divsd(XMMRegister dst, AddressLiteral src) { Assembler::divsd(dst, as_Address(src)); } | |
2241 | |
2242 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); } | |
2243 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); } | |
2244 void divss(XMMRegister dst, AddressLiteral src) { Assembler::divss(dst, as_Address(src)); } | |
2245 | |
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2246 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); } |
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2247 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); } |
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2248 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); } |
2008 | 2249 void movsd(XMMRegister dst, AddressLiteral src) { Assembler::movsd(dst, as_Address(src)); } |
2250 | |
2251 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); } | |
2252 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); } | |
2253 void mulsd(XMMRegister dst, AddressLiteral src) { Assembler::mulsd(dst, as_Address(src)); } | |
2254 | |
2255 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); } | |
2256 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); } | |
2257 void mulss(XMMRegister dst, AddressLiteral src) { Assembler::mulss(dst, as_Address(src)); } | |
2258 | |
2259 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); } | |
2260 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); } | |
2261 void sqrtsd(XMMRegister dst, AddressLiteral src) { Assembler::sqrtsd(dst, as_Address(src)); } | |
2262 | |
2263 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); } | |
2264 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); } | |
2265 void sqrtss(XMMRegister dst, AddressLiteral src) { Assembler::sqrtss(dst, as_Address(src)); } | |
2266 | |
2267 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); } | |
2268 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); } | |
2269 void subsd(XMMRegister dst, AddressLiteral src) { Assembler::subsd(dst, as_Address(src)); } | |
2270 | |
2271 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); } | |
2272 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); } | |
2273 void subss(XMMRegister dst, AddressLiteral src) { Assembler::subss(dst, as_Address(src)); } | |
0 | 2274 |
2275 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); } | |
2276 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); } | |
2277 void ucomiss(XMMRegister dst, AddressLiteral src); | |
2278 | |
2279 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); } | |
2280 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); } | |
2281 void ucomisd(XMMRegister dst, AddressLiteral src); | |
2282 | |
2283 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values | |
2284 void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); } | |
2285 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); } | |
2286 void xorpd(XMMRegister dst, AddressLiteral src); | |
2287 | |
2288 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values | |
2289 void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); } | |
2290 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); } | |
2291 void xorps(XMMRegister dst, AddressLiteral src); | |
2292 | |
2293 // Data | |
2294 | |
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2295 void cmov32( Condition cc, Register dst, Address src); |
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2296 void cmov32( Condition cc, Register dst, Register src); |
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2297 |
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2298 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); } |
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2299 |
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2300 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); } |
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2301 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); } |
304 | 2302 |
0 | 2303 void movoop(Register dst, jobject obj); |
2304 void movoop(Address dst, jobject obj); | |
2305 | |
2306 void movptr(ArrayAddress dst, Register src); | |
2307 // can this do an lea? | |
2308 void movptr(Register dst, ArrayAddress src); | |
2309 | |
304 | 2310 void movptr(Register dst, Address src); |
2311 | |
0 | 2312 void movptr(Register dst, AddressLiteral src); |
2313 | |
304 | 2314 void movptr(Register dst, intptr_t src); |
2315 void movptr(Register dst, Register src); | |
2316 void movptr(Address dst, intptr_t src); | |
2317 | |
2318 void movptr(Address dst, Register src); | |
2319 | |
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2320 void movptr(Register dst, RegisterOrConstant src) { |
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2321 if (src.is_constant()) movptr(dst, src.as_constant()); |
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2322 else movptr(dst, src.as_register()); |
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2323 } |
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2324 |
304 | 2325 #ifdef _LP64 |
2326 // Generally the next two are only used for moving NULL | |
2327 // Although there are situations in initializing the mark word where | |
2328 // they could be used. They are dangerous. | |
2329 | |
2330 // They only exist on LP64 so that int32_t and intptr_t are not the same | |
2331 // and we have ambiguous declarations. | |
2332 | |
2333 void movptr(Address dst, int32_t imm32); | |
2334 void movptr(Register dst, int32_t imm32); | |
2335 #endif // _LP64 | |
2336 | |
0 | 2337 // to avoid hiding movl |
2338 void mov32(AddressLiteral dst, Register src); | |
2339 void mov32(Register dst, AddressLiteral src); | |
304 | 2340 |
0 | 2341 // to avoid hiding movb |
2342 void movbyte(ArrayAddress dst, int src); | |
2343 | |
2344 // Can push value or effective address | |
2345 void pushptr(AddressLiteral src); | |
2346 | |
304 | 2347 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); } |
2348 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); } | |
2349 | |
2350 void pushoop(jobject obj); | |
2351 | |
2352 // sign extend as need a l to ptr sized element | |
2353 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); } | |
2354 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); } | |
2355 | |
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2356 // IndexOf strings. |
2320
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2357 // Small strings are loaded through stack if they cross page boundary. |
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2358 void string_indexof(Register str1, Register str2, |
2320
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2359 Register cnt1, Register cnt2, |
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2360 int int_cnt2, Register result, |
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2361 XMMRegister vec, Register tmp); |
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2362 |
2320
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2363 // IndexOf for constant substrings with size >= 8 elements |
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2364 // which don't need to be loaded through stack. |
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2365 void string_indexofC8(Register str1, Register str2, |
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2366 Register cnt1, Register cnt2, |
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2367 int int_cnt2, Register result, |
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2368 XMMRegister vec, Register tmp); |
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2369 |
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2370 // Smallest code: we don't need to load through stack, |
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2371 // check string tail. |
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2372 |
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2373 // Compare strings. |
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2374 void string_compare(Register str1, Register str2, |
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2375 Register cnt1, Register cnt2, Register result, |
2262 | 2376 XMMRegister vec1); |
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2377 |
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2378 // Compare char[] arrays. |
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2379 void char_arrays_equals(bool is_array_equ, Register ary1, Register ary2, |
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2380 Register limit, Register result, Register chr, |
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2381 XMMRegister vec1, XMMRegister vec2); |
304 | 2382 |
1763 | 2383 // Fill primitive arrays |
2384 void generate_fill(BasicType t, bool aligned, | |
2385 Register to, Register value, Register count, | |
2386 Register rtmp, XMMRegister xtmp); | |
2387 | |
0 | 2388 #undef VIRTUAL |
2389 | |
2390 }; | |
2391 | |
2392 /** | |
2393 * class SkipIfEqual: | |
2394 * | |
2395 * Instantiating this class will result in assembly code being output that will | |
2396 * jump around any code emitted between the creation of the instance and it's | |
2397 * automatic destruction at the end of a scope block, depending on the value of | |
2398 * the flag passed to the constructor, which will be checked at run-time. | |
2399 */ | |
2400 class SkipIfEqual { | |
2401 private: | |
2402 MacroAssembler* _masm; | |
2403 Label _label; | |
2404 | |
2405 public: | |
2406 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value); | |
2407 ~SkipIfEqual(); | |
2408 }; | |
2409 | |
2410 #ifdef ASSERT | |
2411 inline bool AbstractAssembler::pd_check_instruction_mark() { return true; } | |
2412 #endif | |
1972 | 2413 |
2414 #endif // CPU_X86_VM_ASSEMBLER_X86_HPP |