Mercurial > hg > graal-compiler
annotate src/os_cpu/windows_x86/vm/windows_x86_32.ad @ 1748:3e8fbc61cee8
6978355: renaming for 6961697
Summary: This is the renaming part of 6961697 to keep the actual changes small for review.
Reviewed-by: kvn, never
| author | twisti |
|---|---|
| date | Wed, 25 Aug 2010 05:27:54 -0700 |
| parents | c18cbe5936b8 |
| children | 9b8ce46870df |
| rev | line source |
|---|---|
| 0 | 1 // |
| 1748 | 2 // Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 // | |
| 5 // This code is free software; you can redistribute it and/or modify it | |
| 6 // under the terms of the GNU General Public License version 2 only, as | |
| 7 // published by the Free Software Foundation. | |
| 8 // | |
| 9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 // version 2 for more details (a copy is included in the LICENSE file that | |
| 13 // accompanied this code). | |
| 14 // | |
| 15 // You should have received a copy of the GNU General Public License version | |
| 16 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 // | |
|
1552
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
0
diff
changeset
|
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
|
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
0
diff
changeset
|
20 // or visit www.oracle.com if you need additional information or have any |
|
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
0
diff
changeset
|
21 // questions. |
| 0 | 22 // |
| 23 // | |
| 24 | |
| 25 // X86 Win32 Architecture Description File | |
| 26 | |
| 27 //----------OS-DEPENDENT ENCODING BLOCK----------------------------------------------------- | |
| 28 // This block specifies the encoding classes used by the compiler to output | |
| 29 // byte streams. Encoding classes generate functions which are called by | |
| 30 // Machine Instruction Nodes in order to generate the bit encoding of the | |
| 31 // instruction. Operands specify their base encoding interface with the | |
| 32 // interface keyword. There are currently supported four interfaces, | |
| 33 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an | |
| 34 // operand to generate a function which returns its register number when | |
| 35 // queried. CONST_INTER causes an operand to generate a function which | |
| 36 // returns the value of the constant when queried. MEMORY_INTER causes an | |
| 37 // operand to generate four functions which return the Base Register, the | |
| 38 // Index Register, the Scale Value, and the Offset Value of the operand when | |
| 39 // queried. COND_INTER causes an operand to generate six functions which | |
| 40 // return the encoding code (ie - encoding bits for the instruction) | |
| 41 // associated with each basic boolean condition for a conditional instruction. | |
| 42 // Instructions specify two basic values for encoding. They use the | |
| 43 // ins_encode keyword to specify their encoding class (which must be one of | |
| 44 // the class names specified in the encoding block), and they use the | |
| 45 // opcode keyword to specify, in order, their primary, secondary, and | |
| 46 // tertiary opcode. Only the opcode sections which a particular instruction | |
| 47 // needs for encoding need to be specified. | |
| 48 encode %{ | |
| 49 // Build emit functions for each basic byte or larger field in the intel | |
| 50 // encoding scheme (opcode, rm, sib, immediate), and call them from C++ | |
| 51 // code in the enc_class source block. Emit functions will live in the | |
| 52 // main source block for now. In future, we can generalize this by | |
| 53 // adding a syntax that specifies the sizes of fields in an order, | |
| 54 // so that the adlc can build the emit functions automagically | |
| 55 | |
| 56 enc_class tlsencode (eRegP dst, eRegP src) %{ | |
| 57 emit_rm(cbuf, 0x2, $dst$$reg, $src$$reg); | |
| 58 emit_d32(cbuf, ThreadLocalStorage::get_thread_ptr_offset() ); | |
| 59 %} | |
| 60 | |
| 61 enc_class call_epilog %{ | |
| 62 if( VerifyStackAtCalls ) { | |
| 63 // Check that stack depth is unchanged: find majik cookie on stack | |
| 64 int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP,-3*VMRegImpl::slots_per_word)); | |
| 65 if(framesize >= 128) { | |
| 66 emit_opcode(cbuf, 0x81); // cmp [esp+0],0xbadb1ood | |
| 67 emit_d8(cbuf,0xBC); | |
| 68 emit_d8(cbuf,0x24); | |
| 69 emit_d32(cbuf,framesize); // Find majik cookie from ESP | |
| 70 emit_d32(cbuf, 0xbadb100d); | |
| 71 } | |
| 72 else { | |
| 73 emit_opcode(cbuf, 0x81); // cmp [esp+0],0xbadb1ood | |
| 74 emit_d8(cbuf,0x7C); | |
| 75 emit_d8(cbuf,0x24); | |
| 76 emit_d8(cbuf,framesize); // Find majik cookie from ESP | |
| 77 emit_d32(cbuf, 0xbadb100d); | |
| 78 } | |
| 79 // jmp EQ around INT3 | |
| 80 emit_opcode(cbuf,0x74); | |
| 81 emit_d8(cbuf,1); | |
| 82 // Die if stack mismatch | |
| 83 emit_opcode(cbuf,0xCC); | |
| 84 } | |
| 85 %} | |
| 86 | |
| 87 %} | |
| 88 | |
| 89 // INSTRUCTIONS -- Platform dependent | |
| 90 | |
| 91 | |
| 92 //----------OS and Locking Instructions---------------------------------------- | |
| 93 | |
| 94 // The prefix of this name is KNOWN by the ADLC and cannot be changed. | |
| 95 instruct tlsLoadP_prefixLoadP(eRegP t1) %{ | |
| 96 effect(DEF t1); | |
| 97 | |
| 98 format %{ "MOV $t1,FS:[0x00] "%} | |
| 99 opcode(0x8B, 0x64); | |
| 100 ins_encode(OpcS, OpcP, conmemref(t1)); | |
| 101 ins_pipe( ialu_reg_fat ); | |
| 102 %} | |
| 103 | |
| 104 // This name is KNOWN by the ADLC and cannot be changed. | |
| 105 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type | |
| 106 // for this guy. | |
| 107 // %%% Should do this with a clause like: bottom_type(TypeRawPtr::BOTTOM); | |
| 108 instruct tlsLoadP(eRegP dst, eRegP t1) %{ | |
| 109 effect(DEF dst, USE t1); | |
| 110 | |
| 111 format %{ "MOV $dst,[$t1 + TLS::thread_ptr_offset()]" %} | |
| 112 opcode(0x8B); | |
| 113 ins_encode(OpcP, tlsencode(dst, t1)); | |
| 114 ins_pipe( ialu_reg_reg_fat ); | |
| 115 %} | |
| 116 | |
| 117 instruct TLS(eRegP dst) %{ | |
| 118 match(Set dst (ThreadLocal)); | |
| 119 expand %{ | |
| 120 eRegP t1; | |
| 121 tlsLoadP_prefixLoadP(t1); | |
| 122 tlsLoadP(dst, t1); | |
| 123 %} | |
| 124 %} | |
| 125 | |
| 126 // Die now | |
| 127 instruct ShouldNotReachHere( ) | |
| 128 %{ | |
| 129 match(Halt); | |
| 130 // Use the following format syntax | |
| 131 format %{ "INT3 ; ShouldNotReachHere" %} | |
| 132 opcode(0xCC); | |
| 133 ins_encode(OpcP); | |
| 134 ins_pipe( pipe_slow ); | |
| 135 %} | |
| 136 | |
| 137 // | |
| 138 // Platform dependent source | |
| 139 // | |
| 140 source %{ | |
| 141 | |
| 142 // emit an interrupt that is caught by the debugger | |
| 143 void emit_break(CodeBuffer &cbuf) { | |
| 1748 | 144 cbuf.insts()->emit_int8((unsigned char) 0xcc); |
| 0 | 145 } |
| 146 | |
| 147 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 148 emit_break(cbuf); | |
| 149 } | |
| 150 | |
| 151 | |
| 152 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { | |
| 153 return 1; | |
| 154 } | |
| 155 | |
| 156 | |
| 157 %} |