Mercurial > hg > graal-compiler
annotate src/cpu/x86/vm/assembler_x86_64.hpp @ 182:44abbb0d4c18
6709093: Compressed Oops: reduce size of compiled methods
Summary: exclude UEP size from nmethod code size and use narrow klass oop to load prototype header.
Reviewed-by: jrose, never
| author | kvn |
|---|---|
| date | Thu, 05 Jun 2008 13:02:51 -0700 |
| parents | 7793bd37a336 |
| children | d1605aabd0a1 6aae2f9d0294 |
| rev | line source |
|---|---|
| 0 | 1 /* |
| 2 * Copyright 2003-2007 Sun Microsystems, Inc. All Rights Reserved. | |
| 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
| 19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 20 * CA 95054 USA or visit www.sun.com if you need additional information or | |
| 21 * have any questions. | |
| 22 * | |
| 23 */ | |
| 24 | |
| 25 class BiasedLockingCounters; | |
| 26 | |
| 27 // Contains all the definitions needed for amd64 assembly code generation. | |
| 28 | |
| 29 #ifdef _LP64 | |
| 30 // Calling convention | |
| 31 class Argument VALUE_OBJ_CLASS_SPEC { | |
| 32 public: | |
| 33 enum { | |
| 34 #ifdef _WIN64 | |
| 35 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...) | |
| 36 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... ) | |
| 37 #else | |
| 38 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...) | |
| 39 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... ) | |
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40 #endif // _WIN64 |
| 0 | 41 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ... |
| 42 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ... | |
| 43 }; | |
| 44 }; | |
| 45 | |
| 46 | |
| 47 // Symbolically name the register arguments used by the c calling convention. | |
| 48 // Windows is different from linux/solaris. So much for standards... | |
| 49 | |
| 50 #ifdef _WIN64 | |
| 51 | |
| 52 REGISTER_DECLARATION(Register, c_rarg0, rcx); | |
| 53 REGISTER_DECLARATION(Register, c_rarg1, rdx); | |
| 54 REGISTER_DECLARATION(Register, c_rarg2, r8); | |
| 55 REGISTER_DECLARATION(Register, c_rarg3, r9); | |
| 56 | |
| 57 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); | |
| 58 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); | |
| 59 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); | |
| 60 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); | |
| 61 | |
| 62 #else | |
| 63 | |
| 64 REGISTER_DECLARATION(Register, c_rarg0, rdi); | |
| 65 REGISTER_DECLARATION(Register, c_rarg1, rsi); | |
| 66 REGISTER_DECLARATION(Register, c_rarg2, rdx); | |
| 67 REGISTER_DECLARATION(Register, c_rarg3, rcx); | |
| 68 REGISTER_DECLARATION(Register, c_rarg4, r8); | |
| 69 REGISTER_DECLARATION(Register, c_rarg5, r9); | |
| 70 | |
| 71 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); | |
| 72 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); | |
| 73 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); | |
| 74 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); | |
| 75 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4); | |
| 76 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5); | |
| 77 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6); | |
| 78 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7); | |
| 79 | |
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80 #endif // _WIN64 |
| 0 | 81 |
| 82 // Symbolically name the register arguments used by the Java calling convention. | |
| 83 // We have control over the convention for java so we can do what we please. | |
| 84 // What pleases us is to offset the java calling convention so that when | |
| 85 // we call a suitable jni method the arguments are lined up and we don't | |
| 86 // have to do little shuffling. A suitable jni method is non-static and a | |
| 87 // small number of arguments (two fewer args on windows) | |
| 88 // | |
| 89 // |-------------------------------------------------------| | |
| 90 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 | | |
| 91 // |-------------------------------------------------------| | |
| 92 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg) | |
| 93 // | rdi rsi rdx rcx r8 r9 | solaris/linux | |
| 94 // |-------------------------------------------------------| | |
| 95 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 | | |
| 96 // |-------------------------------------------------------| | |
| 97 | |
| 98 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1); | |
| 99 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2); | |
| 100 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3); | |
| 101 // Windows runs out of register args here | |
| 102 #ifdef _WIN64 | |
| 103 REGISTER_DECLARATION(Register, j_rarg3, rdi); | |
| 104 REGISTER_DECLARATION(Register, j_rarg4, rsi); | |
| 105 #else | |
| 106 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4); | |
| 107 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5); | |
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108 #endif // _WIN64 |
| 0 | 109 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0); |
| 110 | |
| 111 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0); | |
| 112 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1); | |
| 113 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2); | |
| 114 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3); | |
| 115 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4); | |
| 116 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5); | |
| 117 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6); | |
| 118 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7); | |
| 119 | |
| 120 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile | |
| 121 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile | |
| 122 | |
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123 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved |
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124 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved |
| 0 | 125 |
| 126 #endif // _LP64 | |
| 127 | |
| 128 // Address is an abstraction used to represent a memory location | |
| 129 // using any of the amd64 addressing modes with one object. | |
| 130 // | |
| 131 // Note: A register location is represented via a Register, not | |
| 132 // via an address for efficiency & simplicity reasons. | |
| 133 | |
| 134 class ArrayAddress; | |
| 135 | |
| 136 class Address VALUE_OBJ_CLASS_SPEC { | |
| 137 public: | |
| 138 enum ScaleFactor { | |
| 139 no_scale = -1, | |
| 140 times_1 = 0, | |
| 141 times_2 = 1, | |
| 142 times_4 = 2, | |
| 143 times_8 = 3 | |
| 144 }; | |
| 145 | |
| 146 private: | |
| 147 Register _base; | |
| 148 Register _index; | |
| 149 ScaleFactor _scale; | |
| 150 int _disp; | |
| 151 RelocationHolder _rspec; | |
| 152 | |
| 153 // Easily misused constructors make them private | |
| 154 Address(int disp, address loc, relocInfo::relocType rtype); | |
| 155 Address(int disp, address loc, RelocationHolder spec); | |
| 156 | |
| 157 public: | |
| 158 // creation | |
| 159 Address() | |
| 160 : _base(noreg), | |
| 161 _index(noreg), | |
| 162 _scale(no_scale), | |
| 163 _disp(0) { | |
| 164 } | |
| 165 | |
| 166 // No default displacement otherwise Register can be implicitly | |
| 167 // converted to 0(Register) which is quite a different animal. | |
| 168 | |
| 169 Address(Register base, int disp) | |
| 170 : _base(base), | |
| 171 _index(noreg), | |
| 172 _scale(no_scale), | |
| 173 _disp(disp) { | |
| 174 } | |
| 175 | |
| 176 Address(Register base, Register index, ScaleFactor scale, int disp = 0) | |
| 177 : _base (base), | |
| 178 _index(index), | |
| 179 _scale(scale), | |
| 180 _disp (disp) { | |
| 181 assert(!index->is_valid() == (scale == Address::no_scale), | |
| 182 "inconsistent address"); | |
| 183 } | |
| 184 | |
| 185 // The following two overloads are used in connection with the | |
| 186 // ByteSize type (see sizes.hpp). They simplify the use of | |
| 187 // ByteSize'd arguments in assembly code. Note that their equivalent | |
| 188 // for the optimized build are the member functions with int disp | |
| 189 // argument since ByteSize is mapped to an int type in that case. | |
| 190 // | |
| 191 // Note: DO NOT introduce similar overloaded functions for WordSize | |
| 192 // arguments as in the optimized mode, both ByteSize and WordSize | |
| 193 // are mapped to the same type and thus the compiler cannot make a | |
| 194 // distinction anymore (=> compiler errors). | |
| 195 | |
| 196 #ifdef ASSERT | |
| 197 Address(Register base, ByteSize disp) | |
| 198 : _base(base), | |
| 199 _index(noreg), | |
| 200 _scale(no_scale), | |
| 201 _disp(in_bytes(disp)) { | |
| 202 } | |
| 203 | |
| 204 Address(Register base, Register index, ScaleFactor scale, ByteSize disp) | |
| 205 : _base(base), | |
| 206 _index(index), | |
| 207 _scale(scale), | |
| 208 _disp(in_bytes(disp)) { | |
| 209 assert(!index->is_valid() == (scale == Address::no_scale), | |
| 210 "inconsistent address"); | |
| 211 } | |
| 212 #endif // ASSERT | |
| 213 | |
| 214 // accessors | |
| 215 bool uses(Register reg) const { | |
| 216 return _base == reg || _index == reg; | |
| 217 } | |
| 218 | |
| 219 // Convert the raw encoding form into the form expected by the constructor for | |
| 220 // Address. An index of 4 (rsp) corresponds to having no index, so convert | |
| 221 // that to noreg for the Address constructor. | |
| 222 static Address make_raw(int base, int index, int scale, int disp); | |
| 223 | |
| 224 static Address make_array(ArrayAddress); | |
| 225 | |
| 226 private: | |
| 227 bool base_needs_rex() const { | |
| 228 return _base != noreg && _base->encoding() >= 8; | |
| 229 } | |
| 230 | |
| 231 bool index_needs_rex() const { | |
| 232 return _index != noreg &&_index->encoding() >= 8; | |
| 233 } | |
| 234 | |
| 235 relocInfo::relocType reloc() const { return _rspec.type(); } | |
| 236 | |
| 237 friend class Assembler; | |
| 238 friend class MacroAssembler; | |
| 239 friend class LIR_Assembler; // base/index/scale/disp | |
| 240 }; | |
| 241 | |
| 242 // | |
| 243 // AddressLiteral has been split out from Address because operands of this type | |
| 244 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out | |
| 245 // the few instructions that need to deal with address literals are unique and the | |
| 246 // MacroAssembler does not have to implement every instruction in the Assembler | |
| 247 // in order to search for address literals that may need special handling depending | |
| 248 // on the instruction and the platform. As small step on the way to merging i486/amd64 | |
| 249 // directories. | |
| 250 // | |
| 251 class AddressLiteral VALUE_OBJ_CLASS_SPEC { | |
| 252 friend class ArrayAddress; | |
| 253 RelocationHolder _rspec; | |
| 254 // Typically we use AddressLiterals we want to use their rval | |
| 255 // However in some situations we want the lval (effect address) of the item. | |
| 256 // We provide a special factory for making those lvals. | |
| 257 bool _is_lval; | |
| 258 | |
| 259 // If the target is far we'll need to load the ea of this to | |
| 260 // a register to reach it. Otherwise if near we can do rip | |
| 261 // relative addressing. | |
| 262 | |
| 263 address _target; | |
| 264 | |
| 265 protected: | |
| 266 // creation | |
| 267 AddressLiteral() | |
| 268 : _is_lval(false), | |
| 269 _target(NULL) | |
| 270 {} | |
| 271 | |
| 272 public: | |
| 273 | |
| 274 | |
| 275 AddressLiteral(address target, relocInfo::relocType rtype); | |
| 276 | |
| 277 AddressLiteral(address target, RelocationHolder const& rspec) | |
| 278 : _rspec(rspec), | |
| 279 _is_lval(false), | |
| 280 _target(target) | |
| 281 {} | |
| 282 | |
| 283 AddressLiteral addr() { | |
| 284 AddressLiteral ret = *this; | |
| 285 ret._is_lval = true; | |
| 286 return ret; | |
| 287 } | |
| 288 | |
| 289 | |
| 290 private: | |
| 291 | |
| 292 address target() { return _target; } | |
| 293 bool is_lval() { return _is_lval; } | |
| 294 | |
| 295 relocInfo::relocType reloc() const { return _rspec.type(); } | |
| 296 const RelocationHolder& rspec() const { return _rspec; } | |
| 297 | |
| 298 friend class Assembler; | |
| 299 friend class MacroAssembler; | |
| 300 friend class Address; | |
| 301 friend class LIR_Assembler; | |
| 302 }; | |
| 303 | |
| 304 // Convience classes | |
| 305 class RuntimeAddress: public AddressLiteral { | |
| 306 | |
| 307 public: | |
| 308 | |
| 309 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {} | |
| 310 | |
| 311 }; | |
| 312 | |
| 313 class OopAddress: public AddressLiteral { | |
| 314 | |
| 315 public: | |
| 316 | |
| 317 OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){} | |
| 318 | |
| 319 }; | |
| 320 | |
| 321 class ExternalAddress: public AddressLiteral { | |
| 322 | |
| 323 public: | |
| 324 | |
| 325 ExternalAddress(address target) : AddressLiteral(target, relocInfo::external_word_type){} | |
| 326 | |
| 327 }; | |
| 328 | |
| 329 class InternalAddress: public AddressLiteral { | |
| 330 | |
| 331 public: | |
| 332 | |
| 333 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {} | |
| 334 | |
| 335 }; | |
| 336 | |
| 337 // x86 can do array addressing as a single operation since disp can be an absolute | |
| 338 // address but amd64 can't [e.g. array_base(rx, ry:width) ]. We create a class | |
| 339 // that expresses the concept but does extra magic on amd64 to get the final result | |
| 340 | |
| 341 class ArrayAddress VALUE_OBJ_CLASS_SPEC { | |
| 342 private: | |
| 343 | |
| 344 AddressLiteral _base; | |
| 345 Address _index; | |
| 346 | |
| 347 public: | |
| 348 | |
| 349 ArrayAddress() {}; | |
| 350 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {}; | |
| 351 AddressLiteral base() { return _base; } | |
| 352 Address index() { return _index; } | |
| 353 | |
| 354 }; | |
| 355 | |
| 356 // The amd64 Assembler: Pure assembler doing NO optimizations on | |
| 357 // the instruction level (e.g. mov rax, 0 is not translated into xor | |
| 358 // rax, rax!); i.e., what you write is what you get. The Assembler is | |
| 359 // generating code into a CodeBuffer. | |
| 360 | |
| 361 const int FPUStateSizeInWords = 512 / wordSize; | |
| 362 | |
| 363 class Assembler : public AbstractAssembler { | |
| 364 friend class AbstractAssembler; // for the non-virtual hack | |
| 365 friend class StubGenerator; | |
| 366 | |
| 367 | |
| 368 protected: | |
| 369 #ifdef ASSERT | |
| 370 void check_relocation(RelocationHolder const& rspec, int format); | |
| 371 #endif | |
| 372 | |
| 373 inline void emit_long64(jlong x); | |
| 374 | |
| 375 void emit_data(jint data, relocInfo::relocType rtype, int format /* = 1 */); | |
| 376 void emit_data(jint data, RelocationHolder const& rspec, int format /* = 1 */); | |
| 377 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0); | |
| 378 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0); | |
| 379 | |
| 380 // Helper functions for groups of instructions | |
| 381 void emit_arith_b(int op1, int op2, Register dst, int imm8); | |
| 382 | |
| 383 void emit_arith(int op1, int op2, Register dst, int imm32); | |
| 384 // only x86?? | |
| 385 void emit_arith(int op1, int op2, Register dst, jobject obj); | |
| 386 void emit_arith(int op1, int op2, Register dst, Register src); | |
| 387 | |
| 388 void emit_operand(Register reg, | |
| 389 Register base, Register index, Address::ScaleFactor scale, | |
| 390 int disp, | |
| 391 RelocationHolder const& rspec, | |
| 392 int rip_relative_correction = 0); | |
| 393 void emit_operand(Register reg, Address adr, | |
| 394 int rip_relative_correction = 0); | |
| 395 void emit_operand(XMMRegister reg, | |
| 396 Register base, Register index, Address::ScaleFactor scale, | |
| 397 int disp, | |
| 398 RelocationHolder const& rspec, | |
| 399 int rip_relative_correction = 0); | |
| 400 void emit_operand(XMMRegister reg, Address adr, | |
| 401 int rip_relative_correction = 0); | |
| 402 | |
| 403 // Immediate-to-memory forms | |
| 404 void emit_arith_operand(int op1, Register rm, Address adr, int imm32); | |
| 405 | |
| 406 void emit_farith(int b1, int b2, int i); | |
| 407 | |
| 408 bool reachable(AddressLiteral adr); | |
| 409 | |
| 410 // These are all easily abused and hence protected | |
| 411 | |
| 412 // Make these disappear in 64bit mode since they would never be correct | |
| 413 #ifndef _LP64 | |
| 414 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); | |
| 415 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); | |
| 416 | |
| 417 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); | |
| 418 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); | |
| 419 | |
| 420 void push_literal32(int32_t imm32, RelocationHolder const& rspec); | |
| 421 #endif // _LP64 | |
| 422 | |
| 423 | |
| 424 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); | |
| 425 | |
| 426 // These are unique in that we are ensured by the caller that the 32bit | |
| 427 // relative in these instructions will always be able to reach the potentially | |
| 428 // 64bit address described by entry. Since they can take a 64bit address they | |
| 429 // don't have the 32 suffix like the other instructions in this class. | |
| 430 void jmp_literal(address entry, RelocationHolder const& rspec); | |
| 431 void call_literal(address entry, RelocationHolder const& rspec); | |
| 432 | |
| 433 public: | |
| 434 enum Condition { // The amd64 condition codes used for conditional jumps/moves. | |
| 435 zero = 0x4, | |
| 436 notZero = 0x5, | |
| 437 equal = 0x4, | |
| 438 notEqual = 0x5, | |
| 439 less = 0xc, | |
| 440 lessEqual = 0xe, | |
| 441 greater = 0xf, | |
| 442 greaterEqual = 0xd, | |
| 443 below = 0x2, | |
| 444 belowEqual = 0x6, | |
| 445 above = 0x7, | |
| 446 aboveEqual = 0x3, | |
| 447 overflow = 0x0, | |
| 448 noOverflow = 0x1, | |
| 449 carrySet = 0x2, | |
| 450 carryClear = 0x3, | |
| 451 negative = 0x8, | |
| 452 positive = 0x9, | |
| 453 parity = 0xa, | |
| 454 noParity = 0xb | |
| 455 }; | |
| 456 | |
| 457 enum Prefix { | |
| 458 // segment overrides | |
| 459 // XXX remove segment prefixes | |
| 460 CS_segment = 0x2e, | |
| 461 SS_segment = 0x36, | |
| 462 DS_segment = 0x3e, | |
| 463 ES_segment = 0x26, | |
| 464 FS_segment = 0x64, | |
| 465 GS_segment = 0x65, | |
| 466 | |
| 467 REX = 0x40, | |
| 468 | |
| 469 REX_B = 0x41, | |
| 470 REX_X = 0x42, | |
| 471 REX_XB = 0x43, | |
| 472 REX_R = 0x44, | |
| 473 REX_RB = 0x45, | |
| 474 REX_RX = 0x46, | |
| 475 REX_RXB = 0x47, | |
| 476 | |
| 477 REX_W = 0x48, | |
| 478 | |
| 479 REX_WB = 0x49, | |
| 480 REX_WX = 0x4A, | |
| 481 REX_WXB = 0x4B, | |
| 482 REX_WR = 0x4C, | |
| 483 REX_WRB = 0x4D, | |
| 484 REX_WRX = 0x4E, | |
| 485 REX_WRXB = 0x4F | |
| 486 }; | |
| 487 | |
| 488 enum WhichOperand { | |
| 489 // input to locate_operand, and format code for relocations | |
| 490 imm64_operand = 0, // embedded 64-bit immediate operand | |
| 491 disp32_operand = 1, // embedded 32-bit displacement | |
| 492 call32_operand = 2, // embedded 32-bit self-relative displacement | |
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493 #ifndef AMD64 |
| 0 | 494 _WhichOperand_limit = 3 |
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495 #else |
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496 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop |
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497 _WhichOperand_limit = 4 |
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498 #endif |
| 0 | 499 }; |
| 500 | |
| 501 public: | |
| 502 | |
| 503 // Creation | |
| 504 Assembler(CodeBuffer* code) | |
| 505 : AbstractAssembler(code) { | |
| 506 } | |
| 507 | |
| 508 // Decoding | |
| 509 static address locate_operand(address inst, WhichOperand which); | |
| 510 static address locate_next_instruction(address inst); | |
| 511 | |
| 512 // Utilities | |
| 513 | |
| 514 static bool is_simm(int64_t x, int nbits) { return -( CONST64(1) << (nbits-1) ) <= x && x < ( CONST64(1) << (nbits-1) ); } | |
| 515 static bool is_simm32 (int64_t x) { return x == (int64_t)(int32_t)x; } | |
| 516 | |
| 517 | |
| 518 // Stack | |
| 519 void pushaq(); | |
| 520 void popaq(); | |
| 521 | |
| 522 void pushfq(); | |
| 523 void popfq(); | |
| 524 | |
| 525 void pushq(int imm32); | |
| 526 | |
| 527 void pushq(Register src); | |
| 528 void pushq(Address src); | |
| 529 | |
| 530 void popq(Register dst); | |
| 531 void popq(Address dst); | |
| 532 | |
| 533 // Instruction prefixes | |
| 534 void prefix(Prefix p); | |
| 535 | |
| 536 int prefix_and_encode(int reg_enc, bool byteinst = false); | |
| 537 int prefixq_and_encode(int reg_enc); | |
| 538 | |
| 539 int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false); | |
| 540 int prefixq_and_encode(int dst_enc, int src_enc); | |
| 541 | |
| 542 void prefix(Register reg); | |
| 543 void prefix(Address adr); | |
| 544 void prefixq(Address adr); | |
| 545 | |
| 546 void prefix(Address adr, Register reg, bool byteinst = false); | |
| 547 void prefixq(Address adr, Register reg); | |
| 548 | |
| 549 void prefix(Address adr, XMMRegister reg); | |
| 550 | |
| 551 // Moves | |
| 552 void movb(Register dst, Address src); | |
| 553 void movb(Address dst, int imm8); | |
| 554 void movb(Address dst, Register src); | |
| 555 | |
| 556 void movw(Address dst, int imm16); | |
| 557 void movw(Register dst, Address src); | |
| 558 void movw(Address dst, Register src); | |
| 559 | |
| 560 void movl(Register dst, int imm32); | |
| 561 void movl(Register dst, Register src); | |
| 562 void movl(Register dst, Address src); | |
| 563 void movl(Address dst, int imm32); | |
| 564 void movl(Address dst, Register src); | |
| 565 | |
| 566 void movq(Register dst, Register src); | |
| 567 void movq(Register dst, Address src); | |
| 568 void movq(Address dst, Register src); | |
| 569 // These prevent using movq from converting a zero (like NULL) into Register | |
| 570 // by giving the compiler two choices it can't resolve | |
| 571 void movq(Address dst, void* dummy); | |
| 572 void movq(Register dst, void* dummy); | |
| 573 | |
| 574 void mov64(Register dst, intptr_t imm64); | |
| 575 void mov64(Address dst, intptr_t imm64); | |
| 576 | |
| 577 void movsbl(Register dst, Address src); | |
| 578 void movsbl(Register dst, Register src); | |
| 579 void movswl(Register dst, Address src); | |
| 580 void movswl(Register dst, Register src); | |
| 581 void movslq(Register dst, Address src); | |
| 582 void movslq(Register dst, Register src); | |
| 583 | |
| 584 void movzbl(Register dst, Address src); | |
| 585 void movzbl(Register dst, Register src); | |
| 586 void movzwl(Register dst, Address src); | |
| 587 void movzwl(Register dst, Register src); | |
| 588 | |
| 589 protected: // Avoid using the next instructions directly. | |
| 590 // New cpus require use of movsd and movss to avoid partial register stall | |
| 591 // when loading from memory. But for old Opteron use movlpd instead of movsd. | |
| 592 // The selection is done in MacroAssembler::movdbl() and movflt(). | |
| 593 void movss(XMMRegister dst, XMMRegister src); | |
| 594 void movss(XMMRegister dst, Address src); | |
| 595 void movss(Address dst, XMMRegister src); | |
| 596 void movsd(XMMRegister dst, XMMRegister src); | |
| 597 void movsd(Address dst, XMMRegister src); | |
| 598 void movsd(XMMRegister dst, Address src); | |
| 599 void movlpd(XMMRegister dst, Address src); | |
| 600 // New cpus require use of movaps and movapd to avoid partial register stall | |
| 601 // when moving between registers. | |
| 602 void movapd(XMMRegister dst, XMMRegister src); | |
| 603 void movaps(XMMRegister dst, XMMRegister src); | |
| 604 public: | |
| 605 | |
| 606 void movdl(XMMRegister dst, Register src); | |
| 607 void movdl(Register dst, XMMRegister src); | |
| 608 void movdq(XMMRegister dst, Register src); | |
| 609 void movdq(Register dst, XMMRegister src); | |
| 610 | |
| 611 void cmovl(Condition cc, Register dst, Register src); | |
| 612 void cmovl(Condition cc, Register dst, Address src); | |
| 613 void cmovq(Condition cc, Register dst, Register src); | |
| 614 void cmovq(Condition cc, Register dst, Address src); | |
| 615 | |
| 616 // Prefetches | |
| 617 private: | |
| 618 void prefetch_prefix(Address src); | |
| 619 public: | |
| 620 void prefetcht0(Address src); | |
| 621 void prefetcht1(Address src); | |
| 622 void prefetcht2(Address src); | |
| 623 void prefetchnta(Address src); | |
| 624 void prefetchw(Address src); | |
| 625 | |
| 626 // Arithmetics | |
| 627 void adcl(Register dst, int imm32); | |
| 628 void adcl(Register dst, Address src); | |
| 629 void adcl(Register dst, Register src); | |
| 630 void adcq(Register dst, int imm32); | |
| 631 void adcq(Register dst, Address src); | |
| 632 void adcq(Register dst, Register src); | |
| 633 | |
| 634 void addl(Address dst, int imm32); | |
| 635 void addl(Address dst, Register src); | |
| 636 void addl(Register dst, int imm32); | |
| 637 void addl(Register dst, Address src); | |
| 638 void addl(Register dst, Register src); | |
| 639 void addq(Address dst, int imm32); | |
| 640 void addq(Address dst, Register src); | |
| 641 void addq(Register dst, int imm32); | |
| 642 void addq(Register dst, Address src); | |
| 643 void addq(Register dst, Register src); | |
| 644 | |
| 645 void andl(Register dst, int imm32); | |
| 646 void andl(Register dst, Address src); | |
| 647 void andl(Register dst, Register src); | |
| 648 void andq(Register dst, int imm32); | |
| 649 void andq(Register dst, Address src); | |
| 650 void andq(Register dst, Register src); | |
| 651 | |
| 652 void cmpb(Address dst, int imm8); | |
| 653 void cmpl(Address dst, int imm32); | |
| 654 void cmpl(Register dst, int imm32); | |
| 655 void cmpl(Register dst, Register src); | |
| 656 void cmpl(Register dst, Address src); | |
| 657 void cmpq(Address dst, int imm32); | |
| 658 void cmpq(Address dst, Register src); | |
| 659 void cmpq(Register dst, int imm32); | |
| 660 void cmpq(Register dst, Register src); | |
| 661 void cmpq(Register dst, Address src); | |
| 662 | |
| 663 void ucomiss(XMMRegister dst, XMMRegister src); | |
| 664 void ucomisd(XMMRegister dst, XMMRegister src); | |
| 665 | |
| 666 protected: | |
| 667 // Don't use next inc() and dec() methods directly. INC & DEC instructions | |
| 668 // could cause a partial flag stall since they don't set CF flag. | |
| 669 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods | |
| 670 // which call inc() & dec() or add() & sub() in accordance with | |
| 671 // the product flag UseIncDec value. | |
| 672 | |
| 673 void decl(Register dst); | |
| 674 void decl(Address dst); | |
| 675 void decq(Register dst); | |
| 676 void decq(Address dst); | |
| 677 | |
| 678 void incl(Register dst); | |
| 679 void incl(Address dst); | |
| 680 void incq(Register dst); | |
| 681 void incq(Address dst); | |
| 682 | |
| 683 public: | |
| 684 void idivl(Register src); | |
| 685 void idivq(Register src); | |
| 686 void cdql(); | |
| 687 void cdqq(); | |
| 688 | |
| 689 void imull(Register dst, Register src); | |
| 690 void imull(Register dst, Register src, int value); | |
| 691 void imulq(Register dst, Register src); | |
| 692 void imulq(Register dst, Register src, int value); | |
| 693 | |
| 694 void leal(Register dst, Address src); | |
| 695 void leaq(Register dst, Address src); | |
| 696 | |
| 697 void mull(Address src); | |
| 698 void mull(Register src); | |
| 699 | |
| 700 void negl(Register dst); | |
| 701 void negq(Register dst); | |
| 702 | |
| 703 void notl(Register dst); | |
| 704 void notq(Register dst); | |
| 705 | |
| 706 void orl(Address dst, int imm32); | |
| 707 void orl(Register dst, int imm32); | |
| 708 void orl(Register dst, Address src); | |
| 709 void orl(Register dst, Register src); | |
| 710 void orq(Address dst, int imm32); | |
| 711 void orq(Register dst, int imm32); | |
| 712 void orq(Register dst, Address src); | |
| 713 void orq(Register dst, Register src); | |
| 714 | |
| 715 void rcll(Register dst, int imm8); | |
| 716 void rclq(Register dst, int imm8); | |
| 717 | |
| 718 void sarl(Register dst, int imm8); | |
| 719 void sarl(Register dst); | |
| 720 void sarq(Register dst, int imm8); | |
| 721 void sarq(Register dst); | |
| 722 | |
| 723 void sbbl(Address dst, int imm32); | |
| 724 void sbbl(Register dst, int imm32); | |
| 725 void sbbl(Register dst, Address src); | |
| 726 void sbbl(Register dst, Register src); | |
| 727 void sbbq(Address dst, int imm32); | |
| 728 void sbbq(Register dst, int imm32); | |
| 729 void sbbq(Register dst, Address src); | |
| 730 void sbbq(Register dst, Register src); | |
| 731 | |
| 732 void shll(Register dst, int imm8); | |
| 733 void shll(Register dst); | |
| 734 void shlq(Register dst, int imm8); | |
| 735 void shlq(Register dst); | |
| 736 | |
| 737 void shrl(Register dst, int imm8); | |
| 738 void shrl(Register dst); | |
| 739 void shrq(Register dst, int imm8); | |
| 740 void shrq(Register dst); | |
| 741 | |
| 742 void subl(Address dst, int imm32); | |
| 743 void subl(Address dst, Register src); | |
| 744 void subl(Register dst, int imm32); | |
| 745 void subl(Register dst, Address src); | |
| 746 void subl(Register dst, Register src); | |
| 747 void subq(Address dst, int imm32); | |
| 748 void subq(Address dst, Register src); | |
| 749 void subq(Register dst, int imm32); | |
| 750 void subq(Register dst, Address src); | |
| 751 void subq(Register dst, Register src); | |
| 752 | |
| 753 void testb(Register dst, int imm8); | |
| 754 void testl(Register dst, int imm32); | |
| 755 void testl(Register dst, Register src); | |
| 756 void testq(Register dst, int imm32); | |
| 757 void testq(Register dst, Register src); | |
| 758 | |
| 759 void xaddl(Address dst, Register src); | |
| 760 void xaddq(Address dst, Register src); | |
| 761 | |
| 762 void xorl(Register dst, int imm32); | |
| 763 void xorl(Register dst, Address src); | |
| 764 void xorl(Register dst, Register src); | |
| 765 void xorq(Register dst, int imm32); | |
| 766 void xorq(Register dst, Address src); | |
| 767 void xorq(Register dst, Register src); | |
| 768 | |
| 769 // Miscellaneous | |
| 770 void bswapl(Register reg); | |
| 771 void bswapq(Register reg); | |
| 772 void lock(); | |
| 773 | |
| 774 void xchgl(Register reg, Address adr); | |
| 775 void xchgl(Register dst, Register src); | |
| 776 void xchgq(Register reg, Address adr); | |
| 777 void xchgq(Register dst, Register src); | |
| 778 | |
| 779 void cmpxchgl(Register reg, Address adr); | |
| 780 void cmpxchgq(Register reg, Address adr); | |
| 781 | |
| 782 void nop(int i = 1); | |
| 783 void addr_nop_4(); | |
| 784 void addr_nop_5(); | |
| 785 void addr_nop_7(); | |
| 786 void addr_nop_8(); | |
| 787 | |
| 788 void hlt(); | |
| 789 void ret(int imm16); | |
| 790 void smovl(); | |
| 791 void rep_movl(); | |
| 792 void rep_movq(); | |
| 793 void rep_set(); | |
|
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794 void repne_scanl(); |
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|
795 void repne_scanq(); |
| 0 | 796 void setb(Condition cc, Register dst); |
| 797 | |
| 798 void clflush(Address adr); | |
| 799 | |
| 800 enum Membar_mask_bits { | |
| 801 StoreStore = 1 << 3, | |
| 802 LoadStore = 1 << 2, | |
| 803 StoreLoad = 1 << 1, | |
| 804 LoadLoad = 1 << 0 | |
| 805 }; | |
| 806 | |
| 807 // Serializes memory. | |
| 808 void membar(Membar_mask_bits order_constraint) { | |
| 809 // We only have to handle StoreLoad and LoadLoad | |
| 810 if (order_constraint & StoreLoad) { | |
| 811 // MFENCE subsumes LFENCE | |
| 812 mfence(); | |
| 813 } /* [jk] not needed currently: else if (order_constraint & LoadLoad) { | |
| 814 lfence(); | |
| 815 } */ | |
| 816 } | |
| 817 | |
| 818 void lfence() { | |
| 819 emit_byte(0x0F); | |
| 820 emit_byte(0xAE); | |
| 821 emit_byte(0xE8); | |
| 822 } | |
| 823 | |
| 824 void mfence() { | |
| 825 emit_byte(0x0F); | |
| 826 emit_byte(0xAE); | |
| 827 emit_byte(0xF0); | |
| 828 } | |
| 829 | |
| 830 // Identify processor type and features | |
| 831 void cpuid() { | |
| 832 emit_byte(0x0F); | |
| 833 emit_byte(0xA2); | |
| 834 } | |
| 835 | |
| 836 void cld() { emit_byte(0xfc); | |
| 837 } | |
| 838 | |
| 839 void std() { emit_byte(0xfd); | |
| 840 } | |
| 841 | |
| 842 | |
| 843 // Calls | |
| 844 | |
| 845 void call(Label& L, relocInfo::relocType rtype); | |
| 846 void call(Register reg); | |
| 847 void call(Address adr); | |
| 848 | |
| 849 // Jumps | |
| 850 | |
| 851 void jmp(Register reg); | |
| 852 void jmp(Address adr); | |
| 853 | |
| 854 // Label operations & relative jumps (PPUM Appendix D) | |
| 855 // unconditional jump to L | |
| 856 void jmp(Label& L, relocInfo::relocType rtype = relocInfo::none); | |
| 857 | |
| 858 | |
| 859 // Unconditional 8-bit offset jump to L. | |
| 860 // WARNING: be very careful using this for forward jumps. If the label is | |
| 861 // not bound within an 8-bit offset of this instruction, a run-time error | |
| 862 // will occur. | |
| 863 void jmpb(Label& L); | |
| 864 | |
| 865 // jcc is the generic conditional branch generator to run- time | |
| 866 // routines, jcc is used for branches to labels. jcc takes a branch | |
| 867 // opcode (cc) and a label (L) and generates either a backward | |
| 868 // branch or a forward branch and links it to the label fixup | |
| 869 // chain. Usage: | |
| 870 // | |
| 871 // Label L; // unbound label | |
| 872 // jcc(cc, L); // forward branch to unbound label | |
| 873 // bind(L); // bind label to the current pc | |
| 874 // jcc(cc, L); // backward branch to bound label | |
| 875 // bind(L); // illegal: a label may be bound only once | |
| 876 // | |
| 877 // Note: The same Label can be used for forward and backward branches | |
| 878 // but it may be bound only once. | |
| 879 | |
| 880 void jcc(Condition cc, Label& L, | |
| 881 relocInfo::relocType rtype = relocInfo::none); | |
| 882 | |
| 883 // Conditional jump to a 8-bit offset to L. | |
| 884 // WARNING: be very careful using this for forward jumps. If the label is | |
| 885 // not bound within an 8-bit offset of this instruction, a run-time error | |
| 886 // will occur. | |
| 887 void jccb(Condition cc, Label& L); | |
| 888 | |
| 889 // Floating-point operations | |
| 890 | |
| 891 void fxsave(Address dst); | |
| 892 void fxrstor(Address src); | |
| 893 void ldmxcsr(Address src); | |
| 894 void stmxcsr(Address dst); | |
| 895 | |
| 896 void addss(XMMRegister dst, XMMRegister src); | |
| 897 void addss(XMMRegister dst, Address src); | |
| 898 void subss(XMMRegister dst, XMMRegister src); | |
| 899 void subss(XMMRegister dst, Address src); | |
| 900 void mulss(XMMRegister dst, XMMRegister src); | |
| 901 void mulss(XMMRegister dst, Address src); | |
| 902 void divss(XMMRegister dst, XMMRegister src); | |
| 903 void divss(XMMRegister dst, Address src); | |
| 904 void addsd(XMMRegister dst, XMMRegister src); | |
| 905 void addsd(XMMRegister dst, Address src); | |
| 906 void subsd(XMMRegister dst, XMMRegister src); | |
| 907 void subsd(XMMRegister dst, Address src); | |
| 908 void mulsd(XMMRegister dst, XMMRegister src); | |
| 909 void mulsd(XMMRegister dst, Address src); | |
| 910 void divsd(XMMRegister dst, XMMRegister src); | |
| 911 void divsd(XMMRegister dst, Address src); | |
| 912 | |
| 913 // We only need the double form | |
| 914 void sqrtsd(XMMRegister dst, XMMRegister src); | |
| 915 void sqrtsd(XMMRegister dst, Address src); | |
| 916 | |
| 917 void xorps(XMMRegister dst, XMMRegister src); | |
| 918 void xorps(XMMRegister dst, Address src); | |
| 919 void xorpd(XMMRegister dst, XMMRegister src); | |
| 920 void xorpd(XMMRegister dst, Address src); | |
| 921 | |
| 922 void cvtsi2ssl(XMMRegister dst, Register src); | |
| 923 void cvtsi2ssq(XMMRegister dst, Register src); | |
| 924 void cvtsi2sdl(XMMRegister dst, Register src); | |
| 925 void cvtsi2sdq(XMMRegister dst, Register src); | |
| 926 void cvttss2sil(Register dst, XMMRegister src); // truncates | |
| 927 void cvttss2siq(Register dst, XMMRegister src); // truncates | |
| 928 void cvttsd2sil(Register dst, XMMRegister src); // truncates | |
| 929 void cvttsd2siq(Register dst, XMMRegister src); // truncates | |
| 930 void cvtss2sd(XMMRegister dst, XMMRegister src); | |
| 931 void cvtsd2ss(XMMRegister dst, XMMRegister src); | |
| 71 | 932 void cvtdq2pd(XMMRegister dst, XMMRegister src); |
| 933 void cvtdq2ps(XMMRegister dst, XMMRegister src); | |
| 0 | 934 |
| 935 void pxor(XMMRegister dst, Address src); // Xor Packed Byte Integer Values | |
| 936 void pxor(XMMRegister dst, XMMRegister src); // Xor Packed Byte Integer Values | |
| 937 | |
| 938 void movdqa(XMMRegister dst, Address src); // Move Aligned Double Quadword | |
| 939 void movdqa(XMMRegister dst, XMMRegister src); | |
| 940 void movdqa(Address dst, XMMRegister src); | |
| 941 | |
| 942 void movq(XMMRegister dst, Address src); | |
| 943 void movq(Address dst, XMMRegister src); | |
| 944 | |
| 945 void pshufd(XMMRegister dst, XMMRegister src, int mode); // Shuffle Packed Doublewords | |
| 946 void pshufd(XMMRegister dst, Address src, int mode); | |
| 947 void pshuflw(XMMRegister dst, XMMRegister src, int mode); // Shuffle Packed Low Words | |
| 948 void pshuflw(XMMRegister dst, Address src, int mode); | |
| 949 | |
| 950 void psrlq(XMMRegister dst, int shift); // Shift Right Logical Quadword Immediate | |
| 951 | |
| 952 void punpcklbw(XMMRegister dst, XMMRegister src); // Interleave Low Bytes | |
| 953 void punpcklbw(XMMRegister dst, Address src); | |
| 954 }; | |
| 955 | |
| 956 | |
| 957 // MacroAssembler extends Assembler by frequently used macros. | |
| 958 // | |
| 959 // Instructions for which a 'better' code sequence exists depending | |
| 960 // on arguments should also go in here. | |
| 961 | |
| 962 class MacroAssembler : public Assembler { | |
| 963 friend class LIR_Assembler; | |
| 964 protected: | |
| 965 | |
| 966 Address as_Address(AddressLiteral adr); | |
| 967 Address as_Address(ArrayAddress adr); | |
| 968 | |
| 969 // Support for VM calls | |
| 970 // | |
| 971 // This is the base routine called by the different versions of | |
| 972 // call_VM_leaf. The interpreter may customize this version by | |
| 973 // overriding it for its purposes (e.g., to save/restore additional | |
| 974 // registers when doing a VM call). | |
| 975 | |
| 976 virtual void call_VM_leaf_base( | |
| 977 address entry_point, // the entry point | |
| 978 int number_of_arguments // the number of arguments to | |
| 979 // pop after the call | |
| 980 ); | |
| 981 | |
| 982 // This is the base routine called by the different versions of | |
| 983 // call_VM. The interpreter may customize this version by overriding | |
| 984 // it for its purposes (e.g., to save/restore additional registers | |
| 985 // when doing a VM call). | |
| 986 // | |
| 987 // If no java_thread register is specified (noreg) than rdi will be | |
| 988 // used instead. call_VM_base returns the register which contains | |
| 989 // the thread upon return. If a thread register has been specified, | |
| 990 // the return value will correspond to that register. If no | |
| 991 // last_java_sp is specified (noreg) than rsp will be used instead. | |
| 992 virtual void call_VM_base( // returns the register | |
| 993 // containing the thread upon | |
| 994 // return | |
| 995 Register oop_result, // where an oop-result ends up | |
| 996 // if any; use noreg otherwise | |
| 997 Register java_thread, // the thread if computed | |
| 998 // before ; use noreg otherwise | |
| 999 Register last_java_sp, // to set up last_Java_frame in | |
| 1000 // stubs; use noreg otherwise | |
| 1001 address entry_point, // the entry point | |
| 1002 int number_of_arguments, // the number of arguments (w/o | |
| 1003 // thread) to pop after the | |
| 1004 // call | |
| 1005 bool check_exceptions // whether to check for pending | |
| 1006 // exceptions after return | |
| 1007 ); | |
| 1008 | |
| 1009 // This routines should emit JVMTI PopFrame handling and ForceEarlyReturn code. | |
| 1010 // The implementation is only non-empty for the InterpreterMacroAssembler, | |
| 1011 // as only the interpreter handles PopFrame and ForceEarlyReturn requests. | |
| 1012 virtual void check_and_handle_popframe(Register java_thread); | |
| 1013 virtual void check_and_handle_earlyret(Register java_thread); | |
| 1014 | |
| 1015 void call_VM_helper(Register oop_result, | |
| 1016 address entry_point, | |
| 1017 int number_of_arguments, | |
| 1018 bool check_exceptions = true); | |
| 1019 | |
| 1020 public: | |
| 1021 MacroAssembler(CodeBuffer* code) : Assembler(code) {} | |
| 1022 | |
| 1023 // Support for NULL-checks | |
| 1024 // | |
| 1025 // Generates code that causes a NULL OS exception if the content of | |
| 1026 // reg is NULL. If the accessed location is M[reg + offset] and the | |
| 1027 // offset is known, provide the offset. No explicit code generation | |
| 1028 // is needed if the offset is within a certain range (0 <= offset <= | |
| 1029 // page_size). | |
| 1030 void null_check(Register reg, int offset = -1); | |
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1031 static bool needs_explicit_null_check(intptr_t offset); |
| 0 | 1032 |
| 1033 // Required platform-specific helpers for Label::patch_instructions. | |
| 1034 // They _shadow_ the declarations in AbstractAssembler, which are undefined. | |
| 1035 void pd_patch_instruction(address branch, address target); | |
| 1036 #ifndef PRODUCT | |
| 1037 static void pd_print_patched_instruction(address branch); | |
| 1038 #endif | |
| 1039 | |
| 1040 | |
| 1041 // The following 4 methods return the offset of the appropriate move | |
| 1042 // instruction. Note: these are 32 bit instructions | |
| 1043 | |
| 1044 // Support for fast byte/word loading with zero extension (depending | |
| 1045 // on particular CPU) | |
| 1046 int load_unsigned_byte(Register dst, Address src); | |
| 1047 int load_unsigned_word(Register dst, Address src); | |
| 1048 | |
| 1049 // Support for fast byte/word loading with sign extension (depending | |
| 1050 // on particular CPU) | |
| 1051 int load_signed_byte(Register dst, Address src); | |
| 1052 int load_signed_word(Register dst, Address src); | |
| 1053 | |
| 1054 // Support for inc/dec with optimal instruction selection depending | |
| 1055 // on value | |
| 1056 void incrementl(Register reg, int value = 1); | |
| 1057 void decrementl(Register reg, int value = 1); | |
| 1058 void incrementq(Register reg, int value = 1); | |
| 1059 void decrementq(Register reg, int value = 1); | |
| 1060 | |
| 1061 void incrementl(Address dst, int value = 1); | |
| 1062 void decrementl(Address dst, int value = 1); | |
| 1063 void incrementq(Address dst, int value = 1); | |
| 1064 void decrementq(Address dst, int value = 1); | |
| 1065 | |
| 1066 // Support optimal SSE move instructions. | |
| 1067 void movflt(XMMRegister dst, XMMRegister src) { | |
| 1068 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; } | |
| 1069 else { movss (dst, src); return; } | |
| 1070 } | |
| 1071 | |
| 1072 void movflt(XMMRegister dst, Address src) { movss(dst, src); } | |
| 1073 | |
| 1074 void movflt(XMMRegister dst, AddressLiteral src); | |
| 1075 | |
| 1076 void movflt(Address dst, XMMRegister src) { movss(dst, src); } | |
| 1077 | |
| 1078 void movdbl(XMMRegister dst, XMMRegister src) { | |
| 1079 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; } | |
| 1080 else { movsd (dst, src); return; } | |
| 1081 } | |
| 1082 | |
| 1083 void movdbl(XMMRegister dst, AddressLiteral src); | |
| 1084 | |
| 1085 void movdbl(XMMRegister dst, Address src) { | |
| 1086 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; } | |
| 1087 else { movlpd(dst, src); return; } | |
| 1088 } | |
| 1089 | |
| 1090 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); } | |
| 1091 | |
| 1092 void incrementl(AddressLiteral dst); | |
| 1093 void incrementl(ArrayAddress dst); | |
| 1094 | |
| 1095 // Alignment | |
| 1096 void align(int modulus); | |
| 1097 | |
| 1098 // Misc | |
| 1099 void fat_nop(); // 5 byte nop | |
| 1100 | |
| 1101 | |
| 1102 // C++ bool manipulation | |
| 1103 | |
| 1104 void movbool(Register dst, Address src); | |
| 1105 void movbool(Address dst, bool boolconst); | |
| 1106 void movbool(Address dst, Register src); | |
| 1107 void testbool(Register dst); | |
| 1108 | |
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1109 // oop manipulations |
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1110 void load_klass(Register dst, Register src); |
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1111 void store_klass(Register dst, Register src); |
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1112 void store_klass_gap(Register dst, Register src); |
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1113 |
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1114 void load_prototype_header(Register dst, Register src); |
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1115 |
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1116 void load_heap_oop(Register dst, Address src); |
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1117 void store_heap_oop(Address dst, Register src); |
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1118 void encode_heap_oop(Register r); |
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1119 void decode_heap_oop(Register r); |
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1120 void encode_heap_oop_not_null(Register r); |
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1121 void decode_heap_oop_not_null(Register r); |
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1122 void encode_heap_oop_not_null(Register dst, Register src); |
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1123 void decode_heap_oop_not_null(Register dst, Register src); |
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1125 void set_narrow_oop(Register dst, jobject obj); |
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1126 |
| 0 | 1127 // Stack frame creation/removal |
| 1128 void enter(); | |
| 1129 void leave(); | |
| 1130 | |
| 1131 // Support for getting the JavaThread pointer (i.e.; a reference to | |
| 1132 // thread-local information) The pointer will be loaded into the | |
| 1133 // thread register. | |
| 1134 void get_thread(Register thread); | |
| 1135 | |
| 1136 void int3(); | |
| 1137 | |
| 1138 // Support for VM calls | |
| 1139 // | |
| 1140 // It is imperative that all calls into the VM are handled via the | |
| 1141 // call_VM macros. They make sure that the stack linkage is setup | |
| 1142 // correctly. call_VM's correspond to ENTRY/ENTRY_X entry points | |
| 1143 // while call_VM_leaf's correspond to LEAF entry points. | |
| 1144 void call_VM(Register oop_result, | |
| 1145 address entry_point, | |
| 1146 bool check_exceptions = true); | |
| 1147 void call_VM(Register oop_result, | |
| 1148 address entry_point, | |
| 1149 Register arg_1, | |
| 1150 bool check_exceptions = true); | |
| 1151 void call_VM(Register oop_result, | |
| 1152 address entry_point, | |
| 1153 Register arg_1, Register arg_2, | |
| 1154 bool check_exceptions = true); | |
| 1155 void call_VM(Register oop_result, | |
| 1156 address entry_point, | |
| 1157 Register arg_1, Register arg_2, Register arg_3, | |
| 1158 bool check_exceptions = true); | |
| 1159 | |
| 1160 // Overloadings with last_Java_sp | |
| 1161 void call_VM(Register oop_result, | |
| 1162 Register last_java_sp, | |
| 1163 address entry_point, | |
| 1164 int number_of_arguments = 0, | |
| 1165 bool check_exceptions = true); | |
| 1166 void call_VM(Register oop_result, | |
| 1167 Register last_java_sp, | |
| 1168 address entry_point, | |
| 1169 Register arg_1, bool | |
| 1170 check_exceptions = true); | |
| 1171 void call_VM(Register oop_result, | |
| 1172 Register last_java_sp, | |
| 1173 address entry_point, | |
| 1174 Register arg_1, Register arg_2, | |
| 1175 bool check_exceptions = true); | |
| 1176 void call_VM(Register oop_result, | |
| 1177 Register last_java_sp, | |
| 1178 address entry_point, | |
| 1179 Register arg_1, Register arg_2, Register arg_3, | |
| 1180 bool check_exceptions = true); | |
| 1181 | |
| 1182 void call_VM_leaf(address entry_point, | |
| 1183 int number_of_arguments = 0); | |
| 1184 void call_VM_leaf(address entry_point, | |
| 1185 Register arg_1); | |
| 1186 void call_VM_leaf(address entry_point, | |
| 1187 Register arg_1, Register arg_2); | |
| 1188 void call_VM_leaf(address entry_point, | |
| 1189 Register arg_1, Register arg_2, Register arg_3); | |
| 1190 | |
| 1191 // last Java Frame (fills frame anchor) | |
| 1192 void set_last_Java_frame(Register last_java_sp, | |
| 1193 Register last_java_fp, | |
| 1194 address last_java_pc); | |
| 1195 void reset_last_Java_frame(bool clear_fp, bool clear_pc); | |
| 1196 | |
| 1197 // Stores | |
| 1198 void store_check(Register obj); // store check for | |
| 1199 // obj - register is | |
| 1200 // destroyed | |
| 1201 // afterwards | |
| 1202 void store_check(Register obj, Address dst); // same as above, dst | |
| 1203 // is exact store | |
| 1204 // location (reg. is | |
| 1205 // destroyed) | |
| 1206 | |
| 1207 // split store_check(Register obj) to enhance instruction interleaving | |
| 1208 void store_check_part_1(Register obj); | |
| 1209 void store_check_part_2(Register obj); | |
| 1210 | |
| 1211 // C 'boolean' to Java boolean: x == 0 ? 0 : 1 | |
| 1212 void c2bool(Register x); | |
| 1213 | |
| 1214 // Int division/reminder for Java | |
| 1215 // (as idivl, but checks for special case as described in JVM spec.) | |
| 1216 // returns idivl instruction offset for implicit exception handling | |
| 1217 int corrected_idivl(Register reg); | |
| 1218 // Long division/reminder for Java | |
| 1219 // (as idivq, but checks for special case as described in JVM spec.) | |
| 1220 // returns idivq instruction offset for implicit exception handling | |
| 1221 int corrected_idivq(Register reg); | |
| 1222 | |
| 1223 // Push and pop integer/fpu/cpu state | |
| 1224 void push_IU_state(); | |
| 1225 void pop_IU_state(); | |
| 1226 | |
| 1227 void push_FPU_state(); | |
| 1228 void pop_FPU_state(); | |
| 1229 | |
| 1230 void push_CPU_state(); | |
| 1231 void pop_CPU_state(); | |
| 1232 | |
| 1233 // Sign extension | |
| 1234 void sign_extend_short(Register reg); | |
| 1235 void sign_extend_byte(Register reg); | |
| 1236 | |
| 1237 // Division by power of 2, rounding towards 0 | |
| 1238 void division_with_shift(Register reg, int shift_value); | |
| 1239 | |
| 1240 // Round up to a power of two | |
| 1241 void round_to_l(Register reg, int modulus); | |
| 1242 void round_to_q(Register reg, int modulus); | |
| 1243 | |
| 1244 // allocation | |
| 1245 void eden_allocate( | |
| 1246 Register obj, // result: pointer to object after | |
| 1247 // successful allocation | |
| 1248 Register var_size_in_bytes, // object size in bytes if unknown at | |
| 1249 // compile time; invalid otherwise | |
| 1250 int con_size_in_bytes, // object size in bytes if known at | |
| 1251 // compile time | |
| 1252 Register t1, // temp register | |
| 1253 Label& slow_case // continuation point if fast | |
| 1254 // allocation fails | |
| 1255 ); | |
| 1256 void tlab_allocate( | |
| 1257 Register obj, // result: pointer to object after | |
| 1258 // successful allocation | |
| 1259 Register var_size_in_bytes, // object size in bytes if unknown at | |
| 1260 // compile time; invalid otherwise | |
| 1261 int con_size_in_bytes, // object size in bytes if known at | |
| 1262 // compile time | |
| 1263 Register t1, // temp register | |
| 1264 Register t2, // temp register | |
| 1265 Label& slow_case // continuation point if fast | |
| 1266 // allocation fails | |
| 1267 ); | |
| 1268 void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); | |
| 1269 | |
| 1270 //---- | |
| 1271 | |
| 1272 // Debugging | |
| 1273 | |
| 1274 // only if +VerifyOops | |
| 1275 void verify_oop(Register reg, const char* s = "broken oop"); | |
| 1276 void verify_oop_addr(Address addr, const char * s = "broken oop addr"); | |
| 1277 | |
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1278 // if heap base register is used - reinit it with the correct value |
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1279 void reinit_heapbase(); |
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1280 |
| 0 | 1281 // only if +VerifyFPU |
| 1282 void verify_FPU(int stack_depth, const char* s = "illegal FPU state") {} | |
| 1283 | |
| 1284 // prints msg, dumps registers and stops execution | |
| 1285 void stop(const char* msg); | |
| 1286 | |
| 1287 // prints message and continues | |
| 1288 void warn(const char* msg); | |
| 1289 | |
| 1290 static void debug(char* msg, int64_t pc, int64_t regs[]); | |
| 1291 | |
| 1292 void os_breakpoint(); | |
| 1293 | |
| 1294 void untested() | |
| 1295 { | |
| 1296 stop("untested"); | |
| 1297 } | |
| 1298 | |
| 1299 void unimplemented(const char* what = "") | |
| 1300 { | |
| 1301 char* b = new char[1024]; | |
| 1302 sprintf(b, "unimplemented: %s", what); | |
| 1303 stop(b); | |
| 1304 } | |
| 1305 | |
| 1306 void should_not_reach_here() | |
| 1307 { | |
| 1308 stop("should not reach here"); | |
| 1309 } | |
| 1310 | |
| 1311 // Stack overflow checking | |
| 1312 void bang_stack_with_offset(int offset) | |
| 1313 { | |
| 1314 // stack grows down, caller passes positive offset | |
| 1315 assert(offset > 0, "must bang with negative offset"); | |
| 1316 movl(Address(rsp, (-offset)), rax); | |
| 1317 } | |
| 1318 | |
| 1319 // Writes to stack successive pages until offset reached to check for | |
| 1320 // stack overflow + shadow pages. Also, clobbers tmp | |
| 1321 void bang_stack_size(Register offset, Register tmp); | |
| 1322 | |
| 1323 // Support for serializing memory accesses between threads. | |
| 1324 void serialize_memory(Register thread, Register tmp); | |
| 1325 | |
| 1326 void verify_tlab(); | |
| 1327 | |
| 1328 // Biased locking support | |
| 1329 // lock_reg and obj_reg must be loaded up with the appropriate values. | |
| 1330 // swap_reg must be rax and is killed. | |
| 1331 // tmp_reg must be supplied and is killed. | |
| 1332 // If swap_reg_contains_mark is true then the code assumes that the | |
| 1333 // mark word of the object has already been loaded into swap_reg. | |
| 1334 // Optional slow case is for implementations (interpreter and C1) which branch to | |
| 1335 // slow case directly. Leaves condition codes set for C2's Fast_Lock node. | |
| 1336 // Returns offset of first potentially-faulting instruction for null | |
| 1337 // check info (currently consumed only by C1). If | |
| 1338 // swap_reg_contains_mark is true then returns -1 as it is assumed | |
| 1339 // the calling code has already passed any potential faults. | |
| 1340 int biased_locking_enter(Register lock_reg, Register obj_reg, Register swap_reg, Register tmp_reg, | |
| 1341 bool swap_reg_contains_mark, | |
| 1342 Label& done, Label* slow_case = NULL, | |
| 1343 BiasedLockingCounters* counters = NULL); | |
| 1344 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done); | |
| 1345 | |
| 1346 Condition negate_condition(Condition cond); | |
| 1347 | |
| 1348 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit | |
| 1349 // operands. In general the names are modified to avoid hiding the instruction in Assembler | |
| 1350 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers | |
| 1351 // here in MacroAssembler. The major exception to this rule is call | |
| 1352 | |
| 1353 // Arithmetics | |
| 1354 | |
| 1355 void cmp8(AddressLiteral src1, int8_t imm32); | |
| 1356 | |
| 1357 void cmp32(AddressLiteral src1, int32_t src2); | |
| 1358 // compare reg - mem, or reg - &mem | |
| 1359 void cmp32(Register src1, AddressLiteral src2); | |
| 1360 | |
| 1361 void cmp32(Register src1, Address src2); | |
| 1362 | |
| 1363 #ifndef _LP64 | |
| 1364 void cmpoop(Address dst, jobject obj); | |
| 1365 void cmpoop(Register dst, jobject obj); | |
| 1366 #endif // _LP64 | |
| 1367 | |
| 1368 // NOTE src2 must be the lval. This is NOT an mem-mem compare | |
| 1369 void cmpptr(Address src1, AddressLiteral src2); | |
| 1370 | |
| 1371 void cmpptr(Register src1, AddressLiteral src); | |
| 1372 | |
| 1373 // will be cmpreg(?) | |
| 1374 void cmp64(Register src1, AddressLiteral src); | |
| 1375 | |
| 1376 void cmpxchgptr(Register reg, Address adr); | |
| 1377 void cmpxchgptr(Register reg, AddressLiteral adr); | |
| 1378 | |
| 1379 // Helper functions for statistics gathering. | |
| 1380 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes. | |
| 1381 void cond_inc32(Condition cond, AddressLiteral counter_addr); | |
| 1382 // Unconditional atomic increment. | |
| 1383 void atomic_incl(AddressLiteral counter_addr); | |
| 1384 | |
| 1385 | |
| 1386 void lea(Register dst, AddressLiteral src); | |
| 1387 void lea(Register dst, Address src); | |
| 1388 | |
| 1389 | |
| 1390 // Calls | |
| 1391 void call(Label& L, relocInfo::relocType rtype); | |
| 1392 void call(Register entry); | |
| 1393 void call(AddressLiteral entry); | |
| 1394 | |
| 1395 // Jumps | |
| 1396 | |
| 1397 // 32bit can do a case table jump in one instruction but we no longer allow the base | |
| 1398 // to be installed in the Address class | |
| 1399 void jump(ArrayAddress entry); | |
| 1400 | |
| 1401 void jump(AddressLiteral entry); | |
| 1402 void jump_cc(Condition cc, AddressLiteral dst); | |
| 1403 | |
| 1404 // Floating | |
| 1405 | |
| 1406 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); } | |
| 1407 void ldmxcsr(AddressLiteral src); | |
| 1408 | |
| 1409 private: | |
| 1410 // these are private because users should be doing movflt/movdbl | |
| 1411 | |
| 1412 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); } | |
| 1413 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); } | |
| 1414 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); } | |
| 1415 void movss(XMMRegister dst, AddressLiteral src); | |
| 1416 | |
| 1417 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); } | |
| 1418 void movlpd(XMMRegister dst, AddressLiteral src); | |
| 1419 | |
| 1420 public: | |
| 1421 | |
| 1422 | |
| 1423 void xorpd(XMMRegister dst, XMMRegister src) {Assembler::xorpd(dst, src); } | |
| 1424 void xorpd(XMMRegister dst, Address src) {Assembler::xorpd(dst, src); } | |
| 1425 void xorpd(XMMRegister dst, AddressLiteral src); | |
| 1426 | |
| 1427 void xorps(XMMRegister dst, XMMRegister src) {Assembler::xorps(dst, src); } | |
| 1428 void xorps(XMMRegister dst, Address src) {Assembler::xorps(dst, src); } | |
| 1429 void xorps(XMMRegister dst, AddressLiteral src); | |
| 1430 | |
| 1431 | |
| 1432 // Data | |
| 1433 | |
| 1434 void movoop(Register dst, jobject obj); | |
| 1435 void movoop(Address dst, jobject obj); | |
| 1436 | |
| 1437 void movptr(ArrayAddress dst, Register src); | |
| 1438 void movptr(Register dst, AddressLiteral src); | |
| 1439 | |
| 1440 void movptr(Register dst, intptr_t src); | |
| 1441 void movptr(Address dst, intptr_t src); | |
| 1442 | |
| 1443 void movptr(Register dst, ArrayAddress src); | |
| 1444 | |
| 1445 // to avoid hiding movl | |
| 1446 void mov32(AddressLiteral dst, Register src); | |
| 1447 void mov32(Register dst, AddressLiteral src); | |
| 1448 | |
| 1449 void pushoop(jobject obj); | |
| 1450 | |
| 1451 // Can push value or effective address | |
| 1452 void pushptr(AddressLiteral src); | |
| 1453 | |
| 1454 }; | |
| 1455 | |
| 1456 /** | |
| 1457 * class SkipIfEqual: | |
| 1458 * | |
| 1459 * Instantiating this class will result in assembly code being output that will | |
| 1460 * jump around any code emitted between the creation of the instance and it's | |
| 1461 * automatic destruction at the end of a scope block, depending on the value of | |
| 1462 * the flag passed to the constructor, which will be checked at run-time. | |
| 1463 */ | |
| 1464 class SkipIfEqual { | |
| 1465 private: | |
| 1466 MacroAssembler* _masm; | |
| 1467 Label _label; | |
| 1468 | |
| 1469 public: | |
| 1470 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value); | |
| 1471 ~SkipIfEqual(); | |
| 1472 }; | |
| 1473 | |
| 1474 | |
| 1475 #ifdef ASSERT | |
| 1476 inline bool AbstractAssembler::pd_check_instruction_mark() { return true; } | |
| 1477 #endif |