Mercurial > hg > graal-compiler
annotate src/cpu/x86/vm/assembler_x86.cpp @ 17024:4e2d34d7715b
[SPARC/AMD64] Splitting up oopmap generation for Intel XMM and SPARC Floatingpoint registers
author | Stefan Anzinger <stefan.anzinger@oracle.com> |
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date | Tue, 02 Sep 2014 17:16:26 -0700 |
parents | 88df5d7b1001 |
children | 52b4284cb496 |
rev | line source |
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0 | 1 /* |
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2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #include "precompiled.hpp" |
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26 #include "asm/assembler.hpp" |
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27 #include "asm/assembler.inline.hpp" |
1972 | 28 #include "gc_interface/collectedHeap.inline.hpp" |
29 #include "interpreter/interpreter.hpp" | |
30 #include "memory/cardTableModRefBS.hpp" | |
31 #include "memory/resourceArea.hpp" | |
32 #include "prims/methodHandles.hpp" | |
33 #include "runtime/biasedLocking.hpp" | |
34 #include "runtime/interfaceSupport.hpp" | |
35 #include "runtime/objectMonitor.hpp" | |
36 #include "runtime/os.hpp" | |
37 #include "runtime/sharedRuntime.hpp" | |
38 #include "runtime/stubRoutines.hpp" | |
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39 #include "utilities/macros.hpp" |
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40 #if INCLUDE_ALL_GCS |
1972 | 41 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp" |
42 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp" | |
43 #include "gc_implementation/g1/heapRegion.hpp" | |
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44 #endif // INCLUDE_ALL_GCS |
0 | 45 |
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46 #ifdef PRODUCT |
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47 #define BLOCK_COMMENT(str) /* nothing */ |
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48 #define STOP(error) stop(error) |
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49 #else |
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50 #define BLOCK_COMMENT(str) block_comment(str) |
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51 #define STOP(error) block_comment(error); stop(error) |
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52 #endif |
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53 |
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54 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") |
0 | 55 // Implementation of AddressLiteral |
56 | |
57 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) { | |
58 _is_lval = false; | |
59 _target = target; | |
60 switch (rtype) { | |
61 case relocInfo::oop_type: | |
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62 case relocInfo::metadata_type: |
0 | 63 // Oops are a special case. Normally they would be their own section |
64 // but in cases like icBuffer they are literals in the code stream that | |
65 // we don't have a section for. We use none so that we get a literal address | |
66 // which is always patchable. | |
67 break; | |
68 case relocInfo::external_word_type: | |
69 _rspec = external_word_Relocation::spec(target); | |
70 break; | |
71 case relocInfo::internal_word_type: | |
72 _rspec = internal_word_Relocation::spec(target); | |
73 break; | |
74 case relocInfo::opt_virtual_call_type: | |
75 _rspec = opt_virtual_call_Relocation::spec(); | |
76 break; | |
77 case relocInfo::static_call_type: | |
78 _rspec = static_call_Relocation::spec(); | |
79 break; | |
80 case relocInfo::runtime_call_type: | |
81 _rspec = runtime_call_Relocation::spec(); | |
82 break; | |
83 case relocInfo::poll_type: | |
84 case relocInfo::poll_return_type: | |
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85 _rspec = Relocation::spec_simple(rtype); |
0 | 86 break; |
87 case relocInfo::none: | |
88 break; | |
89 default: | |
90 ShouldNotReachHere(); | |
91 break; | |
92 } | |
93 } | |
94 | |
95 // Implementation of Address | |
96 | |
304 | 97 #ifdef _LP64 |
98 | |
0 | 99 Address Address::make_array(ArrayAddress adr) { |
100 // Not implementable on 64bit machines | |
101 // Should have been handled higher up the call chain. | |
102 ShouldNotReachHere(); | |
304 | 103 return Address(); |
104 } | |
105 | |
106 // exceedingly dangerous constructor | |
107 Address::Address(int disp, address loc, relocInfo::relocType rtype) { | |
108 _base = noreg; | |
109 _index = noreg; | |
110 _scale = no_scale; | |
111 _disp = disp; | |
112 switch (rtype) { | |
113 case relocInfo::external_word_type: | |
114 _rspec = external_word_Relocation::spec(loc); | |
115 break; | |
116 case relocInfo::internal_word_type: | |
117 _rspec = internal_word_Relocation::spec(loc); | |
118 break; | |
119 case relocInfo::runtime_call_type: | |
120 // HMM | |
121 _rspec = runtime_call_Relocation::spec(); | |
122 break; | |
123 case relocInfo::poll_type: | |
124 case relocInfo::poll_return_type: | |
125 _rspec = Relocation::spec_simple(rtype); | |
126 break; | |
127 case relocInfo::none: | |
128 break; | |
129 default: | |
130 ShouldNotReachHere(); | |
131 } | |
132 } | |
133 #else // LP64 | |
134 | |
135 Address Address::make_array(ArrayAddress adr) { | |
0 | 136 AddressLiteral base = adr.base(); |
137 Address index = adr.index(); | |
138 assert(index._disp == 0, "must not have disp"); // maybe it can? | |
139 Address array(index._base, index._index, index._scale, (intptr_t) base.target()); | |
140 array._rspec = base._rspec; | |
141 return array; | |
304 | 142 } |
0 | 143 |
144 // exceedingly dangerous constructor | |
145 Address::Address(address loc, RelocationHolder spec) { | |
146 _base = noreg; | |
147 _index = noreg; | |
148 _scale = no_scale; | |
149 _disp = (intptr_t) loc; | |
150 _rspec = spec; | |
151 } | |
304 | 152 |
0 | 153 #endif // _LP64 |
154 | |
304 | 155 |
156 | |
0 | 157 // Convert the raw encoding form into the form expected by the constructor for |
158 // Address. An index of 4 (rsp) corresponds to having no index, so convert | |
159 // that to noreg for the Address constructor. | |
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160 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) { |
624 | 161 RelocationHolder rspec; |
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162 if (disp_reloc != relocInfo::none) { |
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163 rspec = Relocation::spec_simple(disp_reloc); |
624 | 164 } |
0 | 165 bool valid_index = index != rsp->encoding(); |
166 if (valid_index) { | |
167 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp)); | |
624 | 168 madr._rspec = rspec; |
0 | 169 return madr; |
170 } else { | |
171 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp)); | |
624 | 172 madr._rspec = rspec; |
0 | 173 return madr; |
174 } | |
175 } | |
176 | |
177 // Implementation of Assembler | |
178 | |
179 int AbstractAssembler::code_fill_byte() { | |
180 return (u_char)'\xF4'; // hlt | |
181 } | |
182 | |
183 // make this go away someday | |
184 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) { | |
185 if (rtype == relocInfo::none) | |
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186 emit_int32(data); |
0 | 187 else emit_data(data, Relocation::spec_simple(rtype), format); |
188 } | |
189 | |
190 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) { | |
304 | 191 assert(imm_operand == 0, "default format must be immediate in this file"); |
0 | 192 assert(inst_mark() != NULL, "must be inside InstructionMark"); |
193 if (rspec.type() != relocInfo::none) { | |
194 #ifdef ASSERT | |
195 check_relocation(rspec, format); | |
196 #endif | |
197 // Do not use AbstractAssembler::relocate, which is not intended for | |
198 // embedded words. Instead, relocate to the enclosing instruction. | |
199 | |
200 // hack. call32 is too wide for mask so use disp32 | |
201 if (format == call32_operand) | |
202 code_section()->relocate(inst_mark(), rspec, disp32_operand); | |
203 else | |
204 code_section()->relocate(inst_mark(), rspec, format); | |
205 } | |
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206 emit_int32(data); |
0 | 207 } |
208 | |
304 | 209 static int encode(Register r) { |
210 int enc = r->encoding(); | |
211 if (enc >= 8) { | |
212 enc -= 8; | |
213 } | |
214 return enc; | |
215 } | |
216 | |
0 | 217 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) { |
218 assert(dst->has_byte_register(), "must have byte register"); | |
219 assert(isByte(op1) && isByte(op2), "wrong opcode"); | |
220 assert(isByte(imm8), "not a byte"); | |
221 assert((op1 & 0x01) == 0, "should be 8bit operation"); | |
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222 emit_int8(op1); |
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223 emit_int8(op2 | encode(dst)); |
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224 emit_int8(imm8); |
0 | 225 } |
226 | |
227 | |
304 | 228 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) { |
0 | 229 assert(isByte(op1) && isByte(op2), "wrong opcode"); |
230 assert((op1 & 0x01) == 1, "should be 32bit operation"); | |
231 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
232 if (is8bit(imm32)) { | |
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233 emit_int8(op1 | 0x02); // set sign bit |
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234 emit_int8(op2 | encode(dst)); |
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235 emit_int8(imm32 & 0xFF); |
0 | 236 } else { |
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237 emit_int8(op1); |
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238 emit_int8(op2 | encode(dst)); |
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239 emit_int32(imm32); |
0 | 240 } |
241 } | |
242 | |
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243 // Force generation of a 4 byte immediate value even if it fits into 8bit |
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244 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) { |
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245 assert(isByte(op1) && isByte(op2), "wrong opcode"); |
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246 assert((op1 & 0x01) == 1, "should be 32bit operation"); |
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247 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); |
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248 emit_int8(op1); |
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249 emit_int8(op2 | encode(dst)); |
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250 emit_int32(imm32); |
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251 } |
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252 |
0 | 253 // immediate-to-memory forms |
304 | 254 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) { |
0 | 255 assert((op1 & 0x01) == 1, "should be 32bit operation"); |
256 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
257 if (is8bit(imm32)) { | |
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258 emit_int8(op1 | 0x02); // set sign bit |
304 | 259 emit_operand(rm, adr, 1); |
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260 emit_int8(imm32 & 0xFF); |
0 | 261 } else { |
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262 emit_int8(op1); |
304 | 263 emit_operand(rm, adr, 4); |
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264 emit_int32(imm32); |
0 | 265 } |
266 } | |
267 | |
268 | |
269 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) { | |
270 assert(isByte(op1) && isByte(op2), "wrong opcode"); | |
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271 emit_int8(op1); |
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272 emit_int8(op2 | encode(dst) << 3 | encode(src)); |
304 | 273 } |
274 | |
275 | |
276 void Assembler::emit_operand(Register reg, Register base, Register index, | |
277 Address::ScaleFactor scale, int disp, | |
278 RelocationHolder const& rspec, | |
279 int rip_relative_correction) { | |
0 | 280 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type(); |
304 | 281 |
282 // Encode the registers as needed in the fields they are used in | |
283 | |
284 int regenc = encode(reg) << 3; | |
285 int indexenc = index->is_valid() ? encode(index) << 3 : 0; | |
286 int baseenc = base->is_valid() ? encode(base) : 0; | |
287 | |
0 | 288 if (base->is_valid()) { |
289 if (index->is_valid()) { | |
290 assert(scale != Address::no_scale, "inconsistent address"); | |
291 // [base + index*scale + disp] | |
304 | 292 if (disp == 0 && rtype == relocInfo::none && |
293 base != rbp LP64_ONLY(&& base != r13)) { | |
0 | 294 // [base + index*scale] |
295 // [00 reg 100][ss index base] | |
296 assert(index != rsp, "illegal addressing mode"); | |
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297 emit_int8(0x04 | regenc); |
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298 emit_int8(scale << 6 | indexenc | baseenc); |
0 | 299 } else if (is8bit(disp) && rtype == relocInfo::none) { |
300 // [base + index*scale + imm8] | |
301 // [01 reg 100][ss index base] imm8 | |
302 assert(index != rsp, "illegal addressing mode"); | |
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303 emit_int8(0x44 | regenc); |
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304 emit_int8(scale << 6 | indexenc | baseenc); |
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305 emit_int8(disp & 0xFF); |
0 | 306 } else { |
304 | 307 // [base + index*scale + disp32] |
308 // [10 reg 100][ss index base] disp32 | |
0 | 309 assert(index != rsp, "illegal addressing mode"); |
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310 emit_int8(0x84 | regenc); |
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311 emit_int8(scale << 6 | indexenc | baseenc); |
0 | 312 emit_data(disp, rspec, disp32_operand); |
313 } | |
304 | 314 } else if (base == rsp LP64_ONLY(|| base == r12)) { |
315 // [rsp + disp] | |
0 | 316 if (disp == 0 && rtype == relocInfo::none) { |
304 | 317 // [rsp] |
0 | 318 // [00 reg 100][00 100 100] |
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319 emit_int8(0x04 | regenc); |
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320 emit_int8(0x24); |
0 | 321 } else if (is8bit(disp) && rtype == relocInfo::none) { |
304 | 322 // [rsp + imm8] |
323 // [01 reg 100][00 100 100] disp8 | |
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324 emit_int8(0x44 | regenc); |
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325 emit_int8(0x24); |
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326 emit_int8(disp & 0xFF); |
0 | 327 } else { |
304 | 328 // [rsp + imm32] |
329 // [10 reg 100][00 100 100] disp32 | |
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330 emit_int8(0x84 | regenc); |
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331 emit_int8(0x24); |
0 | 332 emit_data(disp, rspec, disp32_operand); |
333 } | |
334 } else { | |
335 // [base + disp] | |
304 | 336 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode"); |
337 if (disp == 0 && rtype == relocInfo::none && | |
338 base != rbp LP64_ONLY(&& base != r13)) { | |
0 | 339 // [base] |
340 // [00 reg base] | |
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341 emit_int8(0x00 | regenc | baseenc); |
0 | 342 } else if (is8bit(disp) && rtype == relocInfo::none) { |
304 | 343 // [base + disp8] |
344 // [01 reg base] disp8 | |
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345 emit_int8(0x40 | regenc | baseenc); |
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346 emit_int8(disp & 0xFF); |
0 | 347 } else { |
304 | 348 // [base + disp32] |
349 // [10 reg base] disp32 | |
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350 emit_int8(0x80 | regenc | baseenc); |
0 | 351 emit_data(disp, rspec, disp32_operand); |
352 } | |
353 } | |
354 } else { | |
355 if (index->is_valid()) { | |
356 assert(scale != Address::no_scale, "inconsistent address"); | |
357 // [index*scale + disp] | |
304 | 358 // [00 reg 100][ss index 101] disp32 |
0 | 359 assert(index != rsp, "illegal addressing mode"); |
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360 emit_int8(0x04 | regenc); |
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361 emit_int8(scale << 6 | indexenc | 0x05); |
0 | 362 emit_data(disp, rspec, disp32_operand); |
304 | 363 } else if (rtype != relocInfo::none ) { |
364 // [disp] (64bit) RIP-RELATIVE (32bit) abs | |
365 // [00 000 101] disp32 | |
366 | |
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367 emit_int8(0x05 | regenc); |
304 | 368 // Note that the RIP-rel. correction applies to the generated |
369 // disp field, but _not_ to the target address in the rspec. | |
370 | |
371 // disp was created by converting the target address minus the pc | |
372 // at the start of the instruction. That needs more correction here. | |
373 // intptr_t disp = target - next_ip; | |
374 assert(inst_mark() != NULL, "must be inside InstructionMark"); | |
375 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction; | |
376 int64_t adjusted = disp; | |
377 // Do rip-rel adjustment for 64bit | |
378 LP64_ONLY(adjusted -= (next_ip - inst_mark())); | |
379 assert(is_simm32(adjusted), | |
380 "must be 32bit offset (RIP relative address)"); | |
381 emit_data((int32_t) adjusted, rspec, disp32_operand); | |
382 | |
0 | 383 } else { |
304 | 384 // 32bit never did this, did everything as the rip-rel/disp code above |
385 // [disp] ABSOLUTE | |
386 // [00 reg 100][00 100 101] disp32 | |
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387 emit_int8(0x04 | regenc); |
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388 emit_int8(0x25); |
0 | 389 emit_data(disp, rspec, disp32_operand); |
390 } | |
391 } | |
392 } | |
393 | |
304 | 394 void Assembler::emit_operand(XMMRegister reg, Register base, Register index, |
395 Address::ScaleFactor scale, int disp, | |
396 RelocationHolder const& rspec) { | |
397 emit_operand((Register)reg, base, index, scale, disp, rspec); | |
398 } | |
399 | |
0 | 400 // Secret local extension to Assembler::WhichOperand: |
401 #define end_pc_operand (_WhichOperand_limit) | |
402 | |
403 address Assembler::locate_operand(address inst, WhichOperand which) { | |
404 // Decode the given instruction, and return the address of | |
405 // an embedded 32-bit operand word. | |
406 | |
407 // If "which" is disp32_operand, selects the displacement portion | |
408 // of an effective address specifier. | |
304 | 409 // If "which" is imm64_operand, selects the trailing immediate constant. |
0 | 410 // If "which" is call32_operand, selects the displacement of a call or jump. |
411 // Caller is responsible for ensuring that there is such an operand, | |
304 | 412 // and that it is 32/64 bits wide. |
0 | 413 |
414 // If "which" is end_pc_operand, find the end of the instruction. | |
415 | |
416 address ip = inst; | |
304 | 417 bool is_64bit = false; |
418 | |
419 debug_only(bool has_disp32 = false); | |
420 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn | |
421 | |
422 again_after_prefix: | |
0 | 423 switch (0xFF & *ip++) { |
424 | |
425 // These convenience macros generate groups of "case" labels for the switch. | |
304 | 426 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3 |
427 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \ | |
0 | 428 case (x)+4: case (x)+5: case (x)+6: case (x)+7 |
304 | 429 #define REP16(x) REP8((x)+0): \ |
0 | 430 case REP8((x)+8) |
431 | |
432 case CS_segment: | |
433 case SS_segment: | |
434 case DS_segment: | |
435 case ES_segment: | |
436 case FS_segment: | |
437 case GS_segment: | |
304 | 438 // Seems dubious |
439 LP64_ONLY(assert(false, "shouldn't have that prefix")); | |
0 | 440 assert(ip == inst+1, "only one prefix allowed"); |
441 goto again_after_prefix; | |
442 | |
304 | 443 case 0x67: |
444 case REX: | |
445 case REX_B: | |
446 case REX_X: | |
447 case REX_XB: | |
448 case REX_R: | |
449 case REX_RB: | |
450 case REX_RX: | |
451 case REX_RXB: | |
452 NOT_LP64(assert(false, "64bit prefixes")); | |
453 goto again_after_prefix; | |
454 | |
455 case REX_W: | |
456 case REX_WB: | |
457 case REX_WX: | |
458 case REX_WXB: | |
459 case REX_WR: | |
460 case REX_WRB: | |
461 case REX_WRX: | |
462 case REX_WRXB: | |
463 NOT_LP64(assert(false, "64bit prefixes")); | |
464 is_64bit = true; | |
465 goto again_after_prefix; | |
466 | |
467 case 0xFF: // pushq a; decl a; incl a; call a; jmp a | |
0 | 468 case 0x88: // movb a, r |
469 case 0x89: // movl a, r | |
470 case 0x8A: // movb r, a | |
471 case 0x8B: // movl r, a | |
472 case 0x8F: // popl a | |
304 | 473 debug_only(has_disp32 = true); |
0 | 474 break; |
475 | |
304 | 476 case 0x68: // pushq #32 |
477 if (which == end_pc_operand) { | |
478 return ip + 4; | |
479 } | |
480 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate"); | |
0 | 481 return ip; // not produced by emit_operand |
482 | |
483 case 0x66: // movw ... (size prefix) | |
304 | 484 again_after_size_prefix2: |
0 | 485 switch (0xFF & *ip++) { |
304 | 486 case REX: |
487 case REX_B: | |
488 case REX_X: | |
489 case REX_XB: | |
490 case REX_R: | |
491 case REX_RB: | |
492 case REX_RX: | |
493 case REX_RXB: | |
494 case REX_W: | |
495 case REX_WB: | |
496 case REX_WX: | |
497 case REX_WXB: | |
498 case REX_WR: | |
499 case REX_WRB: | |
500 case REX_WRX: | |
501 case REX_WRXB: | |
502 NOT_LP64(assert(false, "64bit prefix found")); | |
503 goto again_after_size_prefix2; | |
0 | 504 case 0x8B: // movw r, a |
505 case 0x89: // movw a, r | |
304 | 506 debug_only(has_disp32 = true); |
0 | 507 break; |
508 case 0xC7: // movw a, #16 | |
304 | 509 debug_only(has_disp32 = true); |
0 | 510 tail_size = 2; // the imm16 |
511 break; | |
512 case 0x0F: // several SSE/SSE2 variants | |
513 ip--; // reparse the 0x0F | |
514 goto again_after_prefix; | |
515 default: | |
516 ShouldNotReachHere(); | |
517 } | |
518 break; | |
519 | |
304 | 520 case REP8(0xB8): // movl/q r, #32/#64(oop?) |
521 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4); | |
522 // these asserts are somewhat nonsensical | |
523 #ifndef _LP64 | |
5984 | 524 assert(which == imm_operand || which == disp32_operand, |
525 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, ip)); | |
304 | 526 #else |
527 assert((which == call32_operand || which == imm_operand) && is_64bit || | |
5984 | 528 which == narrow_oop_operand && !is_64bit, |
529 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, ip)); | |
304 | 530 #endif // _LP64 |
0 | 531 return ip; |
532 | |
533 case 0x69: // imul r, a, #32 | |
534 case 0xC7: // movl a, #32(oop?) | |
535 tail_size = 4; | |
304 | 536 debug_only(has_disp32 = true); // has both kinds of operands! |
0 | 537 break; |
538 | |
539 case 0x0F: // movx..., etc. | |
540 switch (0xFF & *ip++) { | |
4759 | 541 case 0x3A: // pcmpestri |
542 tail_size = 1; | |
543 case 0x38: // ptest, pmovzxbw | |
544 ip++; // skip opcode | |
545 debug_only(has_disp32 = true); // has both kinds of operands! | |
546 break; | |
547 | |
548 case 0x70: // pshufd r, r/a, #8 | |
549 debug_only(has_disp32 = true); // has both kinds of operands! | |
550 case 0x73: // psrldq r, #8 | |
551 tail_size = 1; | |
552 break; | |
553 | |
0 | 554 case 0x12: // movlps |
555 case 0x28: // movaps | |
556 case 0x2E: // ucomiss | |
557 case 0x2F: // comiss | |
558 case 0x54: // andps | |
559 case 0x55: // andnps | |
560 case 0x56: // orps | |
561 case 0x57: // xorps | |
562 case 0x6E: // movd | |
563 case 0x7E: // movd | |
4759 | 564 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush |
304 | 565 debug_only(has_disp32 = true); |
0 | 566 break; |
567 | |
568 case 0xAD: // shrd r, a, %cl | |
569 case 0xAF: // imul r, a | |
304 | 570 case 0xBE: // movsbl r, a (movsxb) |
571 case 0xBF: // movswl r, a (movsxw) | |
572 case 0xB6: // movzbl r, a (movzxb) | |
573 case 0xB7: // movzwl r, a (movzxw) | |
0 | 574 case REP16(0x40): // cmovl cc, r, a |
575 case 0xB0: // cmpxchgb | |
576 case 0xB1: // cmpxchg | |
577 case 0xC1: // xaddl | |
578 case 0xC7: // cmpxchg8 | |
579 case REP16(0x90): // setcc a | |
304 | 580 debug_only(has_disp32 = true); |
0 | 581 // fall out of the switch to decode the address |
582 break; | |
304 | 583 |
4759 | 584 case 0xC4: // pinsrw r, a, #8 |
585 debug_only(has_disp32 = true); | |
586 case 0xC5: // pextrw r, r, #8 | |
587 tail_size = 1; // the imm8 | |
588 break; | |
589 | |
0 | 590 case 0xAC: // shrd r, a, #8 |
304 | 591 debug_only(has_disp32 = true); |
0 | 592 tail_size = 1; // the imm8 |
593 break; | |
304 | 594 |
0 | 595 case REP16(0x80): // jcc rdisp32 |
596 if (which == end_pc_operand) return ip + 4; | |
304 | 597 assert(which == call32_operand, "jcc has no disp32 or imm"); |
0 | 598 return ip; |
599 default: | |
600 ShouldNotReachHere(); | |
601 } | |
602 break; | |
603 | |
604 case 0x81: // addl a, #32; addl r, #32 | |
605 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl | |
304 | 606 // on 32bit in the case of cmpl, the imm might be an oop |
0 | 607 tail_size = 4; |
304 | 608 debug_only(has_disp32 = true); // has both kinds of operands! |
0 | 609 break; |
610 | |
611 case 0x83: // addl a, #8; addl r, #8 | |
612 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl | |
304 | 613 debug_only(has_disp32 = true); // has both kinds of operands! |
0 | 614 tail_size = 1; |
615 break; | |
616 | |
617 case 0x9B: | |
618 switch (0xFF & *ip++) { | |
619 case 0xD9: // fnstcw a | |
304 | 620 debug_only(has_disp32 = true); |
0 | 621 break; |
622 default: | |
623 ShouldNotReachHere(); | |
624 } | |
625 break; | |
626 | |
627 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a | |
628 case REP4(0x10): // adc... | |
629 case REP4(0x20): // and... | |
630 case REP4(0x30): // xor... | |
631 case REP4(0x08): // or... | |
632 case REP4(0x18): // sbb... | |
633 case REP4(0x28): // sub... | |
304 | 634 case 0xF7: // mull a |
635 case 0x8D: // lea r, a | |
636 case 0x87: // xchg r, a | |
0 | 637 case REP4(0x38): // cmp... |
304 | 638 case 0x85: // test r, a |
639 debug_only(has_disp32 = true); // has both kinds of operands! | |
0 | 640 break; |
641 | |
642 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8 | |
643 case 0xC6: // movb a, #8 | |
644 case 0x80: // cmpb a, #8 | |
645 case 0x6B: // imul r, a, #8 | |
304 | 646 debug_only(has_disp32 = true); // has both kinds of operands! |
0 | 647 tail_size = 1; // the imm8 |
648 break; | |
649 | |
4759 | 650 case 0xC4: // VEX_3bytes |
651 case 0xC5: // VEX_2bytes | |
652 assert((UseAVX > 0), "shouldn't have VEX prefix"); | |
653 assert(ip == inst+1, "no prefixes allowed"); | |
654 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions | |
655 // but they have prefix 0x0F and processed when 0x0F processed above. | |
656 // | |
657 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES | |
658 // instructions (these instructions are not supported in 64-bit mode). | |
659 // To distinguish them bits [7:6] are set in the VEX second byte since | |
660 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set | |
661 // those VEX bits REX and vvvv bits are inverted. | |
662 // | |
663 // Fortunately C2 doesn't generate these instructions so we don't need | |
664 // to check for them in product version. | |
665 | |
666 // Check second byte | |
667 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions")); | |
668 | |
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669 int vex_opcode; |
4759 | 670 // First byte |
671 if ((0xFF & *inst) == VEX_3bytes) { | |
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672 vex_opcode = VEX_OPCODE_MASK & *ip; |
4759 | 673 ip++; // third byte |
674 is_64bit = ((VEX_W & *ip) == VEX_W); | |
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675 } else { |
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676 vex_opcode = VEX_OPCODE_0F; |
4759 | 677 } |
678 ip++; // opcode | |
679 // To find the end of instruction (which == end_pc_operand). | |
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680 switch (vex_opcode) { |
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681 case VEX_OPCODE_0F: |
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682 switch (0xFF & *ip) { |
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683 case 0x70: // pshufd r, r/a, #8 |
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684 case 0x71: // ps[rl|ra|ll]w r, #8 |
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685 case 0x72: // ps[rl|ra|ll]d r, #8 |
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686 case 0x73: // ps[rl|ra|ll]q r, #8 |
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687 case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8 |
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688 case 0xC4: // pinsrw r, r, r/a, #8 |
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689 case 0xC5: // pextrw r/a, r, #8 |
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690 case 0xC6: // shufp[s|d] r, r, r/a, #8 |
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691 tail_size = 1; // the imm8 |
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692 break; |
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693 } |
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694 break; |
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695 case VEX_OPCODE_0F_3A: |
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696 tail_size = 1; |
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697 break; |
4759 | 698 } |
699 ip++; // skip opcode | |
700 debug_only(has_disp32 = true); // has both kinds of operands! | |
701 break; | |
0 | 702 |
703 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1 | |
704 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl | |
705 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a | |
706 case 0xDD: // fld_d a; fst_d a; fstp_d a | |
707 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a | |
708 case 0xDF: // fild_d a; fistp_d a | |
709 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a | |
710 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a | |
711 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a | |
304 | 712 debug_only(has_disp32 = true); |
0 | 713 break; |
714 | |
4759 | 715 case 0xE8: // call rdisp32 |
716 case 0xE9: // jmp rdisp32 | |
717 if (which == end_pc_operand) return ip + 4; | |
718 assert(which == call32_operand, "call has no disp32 or imm"); | |
719 return ip; | |
720 | |
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721 case 0xF0: // Lock |
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722 assert(os::is_MP(), "only on MP"); |
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723 goto again_after_prefix; |
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724 |
0 | 725 case 0xF3: // For SSE |
726 case 0xF2: // For SSE2 | |
304 | 727 switch (0xFF & *ip++) { |
728 case REX: | |
729 case REX_B: | |
730 case REX_X: | |
731 case REX_XB: | |
732 case REX_R: | |
733 case REX_RB: | |
734 case REX_RX: | |
735 case REX_RXB: | |
736 case REX_W: | |
737 case REX_WB: | |
738 case REX_WX: | |
739 case REX_WXB: | |
740 case REX_WR: | |
741 case REX_WRB: | |
742 case REX_WRX: | |
743 case REX_WRXB: | |
744 NOT_LP64(assert(false, "found 64bit prefix")); | |
745 ip++; | |
746 default: | |
747 ip++; | |
748 } | |
749 debug_only(has_disp32 = true); // has both kinds of operands! | |
0 | 750 break; |
751 | |
752 default: | |
753 ShouldNotReachHere(); | |
754 | |
304 | 755 #undef REP8 |
756 #undef REP16 | |
0 | 757 } |
758 | |
759 assert(which != call32_operand, "instruction is not a call, jmp, or jcc"); | |
304 | 760 #ifdef _LP64 |
761 assert(which != imm_operand, "instruction is not a movq reg, imm64"); | |
762 #else | |
763 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field"); | |
764 assert(which != imm_operand || has_disp32, "instruction has no imm32 field"); | |
765 #endif // LP64 | |
766 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field"); | |
0 | 767 |
768 // parse the output of emit_operand | |
769 int op2 = 0xFF & *ip++; | |
770 int base = op2 & 0x07; | |
771 int op3 = -1; | |
772 const int b100 = 4; | |
773 const int b101 = 5; | |
774 if (base == b100 && (op2 >> 6) != 3) { | |
775 op3 = 0xFF & *ip++; | |
776 base = op3 & 0x07; // refetch the base | |
777 } | |
778 // now ip points at the disp (if any) | |
779 | |
780 switch (op2 >> 6) { | |
781 case 0: | |
782 // [00 reg 100][ss index base] | |
304 | 783 // [00 reg 100][00 100 esp] |
0 | 784 // [00 reg base] |
785 // [00 reg 100][ss index 101][disp32] | |
786 // [00 reg 101] [disp32] | |
787 | |
788 if (base == b101) { | |
789 if (which == disp32_operand) | |
790 return ip; // caller wants the disp32 | |
791 ip += 4; // skip the disp32 | |
792 } | |
793 break; | |
794 | |
795 case 1: | |
796 // [01 reg 100][ss index base][disp8] | |
304 | 797 // [01 reg 100][00 100 esp][disp8] |
0 | 798 // [01 reg base] [disp8] |
799 ip += 1; // skip the disp8 | |
800 break; | |
801 | |
802 case 2: | |
803 // [10 reg 100][ss index base][disp32] | |
304 | 804 // [10 reg 100][00 100 esp][disp32] |
0 | 805 // [10 reg base] [disp32] |
806 if (which == disp32_operand) | |
807 return ip; // caller wants the disp32 | |
808 ip += 4; // skip the disp32 | |
809 break; | |
810 | |
811 case 3: | |
812 // [11 reg base] (not a memory addressing mode) | |
813 break; | |
814 } | |
815 | |
816 if (which == end_pc_operand) { | |
817 return ip + tail_size; | |
818 } | |
819 | |
304 | 820 #ifdef _LP64 |
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821 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32"); |
304 | 822 #else |
823 assert(which == imm_operand, "instruction has only an imm field"); | |
824 #endif // LP64 | |
0 | 825 return ip; |
826 } | |
827 | |
828 address Assembler::locate_next_instruction(address inst) { | |
829 // Secretly share code with locate_operand: | |
830 return locate_operand(inst, end_pc_operand); | |
831 } | |
832 | |
833 | |
834 #ifdef ASSERT | |
835 void Assembler::check_relocation(RelocationHolder const& rspec, int format) { | |
836 address inst = inst_mark(); | |
837 assert(inst != NULL && inst < pc(), "must point to beginning of instruction"); | |
838 address opnd; | |
839 | |
840 Relocation* r = rspec.reloc(); | |
841 if (r->type() == relocInfo::none) { | |
842 return; | |
843 } else if (r->is_call() || format == call32_operand) { | |
844 // assert(format == imm32_operand, "cannot specify a nonzero format"); | |
845 opnd = locate_operand(inst, call32_operand); | |
846 } else if (r->is_data()) { | |
304 | 847 assert(format == imm_operand || format == disp32_operand |
848 LP64_ONLY(|| format == narrow_oop_operand), "format ok"); | |
0 | 849 opnd = locate_operand(inst, (WhichOperand)format); |
850 } else { | |
304 | 851 assert(format == imm_operand, "cannot specify a format"); |
0 | 852 return; |
853 } | |
854 assert(opnd == pc(), "must put operand where relocs can find it"); | |
855 } | |
304 | 856 #endif // ASSERT |
857 | |
858 void Assembler::emit_operand32(Register reg, Address adr) { | |
859 assert(reg->encoding() < 8, "no extended registers"); | |
860 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
861 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
862 adr._rspec); | |
863 } | |
864 | |
865 void Assembler::emit_operand(Register reg, Address adr, | |
866 int rip_relative_correction) { | |
867 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
868 adr._rspec, | |
869 rip_relative_correction); | |
870 } | |
871 | |
872 void Assembler::emit_operand(XMMRegister reg, Address adr) { | |
873 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
874 adr._rspec); | |
875 } | |
876 | |
877 // MMX operations | |
878 void Assembler::emit_operand(MMXRegister reg, Address adr) { | |
879 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
880 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); | |
881 } | |
882 | |
883 // work around gcc (3.2.1-7a) bug | |
884 void Assembler::emit_operand(Address adr, MMXRegister reg) { | |
885 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
886 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); | |
0 | 887 } |
888 | |
889 | |
890 void Assembler::emit_farith(int b1, int b2, int i) { | |
891 assert(isByte(b1) && isByte(b2), "wrong opcode"); | |
892 assert(0 <= i && i < 8, "illegal stack offset"); | |
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893 emit_int8(b1); |
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894 emit_int8(b2 + i); |
0 | 895 } |
896 | |
897 | |
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898 // Now the Assembler instructions (identical for 32/64 bits) |
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899 |
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900 void Assembler::adcl(Address dst, int32_t imm32) { |
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901 InstructionMark im(this); |
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902 prefix(dst); |
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903 emit_arith_operand(0x81, rdx, dst, imm32); |
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904 } |
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905 |
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906 void Assembler::adcl(Address dst, Register src) { |
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907 InstructionMark im(this); |
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908 prefix(dst, src); |
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909 emit_int8(0x11); |
2100
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910 emit_operand(src, dst); |
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911 } |
304 | 912 |
913 void Assembler::adcl(Register dst, int32_t imm32) { | |
914 prefix(dst); | |
0 | 915 emit_arith(0x81, 0xD0, dst, imm32); |
916 } | |
917 | |
918 void Assembler::adcl(Register dst, Address src) { | |
919 InstructionMark im(this); | |
304 | 920 prefix(src, dst); |
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921 emit_int8(0x13); |
0 | 922 emit_operand(dst, src); |
923 } | |
924 | |
925 void Assembler::adcl(Register dst, Register src) { | |
304 | 926 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
0 | 927 emit_arith(0x13, 0xC0, dst, src); |
928 } | |
929 | |
304 | 930 void Assembler::addl(Address dst, int32_t imm32) { |
931 InstructionMark im(this); | |
932 prefix(dst); | |
933 emit_arith_operand(0x81, rax, dst, imm32); | |
934 } | |
0 | 935 |
936 void Assembler::addl(Address dst, Register src) { | |
937 InstructionMark im(this); | |
304 | 938 prefix(dst, src); |
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939 emit_int8(0x01); |
0 | 940 emit_operand(src, dst); |
941 } | |
942 | |
304 | 943 void Assembler::addl(Register dst, int32_t imm32) { |
944 prefix(dst); | |
0 | 945 emit_arith(0x81, 0xC0, dst, imm32); |
946 } | |
947 | |
948 void Assembler::addl(Register dst, Address src) { | |
949 InstructionMark im(this); | |
304 | 950 prefix(src, dst); |
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951 emit_int8(0x03); |
0 | 952 emit_operand(dst, src); |
953 } | |
954 | |
955 void Assembler::addl(Register dst, Register src) { | |
304 | 956 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
0 | 957 emit_arith(0x03, 0xC0, dst, src); |
958 } | |
959 | |
960 void Assembler::addr_nop_4() { | |
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961 assert(UseAddressNop, "no CPU support"); |
0 | 962 // 4 bytes: NOP DWORD PTR [EAX+0] |
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963 emit_int8(0x0F); |
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964 emit_int8(0x1F); |
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965 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc); |
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966 emit_int8(0); // 8-bits offset (1 byte) |
0 | 967 } |
968 | |
969 void Assembler::addr_nop_5() { | |
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970 assert(UseAddressNop, "no CPU support"); |
0 | 971 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset |
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972 emit_int8(0x0F); |
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973 emit_int8(0x1F); |
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974 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4); |
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975 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); |
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976 emit_int8(0); // 8-bits offset (1 byte) |
0 | 977 } |
978 | |
979 void Assembler::addr_nop_7() { | |
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980 assert(UseAddressNop, "no CPU support"); |
0 | 981 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset |
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982 emit_int8(0x0F); |
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983 emit_int8(0x1F); |
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984 emit_int8((unsigned char)0x80); |
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985 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc); |
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986 emit_int32(0); // 32-bits offset (4 bytes) |
0 | 987 } |
988 | |
989 void Assembler::addr_nop_8() { | |
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990 assert(UseAddressNop, "no CPU support"); |
0 | 991 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset |
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992 emit_int8(0x0F); |
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993 emit_int8(0x1F); |
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994 emit_int8((unsigned char)0x84); |
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995 // emit_rm(cbuf, 0x2, EAX_enc, 0x4); |
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996 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); |
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997 emit_int32(0); // 32-bits offset (4 bytes) |
0 | 998 } |
999 | |
304 | 1000 void Assembler::addsd(XMMRegister dst, XMMRegister src) { |
1001 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1002 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2); |
304 | 1003 } |
1004 | |
1005 void Assembler::addsd(XMMRegister dst, Address src) { | |
1006 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1007 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2); |
304 | 1008 } |
1009 | |
1010 void Assembler::addss(XMMRegister dst, XMMRegister src) { | |
1011 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1012 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3); |
304 | 1013 } |
1014 | |
1015 void Assembler::addss(XMMRegister dst, Address src) { | |
1016 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1017 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3); |
304 | 1018 } |
1019 | |
6894 | 1020 void Assembler::aesdec(XMMRegister dst, Address src) { |
1021 assert(VM_Version::supports_aes(), ""); | |
1022 InstructionMark im(this); | |
1023 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1024 emit_int8((unsigned char)0xDE); |
6894 | 1025 emit_operand(dst, src); |
1026 } | |
1027 | |
1028 void Assembler::aesdec(XMMRegister dst, XMMRegister src) { | |
1029 assert(VM_Version::supports_aes(), ""); | |
1030 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1031 emit_int8((unsigned char)0xDE); |
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1032 emit_int8(0xC0 | encode); |
6894 | 1033 } |
1034 | |
1035 void Assembler::aesdeclast(XMMRegister dst, Address src) { | |
1036 assert(VM_Version::supports_aes(), ""); | |
1037 InstructionMark im(this); | |
1038 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1039 emit_int8((unsigned char)0xDF); |
6894 | 1040 emit_operand(dst, src); |
1041 } | |
1042 | |
1043 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) { | |
1044 assert(VM_Version::supports_aes(), ""); | |
1045 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1046 emit_int8((unsigned char)0xDF); |
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1047 emit_int8((unsigned char)(0xC0 | encode)); |
6894 | 1048 } |
1049 | |
1050 void Assembler::aesenc(XMMRegister dst, Address src) { | |
1051 assert(VM_Version::supports_aes(), ""); | |
1052 InstructionMark im(this); | |
1053 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1054 emit_int8((unsigned char)0xDC); |
6894 | 1055 emit_operand(dst, src); |
1056 } | |
1057 | |
1058 void Assembler::aesenc(XMMRegister dst, XMMRegister src) { | |
1059 assert(VM_Version::supports_aes(), ""); | |
1060 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1061 emit_int8((unsigned char)0xDC); |
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1062 emit_int8(0xC0 | encode); |
6894 | 1063 } |
1064 | |
1065 void Assembler::aesenclast(XMMRegister dst, Address src) { | |
1066 assert(VM_Version::supports_aes(), ""); | |
1067 InstructionMark im(this); | |
1068 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1069 emit_int8((unsigned char)0xDD); |
6894 | 1070 emit_operand(dst, src); |
1071 } | |
1072 | |
1073 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) { | |
1074 assert(VM_Version::supports_aes(), ""); | |
1075 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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1076 emit_int8((unsigned char)0xDD); |
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1077 emit_int8((unsigned char)(0xC0 | encode)); |
6894 | 1078 } |
1079 | |
1080 | |
4759 | 1081 void Assembler::andl(Address dst, int32_t imm32) { |
1082 InstructionMark im(this); | |
1083 prefix(dst); | |
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1084 emit_int8((unsigned char)0x81); |
4759 | 1085 emit_operand(rsp, dst, 4); |
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1086 emit_int32(imm32); |
4759 | 1087 } |
1088 | |
304 | 1089 void Assembler::andl(Register dst, int32_t imm32) { |
1090 prefix(dst); | |
1091 emit_arith(0x81, 0xE0, dst, imm32); | |
1092 } | |
1093 | |
1094 void Assembler::andl(Register dst, Address src) { | |
1095 InstructionMark im(this); | |
1096 prefix(src, dst); | |
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1097 emit_int8(0x23); |
304 | 1098 emit_operand(dst, src); |
1099 } | |
1100 | |
1101 void Assembler::andl(Register dst, Register src) { | |
1102 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
1103 emit_arith(0x23, 0xC0, dst, src); | |
1104 } | |
1105 | |
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1106 void Assembler::bsfl(Register dst, Register src) { |
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1107 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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1108 emit_int8(0x0F); |
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1109 emit_int8((unsigned char)0xBC); |
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1110 emit_int8((unsigned char)(0xC0 | encode)); |
775
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1111 } |
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1112 |
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1113 void Assembler::bsrl(Register dst, Register src) { |
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1114 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT"); |
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1115 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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1116 emit_int8(0x0F); |
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1117 emit_int8((unsigned char)0xBD); |
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1118 emit_int8((unsigned char)(0xC0 | encode)); |
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1119 } |
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1120 |
304 | 1121 void Assembler::bswapl(Register reg) { // bswap |
1122 int encode = prefix_and_encode(reg->encoding()); | |
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1123 emit_int8(0x0F); |
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1124 emit_int8((unsigned char)(0xC8 | encode)); |
304 | 1125 } |
1126 | |
1127 void Assembler::call(Label& L, relocInfo::relocType rtype) { | |
1128 // suspect disp32 is always good | |
1129 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand); | |
1130 | |
1131 if (L.is_bound()) { | |
1132 const int long_size = 5; | |
1133 int offs = (int)( target(L) - pc() ); | |
1134 assert(offs <= 0, "assembler error"); | |
1135 InstructionMark im(this); | |
1136 // 1110 1000 #32-bit disp | |
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1137 emit_int8((unsigned char)0xE8); |
304 | 1138 emit_data(offs - long_size, rtype, operand); |
1139 } else { | |
1140 InstructionMark im(this); | |
1141 // 1110 1000 #32-bit disp | |
1142 L.add_patch_at(code(), locator()); | |
1143 | |
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1144 emit_int8((unsigned char)0xE8); |
304 | 1145 emit_data(int(0), rtype, operand); |
1146 } | |
1147 } | |
1148 | |
1149 void Assembler::call(Register dst) { | |
4759 | 1150 int encode = prefix_and_encode(dst->encoding()); |
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1151 emit_int8((unsigned char)0xFF); |
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1152 emit_int8((unsigned char)(0xD0 | encode)); |
304 | 1153 } |
1154 | |
1155 | |
1156 void Assembler::call(Address adr) { | |
1157 InstructionMark im(this); | |
1158 prefix(adr); | |
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1159 emit_int8((unsigned char)0xFF); |
304 | 1160 emit_operand(rdx, adr); |
1161 } | |
1162 | |
1163 void Assembler::call_literal(address entry, RelocationHolder const& rspec) { | |
1164 assert(entry != NULL, "call most probably wrong"); | |
1165 InstructionMark im(this); | |
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1166 emit_int8((unsigned char)0xE8); |
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1167 intptr_t disp = entry - (pc() + sizeof(int32_t)); |
304 | 1168 assert(is_simm32(disp), "must be 32bit offset (call2)"); |
1169 // Technically, should use call32_operand, but this format is | |
1170 // implied by the fact that we're emitting a call instruction. | |
1171 | |
1172 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand); | |
1173 emit_data((int) disp, rspec, operand); | |
1174 } | |
1175 | |
1176 void Assembler::cdql() { | |
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1177 emit_int8((unsigned char)0x99); |
304 | 1178 } |
1179 | |
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1180 void Assembler::cld() { |
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1181 emit_int8((unsigned char)0xFC); |
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1182 } |
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1183 |
304 | 1184 void Assembler::cmovl(Condition cc, Register dst, Register src) { |
1185 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); | |
1186 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
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1187 emit_int8(0x0F); |
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1188 emit_int8(0x40 | cc); |
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1189 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1190 } |
1191 | |
1192 | |
1193 void Assembler::cmovl(Condition cc, Register dst, Address src) { | |
1194 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); | |
1195 prefix(src, dst); | |
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1196 emit_int8(0x0F); |
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1197 emit_int8(0x40 | cc); |
304 | 1198 emit_operand(dst, src); |
1199 } | |
1200 | |
1201 void Assembler::cmpb(Address dst, int imm8) { | |
1202 InstructionMark im(this); | |
1203 prefix(dst); | |
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1204 emit_int8((unsigned char)0x80); |
304 | 1205 emit_operand(rdi, dst, 1); |
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1206 emit_int8(imm8); |
304 | 1207 } |
1208 | |
1209 void Assembler::cmpl(Address dst, int32_t imm32) { | |
1210 InstructionMark im(this); | |
1211 prefix(dst); | |
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1212 emit_int8((unsigned char)0x81); |
304 | 1213 emit_operand(rdi, dst, 4); |
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1214 emit_int32(imm32); |
304 | 1215 } |
1216 | |
1217 void Assembler::cmpl(Register dst, int32_t imm32) { | |
1218 prefix(dst); | |
1219 emit_arith(0x81, 0xF8, dst, imm32); | |
1220 } | |
1221 | |
1222 void Assembler::cmpl(Register dst, Register src) { | |
1223 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
1224 emit_arith(0x3B, 0xC0, dst, src); | |
1225 } | |
1226 | |
1227 | |
1228 void Assembler::cmpl(Register dst, Address src) { | |
1229 InstructionMark im(this); | |
1230 prefix(src, dst); | |
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1231 emit_int8((unsigned char)0x3B); |
304 | 1232 emit_operand(dst, src); |
1233 } | |
1234 | |
1235 void Assembler::cmpw(Address dst, int imm16) { | |
1236 InstructionMark im(this); | |
1237 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers"); | |
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1238 emit_int8(0x66); |
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1239 emit_int8((unsigned char)0x81); |
304 | 1240 emit_operand(rdi, dst, 2); |
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1241 emit_int16(imm16); |
304 | 1242 } |
1243 | |
1244 // The 32-bit cmpxchg compares the value at adr with the contents of rax, | |
1245 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,. | |
1246 // The ZF is set if the compared values were equal, and cleared otherwise. | |
1247 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg | |
6834 | 1248 InstructionMark im(this); |
1249 prefix(adr, reg); | |
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1250 emit_int8(0x0F); |
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1251 emit_int8((unsigned char)0xB1); |
6834 | 1252 emit_operand(reg, adr); |
304 | 1253 } |
1254 | |
1255 void Assembler::comisd(XMMRegister dst, Address src) { | |
1256 // NOTE: dbx seems to decode this as comiss even though the | |
1257 // 0x66 is there. Strangly ucomisd comes out correct | |
1258 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1259 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66); |
4759 | 1260 } |
1261 | |
1262 void Assembler::comisd(XMMRegister dst, XMMRegister src) { | |
1263 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1264 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66); |
304 | 1265 } |
1266 | |
1267 void Assembler::comiss(XMMRegister dst, Address src) { | |
1268 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1269 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE); |
304 | 1270 } |
1271 | |
4759 | 1272 void Assembler::comiss(XMMRegister dst, XMMRegister src) { |
1273 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1274 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE); |
4759 | 1275 } |
1276 | |
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1277 void Assembler::cpuid() { |
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1278 emit_int8(0x0F); |
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1279 emit_int8((unsigned char)0xA2); |
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1280 } |
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1281 |
304 | 1282 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) { |
1283 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1284 emit_simd_arith_nonds(0xE6, dst, src, VEX_SIMD_F3); |
304 | 1285 } |
1286 | |
1287 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) { | |
1288 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1289 emit_simd_arith_nonds(0x5B, dst, src, VEX_SIMD_NONE); |
304 | 1290 } |
1291 | |
1292 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) { | |
1293 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1294 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2); |
304 | 1295 } |
1296 | |
4759 | 1297 void Assembler::cvtsd2ss(XMMRegister dst, Address src) { |
1298 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1299 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2); |
4759 | 1300 } |
1301 | |
304 | 1302 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) { |
1303 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
4759 | 1304 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2); |
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1305 emit_int8(0x2A); |
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1306 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1307 } |
1308 | |
4759 | 1309 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) { |
1310 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1311 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F2); |
4759 | 1312 } |
1313 | |
304 | 1314 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) { |
1315 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
4759 | 1316 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3); |
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1317 emit_int8(0x2A); |
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1318 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1319 } |
1320 | |
4759 | 1321 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) { |
1322 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1323 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F3); |
4759 | 1324 } |
1325 | |
304 | 1326 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) { |
1327 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1328 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3); |
304 | 1329 } |
1330 | |
4759 | 1331 void Assembler::cvtss2sd(XMMRegister dst, Address src) { |
1332 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1333 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3); |
4759 | 1334 } |
1335 | |
1336 | |
304 | 1337 void Assembler::cvttsd2sil(Register dst, XMMRegister src) { |
1338 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
4759 | 1339 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2); |
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1340 emit_int8(0x2C); |
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1341 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1342 } |
1343 | |
1344 void Assembler::cvttss2sil(Register dst, XMMRegister src) { | |
1345 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
4759 | 1346 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3); |
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1347 emit_int8(0x2C); |
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1348 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1349 } |
1350 | |
1351 void Assembler::decl(Address dst) { | |
1352 // Don't use it directly. Use MacroAssembler::decrement() instead. | |
1353 InstructionMark im(this); | |
1354 prefix(dst); | |
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1355 emit_int8((unsigned char)0xFF); |
304 | 1356 emit_operand(rcx, dst); |
1357 } | |
1358 | |
1359 void Assembler::divsd(XMMRegister dst, Address src) { | |
1360 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1361 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2); |
304 | 1362 } |
1363 | |
1364 void Assembler::divsd(XMMRegister dst, XMMRegister src) { | |
1365 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1366 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2); |
304 | 1367 } |
1368 | |
1369 void Assembler::divss(XMMRegister dst, Address src) { | |
1370 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1371 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3); |
304 | 1372 } |
1373 | |
1374 void Assembler::divss(XMMRegister dst, XMMRegister src) { | |
1375 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1376 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3); |
304 | 1377 } |
1378 | |
1379 void Assembler::emms() { | |
1380 NOT_LP64(assert(VM_Version::supports_mmx(), "")); | |
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1381 emit_int8(0x0F); |
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1382 emit_int8(0x77); |
304 | 1383 } |
1384 | |
1385 void Assembler::hlt() { | |
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1386 emit_int8((unsigned char)0xF4); |
304 | 1387 } |
1388 | |
1389 void Assembler::idivl(Register src) { | |
1390 int encode = prefix_and_encode(src->encoding()); | |
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1391 emit_int8((unsigned char)0xF7); |
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1392 emit_int8((unsigned char)(0xF8 | encode)); |
304 | 1393 } |
1394 | |
1920 | 1395 void Assembler::divl(Register src) { // Unsigned |
1396 int encode = prefix_and_encode(src->encoding()); | |
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1397 emit_int8((unsigned char)0xF7); |
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1398 emit_int8((unsigned char)(0xF0 | encode)); |
1920 | 1399 } |
1400 | |
304 | 1401 void Assembler::imull(Register dst, Register src) { |
1402 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
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1403 emit_int8(0x0F); |
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1404 emit_int8((unsigned char)0xAF); |
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1405 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1406 } |
1407 | |
1408 | |
1409 void Assembler::imull(Register dst, Register src, int value) { | |
1410 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1411 if (is8bit(value)) { | |
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1412 emit_int8(0x6B); |
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1413 emit_int8((unsigned char)(0xC0 | encode)); |
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1414 emit_int8(value & 0xFF); |
304 | 1415 } else { |
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1416 emit_int8(0x69); |
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1417 emit_int8((unsigned char)(0xC0 | encode)); |
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1418 emit_int32(value); |
304 | 1419 } |
1420 } | |
1421 | |
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1422 void Assembler::imull(Register dst, Address src) { |
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1423 InstructionMark im(this); |
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1424 prefix(src, dst); |
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1425 emit_int8(0x0F); |
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1426 emit_int8((unsigned char) 0xAF); |
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1427 emit_operand(dst, src); |
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1428 } |
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1429 |
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1430 |
304 | 1431 void Assembler::incl(Address dst) { |
1432 // Don't use it directly. Use MacroAssembler::increment() instead. | |
1433 InstructionMark im(this); | |
1434 prefix(dst); | |
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1435 emit_int8((unsigned char)0xFF); |
304 | 1436 emit_operand(rax, dst); |
1437 } | |
1438 | |
3851 | 1439 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) { |
1440 InstructionMark im(this); | |
304 | 1441 assert((0 <= cc) && (cc < 16), "illegal cc"); |
1442 if (L.is_bound()) { | |
1443 address dst = target(L); | |
1444 assert(dst != NULL, "jcc most probably wrong"); | |
1445 | |
1446 const int short_size = 2; | |
1447 const int long_size = 6; | |
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1448 intptr_t offs = (intptr_t)dst - (intptr_t)pc(); |
3851 | 1449 if (maybe_short && is8bit(offs - short_size)) { |
304 | 1450 // 0111 tttn #8-bit disp |
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1451 emit_int8(0x70 | cc); |
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1452 emit_int8((offs - short_size) & 0xFF); |
304 | 1453 } else { |
1454 // 0000 1111 1000 tttn #32-bit disp | |
1455 assert(is_simm32(offs - long_size), | |
1456 "must be 32bit offset (call4)"); | |
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1457 emit_int8(0x0F); |
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1458 emit_int8((unsigned char)(0x80 | cc)); |
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1459 emit_int32(offs - long_size); |
304 | 1460 } |
1461 } else { | |
1462 // Note: could eliminate cond. jumps to this jump if condition | |
1463 // is the same however, seems to be rather unlikely case. | |
1464 // Note: use jccb() if label to be bound is very close to get | |
1465 // an 8-bit displacement | |
1466 L.add_patch_at(code(), locator()); | |
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1467 emit_int8(0x0F); |
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1468 emit_int8((unsigned char)(0x80 | cc)); |
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1469 emit_int32(0); |
304 | 1470 } |
1471 } | |
1472 | |
1473 void Assembler::jccb(Condition cc, Label& L) { | |
1474 if (L.is_bound()) { | |
1475 const int short_size = 2; | |
1476 address entry = target(L); | |
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1477 #ifdef ASSERT |
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1478 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size); |
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1479 intptr_t delta = short_branch_delta(); |
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1480 if (delta != 0) { |
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1481 dist += (dist < 0 ? (-delta) :delta); |
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1482 } |
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1483 assert(is8bit(dist), "Dispacement too large for a short jmp"); |
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1484 #endif |
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1485 intptr_t offs = (intptr_t)entry - (intptr_t)pc(); |
304 | 1486 // 0111 tttn #8-bit disp |
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1487 emit_int8(0x70 | cc); |
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1488 emit_int8((offs - short_size) & 0xFF); |
304 | 1489 } else { |
1490 InstructionMark im(this); | |
1491 L.add_patch_at(code(), locator()); | |
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1492 emit_int8(0x70 | cc); |
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1493 emit_int8(0); |
304 | 1494 } |
1495 } | |
1496 | |
1497 void Assembler::jmp(Address adr) { | |
1498 InstructionMark im(this); | |
1499 prefix(adr); | |
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1500 emit_int8((unsigned char)0xFF); |
304 | 1501 emit_operand(rsp, adr); |
1502 } | |
1503 | |
3851 | 1504 void Assembler::jmp(Label& L, bool maybe_short) { |
304 | 1505 if (L.is_bound()) { |
1506 address entry = target(L); | |
1507 assert(entry != NULL, "jmp most probably wrong"); | |
1508 InstructionMark im(this); | |
1509 const int short_size = 2; | |
1510 const int long_size = 5; | |
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1511 intptr_t offs = entry - pc(); |
3851 | 1512 if (maybe_short && is8bit(offs - short_size)) { |
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1513 emit_int8((unsigned char)0xEB); |
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1514 emit_int8((offs - short_size) & 0xFF); |
304 | 1515 } else { |
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1516 emit_int8((unsigned char)0xE9); |
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1517 emit_int32(offs - long_size); |
304 | 1518 } |
1519 } else { | |
1520 // By default, forward jumps are always 32-bit displacements, since | |
1521 // we can't yet know where the label will be bound. If you're sure that | |
1522 // the forward jump will not run beyond 256 bytes, use jmpb to | |
1523 // force an 8-bit displacement. | |
1524 InstructionMark im(this); | |
1525 L.add_patch_at(code(), locator()); | |
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1526 emit_int8((unsigned char)0xE9); |
7476
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1527 emit_int32(0); |
304 | 1528 } |
1529 } | |
1530 | |
1531 void Assembler::jmp(Register entry) { | |
1532 int encode = prefix_and_encode(entry->encoding()); | |
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1533 emit_int8((unsigned char)0xFF); |
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1534 emit_int8((unsigned char)(0xE0 | encode)); |
304 | 1535 } |
1536 | |
1537 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) { | |
1538 InstructionMark im(this); | |
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1539 emit_int8((unsigned char)0xE9); |
304 | 1540 assert(dest != NULL, "must have a target"); |
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1541 intptr_t disp = dest - (pc() + sizeof(int32_t)); |
304 | 1542 assert(is_simm32(disp), "must be 32bit offset (jmp)"); |
1543 emit_data(disp, rspec.reloc(), call32_operand); | |
1544 } | |
1545 | |
1546 void Assembler::jmpb(Label& L) { | |
1547 if (L.is_bound()) { | |
1548 const int short_size = 2; | |
1549 address entry = target(L); | |
1550 assert(entry != NULL, "jmp most probably wrong"); | |
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1551 #ifdef ASSERT |
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1552 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size); |
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1553 intptr_t delta = short_branch_delta(); |
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1554 if (delta != 0) { |
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1555 dist += (dist < 0 ? (-delta) :delta); |
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1556 } |
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1557 assert(is8bit(dist), "Dispacement too large for a short jmp"); |
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1558 #endif |
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1559 intptr_t offs = entry - pc(); |
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1560 emit_int8((unsigned char)0xEB); |
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1561 emit_int8((offs - short_size) & 0xFF); |
304 | 1562 } else { |
1563 InstructionMark im(this); | |
1564 L.add_patch_at(code(), locator()); | |
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1565 emit_int8((unsigned char)0xEB); |
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1566 emit_int8(0); |
304 | 1567 } |
1568 } | |
1569 | |
1570 void Assembler::ldmxcsr( Address src) { | |
1571 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1572 InstructionMark im(this); | |
1573 prefix(src); | |
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1574 emit_int8(0x0F); |
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1575 emit_int8((unsigned char)0xAE); |
304 | 1576 emit_operand(as_Register(2), src); |
1577 } | |
1578 | |
1579 void Assembler::leal(Register dst, Address src) { | |
1580 InstructionMark im(this); | |
1581 #ifdef _LP64 | |
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1582 emit_int8(0x67); // addr32 |
304 | 1583 prefix(src, dst); |
1584 #endif // LP64 | |
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1585 emit_int8((unsigned char)0x8D); |
304 | 1586 emit_operand(dst, src); |
1587 } | |
1588 | |
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1589 void Assembler::lfence() { |
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1590 emit_int8(0x0F); |
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1591 emit_int8((unsigned char)0xAE); |
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1592 emit_int8((unsigned char)0xE8); |
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1593 } |
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1594 |
304 | 1595 void Assembler::lock() { |
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1596 emit_int8((unsigned char)0xF0); |
304 | 1597 } |
1598 | |
775
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1599 void Assembler::lzcntl(Register dst, Register src) { |
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1600 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); |
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1601 emit_int8((unsigned char)0xF3); |
775
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|
1602 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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1603 emit_int8(0x0F); |
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1604 emit_int8((unsigned char)0xBD); |
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|
1605 emit_int8((unsigned char)(0xC0 | encode)); |
775
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1606 } |
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1607 |
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|
1608 // Emit mfence instruction |
304 | 1609 void Assembler::mfence() { |
671
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|
1610 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");) |
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1611 emit_int8(0x0F); |
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1612 emit_int8((unsigned char)0xAE); |
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1613 emit_int8((unsigned char)0xF0); |
304 | 1614 } |
1615 | |
1616 void Assembler::mov(Register dst, Register src) { | |
1617 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
1618 } | |
1619 | |
1620 void Assembler::movapd(XMMRegister dst, XMMRegister src) { | |
1621 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1622 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_66); |
304 | 1623 } |
1624 | |
1625 void Assembler::movaps(XMMRegister dst, XMMRegister src) { | |
1626 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1627 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_NONE); |
304 | 1628 } |
1629 | |
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1630 void Assembler::movlhps(XMMRegister dst, XMMRegister src) { |
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|
1631 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
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1632 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE); |
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|
1633 emit_int8(0x16); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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|
1634 emit_int8((unsigned char)(0xC0 | encode)); |
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1635 } |
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|
1636 |
304 | 1637 void Assembler::movb(Register dst, Address src) { |
1638 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); | |
1639 InstructionMark im(this); | |
1640 prefix(src, dst, true); | |
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|
1641 emit_int8((unsigned char)0x8A); |
304 | 1642 emit_operand(dst, src); |
1643 } | |
1644 | |
1645 | |
1646 void Assembler::movb(Address dst, int imm8) { | |
1647 InstructionMark im(this); | |
1648 prefix(dst); | |
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|
1649 emit_int8((unsigned char)0xC6); |
304 | 1650 emit_operand(rax, dst, 1); |
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|
1651 emit_int8(imm8); |
304 | 1652 } |
1653 | |
1654 | |
1655 void Assembler::movb(Address dst, Register src) { | |
1656 assert(src->has_byte_register(), "must have byte register"); | |
1657 InstructionMark im(this); | |
1658 prefix(dst, src, true); | |
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|
1659 emit_int8((unsigned char)0x88); |
304 | 1660 emit_operand(src, dst); |
1661 } | |
1662 | |
1663 void Assembler::movdl(XMMRegister dst, Register src) { | |
1664 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
4759 | 1665 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66); |
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|
1666 emit_int8(0x6E); |
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|
1667 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1668 } |
1669 | |
1670 void Assembler::movdl(Register dst, XMMRegister src) { | |
1671 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1672 // swap src/dst to get correct prefix | |
4759 | 1673 int encode = simd_prefix_and_encode(src, dst, VEX_SIMD_66); |
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|
1674 emit_int8(0x7E); |
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|
1675 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1676 } |
1677 | |
2320
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|
1678 void Assembler::movdl(XMMRegister dst, Address src) { |
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|
1679 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
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|
1680 InstructionMark im(this); |
4759 | 1681 simd_prefix(dst, src, VEX_SIMD_66); |
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|
1682 emit_int8(0x6E); |
2320
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|
1683 emit_operand(dst, src); |
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|
1684 } |
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|
1685 |
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1686 void Assembler::movdl(Address dst, XMMRegister src) { |
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|
1687 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
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|
1688 InstructionMark im(this); |
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|
1689 simd_prefix(dst, src, VEX_SIMD_66); |
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|
1690 emit_int8(0x7E); |
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|
1691 emit_operand(src, dst); |
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|
1692 } |
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|
1693 |
304 | 1694 void Assembler::movdqa(XMMRegister dst, XMMRegister src) { |
1695 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1696 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66); |
304 | 1697 } |
1698 | |
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|
1699 void Assembler::movdqa(XMMRegister dst, Address src) { |
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1700 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
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1701 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66); |
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1702 } |
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|
1703 |
405 | 1704 void Assembler::movdqu(XMMRegister dst, Address src) { |
1705 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1706 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3); |
405 | 1707 } |
1708 | |
1709 void Assembler::movdqu(XMMRegister dst, XMMRegister src) { | |
1710 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1711 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3); |
405 | 1712 } |
1713 | |
1714 void Assembler::movdqu(Address dst, XMMRegister src) { | |
1715 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1716 InstructionMark im(this); | |
4759 | 1717 simd_prefix(dst, src, VEX_SIMD_F3); |
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|
1718 emit_int8(0x7F); |
405 | 1719 emit_operand(src, dst); |
1720 } | |
1721 | |
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|
1722 // Move Unaligned 256bit Vector |
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1723 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) { |
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1724 assert(UseAVX, ""); |
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1725 bool vector256 = true; |
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1726 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, vector256); |
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1727 emit_int8(0x6F); |
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1728 emit_int8((unsigned char)(0xC0 | encode)); |
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1729 } |
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1730 |
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1731 void Assembler::vmovdqu(XMMRegister dst, Address src) { |
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1732 assert(UseAVX, ""); |
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1733 InstructionMark im(this); |
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1734 bool vector256 = true; |
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1735 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector256); |
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1736 emit_int8(0x6F); |
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1737 emit_operand(dst, src); |
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1738 } |
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1739 |
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1740 void Assembler::vmovdqu(Address dst, XMMRegister src) { |
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1741 assert(UseAVX, ""); |
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1742 InstructionMark im(this); |
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1743 bool vector256 = true; |
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1744 // swap src<->dst for encoding |
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1745 assert(src != xnoreg, "sanity"); |
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1746 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector256); |
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1747 emit_int8(0x7F); |
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1748 emit_operand(src, dst); |
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1749 } |
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1750 |
304 | 1751 // Uses zero extension on 64bit |
1752 | |
1753 void Assembler::movl(Register dst, int32_t imm32) { | |
1754 int encode = prefix_and_encode(dst->encoding()); | |
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1755 emit_int8((unsigned char)(0xB8 | encode)); |
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1756 emit_int32(imm32); |
304 | 1757 } |
1758 | |
1759 void Assembler::movl(Register dst, Register src) { | |
1760 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
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1761 emit_int8((unsigned char)0x8B); |
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1762 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1763 } |
1764 | |
1765 void Assembler::movl(Register dst, Address src) { | |
1766 InstructionMark im(this); | |
1767 prefix(src, dst); | |
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1768 emit_int8((unsigned char)0x8B); |
304 | 1769 emit_operand(dst, src); |
1770 } | |
1771 | |
1772 void Assembler::movl(Address dst, int32_t imm32) { | |
1773 InstructionMark im(this); | |
1774 prefix(dst); | |
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1775 emit_int8((unsigned char)0xC7); |
304 | 1776 emit_operand(rax, dst, 4); |
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1777 emit_int32(imm32); |
304 | 1778 } |
1779 | |
1780 void Assembler::movl(Address dst, Register src) { | |
1781 InstructionMark im(this); | |
1782 prefix(dst, src); | |
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1783 emit_int8((unsigned char)0x89); |
304 | 1784 emit_operand(src, dst); |
1785 } | |
1786 | |
1787 // New cpus require to use movsd and movss to avoid partial register stall | |
1788 // when loading from memory. But for old Opteron use movlpd instead of movsd. | |
1789 // The selection is done in MacroAssembler::movdbl() and movflt(). | |
1790 void Assembler::movlpd(XMMRegister dst, Address src) { | |
1791 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1792 emit_simd_arith(0x12, dst, src, VEX_SIMD_66); |
304 | 1793 } |
1794 | |
1795 void Assembler::movq( MMXRegister dst, Address src ) { | |
1796 assert( VM_Version::supports_mmx(), "" ); | |
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1797 emit_int8(0x0F); |
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1798 emit_int8(0x6F); |
304 | 1799 emit_operand(dst, src); |
1800 } | |
1801 | |
1802 void Assembler::movq( Address dst, MMXRegister src ) { | |
1803 assert( VM_Version::supports_mmx(), "" ); | |
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1804 emit_int8(0x0F); |
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1805 emit_int8(0x7F); |
304 | 1806 // workaround gcc (3.2.1-7a) bug |
1807 // In that version of gcc with only an emit_operand(MMX, Address) | |
1808 // gcc will tail jump and try and reverse the parameters completely | |
1809 // obliterating dst in the process. By having a version available | |
1810 // that doesn't need to swap the args at the tail jump the bug is | |
1811 // avoided. | |
1812 emit_operand(dst, src); | |
1813 } | |
1814 | |
1815 void Assembler::movq(XMMRegister dst, Address src) { | |
1816 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1817 InstructionMark im(this); | |
4759 | 1818 simd_prefix(dst, src, VEX_SIMD_F3); |
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1819 emit_int8(0x7E); |
304 | 1820 emit_operand(dst, src); |
1821 } | |
1822 | |
1823 void Assembler::movq(Address dst, XMMRegister src) { | |
1824 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1825 InstructionMark im(this); | |
4759 | 1826 simd_prefix(dst, src, VEX_SIMD_66); |
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1827 emit_int8((unsigned char)0xD6); |
304 | 1828 emit_operand(src, dst); |
1829 } | |
1830 | |
1831 void Assembler::movsbl(Register dst, Address src) { // movsxb | |
1832 InstructionMark im(this); | |
1833 prefix(src, dst); | |
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1834 emit_int8(0x0F); |
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1835 emit_int8((unsigned char)0xBE); |
304 | 1836 emit_operand(dst, src); |
1837 } | |
1838 | |
1839 void Assembler::movsbl(Register dst, Register src) { // movsxb | |
1840 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); | |
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1841 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true); |
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1842 emit_int8(0x0F); |
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1843 emit_int8((unsigned char)0xBE); |
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1844 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1845 } |
1846 | |
1847 void Assembler::movsd(XMMRegister dst, XMMRegister src) { | |
1848 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1849 emit_simd_arith(0x10, dst, src, VEX_SIMD_F2); |
304 | 1850 } |
1851 | |
1852 void Assembler::movsd(XMMRegister dst, Address src) { | |
1853 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1854 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F2); |
304 | 1855 } |
1856 | |
1857 void Assembler::movsd(Address dst, XMMRegister src) { | |
1858 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1859 InstructionMark im(this); | |
4759 | 1860 simd_prefix(dst, src, VEX_SIMD_F2); |
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1861 emit_int8(0x11); |
304 | 1862 emit_operand(src, dst); |
1863 } | |
1864 | |
1865 void Assembler::movss(XMMRegister dst, XMMRegister src) { | |
1866 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1867 emit_simd_arith(0x10, dst, src, VEX_SIMD_F3); |
304 | 1868 } |
1869 | |
1870 void Assembler::movss(XMMRegister dst, Address src) { | |
1871 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1872 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F3); |
304 | 1873 } |
1874 | |
1875 void Assembler::movss(Address dst, XMMRegister src) { | |
1876 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1877 InstructionMark im(this); | |
4759 | 1878 simd_prefix(dst, src, VEX_SIMD_F3); |
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1879 emit_int8(0x11); |
304 | 1880 emit_operand(src, dst); |
1881 } | |
1882 | |
1883 void Assembler::movswl(Register dst, Address src) { // movsxw | |
1884 InstructionMark im(this); | |
1885 prefix(src, dst); | |
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1886 emit_int8(0x0F); |
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1887 emit_int8((unsigned char)0xBF); |
304 | 1888 emit_operand(dst, src); |
1889 } | |
1890 | |
1891 void Assembler::movswl(Register dst, Register src) { // movsxw | |
1892 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
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1893 emit_int8(0x0F); |
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1894 emit_int8((unsigned char)0xBF); |
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1895 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 1896 } |
1897 | |
1898 void Assembler::movw(Address dst, int imm16) { | |
1899 InstructionMark im(this); | |
1900 | |
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1901 emit_int8(0x66); // switch to 16-bit mode |
304 | 1902 prefix(dst); |
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1903 emit_int8((unsigned char)0xC7); |
304 | 1904 emit_operand(rax, dst, 2); |
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1905 emit_int16(imm16); |
304 | 1906 } |
1907 | |
1908 void Assembler::movw(Register dst, Address src) { | |
1909 InstructionMark im(this); | |
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1910 emit_int8(0x66); |
304 | 1911 prefix(src, dst); |
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1912 emit_int8((unsigned char)0x8B); |
304 | 1913 emit_operand(dst, src); |
1914 } | |
1915 | |
1916 void Assembler::movw(Address dst, Register src) { | |
1917 InstructionMark im(this); | |
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1918 emit_int8(0x66); |
304 | 1919 prefix(dst, src); |
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1920 emit_int8((unsigned char)0x89); |
304 | 1921 emit_operand(src, dst); |
1922 } | |
1923 | |
1924 void Assembler::movzbl(Register dst, Address src) { // movzxb | |
1925 InstructionMark im(this); | |
1926 prefix(src, dst); | |
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1927 emit_int8(0x0F); |
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1928 emit_int8((unsigned char)0xB6); |
304 | 1929 emit_operand(dst, src); |
1930 } | |
1931 | |
1932 void Assembler::movzbl(Register dst, Register src) { // movzxb | |
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1933 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); |
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1934 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true); |
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1935 emit_int8(0x0F); |
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1936 emit_int8((unsigned char)0xB6); |
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1937 emit_int8(0xC0 | encode); |
304 | 1938 } |
1939 | |
1940 void Assembler::movzwl(Register dst, Address src) { // movzxw | |
1941 InstructionMark im(this); | |
1942 prefix(src, dst); | |
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1943 emit_int8(0x0F); |
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1944 emit_int8((unsigned char)0xB7); |
304 | 1945 emit_operand(dst, src); |
1946 } | |
1947 | |
1948 void Assembler::movzwl(Register dst, Register src) { // movzxw | |
1949 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
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1950 emit_int8(0x0F); |
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1951 emit_int8((unsigned char)0xB7); |
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1952 emit_int8(0xC0 | encode); |
304 | 1953 } |
1954 | |
1955 void Assembler::mull(Address src) { | |
1956 InstructionMark im(this); | |
1957 prefix(src); | |
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1958 emit_int8((unsigned char)0xF7); |
304 | 1959 emit_operand(rsp, src); |
1960 } | |
1961 | |
1962 void Assembler::mull(Register src) { | |
1963 int encode = prefix_and_encode(src->encoding()); | |
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1964 emit_int8((unsigned char)0xF7); |
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1965 emit_int8((unsigned char)(0xE0 | encode)); |
304 | 1966 } |
1967 | |
1968 void Assembler::mulsd(XMMRegister dst, Address src) { | |
1969 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1970 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2); |
304 | 1971 } |
1972 | |
1973 void Assembler::mulsd(XMMRegister dst, XMMRegister src) { | |
1974 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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1975 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2); |
304 | 1976 } |
1977 | |
1978 void Assembler::mulss(XMMRegister dst, Address src) { | |
1979 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1980 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3); |
304 | 1981 } |
1982 | |
1983 void Assembler::mulss(XMMRegister dst, XMMRegister src) { | |
1984 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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1985 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3); |
304 | 1986 } |
1987 | |
1988 void Assembler::negl(Register dst) { | |
1989 int encode = prefix_and_encode(dst->encoding()); | |
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1990 emit_int8((unsigned char)0xF7); |
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1991 emit_int8((unsigned char)(0xD8 | encode)); |
304 | 1992 } |
1993 | |
0 | 1994 void Assembler::nop(int i) { |
304 | 1995 #ifdef ASSERT |
0 | 1996 assert(i > 0, " "); |
304 | 1997 // The fancy nops aren't currently recognized by debuggers making it a |
1998 // pain to disassemble code while debugging. If asserts are on clearly | |
1999 // speed is not an issue so simply use the single byte traditional nop | |
2000 // to do alignment. | |
2001 | |
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2002 for (; i > 0 ; i--) emit_int8((unsigned char)0x90); |
304 | 2003 return; |
2004 | |
2005 #endif // ASSERT | |
2006 | |
0 | 2007 if (UseAddressNop && VM_Version::is_intel()) { |
2008 // | |
2009 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel | |
2010 // 1: 0x90 | |
2011 // 2: 0x66 0x90 | |
2012 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) | |
2013 // 4: 0x0F 0x1F 0x40 0x00 | |
2014 // 5: 0x0F 0x1F 0x44 0x00 0x00 | |
2015 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
2016 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
2017 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2018 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2019 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2020 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2021 | |
2022 // The rest coding is Intel specific - don't use consecutive address nops | |
2023 | |
2024 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
2025 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
2026 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
2027 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
2028 | |
2029 while(i >= 15) { | |
2030 // For Intel don't generate consecutive addess nops (mix with regular nops) | |
2031 i -= 15; | |
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2032 emit_int8(0x66); // size prefix |
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2033 emit_int8(0x66); // size prefix |
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2034 emit_int8(0x66); // size prefix |
0 | 2035 addr_nop_8(); |
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2036 emit_int8(0x66); // size prefix |
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2037 emit_int8(0x66); // size prefix |
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2038 emit_int8(0x66); // size prefix |
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2039 emit_int8((unsigned char)0x90); |
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2040 // nop |
0 | 2041 } |
2042 switch (i) { | |
2043 case 14: | |
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2044 emit_int8(0x66); // size prefix |
0 | 2045 case 13: |
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2046 emit_int8(0x66); // size prefix |
0 | 2047 case 12: |
2048 addr_nop_8(); | |
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2049 emit_int8(0x66); // size prefix |
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2050 emit_int8(0x66); // size prefix |
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2051 emit_int8(0x66); // size prefix |
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2052 emit_int8((unsigned char)0x90); |
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2053 // nop |
0 | 2054 break; |
2055 case 11: | |
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2056 emit_int8(0x66); // size prefix |
0 | 2057 case 10: |
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2058 emit_int8(0x66); // size prefix |
0 | 2059 case 9: |
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2060 emit_int8(0x66); // size prefix |
0 | 2061 case 8: |
2062 addr_nop_8(); | |
2063 break; | |
2064 case 7: | |
2065 addr_nop_7(); | |
2066 break; | |
2067 case 6: | |
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2068 emit_int8(0x66); // size prefix |
0 | 2069 case 5: |
2070 addr_nop_5(); | |
2071 break; | |
2072 case 4: | |
2073 addr_nop_4(); | |
2074 break; | |
2075 case 3: | |
2076 // Don't use "0x0F 0x1F 0x00" - need patching safe padding | |
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2077 emit_int8(0x66); // size prefix |
0 | 2078 case 2: |
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2079 emit_int8(0x66); // size prefix |
0 | 2080 case 1: |
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2081 emit_int8((unsigned char)0x90); |
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2082 // nop |
0 | 2083 break; |
2084 default: | |
2085 assert(i == 0, " "); | |
2086 } | |
2087 return; | |
2088 } | |
2089 if (UseAddressNop && VM_Version::is_amd()) { | |
2090 // | |
2091 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD. | |
2092 // 1: 0x90 | |
2093 // 2: 0x66 0x90 | |
2094 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) | |
2095 // 4: 0x0F 0x1F 0x40 0x00 | |
2096 // 5: 0x0F 0x1F 0x44 0x00 0x00 | |
2097 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
2098 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
2099 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2100 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2101 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2102 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2103 | |
2104 // The rest coding is AMD specific - use consecutive address nops | |
2105 | |
2106 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
2107 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
2108 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
2109 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
2110 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2111 // Size prefixes (0x66) are added for larger sizes | |
2112 | |
2113 while(i >= 22) { | |
2114 i -= 11; | |
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2115 emit_int8(0x66); // size prefix |
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2116 emit_int8(0x66); // size prefix |
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2117 emit_int8(0x66); // size prefix |
0 | 2118 addr_nop_8(); |
2119 } | |
2120 // Generate first nop for size between 21-12 | |
2121 switch (i) { | |
2122 case 21: | |
2123 i -= 1; | |
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2124 emit_int8(0x66); // size prefix |
0 | 2125 case 20: |
2126 case 19: | |
2127 i -= 1; | |
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2128 emit_int8(0x66); // size prefix |
0 | 2129 case 18: |
2130 case 17: | |
2131 i -= 1; | |
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2132 emit_int8(0x66); // size prefix |
0 | 2133 case 16: |
2134 case 15: | |
2135 i -= 8; | |
2136 addr_nop_8(); | |
2137 break; | |
2138 case 14: | |
2139 case 13: | |
2140 i -= 7; | |
2141 addr_nop_7(); | |
2142 break; | |
2143 case 12: | |
2144 i -= 6; | |
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2145 emit_int8(0x66); // size prefix |
0 | 2146 addr_nop_5(); |
2147 break; | |
2148 default: | |
2149 assert(i < 12, " "); | |
2150 } | |
2151 | |
2152 // Generate second nop for size between 11-1 | |
2153 switch (i) { | |
2154 case 11: | |
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2155 emit_int8(0x66); // size prefix |
0 | 2156 case 10: |
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2157 emit_int8(0x66); // size prefix |
0 | 2158 case 9: |
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2159 emit_int8(0x66); // size prefix |
0 | 2160 case 8: |
2161 addr_nop_8(); | |
2162 break; | |
2163 case 7: | |
2164 addr_nop_7(); | |
2165 break; | |
2166 case 6: | |
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2167 emit_int8(0x66); // size prefix |
0 | 2168 case 5: |
2169 addr_nop_5(); | |
2170 break; | |
2171 case 4: | |
2172 addr_nop_4(); | |
2173 break; | |
2174 case 3: | |
2175 // Don't use "0x0F 0x1F 0x00" - need patching safe padding | |
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2176 emit_int8(0x66); // size prefix |
0 | 2177 case 2: |
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2178 emit_int8(0x66); // size prefix |
0 | 2179 case 1: |
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2180 emit_int8((unsigned char)0x90); |
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2181 // nop |
0 | 2182 break; |
2183 default: | |
2184 assert(i == 0, " "); | |
2185 } | |
2186 return; | |
2187 } | |
2188 | |
2189 // Using nops with size prefixes "0x66 0x90". | |
2190 // From AMD Optimization Guide: | |
2191 // 1: 0x90 | |
2192 // 2: 0x66 0x90 | |
2193 // 3: 0x66 0x66 0x90 | |
2194 // 4: 0x66 0x66 0x66 0x90 | |
2195 // 5: 0x66 0x66 0x90 0x66 0x90 | |
2196 // 6: 0x66 0x66 0x90 0x66 0x66 0x90 | |
2197 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 | |
2198 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90 | |
2199 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 | |
2200 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 | |
2201 // | |
2202 while(i > 12) { | |
2203 i -= 4; | |
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2204 emit_int8(0x66); // size prefix |
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2205 emit_int8(0x66); |
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2206 emit_int8(0x66); |
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2207 emit_int8((unsigned char)0x90); |
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2208 // nop |
0 | 2209 } |
2210 // 1 - 12 nops | |
2211 if(i > 8) { | |
2212 if(i > 9) { | |
2213 i -= 1; | |
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2214 emit_int8(0x66); |
0 | 2215 } |
2216 i -= 3; | |
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2217 emit_int8(0x66); |
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2218 emit_int8(0x66); |
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2219 emit_int8((unsigned char)0x90); |
0 | 2220 } |
2221 // 1 - 8 nops | |
2222 if(i > 4) { | |
2223 if(i > 6) { | |
2224 i -= 1; | |
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2225 emit_int8(0x66); |
0 | 2226 } |
2227 i -= 3; | |
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2228 emit_int8(0x66); |
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2229 emit_int8(0x66); |
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2230 emit_int8((unsigned char)0x90); |
0 | 2231 } |
2232 switch (i) { | |
2233 case 4: | |
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2234 emit_int8(0x66); |
0 | 2235 case 3: |
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|
2236 emit_int8(0x66); |
0 | 2237 case 2: |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
2238 emit_int8(0x66); |
0 | 2239 case 1: |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
2240 emit_int8((unsigned char)0x90); |
0 | 2241 break; |
2242 default: | |
2243 assert(i == 0, " "); | |
2244 } | |
2245 } | |
2246 | |
304 | 2247 void Assembler::notl(Register dst) { |
2248 int encode = prefix_and_encode(dst->encoding()); | |
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|
2249 emit_int8((unsigned char)0xF7); |
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|
2250 emit_int8((unsigned char)(0xD0 | encode)); |
304 | 2251 } |
2252 | |
2253 void Assembler::orl(Address dst, int32_t imm32) { | |
2254 InstructionMark im(this); | |
2255 prefix(dst); | |
2100
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changeset
|
2256 emit_arith_operand(0x81, rcx, dst, imm32); |
304 | 2257 } |
2258 | |
2259 void Assembler::orl(Register dst, int32_t imm32) { | |
2260 prefix(dst); | |
2261 emit_arith(0x81, 0xC8, dst, imm32); | |
2262 } | |
2263 | |
2264 void Assembler::orl(Register dst, Address src) { | |
2265 InstructionMark im(this); | |
2266 prefix(src, dst); | |
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|
2267 emit_int8(0x0B); |
304 | 2268 emit_operand(dst, src); |
2269 } | |
2270 | |
2271 void Assembler::orl(Register dst, Register src) { | |
2272 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
2273 emit_arith(0x0B, 0xC0, dst, src); | |
2274 } | |
2275 | |
4759 | 2276 void Assembler::packuswb(XMMRegister dst, Address src) { |
2277 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2278 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
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|
2279 emit_simd_arith(0x67, dst, src, VEX_SIMD_66); |
4759 | 2280 } |
2281 | |
2282 void Assembler::packuswb(XMMRegister dst, XMMRegister src) { | |
2283 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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|
2284 emit_simd_arith(0x67, dst, src, VEX_SIMD_66); |
4759 | 2285 } |
2286 | |
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|
2287 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
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|
2288 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
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|
2289 emit_vex_arith(0x67, dst, nds, src, VEX_SIMD_66, vector256); |
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|
2290 } |
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|
2291 |
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|
2292 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, bool vector256) { |
8042
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|
2293 assert(VM_Version::supports_avx2(), ""); |
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|
2294 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, true, vector256); |
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|
2295 emit_int8(0x00); |
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|
2296 emit_int8(0xC0 | encode); |
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|
2297 emit_int8(imm8); |
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2298 } |
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|
2299 |
681 | 2300 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) { |
2301 assert(VM_Version::supports_sse4_2(), ""); | |
4759 | 2302 InstructionMark im(this); |
2303 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A); | |
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|
2304 emit_int8(0x61); |
681 | 2305 emit_operand(dst, src); |
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|
2306 emit_int8(imm8); |
681 | 2307 } |
2308 | |
2309 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { | |
2310 assert(VM_Version::supports_sse4_2(), ""); | |
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|
2311 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A); |
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|
2312 emit_int8(0x61); |
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|
2313 emit_int8((unsigned char)(0xC0 | encode)); |
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|
2314 emit_int8(imm8); |
681 | 2315 } |
2316 | |
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2317 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) { |
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|
2318 assert(VM_Version::supports_sse4_1(), ""); |
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2319 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, false); |
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|
2320 emit_int8(0x16); |
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|
2321 emit_int8((unsigned char)(0xC0 | encode)); |
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|
2322 emit_int8(imm8); |
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2323 } |
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|
2324 |
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2325 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) { |
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2326 assert(VM_Version::supports_sse4_1(), ""); |
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2327 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, true); |
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|
2328 emit_int8(0x16); |
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|
2329 emit_int8((unsigned char)(0xC0 | encode)); |
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|
2330 emit_int8(imm8); |
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2331 } |
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|
2332 |
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2333 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) { |
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2334 assert(VM_Version::supports_sse4_1(), ""); |
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|
2335 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, false); |
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|
2336 emit_int8(0x22); |
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|
2337 emit_int8((unsigned char)(0xC0 | encode)); |
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|
2338 emit_int8(imm8); |
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2339 } |
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|
2340 |
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2341 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) { |
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|
2342 assert(VM_Version::supports_sse4_1(), ""); |
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|
2343 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, true); |
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|
2344 emit_int8(0x22); |
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|
2345 emit_int8((unsigned char)(0xC0 | encode)); |
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|
2346 emit_int8(imm8); |
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|
2347 } |
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|
2348 |
4759 | 2349 void Assembler::pmovzxbw(XMMRegister dst, Address src) { |
2350 assert(VM_Version::supports_sse4_1(), ""); | |
2351 InstructionMark im(this); | |
2352 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
7430
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changeset
|
2353 emit_int8(0x30); |
4759 | 2354 emit_operand(dst, src); |
2355 } | |
2356 | |
2357 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) { | |
2358 assert(VM_Version::supports_sse4_1(), ""); | |
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|
2359 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
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|
2360 emit_int8(0x30); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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|
2361 emit_int8((unsigned char)(0xC0 | encode)); |
4759 | 2362 } |
2363 | |
304 | 2364 // generic |
2365 void Assembler::pop(Register dst) { | |
2366 int encode = prefix_and_encode(dst->encoding()); | |
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|
2367 emit_int8(0x58 | encode); |
304 | 2368 } |
2369 | |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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|
2370 void Assembler::popcntl(Register dst, Address src) { |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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|
2371 assert(VM_Version::supports_popcnt(), "must support"); |
c771b7f43bbf
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|
2372 InstructionMark im(this); |
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|
2373 emit_int8((unsigned char)0xF3); |
643
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changeset
|
2374 prefix(src, dst); |
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|
2375 emit_int8(0x0F); |
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|
2376 emit_int8((unsigned char)0xB8); |
643
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|
2377 emit_operand(dst, src); |
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|
2378 } |
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|
2379 |
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2380 void Assembler::popcntl(Register dst, Register src) { |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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|
2381 assert(VM_Version::supports_popcnt(), "must support"); |
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changeset
|
2382 emit_int8((unsigned char)0xF3); |
643
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changeset
|
2383 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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|
2384 emit_int8(0x0F); |
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changeset
|
2385 emit_int8((unsigned char)0xB8); |
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changeset
|
2386 emit_int8((unsigned char)(0xC0 | encode)); |
643
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|
2387 } |
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2388 |
304 | 2389 void Assembler::popf() { |
7430
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|
2390 emit_int8((unsigned char)0x9D); |
304 | 2391 } |
2392 | |
1060 | 2393 #ifndef _LP64 // no 32bit push/pop on amd64 |
304 | 2394 void Assembler::popl(Address dst) { |
2395 // NOTE: this will adjust stack by 8byte on 64bits | |
2396 InstructionMark im(this); | |
2397 prefix(dst); | |
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|
2398 emit_int8((unsigned char)0x8F); |
304 | 2399 emit_operand(rax, dst); |
2400 } | |
1060 | 2401 #endif |
304 | 2402 |
2403 void Assembler::prefetch_prefix(Address src) { | |
2404 prefix(src); | |
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|
2405 emit_int8(0x0F); |
304 | 2406 } |
2407 | |
2408 void Assembler::prefetchnta(Address src) { | |
3873
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|
2409 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); |
304 | 2410 InstructionMark im(this); |
2411 prefetch_prefix(src); | |
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|
2412 emit_int8(0x18); |
304 | 2413 emit_operand(rax, src); // 0, src |
2414 } | |
2415 | |
2416 void Assembler::prefetchr(Address src) { | |
3854 | 2417 assert(VM_Version::supports_3dnow_prefetch(), "must support"); |
304 | 2418 InstructionMark im(this); |
2419 prefetch_prefix(src); | |
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2420 emit_int8(0x0D); |
304 | 2421 emit_operand(rax, src); // 0, src |
2422 } | |
2423 | |
2424 void Assembler::prefetcht0(Address src) { | |
2425 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
2426 InstructionMark im(this); | |
2427 prefetch_prefix(src); | |
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2428 emit_int8(0x18); |
304 | 2429 emit_operand(rcx, src); // 1, src |
2430 } | |
2431 | |
2432 void Assembler::prefetcht1(Address src) { | |
2433 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
2434 InstructionMark im(this); | |
2435 prefetch_prefix(src); | |
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2436 emit_int8(0x18); |
304 | 2437 emit_operand(rdx, src); // 2, src |
2438 } | |
2439 | |
2440 void Assembler::prefetcht2(Address src) { | |
2441 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
2442 InstructionMark im(this); | |
2443 prefetch_prefix(src); | |
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2444 emit_int8(0x18); |
304 | 2445 emit_operand(rbx, src); // 3, src |
2446 } | |
2447 | |
2448 void Assembler::prefetchw(Address src) { | |
3854 | 2449 assert(VM_Version::supports_3dnow_prefetch(), "must support"); |
304 | 2450 InstructionMark im(this); |
2451 prefetch_prefix(src); | |
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2452 emit_int8(0x0D); |
304 | 2453 emit_operand(rcx, src); // 1, src |
2454 } | |
2455 | |
2456 void Assembler::prefix(Prefix p) { | |
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2457 emit_int8(p); |
304 | 2458 } |
2459 | |
6894 | 2460 void Assembler::pshufb(XMMRegister dst, XMMRegister src) { |
2461 assert(VM_Version::supports_ssse3(), ""); | |
2462 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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2463 emit_int8(0x00); |
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2464 emit_int8((unsigned char)(0xC0 | encode)); |
6894 | 2465 } |
2466 | |
2467 void Assembler::pshufb(XMMRegister dst, Address src) { | |
2468 assert(VM_Version::supports_ssse3(), ""); | |
2469 InstructionMark im(this); | |
2470 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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2471 emit_int8(0x00); |
6894 | 2472 emit_operand(dst, src); |
2473 } | |
2474 | |
304 | 2475 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) { |
2476 assert(isByte(mode), "invalid value"); | |
2477 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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2478 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_66); |
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2479 emit_int8(mode & 0xFF); |
304 | 2480 |
2481 } | |
2482 | |
2483 void Assembler::pshufd(XMMRegister dst, Address src, int mode) { | |
2484 assert(isByte(mode), "invalid value"); | |
2485 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
4759 | 2486 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
2487 InstructionMark im(this); | |
2488 simd_prefix(dst, src, VEX_SIMD_66); | |
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2489 emit_int8(0x70); |
304 | 2490 emit_operand(dst, src); |
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2491 emit_int8(mode & 0xFF); |
304 | 2492 } |
2493 | |
2494 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { | |
2495 assert(isByte(mode), "invalid value"); | |
2496 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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2497 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_F2); |
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2498 emit_int8(mode & 0xFF); |
304 | 2499 } |
2500 | |
2501 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) { | |
2502 assert(isByte(mode), "invalid value"); | |
2503 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
4759 | 2504 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
2505 InstructionMark im(this); | |
2506 simd_prefix(dst, src, VEX_SIMD_F2); | |
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2507 emit_int8(0x70); |
304 | 2508 emit_operand(dst, src); |
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2509 emit_int8(mode & 0xFF); |
304 | 2510 } |
2511 | |
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2512 void Assembler::psrldq(XMMRegister dst, int shift) { |
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2513 // Shift 128 bit value in xmm register by number of bytes. |
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2514 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
4759 | 2515 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66); |
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2516 emit_int8(0x73); |
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2517 emit_int8((unsigned char)(0xC0 | encode)); |
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2518 emit_int8(shift); |
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2519 } |
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2520 |
681 | 2521 void Assembler::ptest(XMMRegister dst, Address src) { |
2522 assert(VM_Version::supports_sse4_1(), ""); | |
4759 | 2523 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); |
2524 InstructionMark im(this); | |
2525 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); | |
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2526 emit_int8(0x17); |
681 | 2527 emit_operand(dst, src); |
2528 } | |
2529 | |
2530 void Assembler::ptest(XMMRegister dst, XMMRegister src) { | |
2531 assert(VM_Version::supports_sse4_1(), ""); | |
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2532 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
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2533 emit_int8(0x17); |
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2534 emit_int8((unsigned char)(0xC0 | encode)); |
681 | 2535 } |
2536 | |
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2537 void Assembler::vptest(XMMRegister dst, Address src) { |
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2538 assert(VM_Version::supports_avx(), ""); |
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2539 InstructionMark im(this); |
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2540 bool vector256 = true; |
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2541 assert(dst != xnoreg, "sanity"); |
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2542 int dst_enc = dst->encoding(); |
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2543 // swap src<->dst for encoding |
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2544 vex_prefix(src, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256); |
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2545 emit_int8(0x17); |
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2546 emit_operand(dst, src); |
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2547 } |
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2548 |
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2549 void Assembler::vptest(XMMRegister dst, XMMRegister src) { |
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2550 assert(VM_Version::supports_avx(), ""); |
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2551 bool vector256 = true; |
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2552 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38); |
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2553 emit_int8(0x17); |
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2554 emit_int8((unsigned char)(0xC0 | encode)); |
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2555 } |
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2556 |
4759 | 2557 void Assembler::punpcklbw(XMMRegister dst, Address src) { |
2558 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2559 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
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2560 emit_simd_arith(0x60, dst, src, VEX_SIMD_66); |
4759 | 2561 } |
2562 | |
304 | 2563 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) { |
2564 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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2565 emit_simd_arith(0x60, dst, src, VEX_SIMD_66); |
304 | 2566 } |
2567 | |
4759 | 2568 void Assembler::punpckldq(XMMRegister dst, Address src) { |
2569 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2570 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); | |
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2571 emit_simd_arith(0x62, dst, src, VEX_SIMD_66); |
4759 | 2572 } |
2573 | |
2574 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) { | |
2575 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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2576 emit_simd_arith(0x62, dst, src, VEX_SIMD_66); |
4759 | 2577 } |
2578 | |
6225 | 2579 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) { |
2580 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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2581 emit_simd_arith(0x6C, dst, src, VEX_SIMD_66); |
6225 | 2582 } |
2583 | |
304 | 2584 void Assembler::push(int32_t imm32) { |
2585 // in 64bits we push 64bits onto the stack but only | |
2586 // take a 32bit immediate | |
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2587 emit_int8(0x68); |
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2588 emit_int32(imm32); |
304 | 2589 } |
2590 | |
2591 void Assembler::push(Register src) { | |
2592 int encode = prefix_and_encode(src->encoding()); | |
2593 | |
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2594 emit_int8(0x50 | encode); |
304 | 2595 } |
2596 | |
2597 void Assembler::pushf() { | |
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2598 emit_int8((unsigned char)0x9C); |
304 | 2599 } |
2600 | |
1060 | 2601 #ifndef _LP64 // no 32bit push/pop on amd64 |
304 | 2602 void Assembler::pushl(Address src) { |
2603 // Note this will push 64bit on 64bit | |
2604 InstructionMark im(this); | |
2605 prefix(src); | |
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2606 emit_int8((unsigned char)0xFF); |
304 | 2607 emit_operand(rsi, src); |
2608 } | |
1060 | 2609 #endif |
304 | 2610 |
2611 void Assembler::rcll(Register dst, int imm8) { | |
2612 assert(isShiftCount(imm8), "illegal shift count"); | |
2613 int encode = prefix_and_encode(dst->encoding()); | |
2614 if (imm8 == 1) { | |
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2615 emit_int8((unsigned char)0xD1); |
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2616 emit_int8((unsigned char)(0xD0 | encode)); |
304 | 2617 } else { |
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2618 emit_int8((unsigned char)0xC1); |
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2619 emit_int8((unsigned char)0xD0 | encode); |
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2620 emit_int8(imm8); |
304 | 2621 } |
2622 } | |
2623 | |
2624 // copies data from [esi] to [edi] using rcx pointer sized words | |
2625 // generic | |
2626 void Assembler::rep_mov() { | |
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2627 emit_int8((unsigned char)0xF3); |
304 | 2628 // MOVSQ |
2629 LP64_ONLY(prefix(REX_W)); | |
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2630 emit_int8((unsigned char)0xA5); |
304 | 2631 } |
2632 | |
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2633 // sets rcx bytes with rax, value at [edi] |
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2634 void Assembler::rep_stosb() { |
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2635 emit_int8((unsigned char)0xF3); // REP |
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2636 LP64_ONLY(prefix(REX_W)); |
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2637 emit_int8((unsigned char)0xAA); // STOSB |
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2638 } |
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2639 |
304 | 2640 // sets rcx pointer sized words with rax, value at [edi] |
2641 // generic | |
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2642 void Assembler::rep_stos() { |
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2643 emit_int8((unsigned char)0xF3); // REP |
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2644 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD |
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2645 emit_int8((unsigned char)0xAB); |
304 | 2646 } |
2647 | |
2648 // scans rcx pointer sized words at [edi] for occurance of rax, | |
2649 // generic | |
2650 void Assembler::repne_scan() { // repne_scan | |
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2651 emit_int8((unsigned char)0xF2); |
304 | 2652 // SCASQ |
2653 LP64_ONLY(prefix(REX_W)); | |
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2654 emit_int8((unsigned char)0xAF); |
304 | 2655 } |
2656 | |
2657 #ifdef _LP64 | |
2658 // scans rcx 4 byte words at [edi] for occurance of rax, | |
2659 // generic | |
2660 void Assembler::repne_scanl() { // repne_scan | |
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2661 emit_int8((unsigned char)0xF2); |
304 | 2662 // SCASL |
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2663 emit_int8((unsigned char)0xAF); |
304 | 2664 } |
2665 #endif | |
2666 | |
0 | 2667 void Assembler::ret(int imm16) { |
2668 if (imm16 == 0) { | |
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2669 emit_int8((unsigned char)0xC3); |
0 | 2670 } else { |
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|
2671 emit_int8((unsigned char)0xC2); |
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|
2672 emit_int16(imm16); |
0 | 2673 } |
2674 } | |
2675 | |
304 | 2676 void Assembler::sahf() { |
2677 #ifdef _LP64 | |
2678 // Not supported in 64bit mode | |
2679 ShouldNotReachHere(); | |
2680 #endif | |
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2681 emit_int8((unsigned char)0x9E); |
304 | 2682 } |
2683 | |
2684 void Assembler::sarl(Register dst, int imm8) { | |
2685 int encode = prefix_and_encode(dst->encoding()); | |
2686 assert(isShiftCount(imm8), "illegal shift count"); | |
2687 if (imm8 == 1) { | |
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2688 emit_int8((unsigned char)0xD1); |
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2689 emit_int8((unsigned char)(0xF8 | encode)); |
304 | 2690 } else { |
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|
2691 emit_int8((unsigned char)0xC1); |
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|
2692 emit_int8((unsigned char)(0xF8 | encode)); |
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2693 emit_int8(imm8); |
304 | 2694 } |
2695 } | |
2696 | |
2697 void Assembler::sarl(Register dst) { | |
2698 int encode = prefix_and_encode(dst->encoding()); | |
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|
2699 emit_int8((unsigned char)0xD3); |
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2700 emit_int8((unsigned char)(0xF8 | encode)); |
304 | 2701 } |
2702 | |
2703 void Assembler::sbbl(Address dst, int32_t imm32) { | |
2704 InstructionMark im(this); | |
2705 prefix(dst); | |
2706 emit_arith_operand(0x81, rbx, dst, imm32); | |
2707 } | |
2708 | |
2709 void Assembler::sbbl(Register dst, int32_t imm32) { | |
2710 prefix(dst); | |
2711 emit_arith(0x81, 0xD8, dst, imm32); | |
2712 } | |
2713 | |
2714 | |
2715 void Assembler::sbbl(Register dst, Address src) { | |
2716 InstructionMark im(this); | |
2717 prefix(src, dst); | |
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|
2718 emit_int8(0x1B); |
304 | 2719 emit_operand(dst, src); |
2720 } | |
2721 | |
2722 void Assembler::sbbl(Register dst, Register src) { | |
2723 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
2724 emit_arith(0x1B, 0xC0, dst, src); | |
2725 } | |
2726 | |
2727 void Assembler::setb(Condition cc, Register dst) { | |
2728 assert(0 <= cc && cc < 16, "illegal cc"); | |
2729 int encode = prefix_and_encode(dst->encoding(), true); | |
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|
2730 emit_int8(0x0F); |
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|
2731 emit_int8((unsigned char)0x90 | cc); |
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|
2732 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 2733 } |
2734 | |
2735 void Assembler::shll(Register dst, int imm8) { | |
2736 assert(isShiftCount(imm8), "illegal shift count"); | |
2737 int encode = prefix_and_encode(dst->encoding()); | |
2738 if (imm8 == 1 ) { | |
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|
2739 emit_int8((unsigned char)0xD1); |
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|
2740 emit_int8((unsigned char)(0xE0 | encode)); |
304 | 2741 } else { |
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|
2742 emit_int8((unsigned char)0xC1); |
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|
2743 emit_int8((unsigned char)(0xE0 | encode)); |
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|
2744 emit_int8(imm8); |
304 | 2745 } |
2746 } | |
2747 | |
2748 void Assembler::shll(Register dst) { | |
2749 int encode = prefix_and_encode(dst->encoding()); | |
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|
2750 emit_int8((unsigned char)0xD3); |
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|
2751 emit_int8((unsigned char)(0xE0 | encode)); |
304 | 2752 } |
2753 | |
2754 void Assembler::shrl(Register dst, int imm8) { | |
2755 assert(isShiftCount(imm8), "illegal shift count"); | |
2756 int encode = prefix_and_encode(dst->encoding()); | |
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|
2757 emit_int8((unsigned char)0xC1); |
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|
2758 emit_int8((unsigned char)(0xE8 | encode)); |
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|
2759 emit_int8(imm8); |
304 | 2760 } |
2761 | |
2762 void Assembler::shrl(Register dst) { | |
2763 int encode = prefix_and_encode(dst->encoding()); | |
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|
2764 emit_int8((unsigned char)0xD3); |
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|
2765 emit_int8((unsigned char)(0xE8 | encode)); |
304 | 2766 } |
0 | 2767 |
2768 // copies a single word from [esi] to [edi] | |
2769 void Assembler::smovl() { | |
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|
2770 emit_int8((unsigned char)0xA5); |
0 | 2771 } |
2772 | |
304 | 2773 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { |
2774 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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2775 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2); |
304 | 2776 } |
2777 | |
2008 | 2778 void Assembler::sqrtsd(XMMRegister dst, Address src) { |
2779 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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|
2780 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2); |
2008 | 2781 } |
2782 | |
2783 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) { | |
4759 | 2784 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
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2785 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3); |
2008 | 2786 } |
2787 | |
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|
2788 void Assembler::std() { |
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|
2789 emit_int8((unsigned char)0xFD); |
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|
2790 } |
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|
2791 |
2008 | 2792 void Assembler::sqrtss(XMMRegister dst, Address src) { |
4759 | 2793 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
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|
2794 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3); |
2008 | 2795 } |
2796 | |
304 | 2797 void Assembler::stmxcsr( Address dst) { |
2798 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
2799 InstructionMark im(this); | |
2800 prefix(dst); | |
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|
2801 emit_int8(0x0F); |
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|
2802 emit_int8((unsigned char)0xAE); |
304 | 2803 emit_operand(as_Register(3), dst); |
2804 } | |
2805 | |
2806 void Assembler::subl(Address dst, int32_t imm32) { | |
2807 InstructionMark im(this); | |
2808 prefix(dst); | |
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b1a2afa37ec4
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diff
changeset
|
2809 emit_arith_operand(0x81, rbp, dst, imm32); |
304 | 2810 } |
2811 | |
2812 void Assembler::subl(Address dst, Register src) { | |
2813 InstructionMark im(this); | |
2814 prefix(dst, src); | |
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|
2815 emit_int8(0x29); |
304 | 2816 emit_operand(src, dst); |
2817 } | |
2818 | |
2100
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diff
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|
2819 void Assembler::subl(Register dst, int32_t imm32) { |
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|
2820 prefix(dst); |
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|
2821 emit_arith(0x81, 0xE8, dst, imm32); |
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|
2822 } |
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|
2823 |
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changeset
|
2824 // Force generation of a 4 byte immediate value even if it fits into 8bit |
fd8114661503
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changeset
|
2825 void Assembler::subl_imm32(Register dst, int32_t imm32) { |
fd8114661503
7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
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changeset
|
2826 prefix(dst); |
fd8114661503
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changeset
|
2827 emit_arith_imm32(0x81, 0xE8, dst, imm32); |
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changeset
|
2828 } |
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|
2829 |
304 | 2830 void Assembler::subl(Register dst, Address src) { |
2831 InstructionMark im(this); | |
2832 prefix(src, dst); | |
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changeset
|
2833 emit_int8(0x2B); |
304 | 2834 emit_operand(dst, src); |
2835 } | |
2836 | |
2837 void Assembler::subl(Register dst, Register src) { | |
2838 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
2839 emit_arith(0x2B, 0xC0, dst, src); | |
2840 } | |
2841 | |
2842 void Assembler::subsd(XMMRegister dst, XMMRegister src) { | |
2843 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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|
2844 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2); |
304 | 2845 } |
2846 | |
2847 void Assembler::subsd(XMMRegister dst, Address src) { | |
2848 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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|
2849 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2); |
304 | 2850 } |
2851 | |
2852 void Assembler::subss(XMMRegister dst, XMMRegister src) { | |
2853 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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|
2854 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3); |
304 | 2855 } |
2856 | |
2857 void Assembler::subss(XMMRegister dst, Address src) { | |
2858 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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|
2859 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3); |
304 | 2860 } |
2861 | |
2862 void Assembler::testb(Register dst, int imm8) { | |
2863 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); | |
2864 (void) prefix_and_encode(dst->encoding(), true); | |
2865 emit_arith_b(0xF6, 0xC0, dst, imm8); | |
2866 } | |
2867 | |
2868 void Assembler::testl(Register dst, int32_t imm32) { | |
2869 // not using emit_arith because test | |
2870 // doesn't support sign-extension of | |
2871 // 8bit operands | |
2872 int encode = dst->encoding(); | |
2873 if (encode == 0) { | |
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|
2874 emit_int8((unsigned char)0xA9); |
304 | 2875 } else { |
2876 encode = prefix_and_encode(encode); | |
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|
2877 emit_int8((unsigned char)0xF7); |
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|
2878 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 2879 } |
7476
ffa87474d7a4
8004537: replace AbstractAssembler emit_long with emit_int32
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7475
diff
changeset
|
2880 emit_int32(imm32); |
304 | 2881 } |
2882 | |
2883 void Assembler::testl(Register dst, Register src) { | |
2884 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
2885 emit_arith(0x85, 0xC0, dst, src); | |
2886 } | |
2887 | |
2888 void Assembler::testl(Register dst, Address src) { | |
2889 InstructionMark im(this); | |
2890 prefix(src, dst); | |
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|
2891 emit_int8((unsigned char)0x85); |
304 | 2892 emit_operand(dst, src); |
2893 } | |
2894 | |
2895 void Assembler::ucomisd(XMMRegister dst, Address src) { | |
2896 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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|
2897 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66); |
304 | 2898 } |
2899 | |
2900 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) { | |
2901 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
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|
2902 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66); |
304 | 2903 } |
2904 | |
2905 void Assembler::ucomiss(XMMRegister dst, Address src) { | |
2906 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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|
2907 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE); |
304 | 2908 } |
2909 | |
2910 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) { | |
2911 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
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|
2912 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE); |
304 | 2913 } |
2914 | |
2915 | |
2916 void Assembler::xaddl(Address dst, Register src) { | |
2917 InstructionMark im(this); | |
2918 prefix(dst, src); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
2919 emit_int8(0x0F); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
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7427
diff
changeset
|
2920 emit_int8((unsigned char)0xC1); |
304 | 2921 emit_operand(src, dst); |
2922 } | |
2923 | |
2924 void Assembler::xchgl(Register dst, Address src) { // xchg | |
2925 InstructionMark im(this); | |
2926 prefix(src, dst); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
2927 emit_int8((unsigned char)0x87); |
304 | 2928 emit_operand(dst, src); |
2929 } | |
2930 | |
2931 void Assembler::xchgl(Register dst, Register src) { | |
2932 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
2933 emit_int8((unsigned char)0x87); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
2934 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 2935 } |
2936 | |
7199
cd3d6a6b95d9
8003240: x86: move MacroAssembler into separate file
twisti
parents:
7198
diff
changeset
|
2937 void Assembler::xgetbv() { |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
2938 emit_int8(0x0F); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
2939 emit_int8(0x01); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
2940 emit_int8((unsigned char)0xD0); |
7199
cd3d6a6b95d9
8003240: x86: move MacroAssembler into separate file
twisti
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7198
diff
changeset
|
2941 } |
cd3d6a6b95d9
8003240: x86: move MacroAssembler into separate file
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7198
diff
changeset
|
2942 |
304 | 2943 void Assembler::xorl(Register dst, int32_t imm32) { |
2944 prefix(dst); | |
2945 emit_arith(0x81, 0xF0, dst, imm32); | |
2946 } | |
2947 | |
2948 void Assembler::xorl(Register dst, Address src) { | |
2949 InstructionMark im(this); | |
2950 prefix(src, dst); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
2951 emit_int8(0x33); |
304 | 2952 emit_operand(dst, src); |
2953 } | |
2954 | |
2955 void Assembler::xorl(Register dst, Register src) { | |
2956 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
2957 emit_arith(0x33, 0xC0, dst, src); | |
2958 } | |
2959 | |
6614
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
2960 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
2961 // AVX 3-operands scalar float-point arithmetic instructions |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
2962 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
2963 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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diff
changeset
|
2964 assert(VM_Version::supports_avx(), ""); |
6614
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
2965 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
2966 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
2967 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
2968 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
2969 assert(VM_Version::supports_avx(), ""); |
6614
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
2970 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
2971 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
2972 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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changeset
|
2973 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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diff
changeset
|
2974 assert(VM_Version::supports_avx(), ""); |
6614
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
2975 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
2976 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
2977 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
2978 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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diff
changeset
|
2979 assert(VM_Version::supports_avx(), ""); |
6614
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6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
2980 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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4759
diff
changeset
|
2981 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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4759
diff
changeset
|
2982 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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diff
changeset
|
2983 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2984 assert(VM_Version::supports_avx(), ""); |
6614
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6340864: Implement vectorization optimizations in hotspot-server
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6266
diff
changeset
|
2985 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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diff
changeset
|
2986 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2987 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2988 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2989 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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6266
diff
changeset
|
2990 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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4759
diff
changeset
|
2991 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2992 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2993 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2994 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
2995 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2996 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2997 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2998 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
2999 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3000 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3001 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3002 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3003 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3004 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3005 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3006 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3007 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3008 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3009 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3010 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3011 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3012 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3013 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) { |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3014 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3015 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3016 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3017 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3018 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3019 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3020 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3021 } |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3022 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3023 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3024 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3025 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3026 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3027 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3028 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3029 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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6266
diff
changeset
|
3030 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3031 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3032 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3033 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3034 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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6266
diff
changeset
|
3035 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3036 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3037 |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3038 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3039 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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diff
changeset
|
3040 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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diff
changeset
|
3041 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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diff
changeset
|
3042 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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diff
changeset
|
3043 //====================VECTOR ARITHMETIC===================================== |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
3044 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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6266
diff
changeset
|
3045 // Float-point vector arithmetic |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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diff
changeset
|
3046 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
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changeset
|
3047 void Assembler::addpd(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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diff
changeset
|
3048 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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6266
diff
changeset
|
3049 emit_simd_arith(0x58, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
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diff
changeset
|
3050 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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diff
changeset
|
3051 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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diff
changeset
|
3052 void Assembler::addps(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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diff
changeset
|
3053 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3054 emit_simd_arith(0x58, dst, src, VEX_SIMD_NONE); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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diff
changeset
|
3055 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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diff
changeset
|
3056 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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6266
diff
changeset
|
3057 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
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6266
diff
changeset
|
3058 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3059 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3060 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3061 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3062 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3063 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3064 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3065 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3066 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3067 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3068 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3069 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3070 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3071 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3072 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3073 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3074 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3075 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3076 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3077 void Assembler::subpd(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3078 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3079 emit_simd_arith(0x5C, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3080 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3081 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3082 void Assembler::subps(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3083 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3084 emit_simd_arith(0x5C, dst, src, VEX_SIMD_NONE); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3085 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3086 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3087 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3088 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3089 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3090 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3091 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3092 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3093 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3094 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3095 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3096 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3097 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3098 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3099 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3100 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3101 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3102 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3103 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3104 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3105 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3106 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3107 void Assembler::mulpd(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3108 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3109 emit_simd_arith(0x59, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3110 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3111 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3112 void Assembler::mulps(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3113 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3114 emit_simd_arith(0x59, dst, src, VEX_SIMD_NONE); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3115 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3116 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3117 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3118 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3119 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3120 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3121 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3122 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3123 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3124 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3125 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3126 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3127 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3128 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3129 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3130 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3131 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3132 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3133 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3134 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3135 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3136 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3137 void Assembler::divpd(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3138 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3139 emit_simd_arith(0x5E, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3140 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3141 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3142 void Assembler::divps(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3143 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3144 emit_simd_arith(0x5E, dst, src, VEX_SIMD_NONE); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3145 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3146 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3147 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3148 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3149 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3150 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3151 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3152 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3153 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3154 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3155 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3156 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3157 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3158 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3159 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3160 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3161 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3162 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3163 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3164 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3165 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3166 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3167 void Assembler::andpd(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3168 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3169 emit_simd_arith(0x54, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3170 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3171 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3172 void Assembler::andps(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3173 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3174 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3175 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3176 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3177 void Assembler::andps(XMMRegister dst, Address src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3178 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3179 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3180 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3181 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3182 void Assembler::andpd(XMMRegister dst, Address src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3183 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3184 emit_simd_arith(0x54, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3185 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3186 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3187 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3188 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3189 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3190 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3191 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3192 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3193 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3194 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3195 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3196 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3197 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3198 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3199 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3200 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3201 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3202 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3203 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3204 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3205 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3206 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3207 void Assembler::xorpd(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3208 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3209 emit_simd_arith(0x57, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3210 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3211 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3212 void Assembler::xorps(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3213 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3214 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3215 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3216 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3217 void Assembler::xorpd(XMMRegister dst, Address src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3218 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3219 emit_simd_arith(0x57, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3220 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3221 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3222 void Assembler::xorps(XMMRegister dst, Address src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3223 NOT_LP64(assert(VM_Version::supports_sse(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3224 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3225 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3226 |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3227 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3228 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3229 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256); |
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3230 } |
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4759
diff
changeset
|
3231 |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3232 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3233 assert(VM_Version::supports_avx(), ""); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3234 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3235 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3236 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3237 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3238 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3239 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3240 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3241 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3242 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3243 assert(VM_Version::supports_avx(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3244 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3245 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3246 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3247 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3248 // Integer vector arithmetic |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3249 void Assembler::paddb(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3250 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3251 emit_simd_arith(0xFC, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3252 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3253 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3254 void Assembler::paddw(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3255 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3256 emit_simd_arith(0xFD, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3257 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3258 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3259 void Assembler::paddd(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3260 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3261 emit_simd_arith(0xFE, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3262 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3263 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3264 void Assembler::paddq(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3265 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3266 emit_simd_arith(0xD4, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3267 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3268 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3269 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3270 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3271 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3272 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3273 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3274 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3275 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3276 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3277 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3278 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3279 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3280 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3281 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3282 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3283 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3284 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3285 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3286 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3287 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3288 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3289 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3290 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3291 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3292 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3293 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3294 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3295 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3296 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3297 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3298 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3299 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3300 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3301 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3302 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3303 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3304 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3305 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3306 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3307 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3308 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3309 void Assembler::psubb(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3310 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3311 emit_simd_arith(0xF8, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3312 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3313 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3314 void Assembler::psubw(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3315 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3316 emit_simd_arith(0xF9, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3317 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3318 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3319 void Assembler::psubd(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3320 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3321 emit_simd_arith(0xFA, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3322 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3323 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3324 void Assembler::psubq(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3325 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3326 emit_simd_arith(0xFB, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3327 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3328 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3329 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3330 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3331 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3332 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3333 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3334 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3335 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3336 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3337 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3338 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3339 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3340 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3341 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3342 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3343 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3344 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3345 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3346 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3347 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3348 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3349 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3350 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3351 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3352 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3353 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3354 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3355 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3356 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3357 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3358 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3359 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3360 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3361 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3362 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3363 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3364 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3365 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3366 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3367 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3368 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3369 void Assembler::pmullw(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3370 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3371 emit_simd_arith(0xD5, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3372 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3373 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3374 void Assembler::pmulld(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3375 assert(VM_Version::supports_sse4_1(), ""); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3376 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3377 emit_int8(0x40); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3378 emit_int8((unsigned char)(0xC0 | encode)); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3379 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3380 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3381 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3382 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3383 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3384 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3385 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3386 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3387 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3388 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3389 emit_int8(0x40); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3390 emit_int8((unsigned char)(0xC0 | encode)); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3391 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3392 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3393 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3394 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3395 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3396 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3397 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3398 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3399 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3400 InstructionMark im(this); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3401 int dst_enc = dst->encoding(); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3402 int nds_enc = nds->is_valid() ? nds->encoding() : 0; |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3403 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3404 emit_int8(0x40); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3405 emit_operand(dst, src); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3406 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3407 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3408 // Shift packed integers left by specified number of bits. |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3409 void Assembler::psllw(XMMRegister dst, int shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3410 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3411 // XMM6 is for /6 encoding: 66 0F 71 /6 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3412 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3413 emit_int8(0x71); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3414 emit_int8((unsigned char)(0xC0 | encode)); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3415 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3416 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3417 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3418 void Assembler::pslld(XMMRegister dst, int shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3419 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3420 // XMM6 is for /6 encoding: 66 0F 72 /6 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3421 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3422 emit_int8(0x72); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3423 emit_int8((unsigned char)(0xC0 | encode)); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3424 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3425 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3426 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3427 void Assembler::psllq(XMMRegister dst, int shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3428 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3429 // XMM6 is for /6 encoding: 66 0F 73 /6 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3430 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3431 emit_int8(0x73); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3432 emit_int8((unsigned char)(0xC0 | encode)); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3433 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3434 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3435 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3436 void Assembler::psllw(XMMRegister dst, XMMRegister shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3437 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3438 emit_simd_arith(0xF1, dst, shift, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3439 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3440 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3441 void Assembler::pslld(XMMRegister dst, XMMRegister shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3442 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3443 emit_simd_arith(0xF2, dst, shift, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3444 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3445 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3446 void Assembler::psllq(XMMRegister dst, XMMRegister shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3447 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3448 emit_simd_arith(0xF3, dst, shift, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3449 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3450 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3451 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3452 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3453 // XMM6 is for /6 encoding: 66 0F 71 /6 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3454 emit_vex_arith(0x71, xmm6, dst, src, VEX_SIMD_66, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3455 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3456 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3457 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3458 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3459 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3460 // XMM6 is for /6 encoding: 66 0F 72 /6 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3461 emit_vex_arith(0x72, xmm6, dst, src, VEX_SIMD_66, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3462 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3463 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3464 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3465 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3466 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3467 // XMM6 is for /6 encoding: 66 0F 73 /6 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3468 emit_vex_arith(0x73, xmm6, dst, src, VEX_SIMD_66, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3469 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3470 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3471 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3472 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3473 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3474 emit_vex_arith(0xF1, dst, src, shift, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3475 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3476 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3477 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3478 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3479 emit_vex_arith(0xF2, dst, src, shift, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3480 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3481 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3482 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3483 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3484 emit_vex_arith(0xF3, dst, src, shift, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3485 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3486 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3487 // Shift packed integers logically right by specified number of bits. |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3488 void Assembler::psrlw(XMMRegister dst, int shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3489 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3490 // XMM2 is for /2 encoding: 66 0F 71 /2 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3491 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3492 emit_int8(0x71); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3493 emit_int8((unsigned char)(0xC0 | encode)); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3494 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3495 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3496 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3497 void Assembler::psrld(XMMRegister dst, int shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3498 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3499 // XMM2 is for /2 encoding: 66 0F 72 /2 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3500 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3501 emit_int8(0x72); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3502 emit_int8((unsigned char)(0xC0 | encode)); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3503 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3504 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3505 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3506 void Assembler::psrlq(XMMRegister dst, int shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3507 // Do not confuse it with psrldq SSE2 instruction which |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3508 // shifts 128 bit value in xmm register by number of bytes. |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3509 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3510 // XMM2 is for /2 encoding: 66 0F 73 /2 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3511 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3512 emit_int8(0x73); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3513 emit_int8((unsigned char)(0xC0 | encode)); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3514 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3515 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3516 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3517 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3518 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3519 emit_simd_arith(0xD1, dst, shift, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3520 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3521 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3522 void Assembler::psrld(XMMRegister dst, XMMRegister shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3523 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3524 emit_simd_arith(0xD2, dst, shift, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3525 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3526 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3527 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3528 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3529 emit_simd_arith(0xD3, dst, shift, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3530 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3531 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3532 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3533 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3534 // XMM2 is for /2 encoding: 66 0F 73 /2 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3535 emit_vex_arith(0x71, xmm2, dst, src, VEX_SIMD_66, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3536 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3537 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3538 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3539 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3540 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3541 // XMM2 is for /2 encoding: 66 0F 73 /2 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3542 emit_vex_arith(0x72, xmm2, dst, src, VEX_SIMD_66, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3543 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3544 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3545 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3546 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3547 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3548 // XMM2 is for /2 encoding: 66 0F 73 /2 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3549 emit_vex_arith(0x73, xmm2, dst, src, VEX_SIMD_66, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3550 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3551 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3552 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3553 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3554 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3555 emit_vex_arith(0xD1, dst, src, shift, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3556 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3557 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3558 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3559 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3560 emit_vex_arith(0xD2, dst, src, shift, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3561 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3562 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3563 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3564 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3565 emit_vex_arith(0xD3, dst, src, shift, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3566 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3567 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3568 // Shift packed integers arithmetically right by specified number of bits. |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3569 void Assembler::psraw(XMMRegister dst, int shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3570 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3571 // XMM4 is for /4 encoding: 66 0F 71 /4 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3572 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3573 emit_int8(0x71); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3574 emit_int8((unsigned char)(0xC0 | encode)); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3575 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3576 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3577 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3578 void Assembler::psrad(XMMRegister dst, int shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3579 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3580 // XMM4 is for /4 encoding: 66 0F 72 /4 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3581 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3582 emit_int8(0x72); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3583 emit_int8((unsigned char)(0xC0 | encode)); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3584 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3585 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3586 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3587 void Assembler::psraw(XMMRegister dst, XMMRegister shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3588 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3589 emit_simd_arith(0xE1, dst, shift, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3590 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3591 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3592 void Assembler::psrad(XMMRegister dst, XMMRegister shift) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3593 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3594 emit_simd_arith(0xE2, dst, shift, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3595 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3596 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3597 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3598 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3599 // XMM4 is for /4 encoding: 66 0F 71 /4 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3600 emit_vex_arith(0x71, xmm4, dst, src, VEX_SIMD_66, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3601 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3602 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3603 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3604 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3605 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3606 // XMM4 is for /4 encoding: 66 0F 71 /4 ib |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3607 emit_vex_arith(0x72, xmm4, dst, src, VEX_SIMD_66, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3608 emit_int8(shift & 0xFF); |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3609 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3610 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3611 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3612 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3613 emit_vex_arith(0xE1, dst, src, shift, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3614 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3615 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3616 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3617 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3618 emit_vex_arith(0xE2, dst, src, shift, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3619 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3620 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3621 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3622 // AND packed integers |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3623 void Assembler::pand(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3624 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3625 emit_simd_arith(0xDB, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3626 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3627 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3628 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3629 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3630 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3631 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3632 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3633 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3634 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3635 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3636 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3637 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3638 void Assembler::por(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3639 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3640 emit_simd_arith(0xEB, dst, src, VEX_SIMD_66); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3641 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3642 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3643 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3644 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3645 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3646 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3647 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3648 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3649 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3650 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3651 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3652 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3653 void Assembler::pxor(XMMRegister dst, XMMRegister src) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3654 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3655 emit_simd_arith(0xEF, dst, src, VEX_SIMD_66); |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3656 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3657 |
6225 | 3658 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { |
6614
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3659 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3660 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3661 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3662 |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3663 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3664 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3665 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256); |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3666 } |
006050192a5a
6340864: Implement vectorization optimizations in hotspot-server
kvn
parents:
6266
diff
changeset
|
3667 |
6225 | 3668 |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3669 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3670 assert(VM_Version::supports_avx(), ""); |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3671 bool vector256 = true; |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3672 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3673 emit_int8(0x18); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3674 emit_int8((unsigned char)(0xC0 | encode)); |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3675 // 0x00 - insert into lower 128 bits |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3676 // 0x01 - insert into upper 128 bits |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3677 emit_int8(0x01); |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3678 } |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3679 |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3680 void Assembler::vinsertf128h(XMMRegister dst, Address src) { |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3681 assert(VM_Version::supports_avx(), ""); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3682 InstructionMark im(this); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3683 bool vector256 = true; |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3684 assert(dst != xnoreg, "sanity"); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3685 int dst_enc = dst->encoding(); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3686 // swap src<->dst for encoding |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3687 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3688 emit_int8(0x18); |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3689 emit_operand(dst, src); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3690 // 0x01 - insert into upper 128 bits |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3691 emit_int8(0x01); |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3692 } |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3693 |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3694 void Assembler::vextractf128h(Address dst, XMMRegister src) { |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3695 assert(VM_Version::supports_avx(), ""); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3696 InstructionMark im(this); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3697 bool vector256 = true; |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3698 assert(src != xnoreg, "sanity"); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3699 int src_enc = src->encoding(); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3700 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3701 emit_int8(0x19); |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3702 emit_operand(src, dst); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3703 // 0x01 - extract from upper 128 bits |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3704 emit_int8(0x01); |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3705 } |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3706 |
6225 | 3707 void Assembler::vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) { |
3708 assert(VM_Version::supports_avx2(), ""); | |
3709 bool vector256 = true; | |
3710 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A); | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3711 emit_int8(0x38); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3712 emit_int8((unsigned char)(0xC0 | encode)); |
6225 | 3713 // 0x00 - insert into lower 128 bits |
3714 // 0x01 - insert into upper 128 bits | |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3715 emit_int8(0x01); |
6225 | 3716 } |
3717 | |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3718 void Assembler::vinserti128h(XMMRegister dst, Address src) { |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3719 assert(VM_Version::supports_avx2(), ""); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3720 InstructionMark im(this); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3721 bool vector256 = true; |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3722 assert(dst != xnoreg, "sanity"); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3723 int dst_enc = dst->encoding(); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3724 // swap src<->dst for encoding |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3725 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3726 emit_int8(0x38); |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3727 emit_operand(dst, src); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3728 // 0x01 - insert into upper 128 bits |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3729 emit_int8(0x01); |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3730 } |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3731 |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3732 void Assembler::vextracti128h(Address dst, XMMRegister src) { |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3733 assert(VM_Version::supports_avx2(), ""); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3734 InstructionMark im(this); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3735 bool vector256 = true; |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3736 assert(src != xnoreg, "sanity"); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3737 int src_enc = src->encoding(); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3738 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256); |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3739 emit_int8(0x39); |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3740 emit_operand(src, dst); |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3741 // 0x01 - extract from upper 128 bits |
7430
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
parents:
7427
diff
changeset
|
3742 emit_int8(0x01); |
6792
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3743 } |
137868b7aa6f
7196199: java/text/Bidi/Bug6665028.java failed: Bidi run count incorrect
kvn
parents:
6725
diff
changeset
|
3744 |
7475
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
3745 // duplicate 4-bytes integer data from src into 8 locations in dest |
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
3746 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) { |
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
3747 assert(VM_Version::supports_avx2(), ""); |
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
3748 bool vector256 = true; |
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
3749 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38); |
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
3750 emit_int8(0x58); |
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
3751 emit_int8((unsigned char)(0xC0 | encode)); |
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
3752 } |
e2e6bf86682c
8005544: Use 256bit YMM registers in arraycopy stubs on x86
kvn
parents:
7474
diff
changeset
|
3753 |
11080
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
9060
diff
changeset
|
3754 // Carry-Less Multiplication Quadword |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
9060
diff
changeset
|
3755 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) { |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
9060
diff
changeset
|
3756 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), ""); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
9060
diff
changeset
|
3757 bool vector256 = false; |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
9060
diff
changeset
|
3758 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
9060
diff
changeset
|
3759 emit_int8(0x44); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
9060
diff
changeset
|
3760 emit_int8((unsigned char)(0xC0 | encode)); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
9060
diff
changeset
|
3761 emit_int8((unsigned char)mask); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
9060
diff
changeset
|
3762 } |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
parents:
9060
diff
changeset
|
3763 |
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3764 void Assembler::vzeroupper() { |
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
6141
diff
changeset
|
3765 assert(VM_Version::supports_avx(), ""); |
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3766 (void)vex_prefix_and_encode(xmm0, xmm0, xmm0, VEX_SIMD_NONE); |
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3767 emit_int8(0x77); |
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3768 } |
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3769 |
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3770 |
304 | 3771 #ifndef _LP64 |
3772 // 32bit only pieces of the assembler | |
3773 | |
3774 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) { | |
3775 // NO PREFIX AS NEVER 64BIT | |
3776 InstructionMark im(this); | |
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3777 emit_int8((unsigned char)0x81); |
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3778 emit_int8((unsigned char)(0xF8 | src1->encoding())); |
304 | 3779 emit_data(imm32, rspec, 0); |
3780 } | |
3781 | |
3782 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) { | |
3783 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs | |
3784 InstructionMark im(this); | |
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3785 emit_int8((unsigned char)0x81); |
304 | 3786 emit_operand(rdi, src1); |
3787 emit_data(imm32, rspec, 0); | |
3788 } | |
3789 | |
3790 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax, | |
3791 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded | |
3792 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise. | |
3793 void Assembler::cmpxchg8(Address adr) { | |
3794 InstructionMark im(this); | |
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3795 emit_int8(0x0F); |
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3796 emit_int8((unsigned char)0xC7); |
304 | 3797 emit_operand(rcx, adr); |
3798 } | |
3799 | |
3800 void Assembler::decl(Register dst) { | |
3801 // Don't use it directly. Use MacroAssembler::decrementl() instead. | |
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3802 emit_int8(0x48 | dst->encoding()); |
304 | 3803 } |
3804 | |
3805 #endif // _LP64 | |
3806 | |
3807 // 64bit typically doesn't use the x87 but needs to for the trig funcs | |
3808 | |
3809 void Assembler::fabs() { | |
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3810 emit_int8((unsigned char)0xD9); |
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3811 emit_int8((unsigned char)0xE1); |
304 | 3812 } |
3813 | |
3814 void Assembler::fadd(int i) { | |
3815 emit_farith(0xD8, 0xC0, i); | |
3816 } | |
3817 | |
3818 void Assembler::fadd_d(Address src) { | |
3819 InstructionMark im(this); | |
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3820 emit_int8((unsigned char)0xDC); |
304 | 3821 emit_operand32(rax, src); |
3822 } | |
3823 | |
3824 void Assembler::fadd_s(Address src) { | |
3825 InstructionMark im(this); | |
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3826 emit_int8((unsigned char)0xD8); |
304 | 3827 emit_operand32(rax, src); |
3828 } | |
3829 | |
3830 void Assembler::fadda(int i) { | |
3831 emit_farith(0xDC, 0xC0, i); | |
3832 } | |
3833 | |
3834 void Assembler::faddp(int i) { | |
3835 emit_farith(0xDE, 0xC0, i); | |
3836 } | |
3837 | |
3838 void Assembler::fchs() { | |
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3839 emit_int8((unsigned char)0xD9); |
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3840 emit_int8((unsigned char)0xE0); |
304 | 3841 } |
3842 | |
3843 void Assembler::fcom(int i) { | |
3844 emit_farith(0xD8, 0xD0, i); | |
3845 } | |
3846 | |
3847 void Assembler::fcomp(int i) { | |
3848 emit_farith(0xD8, 0xD8, i); | |
3849 } | |
3850 | |
3851 void Assembler::fcomp_d(Address src) { | |
3852 InstructionMark im(this); | |
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3853 emit_int8((unsigned char)0xDC); |
304 | 3854 emit_operand32(rbx, src); |
3855 } | |
3856 | |
3857 void Assembler::fcomp_s(Address src) { | |
3858 InstructionMark im(this); | |
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3859 emit_int8((unsigned char)0xD8); |
304 | 3860 emit_operand32(rbx, src); |
3861 } | |
3862 | |
3863 void Assembler::fcompp() { | |
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3864 emit_int8((unsigned char)0xDE); |
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3865 emit_int8((unsigned char)0xD9); |
304 | 3866 } |
3867 | |
3868 void Assembler::fcos() { | |
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3869 emit_int8((unsigned char)0xD9); |
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3870 emit_int8((unsigned char)0xFF); |
304 | 3871 } |
3872 | |
3873 void Assembler::fdecstp() { | |
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3874 emit_int8((unsigned char)0xD9); |
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3875 emit_int8((unsigned char)0xF6); |
304 | 3876 } |
3877 | |
3878 void Assembler::fdiv(int i) { | |
3879 emit_farith(0xD8, 0xF0, i); | |
3880 } | |
3881 | |
3882 void Assembler::fdiv_d(Address src) { | |
3883 InstructionMark im(this); | |
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3884 emit_int8((unsigned char)0xDC); |
304 | 3885 emit_operand32(rsi, src); |
3886 } | |
3887 | |
3888 void Assembler::fdiv_s(Address src) { | |
3889 InstructionMark im(this); | |
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3890 emit_int8((unsigned char)0xD8); |
304 | 3891 emit_operand32(rsi, src); |
3892 } | |
3893 | |
3894 void Assembler::fdiva(int i) { | |
3895 emit_farith(0xDC, 0xF8, i); | |
3896 } | |
3897 | |
3898 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994) | |
3899 // is erroneous for some of the floating-point instructions below. | |
3900 | |
3901 void Assembler::fdivp(int i) { | |
3902 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong) | |
3903 } | |
3904 | |
3905 void Assembler::fdivr(int i) { | |
3906 emit_farith(0xD8, 0xF8, i); | |
3907 } | |
3908 | |
3909 void Assembler::fdivr_d(Address src) { | |
3910 InstructionMark im(this); | |
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3911 emit_int8((unsigned char)0xDC); |
304 | 3912 emit_operand32(rdi, src); |
3913 } | |
3914 | |
3915 void Assembler::fdivr_s(Address src) { | |
3916 InstructionMark im(this); | |
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3917 emit_int8((unsigned char)0xD8); |
304 | 3918 emit_operand32(rdi, src); |
3919 } | |
3920 | |
3921 void Assembler::fdivra(int i) { | |
3922 emit_farith(0xDC, 0xF0, i); | |
3923 } | |
3924 | |
3925 void Assembler::fdivrp(int i) { | |
3926 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong) | |
3927 } | |
3928 | |
3929 void Assembler::ffree(int i) { | |
3930 emit_farith(0xDD, 0xC0, i); | |
3931 } | |
3932 | |
3933 void Assembler::fild_d(Address adr) { | |
3934 InstructionMark im(this); | |
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3935 emit_int8((unsigned char)0xDF); |
304 | 3936 emit_operand32(rbp, adr); |
3937 } | |
3938 | |
3939 void Assembler::fild_s(Address adr) { | |
3940 InstructionMark im(this); | |
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3941 emit_int8((unsigned char)0xDB); |
304 | 3942 emit_operand32(rax, adr); |
3943 } | |
3944 | |
3945 void Assembler::fincstp() { | |
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3946 emit_int8((unsigned char)0xD9); |
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3947 emit_int8((unsigned char)0xF7); |
304 | 3948 } |
3949 | |
3950 void Assembler::finit() { | |
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|
3951 emit_int8((unsigned char)0x9B); |
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|
3952 emit_int8((unsigned char)0xDB); |
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|
3953 emit_int8((unsigned char)0xE3); |
304 | 3954 } |
3955 | |
3956 void Assembler::fist_s(Address adr) { | |
3957 InstructionMark im(this); | |
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|
3958 emit_int8((unsigned char)0xDB); |
304 | 3959 emit_operand32(rdx, adr); |
3960 } | |
3961 | |
3962 void Assembler::fistp_d(Address adr) { | |
3963 InstructionMark im(this); | |
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|
3964 emit_int8((unsigned char)0xDF); |
304 | 3965 emit_operand32(rdi, adr); |
3966 } | |
3967 | |
3968 void Assembler::fistp_s(Address adr) { | |
3969 InstructionMark im(this); | |
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|
3970 emit_int8((unsigned char)0xDB); |
304 | 3971 emit_operand32(rbx, adr); |
3972 } | |
0 | 3973 |
3974 void Assembler::fld1() { | |
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|
3975 emit_int8((unsigned char)0xD9); |
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|
3976 emit_int8((unsigned char)0xE8); |
0 | 3977 } |
3978 | |
304 | 3979 void Assembler::fld_d(Address adr) { |
3980 InstructionMark im(this); | |
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|
3981 emit_int8((unsigned char)0xDD); |
304 | 3982 emit_operand32(rax, adr); |
3983 } | |
0 | 3984 |
3985 void Assembler::fld_s(Address adr) { | |
3986 InstructionMark im(this); | |
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3987 emit_int8((unsigned char)0xD9); |
304 | 3988 emit_operand32(rax, adr); |
3989 } | |
3990 | |
3991 | |
3992 void Assembler::fld_s(int index) { | |
0 | 3993 emit_farith(0xD9, 0xC0, index); |
3994 } | |
3995 | |
3996 void Assembler::fld_x(Address adr) { | |
3997 InstructionMark im(this); | |
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|
3998 emit_int8((unsigned char)0xDB); |
304 | 3999 emit_operand32(rbp, adr); |
4000 } | |
4001 | |
4002 void Assembler::fldcw(Address src) { | |
4003 InstructionMark im(this); | |
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4004 emit_int8((unsigned char)0xD9); |
304 | 4005 emit_operand32(rbp, src); |
4006 } | |
4007 | |
4008 void Assembler::fldenv(Address src) { | |
0 | 4009 InstructionMark im(this); |
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4010 emit_int8((unsigned char)0xD9); |
304 | 4011 emit_operand32(rsp, src); |
4012 } | |
4013 | |
4014 void Assembler::fldlg2() { | |
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4015 emit_int8((unsigned char)0xD9); |
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|
4016 emit_int8((unsigned char)0xEC); |
304 | 4017 } |
0 | 4018 |
4019 void Assembler::fldln2() { | |
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|
4020 emit_int8((unsigned char)0xD9); |
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4021 emit_int8((unsigned char)0xED); |
0 | 4022 } |
4023 | |
304 | 4024 void Assembler::fldz() { |
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|
4025 emit_int8((unsigned char)0xD9); |
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4026 emit_int8((unsigned char)0xEE); |
304 | 4027 } |
0 | 4028 |
4029 void Assembler::flog() { | |
4030 fldln2(); | |
4031 fxch(); | |
4032 fyl2x(); | |
4033 } | |
4034 | |
4035 void Assembler::flog10() { | |
4036 fldlg2(); | |
4037 fxch(); | |
4038 fyl2x(); | |
4039 } | |
4040 | |
304 | 4041 void Assembler::fmul(int i) { |
4042 emit_farith(0xD8, 0xC8, i); | |
4043 } | |
4044 | |
4045 void Assembler::fmul_d(Address src) { | |
4046 InstructionMark im(this); | |
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|
4047 emit_int8((unsigned char)0xDC); |
304 | 4048 emit_operand32(rcx, src); |
4049 } | |
4050 | |
4051 void Assembler::fmul_s(Address src) { | |
4052 InstructionMark im(this); | |
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|
4053 emit_int8((unsigned char)0xD8); |
304 | 4054 emit_operand32(rcx, src); |
4055 } | |
4056 | |
4057 void Assembler::fmula(int i) { | |
4058 emit_farith(0xDC, 0xC8, i); | |
4059 } | |
4060 | |
4061 void Assembler::fmulp(int i) { | |
4062 emit_farith(0xDE, 0xC8, i); | |
4063 } | |
4064 | |
4065 void Assembler::fnsave(Address dst) { | |
4066 InstructionMark im(this); | |
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|
4067 emit_int8((unsigned char)0xDD); |
304 | 4068 emit_operand32(rsi, dst); |
4069 } | |
4070 | |
4071 void Assembler::fnstcw(Address src) { | |
4072 InstructionMark im(this); | |
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|
4073 emit_int8((unsigned char)0x9B); |
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|
4074 emit_int8((unsigned char)0xD9); |
304 | 4075 emit_operand32(rdi, src); |
4076 } | |
4077 | |
4078 void Assembler::fnstsw_ax() { | |
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|
4079 emit_int8((unsigned char)0xDF); |
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|
4080 emit_int8((unsigned char)0xE0); |
304 | 4081 } |
4082 | |
4083 void Assembler::fprem() { | |
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|
4084 emit_int8((unsigned char)0xD9); |
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changeset
|
4085 emit_int8((unsigned char)0xF8); |
304 | 4086 } |
4087 | |
4088 void Assembler::fprem1() { | |
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4089 emit_int8((unsigned char)0xD9); |
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4090 emit_int8((unsigned char)0xF5); |
304 | 4091 } |
4092 | |
4093 void Assembler::frstor(Address src) { | |
4094 InstructionMark im(this); | |
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4095 emit_int8((unsigned char)0xDD); |
304 | 4096 emit_operand32(rsp, src); |
4097 } | |
0 | 4098 |
4099 void Assembler::fsin() { | |
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4100 emit_int8((unsigned char)0xD9); |
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4101 emit_int8((unsigned char)0xFE); |
0 | 4102 } |
4103 | |
304 | 4104 void Assembler::fsqrt() { |
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4105 emit_int8((unsigned char)0xD9); |
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4106 emit_int8((unsigned char)0xFA); |
304 | 4107 } |
4108 | |
4109 void Assembler::fst_d(Address adr) { | |
4110 InstructionMark im(this); | |
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4111 emit_int8((unsigned char)0xDD); |
304 | 4112 emit_operand32(rdx, adr); |
4113 } | |
4114 | |
4115 void Assembler::fst_s(Address adr) { | |
4116 InstructionMark im(this); | |
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4117 emit_int8((unsigned char)0xD9); |
304 | 4118 emit_operand32(rdx, adr); |
4119 } | |
4120 | |
4121 void Assembler::fstp_d(Address adr) { | |
4122 InstructionMark im(this); | |
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4123 emit_int8((unsigned char)0xDD); |
304 | 4124 emit_operand32(rbx, adr); |
4125 } | |
4126 | |
4127 void Assembler::fstp_d(int index) { | |
4128 emit_farith(0xDD, 0xD8, index); | |
4129 } | |
4130 | |
4131 void Assembler::fstp_s(Address adr) { | |
4132 InstructionMark im(this); | |
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4133 emit_int8((unsigned char)0xD9); |
304 | 4134 emit_operand32(rbx, adr); |
4135 } | |
4136 | |
4137 void Assembler::fstp_x(Address adr) { | |
4138 InstructionMark im(this); | |
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4139 emit_int8((unsigned char)0xDB); |
304 | 4140 emit_operand32(rdi, adr); |
4141 } | |
4142 | |
4143 void Assembler::fsub(int i) { | |
4144 emit_farith(0xD8, 0xE0, i); | |
4145 } | |
4146 | |
4147 void Assembler::fsub_d(Address src) { | |
4148 InstructionMark im(this); | |
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4149 emit_int8((unsigned char)0xDC); |
304 | 4150 emit_operand32(rsp, src); |
4151 } | |
4152 | |
4153 void Assembler::fsub_s(Address src) { | |
4154 InstructionMark im(this); | |
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4155 emit_int8((unsigned char)0xD8); |
304 | 4156 emit_operand32(rsp, src); |
4157 } | |
4158 | |
4159 void Assembler::fsuba(int i) { | |
4160 emit_farith(0xDC, 0xE8, i); | |
4161 } | |
4162 | |
4163 void Assembler::fsubp(int i) { | |
4164 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong) | |
4165 } | |
4166 | |
4167 void Assembler::fsubr(int i) { | |
4168 emit_farith(0xD8, 0xE8, i); | |
4169 } | |
4170 | |
4171 void Assembler::fsubr_d(Address src) { | |
4172 InstructionMark im(this); | |
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4173 emit_int8((unsigned char)0xDC); |
304 | 4174 emit_operand32(rbp, src); |
4175 } | |
4176 | |
4177 void Assembler::fsubr_s(Address src) { | |
4178 InstructionMark im(this); | |
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4179 emit_int8((unsigned char)0xD8); |
304 | 4180 emit_operand32(rbp, src); |
4181 } | |
4182 | |
4183 void Assembler::fsubra(int i) { | |
4184 emit_farith(0xDC, 0xE0, i); | |
4185 } | |
4186 | |
4187 void Assembler::fsubrp(int i) { | |
4188 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong) | |
0 | 4189 } |
4190 | |
4191 void Assembler::ftan() { | |
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|
4192 emit_int8((unsigned char)0xD9); |
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4193 emit_int8((unsigned char)0xF2); |
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4194 emit_int8((unsigned char)0xDD); |
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4195 emit_int8((unsigned char)0xD8); |
0 | 4196 } |
4197 | |
304 | 4198 void Assembler::ftst() { |
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4199 emit_int8((unsigned char)0xD9); |
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4200 emit_int8((unsigned char)0xE4); |
304 | 4201 } |
0 | 4202 |
4203 void Assembler::fucomi(int i) { | |
4204 // make sure the instruction is supported (introduced for P6, together with cmov) | |
4205 guarantee(VM_Version::supports_cmov(), "illegal instruction"); | |
4206 emit_farith(0xDB, 0xE8, i); | |
4207 } | |
4208 | |
4209 void Assembler::fucomip(int i) { | |
4210 // make sure the instruction is supported (introduced for P6, together with cmov) | |
4211 guarantee(VM_Version::supports_cmov(), "illegal instruction"); | |
4212 emit_farith(0xDF, 0xE8, i); | |
4213 } | |
4214 | |
4215 void Assembler::fwait() { | |
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4216 emit_int8((unsigned char)0x9B); |
0 | 4217 } |
4218 | |
304 | 4219 void Assembler::fxch(int i) { |
4220 emit_farith(0xD9, 0xC8, i); | |
4221 } | |
4222 | |
4223 void Assembler::fyl2x() { | |
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4224 emit_int8((unsigned char)0xD9); |
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4225 emit_int8((unsigned char)0xF1); |
304 | 4226 } |
4227 | |
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4228 void Assembler::frndint() { |
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4229 emit_int8((unsigned char)0xD9); |
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4230 emit_int8((unsigned char)0xFC); |
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4231 } |
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|
4232 |
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4233 void Assembler::f2xm1() { |
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4234 emit_int8((unsigned char)0xD9); |
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4235 emit_int8((unsigned char)0xF0); |
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|
4236 } |
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|
4237 |
6759698e3140
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4238 void Assembler::fldl2e() { |
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4239 emit_int8((unsigned char)0xD9); |
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|
4240 emit_int8((unsigned char)0xEA); |
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|
4241 } |
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4242 |
4759 | 4243 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding. |
4244 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 }; | |
4245 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding. | |
4246 static int simd_opc[4] = { 0, 0, 0x38, 0x3A }; | |
4247 | |
4248 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding. | |
4249 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { | |
4250 if (pre > 0) { | |
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4251 emit_int8(simd_pre[pre]); |
4759 | 4252 } |
4253 if (rex_w) { | |
4254 prefixq(adr, xreg); | |
4255 } else { | |
4256 prefix(adr, xreg); | |
4257 } | |
4258 if (opc > 0) { | |
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4259 emit_int8(0x0F); |
4759 | 4260 int opc2 = simd_opc[opc]; |
4261 if (opc2 > 0) { | |
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4262 emit_int8(opc2); |
4759 | 4263 } |
4264 } | |
4265 } | |
4266 | |
4267 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { | |
4268 if (pre > 0) { | |
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4269 emit_int8(simd_pre[pre]); |
4759 | 4270 } |
4271 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : | |
4272 prefix_and_encode(dst_enc, src_enc); | |
4273 if (opc > 0) { | |
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|
4274 emit_int8(0x0F); |
4759 | 4275 int opc2 = simd_opc[opc]; |
4276 if (opc2 > 0) { | |
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|
4277 emit_int8(opc2); |
4759 | 4278 } |
4279 } | |
4280 return encode; | |
4281 } | |
4282 | |
4283 | |
4284 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, int nds_enc, VexSimdPrefix pre, VexOpcode opc, bool vector256) { | |
4285 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) { | |
4286 prefix(VEX_3bytes); | |
4287 | |
4288 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0); | |
4289 byte1 = (~byte1) & 0xE0; | |
4290 byte1 |= opc; | |
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|
4291 emit_int8(byte1); |
4759 | 4292 |
4293 int byte2 = ((~nds_enc) & 0xf) << 3; | |
4294 byte2 |= (vex_w ? VEX_W : 0) | (vector256 ? 4 : 0) | pre; | |
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|
4295 emit_int8(byte2); |
4759 | 4296 } else { |
4297 prefix(VEX_2bytes); | |
4298 | |
4299 int byte1 = vex_r ? VEX_R : 0; | |
4300 byte1 = (~byte1) & 0x80; | |
4301 byte1 |= ((~nds_enc) & 0xf) << 3; | |
4302 byte1 |= (vector256 ? 4 : 0) | pre; | |
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|
4303 emit_int8(byte1); |
4759 | 4304 } |
4305 } | |
4306 | |
4307 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256){ | |
4308 bool vex_r = (xreg_enc >= 8); | |
4309 bool vex_b = adr.base_needs_rex(); | |
4310 bool vex_x = adr.index_needs_rex(); | |
4311 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256); | |
4312 } | |
4313 | |
4314 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256) { | |
4315 bool vex_r = (dst_enc >= 8); | |
4316 bool vex_b = (src_enc >= 8); | |
4317 bool vex_x = false; | |
4318 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256); | |
4319 return (((dst_enc & 7) << 3) | (src_enc & 7)); | |
4320 } | |
4321 | |
4322 | |
4323 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) { | |
4324 if (UseAVX > 0) { | |
4325 int xreg_enc = xreg->encoding(); | |
4326 int nds_enc = nds->is_valid() ? nds->encoding() : 0; | |
4327 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, rex_w, vector256); | |
4328 } else { | |
4329 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding"); | |
4330 rex_prefix(adr, xreg, pre, opc, rex_w); | |
4331 } | |
4332 } | |
4333 | |
4334 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) { | |
4335 int dst_enc = dst->encoding(); | |
4336 int src_enc = src->encoding(); | |
4337 if (UseAVX > 0) { | |
4338 int nds_enc = nds->is_valid() ? nds->encoding() : 0; | |
4339 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector256); | |
4340 } else { | |
4341 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding"); | |
4342 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, rex_w); | |
4343 } | |
4344 } | |
304 | 4345 |
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4346 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) { |
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4347 InstructionMark im(this); |
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4348 simd_prefix(dst, dst, src, pre); |
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4349 emit_int8(opcode); |
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4350 emit_operand(dst, src); |
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4351 } |
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4352 |
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4353 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) { |
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4354 int encode = simd_prefix_and_encode(dst, dst, src, pre); |
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4355 emit_int8(opcode); |
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4356 emit_int8((unsigned char)(0xC0 | encode)); |
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4357 } |
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4358 |
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4359 // Versions with no second source register (non-destructive source). |
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4360 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) { |
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4361 InstructionMark im(this); |
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4362 simd_prefix(dst, xnoreg, src, pre); |
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4363 emit_int8(opcode); |
6614
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4364 emit_operand(dst, src); |
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4365 } |
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4366 |
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4367 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) { |
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4368 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre); |
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4369 emit_int8(opcode); |
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4370 emit_int8((unsigned char)(0xC0 | encode)); |
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4371 } |
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4372 |
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4373 // 3-operands AVX instructions |
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4374 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, |
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4375 Address src, VexSimdPrefix pre, bool vector256) { |
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4376 InstructionMark im(this); |
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4377 vex_prefix(dst, nds, src, pre, vector256); |
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4378 emit_int8(opcode); |
6614
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4379 emit_operand(dst, src); |
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4380 } |
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4381 |
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4382 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds, |
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4383 XMMRegister src, VexSimdPrefix pre, bool vector256) { |
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4384 int encode = vex_prefix_and_encode(dst, nds, src, pre, vector256); |
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4385 emit_int8(opcode); |
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4386 emit_int8((unsigned char)(0xC0 | encode)); |
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4387 } |
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4388 |
304 | 4389 #ifndef _LP64 |
4390 | |
4391 void Assembler::incl(Register dst) { | |
4392 // Don't use it directly. Use MacroAssembler::incrementl() instead. | |
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4393 emit_int8(0x40 | dst->encoding()); |
304 | 4394 } |
4395 | |
4396 void Assembler::lea(Register dst, Address src) { | |
4397 leal(dst, src); | |
4398 } | |
4399 | |
4400 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) { | |
4401 InstructionMark im(this); | |
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4402 emit_int8((unsigned char)0xC7); |
304 | 4403 emit_operand(rax, dst); |
4404 emit_data((int)imm32, rspec, 0); | |
4405 } | |
4406 | |
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4407 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) { |
660978a2a31a
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4408 InstructionMark im(this); |
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4409 int encode = prefix_and_encode(dst->encoding()); |
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4410 emit_int8((unsigned char)(0xB8 | encode)); |
642
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4411 emit_data((int)imm32, rspec, 0); |
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4412 } |
304 | 4413 |
4414 void Assembler::popa() { // 32bit | |
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4415 emit_int8(0x61); |
304 | 4416 } |
4417 | |
4418 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) { | |
4419 InstructionMark im(this); | |
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|
4420 emit_int8(0x68); |
304 | 4421 emit_data(imm32, rspec, 0); |
4422 } | |
4423 | |
4424 void Assembler::pusha() { // 32bit | |
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4425 emit_int8(0x60); |
304 | 4426 } |
4427 | |
4428 void Assembler::set_byte_if_not_zero(Register dst) { | |
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4429 emit_int8(0x0F); |
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4430 emit_int8((unsigned char)0x95); |
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4431 emit_int8((unsigned char)(0xE0 | dst->encoding())); |
304 | 4432 } |
4433 | |
4434 void Assembler::shldl(Register dst, Register src) { | |
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4435 emit_int8(0x0F); |
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4436 emit_int8((unsigned char)0xA5); |
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4437 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding())); |
304 | 4438 } |
4439 | |
4440 void Assembler::shrdl(Register dst, Register src) { | |
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4441 emit_int8(0x0F); |
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4442 emit_int8((unsigned char)0xAD); |
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4443 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding())); |
304 | 4444 } |
4445 | |
4446 #else // LP64 | |
4447 | |
1369 | 4448 void Assembler::set_byte_if_not_zero(Register dst) { |
4449 int enc = prefix_and_encode(dst->encoding(), true); | |
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4450 emit_int8(0x0F); |
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4451 emit_int8((unsigned char)0x95); |
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4452 emit_int8((unsigned char)(0xE0 | enc)); |
1369 | 4453 } |
4454 | |
304 | 4455 // 64bit only pieces of the assembler |
4456 // This should only be used by 64bit instructions that can use rip-relative | |
4457 // it cannot be used by instructions that want an immediate value. | |
4458 | |
4459 bool Assembler::reachable(AddressLiteral adr) { | |
4460 int64_t disp; | |
4461 // None will force a 64bit literal to the code stream. Likely a placeholder | |
4462 // for something that will be patched later and we need to certain it will | |
4463 // always be reachable. | |
4464 if (adr.reloc() == relocInfo::none) { | |
4465 return false; | |
4466 } | |
4467 if (adr.reloc() == relocInfo::internal_word_type) { | |
4468 // This should be rip relative and easily reachable. | |
4469 return true; | |
4470 } | |
4471 if (adr.reloc() == relocInfo::virtual_call_type || | |
4472 adr.reloc() == relocInfo::opt_virtual_call_type || | |
4473 adr.reloc() == relocInfo::static_call_type || | |
4474 adr.reloc() == relocInfo::static_stub_type ) { | |
4475 // This should be rip relative within the code cache and easily | |
4476 // reachable until we get huge code caches. (At which point | |
4477 // ic code is going to have issues). | |
4478 return true; | |
4479 } | |
4480 if (adr.reloc() != relocInfo::external_word_type && | |
4481 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special | |
4482 adr.reloc() != relocInfo::poll_type && // relocs to identify them | |
4483 adr.reloc() != relocInfo::runtime_call_type ) { | |
4484 return false; | |
4485 } | |
4486 | |
4487 // Stress the correction code | |
4488 if (ForceUnreachable) { | |
4489 // Must be runtimecall reloc, see if it is in the codecache | |
4490 // Flipping stuff in the codecache to be unreachable causes issues | |
4491 // with things like inline caches where the additional instructions | |
4492 // are not handled. | |
4493 if (CodeCache::find_blob(adr._target) == NULL) { | |
4494 return false; | |
4495 } | |
4496 } | |
4497 // For external_word_type/runtime_call_type if it is reachable from where we | |
4498 // are now (possibly a temp buffer) and where we might end up | |
4499 // anywhere in the codeCache then we are always reachable. | |
4500 // This would have to change if we ever save/restore shared code | |
4501 // to be more pessimistic. | |
4502 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int)); | |
4503 if (!is_simm32(disp)) return false; | |
4504 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int)); | |
4505 if (!is_simm32(disp)) return false; | |
4506 | |
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twisti
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4507 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int)); |
304 | 4508 |
4509 // Because rip relative is a disp + address_of_next_instruction and we | |
4510 // don't know the value of address_of_next_instruction we apply a fudge factor | |
4511 // to make sure we will be ok no matter the size of the instruction we get placed into. | |
4512 // We don't have to fudge the checks above here because they are already worst case. | |
4513 | |
4514 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal | |
4515 // + 4 because better safe than sorry. | |
4516 const int fudge = 12 + 4; | |
4517 if (disp < 0) { | |
4518 disp -= fudge; | |
4519 } else { | |
4520 disp += fudge; | |
4521 } | |
4522 return is_simm32(disp); | |
4523 } | |
4524 | |
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|
4525 // Check if the polling page is not reachable from the code cache using rip-relative |
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|
4526 // addressing. |
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|
4527 bool Assembler::is_polling_page_far() { |
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diff
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|
4528 intptr_t addr = (intptr_t)os::get_polling_page(); |
4118
59bc0d4d9ea3
7110489: C1: 64-bit tiered with ForceUnreachable: assert(reachable(src)) failed: Address should be reachable
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diff
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|
4529 return ForceUnreachable || |
59bc0d4d9ea3
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|
4530 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) || |
2404
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4531 !is_simm32(addr - (intptr_t)CodeCache::high_bound()); |
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4532 } |
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|
4533 |
304 | 4534 void Assembler::emit_data64(jlong data, |
4535 relocInfo::relocType rtype, | |
4536 int format) { | |
4537 if (rtype == relocInfo::none) { | |
7198
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4538 emit_int64(data); |
304 | 4539 } else { |
4540 emit_data64(data, Relocation::spec_simple(rtype), format); | |
4541 } | |
4542 } | |
4543 | |
4544 void Assembler::emit_data64(jlong data, | |
4545 RelocationHolder const& rspec, | |
4546 int format) { | |
4547 assert(imm_operand == 0, "default format must be immediate in this file"); | |
4548 assert(imm_operand == format, "must be immediate"); | |
4549 assert(inst_mark() != NULL, "must be inside InstructionMark"); | |
4550 // Do not use AbstractAssembler::relocate, which is not intended for | |
4551 // embedded words. Instead, relocate to the enclosing instruction. | |
4552 code_section()->relocate(inst_mark(), rspec, format); | |
4553 #ifdef ASSERT | |
4554 check_relocation(rspec, format); | |
4555 #endif | |
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4556 emit_int64(data); |
304 | 4557 } |
4558 | |
4559 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) { | |
4560 if (reg_enc >= 8) { | |
4561 prefix(REX_B); | |
4562 reg_enc -= 8; | |
4563 } else if (byteinst && reg_enc >= 4) { | |
4564 prefix(REX); | |
4565 } | |
4566 return reg_enc; | |
4567 } | |
4568 | |
4569 int Assembler::prefixq_and_encode(int reg_enc) { | |
4570 if (reg_enc < 8) { | |
4571 prefix(REX_W); | |
4572 } else { | |
4573 prefix(REX_WB); | |
4574 reg_enc -= 8; | |
4575 } | |
4576 return reg_enc; | |
4577 } | |
4578 | |
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Christian Wimmer <christian.wimmer@oracle.com>
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16047
diff
changeset
|
4579 int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) { |
304 | 4580 if (dst_enc < 8) { |
4581 if (src_enc >= 8) { | |
4582 prefix(REX_B); | |
4583 src_enc -= 8; | |
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|
4584 } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) { |
304 | 4585 prefix(REX); |
4586 } | |
4587 } else { | |
4588 if (src_enc < 8) { | |
4589 prefix(REX_R); | |
4590 } else { | |
4591 prefix(REX_RB); | |
4592 src_enc -= 8; | |
4593 } | |
4594 dst_enc -= 8; | |
4595 } | |
4596 return dst_enc << 3 | src_enc; | |
4597 } | |
4598 | |
4599 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) { | |
4600 if (dst_enc < 8) { | |
4601 if (src_enc < 8) { | |
4602 prefix(REX_W); | |
4603 } else { | |
4604 prefix(REX_WB); | |
4605 src_enc -= 8; | |
4606 } | |
4607 } else { | |
4608 if (src_enc < 8) { | |
4609 prefix(REX_WR); | |
4610 } else { | |
4611 prefix(REX_WRB); | |
4612 src_enc -= 8; | |
4613 } | |
4614 dst_enc -= 8; | |
4615 } | |
4616 return dst_enc << 3 | src_enc; | |
4617 } | |
4618 | |
4619 void Assembler::prefix(Register reg) { | |
4620 if (reg->encoding() >= 8) { | |
4621 prefix(REX_B); | |
4622 } | |
4623 } | |
4624 | |
4625 void Assembler::prefix(Address adr) { | |
4626 if (adr.base_needs_rex()) { | |
4627 if (adr.index_needs_rex()) { | |
4628 prefix(REX_XB); | |
4629 } else { | |
4630 prefix(REX_B); | |
4631 } | |
4632 } else { | |
4633 if (adr.index_needs_rex()) { | |
4634 prefix(REX_X); | |
4635 } | |
4636 } | |
4637 } | |
4638 | |
4639 void Assembler::prefixq(Address adr) { | |
4640 if (adr.base_needs_rex()) { | |
4641 if (adr.index_needs_rex()) { | |
4642 prefix(REX_WXB); | |
4643 } else { | |
4644 prefix(REX_WB); | |
4645 } | |
4646 } else { | |
4647 if (adr.index_needs_rex()) { | |
4648 prefix(REX_WX); | |
4649 } else { | |
4650 prefix(REX_W); | |
4651 } | |
4652 } | |
4653 } | |
4654 | |
4655 | |
4656 void Assembler::prefix(Address adr, Register reg, bool byteinst) { | |
4657 if (reg->encoding() < 8) { | |
4658 if (adr.base_needs_rex()) { | |
4659 if (adr.index_needs_rex()) { | |
4660 prefix(REX_XB); | |
4661 } else { | |
4662 prefix(REX_B); | |
4663 } | |
4664 } else { | |
4665 if (adr.index_needs_rex()) { | |
4666 prefix(REX_X); | |
3855 | 4667 } else if (byteinst && reg->encoding() >= 4 ) { |
304 | 4668 prefix(REX); |
4669 } | |
4670 } | |
4671 } else { | |
4672 if (adr.base_needs_rex()) { | |
4673 if (adr.index_needs_rex()) { | |
4674 prefix(REX_RXB); | |
4675 } else { | |
4676 prefix(REX_RB); | |
4677 } | |
4678 } else { | |
4679 if (adr.index_needs_rex()) { | |
4680 prefix(REX_RX); | |
4681 } else { | |
4682 prefix(REX_R); | |
4683 } | |
4684 } | |
4685 } | |
4686 } | |
4687 | |
4688 void Assembler::prefixq(Address adr, Register src) { | |
4689 if (src->encoding() < 8) { | |
4690 if (adr.base_needs_rex()) { | |
4691 if (adr.index_needs_rex()) { | |
4692 prefix(REX_WXB); | |
4693 } else { | |
4694 prefix(REX_WB); | |
4695 } | |
4696 } else { | |
4697 if (adr.index_needs_rex()) { | |
4698 prefix(REX_WX); | |
4699 } else { | |
4700 prefix(REX_W); | |
4701 } | |
4702 } | |
4703 } else { | |
4704 if (adr.base_needs_rex()) { | |
4705 if (adr.index_needs_rex()) { | |
4706 prefix(REX_WRXB); | |
4707 } else { | |
4708 prefix(REX_WRB); | |
4709 } | |
4710 } else { | |
4711 if (adr.index_needs_rex()) { | |
4712 prefix(REX_WRX); | |
4713 } else { | |
4714 prefix(REX_WR); | |
4715 } | |
4716 } | |
4717 } | |
4718 } | |
4719 | |
4720 void Assembler::prefix(Address adr, XMMRegister reg) { | |
4721 if (reg->encoding() < 8) { | |
4722 if (adr.base_needs_rex()) { | |
4723 if (adr.index_needs_rex()) { | |
4724 prefix(REX_XB); | |
4725 } else { | |
4726 prefix(REX_B); | |
4727 } | |
4728 } else { | |
4729 if (adr.index_needs_rex()) { | |
4730 prefix(REX_X); | |
4731 } | |
4732 } | |
4733 } else { | |
4734 if (adr.base_needs_rex()) { | |
4735 if (adr.index_needs_rex()) { | |
4736 prefix(REX_RXB); | |
4737 } else { | |
4738 prefix(REX_RB); | |
4739 } | |
4740 } else { | |
4741 if (adr.index_needs_rex()) { | |
4742 prefix(REX_RX); | |
4743 } else { | |
4744 prefix(REX_R); | |
4745 } | |
4746 } | |
4747 } | |
4748 } | |
4749 | |
4759 | 4750 void Assembler::prefixq(Address adr, XMMRegister src) { |
4751 if (src->encoding() < 8) { | |
4752 if (adr.base_needs_rex()) { | |
4753 if (adr.index_needs_rex()) { | |
4754 prefix(REX_WXB); | |
4755 } else { | |
4756 prefix(REX_WB); | |
4757 } | |
4758 } else { | |
4759 if (adr.index_needs_rex()) { | |
4760 prefix(REX_WX); | |
4761 } else { | |
4762 prefix(REX_W); | |
4763 } | |
4764 } | |
4765 } else { | |
4766 if (adr.base_needs_rex()) { | |
4767 if (adr.index_needs_rex()) { | |
4768 prefix(REX_WRXB); | |
4769 } else { | |
4770 prefix(REX_WRB); | |
4771 } | |
4772 } else { | |
4773 if (adr.index_needs_rex()) { | |
4774 prefix(REX_WRX); | |
4775 } else { | |
4776 prefix(REX_WR); | |
4777 } | |
4778 } | |
4779 } | |
4780 } | |
4781 | |
304 | 4782 void Assembler::adcq(Register dst, int32_t imm32) { |
4783 (void) prefixq_and_encode(dst->encoding()); | |
4784 emit_arith(0x81, 0xD0, dst, imm32); | |
4785 } | |
4786 | |
4787 void Assembler::adcq(Register dst, Address src) { | |
4788 InstructionMark im(this); | |
4789 prefixq(src, dst); | |
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changeset
|
4790 emit_int8(0x13); |
304 | 4791 emit_operand(dst, src); |
4792 } | |
4793 | |
4794 void Assembler::adcq(Register dst, Register src) { | |
12329 | 4795 (void) prefixq_and_encode(dst->encoding(), src->encoding()); |
304 | 4796 emit_arith(0x13, 0xC0, dst, src); |
4797 } | |
4798 | |
4799 void Assembler::addq(Address dst, int32_t imm32) { | |
4800 InstructionMark im(this); | |
4801 prefixq(dst); | |
4802 emit_arith_operand(0x81, rax, dst,imm32); | |
4803 } | |
4804 | |
4805 void Assembler::addq(Address dst, Register src) { | |
4806 InstructionMark im(this); | |
4807 prefixq(dst, src); | |
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changeset
|
4808 emit_int8(0x01); |
304 | 4809 emit_operand(src, dst); |
4810 } | |
4811 | |
4812 void Assembler::addq(Register dst, int32_t imm32) { | |
4813 (void) prefixq_and_encode(dst->encoding()); | |
4814 emit_arith(0x81, 0xC0, dst, imm32); | |
4815 } | |
4816 | |
4817 void Assembler::addq(Register dst, Address src) { | |
4818 InstructionMark im(this); | |
4819 prefixq(src, dst); | |
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diff
changeset
|
4820 emit_int8(0x03); |
304 | 4821 emit_operand(dst, src); |
4822 } | |
4823 | |
4824 void Assembler::addq(Register dst, Register src) { | |
4825 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
4826 emit_arith(0x03, 0xC0, dst, src); | |
4827 } | |
4828 | |
3457 | 4829 void Assembler::andq(Address dst, int32_t imm32) { |
4830 InstructionMark im(this); | |
4831 prefixq(dst); | |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
4832 emit_int8((unsigned char)0x81); |
3457 | 4833 emit_operand(rsp, dst, 4); |
7476
ffa87474d7a4
8004537: replace AbstractAssembler emit_long with emit_int32
twisti
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7475
diff
changeset
|
4834 emit_int32(imm32); |
3457 | 4835 } |
4836 | |
304 | 4837 void Assembler::andq(Register dst, int32_t imm32) { |
4838 (void) prefixq_and_encode(dst->encoding()); | |
4839 emit_arith(0x81, 0xE0, dst, imm32); | |
4840 } | |
4841 | |
4842 void Assembler::andq(Register dst, Address src) { | |
4843 InstructionMark im(this); | |
4844 prefixq(src, dst); | |
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diff
changeset
|
4845 emit_int8(0x23); |
304 | 4846 emit_operand(dst, src); |
4847 } | |
4848 | |
4849 void Assembler::andq(Register dst, Register src) { | |
12329 | 4850 (void) prefixq_and_encode(dst->encoding(), src->encoding()); |
304 | 4851 emit_arith(0x23, 0xC0, dst, src); |
4852 } | |
4853 | |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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diff
changeset
|
4854 void Assembler::bsfq(Register dst, Register src) { |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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diff
changeset
|
4855 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
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diff
changeset
|
4856 emit_int8(0x0F); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4857 emit_int8((unsigned char)0xBC); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4858 emit_int8((unsigned char)(0xC0 | encode)); |
775
93c14e5562c4
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twisti
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diff
changeset
|
4859 } |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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diff
changeset
|
4860 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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diff
changeset
|
4861 void Assembler::bsrq(Register dst, Register src) { |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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diff
changeset
|
4862 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT"); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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diff
changeset
|
4863 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4864 emit_int8(0x0F); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4865 emit_int8((unsigned char)0xBD); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
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diff
changeset
|
4866 emit_int8((unsigned char)(0xC0 | encode)); |
775
93c14e5562c4
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twisti
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710
diff
changeset
|
4867 } |
93c14e5562c4
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twisti
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diff
changeset
|
4868 |
304 | 4869 void Assembler::bswapq(Register reg) { |
4870 int encode = prefixq_and_encode(reg->encoding()); | |
7430
d02120b7a34f
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diff
changeset
|
4871 emit_int8(0x0F); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4872 emit_int8((unsigned char)(0xC8 | encode)); |
304 | 4873 } |
4874 | |
4875 void Assembler::cdqq() { | |
4876 prefix(REX_W); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4877 emit_int8((unsigned char)0x99); |
304 | 4878 } |
4879 | |
4880 void Assembler::clflush(Address adr) { | |
4881 prefix(adr); | |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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|
4882 emit_int8(0x0F); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4883 emit_int8((unsigned char)0xAE); |
304 | 4884 emit_operand(rdi, adr); |
4885 } | |
4886 | |
4887 void Assembler::cmovq(Condition cc, Register dst, Register src) { | |
4888 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
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changeset
|
4889 emit_int8(0x0F); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4890 emit_int8(0x40 | cc); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4891 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 4892 } |
4893 | |
4894 void Assembler::cmovq(Condition cc, Register dst, Address src) { | |
4895 InstructionMark im(this); | |
4896 prefixq(src, dst); | |
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diff
changeset
|
4897 emit_int8(0x0F); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4898 emit_int8(0x40 | cc); |
304 | 4899 emit_operand(dst, src); |
4900 } | |
4901 | |
4902 void Assembler::cmpq(Address dst, int32_t imm32) { | |
4903 InstructionMark im(this); | |
4904 prefixq(dst); | |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4905 emit_int8((unsigned char)0x81); |
304 | 4906 emit_operand(rdi, dst, 4); |
7476
ffa87474d7a4
8004537: replace AbstractAssembler emit_long with emit_int32
twisti
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7475
diff
changeset
|
4907 emit_int32(imm32); |
304 | 4908 } |
4909 | |
4910 void Assembler::cmpq(Register dst, int32_t imm32) { | |
4911 (void) prefixq_and_encode(dst->encoding()); | |
4912 emit_arith(0x81, 0xF8, dst, imm32); | |
4913 } | |
4914 | |
4915 void Assembler::cmpq(Address dst, Register src) { | |
4916 InstructionMark im(this); | |
4917 prefixq(dst, src); | |
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d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4918 emit_int8(0x3B); |
304 | 4919 emit_operand(src, dst); |
4920 } | |
4921 | |
4922 void Assembler::cmpq(Register dst, Register src) { | |
4923 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
4924 emit_arith(0x3B, 0xC0, dst, src); | |
4925 } | |
4926 | |
4927 void Assembler::cmpq(Register dst, Address src) { | |
4928 InstructionMark im(this); | |
4929 prefixq(src, dst); | |
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diff
changeset
|
4930 emit_int8(0x3B); |
304 | 4931 emit_operand(dst, src); |
4932 } | |
4933 | |
4934 void Assembler::cmpxchgq(Register reg, Address adr) { | |
4935 InstructionMark im(this); | |
4936 prefixq(adr, reg); | |
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diff
changeset
|
4937 emit_int8(0x0F); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4938 emit_int8((unsigned char)0xB1); |
304 | 4939 emit_operand(reg, adr); |
4940 } | |
4941 | |
4942 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) { | |
4943 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
4759 | 4944 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2); |
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7427
diff
changeset
|
4945 emit_int8(0x2A); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
4946 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 4947 } |
4948 | |
4759 | 4949 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) { |
4950 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
4951 InstructionMark im(this); | |
4952 simd_prefix_q(dst, dst, src, VEX_SIMD_F2); | |
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diff
changeset
|
4953 emit_int8(0x2A); |
4759 | 4954 emit_operand(dst, src); |
4955 } | |
4956 | |
304 | 4957 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) { |
4958 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
4759 | 4959 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3); |
7430
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diff
changeset
|
4960 emit_int8(0x2A); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4961 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 4962 } |
4963 | |
4759 | 4964 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) { |
4965 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
4966 InstructionMark im(this); | |
4967 simd_prefix_q(dst, dst, src, VEX_SIMD_F3); | |
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diff
changeset
|
4968 emit_int8(0x2A); |
4759 | 4969 emit_operand(dst, src); |
4970 } | |
4971 | |
304 | 4972 void Assembler::cvttsd2siq(Register dst, XMMRegister src) { |
4973 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
4759 | 4974 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2); |
7430
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diff
changeset
|
4975 emit_int8(0x2C); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
4976 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 4977 } |
4978 | |
4979 void Assembler::cvttss2siq(Register dst, XMMRegister src) { | |
4980 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
4759 | 4981 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F3); |
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changeset
|
4982 emit_int8(0x2C); |
d02120b7a34f
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diff
changeset
|
4983 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 4984 } |
4985 | |
4986 void Assembler::decl(Register dst) { | |
4987 // Don't use it directly. Use MacroAssembler::decrementl() instead. | |
4988 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode) | |
4989 int encode = prefix_and_encode(dst->encoding()); | |
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changeset
|
4990 emit_int8((unsigned char)0xFF); |
d02120b7a34f
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diff
changeset
|
4991 emit_int8((unsigned char)(0xC8 | encode)); |
304 | 4992 } |
4993 | |
4994 void Assembler::decq(Register dst) { | |
4995 // Don't use it directly. Use MacroAssembler::decrementq() instead. | |
4996 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
4997 int encode = prefixq_and_encode(dst->encoding()); | |
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changeset
|
4998 emit_int8((unsigned char)0xFF); |
d02120b7a34f
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diff
changeset
|
4999 emit_int8(0xC8 | encode); |
304 | 5000 } |
5001 | |
5002 void Assembler::decq(Address dst) { | |
5003 // Don't use it directly. Use MacroAssembler::decrementq() instead. | |
5004 InstructionMark im(this); | |
5005 prefixq(dst); | |
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changeset
|
5006 emit_int8((unsigned char)0xFF); |
304 | 5007 emit_operand(rcx, dst); |
5008 } | |
5009 | |
5010 void Assembler::fxrstor(Address src) { | |
5011 prefixq(src); | |
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7427
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changeset
|
5012 emit_int8(0x0F); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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|
5013 emit_int8((unsigned char)0xAE); |
304 | 5014 emit_operand(as_Register(1), src); |
5015 } | |
5016 | |
5017 void Assembler::fxsave(Address dst) { | |
5018 prefixq(dst); | |
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changeset
|
5019 emit_int8(0x0F); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
5020 emit_int8((unsigned char)0xAE); |
304 | 5021 emit_operand(as_Register(0), dst); |
5022 } | |
5023 | |
5024 void Assembler::idivq(Register src) { | |
5025 int encode = prefixq_and_encode(src->encoding()); | |
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changeset
|
5026 emit_int8((unsigned char)0xF7); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
5027 emit_int8((unsigned char)(0xF8 | encode)); |
304 | 5028 } |
5029 | |
5030 void Assembler::imulq(Register dst, Register src) { | |
5031 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
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|
5032 emit_int8(0x0F); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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|
5033 emit_int8((unsigned char)0xAF); |
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changeset
|
5034 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 5035 } |
5036 | |
5037 void Assembler::imulq(Register dst, Register src, int value) { | |
5038 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
5039 if (is8bit(value)) { | |
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changeset
|
5040 emit_int8(0x6B); |
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
5041 emit_int8((unsigned char)(0xC0 | encode)); |
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changeset
|
5042 emit_int8(value & 0xFF); |
304 | 5043 } else { |
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changeset
|
5044 emit_int8(0x69); |
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changeset
|
5045 emit_int8((unsigned char)(0xC0 | encode)); |
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ffa87474d7a4
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changeset
|
5046 emit_int32(value); |
304 | 5047 } |
5048 } | |
5049 | |
12972
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changeset
|
5050 void Assembler::imulq(Register dst, Address src) { |
59e8ad757e19
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diff
changeset
|
5051 InstructionMark im(this); |
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diff
changeset
|
5052 prefixq(src, dst); |
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changeset
|
5053 emit_int8(0x0F); |
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changeset
|
5054 emit_int8((unsigned char) 0xAF); |
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diff
changeset
|
5055 emit_operand(dst, src); |
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|
5056 } |
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|
5057 |
304 | 5058 void Assembler::incl(Register dst) { |
5059 // Don't use it directly. Use MacroAssembler::incrementl() instead. | |
5060 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
5061 int encode = prefix_and_encode(dst->encoding()); | |
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|
5062 emit_int8((unsigned char)0xFF); |
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changeset
|
5063 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 5064 } |
5065 | |
5066 void Assembler::incq(Register dst) { | |
5067 // Don't use it directly. Use MacroAssembler::incrementq() instead. | |
5068 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
5069 int encode = prefixq_and_encode(dst->encoding()); | |
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changeset
|
5070 emit_int8((unsigned char)0xFF); |
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changeset
|
5071 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 5072 } |
5073 | |
5074 void Assembler::incq(Address dst) { | |
5075 // Don't use it directly. Use MacroAssembler::incrementq() instead. | |
5076 InstructionMark im(this); | |
5077 prefixq(dst); | |
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changeset
|
5078 emit_int8((unsigned char)0xFF); |
304 | 5079 emit_operand(rax, dst); |
5080 } | |
5081 | |
5082 void Assembler::lea(Register dst, Address src) { | |
5083 leaq(dst, src); | |
5084 } | |
5085 | |
5086 void Assembler::leaq(Register dst, Address src) { | |
5087 InstructionMark im(this); | |
5088 prefixq(src, dst); | |
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changeset
|
5089 emit_int8((unsigned char)0x8D); |
304 | 5090 emit_operand(dst, src); |
5091 } | |
5092 | |
5093 void Assembler::mov64(Register dst, int64_t imm64) { | |
5094 InstructionMark im(this); | |
5095 int encode = prefixq_and_encode(dst->encoding()); | |
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changeset
|
5096 emit_int8((unsigned char)(0xB8 | encode)); |
7198
6ab62ad83507
8003195: AbstractAssembler should not store code pointers but use the CodeSection directly
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6894
diff
changeset
|
5097 emit_int64(imm64); |
304 | 5098 } |
5099 | |
5100 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) { | |
5101 InstructionMark im(this); | |
5102 int encode = prefixq_and_encode(dst->encoding()); | |
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changeset
|
5103 emit_int8(0xB8 | encode); |
304 | 5104 emit_data64(imm64, rspec); |
5105 } | |
5106 | |
642
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|
5107 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) { |
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|
5108 InstructionMark im(this); |
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changeset
|
5109 int encode = prefix_and_encode(dst->encoding()); |
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changeset
|
5110 emit_int8((unsigned char)(0xB8 | encode)); |
642
660978a2a31a
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624
diff
changeset
|
5111 emit_data((int)imm32, rspec, narrow_oop_operand); |
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diff
changeset
|
5112 } |
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changeset
|
5113 |
660978a2a31a
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changeset
|
5114 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) { |
660978a2a31a
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changeset
|
5115 InstructionMark im(this); |
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changeset
|
5116 prefix(dst); |
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|
5117 emit_int8((unsigned char)0xC7); |
642
660978a2a31a
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changeset
|
5118 emit_operand(rax, dst, 4); |
660978a2a31a
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changeset
|
5119 emit_data((int)imm32, rspec, narrow_oop_operand); |
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diff
changeset
|
5120 } |
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diff
changeset
|
5121 |
660978a2a31a
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|
5122 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) { |
660978a2a31a
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|
5123 InstructionMark im(this); |
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changeset
|
5124 int encode = prefix_and_encode(src1->encoding()); |
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|
5125 emit_int8((unsigned char)0x81); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
5126 emit_int8((unsigned char)(0xF8 | encode)); |
642
660978a2a31a
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624
diff
changeset
|
5127 emit_data((int)imm32, rspec, narrow_oop_operand); |
660978a2a31a
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624
diff
changeset
|
5128 } |
660978a2a31a
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624
diff
changeset
|
5129 |
660978a2a31a
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diff
changeset
|
5130 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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diff
changeset
|
5131 InstructionMark im(this); |
660978a2a31a
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diff
changeset
|
5132 prefix(src1); |
7430
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|
5133 emit_int8((unsigned char)0x81); |
642
660978a2a31a
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624
diff
changeset
|
5134 emit_operand(rax, src1, 4); |
660978a2a31a
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diff
changeset
|
5135 emit_data((int)imm32, rspec, narrow_oop_operand); |
660978a2a31a
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diff
changeset
|
5136 } |
660978a2a31a
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624
diff
changeset
|
5137 |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
5138 void Assembler::lzcntq(Register dst, Register src) { |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
5139 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
twisti
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7427
diff
changeset
|
5140 emit_int8((unsigned char)0xF3); |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
5141 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
7430
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8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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parents:
7427
diff
changeset
|
5142 emit_int8(0x0F); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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parents:
7427
diff
changeset
|
5143 emit_int8((unsigned char)0xBD); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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7427
diff
changeset
|
5144 emit_int8((unsigned char)(0xC0 | encode)); |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
5145 } |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
5146 |
304 | 5147 void Assembler::movdq(XMMRegister dst, Register src) { |
5148 // table D-1 says MMX/SSE2 | |
4759 | 5149 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
5150 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_66); | |
7430
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changeset
|
5151 emit_int8(0x6E); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
5152 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 5153 } |
5154 | |
5155 void Assembler::movdq(Register dst, XMMRegister src) { | |
5156 // table D-1 says MMX/SSE2 | |
4759 | 5157 NOT_LP64(assert(VM_Version::supports_sse2(), "")); |
304 | 5158 // swap src/dst to get correct prefix |
4759 | 5159 int encode = simd_prefix_and_encode_q(src, dst, VEX_SIMD_66); |
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changeset
|
5160 emit_int8(0x7E); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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changeset
|
5161 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 5162 } |
5163 | |
5164 void Assembler::movq(Register dst, Register src) { | |
5165 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
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changeset
|
5166 emit_int8((unsigned char)0x8B); |
d02120b7a34f
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diff
changeset
|
5167 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 5168 } |
5169 | |
5170 void Assembler::movq(Register dst, Address src) { | |
5171 InstructionMark im(this); | |
5172 prefixq(src, dst); | |
7430
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changeset
|
5173 emit_int8((unsigned char)0x8B); |
304 | 5174 emit_operand(dst, src); |
5175 } | |
5176 | |
5177 void Assembler::movq(Address dst, Register src) { | |
5178 InstructionMark im(this); | |
5179 prefixq(dst, src); | |
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changeset
|
5180 emit_int8((unsigned char)0x89); |
304 | 5181 emit_operand(src, dst); |
5182 } | |
5183 | |
624 | 5184 void Assembler::movsbq(Register dst, Address src) { |
5185 InstructionMark im(this); | |
5186 prefixq(src, dst); | |
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changeset
|
5187 emit_int8(0x0F); |
d02120b7a34f
8004250: replace AbstractAssembler a_byte/a_long with emit_int8/emit_int32
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diff
changeset
|
5188 emit_int8((unsigned char)0xBE); |
624 | 5189 emit_operand(dst, src); |
5190 } | |
5191 | |
5192 void Assembler::movsbq(Register dst, Register src) { | |
5193 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
7430
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changeset
|
5194 emit_int8(0x0F); |
d02120b7a34f
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changeset
|
5195 emit_int8((unsigned char)0xBE); |
d02120b7a34f
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changeset
|
5196 emit_int8((unsigned char)(0xC0 | encode)); |
624 | 5197 } |
5198 | |
304 | 5199 void Assembler::movslq(Register dst, int32_t imm32) { |
5200 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx) | |
5201 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx) | |
5202 // as a result we shouldn't use until tested at runtime... | |
5203 ShouldNotReachHere(); | |
5204 InstructionMark im(this); | |
5205 int encode = prefixq_and_encode(dst->encoding()); | |
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changeset
|
5206 emit_int8((unsigned char)(0xC7 | encode)); |
7476
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8004537: replace AbstractAssembler emit_long with emit_int32
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7475
diff
changeset
|
5207 emit_int32(imm32); |
304 | 5208 } |
5209 | |
5210 void Assembler::movslq(Address dst, int32_t imm32) { | |
5211 assert(is_simm32(imm32), "lost bits"); | |
5212 InstructionMark im(this); | |
5213 prefixq(dst); | |
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changeset
|
5214 emit_int8((unsigned char)0xC7); |
304 | 5215 emit_operand(rax, dst, 4); |
7476
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8004537: replace AbstractAssembler emit_long with emit_int32
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diff
changeset
|
5216 emit_int32(imm32); |
304 | 5217 } |
5218 | |
5219 void Assembler::movslq(Register dst, Address src) { | |
5220 InstructionMark im(this); | |
5221 prefixq(src, dst); | |
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5222 emit_int8(0x63); |
304 | 5223 emit_operand(dst, src); |
5224 } | |
5225 | |
5226 void Assembler::movslq(Register dst, Register src) { | |
5227 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
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|
5228 emit_int8(0x63); |
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|
5229 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 5230 } |
5231 | |
624 | 5232 void Assembler::movswq(Register dst, Address src) { |
5233 InstructionMark im(this); | |
5234 prefixq(src, dst); | |
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|
5235 emit_int8(0x0F); |
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|
5236 emit_int8((unsigned char)0xBF); |
624 | 5237 emit_operand(dst, src); |
5238 } | |
5239 | |
5240 void Assembler::movswq(Register dst, Register src) { | |
5241 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
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5242 emit_int8((unsigned char)0x0F); |
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|
5243 emit_int8((unsigned char)0xBF); |
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5244 emit_int8((unsigned char)(0xC0 | encode)); |
624 | 5245 } |
5246 | |
5247 void Assembler::movzbq(Register dst, Address src) { | |
5248 InstructionMark im(this); | |
5249 prefixq(src, dst); | |
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|
5250 emit_int8((unsigned char)0x0F); |
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|
5251 emit_int8((unsigned char)0xB6); |
624 | 5252 emit_operand(dst, src); |
5253 } | |
5254 | |
5255 void Assembler::movzbq(Register dst, Register src) { | |
5256 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
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|
5257 emit_int8(0x0F); |
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|
5258 emit_int8((unsigned char)0xB6); |
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|
5259 emit_int8(0xC0 | encode); |
624 | 5260 } |
5261 | |
5262 void Assembler::movzwq(Register dst, Address src) { | |
5263 InstructionMark im(this); | |
5264 prefixq(src, dst); | |
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|
5265 emit_int8((unsigned char)0x0F); |
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|
5266 emit_int8((unsigned char)0xB7); |
624 | 5267 emit_operand(dst, src); |
5268 } | |
5269 | |
5270 void Assembler::movzwq(Register dst, Register src) { | |
5271 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
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|
5272 emit_int8((unsigned char)0x0F); |
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|
5273 emit_int8((unsigned char)0xB7); |
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|
5274 emit_int8((unsigned char)(0xC0 | encode)); |
624 | 5275 } |
5276 | |
304 | 5277 void Assembler::negq(Register dst) { |
5278 int encode = prefixq_and_encode(dst->encoding()); | |
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|
5279 emit_int8((unsigned char)0xF7); |
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|
5280 emit_int8((unsigned char)(0xD8 | encode)); |
304 | 5281 } |
5282 | |
5283 void Assembler::notq(Register dst) { | |
5284 int encode = prefixq_and_encode(dst->encoding()); | |
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|
5285 emit_int8((unsigned char)0xF7); |
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|
5286 emit_int8((unsigned char)(0xD0 | encode)); |
304 | 5287 } |
5288 | |
5289 void Assembler::orq(Address dst, int32_t imm32) { | |
5290 InstructionMark im(this); | |
5291 prefixq(dst); | |
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|
5292 emit_int8((unsigned char)0x81); |
304 | 5293 emit_operand(rcx, dst, 4); |
7476
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8004537: replace AbstractAssembler emit_long with emit_int32
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7475
diff
changeset
|
5294 emit_int32(imm32); |
304 | 5295 } |
5296 | |
5297 void Assembler::orq(Register dst, int32_t imm32) { | |
5298 (void) prefixq_and_encode(dst->encoding()); | |
5299 emit_arith(0x81, 0xC8, dst, imm32); | |
5300 } | |
5301 | |
5302 void Assembler::orq(Register dst, Address src) { | |
5303 InstructionMark im(this); | |
5304 prefixq(src, dst); | |
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|
5305 emit_int8(0x0B); |
304 | 5306 emit_operand(dst, src); |
5307 } | |
5308 | |
5309 void Assembler::orq(Register dst, Register src) { | |
5310 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
5311 emit_arith(0x0B, 0xC0, dst, src); | |
5312 } | |
5313 | |
5314 void Assembler::popa() { // 64bit | |
5315 movq(r15, Address(rsp, 0)); | |
5316 movq(r14, Address(rsp, wordSize)); | |
5317 movq(r13, Address(rsp, 2 * wordSize)); | |
5318 movq(r12, Address(rsp, 3 * wordSize)); | |
5319 movq(r11, Address(rsp, 4 * wordSize)); | |
5320 movq(r10, Address(rsp, 5 * wordSize)); | |
5321 movq(r9, Address(rsp, 6 * wordSize)); | |
5322 movq(r8, Address(rsp, 7 * wordSize)); | |
5323 movq(rdi, Address(rsp, 8 * wordSize)); | |
5324 movq(rsi, Address(rsp, 9 * wordSize)); | |
5325 movq(rbp, Address(rsp, 10 * wordSize)); | |
5326 // skip rsp | |
5327 movq(rbx, Address(rsp, 12 * wordSize)); | |
5328 movq(rdx, Address(rsp, 13 * wordSize)); | |
5329 movq(rcx, Address(rsp, 14 * wordSize)); | |
5330 movq(rax, Address(rsp, 15 * wordSize)); | |
5331 | |
5332 addq(rsp, 16 * wordSize); | |
5333 } | |
5334 | |
643
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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5335 void Assembler::popcntq(Register dst, Address src) { |
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|
5336 assert(VM_Version::supports_popcnt(), "must support"); |
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|
5337 InstructionMark im(this); |
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|
5338 emit_int8((unsigned char)0xF3); |
643
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|
5339 prefixq(src, dst); |
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|
5340 emit_int8((unsigned char)0x0F); |
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|
5341 emit_int8((unsigned char)0xB8); |
643
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changeset
|
5342 emit_operand(dst, src); |
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|
5343 } |
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|
5344 |
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|
5345 void Assembler::popcntq(Register dst, Register src) { |
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changeset
|
5346 assert(VM_Version::supports_popcnt(), "must support"); |
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|
5347 emit_int8((unsigned char)0xF3); |
643
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|
5348 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
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|
5349 emit_int8((unsigned char)0x0F); |
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|
5350 emit_int8((unsigned char)0xB8); |
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|
5351 emit_int8((unsigned char)(0xC0 | encode)); |
643
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|
5352 } |
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diff
changeset
|
5353 |
304 | 5354 void Assembler::popq(Address dst) { |
5355 InstructionMark im(this); | |
5356 prefixq(dst); | |
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changeset
|
5357 emit_int8((unsigned char)0x8F); |
304 | 5358 emit_operand(rax, dst); |
5359 } | |
5360 | |
5361 void Assembler::pusha() { // 64bit | |
5362 // we have to store original rsp. ABI says that 128 bytes | |
5363 // below rsp are local scratch. | |
5364 movq(Address(rsp, -5 * wordSize), rsp); | |
5365 | |
5366 subq(rsp, 16 * wordSize); | |
5367 | |
5368 movq(Address(rsp, 15 * wordSize), rax); | |
5369 movq(Address(rsp, 14 * wordSize), rcx); | |
5370 movq(Address(rsp, 13 * wordSize), rdx); | |
5371 movq(Address(rsp, 12 * wordSize), rbx); | |
5372 // skip rsp | |
5373 movq(Address(rsp, 10 * wordSize), rbp); | |
5374 movq(Address(rsp, 9 * wordSize), rsi); | |
5375 movq(Address(rsp, 8 * wordSize), rdi); | |
5376 movq(Address(rsp, 7 * wordSize), r8); | |
5377 movq(Address(rsp, 6 * wordSize), r9); | |
5378 movq(Address(rsp, 5 * wordSize), r10); | |
5379 movq(Address(rsp, 4 * wordSize), r11); | |
5380 movq(Address(rsp, 3 * wordSize), r12); | |
5381 movq(Address(rsp, 2 * wordSize), r13); | |
5382 movq(Address(rsp, wordSize), r14); | |
5383 movq(Address(rsp, 0), r15); | |
5384 } | |
5385 | |
5386 void Assembler::pushq(Address src) { | |
5387 InstructionMark im(this); | |
5388 prefixq(src); | |
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|
5389 emit_int8((unsigned char)0xFF); |
304 | 5390 emit_operand(rsi, src); |
5391 } | |
5392 | |
5393 void Assembler::rclq(Register dst, int imm8) { | |
5394 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
5395 int encode = prefixq_and_encode(dst->encoding()); | |
5396 if (imm8 == 1) { | |
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|
5397 emit_int8((unsigned char)0xD1); |
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|
5398 emit_int8((unsigned char)(0xD0 | encode)); |
304 | 5399 } else { |
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|
5400 emit_int8((unsigned char)0xC1); |
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|
5401 emit_int8((unsigned char)(0xD0 | encode)); |
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changeset
|
5402 emit_int8(imm8); |
304 | 5403 } |
5404 } | |
5405 void Assembler::sarq(Register dst, int imm8) { | |
5406 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
5407 int encode = prefixq_and_encode(dst->encoding()); | |
5408 if (imm8 == 1) { | |
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|
5409 emit_int8((unsigned char)0xD1); |
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|
5410 emit_int8((unsigned char)(0xF8 | encode)); |
304 | 5411 } else { |
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|
5412 emit_int8((unsigned char)0xC1); |
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|
5413 emit_int8((unsigned char)(0xF8 | encode)); |
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|
5414 emit_int8(imm8); |
304 | 5415 } |
5416 } | |
5417 | |
5418 void Assembler::sarq(Register dst) { | |
5419 int encode = prefixq_and_encode(dst->encoding()); | |
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|
5420 emit_int8((unsigned char)0xD3); |
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|
5421 emit_int8((unsigned char)(0xF8 | encode)); |
304 | 5422 } |
2100
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|
5423 |
304 | 5424 void Assembler::sbbq(Address dst, int32_t imm32) { |
5425 InstructionMark im(this); | |
5426 prefixq(dst); | |
5427 emit_arith_operand(0x81, rbx, dst, imm32); | |
5428 } | |
5429 | |
5430 void Assembler::sbbq(Register dst, int32_t imm32) { | |
5431 (void) prefixq_and_encode(dst->encoding()); | |
5432 emit_arith(0x81, 0xD8, dst, imm32); | |
5433 } | |
5434 | |
5435 void Assembler::sbbq(Register dst, Address src) { | |
5436 InstructionMark im(this); | |
5437 prefixq(src, dst); | |
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|
5438 emit_int8(0x1B); |
304 | 5439 emit_operand(dst, src); |
5440 } | |
5441 | |
5442 void Assembler::sbbq(Register dst, Register src) { | |
5443 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
5444 emit_arith(0x1B, 0xC0, dst, src); | |
5445 } | |
5446 | |
5447 void Assembler::shlq(Register dst, int imm8) { | |
5448 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
5449 int encode = prefixq_and_encode(dst->encoding()); | |
5450 if (imm8 == 1) { | |
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|
5451 emit_int8((unsigned char)0xD1); |
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|
5452 emit_int8((unsigned char)(0xE0 | encode)); |
304 | 5453 } else { |
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|
5454 emit_int8((unsigned char)0xC1); |
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changeset
|
5455 emit_int8((unsigned char)(0xE0 | encode)); |
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|
5456 emit_int8(imm8); |
304 | 5457 } |
5458 } | |
5459 | |
5460 void Assembler::shlq(Register dst) { | |
5461 int encode = prefixq_and_encode(dst->encoding()); | |
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|
5462 emit_int8((unsigned char)0xD3); |
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|
5463 emit_int8((unsigned char)(0xE0 | encode)); |
304 | 5464 } |
5465 | |
5466 void Assembler::shrq(Register dst, int imm8) { | |
5467 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
5468 int encode = prefixq_and_encode(dst->encoding()); | |
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|
5469 emit_int8((unsigned char)0xC1); |
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|
5470 emit_int8((unsigned char)(0xE8 | encode)); |
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|
5471 emit_int8(imm8); |
304 | 5472 } |
5473 | |
5474 void Assembler::shrq(Register dst) { | |
5475 int encode = prefixq_and_encode(dst->encoding()); | |
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5476 emit_int8((unsigned char)0xD3); |
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5477 emit_int8(0xE8 | encode); |
304 | 5478 } |
5479 | |
5480 void Assembler::subq(Address dst, int32_t imm32) { | |
5481 InstructionMark im(this); | |
5482 prefixq(dst); | |
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5483 emit_arith_operand(0x81, rbp, dst, imm32); |
304 | 5484 } |
5485 | |
5486 void Assembler::subq(Address dst, Register src) { | |
5487 InstructionMark im(this); | |
5488 prefixq(dst, src); | |
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5489 emit_int8(0x29); |
304 | 5490 emit_operand(src, dst); |
5491 } | |
5492 | |
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5493 void Assembler::subq(Register dst, int32_t imm32) { |
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5494 (void) prefixq_and_encode(dst->encoding()); |
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5495 emit_arith(0x81, 0xE8, dst, imm32); |
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5496 } |
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5497 |
4947
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5498 // Force generation of a 4 byte immediate value even if it fits into 8bit |
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5499 void Assembler::subq_imm32(Register dst, int32_t imm32) { |
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5500 (void) prefixq_and_encode(dst->encoding()); |
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5501 emit_arith_imm32(0x81, 0xE8, dst, imm32); |
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5502 } |
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5503 |
304 | 5504 void Assembler::subq(Register dst, Address src) { |
5505 InstructionMark im(this); | |
5506 prefixq(src, dst); | |
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5507 emit_int8(0x2B); |
304 | 5508 emit_operand(dst, src); |
5509 } | |
5510 | |
5511 void Assembler::subq(Register dst, Register src) { | |
5512 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
5513 emit_arith(0x2B, 0xC0, dst, src); | |
5514 } | |
5515 | |
5516 void Assembler::testq(Register dst, int32_t imm32) { | |
5517 // not using emit_arith because test | |
5518 // doesn't support sign-extension of | |
5519 // 8bit operands | |
5520 int encode = dst->encoding(); | |
5521 if (encode == 0) { | |
5522 prefix(REX_W); | |
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5523 emit_int8((unsigned char)0xA9); |
304 | 5524 } else { |
5525 encode = prefixq_and_encode(encode); | |
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5526 emit_int8((unsigned char)0xF7); |
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5527 emit_int8((unsigned char)(0xC0 | encode)); |
304 | 5528 } |
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5529 emit_int32(imm32); |
304 | 5530 } |
5531 | |
5532 void Assembler::testq(Register dst, Register src) { | |
5533 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
5534 emit_arith(0x85, 0xC0, dst, src); | |
5535 } | |
5536 | |
5537 void Assembler::xaddq(Address dst, Register src) { | |
5538 InstructionMark im(this); | |
5539 prefixq(dst, src); | |
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5540 emit_int8(0x0F); |
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5541 emit_int8((unsigned char)0xC1); |
304 | 5542 emit_operand(src, dst); |
5543 } | |
5544 | |
5545 void Assembler::xchgq(Register dst, Address src) { | |
5546 InstructionMark im(this); | |
5547 prefixq(src, dst); | |
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5548 emit_int8((unsigned char)0x87); |
304 | 5549 emit_operand(dst, src); |
5550 } | |
5551 | |
5552 void Assembler::xchgq(Register dst, Register src) { | |
5553 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
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5554 emit_int8((unsigned char)0x87); |
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5555 emit_int8((unsigned char)(0xc0 | encode)); |
304 | 5556 } |
5557 | |
5558 void Assembler::xorq(Register dst, Register src) { | |
5559 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
5560 emit_arith(0x33, 0xC0, dst, src); | |
5561 } | |
5562 | |
5563 void Assembler::xorq(Register dst, Address src) { | |
5564 InstructionMark im(this); | |
5565 prefixq(src, dst); | |
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5566 emit_int8(0x33); |
304 | 5567 emit_operand(dst, src); |
5568 } | |
5569 | |
5570 #endif // !LP64 |