Mercurial > hg > graal-compiler
annotate src/cpu/x86/vm/assembler_x86.cpp @ 2262:6bbaedb03534
7016474: string compare intrinsic improvements
Reviewed-by: kvn
| author | never |
|---|---|
| date | Wed, 09 Feb 2011 15:02:23 -0800 |
| parents | 28bf941f445e |
| children | 2ab52cda08e5 41d4973cf100 |
| rev | line source |
|---|---|
| 0 | 1 /* |
|
2100
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
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2014
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changeset
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2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
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1552
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
|
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
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20 * or visit www.oracle.com if you need additional information or have any |
|
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6941466: Oracle rebranding changes for Hotspot repositories
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21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #include "precompiled.hpp" |
| 26 #include "assembler_x86.inline.hpp" | |
| 27 #include "gc_interface/collectedHeap.inline.hpp" | |
| 28 #include "interpreter/interpreter.hpp" | |
| 29 #include "memory/cardTableModRefBS.hpp" | |
| 30 #include "memory/resourceArea.hpp" | |
| 31 #include "prims/methodHandles.hpp" | |
| 32 #include "runtime/biasedLocking.hpp" | |
| 33 #include "runtime/interfaceSupport.hpp" | |
| 34 #include "runtime/objectMonitor.hpp" | |
| 35 #include "runtime/os.hpp" | |
| 36 #include "runtime/sharedRuntime.hpp" | |
| 37 #include "runtime/stubRoutines.hpp" | |
| 38 #ifndef SERIALGC | |
| 39 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp" | |
| 40 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp" | |
| 41 #include "gc_implementation/g1/heapRegion.hpp" | |
| 42 #endif | |
| 0 | 43 |
| 44 // Implementation of AddressLiteral | |
| 45 | |
| 46 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) { | |
| 47 _is_lval = false; | |
| 48 _target = target; | |
| 49 switch (rtype) { | |
| 50 case relocInfo::oop_type: | |
| 51 // Oops are a special case. Normally they would be their own section | |
| 52 // but in cases like icBuffer they are literals in the code stream that | |
| 53 // we don't have a section for. We use none so that we get a literal address | |
| 54 // which is always patchable. | |
| 55 break; | |
| 56 case relocInfo::external_word_type: | |
| 57 _rspec = external_word_Relocation::spec(target); | |
| 58 break; | |
| 59 case relocInfo::internal_word_type: | |
| 60 _rspec = internal_word_Relocation::spec(target); | |
| 61 break; | |
| 62 case relocInfo::opt_virtual_call_type: | |
| 63 _rspec = opt_virtual_call_Relocation::spec(); | |
| 64 break; | |
| 65 case relocInfo::static_call_type: | |
| 66 _rspec = static_call_Relocation::spec(); | |
| 67 break; | |
| 68 case relocInfo::runtime_call_type: | |
| 69 _rspec = runtime_call_Relocation::spec(); | |
| 70 break; | |
| 71 case relocInfo::poll_type: | |
| 72 case relocInfo::poll_return_type: | |
| 73 _rspec = Relocation::spec_simple(rtype); | |
| 74 break; | |
| 75 case relocInfo::none: | |
| 76 break; | |
| 77 default: | |
| 78 ShouldNotReachHere(); | |
| 79 break; | |
| 80 } | |
| 81 } | |
| 82 | |
| 83 // Implementation of Address | |
| 84 | |
| 304 | 85 #ifdef _LP64 |
| 86 | |
| 0 | 87 Address Address::make_array(ArrayAddress adr) { |
| 88 // Not implementable on 64bit machines | |
| 89 // Should have been handled higher up the call chain. | |
| 90 ShouldNotReachHere(); | |
| 304 | 91 return Address(); |
| 92 } | |
| 93 | |
| 94 // exceedingly dangerous constructor | |
| 95 Address::Address(int disp, address loc, relocInfo::relocType rtype) { | |
| 96 _base = noreg; | |
| 97 _index = noreg; | |
| 98 _scale = no_scale; | |
| 99 _disp = disp; | |
| 100 switch (rtype) { | |
| 101 case relocInfo::external_word_type: | |
| 102 _rspec = external_word_Relocation::spec(loc); | |
| 103 break; | |
| 104 case relocInfo::internal_word_type: | |
| 105 _rspec = internal_word_Relocation::spec(loc); | |
| 106 break; | |
| 107 case relocInfo::runtime_call_type: | |
| 108 // HMM | |
| 109 _rspec = runtime_call_Relocation::spec(); | |
| 110 break; | |
| 111 case relocInfo::poll_type: | |
| 112 case relocInfo::poll_return_type: | |
| 113 _rspec = Relocation::spec_simple(rtype); | |
| 114 break; | |
| 115 case relocInfo::none: | |
| 116 break; | |
| 117 default: | |
| 118 ShouldNotReachHere(); | |
| 119 } | |
| 120 } | |
| 121 #else // LP64 | |
| 122 | |
| 123 Address Address::make_array(ArrayAddress adr) { | |
| 0 | 124 AddressLiteral base = adr.base(); |
| 125 Address index = adr.index(); | |
| 126 assert(index._disp == 0, "must not have disp"); // maybe it can? | |
| 127 Address array(index._base, index._index, index._scale, (intptr_t) base.target()); | |
| 128 array._rspec = base._rspec; | |
| 129 return array; | |
| 304 | 130 } |
| 0 | 131 |
| 132 // exceedingly dangerous constructor | |
| 133 Address::Address(address loc, RelocationHolder spec) { | |
| 134 _base = noreg; | |
| 135 _index = noreg; | |
| 136 _scale = no_scale; | |
| 137 _disp = (intptr_t) loc; | |
| 138 _rspec = spec; | |
| 139 } | |
| 304 | 140 |
| 0 | 141 #endif // _LP64 |
| 142 | |
| 304 | 143 |
| 144 | |
| 0 | 145 // Convert the raw encoding form into the form expected by the constructor for |
| 146 // Address. An index of 4 (rsp) corresponds to having no index, so convert | |
| 147 // that to noreg for the Address constructor. | |
| 624 | 148 Address Address::make_raw(int base, int index, int scale, int disp, bool disp_is_oop) { |
| 149 RelocationHolder rspec; | |
| 150 if (disp_is_oop) { | |
| 151 rspec = Relocation::spec_simple(relocInfo::oop_type); | |
| 152 } | |
| 0 | 153 bool valid_index = index != rsp->encoding(); |
| 154 if (valid_index) { | |
| 155 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp)); | |
| 624 | 156 madr._rspec = rspec; |
| 0 | 157 return madr; |
| 158 } else { | |
| 159 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp)); | |
| 624 | 160 madr._rspec = rspec; |
| 0 | 161 return madr; |
| 162 } | |
| 163 } | |
| 164 | |
| 165 // Implementation of Assembler | |
| 166 | |
| 167 int AbstractAssembler::code_fill_byte() { | |
| 168 return (u_char)'\xF4'; // hlt | |
| 169 } | |
| 170 | |
| 171 // make this go away someday | |
| 172 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) { | |
| 173 if (rtype == relocInfo::none) | |
| 174 emit_long(data); | |
| 175 else emit_data(data, Relocation::spec_simple(rtype), format); | |
| 176 } | |
| 177 | |
| 178 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) { | |
| 304 | 179 assert(imm_operand == 0, "default format must be immediate in this file"); |
| 0 | 180 assert(inst_mark() != NULL, "must be inside InstructionMark"); |
| 181 if (rspec.type() != relocInfo::none) { | |
| 182 #ifdef ASSERT | |
| 183 check_relocation(rspec, format); | |
| 184 #endif | |
| 185 // Do not use AbstractAssembler::relocate, which is not intended for | |
| 186 // embedded words. Instead, relocate to the enclosing instruction. | |
| 187 | |
| 188 // hack. call32 is too wide for mask so use disp32 | |
| 189 if (format == call32_operand) | |
| 190 code_section()->relocate(inst_mark(), rspec, disp32_operand); | |
| 191 else | |
| 192 code_section()->relocate(inst_mark(), rspec, format); | |
| 193 } | |
| 194 emit_long(data); | |
| 195 } | |
| 196 | |
| 304 | 197 static int encode(Register r) { |
| 198 int enc = r->encoding(); | |
| 199 if (enc >= 8) { | |
| 200 enc -= 8; | |
| 201 } | |
| 202 return enc; | |
| 203 } | |
| 204 | |
| 205 static int encode(XMMRegister r) { | |
| 206 int enc = r->encoding(); | |
| 207 if (enc >= 8) { | |
| 208 enc -= 8; | |
| 209 } | |
| 210 return enc; | |
| 211 } | |
| 0 | 212 |
| 213 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) { | |
| 214 assert(dst->has_byte_register(), "must have byte register"); | |
| 215 assert(isByte(op1) && isByte(op2), "wrong opcode"); | |
| 216 assert(isByte(imm8), "not a byte"); | |
| 217 assert((op1 & 0x01) == 0, "should be 8bit operation"); | |
| 218 emit_byte(op1); | |
| 304 | 219 emit_byte(op2 | encode(dst)); |
| 0 | 220 emit_byte(imm8); |
| 221 } | |
| 222 | |
| 223 | |
| 304 | 224 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) { |
| 0 | 225 assert(isByte(op1) && isByte(op2), "wrong opcode"); |
| 226 assert((op1 & 0x01) == 1, "should be 32bit operation"); | |
| 227 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
| 228 if (is8bit(imm32)) { | |
| 229 emit_byte(op1 | 0x02); // set sign bit | |
| 304 | 230 emit_byte(op2 | encode(dst)); |
| 0 | 231 emit_byte(imm32 & 0xFF); |
| 232 } else { | |
| 233 emit_byte(op1); | |
| 304 | 234 emit_byte(op2 | encode(dst)); |
| 0 | 235 emit_long(imm32); |
| 236 } | |
| 237 } | |
| 238 | |
| 239 // immediate-to-memory forms | |
| 304 | 240 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) { |
| 0 | 241 assert((op1 & 0x01) == 1, "should be 32bit operation"); |
| 242 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
| 243 if (is8bit(imm32)) { | |
| 244 emit_byte(op1 | 0x02); // set sign bit | |
| 304 | 245 emit_operand(rm, adr, 1); |
| 0 | 246 emit_byte(imm32 & 0xFF); |
| 247 } else { | |
| 248 emit_byte(op1); | |
| 304 | 249 emit_operand(rm, adr, 4); |
| 0 | 250 emit_long(imm32); |
| 251 } | |
| 252 } | |
| 253 | |
| 254 void Assembler::emit_arith(int op1, int op2, Register dst, jobject obj) { | |
| 304 | 255 LP64_ONLY(ShouldNotReachHere()); |
| 0 | 256 assert(isByte(op1) && isByte(op2), "wrong opcode"); |
| 257 assert((op1 & 0x01) == 1, "should be 32bit operation"); | |
| 258 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
| 259 InstructionMark im(this); | |
| 260 emit_byte(op1); | |
| 304 | 261 emit_byte(op2 | encode(dst)); |
| 262 emit_data((intptr_t)obj, relocInfo::oop_type, 0); | |
| 0 | 263 } |
| 264 | |
| 265 | |
| 266 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) { | |
| 267 assert(isByte(op1) && isByte(op2), "wrong opcode"); | |
| 268 emit_byte(op1); | |
| 304 | 269 emit_byte(op2 | encode(dst) << 3 | encode(src)); |
| 270 } | |
| 271 | |
| 272 | |
| 273 void Assembler::emit_operand(Register reg, Register base, Register index, | |
| 274 Address::ScaleFactor scale, int disp, | |
| 275 RelocationHolder const& rspec, | |
| 276 int rip_relative_correction) { | |
| 0 | 277 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type(); |
| 304 | 278 |
| 279 // Encode the registers as needed in the fields they are used in | |
| 280 | |
| 281 int regenc = encode(reg) << 3; | |
| 282 int indexenc = index->is_valid() ? encode(index) << 3 : 0; | |
| 283 int baseenc = base->is_valid() ? encode(base) : 0; | |
| 284 | |
| 0 | 285 if (base->is_valid()) { |
| 286 if (index->is_valid()) { | |
| 287 assert(scale != Address::no_scale, "inconsistent address"); | |
| 288 // [base + index*scale + disp] | |
| 304 | 289 if (disp == 0 && rtype == relocInfo::none && |
| 290 base != rbp LP64_ONLY(&& base != r13)) { | |
| 0 | 291 // [base + index*scale] |
| 292 // [00 reg 100][ss index base] | |
| 293 assert(index != rsp, "illegal addressing mode"); | |
| 304 | 294 emit_byte(0x04 | regenc); |
| 295 emit_byte(scale << 6 | indexenc | baseenc); | |
| 0 | 296 } else if (is8bit(disp) && rtype == relocInfo::none) { |
| 297 // [base + index*scale + imm8] | |
| 298 // [01 reg 100][ss index base] imm8 | |
| 299 assert(index != rsp, "illegal addressing mode"); | |
| 304 | 300 emit_byte(0x44 | regenc); |
| 301 emit_byte(scale << 6 | indexenc | baseenc); | |
| 0 | 302 emit_byte(disp & 0xFF); |
| 303 } else { | |
| 304 | 304 // [base + index*scale + disp32] |
| 305 // [10 reg 100][ss index base] disp32 | |
| 0 | 306 assert(index != rsp, "illegal addressing mode"); |
| 304 | 307 emit_byte(0x84 | regenc); |
| 308 emit_byte(scale << 6 | indexenc | baseenc); | |
| 0 | 309 emit_data(disp, rspec, disp32_operand); |
| 310 } | |
| 304 | 311 } else if (base == rsp LP64_ONLY(|| base == r12)) { |
| 312 // [rsp + disp] | |
| 0 | 313 if (disp == 0 && rtype == relocInfo::none) { |
| 304 | 314 // [rsp] |
| 0 | 315 // [00 reg 100][00 100 100] |
| 304 | 316 emit_byte(0x04 | regenc); |
| 0 | 317 emit_byte(0x24); |
| 318 } else if (is8bit(disp) && rtype == relocInfo::none) { | |
| 304 | 319 // [rsp + imm8] |
| 320 // [01 reg 100][00 100 100] disp8 | |
| 321 emit_byte(0x44 | regenc); | |
| 0 | 322 emit_byte(0x24); |
| 323 emit_byte(disp & 0xFF); | |
| 324 } else { | |
| 304 | 325 // [rsp + imm32] |
| 326 // [10 reg 100][00 100 100] disp32 | |
| 327 emit_byte(0x84 | regenc); | |
| 0 | 328 emit_byte(0x24); |
| 329 emit_data(disp, rspec, disp32_operand); | |
| 330 } | |
| 331 } else { | |
| 332 // [base + disp] | |
| 304 | 333 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode"); |
| 334 if (disp == 0 && rtype == relocInfo::none && | |
| 335 base != rbp LP64_ONLY(&& base != r13)) { | |
| 0 | 336 // [base] |
| 337 // [00 reg base] | |
| 304 | 338 emit_byte(0x00 | regenc | baseenc); |
| 0 | 339 } else if (is8bit(disp) && rtype == relocInfo::none) { |
| 304 | 340 // [base + disp8] |
| 341 // [01 reg base] disp8 | |
| 342 emit_byte(0x40 | regenc | baseenc); | |
| 0 | 343 emit_byte(disp & 0xFF); |
| 344 } else { | |
| 304 | 345 // [base + disp32] |
| 346 // [10 reg base] disp32 | |
| 347 emit_byte(0x80 | regenc | baseenc); | |
| 0 | 348 emit_data(disp, rspec, disp32_operand); |
| 349 } | |
| 350 } | |
| 351 } else { | |
| 352 if (index->is_valid()) { | |
| 353 assert(scale != Address::no_scale, "inconsistent address"); | |
| 354 // [index*scale + disp] | |
| 304 | 355 // [00 reg 100][ss index 101] disp32 |
| 0 | 356 assert(index != rsp, "illegal addressing mode"); |
| 304 | 357 emit_byte(0x04 | regenc); |
| 358 emit_byte(scale << 6 | indexenc | 0x05); | |
| 0 | 359 emit_data(disp, rspec, disp32_operand); |
| 304 | 360 } else if (rtype != relocInfo::none ) { |
| 361 // [disp] (64bit) RIP-RELATIVE (32bit) abs | |
| 362 // [00 000 101] disp32 | |
| 363 | |
| 364 emit_byte(0x05 | regenc); | |
| 365 // Note that the RIP-rel. correction applies to the generated | |
| 366 // disp field, but _not_ to the target address in the rspec. | |
| 367 | |
| 368 // disp was created by converting the target address minus the pc | |
| 369 // at the start of the instruction. That needs more correction here. | |
| 370 // intptr_t disp = target - next_ip; | |
| 371 assert(inst_mark() != NULL, "must be inside InstructionMark"); | |
| 372 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction; | |
| 373 int64_t adjusted = disp; | |
| 374 // Do rip-rel adjustment for 64bit | |
| 375 LP64_ONLY(adjusted -= (next_ip - inst_mark())); | |
| 376 assert(is_simm32(adjusted), | |
| 377 "must be 32bit offset (RIP relative address)"); | |
| 378 emit_data((int32_t) adjusted, rspec, disp32_operand); | |
| 379 | |
| 0 | 380 } else { |
| 304 | 381 // 32bit never did this, did everything as the rip-rel/disp code above |
| 382 // [disp] ABSOLUTE | |
| 383 // [00 reg 100][00 100 101] disp32 | |
| 384 emit_byte(0x04 | regenc); | |
| 385 emit_byte(0x25); | |
| 0 | 386 emit_data(disp, rspec, disp32_operand); |
| 387 } | |
| 388 } | |
| 389 } | |
| 390 | |
| 304 | 391 void Assembler::emit_operand(XMMRegister reg, Register base, Register index, |
| 392 Address::ScaleFactor scale, int disp, | |
| 393 RelocationHolder const& rspec) { | |
| 394 emit_operand((Register)reg, base, index, scale, disp, rspec); | |
| 395 } | |
| 396 | |
| 0 | 397 // Secret local extension to Assembler::WhichOperand: |
| 398 #define end_pc_operand (_WhichOperand_limit) | |
| 399 | |
| 400 address Assembler::locate_operand(address inst, WhichOperand which) { | |
| 401 // Decode the given instruction, and return the address of | |
| 402 // an embedded 32-bit operand word. | |
| 403 | |
| 404 // If "which" is disp32_operand, selects the displacement portion | |
| 405 // of an effective address specifier. | |
| 304 | 406 // If "which" is imm64_operand, selects the trailing immediate constant. |
| 0 | 407 // If "which" is call32_operand, selects the displacement of a call or jump. |
| 408 // Caller is responsible for ensuring that there is such an operand, | |
| 304 | 409 // and that it is 32/64 bits wide. |
| 0 | 410 |
| 411 // If "which" is end_pc_operand, find the end of the instruction. | |
| 412 | |
| 413 address ip = inst; | |
| 304 | 414 bool is_64bit = false; |
| 415 | |
| 416 debug_only(bool has_disp32 = false); | |
| 417 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn | |
| 418 | |
| 419 again_after_prefix: | |
| 0 | 420 switch (0xFF & *ip++) { |
| 421 | |
| 422 // These convenience macros generate groups of "case" labels for the switch. | |
| 304 | 423 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3 |
| 424 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \ | |
| 0 | 425 case (x)+4: case (x)+5: case (x)+6: case (x)+7 |
| 304 | 426 #define REP16(x) REP8((x)+0): \ |
| 0 | 427 case REP8((x)+8) |
| 428 | |
| 429 case CS_segment: | |
| 430 case SS_segment: | |
| 431 case DS_segment: | |
| 432 case ES_segment: | |
| 433 case FS_segment: | |
| 434 case GS_segment: | |
| 304 | 435 // Seems dubious |
| 436 LP64_ONLY(assert(false, "shouldn't have that prefix")); | |
| 0 | 437 assert(ip == inst+1, "only one prefix allowed"); |
| 438 goto again_after_prefix; | |
| 439 | |
| 304 | 440 case 0x67: |
| 441 case REX: | |
| 442 case REX_B: | |
| 443 case REX_X: | |
| 444 case REX_XB: | |
| 445 case REX_R: | |
| 446 case REX_RB: | |
| 447 case REX_RX: | |
| 448 case REX_RXB: | |
| 449 NOT_LP64(assert(false, "64bit prefixes")); | |
| 450 goto again_after_prefix; | |
| 451 | |
| 452 case REX_W: | |
| 453 case REX_WB: | |
| 454 case REX_WX: | |
| 455 case REX_WXB: | |
| 456 case REX_WR: | |
| 457 case REX_WRB: | |
| 458 case REX_WRX: | |
| 459 case REX_WRXB: | |
| 460 NOT_LP64(assert(false, "64bit prefixes")); | |
| 461 is_64bit = true; | |
| 462 goto again_after_prefix; | |
| 463 | |
| 464 case 0xFF: // pushq a; decl a; incl a; call a; jmp a | |
| 0 | 465 case 0x88: // movb a, r |
| 466 case 0x89: // movl a, r | |
| 467 case 0x8A: // movb r, a | |
| 468 case 0x8B: // movl r, a | |
| 469 case 0x8F: // popl a | |
| 304 | 470 debug_only(has_disp32 = true); |
| 0 | 471 break; |
| 472 | |
| 304 | 473 case 0x68: // pushq #32 |
| 474 if (which == end_pc_operand) { | |
| 475 return ip + 4; | |
| 476 } | |
| 477 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate"); | |
| 0 | 478 return ip; // not produced by emit_operand |
| 479 | |
| 480 case 0x66: // movw ... (size prefix) | |
| 304 | 481 again_after_size_prefix2: |
| 0 | 482 switch (0xFF & *ip++) { |
| 304 | 483 case REX: |
| 484 case REX_B: | |
| 485 case REX_X: | |
| 486 case REX_XB: | |
| 487 case REX_R: | |
| 488 case REX_RB: | |
| 489 case REX_RX: | |
| 490 case REX_RXB: | |
| 491 case REX_W: | |
| 492 case REX_WB: | |
| 493 case REX_WX: | |
| 494 case REX_WXB: | |
| 495 case REX_WR: | |
| 496 case REX_WRB: | |
| 497 case REX_WRX: | |
| 498 case REX_WRXB: | |
| 499 NOT_LP64(assert(false, "64bit prefix found")); | |
| 500 goto again_after_size_prefix2; | |
| 0 | 501 case 0x8B: // movw r, a |
| 502 case 0x89: // movw a, r | |
| 304 | 503 debug_only(has_disp32 = true); |
| 0 | 504 break; |
| 505 case 0xC7: // movw a, #16 | |
| 304 | 506 debug_only(has_disp32 = true); |
| 0 | 507 tail_size = 2; // the imm16 |
| 508 break; | |
| 509 case 0x0F: // several SSE/SSE2 variants | |
| 510 ip--; // reparse the 0x0F | |
| 511 goto again_after_prefix; | |
| 512 default: | |
| 513 ShouldNotReachHere(); | |
| 514 } | |
| 515 break; | |
| 516 | |
| 304 | 517 case REP8(0xB8): // movl/q r, #32/#64(oop?) |
| 518 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4); | |
| 519 // these asserts are somewhat nonsensical | |
| 520 #ifndef _LP64 | |
| 521 assert(which == imm_operand || which == disp32_operand, ""); | |
| 522 #else | |
| 523 assert((which == call32_operand || which == imm_operand) && is_64bit || | |
| 524 which == narrow_oop_operand && !is_64bit, ""); | |
| 525 #endif // _LP64 | |
| 0 | 526 return ip; |
| 527 | |
| 528 case 0x69: // imul r, a, #32 | |
| 529 case 0xC7: // movl a, #32(oop?) | |
| 530 tail_size = 4; | |
| 304 | 531 debug_only(has_disp32 = true); // has both kinds of operands! |
| 0 | 532 break; |
| 533 | |
| 534 case 0x0F: // movx..., etc. | |
| 535 switch (0xFF & *ip++) { | |
| 536 case 0x12: // movlps | |
| 537 case 0x28: // movaps | |
| 538 case 0x2E: // ucomiss | |
| 539 case 0x2F: // comiss | |
| 540 case 0x54: // andps | |
| 541 case 0x55: // andnps | |
| 542 case 0x56: // orps | |
| 543 case 0x57: // xorps | |
| 544 case 0x6E: // movd | |
| 545 case 0x7E: // movd | |
| 546 case 0xAE: // ldmxcsr a | |
| 304 | 547 // 64bit side says it these have both operands but that doesn't |
| 548 // appear to be true | |
| 549 debug_only(has_disp32 = true); | |
| 0 | 550 break; |
| 551 | |
| 552 case 0xAD: // shrd r, a, %cl | |
| 553 case 0xAF: // imul r, a | |
| 304 | 554 case 0xBE: // movsbl r, a (movsxb) |
| 555 case 0xBF: // movswl r, a (movsxw) | |
| 556 case 0xB6: // movzbl r, a (movzxb) | |
| 557 case 0xB7: // movzwl r, a (movzxw) | |
| 0 | 558 case REP16(0x40): // cmovl cc, r, a |
| 559 case 0xB0: // cmpxchgb | |
| 560 case 0xB1: // cmpxchg | |
| 561 case 0xC1: // xaddl | |
| 562 case 0xC7: // cmpxchg8 | |
| 563 case REP16(0x90): // setcc a | |
| 304 | 564 debug_only(has_disp32 = true); |
| 0 | 565 // fall out of the switch to decode the address |
| 566 break; | |
| 304 | 567 |
| 0 | 568 case 0xAC: // shrd r, a, #8 |
| 304 | 569 debug_only(has_disp32 = true); |
| 0 | 570 tail_size = 1; // the imm8 |
| 571 break; | |
| 304 | 572 |
| 0 | 573 case REP16(0x80): // jcc rdisp32 |
| 574 if (which == end_pc_operand) return ip + 4; | |
| 304 | 575 assert(which == call32_operand, "jcc has no disp32 or imm"); |
| 0 | 576 return ip; |
| 577 default: | |
| 578 ShouldNotReachHere(); | |
| 579 } | |
| 580 break; | |
| 581 | |
| 582 case 0x81: // addl a, #32; addl r, #32 | |
| 583 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl | |
| 304 | 584 // on 32bit in the case of cmpl, the imm might be an oop |
| 0 | 585 tail_size = 4; |
| 304 | 586 debug_only(has_disp32 = true); // has both kinds of operands! |
| 0 | 587 break; |
| 588 | |
| 589 case 0x83: // addl a, #8; addl r, #8 | |
| 590 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl | |
| 304 | 591 debug_only(has_disp32 = true); // has both kinds of operands! |
| 0 | 592 tail_size = 1; |
| 593 break; | |
| 594 | |
| 595 case 0x9B: | |
| 596 switch (0xFF & *ip++) { | |
| 597 case 0xD9: // fnstcw a | |
| 304 | 598 debug_only(has_disp32 = true); |
| 0 | 599 break; |
| 600 default: | |
| 601 ShouldNotReachHere(); | |
| 602 } | |
| 603 break; | |
| 604 | |
| 605 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a | |
| 606 case REP4(0x10): // adc... | |
| 607 case REP4(0x20): // and... | |
| 608 case REP4(0x30): // xor... | |
| 609 case REP4(0x08): // or... | |
| 610 case REP4(0x18): // sbb... | |
| 611 case REP4(0x28): // sub... | |
| 304 | 612 case 0xF7: // mull a |
| 613 case 0x8D: // lea r, a | |
| 614 case 0x87: // xchg r, a | |
| 0 | 615 case REP4(0x38): // cmp... |
| 304 | 616 case 0x85: // test r, a |
| 617 debug_only(has_disp32 = true); // has both kinds of operands! | |
| 0 | 618 break; |
| 619 | |
| 620 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8 | |
| 621 case 0xC6: // movb a, #8 | |
| 622 case 0x80: // cmpb a, #8 | |
| 623 case 0x6B: // imul r, a, #8 | |
| 304 | 624 debug_only(has_disp32 = true); // has both kinds of operands! |
| 0 | 625 tail_size = 1; // the imm8 |
| 626 break; | |
| 627 | |
| 628 case 0xE8: // call rdisp32 | |
| 629 case 0xE9: // jmp rdisp32 | |
| 630 if (which == end_pc_operand) return ip + 4; | |
| 304 | 631 assert(which == call32_operand, "call has no disp32 or imm"); |
| 0 | 632 return ip; |
| 633 | |
| 634 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1 | |
| 635 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl | |
| 636 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a | |
| 637 case 0xDD: // fld_d a; fst_d a; fstp_d a | |
| 638 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a | |
| 639 case 0xDF: // fild_d a; fistp_d a | |
| 640 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a | |
| 641 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a | |
| 642 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a | |
| 304 | 643 debug_only(has_disp32 = true); |
| 0 | 644 break; |
| 645 | |
|
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646 case 0xF0: // Lock |
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647 assert(os::is_MP(), "only on MP"); |
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648 goto again_after_prefix; |
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649 |
| 0 | 650 case 0xF3: // For SSE |
| 651 case 0xF2: // For SSE2 | |
| 304 | 652 switch (0xFF & *ip++) { |
| 653 case REX: | |
| 654 case REX_B: | |
| 655 case REX_X: | |
| 656 case REX_XB: | |
| 657 case REX_R: | |
| 658 case REX_RB: | |
| 659 case REX_RX: | |
| 660 case REX_RXB: | |
| 661 case REX_W: | |
| 662 case REX_WB: | |
| 663 case REX_WX: | |
| 664 case REX_WXB: | |
| 665 case REX_WR: | |
| 666 case REX_WRB: | |
| 667 case REX_WRX: | |
| 668 case REX_WRXB: | |
| 669 NOT_LP64(assert(false, "found 64bit prefix")); | |
| 670 ip++; | |
| 671 default: | |
| 672 ip++; | |
| 673 } | |
| 674 debug_only(has_disp32 = true); // has both kinds of operands! | |
| 0 | 675 break; |
| 676 | |
| 677 default: | |
| 678 ShouldNotReachHere(); | |
| 679 | |
| 304 | 680 #undef REP8 |
| 681 #undef REP16 | |
| 0 | 682 } |
| 683 | |
| 684 assert(which != call32_operand, "instruction is not a call, jmp, or jcc"); | |
| 304 | 685 #ifdef _LP64 |
| 686 assert(which != imm_operand, "instruction is not a movq reg, imm64"); | |
| 687 #else | |
| 688 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field"); | |
| 689 assert(which != imm_operand || has_disp32, "instruction has no imm32 field"); | |
| 690 #endif // LP64 | |
| 691 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field"); | |
| 0 | 692 |
| 693 // parse the output of emit_operand | |
| 694 int op2 = 0xFF & *ip++; | |
| 695 int base = op2 & 0x07; | |
| 696 int op3 = -1; | |
| 697 const int b100 = 4; | |
| 698 const int b101 = 5; | |
| 699 if (base == b100 && (op2 >> 6) != 3) { | |
| 700 op3 = 0xFF & *ip++; | |
| 701 base = op3 & 0x07; // refetch the base | |
| 702 } | |
| 703 // now ip points at the disp (if any) | |
| 704 | |
| 705 switch (op2 >> 6) { | |
| 706 case 0: | |
| 707 // [00 reg 100][ss index base] | |
| 304 | 708 // [00 reg 100][00 100 esp] |
| 0 | 709 // [00 reg base] |
| 710 // [00 reg 100][ss index 101][disp32] | |
| 711 // [00 reg 101] [disp32] | |
| 712 | |
| 713 if (base == b101) { | |
| 714 if (which == disp32_operand) | |
| 715 return ip; // caller wants the disp32 | |
| 716 ip += 4; // skip the disp32 | |
| 717 } | |
| 718 break; | |
| 719 | |
| 720 case 1: | |
| 721 // [01 reg 100][ss index base][disp8] | |
| 304 | 722 // [01 reg 100][00 100 esp][disp8] |
| 0 | 723 // [01 reg base] [disp8] |
| 724 ip += 1; // skip the disp8 | |
| 725 break; | |
| 726 | |
| 727 case 2: | |
| 728 // [10 reg 100][ss index base][disp32] | |
| 304 | 729 // [10 reg 100][00 100 esp][disp32] |
| 0 | 730 // [10 reg base] [disp32] |
| 731 if (which == disp32_operand) | |
| 732 return ip; // caller wants the disp32 | |
| 733 ip += 4; // skip the disp32 | |
| 734 break; | |
| 735 | |
| 736 case 3: | |
| 737 // [11 reg base] (not a memory addressing mode) | |
| 738 break; | |
| 739 } | |
| 740 | |
| 741 if (which == end_pc_operand) { | |
| 742 return ip + tail_size; | |
| 743 } | |
| 744 | |
| 304 | 745 #ifdef _LP64 |
|
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746 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32"); |
| 304 | 747 #else |
| 748 assert(which == imm_operand, "instruction has only an imm field"); | |
| 749 #endif // LP64 | |
| 0 | 750 return ip; |
| 751 } | |
| 752 | |
| 753 address Assembler::locate_next_instruction(address inst) { | |
| 754 // Secretly share code with locate_operand: | |
| 755 return locate_operand(inst, end_pc_operand); | |
| 756 } | |
| 757 | |
| 758 | |
| 759 #ifdef ASSERT | |
| 760 void Assembler::check_relocation(RelocationHolder const& rspec, int format) { | |
| 761 address inst = inst_mark(); | |
| 762 assert(inst != NULL && inst < pc(), "must point to beginning of instruction"); | |
| 763 address opnd; | |
| 764 | |
| 765 Relocation* r = rspec.reloc(); | |
| 766 if (r->type() == relocInfo::none) { | |
| 767 return; | |
| 768 } else if (r->is_call() || format == call32_operand) { | |
| 769 // assert(format == imm32_operand, "cannot specify a nonzero format"); | |
| 770 opnd = locate_operand(inst, call32_operand); | |
| 771 } else if (r->is_data()) { | |
| 304 | 772 assert(format == imm_operand || format == disp32_operand |
| 773 LP64_ONLY(|| format == narrow_oop_operand), "format ok"); | |
| 0 | 774 opnd = locate_operand(inst, (WhichOperand)format); |
| 775 } else { | |
| 304 | 776 assert(format == imm_operand, "cannot specify a format"); |
| 0 | 777 return; |
| 778 } | |
| 779 assert(opnd == pc(), "must put operand where relocs can find it"); | |
| 780 } | |
| 304 | 781 #endif // ASSERT |
| 782 | |
| 783 void Assembler::emit_operand32(Register reg, Address adr) { | |
| 784 assert(reg->encoding() < 8, "no extended registers"); | |
| 785 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
| 786 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
| 787 adr._rspec); | |
| 788 } | |
| 789 | |
| 790 void Assembler::emit_operand(Register reg, Address adr, | |
| 791 int rip_relative_correction) { | |
| 792 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
| 793 adr._rspec, | |
| 794 rip_relative_correction); | |
| 795 } | |
| 796 | |
| 797 void Assembler::emit_operand(XMMRegister reg, Address adr) { | |
| 798 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
| 799 adr._rspec); | |
| 800 } | |
| 801 | |
| 802 // MMX operations | |
| 803 void Assembler::emit_operand(MMXRegister reg, Address adr) { | |
| 804 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
| 805 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); | |
| 806 } | |
| 807 | |
| 808 // work around gcc (3.2.1-7a) bug | |
| 809 void Assembler::emit_operand(Address adr, MMXRegister reg) { | |
| 810 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
| 811 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); | |
| 0 | 812 } |
| 813 | |
| 814 | |
| 815 void Assembler::emit_farith(int b1, int b2, int i) { | |
| 816 assert(isByte(b1) && isByte(b2), "wrong opcode"); | |
| 817 assert(0 <= i && i < 8, "illegal stack offset"); | |
| 818 emit_byte(b1); | |
| 819 emit_byte(b2 + i); | |
| 820 } | |
| 821 | |
| 822 | |
|
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823 // Now the Assembler instructions (identical for 32/64 bits) |
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824 |
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825 void Assembler::adcl(Address dst, int32_t imm32) { |
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826 InstructionMark im(this); |
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827 prefix(dst); |
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828 emit_arith_operand(0x81, rdx, dst, imm32); |
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829 } |
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830 |
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831 void Assembler::adcl(Address dst, Register src) { |
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832 InstructionMark im(this); |
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833 prefix(dst, src); |
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834 emit_byte(0x11); |
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835 emit_operand(src, dst); |
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836 } |
| 304 | 837 |
| 838 void Assembler::adcl(Register dst, int32_t imm32) { | |
| 839 prefix(dst); | |
| 0 | 840 emit_arith(0x81, 0xD0, dst, imm32); |
| 841 } | |
| 842 | |
| 843 void Assembler::adcl(Register dst, Address src) { | |
| 844 InstructionMark im(this); | |
| 304 | 845 prefix(src, dst); |
| 0 | 846 emit_byte(0x13); |
| 847 emit_operand(dst, src); | |
| 848 } | |
| 849 | |
| 850 void Assembler::adcl(Register dst, Register src) { | |
| 304 | 851 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
| 0 | 852 emit_arith(0x13, 0xC0, dst, src); |
| 853 } | |
| 854 | |
| 304 | 855 void Assembler::addl(Address dst, int32_t imm32) { |
| 856 InstructionMark im(this); | |
| 857 prefix(dst); | |
| 858 emit_arith_operand(0x81, rax, dst, imm32); | |
| 859 } | |
| 0 | 860 |
| 861 void Assembler::addl(Address dst, Register src) { | |
| 862 InstructionMark im(this); | |
| 304 | 863 prefix(dst, src); |
| 0 | 864 emit_byte(0x01); |
| 865 emit_operand(src, dst); | |
| 866 } | |
| 867 | |
| 304 | 868 void Assembler::addl(Register dst, int32_t imm32) { |
| 869 prefix(dst); | |
| 0 | 870 emit_arith(0x81, 0xC0, dst, imm32); |
| 871 } | |
| 872 | |
| 873 void Assembler::addl(Register dst, Address src) { | |
| 874 InstructionMark im(this); | |
| 304 | 875 prefix(src, dst); |
| 0 | 876 emit_byte(0x03); |
| 877 emit_operand(dst, src); | |
| 878 } | |
| 879 | |
| 880 void Assembler::addl(Register dst, Register src) { | |
| 304 | 881 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
| 0 | 882 emit_arith(0x03, 0xC0, dst, src); |
| 883 } | |
| 884 | |
| 885 void Assembler::addr_nop_4() { | |
| 886 // 4 bytes: NOP DWORD PTR [EAX+0] | |
| 887 emit_byte(0x0F); | |
| 888 emit_byte(0x1F); | |
| 889 emit_byte(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc); | |
| 890 emit_byte(0); // 8-bits offset (1 byte) | |
| 891 } | |
| 892 | |
| 893 void Assembler::addr_nop_5() { | |
| 894 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset | |
| 895 emit_byte(0x0F); | |
| 896 emit_byte(0x1F); | |
| 897 emit_byte(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4); | |
| 898 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); | |
| 899 emit_byte(0); // 8-bits offset (1 byte) | |
| 900 } | |
| 901 | |
| 902 void Assembler::addr_nop_7() { | |
| 903 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset | |
| 904 emit_byte(0x0F); | |
| 905 emit_byte(0x1F); | |
| 906 emit_byte(0x80); // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc); | |
| 907 emit_long(0); // 32-bits offset (4 bytes) | |
| 908 } | |
| 909 | |
| 910 void Assembler::addr_nop_8() { | |
| 911 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset | |
| 912 emit_byte(0x0F); | |
| 913 emit_byte(0x1F); | |
| 914 emit_byte(0x84); // emit_rm(cbuf, 0x2, EAX_enc, 0x4); | |
| 915 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); | |
| 916 emit_long(0); // 32-bits offset (4 bytes) | |
| 917 } | |
| 918 | |
| 304 | 919 void Assembler::addsd(XMMRegister dst, XMMRegister src) { |
| 920 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 921 emit_byte(0xF2); | |
| 922 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 923 emit_byte(0x0F); | |
| 924 emit_byte(0x58); | |
| 925 emit_byte(0xC0 | encode); | |
| 926 } | |
| 927 | |
| 928 void Assembler::addsd(XMMRegister dst, Address src) { | |
| 929 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 930 InstructionMark im(this); | |
| 931 emit_byte(0xF2); | |
| 932 prefix(src, dst); | |
| 933 emit_byte(0x0F); | |
| 934 emit_byte(0x58); | |
| 935 emit_operand(dst, src); | |
| 936 } | |
| 937 | |
| 938 void Assembler::addss(XMMRegister dst, XMMRegister src) { | |
| 939 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 940 emit_byte(0xF3); | |
| 941 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 942 emit_byte(0x0F); | |
| 943 emit_byte(0x58); | |
| 944 emit_byte(0xC0 | encode); | |
| 945 } | |
| 946 | |
| 947 void Assembler::addss(XMMRegister dst, Address src) { | |
| 948 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 949 InstructionMark im(this); | |
| 950 emit_byte(0xF3); | |
| 951 prefix(src, dst); | |
| 952 emit_byte(0x0F); | |
| 953 emit_byte(0x58); | |
| 954 emit_operand(dst, src); | |
| 955 } | |
| 956 | |
| 957 void Assembler::andl(Register dst, int32_t imm32) { | |
| 958 prefix(dst); | |
| 959 emit_arith(0x81, 0xE0, dst, imm32); | |
| 960 } | |
| 961 | |
| 962 void Assembler::andl(Register dst, Address src) { | |
| 963 InstructionMark im(this); | |
| 964 prefix(src, dst); | |
| 965 emit_byte(0x23); | |
| 966 emit_operand(dst, src); | |
| 967 } | |
| 968 | |
| 969 void Assembler::andl(Register dst, Register src) { | |
| 970 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 971 emit_arith(0x23, 0xC0, dst, src); | |
| 972 } | |
| 973 | |
| 974 void Assembler::andpd(XMMRegister dst, Address src) { | |
| 975 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 976 InstructionMark im(this); | |
| 977 emit_byte(0x66); | |
| 978 prefix(src, dst); | |
| 979 emit_byte(0x0F); | |
| 980 emit_byte(0x54); | |
| 981 emit_operand(dst, src); | |
| 982 } | |
| 983 | |
|
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984 void Assembler::bsfl(Register dst, Register src) { |
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985 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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986 emit_byte(0x0F); |
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987 emit_byte(0xBC); |
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988 emit_byte(0xC0 | encode); |
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989 } |
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990 |
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991 void Assembler::bsrl(Register dst, Register src) { |
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992 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT"); |
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993 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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994 emit_byte(0x0F); |
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995 emit_byte(0xBD); |
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996 emit_byte(0xC0 | encode); |
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997 } |
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998 |
| 304 | 999 void Assembler::bswapl(Register reg) { // bswap |
| 1000 int encode = prefix_and_encode(reg->encoding()); | |
| 1001 emit_byte(0x0F); | |
| 1002 emit_byte(0xC8 | encode); | |
| 1003 } | |
| 1004 | |
| 1005 void Assembler::call(Label& L, relocInfo::relocType rtype) { | |
| 1006 // suspect disp32 is always good | |
| 1007 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand); | |
| 1008 | |
| 1009 if (L.is_bound()) { | |
| 1010 const int long_size = 5; | |
| 1011 int offs = (int)( target(L) - pc() ); | |
| 1012 assert(offs <= 0, "assembler error"); | |
| 1013 InstructionMark im(this); | |
| 1014 // 1110 1000 #32-bit disp | |
| 1015 emit_byte(0xE8); | |
| 1016 emit_data(offs - long_size, rtype, operand); | |
| 1017 } else { | |
| 1018 InstructionMark im(this); | |
| 1019 // 1110 1000 #32-bit disp | |
| 1020 L.add_patch_at(code(), locator()); | |
| 1021 | |
| 1022 emit_byte(0xE8); | |
| 1023 emit_data(int(0), rtype, operand); | |
| 1024 } | |
| 1025 } | |
| 1026 | |
| 1027 void Assembler::call(Register dst) { | |
| 1028 // This was originally using a 32bit register encoding | |
| 1029 // and surely we want 64bit! | |
| 1030 // this is a 32bit encoding but in 64bit mode the default | |
| 1031 // operand size is 64bit so there is no need for the | |
| 1032 // wide prefix. So prefix only happens if we use the | |
| 1033 // new registers. Much like push/pop. | |
| 1034 int x = offset(); | |
| 1035 // this may be true but dbx disassembles it as if it | |
| 1036 // were 32bits... | |
| 1037 // int encode = prefix_and_encode(dst->encoding()); | |
| 1038 // if (offset() != x) assert(dst->encoding() >= 8, "what?"); | |
| 1039 int encode = prefixq_and_encode(dst->encoding()); | |
| 1040 | |
| 1041 emit_byte(0xFF); | |
| 1042 emit_byte(0xD0 | encode); | |
| 1043 } | |
| 1044 | |
| 1045 | |
| 1046 void Assembler::call(Address adr) { | |
| 1047 InstructionMark im(this); | |
| 1048 prefix(adr); | |
| 1049 emit_byte(0xFF); | |
| 1050 emit_operand(rdx, adr); | |
| 1051 } | |
| 1052 | |
| 1053 void Assembler::call_literal(address entry, RelocationHolder const& rspec) { | |
| 1054 assert(entry != NULL, "call most probably wrong"); | |
| 1055 InstructionMark im(this); | |
| 1056 emit_byte(0xE8); | |
| 1057 intptr_t disp = entry - (_code_pos + sizeof(int32_t)); | |
| 1058 assert(is_simm32(disp), "must be 32bit offset (call2)"); | |
| 1059 // Technically, should use call32_operand, but this format is | |
| 1060 // implied by the fact that we're emitting a call instruction. | |
| 1061 | |
| 1062 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand); | |
| 1063 emit_data((int) disp, rspec, operand); | |
| 1064 } | |
| 1065 | |
| 1066 void Assembler::cdql() { | |
| 1067 emit_byte(0x99); | |
| 1068 } | |
| 1069 | |
| 1070 void Assembler::cmovl(Condition cc, Register dst, Register src) { | |
| 1071 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); | |
| 1072 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1073 emit_byte(0x0F); | |
| 1074 emit_byte(0x40 | cc); | |
| 1075 emit_byte(0xC0 | encode); | |
| 1076 } | |
| 1077 | |
| 1078 | |
| 1079 void Assembler::cmovl(Condition cc, Register dst, Address src) { | |
| 1080 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); | |
| 1081 prefix(src, dst); | |
| 1082 emit_byte(0x0F); | |
| 1083 emit_byte(0x40 | cc); | |
| 1084 emit_operand(dst, src); | |
| 1085 } | |
| 1086 | |
| 1087 void Assembler::cmpb(Address dst, int imm8) { | |
| 1088 InstructionMark im(this); | |
| 1089 prefix(dst); | |
| 1090 emit_byte(0x80); | |
| 1091 emit_operand(rdi, dst, 1); | |
| 1092 emit_byte(imm8); | |
| 1093 } | |
| 1094 | |
| 1095 void Assembler::cmpl(Address dst, int32_t imm32) { | |
| 1096 InstructionMark im(this); | |
| 1097 prefix(dst); | |
| 1098 emit_byte(0x81); | |
| 1099 emit_operand(rdi, dst, 4); | |
| 1100 emit_long(imm32); | |
| 1101 } | |
| 1102 | |
| 1103 void Assembler::cmpl(Register dst, int32_t imm32) { | |
| 1104 prefix(dst); | |
| 1105 emit_arith(0x81, 0xF8, dst, imm32); | |
| 1106 } | |
| 1107 | |
| 1108 void Assembler::cmpl(Register dst, Register src) { | |
| 1109 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1110 emit_arith(0x3B, 0xC0, dst, src); | |
| 1111 } | |
| 1112 | |
| 1113 | |
| 1114 void Assembler::cmpl(Register dst, Address src) { | |
| 1115 InstructionMark im(this); | |
| 1116 prefix(src, dst); | |
| 1117 emit_byte(0x3B); | |
| 1118 emit_operand(dst, src); | |
| 1119 } | |
| 1120 | |
| 1121 void Assembler::cmpw(Address dst, int imm16) { | |
| 1122 InstructionMark im(this); | |
| 1123 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers"); | |
| 1124 emit_byte(0x66); | |
| 1125 emit_byte(0x81); | |
| 1126 emit_operand(rdi, dst, 2); | |
| 1127 emit_word(imm16); | |
| 1128 } | |
| 1129 | |
| 1130 // The 32-bit cmpxchg compares the value at adr with the contents of rax, | |
| 1131 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,. | |
| 1132 // The ZF is set if the compared values were equal, and cleared otherwise. | |
| 1133 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg | |
| 1134 if (Atomics & 2) { | |
| 1135 // caveat: no instructionmark, so this isn't relocatable. | |
| 1136 // Emit a synthetic, non-atomic, CAS equivalent. | |
| 1137 // Beware. The synthetic form sets all ICCs, not just ZF. | |
| 1138 // cmpxchg r,[m] is equivalent to rax, = CAS (m, rax, r) | |
| 1139 cmpl(rax, adr); | |
| 1140 movl(rax, adr); | |
| 1141 if (reg != rax) { | |
| 1142 Label L ; | |
| 1143 jcc(Assembler::notEqual, L); | |
| 1144 movl(adr, reg); | |
| 1145 bind(L); | |
| 1146 } | |
| 1147 } else { | |
| 1148 InstructionMark im(this); | |
| 1149 prefix(adr, reg); | |
| 1150 emit_byte(0x0F); | |
| 1151 emit_byte(0xB1); | |
| 1152 emit_operand(reg, adr); | |
| 1153 } | |
| 1154 } | |
| 1155 | |
| 1156 void Assembler::comisd(XMMRegister dst, Address src) { | |
| 1157 // NOTE: dbx seems to decode this as comiss even though the | |
| 1158 // 0x66 is there. Strangly ucomisd comes out correct | |
| 1159 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1160 emit_byte(0x66); | |
| 1161 comiss(dst, src); | |
| 1162 } | |
| 1163 | |
| 1164 void Assembler::comiss(XMMRegister dst, Address src) { | |
| 1165 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1166 | |
| 1167 InstructionMark im(this); | |
| 1168 prefix(src, dst); | |
| 1169 emit_byte(0x0F); | |
| 1170 emit_byte(0x2F); | |
| 1171 emit_operand(dst, src); | |
| 1172 } | |
| 1173 | |
| 1174 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) { | |
| 1175 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1176 emit_byte(0xF3); | |
| 1177 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1178 emit_byte(0x0F); | |
| 1179 emit_byte(0xE6); | |
| 1180 emit_byte(0xC0 | encode); | |
| 1181 } | |
| 1182 | |
| 1183 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) { | |
| 1184 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1185 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1186 emit_byte(0x0F); | |
| 1187 emit_byte(0x5B); | |
| 1188 emit_byte(0xC0 | encode); | |
| 1189 } | |
| 1190 | |
| 1191 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) { | |
| 1192 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1193 emit_byte(0xF2); | |
| 1194 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1195 emit_byte(0x0F); | |
| 1196 emit_byte(0x5A); | |
| 1197 emit_byte(0xC0 | encode); | |
| 1198 } | |
| 1199 | |
| 1200 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) { | |
| 1201 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1202 emit_byte(0xF2); | |
| 1203 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1204 emit_byte(0x0F); | |
| 1205 emit_byte(0x2A); | |
| 1206 emit_byte(0xC0 | encode); | |
| 1207 } | |
| 1208 | |
| 1209 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) { | |
| 1210 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1211 emit_byte(0xF3); | |
| 1212 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1213 emit_byte(0x0F); | |
| 1214 emit_byte(0x2A); | |
| 1215 emit_byte(0xC0 | encode); | |
| 1216 } | |
| 1217 | |
| 1218 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) { | |
| 1219 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1220 emit_byte(0xF3); | |
| 1221 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1222 emit_byte(0x0F); | |
| 1223 emit_byte(0x5A); | |
| 1224 emit_byte(0xC0 | encode); | |
| 1225 } | |
| 1226 | |
| 1227 void Assembler::cvttsd2sil(Register dst, XMMRegister src) { | |
| 1228 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1229 emit_byte(0xF2); | |
| 1230 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1231 emit_byte(0x0F); | |
| 1232 emit_byte(0x2C); | |
| 1233 emit_byte(0xC0 | encode); | |
| 1234 } | |
| 1235 | |
| 1236 void Assembler::cvttss2sil(Register dst, XMMRegister src) { | |
| 1237 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1238 emit_byte(0xF3); | |
| 1239 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1240 emit_byte(0x0F); | |
| 1241 emit_byte(0x2C); | |
| 1242 emit_byte(0xC0 | encode); | |
| 1243 } | |
| 1244 | |
| 1245 void Assembler::decl(Address dst) { | |
| 1246 // Don't use it directly. Use MacroAssembler::decrement() instead. | |
| 1247 InstructionMark im(this); | |
| 1248 prefix(dst); | |
| 1249 emit_byte(0xFF); | |
| 1250 emit_operand(rcx, dst); | |
| 1251 } | |
| 1252 | |
| 1253 void Assembler::divsd(XMMRegister dst, Address src) { | |
| 1254 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1255 InstructionMark im(this); | |
| 1256 emit_byte(0xF2); | |
| 1257 prefix(src, dst); | |
| 1258 emit_byte(0x0F); | |
| 1259 emit_byte(0x5E); | |
| 1260 emit_operand(dst, src); | |
| 1261 } | |
| 1262 | |
| 1263 void Assembler::divsd(XMMRegister dst, XMMRegister src) { | |
| 1264 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1265 emit_byte(0xF2); | |
| 1266 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1267 emit_byte(0x0F); | |
| 1268 emit_byte(0x5E); | |
| 1269 emit_byte(0xC0 | encode); | |
| 1270 } | |
| 1271 | |
| 1272 void Assembler::divss(XMMRegister dst, Address src) { | |
| 1273 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1274 InstructionMark im(this); | |
| 1275 emit_byte(0xF3); | |
| 1276 prefix(src, dst); | |
| 1277 emit_byte(0x0F); | |
| 1278 emit_byte(0x5E); | |
| 1279 emit_operand(dst, src); | |
| 1280 } | |
| 1281 | |
| 1282 void Assembler::divss(XMMRegister dst, XMMRegister src) { | |
| 1283 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1284 emit_byte(0xF3); | |
| 1285 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1286 emit_byte(0x0F); | |
| 1287 emit_byte(0x5E); | |
| 1288 emit_byte(0xC0 | encode); | |
| 1289 } | |
| 1290 | |
| 1291 void Assembler::emms() { | |
| 1292 NOT_LP64(assert(VM_Version::supports_mmx(), "")); | |
| 1293 emit_byte(0x0F); | |
| 1294 emit_byte(0x77); | |
| 1295 } | |
| 1296 | |
| 1297 void Assembler::hlt() { | |
| 1298 emit_byte(0xF4); | |
| 1299 } | |
| 1300 | |
| 1301 void Assembler::idivl(Register src) { | |
| 1302 int encode = prefix_and_encode(src->encoding()); | |
| 1303 emit_byte(0xF7); | |
| 1304 emit_byte(0xF8 | encode); | |
| 1305 } | |
| 1306 | |
| 1920 | 1307 void Assembler::divl(Register src) { // Unsigned |
| 1308 int encode = prefix_and_encode(src->encoding()); | |
| 1309 emit_byte(0xF7); | |
| 1310 emit_byte(0xF0 | encode); | |
| 1311 } | |
| 1312 | |
| 304 | 1313 void Assembler::imull(Register dst, Register src) { |
| 1314 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1315 emit_byte(0x0F); | |
| 1316 emit_byte(0xAF); | |
| 1317 emit_byte(0xC0 | encode); | |
| 1318 } | |
| 1319 | |
| 1320 | |
| 1321 void Assembler::imull(Register dst, Register src, int value) { | |
| 1322 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1323 if (is8bit(value)) { | |
| 1324 emit_byte(0x6B); | |
| 1325 emit_byte(0xC0 | encode); | |
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1326 emit_byte(value & 0xFF); |
| 304 | 1327 } else { |
| 1328 emit_byte(0x69); | |
| 1329 emit_byte(0xC0 | encode); | |
| 1330 emit_long(value); | |
| 1331 } | |
| 1332 } | |
| 1333 | |
| 1334 void Assembler::incl(Address dst) { | |
| 1335 // Don't use it directly. Use MacroAssembler::increment() instead. | |
| 1336 InstructionMark im(this); | |
| 1337 prefix(dst); | |
| 1338 emit_byte(0xFF); | |
| 1339 emit_operand(rax, dst); | |
| 1340 } | |
| 1341 | |
| 1342 void Assembler::jcc(Condition cc, Label& L, relocInfo::relocType rtype) { | |
| 1343 InstructionMark im(this); | |
| 1344 relocate(rtype); | |
| 1345 assert((0 <= cc) && (cc < 16), "illegal cc"); | |
| 1346 if (L.is_bound()) { | |
| 1347 address dst = target(L); | |
| 1348 assert(dst != NULL, "jcc most probably wrong"); | |
| 1349 | |
| 1350 const int short_size = 2; | |
| 1351 const int long_size = 6; | |
| 1352 intptr_t offs = (intptr_t)dst - (intptr_t)_code_pos; | |
| 1353 if (rtype == relocInfo::none && is8bit(offs - short_size)) { | |
| 1354 // 0111 tttn #8-bit disp | |
| 1355 emit_byte(0x70 | cc); | |
| 1356 emit_byte((offs - short_size) & 0xFF); | |
| 1357 } else { | |
| 1358 // 0000 1111 1000 tttn #32-bit disp | |
| 1359 assert(is_simm32(offs - long_size), | |
| 1360 "must be 32bit offset (call4)"); | |
| 1361 emit_byte(0x0F); | |
| 1362 emit_byte(0x80 | cc); | |
| 1363 emit_long(offs - long_size); | |
| 1364 } | |
| 1365 } else { | |
| 1366 // Note: could eliminate cond. jumps to this jump if condition | |
| 1367 // is the same however, seems to be rather unlikely case. | |
| 1368 // Note: use jccb() if label to be bound is very close to get | |
| 1369 // an 8-bit displacement | |
| 1370 L.add_patch_at(code(), locator()); | |
| 1371 emit_byte(0x0F); | |
| 1372 emit_byte(0x80 | cc); | |
| 1373 emit_long(0); | |
| 1374 } | |
| 1375 } | |
| 1376 | |
| 1377 void Assembler::jccb(Condition cc, Label& L) { | |
| 1378 if (L.is_bound()) { | |
| 1379 const int short_size = 2; | |
| 1380 address entry = target(L); | |
| 1381 assert(is8bit((intptr_t)entry - ((intptr_t)_code_pos + short_size)), | |
| 1382 "Dispacement too large for a short jmp"); | |
| 1383 intptr_t offs = (intptr_t)entry - (intptr_t)_code_pos; | |
| 1384 // 0111 tttn #8-bit disp | |
| 1385 emit_byte(0x70 | cc); | |
| 1386 emit_byte((offs - short_size) & 0xFF); | |
| 1387 } else { | |
| 1388 InstructionMark im(this); | |
| 1389 L.add_patch_at(code(), locator()); | |
| 1390 emit_byte(0x70 | cc); | |
| 1391 emit_byte(0); | |
| 1392 } | |
| 1393 } | |
| 1394 | |
| 1395 void Assembler::jmp(Address adr) { | |
| 1396 InstructionMark im(this); | |
| 1397 prefix(adr); | |
| 1398 emit_byte(0xFF); | |
| 1399 emit_operand(rsp, adr); | |
| 1400 } | |
| 1401 | |
| 1402 void Assembler::jmp(Label& L, relocInfo::relocType rtype) { | |
| 1403 if (L.is_bound()) { | |
| 1404 address entry = target(L); | |
| 1405 assert(entry != NULL, "jmp most probably wrong"); | |
| 1406 InstructionMark im(this); | |
| 1407 const int short_size = 2; | |
| 1408 const int long_size = 5; | |
| 1409 intptr_t offs = entry - _code_pos; | |
| 1410 if (rtype == relocInfo::none && is8bit(offs - short_size)) { | |
| 1411 emit_byte(0xEB); | |
| 1412 emit_byte((offs - short_size) & 0xFF); | |
| 1413 } else { | |
| 1414 emit_byte(0xE9); | |
| 1415 emit_long(offs - long_size); | |
| 1416 } | |
| 1417 } else { | |
| 1418 // By default, forward jumps are always 32-bit displacements, since | |
| 1419 // we can't yet know where the label will be bound. If you're sure that | |
| 1420 // the forward jump will not run beyond 256 bytes, use jmpb to | |
| 1421 // force an 8-bit displacement. | |
| 1422 InstructionMark im(this); | |
| 1423 relocate(rtype); | |
| 1424 L.add_patch_at(code(), locator()); | |
| 1425 emit_byte(0xE9); | |
| 1426 emit_long(0); | |
| 1427 } | |
| 1428 } | |
| 1429 | |
| 1430 void Assembler::jmp(Register entry) { | |
| 1431 int encode = prefix_and_encode(entry->encoding()); | |
| 1432 emit_byte(0xFF); | |
| 1433 emit_byte(0xE0 | encode); | |
| 1434 } | |
| 1435 | |
| 1436 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) { | |
| 1437 InstructionMark im(this); | |
| 1438 emit_byte(0xE9); | |
| 1439 assert(dest != NULL, "must have a target"); | |
| 1440 intptr_t disp = dest - (_code_pos + sizeof(int32_t)); | |
| 1441 assert(is_simm32(disp), "must be 32bit offset (jmp)"); | |
| 1442 emit_data(disp, rspec.reloc(), call32_operand); | |
| 1443 } | |
| 1444 | |
| 1445 void Assembler::jmpb(Label& L) { | |
| 1446 if (L.is_bound()) { | |
| 1447 const int short_size = 2; | |
| 1448 address entry = target(L); | |
| 1449 assert(is8bit((entry - _code_pos) + short_size), | |
| 1450 "Dispacement too large for a short jmp"); | |
| 1451 assert(entry != NULL, "jmp most probably wrong"); | |
| 1452 intptr_t offs = entry - _code_pos; | |
| 1453 emit_byte(0xEB); | |
| 1454 emit_byte((offs - short_size) & 0xFF); | |
| 1455 } else { | |
| 1456 InstructionMark im(this); | |
| 1457 L.add_patch_at(code(), locator()); | |
| 1458 emit_byte(0xEB); | |
| 1459 emit_byte(0); | |
| 1460 } | |
| 1461 } | |
| 1462 | |
| 1463 void Assembler::ldmxcsr( Address src) { | |
| 1464 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1465 InstructionMark im(this); | |
| 1466 prefix(src); | |
| 1467 emit_byte(0x0F); | |
| 1468 emit_byte(0xAE); | |
| 1469 emit_operand(as_Register(2), src); | |
| 1470 } | |
| 1471 | |
| 1472 void Assembler::leal(Register dst, Address src) { | |
| 1473 InstructionMark im(this); | |
| 1474 #ifdef _LP64 | |
| 1475 emit_byte(0x67); // addr32 | |
| 1476 prefix(src, dst); | |
| 1477 #endif // LP64 | |
| 1478 emit_byte(0x8D); | |
| 1479 emit_operand(dst, src); | |
| 1480 } | |
| 1481 | |
| 1482 void Assembler::lock() { | |
| 1483 if (Atomics & 1) { | |
| 1484 // Emit either nothing, a NOP, or a NOP: prefix | |
| 1485 emit_byte(0x90) ; | |
| 1486 } else { | |
| 1487 emit_byte(0xF0); | |
| 1488 } | |
| 1489 } | |
| 1490 | |
|
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1491 void Assembler::lzcntl(Register dst, Register src) { |
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1492 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); |
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1493 emit_byte(0xF3); |
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1494 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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1495 emit_byte(0x0F); |
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1496 emit_byte(0xBD); |
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1497 emit_byte(0xC0 | encode); |
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1498 } |
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1499 |
|
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1500 // Emit mfence instruction |
| 304 | 1501 void Assembler::mfence() { |
|
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1502 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");) |
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1503 emit_byte( 0x0F ); |
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1504 emit_byte( 0xAE ); |
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1505 emit_byte( 0xF0 ); |
| 304 | 1506 } |
| 1507 | |
| 1508 void Assembler::mov(Register dst, Register src) { | |
| 1509 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
| 1510 } | |
| 1511 | |
| 1512 void Assembler::movapd(XMMRegister dst, XMMRegister src) { | |
| 1513 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1514 int dstenc = dst->encoding(); | |
| 1515 int srcenc = src->encoding(); | |
| 1516 emit_byte(0x66); | |
| 1517 if (dstenc < 8) { | |
| 1518 if (srcenc >= 8) { | |
| 1519 prefix(REX_B); | |
| 1520 srcenc -= 8; | |
| 1521 } | |
| 1522 } else { | |
| 1523 if (srcenc < 8) { | |
| 1524 prefix(REX_R); | |
| 1525 } else { | |
| 1526 prefix(REX_RB); | |
| 1527 srcenc -= 8; | |
| 1528 } | |
| 1529 dstenc -= 8; | |
| 1530 } | |
| 1531 emit_byte(0x0F); | |
| 1532 emit_byte(0x28); | |
| 1533 emit_byte(0xC0 | dstenc << 3 | srcenc); | |
| 1534 } | |
| 1535 | |
| 1536 void Assembler::movaps(XMMRegister dst, XMMRegister src) { | |
| 1537 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1538 int dstenc = dst->encoding(); | |
| 1539 int srcenc = src->encoding(); | |
| 1540 if (dstenc < 8) { | |
| 1541 if (srcenc >= 8) { | |
| 1542 prefix(REX_B); | |
| 1543 srcenc -= 8; | |
| 1544 } | |
| 1545 } else { | |
| 1546 if (srcenc < 8) { | |
| 1547 prefix(REX_R); | |
| 1548 } else { | |
| 1549 prefix(REX_RB); | |
| 1550 srcenc -= 8; | |
| 1551 } | |
| 1552 dstenc -= 8; | |
| 1553 } | |
| 1554 emit_byte(0x0F); | |
| 1555 emit_byte(0x28); | |
| 1556 emit_byte(0xC0 | dstenc << 3 | srcenc); | |
| 1557 } | |
| 1558 | |
| 1559 void Assembler::movb(Register dst, Address src) { | |
| 1560 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); | |
| 1561 InstructionMark im(this); | |
| 1562 prefix(src, dst, true); | |
| 1563 emit_byte(0x8A); | |
| 1564 emit_operand(dst, src); | |
| 1565 } | |
| 1566 | |
| 1567 | |
| 1568 void Assembler::movb(Address dst, int imm8) { | |
| 1569 InstructionMark im(this); | |
| 1570 prefix(dst); | |
| 1571 emit_byte(0xC6); | |
| 1572 emit_operand(rax, dst, 1); | |
| 1573 emit_byte(imm8); | |
| 1574 } | |
| 1575 | |
| 1576 | |
| 1577 void Assembler::movb(Address dst, Register src) { | |
| 1578 assert(src->has_byte_register(), "must have byte register"); | |
| 1579 InstructionMark im(this); | |
| 1580 prefix(dst, src, true); | |
| 1581 emit_byte(0x88); | |
| 1582 emit_operand(src, dst); | |
| 1583 } | |
| 1584 | |
| 1585 void Assembler::movdl(XMMRegister dst, Register src) { | |
| 1586 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1587 emit_byte(0x66); | |
| 1588 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1589 emit_byte(0x0F); | |
| 1590 emit_byte(0x6E); | |
| 1591 emit_byte(0xC0 | encode); | |
| 1592 } | |
| 1593 | |
| 1594 void Assembler::movdl(Register dst, XMMRegister src) { | |
| 1595 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1596 emit_byte(0x66); | |
| 1597 // swap src/dst to get correct prefix | |
| 1598 int encode = prefix_and_encode(src->encoding(), dst->encoding()); | |
| 1599 emit_byte(0x0F); | |
| 1600 emit_byte(0x7E); | |
| 1601 emit_byte(0xC0 | encode); | |
| 1602 } | |
| 1603 | |
| 1604 void Assembler::movdqa(XMMRegister dst, Address src) { | |
| 1605 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1606 InstructionMark im(this); | |
| 1607 emit_byte(0x66); | |
| 1608 prefix(src, dst); | |
| 1609 emit_byte(0x0F); | |
| 1610 emit_byte(0x6F); | |
| 1611 emit_operand(dst, src); | |
| 1612 } | |
| 1613 | |
| 1614 void Assembler::movdqa(XMMRegister dst, XMMRegister src) { | |
| 1615 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1616 emit_byte(0x66); | |
| 1617 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 1618 emit_byte(0x0F); | |
| 1619 emit_byte(0x6F); | |
| 1620 emit_byte(0xC0 | encode); | |
| 1621 } | |
| 1622 | |
| 1623 void Assembler::movdqa(Address dst, XMMRegister src) { | |
| 1624 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1625 InstructionMark im(this); | |
| 1626 emit_byte(0x66); | |
| 1627 prefix(dst, src); | |
| 1628 emit_byte(0x0F); | |
| 1629 emit_byte(0x7F); | |
| 1630 emit_operand(src, dst); | |
| 1631 } | |
| 1632 | |
| 405 | 1633 void Assembler::movdqu(XMMRegister dst, Address src) { |
| 1634 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1635 InstructionMark im(this); | |
| 1636 emit_byte(0xF3); | |
| 1637 prefix(src, dst); | |
| 1638 emit_byte(0x0F); | |
| 1639 emit_byte(0x6F); | |
| 1640 emit_operand(dst, src); | |
| 1641 } | |
| 1642 | |
| 1643 void Assembler::movdqu(XMMRegister dst, XMMRegister src) { | |
| 1644 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1645 emit_byte(0xF3); | |
| 1646 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 1647 emit_byte(0x0F); | |
| 1648 emit_byte(0x6F); | |
| 1649 emit_byte(0xC0 | encode); | |
| 1650 } | |
| 1651 | |
| 1652 void Assembler::movdqu(Address dst, XMMRegister src) { | |
| 1653 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1654 InstructionMark im(this); | |
| 1655 emit_byte(0xF3); | |
| 1656 prefix(dst, src); | |
| 1657 emit_byte(0x0F); | |
| 1658 emit_byte(0x7F); | |
| 1659 emit_operand(src, dst); | |
| 1660 } | |
| 1661 | |
| 304 | 1662 // Uses zero extension on 64bit |
| 1663 | |
| 1664 void Assembler::movl(Register dst, int32_t imm32) { | |
| 1665 int encode = prefix_and_encode(dst->encoding()); | |
| 1666 emit_byte(0xB8 | encode); | |
| 1667 emit_long(imm32); | |
| 1668 } | |
| 1669 | |
| 1670 void Assembler::movl(Register dst, Register src) { | |
| 1671 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1672 emit_byte(0x8B); | |
| 1673 emit_byte(0xC0 | encode); | |
| 1674 } | |
| 1675 | |
| 1676 void Assembler::movl(Register dst, Address src) { | |
| 1677 InstructionMark im(this); | |
| 1678 prefix(src, dst); | |
| 1679 emit_byte(0x8B); | |
| 1680 emit_operand(dst, src); | |
| 1681 } | |
| 1682 | |
| 1683 void Assembler::movl(Address dst, int32_t imm32) { | |
| 1684 InstructionMark im(this); | |
| 1685 prefix(dst); | |
| 1686 emit_byte(0xC7); | |
| 1687 emit_operand(rax, dst, 4); | |
| 1688 emit_long(imm32); | |
| 1689 } | |
| 1690 | |
| 1691 void Assembler::movl(Address dst, Register src) { | |
| 1692 InstructionMark im(this); | |
| 1693 prefix(dst, src); | |
| 1694 emit_byte(0x89); | |
| 1695 emit_operand(src, dst); | |
| 1696 } | |
| 1697 | |
| 1698 // New cpus require to use movsd and movss to avoid partial register stall | |
| 1699 // when loading from memory. But for old Opteron use movlpd instead of movsd. | |
| 1700 // The selection is done in MacroAssembler::movdbl() and movflt(). | |
| 1701 void Assembler::movlpd(XMMRegister dst, Address src) { | |
| 1702 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1703 InstructionMark im(this); | |
| 1704 emit_byte(0x66); | |
| 1705 prefix(src, dst); | |
| 1706 emit_byte(0x0F); | |
| 1707 emit_byte(0x12); | |
| 1708 emit_operand(dst, src); | |
| 1709 } | |
| 1710 | |
| 1711 void Assembler::movq( MMXRegister dst, Address src ) { | |
| 1712 assert( VM_Version::supports_mmx(), "" ); | |
| 1713 emit_byte(0x0F); | |
| 1714 emit_byte(0x6F); | |
| 1715 emit_operand(dst, src); | |
| 1716 } | |
| 1717 | |
| 1718 void Assembler::movq( Address dst, MMXRegister src ) { | |
| 1719 assert( VM_Version::supports_mmx(), "" ); | |
| 1720 emit_byte(0x0F); | |
| 1721 emit_byte(0x7F); | |
| 1722 // workaround gcc (3.2.1-7a) bug | |
| 1723 // In that version of gcc with only an emit_operand(MMX, Address) | |
| 1724 // gcc will tail jump and try and reverse the parameters completely | |
| 1725 // obliterating dst in the process. By having a version available | |
| 1726 // that doesn't need to swap the args at the tail jump the bug is | |
| 1727 // avoided. | |
| 1728 emit_operand(dst, src); | |
| 1729 } | |
| 1730 | |
| 1731 void Assembler::movq(XMMRegister dst, Address src) { | |
| 1732 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1733 InstructionMark im(this); | |
| 1734 emit_byte(0xF3); | |
| 1735 prefix(src, dst); | |
| 1736 emit_byte(0x0F); | |
| 1737 emit_byte(0x7E); | |
| 1738 emit_operand(dst, src); | |
| 1739 } | |
| 1740 | |
| 1741 void Assembler::movq(Address dst, XMMRegister src) { | |
| 1742 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1743 InstructionMark im(this); | |
| 1744 emit_byte(0x66); | |
| 1745 prefix(dst, src); | |
| 1746 emit_byte(0x0F); | |
| 1747 emit_byte(0xD6); | |
| 1748 emit_operand(src, dst); | |
| 1749 } | |
| 1750 | |
| 1751 void Assembler::movsbl(Register dst, Address src) { // movsxb | |
| 1752 InstructionMark im(this); | |
| 1753 prefix(src, dst); | |
| 1754 emit_byte(0x0F); | |
| 1755 emit_byte(0xBE); | |
| 1756 emit_operand(dst, src); | |
| 1757 } | |
| 1758 | |
| 1759 void Assembler::movsbl(Register dst, Register src) { // movsxb | |
| 1760 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); | |
| 1761 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true); | |
| 1762 emit_byte(0x0F); | |
| 1763 emit_byte(0xBE); | |
| 1764 emit_byte(0xC0 | encode); | |
| 1765 } | |
| 1766 | |
| 1767 void Assembler::movsd(XMMRegister dst, XMMRegister src) { | |
| 1768 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1769 emit_byte(0xF2); | |
| 1770 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1771 emit_byte(0x0F); | |
| 1772 emit_byte(0x10); | |
| 1773 emit_byte(0xC0 | encode); | |
| 1774 } | |
| 1775 | |
| 1776 void Assembler::movsd(XMMRegister dst, Address src) { | |
| 1777 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1778 InstructionMark im(this); | |
| 1779 emit_byte(0xF2); | |
| 1780 prefix(src, dst); | |
| 1781 emit_byte(0x0F); | |
| 1782 emit_byte(0x10); | |
| 1783 emit_operand(dst, src); | |
| 1784 } | |
| 1785 | |
| 1786 void Assembler::movsd(Address dst, XMMRegister src) { | |
| 1787 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1788 InstructionMark im(this); | |
| 1789 emit_byte(0xF2); | |
| 1790 prefix(dst, src); | |
| 1791 emit_byte(0x0F); | |
| 1792 emit_byte(0x11); | |
| 1793 emit_operand(src, dst); | |
| 1794 } | |
| 1795 | |
| 1796 void Assembler::movss(XMMRegister dst, XMMRegister src) { | |
| 1797 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1798 emit_byte(0xF3); | |
| 1799 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1800 emit_byte(0x0F); | |
| 1801 emit_byte(0x10); | |
| 1802 emit_byte(0xC0 | encode); | |
| 1803 } | |
| 1804 | |
| 1805 void Assembler::movss(XMMRegister dst, Address src) { | |
| 1806 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1807 InstructionMark im(this); | |
| 1808 emit_byte(0xF3); | |
| 1809 prefix(src, dst); | |
| 1810 emit_byte(0x0F); | |
| 1811 emit_byte(0x10); | |
| 1812 emit_operand(dst, src); | |
| 1813 } | |
| 1814 | |
| 1815 void Assembler::movss(Address dst, XMMRegister src) { | |
| 1816 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1817 InstructionMark im(this); | |
| 1818 emit_byte(0xF3); | |
| 1819 prefix(dst, src); | |
| 1820 emit_byte(0x0F); | |
| 1821 emit_byte(0x11); | |
| 1822 emit_operand(src, dst); | |
| 1823 } | |
| 1824 | |
| 1825 void Assembler::movswl(Register dst, Address src) { // movsxw | |
| 1826 InstructionMark im(this); | |
| 1827 prefix(src, dst); | |
| 1828 emit_byte(0x0F); | |
| 1829 emit_byte(0xBF); | |
| 1830 emit_operand(dst, src); | |
| 1831 } | |
| 1832 | |
| 1833 void Assembler::movswl(Register dst, Register src) { // movsxw | |
| 1834 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1835 emit_byte(0x0F); | |
| 1836 emit_byte(0xBF); | |
| 1837 emit_byte(0xC0 | encode); | |
| 1838 } | |
| 1839 | |
| 1840 void Assembler::movw(Address dst, int imm16) { | |
| 1841 InstructionMark im(this); | |
| 1842 | |
| 1843 emit_byte(0x66); // switch to 16-bit mode | |
| 1844 prefix(dst); | |
| 1845 emit_byte(0xC7); | |
| 1846 emit_operand(rax, dst, 2); | |
| 1847 emit_word(imm16); | |
| 1848 } | |
| 1849 | |
| 1850 void Assembler::movw(Register dst, Address src) { | |
| 1851 InstructionMark im(this); | |
| 1852 emit_byte(0x66); | |
| 1853 prefix(src, dst); | |
| 1854 emit_byte(0x8B); | |
| 1855 emit_operand(dst, src); | |
| 1856 } | |
| 1857 | |
| 1858 void Assembler::movw(Address dst, Register src) { | |
| 1859 InstructionMark im(this); | |
| 1860 emit_byte(0x66); | |
| 1861 prefix(dst, src); | |
| 1862 emit_byte(0x89); | |
| 1863 emit_operand(src, dst); | |
| 1864 } | |
| 1865 | |
| 1866 void Assembler::movzbl(Register dst, Address src) { // movzxb | |
| 1867 InstructionMark im(this); | |
| 1868 prefix(src, dst); | |
| 1869 emit_byte(0x0F); | |
| 1870 emit_byte(0xB6); | |
| 1871 emit_operand(dst, src); | |
| 1872 } | |
| 1873 | |
| 1874 void Assembler::movzbl(Register dst, Register src) { // movzxb | |
| 1875 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); | |
| 1876 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true); | |
| 1877 emit_byte(0x0F); | |
| 1878 emit_byte(0xB6); | |
| 1879 emit_byte(0xC0 | encode); | |
| 1880 } | |
| 1881 | |
| 1882 void Assembler::movzwl(Register dst, Address src) { // movzxw | |
| 1883 InstructionMark im(this); | |
| 1884 prefix(src, dst); | |
| 1885 emit_byte(0x0F); | |
| 1886 emit_byte(0xB7); | |
| 1887 emit_operand(dst, src); | |
| 1888 } | |
| 1889 | |
| 1890 void Assembler::movzwl(Register dst, Register src) { // movzxw | |
| 1891 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1892 emit_byte(0x0F); | |
| 1893 emit_byte(0xB7); | |
| 1894 emit_byte(0xC0 | encode); | |
| 1895 } | |
| 1896 | |
| 1897 void Assembler::mull(Address src) { | |
| 1898 InstructionMark im(this); | |
| 1899 prefix(src); | |
| 1900 emit_byte(0xF7); | |
| 1901 emit_operand(rsp, src); | |
| 1902 } | |
| 1903 | |
| 1904 void Assembler::mull(Register src) { | |
| 1905 int encode = prefix_and_encode(src->encoding()); | |
| 1906 emit_byte(0xF7); | |
| 1907 emit_byte(0xE0 | encode); | |
| 1908 } | |
| 1909 | |
| 1910 void Assembler::mulsd(XMMRegister dst, Address src) { | |
| 1911 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1912 InstructionMark im(this); | |
| 1913 emit_byte(0xF2); | |
| 1914 prefix(src, dst); | |
| 1915 emit_byte(0x0F); | |
| 1916 emit_byte(0x59); | |
| 1917 emit_operand(dst, src); | |
| 1918 } | |
| 1919 | |
| 1920 void Assembler::mulsd(XMMRegister dst, XMMRegister src) { | |
| 1921 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 1922 emit_byte(0xF2); | |
| 1923 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1924 emit_byte(0x0F); | |
| 1925 emit_byte(0x59); | |
| 1926 emit_byte(0xC0 | encode); | |
| 1927 } | |
| 1928 | |
| 1929 void Assembler::mulss(XMMRegister dst, Address src) { | |
| 1930 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1931 InstructionMark im(this); | |
| 1932 emit_byte(0xF3); | |
| 1933 prefix(src, dst); | |
| 1934 emit_byte(0x0F); | |
| 1935 emit_byte(0x59); | |
| 1936 emit_operand(dst, src); | |
| 1937 } | |
| 1938 | |
| 1939 void Assembler::mulss(XMMRegister dst, XMMRegister src) { | |
| 1940 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 1941 emit_byte(0xF3); | |
| 1942 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 1943 emit_byte(0x0F); | |
| 1944 emit_byte(0x59); | |
| 1945 emit_byte(0xC0 | encode); | |
| 1946 } | |
| 1947 | |
| 1948 void Assembler::negl(Register dst) { | |
| 1949 int encode = prefix_and_encode(dst->encoding()); | |
| 1950 emit_byte(0xF7); | |
| 1951 emit_byte(0xD8 | encode); | |
| 1952 } | |
| 1953 | |
| 0 | 1954 void Assembler::nop(int i) { |
| 304 | 1955 #ifdef ASSERT |
| 0 | 1956 assert(i > 0, " "); |
| 304 | 1957 // The fancy nops aren't currently recognized by debuggers making it a |
| 1958 // pain to disassemble code while debugging. If asserts are on clearly | |
| 1959 // speed is not an issue so simply use the single byte traditional nop | |
| 1960 // to do alignment. | |
| 1961 | |
| 1962 for (; i > 0 ; i--) emit_byte(0x90); | |
| 1963 return; | |
| 1964 | |
| 1965 #endif // ASSERT | |
| 1966 | |
| 0 | 1967 if (UseAddressNop && VM_Version::is_intel()) { |
| 1968 // | |
| 1969 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel | |
| 1970 // 1: 0x90 | |
| 1971 // 2: 0x66 0x90 | |
| 1972 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) | |
| 1973 // 4: 0x0F 0x1F 0x40 0x00 | |
| 1974 // 5: 0x0F 0x1F 0x44 0x00 0x00 | |
| 1975 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
| 1976 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
| 1977 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 1978 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 1979 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 1980 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 1981 | |
| 1982 // The rest coding is Intel specific - don't use consecutive address nops | |
| 1983 | |
| 1984 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
| 1985 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
| 1986 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
| 1987 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
| 1988 | |
| 1989 while(i >= 15) { | |
| 1990 // For Intel don't generate consecutive addess nops (mix with regular nops) | |
| 1991 i -= 15; | |
| 1992 emit_byte(0x66); // size prefix | |
| 1993 emit_byte(0x66); // size prefix | |
| 1994 emit_byte(0x66); // size prefix | |
| 1995 addr_nop_8(); | |
| 1996 emit_byte(0x66); // size prefix | |
| 1997 emit_byte(0x66); // size prefix | |
| 1998 emit_byte(0x66); // size prefix | |
| 1999 emit_byte(0x90); // nop | |
| 2000 } | |
| 2001 switch (i) { | |
| 2002 case 14: | |
| 2003 emit_byte(0x66); // size prefix | |
| 2004 case 13: | |
| 2005 emit_byte(0x66); // size prefix | |
| 2006 case 12: | |
| 2007 addr_nop_8(); | |
| 2008 emit_byte(0x66); // size prefix | |
| 2009 emit_byte(0x66); // size prefix | |
| 2010 emit_byte(0x66); // size prefix | |
| 2011 emit_byte(0x90); // nop | |
| 2012 break; | |
| 2013 case 11: | |
| 2014 emit_byte(0x66); // size prefix | |
| 2015 case 10: | |
| 2016 emit_byte(0x66); // size prefix | |
| 2017 case 9: | |
| 2018 emit_byte(0x66); // size prefix | |
| 2019 case 8: | |
| 2020 addr_nop_8(); | |
| 2021 break; | |
| 2022 case 7: | |
| 2023 addr_nop_7(); | |
| 2024 break; | |
| 2025 case 6: | |
| 2026 emit_byte(0x66); // size prefix | |
| 2027 case 5: | |
| 2028 addr_nop_5(); | |
| 2029 break; | |
| 2030 case 4: | |
| 2031 addr_nop_4(); | |
| 2032 break; | |
| 2033 case 3: | |
| 2034 // Don't use "0x0F 0x1F 0x00" - need patching safe padding | |
| 2035 emit_byte(0x66); // size prefix | |
| 2036 case 2: | |
| 2037 emit_byte(0x66); // size prefix | |
| 2038 case 1: | |
| 2039 emit_byte(0x90); // nop | |
| 2040 break; | |
| 2041 default: | |
| 2042 assert(i == 0, " "); | |
| 2043 } | |
| 2044 return; | |
| 2045 } | |
| 2046 if (UseAddressNop && VM_Version::is_amd()) { | |
| 2047 // | |
| 2048 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD. | |
| 2049 // 1: 0x90 | |
| 2050 // 2: 0x66 0x90 | |
| 2051 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) | |
| 2052 // 4: 0x0F 0x1F 0x40 0x00 | |
| 2053 // 5: 0x0F 0x1F 0x44 0x00 0x00 | |
| 2054 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
| 2055 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
| 2056 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2057 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2058 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2059 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2060 | |
| 2061 // The rest coding is AMD specific - use consecutive address nops | |
| 2062 | |
| 2063 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
| 2064 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
| 2065 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
| 2066 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
| 2067 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
| 2068 // Size prefixes (0x66) are added for larger sizes | |
| 2069 | |
| 2070 while(i >= 22) { | |
| 2071 i -= 11; | |
| 2072 emit_byte(0x66); // size prefix | |
| 2073 emit_byte(0x66); // size prefix | |
| 2074 emit_byte(0x66); // size prefix | |
| 2075 addr_nop_8(); | |
| 2076 } | |
| 2077 // Generate first nop for size between 21-12 | |
| 2078 switch (i) { | |
| 2079 case 21: | |
| 2080 i -= 1; | |
| 2081 emit_byte(0x66); // size prefix | |
| 2082 case 20: | |
| 2083 case 19: | |
| 2084 i -= 1; | |
| 2085 emit_byte(0x66); // size prefix | |
| 2086 case 18: | |
| 2087 case 17: | |
| 2088 i -= 1; | |
| 2089 emit_byte(0x66); // size prefix | |
| 2090 case 16: | |
| 2091 case 15: | |
| 2092 i -= 8; | |
| 2093 addr_nop_8(); | |
| 2094 break; | |
| 2095 case 14: | |
| 2096 case 13: | |
| 2097 i -= 7; | |
| 2098 addr_nop_7(); | |
| 2099 break; | |
| 2100 case 12: | |
| 2101 i -= 6; | |
| 2102 emit_byte(0x66); // size prefix | |
| 2103 addr_nop_5(); | |
| 2104 break; | |
| 2105 default: | |
| 2106 assert(i < 12, " "); | |
| 2107 } | |
| 2108 | |
| 2109 // Generate second nop for size between 11-1 | |
| 2110 switch (i) { | |
| 2111 case 11: | |
| 2112 emit_byte(0x66); // size prefix | |
| 2113 case 10: | |
| 2114 emit_byte(0x66); // size prefix | |
| 2115 case 9: | |
| 2116 emit_byte(0x66); // size prefix | |
| 2117 case 8: | |
| 2118 addr_nop_8(); | |
| 2119 break; | |
| 2120 case 7: | |
| 2121 addr_nop_7(); | |
| 2122 break; | |
| 2123 case 6: | |
| 2124 emit_byte(0x66); // size prefix | |
| 2125 case 5: | |
| 2126 addr_nop_5(); | |
| 2127 break; | |
| 2128 case 4: | |
| 2129 addr_nop_4(); | |
| 2130 break; | |
| 2131 case 3: | |
| 2132 // Don't use "0x0F 0x1F 0x00" - need patching safe padding | |
| 2133 emit_byte(0x66); // size prefix | |
| 2134 case 2: | |
| 2135 emit_byte(0x66); // size prefix | |
| 2136 case 1: | |
| 2137 emit_byte(0x90); // nop | |
| 2138 break; | |
| 2139 default: | |
| 2140 assert(i == 0, " "); | |
| 2141 } | |
| 2142 return; | |
| 2143 } | |
| 2144 | |
| 2145 // Using nops with size prefixes "0x66 0x90". | |
| 2146 // From AMD Optimization Guide: | |
| 2147 // 1: 0x90 | |
| 2148 // 2: 0x66 0x90 | |
| 2149 // 3: 0x66 0x66 0x90 | |
| 2150 // 4: 0x66 0x66 0x66 0x90 | |
| 2151 // 5: 0x66 0x66 0x90 0x66 0x90 | |
| 2152 // 6: 0x66 0x66 0x90 0x66 0x66 0x90 | |
| 2153 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 | |
| 2154 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90 | |
| 2155 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 | |
| 2156 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 | |
| 2157 // | |
| 2158 while(i > 12) { | |
| 2159 i -= 4; | |
| 2160 emit_byte(0x66); // size prefix | |
| 2161 emit_byte(0x66); | |
| 2162 emit_byte(0x66); | |
| 2163 emit_byte(0x90); // nop | |
| 2164 } | |
| 2165 // 1 - 12 nops | |
| 2166 if(i > 8) { | |
| 2167 if(i > 9) { | |
| 2168 i -= 1; | |
| 2169 emit_byte(0x66); | |
| 2170 } | |
| 2171 i -= 3; | |
| 2172 emit_byte(0x66); | |
| 2173 emit_byte(0x66); | |
| 2174 emit_byte(0x90); | |
| 2175 } | |
| 2176 // 1 - 8 nops | |
| 2177 if(i > 4) { | |
| 2178 if(i > 6) { | |
| 2179 i -= 1; | |
| 2180 emit_byte(0x66); | |
| 2181 } | |
| 2182 i -= 3; | |
| 2183 emit_byte(0x66); | |
| 2184 emit_byte(0x66); | |
| 2185 emit_byte(0x90); | |
| 2186 } | |
| 2187 switch (i) { | |
| 2188 case 4: | |
| 2189 emit_byte(0x66); | |
| 2190 case 3: | |
| 2191 emit_byte(0x66); | |
| 2192 case 2: | |
| 2193 emit_byte(0x66); | |
| 2194 case 1: | |
| 2195 emit_byte(0x90); | |
| 2196 break; | |
| 2197 default: | |
| 2198 assert(i == 0, " "); | |
| 2199 } | |
| 2200 } | |
| 2201 | |
| 304 | 2202 void Assembler::notl(Register dst) { |
| 2203 int encode = prefix_and_encode(dst->encoding()); | |
| 2204 emit_byte(0xF7); | |
| 2205 emit_byte(0xD0 | encode ); | |
| 2206 } | |
| 2207 | |
| 2208 void Assembler::orl(Address dst, int32_t imm32) { | |
| 2209 InstructionMark im(this); | |
| 2210 prefix(dst); | |
|
2100
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2211 emit_arith_operand(0x81, rcx, dst, imm32); |
| 304 | 2212 } |
| 2213 | |
| 2214 void Assembler::orl(Register dst, int32_t imm32) { | |
| 2215 prefix(dst); | |
| 2216 emit_arith(0x81, 0xC8, dst, imm32); | |
| 2217 } | |
| 2218 | |
| 2219 void Assembler::orl(Register dst, Address src) { | |
| 2220 InstructionMark im(this); | |
| 2221 prefix(src, dst); | |
| 2222 emit_byte(0x0B); | |
| 2223 emit_operand(dst, src); | |
| 2224 } | |
| 2225 | |
| 2226 void Assembler::orl(Register dst, Register src) { | |
| 2227 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2228 emit_arith(0x0B, 0xC0, dst, src); | |
| 2229 } | |
| 2230 | |
| 681 | 2231 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) { |
| 2232 assert(VM_Version::supports_sse4_2(), ""); | |
| 2233 | |
| 2234 InstructionMark im(this); | |
| 2235 emit_byte(0x66); | |
| 2236 prefix(src, dst); | |
| 2237 emit_byte(0x0F); | |
| 2238 emit_byte(0x3A); | |
| 2239 emit_byte(0x61); | |
| 2240 emit_operand(dst, src); | |
| 2241 emit_byte(imm8); | |
| 2242 } | |
| 2243 | |
| 2244 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { | |
| 2245 assert(VM_Version::supports_sse4_2(), ""); | |
| 2246 | |
| 2247 emit_byte(0x66); | |
| 2248 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 2249 emit_byte(0x0F); | |
| 2250 emit_byte(0x3A); | |
| 2251 emit_byte(0x61); | |
| 2252 emit_byte(0xC0 | encode); | |
| 2253 emit_byte(imm8); | |
| 2254 } | |
| 2255 | |
| 304 | 2256 // generic |
| 2257 void Assembler::pop(Register dst) { | |
| 2258 int encode = prefix_and_encode(dst->encoding()); | |
| 2259 emit_byte(0x58 | encode); | |
| 2260 } | |
| 2261 | |
|
643
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2262 void Assembler::popcntl(Register dst, Address src) { |
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2263 assert(VM_Version::supports_popcnt(), "must support"); |
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2264 InstructionMark im(this); |
|
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2265 emit_byte(0xF3); |
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2266 prefix(src, dst); |
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2267 emit_byte(0x0F); |
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2268 emit_byte(0xB8); |
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2269 emit_operand(dst, src); |
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2270 } |
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2271 |
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2272 void Assembler::popcntl(Register dst, Register src) { |
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2273 assert(VM_Version::supports_popcnt(), "must support"); |
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2274 emit_byte(0xF3); |
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2275 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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2276 emit_byte(0x0F); |
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2277 emit_byte(0xB8); |
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2278 emit_byte(0xC0 | encode); |
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2279 } |
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2280 |
| 304 | 2281 void Assembler::popf() { |
| 2282 emit_byte(0x9D); | |
| 2283 } | |
| 2284 | |
| 1060 | 2285 #ifndef _LP64 // no 32bit push/pop on amd64 |
| 304 | 2286 void Assembler::popl(Address dst) { |
| 2287 // NOTE: this will adjust stack by 8byte on 64bits | |
| 2288 InstructionMark im(this); | |
| 2289 prefix(dst); | |
| 2290 emit_byte(0x8F); | |
| 2291 emit_operand(rax, dst); | |
| 2292 } | |
| 1060 | 2293 #endif |
| 304 | 2294 |
| 2295 void Assembler::prefetch_prefix(Address src) { | |
| 2296 prefix(src); | |
| 2297 emit_byte(0x0F); | |
| 2298 } | |
| 2299 | |
| 2300 void Assembler::prefetchnta(Address src) { | |
| 2301 NOT_LP64(assert(VM_Version::supports_sse2(), "must support")); | |
| 2302 InstructionMark im(this); | |
| 2303 prefetch_prefix(src); | |
| 2304 emit_byte(0x18); | |
| 2305 emit_operand(rax, src); // 0, src | |
| 2306 } | |
| 2307 | |
| 2308 void Assembler::prefetchr(Address src) { | |
| 2309 NOT_LP64(assert(VM_Version::supports_3dnow(), "must support")); | |
| 2310 InstructionMark im(this); | |
| 2311 prefetch_prefix(src); | |
| 2312 emit_byte(0x0D); | |
| 2313 emit_operand(rax, src); // 0, src | |
| 2314 } | |
| 2315 | |
| 2316 void Assembler::prefetcht0(Address src) { | |
| 2317 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
| 2318 InstructionMark im(this); | |
| 2319 prefetch_prefix(src); | |
| 2320 emit_byte(0x18); | |
| 2321 emit_operand(rcx, src); // 1, src | |
| 2322 } | |
| 2323 | |
| 2324 void Assembler::prefetcht1(Address src) { | |
| 2325 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
| 2326 InstructionMark im(this); | |
| 2327 prefetch_prefix(src); | |
| 2328 emit_byte(0x18); | |
| 2329 emit_operand(rdx, src); // 2, src | |
| 2330 } | |
| 2331 | |
| 2332 void Assembler::prefetcht2(Address src) { | |
| 2333 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
| 2334 InstructionMark im(this); | |
| 2335 prefetch_prefix(src); | |
| 2336 emit_byte(0x18); | |
| 2337 emit_operand(rbx, src); // 3, src | |
| 2338 } | |
| 2339 | |
| 2340 void Assembler::prefetchw(Address src) { | |
| 2341 NOT_LP64(assert(VM_Version::supports_3dnow(), "must support")); | |
| 2342 InstructionMark im(this); | |
| 2343 prefetch_prefix(src); | |
| 2344 emit_byte(0x0D); | |
| 2345 emit_operand(rcx, src); // 1, src | |
| 2346 } | |
| 2347 | |
| 2348 void Assembler::prefix(Prefix p) { | |
| 2349 a_byte(p); | |
| 2350 } | |
| 2351 | |
| 2262 | 2352 void Assembler::por(XMMRegister dst, XMMRegister src) { |
| 2353 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2354 | |
| 2355 emit_byte(0x66); | |
| 2356 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2357 emit_byte(0x0F); | |
| 2358 | |
| 2359 emit_byte(0xEB); | |
| 2360 emit_byte(0xC0 | encode); | |
| 2361 } | |
| 2362 | |
| 304 | 2363 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) { |
| 2364 assert(isByte(mode), "invalid value"); | |
| 2365 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2366 | |
| 2367 emit_byte(0x66); | |
| 2368 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2369 emit_byte(0x0F); | |
| 2370 emit_byte(0x70); | |
| 2371 emit_byte(0xC0 | encode); | |
| 2372 emit_byte(mode & 0xFF); | |
| 2373 | |
| 2374 } | |
| 2375 | |
| 2376 void Assembler::pshufd(XMMRegister dst, Address src, int mode) { | |
| 2377 assert(isByte(mode), "invalid value"); | |
| 2378 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2379 | |
| 2380 InstructionMark im(this); | |
| 2381 emit_byte(0x66); | |
| 2382 prefix(src, dst); | |
| 2383 emit_byte(0x0F); | |
| 2384 emit_byte(0x70); | |
| 2385 emit_operand(dst, src); | |
| 2386 emit_byte(mode & 0xFF); | |
| 2387 } | |
| 2388 | |
| 2389 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { | |
| 2390 assert(isByte(mode), "invalid value"); | |
| 2391 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2392 | |
| 2393 emit_byte(0xF2); | |
| 2394 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2395 emit_byte(0x0F); | |
| 2396 emit_byte(0x70); | |
| 2397 emit_byte(0xC0 | encode); | |
| 2398 emit_byte(mode & 0xFF); | |
| 2399 } | |
| 2400 | |
| 2401 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) { | |
| 2402 assert(isByte(mode), "invalid value"); | |
| 2403 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2404 | |
| 2405 InstructionMark im(this); | |
| 2406 emit_byte(0xF2); | |
| 2407 prefix(src, dst); // QQ new | |
| 2408 emit_byte(0x0F); | |
| 2409 emit_byte(0x70); | |
| 2410 emit_operand(dst, src); | |
| 2411 emit_byte(mode & 0xFF); | |
| 2412 } | |
| 2413 | |
| 2414 void Assembler::psrlq(XMMRegister dst, int shift) { | |
| 2415 // HMM Table D-1 says sse2 or mmx | |
| 2416 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2417 | |
| 2418 int encode = prefixq_and_encode(xmm2->encoding(), dst->encoding()); | |
| 2419 emit_byte(0x66); | |
| 2420 emit_byte(0x0F); | |
| 2421 emit_byte(0x73); | |
| 2422 emit_byte(0xC0 | encode); | |
| 2423 emit_byte(shift); | |
| 2424 } | |
| 2425 | |
| 681 | 2426 void Assembler::ptest(XMMRegister dst, Address src) { |
| 2427 assert(VM_Version::supports_sse4_1(), ""); | |
| 2428 | |
| 2429 InstructionMark im(this); | |
| 2430 emit_byte(0x66); | |
| 2431 prefix(src, dst); | |
| 2432 emit_byte(0x0F); | |
| 2433 emit_byte(0x38); | |
| 2434 emit_byte(0x17); | |
| 2435 emit_operand(dst, src); | |
| 2436 } | |
| 2437 | |
| 2438 void Assembler::ptest(XMMRegister dst, XMMRegister src) { | |
| 2439 assert(VM_Version::supports_sse4_1(), ""); | |
| 2440 | |
| 2441 emit_byte(0x66); | |
| 2442 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 2443 emit_byte(0x0F); | |
| 2444 emit_byte(0x38); | |
| 2445 emit_byte(0x17); | |
| 2446 emit_byte(0xC0 | encode); | |
| 2447 } | |
| 2448 | |
| 304 | 2449 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) { |
| 2450 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2451 emit_byte(0x66); | |
| 2452 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2453 emit_byte(0x0F); | |
| 2454 emit_byte(0x60); | |
| 2455 emit_byte(0xC0 | encode); | |
| 2456 } | |
| 2457 | |
| 2458 void Assembler::push(int32_t imm32) { | |
| 2459 // in 64bits we push 64bits onto the stack but only | |
| 2460 // take a 32bit immediate | |
| 2461 emit_byte(0x68); | |
| 2462 emit_long(imm32); | |
| 2463 } | |
| 2464 | |
| 2465 void Assembler::push(Register src) { | |
| 2466 int encode = prefix_and_encode(src->encoding()); | |
| 2467 | |
| 2468 emit_byte(0x50 | encode); | |
| 2469 } | |
| 2470 | |
| 2471 void Assembler::pushf() { | |
| 2472 emit_byte(0x9C); | |
| 2473 } | |
| 2474 | |
| 1060 | 2475 #ifndef _LP64 // no 32bit push/pop on amd64 |
| 304 | 2476 void Assembler::pushl(Address src) { |
| 2477 // Note this will push 64bit on 64bit | |
| 2478 InstructionMark im(this); | |
| 2479 prefix(src); | |
| 2480 emit_byte(0xFF); | |
| 2481 emit_operand(rsi, src); | |
| 2482 } | |
| 1060 | 2483 #endif |
| 304 | 2484 |
| 2485 void Assembler::pxor(XMMRegister dst, Address src) { | |
| 2486 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2487 InstructionMark im(this); | |
| 2488 emit_byte(0x66); | |
| 2489 prefix(src, dst); | |
| 2490 emit_byte(0x0F); | |
| 2491 emit_byte(0xEF); | |
| 2492 emit_operand(dst, src); | |
| 2493 } | |
| 2494 | |
| 2495 void Assembler::pxor(XMMRegister dst, XMMRegister src) { | |
| 2496 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2497 InstructionMark im(this); | |
| 2498 emit_byte(0x66); | |
| 2499 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2500 emit_byte(0x0F); | |
| 2501 emit_byte(0xEF); | |
| 2502 emit_byte(0xC0 | encode); | |
| 2503 } | |
| 2504 | |
| 2505 void Assembler::rcll(Register dst, int imm8) { | |
| 2506 assert(isShiftCount(imm8), "illegal shift count"); | |
| 2507 int encode = prefix_and_encode(dst->encoding()); | |
| 2508 if (imm8 == 1) { | |
| 2509 emit_byte(0xD1); | |
| 2510 emit_byte(0xD0 | encode); | |
| 2511 } else { | |
| 2512 emit_byte(0xC1); | |
| 2513 emit_byte(0xD0 | encode); | |
| 2514 emit_byte(imm8); | |
| 2515 } | |
| 2516 } | |
| 2517 | |
| 2518 // copies data from [esi] to [edi] using rcx pointer sized words | |
| 2519 // generic | |
| 2520 void Assembler::rep_mov() { | |
| 2521 emit_byte(0xF3); | |
| 2522 // MOVSQ | |
| 2523 LP64_ONLY(prefix(REX_W)); | |
| 2524 emit_byte(0xA5); | |
| 2525 } | |
| 2526 | |
| 2527 // sets rcx pointer sized words with rax, value at [edi] | |
| 2528 // generic | |
| 2529 void Assembler::rep_set() { // rep_set | |
| 2530 emit_byte(0xF3); | |
| 2531 // STOSQ | |
| 2532 LP64_ONLY(prefix(REX_W)); | |
| 2533 emit_byte(0xAB); | |
| 2534 } | |
| 2535 | |
| 2536 // scans rcx pointer sized words at [edi] for occurance of rax, | |
| 2537 // generic | |
| 2538 void Assembler::repne_scan() { // repne_scan | |
| 2539 emit_byte(0xF2); | |
| 2540 // SCASQ | |
| 2541 LP64_ONLY(prefix(REX_W)); | |
| 2542 emit_byte(0xAF); | |
| 2543 } | |
| 2544 | |
| 2545 #ifdef _LP64 | |
| 2546 // scans rcx 4 byte words at [edi] for occurance of rax, | |
| 2547 // generic | |
| 2548 void Assembler::repne_scanl() { // repne_scan | |
| 2549 emit_byte(0xF2); | |
| 2550 // SCASL | |
| 2551 emit_byte(0xAF); | |
| 2552 } | |
| 2553 #endif | |
| 2554 | |
| 0 | 2555 void Assembler::ret(int imm16) { |
| 2556 if (imm16 == 0) { | |
| 2557 emit_byte(0xC3); | |
| 2558 } else { | |
| 2559 emit_byte(0xC2); | |
| 2560 emit_word(imm16); | |
| 2561 } | |
| 2562 } | |
| 2563 | |
| 304 | 2564 void Assembler::sahf() { |
| 2565 #ifdef _LP64 | |
| 2566 // Not supported in 64bit mode | |
| 2567 ShouldNotReachHere(); | |
| 2568 #endif | |
| 2569 emit_byte(0x9E); | |
| 2570 } | |
| 2571 | |
| 2572 void Assembler::sarl(Register dst, int imm8) { | |
| 2573 int encode = prefix_and_encode(dst->encoding()); | |
| 2574 assert(isShiftCount(imm8), "illegal shift count"); | |
| 2575 if (imm8 == 1) { | |
| 2576 emit_byte(0xD1); | |
| 2577 emit_byte(0xF8 | encode); | |
| 2578 } else { | |
| 2579 emit_byte(0xC1); | |
| 2580 emit_byte(0xF8 | encode); | |
| 2581 emit_byte(imm8); | |
| 2582 } | |
| 2583 } | |
| 2584 | |
| 2585 void Assembler::sarl(Register dst) { | |
| 2586 int encode = prefix_and_encode(dst->encoding()); | |
| 2587 emit_byte(0xD3); | |
| 2588 emit_byte(0xF8 | encode); | |
| 2589 } | |
| 2590 | |
| 2591 void Assembler::sbbl(Address dst, int32_t imm32) { | |
| 2592 InstructionMark im(this); | |
| 2593 prefix(dst); | |
| 2594 emit_arith_operand(0x81, rbx, dst, imm32); | |
| 2595 } | |
| 2596 | |
| 2597 void Assembler::sbbl(Register dst, int32_t imm32) { | |
| 2598 prefix(dst); | |
| 2599 emit_arith(0x81, 0xD8, dst, imm32); | |
| 2600 } | |
| 2601 | |
| 2602 | |
| 2603 void Assembler::sbbl(Register dst, Address src) { | |
| 2604 InstructionMark im(this); | |
| 2605 prefix(src, dst); | |
| 2606 emit_byte(0x1B); | |
| 2607 emit_operand(dst, src); | |
| 2608 } | |
| 2609 | |
| 2610 void Assembler::sbbl(Register dst, Register src) { | |
| 2611 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2612 emit_arith(0x1B, 0xC0, dst, src); | |
| 2613 } | |
| 2614 | |
| 2615 void Assembler::setb(Condition cc, Register dst) { | |
| 2616 assert(0 <= cc && cc < 16, "illegal cc"); | |
| 2617 int encode = prefix_and_encode(dst->encoding(), true); | |
| 0 | 2618 emit_byte(0x0F); |
| 304 | 2619 emit_byte(0x90 | cc); |
| 2620 emit_byte(0xC0 | encode); | |
| 2621 } | |
| 2622 | |
| 2623 void Assembler::shll(Register dst, int imm8) { | |
| 2624 assert(isShiftCount(imm8), "illegal shift count"); | |
| 2625 int encode = prefix_and_encode(dst->encoding()); | |
| 2626 if (imm8 == 1 ) { | |
| 2627 emit_byte(0xD1); | |
| 2628 emit_byte(0xE0 | encode); | |
| 2629 } else { | |
| 2630 emit_byte(0xC1); | |
| 2631 emit_byte(0xE0 | encode); | |
| 2632 emit_byte(imm8); | |
| 2633 } | |
| 2634 } | |
| 2635 | |
| 2636 void Assembler::shll(Register dst) { | |
| 2637 int encode = prefix_and_encode(dst->encoding()); | |
| 2638 emit_byte(0xD3); | |
| 2639 emit_byte(0xE0 | encode); | |
| 2640 } | |
| 2641 | |
| 2642 void Assembler::shrl(Register dst, int imm8) { | |
| 2643 assert(isShiftCount(imm8), "illegal shift count"); | |
| 2644 int encode = prefix_and_encode(dst->encoding()); | |
| 2645 emit_byte(0xC1); | |
| 2646 emit_byte(0xE8 | encode); | |
| 2647 emit_byte(imm8); | |
| 2648 } | |
| 2649 | |
| 2650 void Assembler::shrl(Register dst) { | |
| 2651 int encode = prefix_and_encode(dst->encoding()); | |
| 2652 emit_byte(0xD3); | |
| 2653 emit_byte(0xE8 | encode); | |
| 2654 } | |
| 0 | 2655 |
| 2656 // copies a single word from [esi] to [edi] | |
| 2657 void Assembler::smovl() { | |
| 2658 emit_byte(0xA5); | |
| 2659 } | |
| 2660 | |
| 304 | 2661 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { |
| 2662 // HMM Table D-1 says sse2 | |
| 2663 // NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2664 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2665 emit_byte(0xF2); | |
| 2666 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2667 emit_byte(0x0F); | |
| 2668 emit_byte(0x51); | |
| 2669 emit_byte(0xC0 | encode); | |
| 2670 } | |
| 2671 | |
| 2008 | 2672 void Assembler::sqrtsd(XMMRegister dst, Address src) { |
| 2673 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2674 InstructionMark im(this); | |
| 2675 emit_byte(0xF2); | |
| 2676 prefix(src, dst); | |
| 2677 emit_byte(0x0F); | |
| 2678 emit_byte(0x51); | |
| 2679 emit_operand(dst, src); | |
| 2680 } | |
| 2681 | |
| 2682 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) { | |
| 2683 // HMM Table D-1 says sse2 | |
| 2684 // NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2685 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2686 emit_byte(0xF3); | |
| 2687 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2688 emit_byte(0x0F); | |
| 2689 emit_byte(0x51); | |
| 2690 emit_byte(0xC0 | encode); | |
| 2691 } | |
| 2692 | |
| 2693 void Assembler::sqrtss(XMMRegister dst, Address src) { | |
| 2694 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2695 InstructionMark im(this); | |
| 2696 emit_byte(0xF3); | |
| 2697 prefix(src, dst); | |
| 2698 emit_byte(0x0F); | |
| 2699 emit_byte(0x51); | |
| 2700 emit_operand(dst, src); | |
| 2701 } | |
| 2702 | |
| 304 | 2703 void Assembler::stmxcsr( Address dst) { |
| 2704 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2705 InstructionMark im(this); | |
| 2706 prefix(dst); | |
| 2707 emit_byte(0x0F); | |
| 2708 emit_byte(0xAE); | |
| 2709 emit_operand(as_Register(3), dst); | |
| 2710 } | |
| 2711 | |
| 2712 void Assembler::subl(Address dst, int32_t imm32) { | |
| 2713 InstructionMark im(this); | |
| 2714 prefix(dst); | |
|
2100
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
2715 emit_arith_operand(0x81, rbp, dst, imm32); |
| 304 | 2716 } |
| 2717 | |
| 2718 void Assembler::subl(Address dst, Register src) { | |
| 2719 InstructionMark im(this); | |
| 2720 prefix(dst, src); | |
| 2721 emit_byte(0x29); | |
| 2722 emit_operand(src, dst); | |
| 2723 } | |
| 2724 | |
|
2100
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
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2014
diff
changeset
|
2725 void Assembler::subl(Register dst, int32_t imm32) { |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
2726 prefix(dst); |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
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diff
changeset
|
2727 emit_arith(0x81, 0xE8, dst, imm32); |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
2728 } |
|
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7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
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parents:
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diff
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|
2729 |
| 304 | 2730 void Assembler::subl(Register dst, Address src) { |
| 2731 InstructionMark im(this); | |
| 2732 prefix(src, dst); | |
| 2733 emit_byte(0x2B); | |
| 2734 emit_operand(dst, src); | |
| 2735 } | |
| 2736 | |
| 2737 void Assembler::subl(Register dst, Register src) { | |
| 2738 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2739 emit_arith(0x2B, 0xC0, dst, src); | |
| 2740 } | |
| 2741 | |
| 2742 void Assembler::subsd(XMMRegister dst, XMMRegister src) { | |
| 2743 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2744 emit_byte(0xF2); | |
| 2745 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2746 emit_byte(0x0F); | |
| 2747 emit_byte(0x5C); | |
| 2748 emit_byte(0xC0 | encode); | |
| 2749 } | |
| 2750 | |
| 2751 void Assembler::subsd(XMMRegister dst, Address src) { | |
| 2752 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2753 InstructionMark im(this); | |
| 2754 emit_byte(0xF2); | |
| 2755 prefix(src, dst); | |
| 2756 emit_byte(0x0F); | |
| 2757 emit_byte(0x5C); | |
| 2758 emit_operand(dst, src); | |
| 2759 } | |
| 2760 | |
| 2761 void Assembler::subss(XMMRegister dst, XMMRegister src) { | |
| 2762 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 0 | 2763 emit_byte(0xF3); |
| 304 | 2764 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
| 2765 emit_byte(0x0F); | |
| 2766 emit_byte(0x5C); | |
| 2767 emit_byte(0xC0 | encode); | |
| 2768 } | |
| 2769 | |
| 2770 void Assembler::subss(XMMRegister dst, Address src) { | |
| 2771 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2772 InstructionMark im(this); | |
| 2773 emit_byte(0xF3); | |
| 2774 prefix(src, dst); | |
| 2775 emit_byte(0x0F); | |
| 2776 emit_byte(0x5C); | |
| 2777 emit_operand(dst, src); | |
| 2778 } | |
| 2779 | |
| 2780 void Assembler::testb(Register dst, int imm8) { | |
| 2781 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); | |
| 2782 (void) prefix_and_encode(dst->encoding(), true); | |
| 2783 emit_arith_b(0xF6, 0xC0, dst, imm8); | |
| 2784 } | |
| 2785 | |
| 2786 void Assembler::testl(Register dst, int32_t imm32) { | |
| 2787 // not using emit_arith because test | |
| 2788 // doesn't support sign-extension of | |
| 2789 // 8bit operands | |
| 2790 int encode = dst->encoding(); | |
| 2791 if (encode == 0) { | |
| 2792 emit_byte(0xA9); | |
| 2793 } else { | |
| 2794 encode = prefix_and_encode(encode); | |
| 2795 emit_byte(0xF7); | |
| 2796 emit_byte(0xC0 | encode); | |
| 2797 } | |
| 2798 emit_long(imm32); | |
| 2799 } | |
| 2800 | |
| 2801 void Assembler::testl(Register dst, Register src) { | |
| 2802 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2803 emit_arith(0x85, 0xC0, dst, src); | |
| 2804 } | |
| 2805 | |
| 2806 void Assembler::testl(Register dst, Address src) { | |
| 2807 InstructionMark im(this); | |
| 2808 prefix(src, dst); | |
| 2809 emit_byte(0x85); | |
| 2810 emit_operand(dst, src); | |
| 2811 } | |
| 2812 | |
| 2813 void Assembler::ucomisd(XMMRegister dst, Address src) { | |
| 2814 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2815 emit_byte(0x66); | |
| 2816 ucomiss(dst, src); | |
| 2817 } | |
| 2818 | |
| 2819 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) { | |
| 2820 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2821 emit_byte(0x66); | |
| 2822 ucomiss(dst, src); | |
| 2823 } | |
| 2824 | |
| 2825 void Assembler::ucomiss(XMMRegister dst, Address src) { | |
| 2826 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2827 | |
| 2828 InstructionMark im(this); | |
| 2829 prefix(src, dst); | |
| 2830 emit_byte(0x0F); | |
| 2831 emit_byte(0x2E); | |
| 2832 emit_operand(dst, src); | |
| 2833 } | |
| 2834 | |
| 2835 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) { | |
| 2836 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2837 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2838 emit_byte(0x0F); | |
| 2839 emit_byte(0x2E); | |
| 2840 emit_byte(0xC0 | encode); | |
| 2841 } | |
| 2842 | |
| 2843 | |
| 2844 void Assembler::xaddl(Address dst, Register src) { | |
| 2845 InstructionMark im(this); | |
| 2846 prefix(dst, src); | |
| 0 | 2847 emit_byte(0x0F); |
| 304 | 2848 emit_byte(0xC1); |
| 2849 emit_operand(src, dst); | |
| 2850 } | |
| 2851 | |
| 2852 void Assembler::xchgl(Register dst, Address src) { // xchg | |
| 2853 InstructionMark im(this); | |
| 2854 prefix(src, dst); | |
| 2855 emit_byte(0x87); | |
| 2856 emit_operand(dst, src); | |
| 2857 } | |
| 2858 | |
| 2859 void Assembler::xchgl(Register dst, Register src) { | |
| 2860 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2861 emit_byte(0x87); | |
| 2862 emit_byte(0xc0 | encode); | |
| 2863 } | |
| 2864 | |
| 2865 void Assembler::xorl(Register dst, int32_t imm32) { | |
| 2866 prefix(dst); | |
| 2867 emit_arith(0x81, 0xF0, dst, imm32); | |
| 2868 } | |
| 2869 | |
| 2870 void Assembler::xorl(Register dst, Address src) { | |
| 2871 InstructionMark im(this); | |
| 2872 prefix(src, dst); | |
| 2873 emit_byte(0x33); | |
| 2874 emit_operand(dst, src); | |
| 2875 } | |
| 2876 | |
| 2877 void Assembler::xorl(Register dst, Register src) { | |
| 2878 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2879 emit_arith(0x33, 0xC0, dst, src); | |
| 2880 } | |
| 2881 | |
| 2882 void Assembler::xorpd(XMMRegister dst, XMMRegister src) { | |
| 2883 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2884 emit_byte(0x66); | |
| 2885 xorps(dst, src); | |
| 2886 } | |
| 2887 | |
| 2888 void Assembler::xorpd(XMMRegister dst, Address src) { | |
| 2889 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 2890 InstructionMark im(this); | |
| 2891 emit_byte(0x66); | |
| 2892 prefix(src, dst); | |
| 2893 emit_byte(0x0F); | |
| 2894 emit_byte(0x57); | |
| 2895 emit_operand(dst, src); | |
| 2896 } | |
| 2897 | |
| 2898 | |
| 2899 void Assembler::xorps(XMMRegister dst, XMMRegister src) { | |
| 2900 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2901 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
| 2902 emit_byte(0x0F); | |
| 2903 emit_byte(0x57); | |
| 2904 emit_byte(0xC0 | encode); | |
| 2905 } | |
| 2906 | |
| 2907 void Assembler::xorps(XMMRegister dst, Address src) { | |
| 2908 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 2909 InstructionMark im(this); | |
| 2910 prefix(src, dst); | |
| 2911 emit_byte(0x0F); | |
| 2912 emit_byte(0x57); | |
| 2913 emit_operand(dst, src); | |
| 2914 } | |
| 2915 | |
| 2916 #ifndef _LP64 | |
| 2917 // 32bit only pieces of the assembler | |
| 2918 | |
| 2919 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) { | |
| 2920 // NO PREFIX AS NEVER 64BIT | |
| 2921 InstructionMark im(this); | |
| 2922 emit_byte(0x81); | |
| 2923 emit_byte(0xF8 | src1->encoding()); | |
| 2924 emit_data(imm32, rspec, 0); | |
| 2925 } | |
| 2926 | |
| 2927 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) { | |
| 2928 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs | |
| 2929 InstructionMark im(this); | |
| 2930 emit_byte(0x81); | |
| 2931 emit_operand(rdi, src1); | |
| 2932 emit_data(imm32, rspec, 0); | |
| 2933 } | |
| 2934 | |
| 2935 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax, | |
| 2936 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded | |
| 2937 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise. | |
| 2938 void Assembler::cmpxchg8(Address adr) { | |
| 2939 InstructionMark im(this); | |
| 2940 emit_byte(0x0F); | |
| 2941 emit_byte(0xc7); | |
| 2942 emit_operand(rcx, adr); | |
| 2943 } | |
| 2944 | |
| 2945 void Assembler::decl(Register dst) { | |
| 2946 // Don't use it directly. Use MacroAssembler::decrementl() instead. | |
| 2947 emit_byte(0x48 | dst->encoding()); | |
| 2948 } | |
| 2949 | |
| 2950 #endif // _LP64 | |
| 2951 | |
| 2952 // 64bit typically doesn't use the x87 but needs to for the trig funcs | |
| 2953 | |
| 2954 void Assembler::fabs() { | |
| 2955 emit_byte(0xD9); | |
| 2956 emit_byte(0xE1); | |
| 2957 } | |
| 2958 | |
| 2959 void Assembler::fadd(int i) { | |
| 2960 emit_farith(0xD8, 0xC0, i); | |
| 2961 } | |
| 2962 | |
| 2963 void Assembler::fadd_d(Address src) { | |
| 2964 InstructionMark im(this); | |
| 2965 emit_byte(0xDC); | |
| 2966 emit_operand32(rax, src); | |
| 2967 } | |
| 2968 | |
| 2969 void Assembler::fadd_s(Address src) { | |
| 2970 InstructionMark im(this); | |
| 2971 emit_byte(0xD8); | |
| 2972 emit_operand32(rax, src); | |
| 2973 } | |
| 2974 | |
| 2975 void Assembler::fadda(int i) { | |
| 2976 emit_farith(0xDC, 0xC0, i); | |
| 2977 } | |
| 2978 | |
| 2979 void Assembler::faddp(int i) { | |
| 2980 emit_farith(0xDE, 0xC0, i); | |
| 2981 } | |
| 2982 | |
| 2983 void Assembler::fchs() { | |
| 2984 emit_byte(0xD9); | |
| 2985 emit_byte(0xE0); | |
| 2986 } | |
| 2987 | |
| 2988 void Assembler::fcom(int i) { | |
| 2989 emit_farith(0xD8, 0xD0, i); | |
| 2990 } | |
| 2991 | |
| 2992 void Assembler::fcomp(int i) { | |
| 2993 emit_farith(0xD8, 0xD8, i); | |
| 2994 } | |
| 2995 | |
| 2996 void Assembler::fcomp_d(Address src) { | |
| 2997 InstructionMark im(this); | |
| 2998 emit_byte(0xDC); | |
| 2999 emit_operand32(rbx, src); | |
| 3000 } | |
| 3001 | |
| 3002 void Assembler::fcomp_s(Address src) { | |
| 3003 InstructionMark im(this); | |
| 3004 emit_byte(0xD8); | |
| 3005 emit_operand32(rbx, src); | |
| 3006 } | |
| 3007 | |
| 3008 void Assembler::fcompp() { | |
| 3009 emit_byte(0xDE); | |
| 3010 emit_byte(0xD9); | |
| 3011 } | |
| 3012 | |
| 3013 void Assembler::fcos() { | |
| 3014 emit_byte(0xD9); | |
| 0 | 3015 emit_byte(0xFF); |
| 304 | 3016 } |
| 3017 | |
| 3018 void Assembler::fdecstp() { | |
| 3019 emit_byte(0xD9); | |
| 3020 emit_byte(0xF6); | |
| 3021 } | |
| 3022 | |
| 3023 void Assembler::fdiv(int i) { | |
| 3024 emit_farith(0xD8, 0xF0, i); | |
| 3025 } | |
| 3026 | |
| 3027 void Assembler::fdiv_d(Address src) { | |
| 3028 InstructionMark im(this); | |
| 3029 emit_byte(0xDC); | |
| 3030 emit_operand32(rsi, src); | |
| 3031 } | |
| 3032 | |
| 3033 void Assembler::fdiv_s(Address src) { | |
| 3034 InstructionMark im(this); | |
| 3035 emit_byte(0xD8); | |
| 3036 emit_operand32(rsi, src); | |
| 3037 } | |
| 3038 | |
| 3039 void Assembler::fdiva(int i) { | |
| 3040 emit_farith(0xDC, 0xF8, i); | |
| 3041 } | |
| 3042 | |
| 3043 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994) | |
| 3044 // is erroneous for some of the floating-point instructions below. | |
| 3045 | |
| 3046 void Assembler::fdivp(int i) { | |
| 3047 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong) | |
| 3048 } | |
| 3049 | |
| 3050 void Assembler::fdivr(int i) { | |
| 3051 emit_farith(0xD8, 0xF8, i); | |
| 3052 } | |
| 3053 | |
| 3054 void Assembler::fdivr_d(Address src) { | |
| 3055 InstructionMark im(this); | |
| 3056 emit_byte(0xDC); | |
| 3057 emit_operand32(rdi, src); | |
| 3058 } | |
| 3059 | |
| 3060 void Assembler::fdivr_s(Address src) { | |
| 3061 InstructionMark im(this); | |
| 3062 emit_byte(0xD8); | |
| 3063 emit_operand32(rdi, src); | |
| 3064 } | |
| 3065 | |
| 3066 void Assembler::fdivra(int i) { | |
| 3067 emit_farith(0xDC, 0xF0, i); | |
| 3068 } | |
| 3069 | |
| 3070 void Assembler::fdivrp(int i) { | |
| 3071 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong) | |
| 3072 } | |
| 3073 | |
| 3074 void Assembler::ffree(int i) { | |
| 3075 emit_farith(0xDD, 0xC0, i); | |
| 3076 } | |
| 3077 | |
| 3078 void Assembler::fild_d(Address adr) { | |
| 3079 InstructionMark im(this); | |
| 3080 emit_byte(0xDF); | |
| 3081 emit_operand32(rbp, adr); | |
| 3082 } | |
| 3083 | |
| 3084 void Assembler::fild_s(Address adr) { | |
| 3085 InstructionMark im(this); | |
| 3086 emit_byte(0xDB); | |
| 3087 emit_operand32(rax, adr); | |
| 3088 } | |
| 3089 | |
| 3090 void Assembler::fincstp() { | |
| 3091 emit_byte(0xD9); | |
| 3092 emit_byte(0xF7); | |
| 3093 } | |
| 3094 | |
| 3095 void Assembler::finit() { | |
| 3096 emit_byte(0x9B); | |
| 3097 emit_byte(0xDB); | |
| 3098 emit_byte(0xE3); | |
| 3099 } | |
| 3100 | |
| 3101 void Assembler::fist_s(Address adr) { | |
| 3102 InstructionMark im(this); | |
| 3103 emit_byte(0xDB); | |
| 3104 emit_operand32(rdx, adr); | |
| 3105 } | |
| 3106 | |
| 3107 void Assembler::fistp_d(Address adr) { | |
| 3108 InstructionMark im(this); | |
| 3109 emit_byte(0xDF); | |
| 3110 emit_operand32(rdi, adr); | |
| 3111 } | |
| 3112 | |
| 3113 void Assembler::fistp_s(Address adr) { | |
| 3114 InstructionMark im(this); | |
| 3115 emit_byte(0xDB); | |
| 3116 emit_operand32(rbx, adr); | |
| 3117 } | |
| 0 | 3118 |
| 3119 void Assembler::fld1() { | |
| 3120 emit_byte(0xD9); | |
| 3121 emit_byte(0xE8); | |
| 3122 } | |
| 3123 | |
| 304 | 3124 void Assembler::fld_d(Address adr) { |
| 3125 InstructionMark im(this); | |
| 3126 emit_byte(0xDD); | |
| 3127 emit_operand32(rax, adr); | |
| 3128 } | |
| 0 | 3129 |
| 3130 void Assembler::fld_s(Address adr) { | |
| 3131 InstructionMark im(this); | |
| 3132 emit_byte(0xD9); | |
| 304 | 3133 emit_operand32(rax, adr); |
| 3134 } | |
| 3135 | |
| 3136 | |
| 3137 void Assembler::fld_s(int index) { | |
| 0 | 3138 emit_farith(0xD9, 0xC0, index); |
| 3139 } | |
| 3140 | |
| 3141 void Assembler::fld_x(Address adr) { | |
| 3142 InstructionMark im(this); | |
| 3143 emit_byte(0xDB); | |
| 304 | 3144 emit_operand32(rbp, adr); |
| 3145 } | |
| 3146 | |
| 3147 void Assembler::fldcw(Address src) { | |
| 3148 InstructionMark im(this); | |
| 3149 emit_byte(0xd9); | |
| 3150 emit_operand32(rbp, src); | |
| 3151 } | |
| 3152 | |
| 3153 void Assembler::fldenv(Address src) { | |
| 0 | 3154 InstructionMark im(this); |
| 3155 emit_byte(0xD9); | |
| 304 | 3156 emit_operand32(rsp, src); |
| 3157 } | |
| 3158 | |
| 3159 void Assembler::fldlg2() { | |
| 0 | 3160 emit_byte(0xD9); |
| 304 | 3161 emit_byte(0xEC); |
| 3162 } | |
| 0 | 3163 |
| 3164 void Assembler::fldln2() { | |
| 3165 emit_byte(0xD9); | |
| 3166 emit_byte(0xED); | |
| 3167 } | |
| 3168 | |
| 304 | 3169 void Assembler::fldz() { |
| 0 | 3170 emit_byte(0xD9); |
| 304 | 3171 emit_byte(0xEE); |
| 3172 } | |
| 0 | 3173 |
| 3174 void Assembler::flog() { | |
| 3175 fldln2(); | |
| 3176 fxch(); | |
| 3177 fyl2x(); | |
| 3178 } | |
| 3179 | |
| 3180 void Assembler::flog10() { | |
| 3181 fldlg2(); | |
| 3182 fxch(); | |
| 3183 fyl2x(); | |
| 3184 } | |
| 3185 | |
| 304 | 3186 void Assembler::fmul(int i) { |
| 3187 emit_farith(0xD8, 0xC8, i); | |
| 3188 } | |
| 3189 | |
| 3190 void Assembler::fmul_d(Address src) { | |
| 3191 InstructionMark im(this); | |
| 3192 emit_byte(0xDC); | |
| 3193 emit_operand32(rcx, src); | |
| 3194 } | |
| 3195 | |
| 3196 void Assembler::fmul_s(Address src) { | |
| 3197 InstructionMark im(this); | |
| 3198 emit_byte(0xD8); | |
| 3199 emit_operand32(rcx, src); | |
| 3200 } | |
| 3201 | |
| 3202 void Assembler::fmula(int i) { | |
| 3203 emit_farith(0xDC, 0xC8, i); | |
| 3204 } | |
| 3205 | |
| 3206 void Assembler::fmulp(int i) { | |
| 3207 emit_farith(0xDE, 0xC8, i); | |
| 3208 } | |
| 3209 | |
| 3210 void Assembler::fnsave(Address dst) { | |
| 3211 InstructionMark im(this); | |
| 3212 emit_byte(0xDD); | |
| 3213 emit_operand32(rsi, dst); | |
| 3214 } | |
| 3215 | |
| 3216 void Assembler::fnstcw(Address src) { | |
| 3217 InstructionMark im(this); | |
| 3218 emit_byte(0x9B); | |
| 3219 emit_byte(0xD9); | |
| 3220 emit_operand32(rdi, src); | |
| 3221 } | |
| 3222 | |
| 3223 void Assembler::fnstsw_ax() { | |
| 3224 emit_byte(0xdF); | |
| 3225 emit_byte(0xE0); | |
| 3226 } | |
| 3227 | |
| 3228 void Assembler::fprem() { | |
| 3229 emit_byte(0xD9); | |
| 3230 emit_byte(0xF8); | |
| 3231 } | |
| 3232 | |
| 3233 void Assembler::fprem1() { | |
| 3234 emit_byte(0xD9); | |
| 3235 emit_byte(0xF5); | |
| 3236 } | |
| 3237 | |
| 3238 void Assembler::frstor(Address src) { | |
| 3239 InstructionMark im(this); | |
| 3240 emit_byte(0xDD); | |
| 3241 emit_operand32(rsp, src); | |
| 3242 } | |
| 0 | 3243 |
| 3244 void Assembler::fsin() { | |
| 3245 emit_byte(0xD9); | |
| 3246 emit_byte(0xFE); | |
| 3247 } | |
| 3248 | |
| 304 | 3249 void Assembler::fsqrt() { |
| 3250 emit_byte(0xD9); | |
| 3251 emit_byte(0xFA); | |
| 3252 } | |
| 3253 | |
| 3254 void Assembler::fst_d(Address adr) { | |
| 3255 InstructionMark im(this); | |
| 3256 emit_byte(0xDD); | |
| 3257 emit_operand32(rdx, adr); | |
| 3258 } | |
| 3259 | |
| 3260 void Assembler::fst_s(Address adr) { | |
| 3261 InstructionMark im(this); | |
| 3262 emit_byte(0xD9); | |
| 3263 emit_operand32(rdx, adr); | |
| 3264 } | |
| 3265 | |
| 3266 void Assembler::fstp_d(Address adr) { | |
| 3267 InstructionMark im(this); | |
| 3268 emit_byte(0xDD); | |
| 3269 emit_operand32(rbx, adr); | |
| 3270 } | |
| 3271 | |
| 3272 void Assembler::fstp_d(int index) { | |
| 3273 emit_farith(0xDD, 0xD8, index); | |
| 3274 } | |
| 3275 | |
| 3276 void Assembler::fstp_s(Address adr) { | |
| 3277 InstructionMark im(this); | |
| 0 | 3278 emit_byte(0xD9); |
| 304 | 3279 emit_operand32(rbx, adr); |
| 3280 } | |
| 3281 | |
| 3282 void Assembler::fstp_x(Address adr) { | |
| 3283 InstructionMark im(this); | |
| 3284 emit_byte(0xDB); | |
| 3285 emit_operand32(rdi, adr); | |
| 3286 } | |
| 3287 | |
| 3288 void Assembler::fsub(int i) { | |
| 3289 emit_farith(0xD8, 0xE0, i); | |
| 3290 } | |
| 3291 | |
| 3292 void Assembler::fsub_d(Address src) { | |
| 3293 InstructionMark im(this); | |
| 3294 emit_byte(0xDC); | |
| 3295 emit_operand32(rsp, src); | |
| 3296 } | |
| 3297 | |
| 3298 void Assembler::fsub_s(Address src) { | |
| 3299 InstructionMark im(this); | |
| 3300 emit_byte(0xD8); | |
| 3301 emit_operand32(rsp, src); | |
| 3302 } | |
| 3303 | |
| 3304 void Assembler::fsuba(int i) { | |
| 3305 emit_farith(0xDC, 0xE8, i); | |
| 3306 } | |
| 3307 | |
| 3308 void Assembler::fsubp(int i) { | |
| 3309 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong) | |
| 3310 } | |
| 3311 | |
| 3312 void Assembler::fsubr(int i) { | |
| 3313 emit_farith(0xD8, 0xE8, i); | |
| 3314 } | |
| 3315 | |
| 3316 void Assembler::fsubr_d(Address src) { | |
| 3317 InstructionMark im(this); | |
| 3318 emit_byte(0xDC); | |
| 3319 emit_operand32(rbp, src); | |
| 3320 } | |
| 3321 | |
| 3322 void Assembler::fsubr_s(Address src) { | |
| 3323 InstructionMark im(this); | |
| 3324 emit_byte(0xD8); | |
| 3325 emit_operand32(rbp, src); | |
| 3326 } | |
| 3327 | |
| 3328 void Assembler::fsubra(int i) { | |
| 3329 emit_farith(0xDC, 0xE0, i); | |
| 3330 } | |
| 3331 | |
| 3332 void Assembler::fsubrp(int i) { | |
| 3333 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong) | |
| 0 | 3334 } |
| 3335 | |
| 3336 void Assembler::ftan() { | |
| 3337 emit_byte(0xD9); | |
| 3338 emit_byte(0xF2); | |
| 3339 emit_byte(0xDD); | |
| 3340 emit_byte(0xD8); | |
| 3341 } | |
| 3342 | |
| 304 | 3343 void Assembler::ftst() { |
| 0 | 3344 emit_byte(0xD9); |
| 304 | 3345 emit_byte(0xE4); |
| 3346 } | |
| 0 | 3347 |
| 3348 void Assembler::fucomi(int i) { | |
| 3349 // make sure the instruction is supported (introduced for P6, together with cmov) | |
| 3350 guarantee(VM_Version::supports_cmov(), "illegal instruction"); | |
| 3351 emit_farith(0xDB, 0xE8, i); | |
| 3352 } | |
| 3353 | |
| 3354 void Assembler::fucomip(int i) { | |
| 3355 // make sure the instruction is supported (introduced for P6, together with cmov) | |
| 3356 guarantee(VM_Version::supports_cmov(), "illegal instruction"); | |
| 3357 emit_farith(0xDF, 0xE8, i); | |
| 3358 } | |
| 3359 | |
| 3360 void Assembler::fwait() { | |
| 3361 emit_byte(0x9B); | |
| 3362 } | |
| 3363 | |
| 304 | 3364 void Assembler::fxch(int i) { |
| 3365 emit_farith(0xD9, 0xC8, i); | |
| 3366 } | |
| 3367 | |
| 3368 void Assembler::fyl2x() { | |
| 0 | 3369 emit_byte(0xD9); |
| 304 | 3370 emit_byte(0xF1); |
| 3371 } | |
| 3372 | |
| 3373 | |
| 3374 #ifndef _LP64 | |
| 3375 | |
| 3376 void Assembler::incl(Register dst) { | |
| 3377 // Don't use it directly. Use MacroAssembler::incrementl() instead. | |
| 3378 emit_byte(0x40 | dst->encoding()); | |
| 3379 } | |
| 3380 | |
| 3381 void Assembler::lea(Register dst, Address src) { | |
| 3382 leal(dst, src); | |
| 3383 } | |
| 3384 | |
| 3385 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) { | |
| 3386 InstructionMark im(this); | |
| 3387 emit_byte(0xC7); | |
| 3388 emit_operand(rax, dst); | |
| 3389 emit_data((int)imm32, rspec, 0); | |
| 3390 } | |
| 3391 | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
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diff
changeset
|
3392 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) { |
|
660978a2a31a
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diff
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|
3393 InstructionMark im(this); |
|
660978a2a31a
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diff
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|
3394 int encode = prefix_and_encode(dst->encoding()); |
|
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diff
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|
3395 emit_byte(0xB8 | encode); |
|
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diff
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|
3396 emit_data((int)imm32, rspec, 0); |
|
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|
3397 } |
| 304 | 3398 |
| 3399 void Assembler::popa() { // 32bit | |
| 3400 emit_byte(0x61); | |
| 3401 } | |
| 3402 | |
| 3403 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) { | |
| 3404 InstructionMark im(this); | |
| 3405 emit_byte(0x68); | |
| 3406 emit_data(imm32, rspec, 0); | |
| 3407 } | |
| 3408 | |
| 3409 void Assembler::pusha() { // 32bit | |
| 3410 emit_byte(0x60); | |
| 3411 } | |
| 3412 | |
| 3413 void Assembler::set_byte_if_not_zero(Register dst) { | |
| 0 | 3414 emit_byte(0x0F); |
| 304 | 3415 emit_byte(0x95); |
| 3416 emit_byte(0xE0 | dst->encoding()); | |
| 3417 } | |
| 3418 | |
| 3419 void Assembler::shldl(Register dst, Register src) { | |
| 0 | 3420 emit_byte(0x0F); |
| 304 | 3421 emit_byte(0xA5); |
| 3422 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding()); | |
| 3423 } | |
| 3424 | |
| 3425 void Assembler::shrdl(Register dst, Register src) { | |
| 0 | 3426 emit_byte(0x0F); |
| 304 | 3427 emit_byte(0xAD); |
| 3428 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding()); | |
| 3429 } | |
| 3430 | |
| 3431 #else // LP64 | |
| 3432 | |
| 1369 | 3433 void Assembler::set_byte_if_not_zero(Register dst) { |
| 3434 int enc = prefix_and_encode(dst->encoding(), true); | |
| 3435 emit_byte(0x0F); | |
| 3436 emit_byte(0x95); | |
| 3437 emit_byte(0xE0 | enc); | |
| 3438 } | |
| 3439 | |
| 304 | 3440 // 64bit only pieces of the assembler |
| 3441 // This should only be used by 64bit instructions that can use rip-relative | |
| 3442 // it cannot be used by instructions that want an immediate value. | |
| 3443 | |
| 3444 bool Assembler::reachable(AddressLiteral adr) { | |
| 3445 int64_t disp; | |
| 3446 // None will force a 64bit literal to the code stream. Likely a placeholder | |
| 3447 // for something that will be patched later and we need to certain it will | |
| 3448 // always be reachable. | |
| 3449 if (adr.reloc() == relocInfo::none) { | |
| 3450 return false; | |
| 3451 } | |
| 3452 if (adr.reloc() == relocInfo::internal_word_type) { | |
| 3453 // This should be rip relative and easily reachable. | |
| 3454 return true; | |
| 3455 } | |
| 3456 if (adr.reloc() == relocInfo::virtual_call_type || | |
| 3457 adr.reloc() == relocInfo::opt_virtual_call_type || | |
| 3458 adr.reloc() == relocInfo::static_call_type || | |
| 3459 adr.reloc() == relocInfo::static_stub_type ) { | |
| 3460 // This should be rip relative within the code cache and easily | |
| 3461 // reachable until we get huge code caches. (At which point | |
| 3462 // ic code is going to have issues). | |
| 3463 return true; | |
| 3464 } | |
| 3465 if (adr.reloc() != relocInfo::external_word_type && | |
| 3466 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special | |
| 3467 adr.reloc() != relocInfo::poll_type && // relocs to identify them | |
| 3468 adr.reloc() != relocInfo::runtime_call_type ) { | |
| 3469 return false; | |
| 3470 } | |
| 3471 | |
| 3472 // Stress the correction code | |
| 3473 if (ForceUnreachable) { | |
| 3474 // Must be runtimecall reloc, see if it is in the codecache | |
| 3475 // Flipping stuff in the codecache to be unreachable causes issues | |
| 3476 // with things like inline caches where the additional instructions | |
| 3477 // are not handled. | |
| 3478 if (CodeCache::find_blob(adr._target) == NULL) { | |
| 3479 return false; | |
| 3480 } | |
| 3481 } | |
| 3482 // For external_word_type/runtime_call_type if it is reachable from where we | |
| 3483 // are now (possibly a temp buffer) and where we might end up | |
| 3484 // anywhere in the codeCache then we are always reachable. | |
| 3485 // This would have to change if we ever save/restore shared code | |
| 3486 // to be more pessimistic. | |
| 3487 | |
| 3488 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int)); | |
| 3489 if (!is_simm32(disp)) return false; | |
| 3490 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int)); | |
| 3491 if (!is_simm32(disp)) return false; | |
| 3492 | |
| 3493 disp = (int64_t)adr._target - ((int64_t)_code_pos + sizeof(int)); | |
| 3494 | |
| 3495 // Because rip relative is a disp + address_of_next_instruction and we | |
| 3496 // don't know the value of address_of_next_instruction we apply a fudge factor | |
| 3497 // to make sure we will be ok no matter the size of the instruction we get placed into. | |
| 3498 // We don't have to fudge the checks above here because they are already worst case. | |
| 3499 | |
| 3500 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal | |
| 3501 // + 4 because better safe than sorry. | |
| 3502 const int fudge = 12 + 4; | |
| 3503 if (disp < 0) { | |
| 3504 disp -= fudge; | |
| 3505 } else { | |
| 3506 disp += fudge; | |
| 3507 } | |
| 3508 return is_simm32(disp); | |
| 3509 } | |
| 3510 | |
| 3511 void Assembler::emit_data64(jlong data, | |
| 3512 relocInfo::relocType rtype, | |
| 3513 int format) { | |
| 3514 if (rtype == relocInfo::none) { | |
| 3515 emit_long64(data); | |
| 3516 } else { | |
| 3517 emit_data64(data, Relocation::spec_simple(rtype), format); | |
| 3518 } | |
| 3519 } | |
| 3520 | |
| 3521 void Assembler::emit_data64(jlong data, | |
| 3522 RelocationHolder const& rspec, | |
| 3523 int format) { | |
| 3524 assert(imm_operand == 0, "default format must be immediate in this file"); | |
| 3525 assert(imm_operand == format, "must be immediate"); | |
| 3526 assert(inst_mark() != NULL, "must be inside InstructionMark"); | |
| 3527 // Do not use AbstractAssembler::relocate, which is not intended for | |
| 3528 // embedded words. Instead, relocate to the enclosing instruction. | |
| 3529 code_section()->relocate(inst_mark(), rspec, format); | |
| 3530 #ifdef ASSERT | |
| 3531 check_relocation(rspec, format); | |
| 3532 #endif | |
| 3533 emit_long64(data); | |
| 3534 } | |
| 3535 | |
| 3536 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) { | |
| 3537 if (reg_enc >= 8) { | |
| 3538 prefix(REX_B); | |
| 3539 reg_enc -= 8; | |
| 3540 } else if (byteinst && reg_enc >= 4) { | |
| 3541 prefix(REX); | |
| 3542 } | |
| 3543 return reg_enc; | |
| 3544 } | |
| 3545 | |
| 3546 int Assembler::prefixq_and_encode(int reg_enc) { | |
| 3547 if (reg_enc < 8) { | |
| 3548 prefix(REX_W); | |
| 3549 } else { | |
| 3550 prefix(REX_WB); | |
| 3551 reg_enc -= 8; | |
| 3552 } | |
| 3553 return reg_enc; | |
| 3554 } | |
| 3555 | |
| 3556 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) { | |
| 3557 if (dst_enc < 8) { | |
| 3558 if (src_enc >= 8) { | |
| 3559 prefix(REX_B); | |
| 3560 src_enc -= 8; | |
| 3561 } else if (byteinst && src_enc >= 4) { | |
| 3562 prefix(REX); | |
| 3563 } | |
| 3564 } else { | |
| 3565 if (src_enc < 8) { | |
| 3566 prefix(REX_R); | |
| 3567 } else { | |
| 3568 prefix(REX_RB); | |
| 3569 src_enc -= 8; | |
| 3570 } | |
| 3571 dst_enc -= 8; | |
| 3572 } | |
| 3573 return dst_enc << 3 | src_enc; | |
| 3574 } | |
| 3575 | |
| 3576 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) { | |
| 3577 if (dst_enc < 8) { | |
| 3578 if (src_enc < 8) { | |
| 3579 prefix(REX_W); | |
| 3580 } else { | |
| 3581 prefix(REX_WB); | |
| 3582 src_enc -= 8; | |
| 3583 } | |
| 3584 } else { | |
| 3585 if (src_enc < 8) { | |
| 3586 prefix(REX_WR); | |
| 3587 } else { | |
| 3588 prefix(REX_WRB); | |
| 3589 src_enc -= 8; | |
| 3590 } | |
| 3591 dst_enc -= 8; | |
| 3592 } | |
| 3593 return dst_enc << 3 | src_enc; | |
| 3594 } | |
| 3595 | |
| 3596 void Assembler::prefix(Register reg) { | |
| 3597 if (reg->encoding() >= 8) { | |
| 3598 prefix(REX_B); | |
| 3599 } | |
| 3600 } | |
| 3601 | |
| 3602 void Assembler::prefix(Address adr) { | |
| 3603 if (adr.base_needs_rex()) { | |
| 3604 if (adr.index_needs_rex()) { | |
| 3605 prefix(REX_XB); | |
| 3606 } else { | |
| 3607 prefix(REX_B); | |
| 3608 } | |
| 3609 } else { | |
| 3610 if (adr.index_needs_rex()) { | |
| 3611 prefix(REX_X); | |
| 3612 } | |
| 3613 } | |
| 3614 } | |
| 3615 | |
| 3616 void Assembler::prefixq(Address adr) { | |
| 3617 if (adr.base_needs_rex()) { | |
| 3618 if (adr.index_needs_rex()) { | |
| 3619 prefix(REX_WXB); | |
| 3620 } else { | |
| 3621 prefix(REX_WB); | |
| 3622 } | |
| 3623 } else { | |
| 3624 if (adr.index_needs_rex()) { | |
| 3625 prefix(REX_WX); | |
| 3626 } else { | |
| 3627 prefix(REX_W); | |
| 3628 } | |
| 3629 } | |
| 3630 } | |
| 3631 | |
| 3632 | |
| 3633 void Assembler::prefix(Address adr, Register reg, bool byteinst) { | |
| 3634 if (reg->encoding() < 8) { | |
| 3635 if (adr.base_needs_rex()) { | |
| 3636 if (adr.index_needs_rex()) { | |
| 3637 prefix(REX_XB); | |
| 3638 } else { | |
| 3639 prefix(REX_B); | |
| 3640 } | |
| 3641 } else { | |
| 3642 if (adr.index_needs_rex()) { | |
| 3643 prefix(REX_X); | |
| 3644 } else if (reg->encoding() >= 4 ) { | |
| 3645 prefix(REX); | |
| 3646 } | |
| 3647 } | |
| 3648 } else { | |
| 3649 if (adr.base_needs_rex()) { | |
| 3650 if (adr.index_needs_rex()) { | |
| 3651 prefix(REX_RXB); | |
| 3652 } else { | |
| 3653 prefix(REX_RB); | |
| 3654 } | |
| 3655 } else { | |
| 3656 if (adr.index_needs_rex()) { | |
| 3657 prefix(REX_RX); | |
| 3658 } else { | |
| 3659 prefix(REX_R); | |
| 3660 } | |
| 3661 } | |
| 3662 } | |
| 3663 } | |
| 3664 | |
| 3665 void Assembler::prefixq(Address adr, Register src) { | |
| 3666 if (src->encoding() < 8) { | |
| 3667 if (adr.base_needs_rex()) { | |
| 3668 if (adr.index_needs_rex()) { | |
| 3669 prefix(REX_WXB); | |
| 3670 } else { | |
| 3671 prefix(REX_WB); | |
| 3672 } | |
| 3673 } else { | |
| 3674 if (adr.index_needs_rex()) { | |
| 3675 prefix(REX_WX); | |
| 3676 } else { | |
| 3677 prefix(REX_W); | |
| 3678 } | |
| 3679 } | |
| 3680 } else { | |
| 3681 if (adr.base_needs_rex()) { | |
| 3682 if (adr.index_needs_rex()) { | |
| 3683 prefix(REX_WRXB); | |
| 3684 } else { | |
| 3685 prefix(REX_WRB); | |
| 3686 } | |
| 3687 } else { | |
| 3688 if (adr.index_needs_rex()) { | |
| 3689 prefix(REX_WRX); | |
| 3690 } else { | |
| 3691 prefix(REX_WR); | |
| 3692 } | |
| 3693 } | |
| 3694 } | |
| 3695 } | |
| 3696 | |
| 3697 void Assembler::prefix(Address adr, XMMRegister reg) { | |
| 3698 if (reg->encoding() < 8) { | |
| 3699 if (adr.base_needs_rex()) { | |
| 3700 if (adr.index_needs_rex()) { | |
| 3701 prefix(REX_XB); | |
| 3702 } else { | |
| 3703 prefix(REX_B); | |
| 3704 } | |
| 3705 } else { | |
| 3706 if (adr.index_needs_rex()) { | |
| 3707 prefix(REX_X); | |
| 3708 } | |
| 3709 } | |
| 3710 } else { | |
| 3711 if (adr.base_needs_rex()) { | |
| 3712 if (adr.index_needs_rex()) { | |
| 3713 prefix(REX_RXB); | |
| 3714 } else { | |
| 3715 prefix(REX_RB); | |
| 3716 } | |
| 3717 } else { | |
| 3718 if (adr.index_needs_rex()) { | |
| 3719 prefix(REX_RX); | |
| 3720 } else { | |
| 3721 prefix(REX_R); | |
| 3722 } | |
| 3723 } | |
| 3724 } | |
| 3725 } | |
| 3726 | |
| 3727 void Assembler::adcq(Register dst, int32_t imm32) { | |
| 3728 (void) prefixq_and_encode(dst->encoding()); | |
| 3729 emit_arith(0x81, 0xD0, dst, imm32); | |
| 3730 } | |
| 3731 | |
| 3732 void Assembler::adcq(Register dst, Address src) { | |
| 3733 InstructionMark im(this); | |
| 3734 prefixq(src, dst); | |
| 3735 emit_byte(0x13); | |
| 3736 emit_operand(dst, src); | |
| 3737 } | |
| 3738 | |
| 3739 void Assembler::adcq(Register dst, Register src) { | |
| 3740 (int) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3741 emit_arith(0x13, 0xC0, dst, src); | |
| 3742 } | |
| 3743 | |
| 3744 void Assembler::addq(Address dst, int32_t imm32) { | |
| 3745 InstructionMark im(this); | |
| 3746 prefixq(dst); | |
| 3747 emit_arith_operand(0x81, rax, dst,imm32); | |
| 3748 } | |
| 3749 | |
| 3750 void Assembler::addq(Address dst, Register src) { | |
| 3751 InstructionMark im(this); | |
| 3752 prefixq(dst, src); | |
| 3753 emit_byte(0x01); | |
| 3754 emit_operand(src, dst); | |
| 3755 } | |
| 3756 | |
| 3757 void Assembler::addq(Register dst, int32_t imm32) { | |
| 3758 (void) prefixq_and_encode(dst->encoding()); | |
| 3759 emit_arith(0x81, 0xC0, dst, imm32); | |
| 3760 } | |
| 3761 | |
| 3762 void Assembler::addq(Register dst, Address src) { | |
| 3763 InstructionMark im(this); | |
| 3764 prefixq(src, dst); | |
| 3765 emit_byte(0x03); | |
| 3766 emit_operand(dst, src); | |
| 3767 } | |
| 3768 | |
| 3769 void Assembler::addq(Register dst, Register src) { | |
| 3770 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3771 emit_arith(0x03, 0xC0, dst, src); | |
| 3772 } | |
| 3773 | |
| 3774 void Assembler::andq(Register dst, int32_t imm32) { | |
| 3775 (void) prefixq_and_encode(dst->encoding()); | |
| 3776 emit_arith(0x81, 0xE0, dst, imm32); | |
| 3777 } | |
| 3778 | |
| 3779 void Assembler::andq(Register dst, Address src) { | |
| 3780 InstructionMark im(this); | |
| 3781 prefixq(src, dst); | |
| 3782 emit_byte(0x23); | |
| 3783 emit_operand(dst, src); | |
| 3784 } | |
| 3785 | |
| 3786 void Assembler::andq(Register dst, Register src) { | |
| 3787 (int) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3788 emit_arith(0x23, 0xC0, dst, src); | |
| 3789 } | |
| 3790 | |
|
775
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diff
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|
3791 void Assembler::bsfq(Register dst, Register src) { |
|
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diff
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|
3792 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
|
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diff
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|
3793 emit_byte(0x0F); |
|
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diff
changeset
|
3794 emit_byte(0xBC); |
|
93c14e5562c4
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diff
changeset
|
3795 emit_byte(0xC0 | encode); |
|
93c14e5562c4
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diff
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|
3796 } |
|
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diff
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|
3797 |
|
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changeset
|
3798 void Assembler::bsrq(Register dst, Register src) { |
|
93c14e5562c4
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diff
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|
3799 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT"); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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diff
changeset
|
3800 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
|
93c14e5562c4
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parents:
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diff
changeset
|
3801 emit_byte(0x0F); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
3802 emit_byte(0xBD); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
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diff
changeset
|
3803 emit_byte(0xC0 | encode); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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diff
changeset
|
3804 } |
|
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6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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diff
changeset
|
3805 |
| 304 | 3806 void Assembler::bswapq(Register reg) { |
| 3807 int encode = prefixq_and_encode(reg->encoding()); | |
| 3808 emit_byte(0x0F); | |
| 3809 emit_byte(0xC8 | encode); | |
| 3810 } | |
| 3811 | |
| 3812 void Assembler::cdqq() { | |
| 3813 prefix(REX_W); | |
| 3814 emit_byte(0x99); | |
| 3815 } | |
| 3816 | |
| 3817 void Assembler::clflush(Address adr) { | |
| 3818 prefix(adr); | |
| 3819 emit_byte(0x0F); | |
| 3820 emit_byte(0xAE); | |
| 3821 emit_operand(rdi, adr); | |
| 3822 } | |
| 3823 | |
| 3824 void Assembler::cmovq(Condition cc, Register dst, Register src) { | |
| 3825 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3826 emit_byte(0x0F); | |
| 3827 emit_byte(0x40 | cc); | |
| 3828 emit_byte(0xC0 | encode); | |
| 3829 } | |
| 3830 | |
| 3831 void Assembler::cmovq(Condition cc, Register dst, Address src) { | |
| 3832 InstructionMark im(this); | |
| 3833 prefixq(src, dst); | |
| 3834 emit_byte(0x0F); | |
| 3835 emit_byte(0x40 | cc); | |
| 3836 emit_operand(dst, src); | |
| 3837 } | |
| 3838 | |
| 3839 void Assembler::cmpq(Address dst, int32_t imm32) { | |
| 3840 InstructionMark im(this); | |
| 3841 prefixq(dst); | |
| 3842 emit_byte(0x81); | |
| 3843 emit_operand(rdi, dst, 4); | |
| 3844 emit_long(imm32); | |
| 3845 } | |
| 3846 | |
| 3847 void Assembler::cmpq(Register dst, int32_t imm32) { | |
| 3848 (void) prefixq_and_encode(dst->encoding()); | |
| 3849 emit_arith(0x81, 0xF8, dst, imm32); | |
| 3850 } | |
| 3851 | |
| 3852 void Assembler::cmpq(Address dst, Register src) { | |
| 3853 InstructionMark im(this); | |
| 3854 prefixq(dst, src); | |
| 3855 emit_byte(0x3B); | |
| 3856 emit_operand(src, dst); | |
| 3857 } | |
| 3858 | |
| 3859 void Assembler::cmpq(Register dst, Register src) { | |
| 3860 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3861 emit_arith(0x3B, 0xC0, dst, src); | |
| 3862 } | |
| 3863 | |
| 3864 void Assembler::cmpq(Register dst, Address src) { | |
| 3865 InstructionMark im(this); | |
| 3866 prefixq(src, dst); | |
| 3867 emit_byte(0x3B); | |
| 3868 emit_operand(dst, src); | |
| 3869 } | |
| 3870 | |
| 3871 void Assembler::cmpxchgq(Register reg, Address adr) { | |
| 3872 InstructionMark im(this); | |
| 3873 prefixq(adr, reg); | |
| 3874 emit_byte(0x0F); | |
| 3875 emit_byte(0xB1); | |
| 3876 emit_operand(reg, adr); | |
| 3877 } | |
| 3878 | |
| 3879 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) { | |
| 3880 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 3881 emit_byte(0xF2); | |
| 3882 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3883 emit_byte(0x0F); | |
| 3884 emit_byte(0x2A); | |
| 3885 emit_byte(0xC0 | encode); | |
| 3886 } | |
| 3887 | |
| 3888 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) { | |
| 3889 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 3890 emit_byte(0xF3); | |
| 3891 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3892 emit_byte(0x0F); | |
| 3893 emit_byte(0x2A); | |
| 3894 emit_byte(0xC0 | encode); | |
| 3895 } | |
| 3896 | |
| 3897 void Assembler::cvttsd2siq(Register dst, XMMRegister src) { | |
| 3898 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
| 3899 emit_byte(0xF2); | |
| 3900 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3901 emit_byte(0x0F); | |
| 3902 emit_byte(0x2C); | |
| 3903 emit_byte(0xC0 | encode); | |
| 3904 } | |
| 3905 | |
| 3906 void Assembler::cvttss2siq(Register dst, XMMRegister src) { | |
| 3907 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
| 3908 emit_byte(0xF3); | |
| 3909 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3910 emit_byte(0x0F); | |
| 3911 emit_byte(0x2C); | |
| 3912 emit_byte(0xC0 | encode); | |
| 3913 } | |
| 3914 | |
| 3915 void Assembler::decl(Register dst) { | |
| 3916 // Don't use it directly. Use MacroAssembler::decrementl() instead. | |
| 3917 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode) | |
| 3918 int encode = prefix_and_encode(dst->encoding()); | |
| 3919 emit_byte(0xFF); | |
| 3920 emit_byte(0xC8 | encode); | |
| 3921 } | |
| 3922 | |
| 3923 void Assembler::decq(Register dst) { | |
| 3924 // Don't use it directly. Use MacroAssembler::decrementq() instead. | |
| 3925 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
| 3926 int encode = prefixq_and_encode(dst->encoding()); | |
| 3927 emit_byte(0xFF); | |
| 3928 emit_byte(0xC8 | encode); | |
| 3929 } | |
| 3930 | |
| 3931 void Assembler::decq(Address dst) { | |
| 3932 // Don't use it directly. Use MacroAssembler::decrementq() instead. | |
| 3933 InstructionMark im(this); | |
| 3934 prefixq(dst); | |
| 3935 emit_byte(0xFF); | |
| 3936 emit_operand(rcx, dst); | |
| 3937 } | |
| 3938 | |
| 3939 void Assembler::fxrstor(Address src) { | |
| 3940 prefixq(src); | |
| 3941 emit_byte(0x0F); | |
| 3942 emit_byte(0xAE); | |
| 3943 emit_operand(as_Register(1), src); | |
| 3944 } | |
| 3945 | |
| 3946 void Assembler::fxsave(Address dst) { | |
| 3947 prefixq(dst); | |
| 3948 emit_byte(0x0F); | |
| 3949 emit_byte(0xAE); | |
| 3950 emit_operand(as_Register(0), dst); | |
| 3951 } | |
| 3952 | |
| 3953 void Assembler::idivq(Register src) { | |
| 3954 int encode = prefixq_and_encode(src->encoding()); | |
| 3955 emit_byte(0xF7); | |
| 3956 emit_byte(0xF8 | encode); | |
| 3957 } | |
| 3958 | |
| 3959 void Assembler::imulq(Register dst, Register src) { | |
| 3960 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3961 emit_byte(0x0F); | |
| 3962 emit_byte(0xAF); | |
| 3963 emit_byte(0xC0 | encode); | |
| 3964 } | |
| 3965 | |
| 3966 void Assembler::imulq(Register dst, Register src, int value) { | |
| 3967 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 3968 if (is8bit(value)) { | |
| 3969 emit_byte(0x6B); | |
| 3970 emit_byte(0xC0 | encode); | |
|
1914
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diff
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|
3971 emit_byte(value & 0xFF); |
| 304 | 3972 } else { |
| 3973 emit_byte(0x69); | |
| 3974 emit_byte(0xC0 | encode); | |
| 3975 emit_long(value); | |
| 3976 } | |
| 3977 } | |
| 3978 | |
| 3979 void Assembler::incl(Register dst) { | |
| 3980 // Don't use it directly. Use MacroAssembler::incrementl() instead. | |
| 3981 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
| 3982 int encode = prefix_and_encode(dst->encoding()); | |
| 3983 emit_byte(0xFF); | |
| 3984 emit_byte(0xC0 | encode); | |
| 3985 } | |
| 3986 | |
| 3987 void Assembler::incq(Register dst) { | |
| 3988 // Don't use it directly. Use MacroAssembler::incrementq() instead. | |
| 3989 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
| 3990 int encode = prefixq_and_encode(dst->encoding()); | |
| 3991 emit_byte(0xFF); | |
| 3992 emit_byte(0xC0 | encode); | |
| 3993 } | |
| 3994 | |
| 3995 void Assembler::incq(Address dst) { | |
| 3996 // Don't use it directly. Use MacroAssembler::incrementq() instead. | |
| 3997 InstructionMark im(this); | |
| 3998 prefixq(dst); | |
| 3999 emit_byte(0xFF); | |
| 4000 emit_operand(rax, dst); | |
| 4001 } | |
| 4002 | |
| 4003 void Assembler::lea(Register dst, Address src) { | |
| 4004 leaq(dst, src); | |
| 4005 } | |
| 4006 | |
| 4007 void Assembler::leaq(Register dst, Address src) { | |
| 4008 InstructionMark im(this); | |
| 4009 prefixq(src, dst); | |
| 4010 emit_byte(0x8D); | |
| 4011 emit_operand(dst, src); | |
| 4012 } | |
| 4013 | |
| 4014 void Assembler::mov64(Register dst, int64_t imm64) { | |
| 4015 InstructionMark im(this); | |
| 4016 int encode = prefixq_and_encode(dst->encoding()); | |
| 4017 emit_byte(0xB8 | encode); | |
| 4018 emit_long64(imm64); | |
| 4019 } | |
| 4020 | |
| 4021 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) { | |
| 4022 InstructionMark im(this); | |
| 4023 int encode = prefixq_and_encode(dst->encoding()); | |
| 4024 emit_byte(0xB8 | encode); | |
| 4025 emit_data64(imm64, rspec); | |
| 4026 } | |
| 4027 | |
|
642
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|
4028 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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4029 InstructionMark im(this); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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diff
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|
4030 int encode = prefix_and_encode(dst->encoding()); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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|
4031 emit_byte(0xB8 | encode); |
|
660978a2a31a
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diff
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|
4032 emit_data((int)imm32, rspec, narrow_oop_operand); |
|
660978a2a31a
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|
4033 } |
|
660978a2a31a
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|
4034 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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|
4035 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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diff
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|
4036 InstructionMark im(this); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
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diff
changeset
|
4037 prefix(dst); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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|
4038 emit_byte(0xC7); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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diff
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|
4039 emit_operand(rax, dst, 4); |
|
660978a2a31a
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diff
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|
4040 emit_data((int)imm32, rspec, narrow_oop_operand); |
|
660978a2a31a
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|
4041 } |
|
660978a2a31a
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|
4042 |
|
660978a2a31a
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|
4043 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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|
4044 InstructionMark im(this); |
|
660978a2a31a
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|
4045 int encode = prefix_and_encode(src1->encoding()); |
|
660978a2a31a
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|
4046 emit_byte(0x81); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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diff
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|
4047 emit_byte(0xF8 | encode); |
|
660978a2a31a
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diff
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|
4048 emit_data((int)imm32, rspec, narrow_oop_operand); |
|
660978a2a31a
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|
4049 } |
|
660978a2a31a
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|
4050 |
|
660978a2a31a
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|
4051 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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|
4052 InstructionMark im(this); |
|
660978a2a31a
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624
diff
changeset
|
4053 prefix(src1); |
|
660978a2a31a
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|
4054 emit_byte(0x81); |
|
660978a2a31a
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|
4055 emit_operand(rax, src1, 4); |
|
660978a2a31a
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diff
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|
4056 emit_data((int)imm32, rspec, narrow_oop_operand); |
|
660978a2a31a
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|
4057 } |
|
660978a2a31a
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|
4058 |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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710
diff
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|
4059 void Assembler::lzcntq(Register dst, Register src) { |
|
93c14e5562c4
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twisti
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diff
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|
4060 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); |
|
93c14e5562c4
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twisti
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diff
changeset
|
4061 emit_byte(0xF3); |
|
93c14e5562c4
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twisti
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710
diff
changeset
|
4062 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
|
93c14e5562c4
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twisti
parents:
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diff
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|
4063 emit_byte(0x0F); |
|
93c14e5562c4
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twisti
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710
diff
changeset
|
4064 emit_byte(0xBD); |
|
93c14e5562c4
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twisti
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710
diff
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|
4065 emit_byte(0xC0 | encode); |
|
93c14e5562c4
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diff
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|
4066 } |
|
93c14e5562c4
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twisti
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|
4067 |
| 304 | 4068 void Assembler::movdq(XMMRegister dst, Register src) { |
| 4069 // table D-1 says MMX/SSE2 | |
| 4070 NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), "")); | |
| 0 | 4071 emit_byte(0x66); |
| 304 | 4072 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
| 0 | 4073 emit_byte(0x0F); |
| 304 | 4074 emit_byte(0x6E); |
| 4075 emit_byte(0xC0 | encode); | |
| 4076 } | |
| 4077 | |
| 4078 void Assembler::movdq(Register dst, XMMRegister src) { | |
| 4079 // table D-1 says MMX/SSE2 | |
| 4080 NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), "")); | |
| 0 | 4081 emit_byte(0x66); |
| 304 | 4082 // swap src/dst to get correct prefix |
| 4083 int encode = prefixq_and_encode(src->encoding(), dst->encoding()); | |
| 0 | 4084 emit_byte(0x0F); |
| 4085 emit_byte(0x7E); | |
| 304 | 4086 emit_byte(0xC0 | encode); |
| 4087 } | |
| 4088 | |
| 4089 void Assembler::movq(Register dst, Register src) { | |
| 4090 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4091 emit_byte(0x8B); | |
| 4092 emit_byte(0xC0 | encode); | |
| 4093 } | |
| 4094 | |
| 4095 void Assembler::movq(Register dst, Address src) { | |
| 4096 InstructionMark im(this); | |
| 4097 prefixq(src, dst); | |
| 4098 emit_byte(0x8B); | |
| 4099 emit_operand(dst, src); | |
| 4100 } | |
| 4101 | |
| 4102 void Assembler::movq(Address dst, Register src) { | |
| 4103 InstructionMark im(this); | |
| 4104 prefixq(dst, src); | |
| 4105 emit_byte(0x89); | |
| 4106 emit_operand(src, dst); | |
| 4107 } | |
| 4108 | |
| 624 | 4109 void Assembler::movsbq(Register dst, Address src) { |
| 4110 InstructionMark im(this); | |
| 4111 prefixq(src, dst); | |
| 4112 emit_byte(0x0F); | |
| 4113 emit_byte(0xBE); | |
| 4114 emit_operand(dst, src); | |
| 4115 } | |
| 4116 | |
| 4117 void Assembler::movsbq(Register dst, Register src) { | |
| 4118 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4119 emit_byte(0x0F); | |
| 4120 emit_byte(0xBE); | |
| 4121 emit_byte(0xC0 | encode); | |
| 4122 } | |
| 4123 | |
| 304 | 4124 void Assembler::movslq(Register dst, int32_t imm32) { |
| 4125 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx) | |
| 4126 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx) | |
| 4127 // as a result we shouldn't use until tested at runtime... | |
| 4128 ShouldNotReachHere(); | |
| 4129 InstructionMark im(this); | |
| 4130 int encode = prefixq_and_encode(dst->encoding()); | |
| 4131 emit_byte(0xC7 | encode); | |
| 4132 emit_long(imm32); | |
| 4133 } | |
| 4134 | |
| 4135 void Assembler::movslq(Address dst, int32_t imm32) { | |
| 4136 assert(is_simm32(imm32), "lost bits"); | |
| 4137 InstructionMark im(this); | |
| 4138 prefixq(dst); | |
| 4139 emit_byte(0xC7); | |
| 4140 emit_operand(rax, dst, 4); | |
| 4141 emit_long(imm32); | |
| 4142 } | |
| 4143 | |
| 4144 void Assembler::movslq(Register dst, Address src) { | |
| 4145 InstructionMark im(this); | |
| 4146 prefixq(src, dst); | |
| 4147 emit_byte(0x63); | |
| 4148 emit_operand(dst, src); | |
| 4149 } | |
| 4150 | |
| 4151 void Assembler::movslq(Register dst, Register src) { | |
| 4152 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4153 emit_byte(0x63); | |
| 4154 emit_byte(0xC0 | encode); | |
| 4155 } | |
| 4156 | |
| 624 | 4157 void Assembler::movswq(Register dst, Address src) { |
| 4158 InstructionMark im(this); | |
| 4159 prefixq(src, dst); | |
| 4160 emit_byte(0x0F); | |
| 4161 emit_byte(0xBF); | |
| 4162 emit_operand(dst, src); | |
| 4163 } | |
| 4164 | |
| 4165 void Assembler::movswq(Register dst, Register src) { | |
| 4166 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4167 emit_byte(0x0F); | |
| 4168 emit_byte(0xBF); | |
| 4169 emit_byte(0xC0 | encode); | |
| 4170 } | |
| 4171 | |
| 4172 void Assembler::movzbq(Register dst, Address src) { | |
| 4173 InstructionMark im(this); | |
| 4174 prefixq(src, dst); | |
| 4175 emit_byte(0x0F); | |
| 4176 emit_byte(0xB6); | |
| 4177 emit_operand(dst, src); | |
| 4178 } | |
| 4179 | |
| 4180 void Assembler::movzbq(Register dst, Register src) { | |
| 4181 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4182 emit_byte(0x0F); | |
| 4183 emit_byte(0xB6); | |
| 4184 emit_byte(0xC0 | encode); | |
| 4185 } | |
| 4186 | |
| 4187 void Assembler::movzwq(Register dst, Address src) { | |
| 4188 InstructionMark im(this); | |
| 4189 prefixq(src, dst); | |
| 4190 emit_byte(0x0F); | |
| 4191 emit_byte(0xB7); | |
| 4192 emit_operand(dst, src); | |
| 4193 } | |
| 4194 | |
| 4195 void Assembler::movzwq(Register dst, Register src) { | |
| 4196 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4197 emit_byte(0x0F); | |
| 4198 emit_byte(0xB7); | |
| 4199 emit_byte(0xC0 | encode); | |
| 4200 } | |
| 4201 | |
| 304 | 4202 void Assembler::negq(Register dst) { |
| 4203 int encode = prefixq_and_encode(dst->encoding()); | |
| 4204 emit_byte(0xF7); | |
| 4205 emit_byte(0xD8 | encode); | |
| 4206 } | |
| 4207 | |
| 4208 void Assembler::notq(Register dst) { | |
| 4209 int encode = prefixq_and_encode(dst->encoding()); | |
| 4210 emit_byte(0xF7); | |
| 4211 emit_byte(0xD0 | encode); | |
| 4212 } | |
| 4213 | |
| 4214 void Assembler::orq(Address dst, int32_t imm32) { | |
| 4215 InstructionMark im(this); | |
| 4216 prefixq(dst); | |
| 4217 emit_byte(0x81); | |
| 4218 emit_operand(rcx, dst, 4); | |
| 4219 emit_long(imm32); | |
| 4220 } | |
| 4221 | |
| 4222 void Assembler::orq(Register dst, int32_t imm32) { | |
| 4223 (void) prefixq_and_encode(dst->encoding()); | |
| 4224 emit_arith(0x81, 0xC8, dst, imm32); | |
| 4225 } | |
| 4226 | |
| 4227 void Assembler::orq(Register dst, Address src) { | |
| 4228 InstructionMark im(this); | |
| 4229 prefixq(src, dst); | |
| 4230 emit_byte(0x0B); | |
| 4231 emit_operand(dst, src); | |
| 4232 } | |
| 4233 | |
| 4234 void Assembler::orq(Register dst, Register src) { | |
| 4235 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4236 emit_arith(0x0B, 0xC0, dst, src); | |
| 4237 } | |
| 4238 | |
| 4239 void Assembler::popa() { // 64bit | |
| 4240 movq(r15, Address(rsp, 0)); | |
| 4241 movq(r14, Address(rsp, wordSize)); | |
| 4242 movq(r13, Address(rsp, 2 * wordSize)); | |
| 4243 movq(r12, Address(rsp, 3 * wordSize)); | |
| 4244 movq(r11, Address(rsp, 4 * wordSize)); | |
| 4245 movq(r10, Address(rsp, 5 * wordSize)); | |
| 4246 movq(r9, Address(rsp, 6 * wordSize)); | |
| 4247 movq(r8, Address(rsp, 7 * wordSize)); | |
| 4248 movq(rdi, Address(rsp, 8 * wordSize)); | |
| 4249 movq(rsi, Address(rsp, 9 * wordSize)); | |
| 4250 movq(rbp, Address(rsp, 10 * wordSize)); | |
| 4251 // skip rsp | |
| 4252 movq(rbx, Address(rsp, 12 * wordSize)); | |
| 4253 movq(rdx, Address(rsp, 13 * wordSize)); | |
| 4254 movq(rcx, Address(rsp, 14 * wordSize)); | |
| 4255 movq(rax, Address(rsp, 15 * wordSize)); | |
| 4256 | |
| 4257 addq(rsp, 16 * wordSize); | |
| 4258 } | |
| 4259 | |
|
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4260 void Assembler::popcntq(Register dst, Address src) { |
|
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4261 assert(VM_Version::supports_popcnt(), "must support"); |
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4262 InstructionMark im(this); |
|
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4263 emit_byte(0xF3); |
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4264 prefixq(src, dst); |
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4265 emit_byte(0x0F); |
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4266 emit_byte(0xB8); |
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4267 emit_operand(dst, src); |
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4268 } |
|
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4269 |
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4270 void Assembler::popcntq(Register dst, Register src) { |
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4271 assert(VM_Version::supports_popcnt(), "must support"); |
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4272 emit_byte(0xF3); |
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4273 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
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4274 emit_byte(0x0F); |
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4275 emit_byte(0xB8); |
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4276 emit_byte(0xC0 | encode); |
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4277 } |
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4278 |
| 304 | 4279 void Assembler::popq(Address dst) { |
| 4280 InstructionMark im(this); | |
| 4281 prefixq(dst); | |
| 4282 emit_byte(0x8F); | |
| 4283 emit_operand(rax, dst); | |
| 4284 } | |
| 4285 | |
| 4286 void Assembler::pusha() { // 64bit | |
| 4287 // we have to store original rsp. ABI says that 128 bytes | |
| 4288 // below rsp are local scratch. | |
| 4289 movq(Address(rsp, -5 * wordSize), rsp); | |
| 4290 | |
| 4291 subq(rsp, 16 * wordSize); | |
| 4292 | |
| 4293 movq(Address(rsp, 15 * wordSize), rax); | |
| 4294 movq(Address(rsp, 14 * wordSize), rcx); | |
| 4295 movq(Address(rsp, 13 * wordSize), rdx); | |
| 4296 movq(Address(rsp, 12 * wordSize), rbx); | |
| 4297 // skip rsp | |
| 4298 movq(Address(rsp, 10 * wordSize), rbp); | |
| 4299 movq(Address(rsp, 9 * wordSize), rsi); | |
| 4300 movq(Address(rsp, 8 * wordSize), rdi); | |
| 4301 movq(Address(rsp, 7 * wordSize), r8); | |
| 4302 movq(Address(rsp, 6 * wordSize), r9); | |
| 4303 movq(Address(rsp, 5 * wordSize), r10); | |
| 4304 movq(Address(rsp, 4 * wordSize), r11); | |
| 4305 movq(Address(rsp, 3 * wordSize), r12); | |
| 4306 movq(Address(rsp, 2 * wordSize), r13); | |
| 4307 movq(Address(rsp, wordSize), r14); | |
| 4308 movq(Address(rsp, 0), r15); | |
| 4309 } | |
| 4310 | |
| 4311 void Assembler::pushq(Address src) { | |
| 4312 InstructionMark im(this); | |
| 4313 prefixq(src); | |
| 4314 emit_byte(0xFF); | |
| 4315 emit_operand(rsi, src); | |
| 4316 } | |
| 4317 | |
| 4318 void Assembler::rclq(Register dst, int imm8) { | |
| 4319 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
| 4320 int encode = prefixq_and_encode(dst->encoding()); | |
| 4321 if (imm8 == 1) { | |
| 4322 emit_byte(0xD1); | |
| 4323 emit_byte(0xD0 | encode); | |
| 4324 } else { | |
| 4325 emit_byte(0xC1); | |
| 4326 emit_byte(0xD0 | encode); | |
| 4327 emit_byte(imm8); | |
| 4328 } | |
| 4329 } | |
| 4330 void Assembler::sarq(Register dst, int imm8) { | |
| 4331 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
| 4332 int encode = prefixq_and_encode(dst->encoding()); | |
| 4333 if (imm8 == 1) { | |
| 4334 emit_byte(0xD1); | |
| 4335 emit_byte(0xF8 | encode); | |
| 4336 } else { | |
| 4337 emit_byte(0xC1); | |
| 4338 emit_byte(0xF8 | encode); | |
| 4339 emit_byte(imm8); | |
| 4340 } | |
| 4341 } | |
| 4342 | |
| 4343 void Assembler::sarq(Register dst) { | |
| 4344 int encode = prefixq_and_encode(dst->encoding()); | |
| 4345 emit_byte(0xD3); | |
| 4346 emit_byte(0xF8 | encode); | |
| 4347 } | |
|
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4348 |
| 304 | 4349 void Assembler::sbbq(Address dst, int32_t imm32) { |
| 4350 InstructionMark im(this); | |
| 4351 prefixq(dst); | |
| 4352 emit_arith_operand(0x81, rbx, dst, imm32); | |
| 4353 } | |
| 4354 | |
| 4355 void Assembler::sbbq(Register dst, int32_t imm32) { | |
| 4356 (void) prefixq_and_encode(dst->encoding()); | |
| 4357 emit_arith(0x81, 0xD8, dst, imm32); | |
| 4358 } | |
| 4359 | |
| 4360 void Assembler::sbbq(Register dst, Address src) { | |
| 4361 InstructionMark im(this); | |
| 4362 prefixq(src, dst); | |
| 4363 emit_byte(0x1B); | |
| 4364 emit_operand(dst, src); | |
| 4365 } | |
| 4366 | |
| 4367 void Assembler::sbbq(Register dst, Register src) { | |
| 4368 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4369 emit_arith(0x1B, 0xC0, dst, src); | |
| 4370 } | |
| 4371 | |
| 4372 void Assembler::shlq(Register dst, int imm8) { | |
| 4373 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
| 4374 int encode = prefixq_and_encode(dst->encoding()); | |
| 4375 if (imm8 == 1) { | |
| 4376 emit_byte(0xD1); | |
| 4377 emit_byte(0xE0 | encode); | |
| 4378 } else { | |
| 4379 emit_byte(0xC1); | |
| 4380 emit_byte(0xE0 | encode); | |
| 4381 emit_byte(imm8); | |
| 4382 } | |
| 4383 } | |
| 4384 | |
| 4385 void Assembler::shlq(Register dst) { | |
| 4386 int encode = prefixq_and_encode(dst->encoding()); | |
| 4387 emit_byte(0xD3); | |
| 4388 emit_byte(0xE0 | encode); | |
| 4389 } | |
| 4390 | |
| 4391 void Assembler::shrq(Register dst, int imm8) { | |
| 4392 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
| 4393 int encode = prefixq_and_encode(dst->encoding()); | |
| 4394 emit_byte(0xC1); | |
| 4395 emit_byte(0xE8 | encode); | |
| 4396 emit_byte(imm8); | |
| 4397 } | |
| 4398 | |
| 4399 void Assembler::shrq(Register dst) { | |
| 4400 int encode = prefixq_and_encode(dst->encoding()); | |
| 4401 emit_byte(0xD3); | |
| 4402 emit_byte(0xE8 | encode); | |
| 4403 } | |
| 4404 | |
| 4405 void Assembler::subq(Address dst, int32_t imm32) { | |
| 4406 InstructionMark im(this); | |
| 4407 prefixq(dst); | |
|
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4408 emit_arith_operand(0x81, rbp, dst, imm32); |
| 304 | 4409 } |
| 4410 | |
| 4411 void Assembler::subq(Address dst, Register src) { | |
| 4412 InstructionMark im(this); | |
| 4413 prefixq(dst, src); | |
| 4414 emit_byte(0x29); | |
| 4415 emit_operand(src, dst); | |
| 4416 } | |
| 4417 | |
|
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4418 void Assembler::subq(Register dst, int32_t imm32) { |
|
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4419 (void) prefixq_and_encode(dst->encoding()); |
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4420 emit_arith(0x81, 0xE8, dst, imm32); |
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4421 } |
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4422 |
| 304 | 4423 void Assembler::subq(Register dst, Address src) { |
| 4424 InstructionMark im(this); | |
| 4425 prefixq(src, dst); | |
| 4426 emit_byte(0x2B); | |
| 4427 emit_operand(dst, src); | |
| 4428 } | |
| 4429 | |
| 4430 void Assembler::subq(Register dst, Register src) { | |
| 4431 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4432 emit_arith(0x2B, 0xC0, dst, src); | |
| 4433 } | |
| 4434 | |
| 4435 void Assembler::testq(Register dst, int32_t imm32) { | |
| 4436 // not using emit_arith because test | |
| 4437 // doesn't support sign-extension of | |
| 4438 // 8bit operands | |
| 4439 int encode = dst->encoding(); | |
| 4440 if (encode == 0) { | |
| 4441 prefix(REX_W); | |
| 4442 emit_byte(0xA9); | |
| 4443 } else { | |
| 4444 encode = prefixq_and_encode(encode); | |
| 4445 emit_byte(0xF7); | |
| 4446 emit_byte(0xC0 | encode); | |
| 4447 } | |
| 4448 emit_long(imm32); | |
| 4449 } | |
| 4450 | |
| 4451 void Assembler::testq(Register dst, Register src) { | |
| 4452 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4453 emit_arith(0x85, 0xC0, dst, src); | |
| 4454 } | |
| 4455 | |
| 4456 void Assembler::xaddq(Address dst, Register src) { | |
| 4457 InstructionMark im(this); | |
| 4458 prefixq(dst, src); | |
| 71 | 4459 emit_byte(0x0F); |
| 304 | 4460 emit_byte(0xC1); |
| 4461 emit_operand(src, dst); | |
| 4462 } | |
| 4463 | |
| 4464 void Assembler::xchgq(Register dst, Address src) { | |
| 4465 InstructionMark im(this); | |
| 4466 prefixq(src, dst); | |
| 4467 emit_byte(0x87); | |
| 4468 emit_operand(dst, src); | |
| 4469 } | |
| 4470 | |
| 4471 void Assembler::xchgq(Register dst, Register src) { | |
| 4472 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4473 emit_byte(0x87); | |
| 4474 emit_byte(0xc0 | encode); | |
| 4475 } | |
| 4476 | |
| 4477 void Assembler::xorq(Register dst, Register src) { | |
| 4478 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
| 4479 emit_arith(0x33, 0xC0, dst, src); | |
| 4480 } | |
| 4481 | |
| 4482 void Assembler::xorq(Register dst, Address src) { | |
| 4483 InstructionMark im(this); | |
| 4484 prefixq(src, dst); | |
| 4485 emit_byte(0x33); | |
| 4486 emit_operand(dst, src); | |
| 4487 } | |
| 4488 | |
| 4489 #endif // !LP64 | |
| 4490 | |
| 4491 static Assembler::Condition reverse[] = { | |
| 4492 Assembler::noOverflow /* overflow = 0x0 */ , | |
| 4493 Assembler::overflow /* noOverflow = 0x1 */ , | |
| 4494 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ , | |
| 4495 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ , | |
| 4496 Assembler::notZero /* zero = 0x4, equal = 0x4 */ , | |
| 4497 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ , | |
| 4498 Assembler::above /* belowEqual = 0x6 */ , | |
| 4499 Assembler::belowEqual /* above = 0x7 */ , | |
| 4500 Assembler::positive /* negative = 0x8 */ , | |
| 4501 Assembler::negative /* positive = 0x9 */ , | |
| 4502 Assembler::noParity /* parity = 0xa */ , | |
| 4503 Assembler::parity /* noParity = 0xb */ , | |
| 4504 Assembler::greaterEqual /* less = 0xc */ , | |
| 4505 Assembler::less /* greaterEqual = 0xd */ , | |
| 4506 Assembler::greater /* lessEqual = 0xe */ , | |
| 4507 Assembler::lessEqual /* greater = 0xf, */ | |
| 4508 | |
| 4509 }; | |
| 4510 | |
| 0 | 4511 |
| 4512 // Implementation of MacroAssembler | |
| 4513 | |
| 304 | 4514 // First all the versions that have distinct versions depending on 32/64 bit |
| 4515 // Unless the difference is trivial (1 line or so). | |
| 4516 | |
| 4517 #ifndef _LP64 | |
| 4518 | |
| 4519 // 32bit versions | |
| 4520 | |
| 0 | 4521 Address MacroAssembler::as_Address(AddressLiteral adr) { |
| 4522 return Address(adr.target(), adr.rspec()); | |
| 4523 } | |
| 4524 | |
| 4525 Address MacroAssembler::as_Address(ArrayAddress adr) { | |
| 4526 return Address::make_array(adr); | |
| 4527 } | |
| 4528 | |
| 304 | 4529 int MacroAssembler::biased_locking_enter(Register lock_reg, |
| 4530 Register obj_reg, | |
| 4531 Register swap_reg, | |
| 4532 Register tmp_reg, | |
| 4533 bool swap_reg_contains_mark, | |
| 4534 Label& done, | |
| 4535 Label* slow_case, | |
| 4536 BiasedLockingCounters* counters) { | |
| 4537 assert(UseBiasedLocking, "why call this otherwise?"); | |
| 4538 assert(swap_reg == rax, "swap_reg must be rax, for cmpxchg"); | |
| 4539 assert_different_registers(lock_reg, obj_reg, swap_reg); | |
| 4540 | |
| 4541 if (PrintBiasedLockingStatistics && counters == NULL) | |
| 4542 counters = BiasedLocking::counters(); | |
| 4543 | |
| 4544 bool need_tmp_reg = false; | |
| 4545 if (tmp_reg == noreg) { | |
| 4546 need_tmp_reg = true; | |
| 4547 tmp_reg = lock_reg; | |
| 4548 } else { | |
| 4549 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); | |
| 4550 } | |
| 4551 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); | |
| 4552 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); | |
| 4553 Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes()); | |
| 4554 Address saved_mark_addr(lock_reg, 0); | |
| 4555 | |
| 4556 // Biased locking | |
| 4557 // See whether the lock is currently biased toward our thread and | |
| 4558 // whether the epoch is still valid | |
| 4559 // Note that the runtime guarantees sufficient alignment of JavaThread | |
| 4560 // pointers to allow age to be placed into low bits | |
| 4561 // First check to see whether biasing is even enabled for this object | |
| 4562 Label cas_label; | |
| 4563 int null_check_offset = -1; | |
| 4564 if (!swap_reg_contains_mark) { | |
| 4565 null_check_offset = offset(); | |
| 4566 movl(swap_reg, mark_addr); | |
| 4567 } | |
| 4568 if (need_tmp_reg) { | |
| 4569 push(tmp_reg); | |
| 4570 } | |
| 4571 movl(tmp_reg, swap_reg); | |
| 4572 andl(tmp_reg, markOopDesc::biased_lock_mask_in_place); | |
| 4573 cmpl(tmp_reg, markOopDesc::biased_lock_pattern); | |
| 4574 if (need_tmp_reg) { | |
| 4575 pop(tmp_reg); | |
| 4576 } | |
| 4577 jcc(Assembler::notEqual, cas_label); | |
| 4578 // The bias pattern is present in the object's header. Need to check | |
| 4579 // whether the bias owner and the epoch are both still current. | |
| 4580 // Note that because there is no current thread register on x86 we | |
| 4581 // need to store off the mark word we read out of the object to | |
| 4582 // avoid reloading it and needing to recheck invariants below. This | |
| 4583 // store is unfortunate but it makes the overall code shorter and | |
| 4584 // simpler. | |
| 4585 movl(saved_mark_addr, swap_reg); | |
| 4586 if (need_tmp_reg) { | |
| 4587 push(tmp_reg); | |
| 4588 } | |
| 4589 get_thread(tmp_reg); | |
| 4590 xorl(swap_reg, tmp_reg); | |
| 4591 if (swap_reg_contains_mark) { | |
| 4592 null_check_offset = offset(); | |
| 4593 } | |
| 4594 movl(tmp_reg, klass_addr); | |
| 4595 xorl(swap_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | |
| 4596 andl(swap_reg, ~((int) markOopDesc::age_mask_in_place)); | |
| 4597 if (need_tmp_reg) { | |
| 4598 pop(tmp_reg); | |
| 4599 } | |
| 4600 if (counters != NULL) { | |
| 4601 cond_inc32(Assembler::zero, | |
| 4602 ExternalAddress((address)counters->biased_lock_entry_count_addr())); | |
| 4603 } | |
| 4604 jcc(Assembler::equal, done); | |
| 4605 | |
| 4606 Label try_revoke_bias; | |
| 4607 Label try_rebias; | |
| 4608 | |
| 4609 // At this point we know that the header has the bias pattern and | |
| 4610 // that we are not the bias owner in the current epoch. We need to | |
| 4611 // figure out more details about the state of the header in order to | |
| 4612 // know what operations can be legally performed on the object's | |
| 4613 // header. | |
| 4614 | |
| 4615 // If the low three bits in the xor result aren't clear, that means | |
| 4616 // the prototype header is no longer biased and we have to revoke | |
| 4617 // the bias on this object. | |
| 4618 testl(swap_reg, markOopDesc::biased_lock_mask_in_place); | |
| 4619 jcc(Assembler::notZero, try_revoke_bias); | |
| 4620 | |
| 4621 // Biasing is still enabled for this data type. See whether the | |
| 4622 // epoch of the current bias is still valid, meaning that the epoch | |
| 4623 // bits of the mark word are equal to the epoch bits of the | |
| 4624 // prototype header. (Note that the prototype header's epoch bits | |
| 4625 // only change at a safepoint.) If not, attempt to rebias the object | |
| 4626 // toward the current thread. Note that we must be absolutely sure | |
| 4627 // that the current epoch is invalid in order to do this because | |
| 4628 // otherwise the manipulations it performs on the mark word are | |
| 4629 // illegal. | |
| 4630 testl(swap_reg, markOopDesc::epoch_mask_in_place); | |
| 4631 jcc(Assembler::notZero, try_rebias); | |
| 4632 | |
| 4633 // The epoch of the current bias is still valid but we know nothing | |
| 4634 // about the owner; it might be set or it might be clear. Try to | |
| 4635 // acquire the bias of the object using an atomic operation. If this | |
| 4636 // fails we will go in to the runtime to revoke the object's bias. | |
| 4637 // Note that we first construct the presumed unbiased header so we | |
| 4638 // don't accidentally blow away another thread's valid bias. | |
| 4639 movl(swap_reg, saved_mark_addr); | |
| 4640 andl(swap_reg, | |
| 4641 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); | |
| 4642 if (need_tmp_reg) { | |
| 4643 push(tmp_reg); | |
| 4644 } | |
| 4645 get_thread(tmp_reg); | |
| 4646 orl(tmp_reg, swap_reg); | |
| 4647 if (os::is_MP()) { | |
| 4648 lock(); | |
| 4649 } | |
| 4650 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); | |
| 4651 if (need_tmp_reg) { | |
| 4652 pop(tmp_reg); | |
| 4653 } | |
| 4654 // If the biasing toward our thread failed, this means that | |
| 4655 // another thread succeeded in biasing it toward itself and we | |
| 4656 // need to revoke that bias. The revocation will occur in the | |
| 4657 // interpreter runtime in the slow case. | |
| 4658 if (counters != NULL) { | |
| 4659 cond_inc32(Assembler::zero, | |
| 4660 ExternalAddress((address)counters->anonymously_biased_lock_entry_count_addr())); | |
| 4661 } | |
| 4662 if (slow_case != NULL) { | |
| 4663 jcc(Assembler::notZero, *slow_case); | |
| 4664 } | |
| 4665 jmp(done); | |
| 4666 | |
| 4667 bind(try_rebias); | |
| 4668 // At this point we know the epoch has expired, meaning that the | |
| 4669 // current "bias owner", if any, is actually invalid. Under these | |
| 4670 // circumstances _only_, we are allowed to use the current header's | |
| 4671 // value as the comparison value when doing the cas to acquire the | |
| 4672 // bias in the current epoch. In other words, we allow transfer of | |
| 4673 // the bias from one thread to another directly in this situation. | |
| 4674 // | |
| 4675 // FIXME: due to a lack of registers we currently blow away the age | |
| 4676 // bits in this situation. Should attempt to preserve them. | |
| 4677 if (need_tmp_reg) { | |
| 4678 push(tmp_reg); | |
| 4679 } | |
| 4680 get_thread(tmp_reg); | |
| 4681 movl(swap_reg, klass_addr); | |
| 4682 orl(tmp_reg, Address(swap_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | |
| 4683 movl(swap_reg, saved_mark_addr); | |
| 4684 if (os::is_MP()) { | |
| 4685 lock(); | |
| 4686 } | |
| 4687 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); | |
| 4688 if (need_tmp_reg) { | |
| 4689 pop(tmp_reg); | |
| 4690 } | |
| 4691 // If the biasing toward our thread failed, then another thread | |
| 4692 // succeeded in biasing it toward itself and we need to revoke that | |
| 4693 // bias. The revocation will occur in the runtime in the slow case. | |
| 4694 if (counters != NULL) { | |
| 4695 cond_inc32(Assembler::zero, | |
| 4696 ExternalAddress((address)counters->rebiased_lock_entry_count_addr())); | |
| 4697 } | |
| 4698 if (slow_case != NULL) { | |
| 4699 jcc(Assembler::notZero, *slow_case); | |
| 4700 } | |
| 4701 jmp(done); | |
| 4702 | |
| 4703 bind(try_revoke_bias); | |
| 4704 // The prototype mark in the klass doesn't have the bias bit set any | |
| 4705 // more, indicating that objects of this data type are not supposed | |
| 4706 // to be biased any more. We are going to try to reset the mark of | |
| 4707 // this object to the prototype value and fall through to the | |
| 4708 // CAS-based locking scheme. Note that if our CAS fails, it means | |
| 4709 // that another thread raced us for the privilege of revoking the | |
| 4710 // bias of this particular object, so it's okay to continue in the | |
| 4711 // normal locking code. | |
| 4712 // | |
| 4713 // FIXME: due to a lack of registers we currently blow away the age | |
| 4714 // bits in this situation. Should attempt to preserve them. | |
| 4715 movl(swap_reg, saved_mark_addr); | |
| 4716 if (need_tmp_reg) { | |
| 4717 push(tmp_reg); | |
| 4718 } | |
| 4719 movl(tmp_reg, klass_addr); | |
| 4720 movl(tmp_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | |
| 4721 if (os::is_MP()) { | |
| 4722 lock(); | |
| 4723 } | |
| 4724 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); | |
| 4725 if (need_tmp_reg) { | |
| 4726 pop(tmp_reg); | |
| 4727 } | |
| 4728 // Fall through to the normal CAS-based lock, because no matter what | |
| 4729 // the result of the above CAS, some thread must have succeeded in | |
| 4730 // removing the bias bit from the object's header. | |
| 4731 if (counters != NULL) { | |
| 4732 cond_inc32(Assembler::zero, | |
| 4733 ExternalAddress((address)counters->revoked_lock_entry_count_addr())); | |
| 4734 } | |
| 4735 | |
| 4736 bind(cas_label); | |
| 4737 | |
| 4738 return null_check_offset; | |
| 4739 } | |
| 4740 void MacroAssembler::call_VM_leaf_base(address entry_point, | |
| 4741 int number_of_arguments) { | |
| 4742 call(RuntimeAddress(entry_point)); | |
| 4743 increment(rsp, number_of_arguments * wordSize); | |
| 4744 } | |
| 4745 | |
| 4746 void MacroAssembler::cmpoop(Address src1, jobject obj) { | |
| 4747 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
| 4748 } | |
| 4749 | |
| 4750 void MacroAssembler::cmpoop(Register src1, jobject obj) { | |
| 4751 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
| 4752 } | |
| 4753 | |
| 4754 void MacroAssembler::extend_sign(Register hi, Register lo) { | |
| 4755 // According to Intel Doc. AP-526, "Integer Divide", p.18. | |
| 4756 if (VM_Version::is_P6() && hi == rdx && lo == rax) { | |
| 4757 cdql(); | |
| 4758 } else { | |
| 4759 movl(hi, lo); | |
| 4760 sarl(hi, 31); | |
| 4761 } | |
| 4762 } | |
| 4763 | |
| 0 | 4764 void MacroAssembler::fat_nop() { |
| 4765 // A 5 byte nop that is safe for patching (see patch_verified_entry) | |
| 4766 emit_byte(0x26); // es: | |
| 4767 emit_byte(0x2e); // cs: | |
| 4768 emit_byte(0x64); // fs: | |
| 4769 emit_byte(0x65); // gs: | |
| 4770 emit_byte(0x90); | |
| 4771 } | |
| 4772 | |
| 304 | 4773 void MacroAssembler::jC2(Register tmp, Label& L) { |
| 4774 // set parity bit if FPU flag C2 is set (via rax) | |
| 4775 save_rax(tmp); | |
| 4776 fwait(); fnstsw_ax(); | |
| 4777 sahf(); | |
| 4778 restore_rax(tmp); | |
| 4779 // branch | |
| 4780 jcc(Assembler::parity, L); | |
| 4781 } | |
| 4782 | |
| 4783 void MacroAssembler::jnC2(Register tmp, Label& L) { | |
| 4784 // set parity bit if FPU flag C2 is set (via rax) | |
| 4785 save_rax(tmp); | |
| 4786 fwait(); fnstsw_ax(); | |
| 4787 sahf(); | |
| 4788 restore_rax(tmp); | |
| 4789 // branch | |
| 4790 jcc(Assembler::noParity, L); | |
| 4791 } | |
| 4792 | |
| 0 | 4793 // 32bit can do a case table jump in one instruction but we no longer allow the base |
| 4794 // to be installed in the Address class | |
| 4795 void MacroAssembler::jump(ArrayAddress entry) { | |
| 4796 jmp(as_Address(entry)); | |
| 4797 } | |
| 4798 | |
| 304 | 4799 // Note: y_lo will be destroyed |
| 4800 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { | |
| 4801 // Long compare for Java (semantics as described in JVM spec.) | |
| 4802 Label high, low, done; | |
| 4803 | |
| 4804 cmpl(x_hi, y_hi); | |
| 4805 jcc(Assembler::less, low); | |
| 4806 jcc(Assembler::greater, high); | |
| 4807 // x_hi is the return register | |
| 4808 xorl(x_hi, x_hi); | |
| 4809 cmpl(x_lo, y_lo); | |
| 4810 jcc(Assembler::below, low); | |
| 4811 jcc(Assembler::equal, done); | |
| 4812 | |
| 4813 bind(high); | |
| 4814 xorl(x_hi, x_hi); | |
| 4815 increment(x_hi); | |
| 4816 jmp(done); | |
| 4817 | |
| 4818 bind(low); | |
| 4819 xorl(x_hi, x_hi); | |
| 4820 decrementl(x_hi); | |
| 4821 | |
| 4822 bind(done); | |
| 4823 } | |
| 4824 | |
| 4825 void MacroAssembler::lea(Register dst, AddressLiteral src) { | |
| 4826 mov_literal32(dst, (int32_t)src.target(), src.rspec()); | |
| 0 | 4827 } |
| 4828 | |
| 4829 void MacroAssembler::lea(Address dst, AddressLiteral adr) { | |
| 4830 // leal(dst, as_Address(adr)); | |
| 304 | 4831 // see note in movl as to why we must use a move |
| 0 | 4832 mov_literal32(dst, (int32_t) adr.target(), adr.rspec()); |
| 4833 } | |
| 4834 | |
| 4835 void MacroAssembler::leave() { | |
| 304 | 4836 mov(rsp, rbp); |
| 4837 pop(rbp); | |
| 4838 } | |
| 0 | 4839 |
| 4840 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) { | |
| 4841 // Multiplication of two Java long values stored on the stack | |
| 4842 // as illustrated below. Result is in rdx:rax. | |
| 4843 // | |
| 4844 // rsp ---> [ ?? ] \ \ | |
| 4845 // .... | y_rsp_offset | | |
| 4846 // [ y_lo ] / (in bytes) | x_rsp_offset | |
| 4847 // [ y_hi ] | (in bytes) | |
| 4848 // .... | | |
| 4849 // [ x_lo ] / | |
| 4850 // [ x_hi ] | |
| 4851 // .... | |
| 4852 // | |
| 4853 // Basic idea: lo(result) = lo(x_lo * y_lo) | |
| 4854 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) | |
| 4855 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset); | |
| 4856 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset); | |
| 4857 Label quick; | |
| 4858 // load x_hi, y_hi and check if quick | |
| 4859 // multiplication is possible | |
| 4860 movl(rbx, x_hi); | |
| 4861 movl(rcx, y_hi); | |
| 4862 movl(rax, rbx); | |
| 4863 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0 | |
| 4864 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply | |
| 4865 // do full multiplication | |
| 4866 // 1st step | |
| 4867 mull(y_lo); // x_hi * y_lo | |
| 4868 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx, | |
| 4869 // 2nd step | |
| 4870 movl(rax, x_lo); | |
| 4871 mull(rcx); // x_lo * y_hi | |
| 4872 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx, | |
| 4873 // 3rd step | |
| 4874 bind(quick); // note: rbx, = 0 if quick multiply! | |
| 4875 movl(rax, x_lo); | |
| 4876 mull(y_lo); // x_lo * y_lo | |
| 4877 addl(rdx, rbx); // correct hi(x_lo * y_lo) | |
| 4878 } | |
| 4879 | |
| 304 | 4880 void MacroAssembler::lneg(Register hi, Register lo) { |
| 4881 negl(lo); | |
| 4882 adcl(hi, 0); | |
| 4883 negl(hi); | |
| 4884 } | |
| 0 | 4885 |
| 4886 void MacroAssembler::lshl(Register hi, Register lo) { | |
| 4887 // Java shift left long support (semantics as described in JVM spec., p.305) | |
| 4888 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n)) | |
| 4889 // shift value is in rcx ! | |
| 4890 assert(hi != rcx, "must not use rcx"); | |
| 4891 assert(lo != rcx, "must not use rcx"); | |
| 4892 const Register s = rcx; // shift count | |
| 4893 const int n = BitsPerWord; | |
| 4894 Label L; | |
| 4895 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) | |
| 4896 cmpl(s, n); // if (s < n) | |
| 4897 jcc(Assembler::less, L); // else (s >= n) | |
| 4898 movl(hi, lo); // x := x << n | |
| 4899 xorl(lo, lo); | |
| 4900 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! | |
| 4901 bind(L); // s (mod n) < n | |
| 4902 shldl(hi, lo); // x := x << s | |
| 4903 shll(lo); | |
| 4904 } | |
| 4905 | |
| 4906 | |
| 4907 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) { | |
| 4908 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310) | |
| 4909 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n)) | |
| 4910 assert(hi != rcx, "must not use rcx"); | |
| 4911 assert(lo != rcx, "must not use rcx"); | |
| 4912 const Register s = rcx; // shift count | |
| 4913 const int n = BitsPerWord; | |
| 4914 Label L; | |
| 4915 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) | |
| 4916 cmpl(s, n); // if (s < n) | |
| 4917 jcc(Assembler::less, L); // else (s >= n) | |
| 4918 movl(lo, hi); // x := x >> n | |
| 4919 if (sign_extension) sarl(hi, 31); | |
| 4920 else xorl(hi, hi); | |
| 4921 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! | |
| 4922 bind(L); // s (mod n) < n | |
| 4923 shrdl(lo, hi); // x := x >> s | |
| 4924 if (sign_extension) sarl(hi); | |
| 4925 else shrl(hi); | |
| 4926 } | |
| 4927 | |
| 304 | 4928 void MacroAssembler::movoop(Register dst, jobject obj) { |
| 4929 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
| 4930 } | |
| 4931 | |
| 4932 void MacroAssembler::movoop(Address dst, jobject obj) { | |
| 4933 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
| 4934 } | |
| 4935 | |
| 4936 void MacroAssembler::movptr(Register dst, AddressLiteral src) { | |
| 4937 if (src.is_lval()) { | |
| 4938 mov_literal32(dst, (intptr_t)src.target(), src.rspec()); | |
| 4939 } else { | |
| 4940 movl(dst, as_Address(src)); | |
| 4941 } | |
| 4942 } | |
| 4943 | |
| 4944 void MacroAssembler::movptr(ArrayAddress dst, Register src) { | |
| 4945 movl(as_Address(dst), src); | |
| 4946 } | |
| 4947 | |
| 4948 void MacroAssembler::movptr(Register dst, ArrayAddress src) { | |
| 4949 movl(dst, as_Address(src)); | |
| 4950 } | |
| 4951 | |
| 4952 // src should NEVER be a real pointer. Use AddressLiteral for true pointers | |
| 4953 void MacroAssembler::movptr(Address dst, intptr_t src) { | |
| 4954 movl(dst, src); | |
| 4955 } | |
| 4956 | |
| 4957 | |
| 4958 void MacroAssembler::pop_callee_saved_registers() { | |
| 4959 pop(rcx); | |
| 4960 pop(rdx); | |
| 4961 pop(rdi); | |
| 4962 pop(rsi); | |
| 4963 } | |
| 4964 | |
| 4965 void MacroAssembler::pop_fTOS() { | |
| 4966 fld_d(Address(rsp, 0)); | |
| 4967 addl(rsp, 2 * wordSize); | |
| 4968 } | |
| 4969 | |
| 4970 void MacroAssembler::push_callee_saved_registers() { | |
| 4971 push(rsi); | |
| 4972 push(rdi); | |
| 4973 push(rdx); | |
| 4974 push(rcx); | |
| 4975 } | |
| 4976 | |
| 4977 void MacroAssembler::push_fTOS() { | |
| 4978 subl(rsp, 2 * wordSize); | |
| 4979 fstp_d(Address(rsp, 0)); | |
| 4980 } | |
| 4981 | |
| 4982 | |
| 4983 void MacroAssembler::pushoop(jobject obj) { | |
| 4984 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate()); | |
| 4985 } | |
| 4986 | |
| 4987 | |
| 4988 void MacroAssembler::pushptr(AddressLiteral src) { | |
| 4989 if (src.is_lval()) { | |
| 4990 push_literal32((int32_t)src.target(), src.rspec()); | |
| 4991 } else { | |
| 4992 pushl(as_Address(src)); | |
| 4993 } | |
| 4994 } | |
| 4995 | |
| 4996 void MacroAssembler::set_word_if_not_zero(Register dst) { | |
| 4997 xorl(dst, dst); | |
| 4998 set_byte_if_not_zero(dst); | |
| 4999 } | |
| 5000 | |
| 5001 static void pass_arg0(MacroAssembler* masm, Register arg) { | |
| 5002 masm->push(arg); | |
| 5003 } | |
| 5004 | |
| 5005 static void pass_arg1(MacroAssembler* masm, Register arg) { | |
| 5006 masm->push(arg); | |
| 5007 } | |
| 5008 | |
| 5009 static void pass_arg2(MacroAssembler* masm, Register arg) { | |
| 5010 masm->push(arg); | |
| 5011 } | |
| 5012 | |
| 5013 static void pass_arg3(MacroAssembler* masm, Register arg) { | |
| 5014 masm->push(arg); | |
| 5015 } | |
| 5016 | |
| 5017 #ifndef PRODUCT | |
| 5018 extern "C" void findpc(intptr_t x); | |
| 5019 #endif | |
| 5020 | |
| 5021 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) { | |
| 5022 // In order to get locks to work, we need to fake a in_VM state | |
| 5023 JavaThread* thread = JavaThread::current(); | |
| 5024 JavaThreadState saved_state = thread->thread_state(); | |
| 5025 thread->set_thread_state(_thread_in_vm); | |
| 5026 if (ShowMessageBoxOnError) { | |
| 5027 JavaThread* thread = JavaThread::current(); | |
| 5028 JavaThreadState saved_state = thread->thread_state(); | |
| 5029 thread->set_thread_state(_thread_in_vm); | |
| 5030 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { | |
| 5031 ttyLocker ttyl; | |
| 5032 BytecodeCounter::print(); | |
| 5033 } | |
| 5034 // To see where a verify_oop failed, get $ebx+40/X for this frame. | |
| 5035 // This is the value of eip which points to where verify_oop will return. | |
| 5036 if (os::message_box(msg, "Execution stopped, print registers?")) { | |
| 5037 ttyLocker ttyl; | |
| 5038 tty->print_cr("eip = 0x%08x", eip); | |
| 5039 #ifndef PRODUCT | |
|
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|
5040 if ((WizardMode || Verbose) && PrintMiscellaneous) { |
|
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|
5041 tty->cr(); |
|
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|
5042 findpc(eip); |
|
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|
5043 tty->cr(); |
|
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|
5044 } |
| 304 | 5045 #endif |
|
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|
5046 tty->print_cr("rax = 0x%08x", rax); |
|
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|
5047 tty->print_cr("rbx = 0x%08x", rbx); |
| 304 | 5048 tty->print_cr("rcx = 0x%08x", rcx); |
| 5049 tty->print_cr("rdx = 0x%08x", rdx); | |
| 5050 tty->print_cr("rdi = 0x%08x", rdi); | |
| 5051 tty->print_cr("rsi = 0x%08x", rsi); | |
|
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|
5052 tty->print_cr("rbp = 0x%08x", rbp); |
| 304 | 5053 tty->print_cr("rsp = 0x%08x", rsp); |
| 5054 BREAKPOINT; | |
|
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|
5055 assert(false, "start up GDB"); |
| 304 | 5056 } |
| 5057 } else { | |
| 5058 ttyLocker ttyl; | |
| 5059 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg); | |
| 5060 assert(false, "DEBUG MESSAGE"); | |
| 5061 } | |
| 5062 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); | |
| 5063 } | |
| 5064 | |
| 5065 void MacroAssembler::stop(const char* msg) { | |
| 5066 ExternalAddress message((address)msg); | |
| 5067 // push address of message | |
| 5068 pushptr(message.addr()); | |
| 5069 { Label L; call(L, relocInfo::none); bind(L); } // push eip | |
| 5070 pusha(); // push registers | |
| 5071 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32))); | |
| 5072 hlt(); | |
| 5073 } | |
| 5074 | |
| 5075 void MacroAssembler::warn(const char* msg) { | |
| 5076 push_CPU_state(); | |
| 5077 | |
| 5078 ExternalAddress message((address) msg); | |
| 5079 // push address of message | |
| 5080 pushptr(message.addr()); | |
| 5081 | |
| 5082 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning))); | |
| 5083 addl(rsp, wordSize); // discard argument | |
| 5084 pop_CPU_state(); | |
| 5085 } | |
| 5086 | |
| 5087 #else // _LP64 | |
| 5088 | |
| 5089 // 64 bit versions | |
| 5090 | |
| 5091 Address MacroAssembler::as_Address(AddressLiteral adr) { | |
| 5092 // amd64 always does this as a pc-rel | |
| 5093 // we can be absolute or disp based on the instruction type | |
| 5094 // jmp/call are displacements others are absolute | |
| 5095 assert(!adr.is_lval(), "must be rval"); | |
| 5096 assert(reachable(adr), "must be"); | |
| 5097 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc()); | |
| 5098 | |
| 5099 } | |
| 5100 | |
| 5101 Address MacroAssembler::as_Address(ArrayAddress adr) { | |
| 5102 AddressLiteral base = adr.base(); | |
| 5103 lea(rscratch1, base); | |
| 5104 Address index = adr.index(); | |
| 5105 assert(index._disp == 0, "must not have disp"); // maybe it can? | |
| 5106 Address array(rscratch1, index._index, index._scale, index._disp); | |
| 5107 return array; | |
| 5108 } | |
| 5109 | |
| 5110 int MacroAssembler::biased_locking_enter(Register lock_reg, | |
| 5111 Register obj_reg, | |
| 5112 Register swap_reg, | |
| 5113 Register tmp_reg, | |
| 5114 bool swap_reg_contains_mark, | |
| 5115 Label& done, | |
| 5116 Label* slow_case, | |
| 5117 BiasedLockingCounters* counters) { | |
| 5118 assert(UseBiasedLocking, "why call this otherwise?"); | |
| 5119 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq"); | |
| 5120 assert(tmp_reg != noreg, "tmp_reg must be supplied"); | |
| 5121 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); | |
| 5122 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); | |
| 5123 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); | |
| 5124 Address saved_mark_addr(lock_reg, 0); | |
| 5125 | |
| 5126 if (PrintBiasedLockingStatistics && counters == NULL) | |
| 5127 counters = BiasedLocking::counters(); | |
| 5128 | |
| 5129 // Biased locking | |
| 5130 // See whether the lock is currently biased toward our thread and | |
| 5131 // whether the epoch is still valid | |
| 5132 // Note that the runtime guarantees sufficient alignment of JavaThread | |
| 5133 // pointers to allow age to be placed into low bits | |
| 5134 // First check to see whether biasing is even enabled for this object | |
| 5135 Label cas_label; | |
| 5136 int null_check_offset = -1; | |
| 5137 if (!swap_reg_contains_mark) { | |
| 5138 null_check_offset = offset(); | |
| 5139 movq(swap_reg, mark_addr); | |
| 5140 } | |
| 5141 movq(tmp_reg, swap_reg); | |
| 5142 andq(tmp_reg, markOopDesc::biased_lock_mask_in_place); | |
| 5143 cmpq(tmp_reg, markOopDesc::biased_lock_pattern); | |
| 5144 jcc(Assembler::notEqual, cas_label); | |
| 5145 // The bias pattern is present in the object's header. Need to check | |
| 5146 // whether the bias owner and the epoch are both still current. | |
| 5147 load_prototype_header(tmp_reg, obj_reg); | |
| 5148 orq(tmp_reg, r15_thread); | |
| 5149 xorq(tmp_reg, swap_reg); | |
| 5150 andq(tmp_reg, ~((int) markOopDesc::age_mask_in_place)); | |
| 5151 if (counters != NULL) { | |
| 5152 cond_inc32(Assembler::zero, | |
| 5153 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr())); | |
| 5154 } | |
| 0 | 5155 jcc(Assembler::equal, done); |
| 5156 | |
| 304 | 5157 Label try_revoke_bias; |
| 5158 Label try_rebias; | |
| 5159 | |
| 5160 // At this point we know that the header has the bias pattern and | |
| 5161 // that we are not the bias owner in the current epoch. We need to | |
| 5162 // figure out more details about the state of the header in order to | |
| 5163 // know what operations can be legally performed on the object's | |
| 5164 // header. | |
| 5165 | |
| 5166 // If the low three bits in the xor result aren't clear, that means | |
| 5167 // the prototype header is no longer biased and we have to revoke | |
| 5168 // the bias on this object. | |
| 5169 testq(tmp_reg, markOopDesc::biased_lock_mask_in_place); | |
| 5170 jcc(Assembler::notZero, try_revoke_bias); | |
| 5171 | |
| 5172 // Biasing is still enabled for this data type. See whether the | |
| 5173 // epoch of the current bias is still valid, meaning that the epoch | |
| 5174 // bits of the mark word are equal to the epoch bits of the | |
| 5175 // prototype header. (Note that the prototype header's epoch bits | |
| 5176 // only change at a safepoint.) If not, attempt to rebias the object | |
| 5177 // toward the current thread. Note that we must be absolutely sure | |
| 5178 // that the current epoch is invalid in order to do this because | |
| 5179 // otherwise the manipulations it performs on the mark word are | |
| 5180 // illegal. | |
| 5181 testq(tmp_reg, markOopDesc::epoch_mask_in_place); | |
| 5182 jcc(Assembler::notZero, try_rebias); | |
| 5183 | |
| 5184 // The epoch of the current bias is still valid but we know nothing | |
| 5185 // about the owner; it might be set or it might be clear. Try to | |
| 5186 // acquire the bias of the object using an atomic operation. If this | |
| 5187 // fails we will go in to the runtime to revoke the object's bias. | |
| 5188 // Note that we first construct the presumed unbiased header so we | |
| 5189 // don't accidentally blow away another thread's valid bias. | |
| 5190 andq(swap_reg, | |
| 5191 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); | |
| 5192 movq(tmp_reg, swap_reg); | |
| 5193 orq(tmp_reg, r15_thread); | |
| 5194 if (os::is_MP()) { | |
| 5195 lock(); | |
| 5196 } | |
| 5197 cmpxchgq(tmp_reg, Address(obj_reg, 0)); | |
| 5198 // If the biasing toward our thread failed, this means that | |
| 5199 // another thread succeeded in biasing it toward itself and we | |
| 5200 // need to revoke that bias. The revocation will occur in the | |
| 5201 // interpreter runtime in the slow case. | |
| 5202 if (counters != NULL) { | |
| 5203 cond_inc32(Assembler::zero, | |
| 5204 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr())); | |
| 5205 } | |
| 5206 if (slow_case != NULL) { | |
| 5207 jcc(Assembler::notZero, *slow_case); | |
| 5208 } | |
| 0 | 5209 jmp(done); |
| 5210 | |
| 304 | 5211 bind(try_rebias); |
| 5212 // At this point we know the epoch has expired, meaning that the | |
| 5213 // current "bias owner", if any, is actually invalid. Under these | |
| 5214 // circumstances _only_, we are allowed to use the current header's | |
| 5215 // value as the comparison value when doing the cas to acquire the | |
| 5216 // bias in the current epoch. In other words, we allow transfer of | |
| 5217 // the bias from one thread to another directly in this situation. | |
| 5218 // | |
| 5219 // FIXME: due to a lack of registers we currently blow away the age | |
| 5220 // bits in this situation. Should attempt to preserve them. | |
| 5221 load_prototype_header(tmp_reg, obj_reg); | |
| 5222 orq(tmp_reg, r15_thread); | |
| 5223 if (os::is_MP()) { | |
| 5224 lock(); | |
| 5225 } | |
| 5226 cmpxchgq(tmp_reg, Address(obj_reg, 0)); | |
| 5227 // If the biasing toward our thread failed, then another thread | |
| 5228 // succeeded in biasing it toward itself and we need to revoke that | |
| 5229 // bias. The revocation will occur in the runtime in the slow case. | |
| 5230 if (counters != NULL) { | |
| 5231 cond_inc32(Assembler::zero, | |
| 5232 ExternalAddress((address) counters->rebiased_lock_entry_count_addr())); | |
| 5233 } | |
| 5234 if (slow_case != NULL) { | |
| 5235 jcc(Assembler::notZero, *slow_case); | |
| 0 | 5236 } |
| 5237 jmp(done); | |
| 5238 | |
| 304 | 5239 bind(try_revoke_bias); |
| 5240 // The prototype mark in the klass doesn't have the bias bit set any | |
| 5241 // more, indicating that objects of this data type are not supposed | |
| 5242 // to be biased any more. We are going to try to reset the mark of | |
| 5243 // this object to the prototype value and fall through to the | |
| 5244 // CAS-based locking scheme. Note that if our CAS fails, it means | |
| 5245 // that another thread raced us for the privilege of revoking the | |
| 5246 // bias of this particular object, so it's okay to continue in the | |
| 5247 // normal locking code. | |
| 5248 // | |
| 5249 // FIXME: due to a lack of registers we currently blow away the age | |
| 5250 // bits in this situation. Should attempt to preserve them. | |
| 5251 load_prototype_header(tmp_reg, obj_reg); | |
| 5252 if (os::is_MP()) { | |
| 5253 lock(); | |
| 5254 } | |
| 5255 cmpxchgq(tmp_reg, Address(obj_reg, 0)); | |
| 5256 // Fall through to the normal CAS-based lock, because no matter what | |
| 5257 // the result of the above CAS, some thread must have succeeded in | |
| 5258 // removing the bias bit from the object's header. | |
| 5259 if (counters != NULL) { | |
| 5260 cond_inc32(Assembler::zero, | |
| 5261 ExternalAddress((address) counters->revoked_lock_entry_count_addr())); | |
| 5262 } | |
| 5263 | |
| 5264 bind(cas_label); | |
| 5265 | |
| 5266 return null_check_offset; | |
| 5267 } | |
| 5268 | |
| 5269 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) { | |
| 5270 Label L, E; | |
| 5271 | |
| 5272 #ifdef _WIN64 | |
| 5273 // Windows always allocates space for it's register args | |
| 5274 assert(num_args <= 4, "only register arguments supported"); | |
| 5275 subq(rsp, frame::arg_reg_save_area_bytes); | |
| 5276 #endif | |
| 5277 | |
| 5278 // Align stack if necessary | |
| 5279 testl(rsp, 15); | |
| 5280 jcc(Assembler::zero, L); | |
| 5281 | |
| 5282 subq(rsp, 8); | |
| 5283 { | |
| 5284 call(RuntimeAddress(entry_point)); | |
| 5285 } | |
| 5286 addq(rsp, 8); | |
| 5287 jmp(E); | |
| 5288 | |
| 5289 bind(L); | |
| 5290 { | |
| 5291 call(RuntimeAddress(entry_point)); | |
| 5292 } | |
| 5293 | |
| 5294 bind(E); | |
| 5295 | |
| 5296 #ifdef _WIN64 | |
| 5297 // restore stack pointer | |
| 5298 addq(rsp, frame::arg_reg_save_area_bytes); | |
| 5299 #endif | |
| 5300 | |
| 5301 } | |
| 5302 | |
| 5303 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) { | |
| 5304 assert(!src2.is_lval(), "should use cmpptr"); | |
| 5305 | |
| 5306 if (reachable(src2)) { | |
| 5307 cmpq(src1, as_Address(src2)); | |
| 5308 } else { | |
| 5309 lea(rscratch1, src2); | |
| 5310 Assembler::cmpq(src1, Address(rscratch1, 0)); | |
| 5311 } | |
| 5312 } | |
| 5313 | |
| 5314 int MacroAssembler::corrected_idivq(Register reg) { | |
| 5315 // Full implementation of Java ldiv and lrem; checks for special | |
| 5316 // case as described in JVM spec., p.243 & p.271. The function | |
| 5317 // returns the (pc) offset of the idivl instruction - may be needed | |
| 5318 // for implicit exceptions. | |
| 5319 // | |
| 5320 // normal case special case | |
| 5321 // | |
| 5322 // input : rax: dividend min_long | |
| 5323 // reg: divisor (may not be eax/edx) -1 | |
| 5324 // | |
| 5325 // output: rax: quotient (= rax idiv reg) min_long | |
| 5326 // rdx: remainder (= rax irem reg) 0 | |
| 5327 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register"); | |
| 5328 static const int64_t min_long = 0x8000000000000000; | |
| 5329 Label normal_case, special_case; | |
| 5330 | |
| 5331 // check for special case | |
| 5332 cmp64(rax, ExternalAddress((address) &min_long)); | |
| 5333 jcc(Assembler::notEqual, normal_case); | |
| 5334 xorl(rdx, rdx); // prepare rdx for possible special case (where | |
| 5335 // remainder = 0) | |
| 5336 cmpq(reg, -1); | |
| 5337 jcc(Assembler::equal, special_case); | |
| 5338 | |
| 5339 // handle normal case | |
| 5340 bind(normal_case); | |
| 5341 cdqq(); | |
| 5342 int idivq_offset = offset(); | |
| 5343 idivq(reg); | |
| 5344 | |
| 5345 // normal and special case exit | |
| 5346 bind(special_case); | |
| 5347 | |
| 5348 return idivq_offset; | |
| 5349 } | |
| 5350 | |
| 5351 void MacroAssembler::decrementq(Register reg, int value) { | |
| 5352 if (value == min_jint) { subq(reg, value); return; } | |
| 5353 if (value < 0) { incrementq(reg, -value); return; } | |
| 5354 if (value == 0) { ; return; } | |
| 5355 if (value == 1 && UseIncDec) { decq(reg) ; return; } | |
| 5356 /* else */ { subq(reg, value) ; return; } | |
| 5357 } | |
| 5358 | |
| 5359 void MacroAssembler::decrementq(Address dst, int value) { | |
| 5360 if (value == min_jint) { subq(dst, value); return; } | |
| 5361 if (value < 0) { incrementq(dst, -value); return; } | |
| 5362 if (value == 0) { ; return; } | |
| 5363 if (value == 1 && UseIncDec) { decq(dst) ; return; } | |
| 5364 /* else */ { subq(dst, value) ; return; } | |
| 5365 } | |
| 5366 | |
| 5367 void MacroAssembler::fat_nop() { | |
| 5368 // A 5 byte nop that is safe for patching (see patch_verified_entry) | |
| 5369 // Recommened sequence from 'Software Optimization Guide for the AMD | |
| 5370 // Hammer Processor' | |
| 5371 emit_byte(0x66); | |
| 5372 emit_byte(0x66); | |
| 5373 emit_byte(0x90); | |
| 5374 emit_byte(0x66); | |
| 5375 emit_byte(0x90); | |
| 5376 } | |
| 5377 | |
| 5378 void MacroAssembler::incrementq(Register reg, int value) { | |
| 5379 if (value == min_jint) { addq(reg, value); return; } | |
| 5380 if (value < 0) { decrementq(reg, -value); return; } | |
| 5381 if (value == 0) { ; return; } | |
| 5382 if (value == 1 && UseIncDec) { incq(reg) ; return; } | |
| 5383 /* else */ { addq(reg, value) ; return; } | |
| 5384 } | |
| 5385 | |
| 5386 void MacroAssembler::incrementq(Address dst, int value) { | |
| 5387 if (value == min_jint) { addq(dst, value); return; } | |
| 5388 if (value < 0) { decrementq(dst, -value); return; } | |
| 5389 if (value == 0) { ; return; } | |
| 5390 if (value == 1 && UseIncDec) { incq(dst) ; return; } | |
| 5391 /* else */ { addq(dst, value) ; return; } | |
| 5392 } | |
| 5393 | |
| 5394 // 32bit can do a case table jump in one instruction but we no longer allow the base | |
| 5395 // to be installed in the Address class | |
| 5396 void MacroAssembler::jump(ArrayAddress entry) { | |
| 5397 lea(rscratch1, entry.base()); | |
| 5398 Address dispatch = entry.index(); | |
| 5399 assert(dispatch._base == noreg, "must be"); | |
| 5400 dispatch._base = rscratch1; | |
| 5401 jmp(dispatch); | |
| 5402 } | |
| 5403 | |
| 5404 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { | |
| 5405 ShouldNotReachHere(); // 64bit doesn't use two regs | |
| 5406 cmpq(x_lo, y_lo); | |
| 5407 } | |
| 5408 | |
| 5409 void MacroAssembler::lea(Register dst, AddressLiteral src) { | |
| 5410 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); | |
| 5411 } | |
| 5412 | |
| 5413 void MacroAssembler::lea(Address dst, AddressLiteral adr) { | |
| 5414 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec()); | |
| 5415 movptr(dst, rscratch1); | |
| 5416 } | |
| 5417 | |
| 5418 void MacroAssembler::leave() { | |
| 5419 // %%% is this really better? Why not on 32bit too? | |
| 5420 emit_byte(0xC9); // LEAVE | |
| 5421 } | |
| 5422 | |
| 5423 void MacroAssembler::lneg(Register hi, Register lo) { | |
| 5424 ShouldNotReachHere(); // 64bit doesn't use two regs | |
| 5425 negq(lo); | |
| 5426 } | |
| 5427 | |
| 5428 void MacroAssembler::movoop(Register dst, jobject obj) { | |
| 5429 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate()); | |
| 5430 } | |
| 5431 | |
| 5432 void MacroAssembler::movoop(Address dst, jobject obj) { | |
| 5433 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate()); | |
| 5434 movq(dst, rscratch1); | |
| 5435 } | |
| 5436 | |
| 5437 void MacroAssembler::movptr(Register dst, AddressLiteral src) { | |
| 5438 if (src.is_lval()) { | |
| 5439 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); | |
| 5440 } else { | |
| 5441 if (reachable(src)) { | |
| 5442 movq(dst, as_Address(src)); | |
| 5443 } else { | |
| 5444 lea(rscratch1, src); | |
| 5445 movq(dst, Address(rscratch1,0)); | |
| 0 | 5446 } |
| 304 | 5447 } |
| 5448 } | |
| 5449 | |
| 5450 void MacroAssembler::movptr(ArrayAddress dst, Register src) { | |
| 5451 movq(as_Address(dst), src); | |
| 5452 } | |
| 5453 | |
| 5454 void MacroAssembler::movptr(Register dst, ArrayAddress src) { | |
| 5455 movq(dst, as_Address(src)); | |
| 5456 } | |
| 5457 | |
| 5458 // src should NEVER be a real pointer. Use AddressLiteral for true pointers | |
| 5459 void MacroAssembler::movptr(Address dst, intptr_t src) { | |
| 5460 mov64(rscratch1, src); | |
| 5461 movq(dst, rscratch1); | |
| 5462 } | |
| 5463 | |
| 5464 // These are mostly for initializing NULL | |
| 5465 void MacroAssembler::movptr(Address dst, int32_t src) { | |
| 5466 movslq(dst, src); | |
| 5467 } | |
| 5468 | |
| 5469 void MacroAssembler::movptr(Register dst, int32_t src) { | |
| 5470 mov64(dst, (intptr_t)src); | |
| 5471 } | |
| 5472 | |
| 5473 void MacroAssembler::pushoop(jobject obj) { | |
| 5474 movoop(rscratch1, obj); | |
| 5475 push(rscratch1); | |
| 5476 } | |
| 5477 | |
| 5478 void MacroAssembler::pushptr(AddressLiteral src) { | |
| 5479 lea(rscratch1, src); | |
| 5480 if (src.is_lval()) { | |
| 5481 push(rscratch1); | |
| 5482 } else { | |
| 5483 pushq(Address(rscratch1, 0)); | |
| 5484 } | |
| 5485 } | |
| 5486 | |
| 5487 void MacroAssembler::reset_last_Java_frame(bool clear_fp, | |
| 5488 bool clear_pc) { | |
| 5489 // we must set sp to zero to clear frame | |
|
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|
5490 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); |
| 304 | 5491 // must clear fp, so that compiled frames are not confused; it is |
| 5492 // possible that we need it only for debugging | |
| 5493 if (clear_fp) { | |
|
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|
5494 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); |
| 304 | 5495 } |
| 5496 | |
| 5497 if (clear_pc) { | |
|
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|
5498 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); |
| 304 | 5499 } |
| 5500 } | |
| 5501 | |
| 5502 void MacroAssembler::set_last_Java_frame(Register last_java_sp, | |
| 5503 Register last_java_fp, | |
| 5504 address last_java_pc) { | |
| 5505 // determine last_java_sp register | |
| 5506 if (!last_java_sp->is_valid()) { | |
| 5507 last_java_sp = rsp; | |
| 5508 } | |
| 5509 | |
| 5510 // last_java_fp is optional | |
| 5511 if (last_java_fp->is_valid()) { | |
| 5512 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), | |
| 5513 last_java_fp); | |
| 5514 } | |
| 5515 | |
| 5516 // last_java_pc is optional | |
| 5517 if (last_java_pc != NULL) { | |
| 5518 Address java_pc(r15_thread, | |
| 5519 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()); | |
| 5520 lea(rscratch1, InternalAddress(last_java_pc)); | |
| 5521 movptr(java_pc, rscratch1); | |
| 5522 } | |
| 5523 | |
| 5524 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp); | |
| 5525 } | |
| 5526 | |
| 5527 static void pass_arg0(MacroAssembler* masm, Register arg) { | |
| 5528 if (c_rarg0 != arg ) { | |
| 5529 masm->mov(c_rarg0, arg); | |
| 5530 } | |
| 5531 } | |
| 5532 | |
| 5533 static void pass_arg1(MacroAssembler* masm, Register arg) { | |
| 5534 if (c_rarg1 != arg ) { | |
| 5535 masm->mov(c_rarg1, arg); | |
| 5536 } | |
| 5537 } | |
| 5538 | |
| 5539 static void pass_arg2(MacroAssembler* masm, Register arg) { | |
| 5540 if (c_rarg2 != arg ) { | |
| 5541 masm->mov(c_rarg2, arg); | |
| 5542 } | |
| 5543 } | |
| 5544 | |
| 5545 static void pass_arg3(MacroAssembler* masm, Register arg) { | |
| 5546 if (c_rarg3 != arg ) { | |
| 5547 masm->mov(c_rarg3, arg); | |
| 5548 } | |
| 5549 } | |
| 5550 | |
| 5551 void MacroAssembler::stop(const char* msg) { | |
| 5552 address rip = pc(); | |
| 5553 pusha(); // get regs on stack | |
| 5554 lea(c_rarg0, ExternalAddress((address) msg)); | |
| 5555 lea(c_rarg1, InternalAddress(rip)); | |
| 5556 movq(c_rarg2, rsp); // pass pointer to regs array | |
| 5557 andq(rsp, -16); // align stack as required by ABI | |
| 5558 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64))); | |
| 5559 hlt(); | |
| 5560 } | |
| 5561 | |
| 5562 void MacroAssembler::warn(const char* msg) { | |
|
1976
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diff
changeset
|
5563 push(rsp); |
| 304 | 5564 andq(rsp, -16); // align stack as required by push_CPU_state and call |
| 5565 | |
| 5566 push_CPU_state(); // keeps alignment at 16 bytes | |
| 5567 lea(c_rarg0, ExternalAddress((address) msg)); | |
| 5568 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0); | |
| 5569 pop_CPU_state(); | |
|
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diff
changeset
|
5570 pop(rsp); |
| 304 | 5571 } |
| 5572 | |
| 5573 #ifndef PRODUCT | |
| 5574 extern "C" void findpc(intptr_t x); | |
| 5575 #endif | |
| 5576 | |
| 5577 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) { | |
| 5578 // In order to get locks to work, we need to fake a in_VM state | |
| 5579 if (ShowMessageBoxOnError ) { | |
| 5580 JavaThread* thread = JavaThread::current(); | |
| 5581 JavaThreadState saved_state = thread->thread_state(); | |
| 5582 thread->set_thread_state(_thread_in_vm); | |
| 5583 #ifndef PRODUCT | |
| 5584 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { | |
| 5585 ttyLocker ttyl; | |
| 5586 BytecodeCounter::print(); | |
| 0 | 5587 } |
| 304 | 5588 #endif |
| 5589 // To see where a verify_oop failed, get $ebx+40/X for this frame. | |
| 5590 // XXX correct this offset for amd64 | |
| 5591 // This is the value of eip which points to where verify_oop will return. | |
| 5592 if (os::message_box(msg, "Execution stopped, print registers?")) { | |
| 5593 ttyLocker ttyl; | |
| 5594 tty->print_cr("rip = 0x%016lx", pc); | |
| 5595 #ifndef PRODUCT | |
| 5596 tty->cr(); | |
| 5597 findpc(pc); | |
| 5598 tty->cr(); | |
| 5599 #endif | |
| 5600 tty->print_cr("rax = 0x%016lx", regs[15]); | |
| 5601 tty->print_cr("rbx = 0x%016lx", regs[12]); | |
| 5602 tty->print_cr("rcx = 0x%016lx", regs[14]); | |
| 5603 tty->print_cr("rdx = 0x%016lx", regs[13]); | |
| 5604 tty->print_cr("rdi = 0x%016lx", regs[8]); | |
| 5605 tty->print_cr("rsi = 0x%016lx", regs[9]); | |
| 5606 tty->print_cr("rbp = 0x%016lx", regs[10]); | |
| 5607 tty->print_cr("rsp = 0x%016lx", regs[11]); | |
| 5608 tty->print_cr("r8 = 0x%016lx", regs[7]); | |
| 5609 tty->print_cr("r9 = 0x%016lx", regs[6]); | |
| 5610 tty->print_cr("r10 = 0x%016lx", regs[5]); | |
| 5611 tty->print_cr("r11 = 0x%016lx", regs[4]); | |
| 5612 tty->print_cr("r12 = 0x%016lx", regs[3]); | |
| 5613 tty->print_cr("r13 = 0x%016lx", regs[2]); | |
| 5614 tty->print_cr("r14 = 0x%016lx", regs[1]); | |
| 5615 tty->print_cr("r15 = 0x%016lx", regs[0]); | |
| 5616 BREAKPOINT; | |
| 0 | 5617 } |
| 304 | 5618 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); |
| 5619 } else { | |
| 5620 ttyLocker ttyl; | |
| 5621 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", | |
| 5622 msg); | |
| 5623 } | |
| 5624 } | |
| 5625 | |
| 5626 #endif // _LP64 | |
| 5627 | |
| 5628 // Now versions that are common to 32/64 bit | |
| 5629 | |
| 5630 void MacroAssembler::addptr(Register dst, int32_t imm32) { | |
| 5631 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32)); | |
| 5632 } | |
| 5633 | |
| 5634 void MacroAssembler::addptr(Register dst, Register src) { | |
| 5635 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); | |
| 5636 } | |
| 5637 | |
| 5638 void MacroAssembler::addptr(Address dst, Register src) { | |
| 5639 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); | |
| 5640 } | |
| 5641 | |
| 5642 void MacroAssembler::align(int modulus) { | |
| 5643 if (offset() % modulus != 0) { | |
| 5644 nop(modulus - (offset() % modulus)); | |
| 5645 } | |
| 5646 } | |
| 5647 | |
| 5648 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) { | |
| 1060 | 5649 if (reachable(src)) { |
| 5650 andpd(dst, as_Address(src)); | |
| 5651 } else { | |
| 5652 lea(rscratch1, src); | |
| 5653 andpd(dst, Address(rscratch1, 0)); | |
| 5654 } | |
| 304 | 5655 } |
| 5656 | |
| 5657 void MacroAssembler::andptr(Register dst, int32_t imm32) { | |
| 5658 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32)); | |
| 5659 } | |
| 5660 | |
| 5661 void MacroAssembler::atomic_incl(AddressLiteral counter_addr) { | |
| 5662 pushf(); | |
| 5663 if (os::is_MP()) | |
| 5664 lock(); | |
| 5665 incrementl(counter_addr); | |
| 5666 popf(); | |
| 5667 } | |
| 5668 | |
| 5669 // Writes to stack successive pages until offset reached to check for | |
| 5670 // stack overflow + shadow pages. This clobbers tmp. | |
| 5671 void MacroAssembler::bang_stack_size(Register size, Register tmp) { | |
| 5672 movptr(tmp, rsp); | |
| 5673 // Bang stack for total size given plus shadow page size. | |
| 5674 // Bang one page at a time because large size can bang beyond yellow and | |
| 5675 // red zones. | |
| 5676 Label loop; | |
| 5677 bind(loop); | |
| 5678 movl(Address(tmp, (-os::vm_page_size())), size ); | |
| 5679 subptr(tmp, os::vm_page_size()); | |
| 5680 subl(size, os::vm_page_size()); | |
| 5681 jcc(Assembler::greater, loop); | |
| 5682 | |
| 5683 // Bang down shadow pages too. | |
| 5684 // The -1 because we already subtracted 1 page. | |
| 5685 for (int i = 0; i< StackShadowPages-1; i++) { | |
| 5686 // this could be any sized move but this is can be a debugging crumb | |
| 5687 // so the bigger the better. | |
| 5688 movptr(Address(tmp, (-i*os::vm_page_size())), size ); | |
| 5689 } | |
| 5690 } | |
| 5691 | |
| 5692 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) { | |
| 5693 assert(UseBiasedLocking, "why call this otherwise?"); | |
| 5694 | |
| 5695 // Check for biased locking unlock case, which is a no-op | |
| 5696 // Note: we do not have to check the thread ID for two reasons. | |
| 5697 // First, the interpreter checks for IllegalMonitorStateException at | |
| 5698 // a higher level. Second, if the bias was revoked while we held the | |
| 5699 // lock, the object could not be rebiased toward another thread, so | |
| 5700 // the bias bit would be clear. | |
| 5701 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); | |
| 5702 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place); | |
| 5703 cmpptr(temp_reg, markOopDesc::biased_lock_pattern); | |
| 5704 jcc(Assembler::equal, done); | |
| 5705 } | |
| 5706 | |
| 5707 void MacroAssembler::c2bool(Register x) { | |
| 5708 // implements x == 0 ? 0 : 1 | |
| 5709 // note: must only look at least-significant byte of x | |
| 5710 // since C-style booleans are stored in one byte | |
| 5711 // only! (was bug) | |
| 5712 andl(x, 0xFF); | |
| 5713 setb(Assembler::notZero, x); | |
| 5714 } | |
| 5715 | |
| 5716 // Wouldn't need if AddressLiteral version had new name | |
| 5717 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) { | |
| 5718 Assembler::call(L, rtype); | |
| 5719 } | |
| 5720 | |
| 5721 void MacroAssembler::call(Register entry) { | |
| 5722 Assembler::call(entry); | |
| 5723 } | |
| 5724 | |
| 5725 void MacroAssembler::call(AddressLiteral entry) { | |
| 5726 if (reachable(entry)) { | |
| 5727 Assembler::call_literal(entry.target(), entry.rspec()); | |
| 5728 } else { | |
| 5729 lea(rscratch1, entry); | |
| 5730 Assembler::call(rscratch1); | |
| 5731 } | |
| 5732 } | |
| 5733 | |
| 5734 // Implementation of call_VM versions | |
| 5735 | |
| 5736 void MacroAssembler::call_VM(Register oop_result, | |
| 5737 address entry_point, | |
| 5738 bool check_exceptions) { | |
| 5739 Label C, E; | |
| 5740 call(C, relocInfo::none); | |
| 5741 jmp(E); | |
| 5742 | |
| 5743 bind(C); | |
| 5744 call_VM_helper(oop_result, entry_point, 0, check_exceptions); | |
| 5745 ret(0); | |
| 5746 | |
| 5747 bind(E); | |
| 5748 } | |
| 5749 | |
| 5750 void MacroAssembler::call_VM(Register oop_result, | |
| 5751 address entry_point, | |
| 5752 Register arg_1, | |
| 5753 bool check_exceptions) { | |
| 5754 Label C, E; | |
| 5755 call(C, relocInfo::none); | |
| 5756 jmp(E); | |
| 5757 | |
| 5758 bind(C); | |
| 5759 pass_arg1(this, arg_1); | |
| 5760 call_VM_helper(oop_result, entry_point, 1, check_exceptions); | |
| 5761 ret(0); | |
| 5762 | |
| 5763 bind(E); | |
| 5764 } | |
| 5765 | |
| 5766 void MacroAssembler::call_VM(Register oop_result, | |
| 5767 address entry_point, | |
| 5768 Register arg_1, | |
| 5769 Register arg_2, | |
| 5770 bool check_exceptions) { | |
| 5771 Label C, E; | |
| 5772 call(C, relocInfo::none); | |
| 5773 jmp(E); | |
| 5774 | |
| 5775 bind(C); | |
| 5776 | |
| 5777 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
| 5778 | |
| 5779 pass_arg2(this, arg_2); | |
| 5780 pass_arg1(this, arg_1); | |
| 5781 call_VM_helper(oop_result, entry_point, 2, check_exceptions); | |
| 5782 ret(0); | |
| 5783 | |
| 5784 bind(E); | |
| 5785 } | |
| 5786 | |
| 5787 void MacroAssembler::call_VM(Register oop_result, | |
| 5788 address entry_point, | |
| 5789 Register arg_1, | |
| 5790 Register arg_2, | |
| 5791 Register arg_3, | |
| 5792 bool check_exceptions) { | |
| 5793 Label C, E; | |
| 5794 call(C, relocInfo::none); | |
| 5795 jmp(E); | |
| 5796 | |
| 5797 bind(C); | |
| 5798 | |
| 5799 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); | |
| 5800 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); | |
| 5801 pass_arg3(this, arg_3); | |
| 5802 | |
| 5803 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
| 5804 pass_arg2(this, arg_2); | |
| 5805 | |
| 5806 pass_arg1(this, arg_1); | |
| 5807 call_VM_helper(oop_result, entry_point, 3, check_exceptions); | |
| 5808 ret(0); | |
| 5809 | |
| 5810 bind(E); | |
| 5811 } | |
| 5812 | |
| 5813 void MacroAssembler::call_VM(Register oop_result, | |
| 5814 Register last_java_sp, | |
| 5815 address entry_point, | |
| 5816 int number_of_arguments, | |
| 5817 bool check_exceptions) { | |
| 5818 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); | |
| 5819 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); | |
| 5820 } | |
| 5821 | |
| 5822 void MacroAssembler::call_VM(Register oop_result, | |
| 5823 Register last_java_sp, | |
| 5824 address entry_point, | |
| 5825 Register arg_1, | |
| 5826 bool check_exceptions) { | |
| 5827 pass_arg1(this, arg_1); | |
| 5828 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); | |
| 5829 } | |
| 5830 | |
| 5831 void MacroAssembler::call_VM(Register oop_result, | |
| 5832 Register last_java_sp, | |
| 5833 address entry_point, | |
| 5834 Register arg_1, | |
| 5835 Register arg_2, | |
| 5836 bool check_exceptions) { | |
| 5837 | |
| 5838 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
| 5839 pass_arg2(this, arg_2); | |
| 5840 pass_arg1(this, arg_1); | |
| 5841 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); | |
| 5842 } | |
| 5843 | |
| 5844 void MacroAssembler::call_VM(Register oop_result, | |
| 5845 Register last_java_sp, | |
| 5846 address entry_point, | |
| 5847 Register arg_1, | |
| 5848 Register arg_2, | |
| 5849 Register arg_3, | |
| 5850 bool check_exceptions) { | |
| 5851 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); | |
| 5852 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); | |
| 5853 pass_arg3(this, arg_3); | |
| 5854 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
| 5855 pass_arg2(this, arg_2); | |
| 5856 pass_arg1(this, arg_1); | |
| 5857 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); | |
| 5858 } | |
| 5859 | |
| 5860 void MacroAssembler::call_VM_base(Register oop_result, | |
| 5861 Register java_thread, | |
| 5862 Register last_java_sp, | |
| 5863 address entry_point, | |
| 5864 int number_of_arguments, | |
| 5865 bool check_exceptions) { | |
| 5866 // determine java_thread register | |
| 5867 if (!java_thread->is_valid()) { | |
| 5868 #ifdef _LP64 | |
| 5869 java_thread = r15_thread; | |
| 5870 #else | |
| 5871 java_thread = rdi; | |
| 5872 get_thread(java_thread); | |
| 5873 #endif // LP64 | |
| 5874 } | |
| 5875 // determine last_java_sp register | |
| 5876 if (!last_java_sp->is_valid()) { | |
| 5877 last_java_sp = rsp; | |
| 5878 } | |
| 5879 // debugging support | |
| 5880 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); | |
| 5881 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register")); | |
|
1976
0fc262af204f
6780143: hs203t003 hits SIGSEGV/EXCEPTION_ACCESS_VIOLATION with -XX:+UseCompressedOops
coleenp
parents:
1972
diff
changeset
|
5882 #ifdef ASSERT |
|
0fc262af204f
6780143: hs203t003 hits SIGSEGV/EXCEPTION_ACCESS_VIOLATION with -XX:+UseCompressedOops
coleenp
parents:
1972
diff
changeset
|
5883 LP64_ONLY(if (UseCompressedOops) verify_heapbase("call_VM_base");) |
|
0fc262af204f
6780143: hs203t003 hits SIGSEGV/EXCEPTION_ACCESS_VIOLATION with -XX:+UseCompressedOops
coleenp
parents:
1972
diff
changeset
|
5884 #endif // ASSERT |
|
0fc262af204f
6780143: hs203t003 hits SIGSEGV/EXCEPTION_ACCESS_VIOLATION with -XX:+UseCompressedOops
coleenp
parents:
1972
diff
changeset
|
5885 |
| 304 | 5886 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); |
| 5887 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); | |
| 5888 | |
| 5889 // push java thread (becomes first argument of C function) | |
| 5890 | |
| 5891 NOT_LP64(push(java_thread); number_of_arguments++); | |
| 5892 LP64_ONLY(mov(c_rarg0, r15_thread)); | |
| 5893 | |
| 5894 // set last Java frame before call | |
| 5895 assert(last_java_sp != rbp, "can't use ebp/rbp"); | |
| 5896 | |
| 5897 // Only interpreter should have to set fp | |
| 5898 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL); | |
| 5899 | |
| 5900 // do the call, remove parameters | |
| 5901 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments); | |
| 5902 | |
| 5903 // restore the thread (cannot use the pushed argument since arguments | |
| 5904 // may be overwritten by C code generated by an optimizing compiler); | |
| 5905 // however can use the register value directly if it is callee saved. | |
| 5906 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) { | |
| 5907 // rdi & rsi (also r15) are callee saved -> nothing to do | |
| 5908 #ifdef ASSERT | |
| 5909 guarantee(java_thread != rax, "change this code"); | |
| 5910 push(rax); | |
| 5911 { Label L; | |
| 5912 get_thread(rax); | |
| 5913 cmpptr(java_thread, rax); | |
| 5914 jcc(Assembler::equal, L); | |
| 5915 stop("MacroAssembler::call_VM_base: rdi not callee saved?"); | |
| 5916 bind(L); | |
| 0 | 5917 } |
| 304 | 5918 pop(rax); |
| 5919 #endif | |
| 5920 } else { | |
| 5921 get_thread(java_thread); | |
| 5922 } | |
| 5923 // reset last Java frame | |
| 5924 // Only interpreter should have to clear fp | |
| 5925 reset_last_Java_frame(java_thread, true, false); | |
| 5926 | |
| 5927 #ifndef CC_INTERP | |
| 5928 // C++ interp handles this in the interpreter | |
| 5929 check_and_handle_popframe(java_thread); | |
| 5930 check_and_handle_earlyret(java_thread); | |
| 5931 #endif /* CC_INTERP */ | |
| 5932 | |
| 5933 if (check_exceptions) { | |
| 5934 // check for pending exceptions (java_thread is set upon return) | |
| 5935 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD); | |
| 5936 #ifndef _LP64 | |
| 5937 jump_cc(Assembler::notEqual, | |
| 5938 RuntimeAddress(StubRoutines::forward_exception_entry())); | |
| 5939 #else | |
| 5940 // This used to conditionally jump to forward_exception however it is | |
| 5941 // possible if we relocate that the branch will not reach. So we must jump | |
| 5942 // around so we can always reach | |
| 5943 | |
| 5944 Label ok; | |
| 5945 jcc(Assembler::equal, ok); | |
| 5946 jump(RuntimeAddress(StubRoutines::forward_exception_entry())); | |
| 5947 bind(ok); | |
| 5948 #endif // LP64 | |
| 5949 } | |
| 5950 | |
| 5951 // get oop result if there is one and reset the value in the thread | |
| 5952 if (oop_result->is_valid()) { | |
| 5953 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset())); | |
|
512
db4caa99ef11
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents:
420
diff
changeset
|
5954 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD); |
| 304 | 5955 verify_oop(oop_result, "broken oop in call_VM_base"); |
| 5956 } | |
| 5957 } | |
| 5958 | |
| 5959 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { | |
| 5960 | |
| 5961 // Calculate the value for last_Java_sp | |
| 5962 // somewhat subtle. call_VM does an intermediate call | |
| 5963 // which places a return address on the stack just under the | |
| 5964 // stack pointer as the user finsihed with it. This allows | |
| 5965 // use to retrieve last_Java_pc from last_Java_sp[-1]. | |
| 5966 // On 32bit we then have to push additional args on the stack to accomplish | |
| 5967 // the actual requested call. On 64bit call_VM only can use register args | |
| 5968 // so the only extra space is the return address that call_VM created. | |
| 5969 // This hopefully explains the calculations here. | |
| 5970 | |
| 5971 #ifdef _LP64 | |
| 5972 // We've pushed one address, correct last_Java_sp | |
| 5973 lea(rax, Address(rsp, wordSize)); | |
| 5974 #else | |
| 5975 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize)); | |
| 5976 #endif // LP64 | |
| 5977 | |
| 5978 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions); | |
| 5979 | |
| 5980 } | |
| 5981 | |
| 5982 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { | |
| 5983 call_VM_leaf_base(entry_point, number_of_arguments); | |
| 5984 } | |
| 5985 | |
| 5986 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) { | |
| 5987 pass_arg0(this, arg_0); | |
| 5988 call_VM_leaf(entry_point, 1); | |
| 5989 } | |
| 5990 | |
| 5991 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { | |
| 5992 | |
| 5993 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); | |
| 5994 pass_arg1(this, arg_1); | |
| 5995 pass_arg0(this, arg_0); | |
| 5996 call_VM_leaf(entry_point, 2); | |
| 5997 } | |
| 5998 | |
| 5999 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { | |
| 6000 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); | |
| 6001 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
| 6002 pass_arg2(this, arg_2); | |
| 6003 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); | |
| 6004 pass_arg1(this, arg_1); | |
| 6005 pass_arg0(this, arg_0); | |
| 6006 call_VM_leaf(entry_point, 3); | |
| 6007 } | |
| 6008 | |
| 6009 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { | |
| 6010 } | |
| 6011 | |
| 6012 void MacroAssembler::check_and_handle_popframe(Register java_thread) { | |
| 6013 } | |
| 6014 | |
| 6015 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) { | |
| 6016 if (reachable(src1)) { | |
| 6017 cmpl(as_Address(src1), imm); | |
| 6018 } else { | |
| 6019 lea(rscratch1, src1); | |
| 6020 cmpl(Address(rscratch1, 0), imm); | |
| 6021 } | |
| 6022 } | |
| 6023 | |
| 6024 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) { | |
| 6025 assert(!src2.is_lval(), "use cmpptr"); | |
| 6026 if (reachable(src2)) { | |
| 6027 cmpl(src1, as_Address(src2)); | |
| 6028 } else { | |
| 6029 lea(rscratch1, src2); | |
| 6030 cmpl(src1, Address(rscratch1, 0)); | |
| 6031 } | |
| 6032 } | |
| 6033 | |
| 6034 void MacroAssembler::cmp32(Register src1, int32_t imm) { | |
| 6035 Assembler::cmpl(src1, imm); | |
| 6036 } | |
| 6037 | |
| 6038 void MacroAssembler::cmp32(Register src1, Address src2) { | |
| 6039 Assembler::cmpl(src1, src2); | |
| 6040 } | |
| 6041 | |
| 6042 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { | |
| 6043 ucomisd(opr1, opr2); | |
| 6044 | |
| 6045 Label L; | |
| 6046 if (unordered_is_less) { | |
| 6047 movl(dst, -1); | |
| 6048 jcc(Assembler::parity, L); | |
| 6049 jcc(Assembler::below , L); | |
| 6050 movl(dst, 0); | |
| 6051 jcc(Assembler::equal , L); | |
| 6052 increment(dst); | |
| 6053 } else { // unordered is greater | |
| 6054 movl(dst, 1); | |
| 6055 jcc(Assembler::parity, L); | |
| 6056 jcc(Assembler::above , L); | |
| 6057 movl(dst, 0); | |
| 6058 jcc(Assembler::equal , L); | |
| 6059 decrementl(dst); | |
| 6060 } | |
| 6061 bind(L); | |
| 6062 } | |
| 6063 | |
| 6064 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { | |
| 6065 ucomiss(opr1, opr2); | |
| 6066 | |
| 6067 Label L; | |
| 6068 if (unordered_is_less) { | |
| 6069 movl(dst, -1); | |
| 6070 jcc(Assembler::parity, L); | |
| 6071 jcc(Assembler::below , L); | |
| 6072 movl(dst, 0); | |
| 6073 jcc(Assembler::equal , L); | |
| 6074 increment(dst); | |
| 6075 } else { // unordered is greater | |
| 6076 movl(dst, 1); | |
| 6077 jcc(Assembler::parity, L); | |
| 6078 jcc(Assembler::above , L); | |
| 6079 movl(dst, 0); | |
| 6080 jcc(Assembler::equal , L); | |
| 6081 decrementl(dst); | |
| 6082 } | |
| 6083 bind(L); | |
| 6084 } | |
| 6085 | |
| 6086 | |
| 6087 void MacroAssembler::cmp8(AddressLiteral src1, int imm) { | |
| 6088 if (reachable(src1)) { | |
| 6089 cmpb(as_Address(src1), imm); | |
| 6090 } else { | |
| 6091 lea(rscratch1, src1); | |
| 6092 cmpb(Address(rscratch1, 0), imm); | |
| 6093 } | |
| 6094 } | |
| 6095 | |
| 6096 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) { | |
| 6097 #ifdef _LP64 | |
| 6098 if (src2.is_lval()) { | |
| 6099 movptr(rscratch1, src2); | |
| 6100 Assembler::cmpq(src1, rscratch1); | |
| 6101 } else if (reachable(src2)) { | |
| 6102 cmpq(src1, as_Address(src2)); | |
| 6103 } else { | |
| 6104 lea(rscratch1, src2); | |
| 6105 Assembler::cmpq(src1, Address(rscratch1, 0)); | |
| 6106 } | |
| 6107 #else | |
| 6108 if (src2.is_lval()) { | |
| 6109 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); | |
| 6110 } else { | |
| 6111 cmpl(src1, as_Address(src2)); | |
| 6112 } | |
| 6113 #endif // _LP64 | |
| 6114 } | |
| 6115 | |
| 6116 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) { | |
| 6117 assert(src2.is_lval(), "not a mem-mem compare"); | |
| 6118 #ifdef _LP64 | |
| 6119 // moves src2's literal address | |
| 6120 movptr(rscratch1, src2); | |
| 6121 Assembler::cmpq(src1, rscratch1); | |
| 6122 #else | |
| 6123 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); | |
| 6124 #endif // _LP64 | |
| 6125 } | |
| 6126 | |
| 6127 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) { | |
| 6128 if (reachable(adr)) { | |
| 6129 if (os::is_MP()) | |
| 6130 lock(); | |
| 6131 cmpxchgptr(reg, as_Address(adr)); | |
| 6132 } else { | |
| 6133 lea(rscratch1, adr); | |
| 6134 if (os::is_MP()) | |
| 6135 lock(); | |
| 6136 cmpxchgptr(reg, Address(rscratch1, 0)); | |
| 6137 } | |
| 6138 } | |
| 6139 | |
| 6140 void MacroAssembler::cmpxchgptr(Register reg, Address adr) { | |
| 6141 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr)); | |
| 6142 } | |
| 6143 | |
| 6144 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) { | |
| 1060 | 6145 if (reachable(src)) { |
| 6146 comisd(dst, as_Address(src)); | |
| 6147 } else { | |
| 6148 lea(rscratch1, src); | |
| 6149 comisd(dst, Address(rscratch1, 0)); | |
| 6150 } | |
| 304 | 6151 } |
| 6152 | |
| 6153 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) { | |
| 1060 | 6154 if (reachable(src)) { |
| 6155 comiss(dst, as_Address(src)); | |
| 6156 } else { | |
| 6157 lea(rscratch1, src); | |
| 6158 comiss(dst, Address(rscratch1, 0)); | |
| 6159 } | |
| 304 | 6160 } |
| 6161 | |
| 6162 | |
| 6163 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) { | |
| 6164 Condition negated_cond = negate_condition(cond); | |
| 6165 Label L; | |
| 6166 jcc(negated_cond, L); | |
| 6167 atomic_incl(counter_addr); | |
| 6168 bind(L); | |
| 6169 } | |
| 6170 | |
| 6171 int MacroAssembler::corrected_idivl(Register reg) { | |
| 6172 // Full implementation of Java idiv and irem; checks for | |
| 6173 // special case as described in JVM spec., p.243 & p.271. | |
| 6174 // The function returns the (pc) offset of the idivl | |
| 6175 // instruction - may be needed for implicit exceptions. | |
| 6176 // | |
| 6177 // normal case special case | |
| 6178 // | |
| 6179 // input : rax,: dividend min_int | |
| 6180 // reg: divisor (may not be rax,/rdx) -1 | |
| 6181 // | |
| 6182 // output: rax,: quotient (= rax, idiv reg) min_int | |
| 6183 // rdx: remainder (= rax, irem reg) 0 | |
| 6184 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register"); | |
| 6185 const int min_int = 0x80000000; | |
| 6186 Label normal_case, special_case; | |
| 6187 | |
| 6188 // check for special case | |
| 6189 cmpl(rax, min_int); | |
| 6190 jcc(Assembler::notEqual, normal_case); | |
| 6191 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0) | |
| 6192 cmpl(reg, -1); | |
| 6193 jcc(Assembler::equal, special_case); | |
| 6194 | |
| 6195 // handle normal case | |
| 6196 bind(normal_case); | |
| 6197 cdql(); | |
| 6198 int idivl_offset = offset(); | |
| 6199 idivl(reg); | |
| 6200 | |
| 6201 // normal and special case exit | |
| 6202 bind(special_case); | |
| 6203 | |
| 6204 return idivl_offset; | |
| 6205 } | |
| 6206 | |
| 6207 | |
| 6208 | |
| 6209 void MacroAssembler::decrementl(Register reg, int value) { | |
| 6210 if (value == min_jint) {subl(reg, value) ; return; } | |
| 6211 if (value < 0) { incrementl(reg, -value); return; } | |
| 6212 if (value == 0) { ; return; } | |
| 6213 if (value == 1 && UseIncDec) { decl(reg) ; return; } | |
| 6214 /* else */ { subl(reg, value) ; return; } | |
| 6215 } | |
| 6216 | |
| 6217 void MacroAssembler::decrementl(Address dst, int value) { | |
| 6218 if (value == min_jint) {subl(dst, value) ; return; } | |
| 6219 if (value < 0) { incrementl(dst, -value); return; } | |
| 6220 if (value == 0) { ; return; } | |
| 6221 if (value == 1 && UseIncDec) { decl(dst) ; return; } | |
| 6222 /* else */ { subl(dst, value) ; return; } | |
| 6223 } | |
| 6224 | |
| 6225 void MacroAssembler::division_with_shift (Register reg, int shift_value) { | |
| 6226 assert (shift_value > 0, "illegal shift value"); | |
| 6227 Label _is_positive; | |
| 6228 testl (reg, reg); | |
| 6229 jcc (Assembler::positive, _is_positive); | |
| 6230 int offset = (1 << shift_value) - 1 ; | |
| 6231 | |
| 6232 if (offset == 1) { | |
| 6233 incrementl(reg); | |
| 6234 } else { | |
| 6235 addl(reg, offset); | |
| 6236 } | |
| 6237 | |
| 6238 bind (_is_positive); | |
| 6239 sarl(reg, shift_value); | |
| 6240 } | |
| 6241 | |
| 6242 // !defined(COMPILER2) is because of stupid core builds | |
| 6243 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) | |
| 6244 void MacroAssembler::empty_FPU_stack() { | |
| 6245 if (VM_Version::supports_mmx()) { | |
| 6246 emms(); | |
| 6247 } else { | |
| 6248 for (int i = 8; i-- > 0; ) ffree(i); | |
| 6249 } | |
| 6250 } | |
| 6251 #endif // !LP64 || C1 || !C2 | |
| 6252 | |
| 6253 | |
| 6254 // Defines obj, preserves var_size_in_bytes | |
| 6255 void MacroAssembler::eden_allocate(Register obj, | |
| 6256 Register var_size_in_bytes, | |
| 6257 int con_size_in_bytes, | |
| 6258 Register t1, | |
| 6259 Label& slow_case) { | |
| 6260 assert(obj == rax, "obj must be in rax, for cmpxchg"); | |
| 6261 assert_different_registers(obj, var_size_in_bytes, t1); | |
| 362 | 6262 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { |
| 6263 jmp(slow_case); | |
| 304 | 6264 } else { |
| 362 | 6265 Register end = t1; |
| 6266 Label retry; | |
| 6267 bind(retry); | |
| 6268 ExternalAddress heap_top((address) Universe::heap()->top_addr()); | |
| 6269 movptr(obj, heap_top); | |
| 6270 if (var_size_in_bytes == noreg) { | |
| 6271 lea(end, Address(obj, con_size_in_bytes)); | |
| 6272 } else { | |
| 6273 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); | |
| 6274 } | |
| 6275 // if end < obj then we wrapped around => object too long => slow case | |
| 6276 cmpptr(end, obj); | |
| 6277 jcc(Assembler::below, slow_case); | |
| 6278 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr())); | |
| 6279 jcc(Assembler::above, slow_case); | |
| 6280 // Compare obj with the top addr, and if still equal, store the new top addr in | |
| 6281 // end at the address of the top addr pointer. Sets ZF if was equal, and clears | |
| 6282 // it otherwise. Use lock prefix for atomicity on MPs. | |
| 6283 locked_cmpxchgptr(end, heap_top); | |
| 6284 jcc(Assembler::notEqual, retry); | |
| 6285 } | |
| 304 | 6286 } |
| 6287 | |
| 6288 void MacroAssembler::enter() { | |
| 6289 push(rbp); | |
| 6290 mov(rbp, rsp); | |
| 6291 } | |
| 0 | 6292 |
| 6293 void MacroAssembler::fcmp(Register tmp) { | |
| 6294 fcmp(tmp, 1, true, true); | |
| 6295 } | |
| 6296 | |
| 6297 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) { | |
| 6298 assert(!pop_right || pop_left, "usage error"); | |
| 6299 if (VM_Version::supports_cmov()) { | |
| 6300 assert(tmp == noreg, "unneeded temp"); | |
| 6301 if (pop_left) { | |
| 6302 fucomip(index); | |
| 6303 } else { | |
| 6304 fucomi(index); | |
| 6305 } | |
| 6306 if (pop_right) { | |
| 6307 fpop(); | |
| 6308 } | |
| 6309 } else { | |
| 6310 assert(tmp != noreg, "need temp"); | |
| 6311 if (pop_left) { | |
| 6312 if (pop_right) { | |
| 6313 fcompp(); | |
| 6314 } else { | |
| 6315 fcomp(index); | |
| 6316 } | |
| 6317 } else { | |
| 6318 fcom(index); | |
| 6319 } | |
| 6320 // convert FPU condition into eflags condition via rax, | |
| 6321 save_rax(tmp); | |
| 6322 fwait(); fnstsw_ax(); | |
| 6323 sahf(); | |
| 6324 restore_rax(tmp); | |
| 6325 } | |
| 6326 // condition codes set as follows: | |
| 6327 // | |
| 6328 // CF (corresponds to C0) if x < y | |
| 6329 // PF (corresponds to C2) if unordered | |
| 6330 // ZF (corresponds to C3) if x = y | |
| 6331 } | |
| 6332 | |
| 6333 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) { | |
| 6334 fcmp2int(dst, unordered_is_less, 1, true, true); | |
| 6335 } | |
| 6336 | |
| 6337 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) { | |
| 6338 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right); | |
| 6339 Label L; | |
| 6340 if (unordered_is_less) { | |
| 6341 movl(dst, -1); | |
| 6342 jcc(Assembler::parity, L); | |
| 6343 jcc(Assembler::below , L); | |
| 6344 movl(dst, 0); | |
| 6345 jcc(Assembler::equal , L); | |
| 6346 increment(dst); | |
| 6347 } else { // unordered is greater | |
| 6348 movl(dst, 1); | |
| 6349 jcc(Assembler::parity, L); | |
| 6350 jcc(Assembler::above , L); | |
| 6351 movl(dst, 0); | |
| 6352 jcc(Assembler::equal , L); | |
| 304 | 6353 decrementl(dst); |
| 0 | 6354 } |
| 6355 bind(L); | |
| 6356 } | |
| 6357 | |
| 304 | 6358 void MacroAssembler::fld_d(AddressLiteral src) { |
| 6359 fld_d(as_Address(src)); | |
| 6360 } | |
| 6361 | |
| 6362 void MacroAssembler::fld_s(AddressLiteral src) { | |
| 6363 fld_s(as_Address(src)); | |
| 6364 } | |
| 6365 | |
| 6366 void MacroAssembler::fld_x(AddressLiteral src) { | |
| 6367 Assembler::fld_x(as_Address(src)); | |
| 6368 } | |
| 6369 | |
| 6370 void MacroAssembler::fldcw(AddressLiteral src) { | |
| 6371 Assembler::fldcw(as_Address(src)); | |
| 6372 } | |
| 0 | 6373 |
| 6374 void MacroAssembler::fpop() { | |
| 6375 ffree(); | |
| 6376 fincstp(); | |
| 6377 } | |
| 6378 | |
| 304 | 6379 void MacroAssembler::fremr(Register tmp) { |
| 6380 save_rax(tmp); | |
| 6381 { Label L; | |
| 6382 bind(L); | |
| 6383 fprem(); | |
| 6384 fwait(); fnstsw_ax(); | |
| 6385 #ifdef _LP64 | |
| 6386 testl(rax, 0x400); | |
| 6387 jcc(Assembler::notEqual, L); | |
| 6388 #else | |
| 6389 sahf(); | |
| 6390 jcc(Assembler::parity, L); | |
| 6391 #endif // _LP64 | |
| 6392 } | |
| 6393 restore_rax(tmp); | |
| 6394 // Result is in ST0. | |
| 6395 // Note: fxch & fpop to get rid of ST1 | |
| 6396 // (otherwise FPU stack could overflow eventually) | |
| 6397 fxch(1); | |
| 6398 fpop(); | |
| 6399 } | |
| 6400 | |
| 6401 | |
| 6402 void MacroAssembler::incrementl(AddressLiteral dst) { | |
| 6403 if (reachable(dst)) { | |
| 6404 incrementl(as_Address(dst)); | |
| 0 | 6405 } else { |
| 304 | 6406 lea(rscratch1, dst); |
| 6407 incrementl(Address(rscratch1, 0)); | |
| 6408 } | |
| 6409 } | |
| 6410 | |
| 6411 void MacroAssembler::incrementl(ArrayAddress dst) { | |
| 6412 incrementl(as_Address(dst)); | |
| 6413 } | |
| 6414 | |
| 6415 void MacroAssembler::incrementl(Register reg, int value) { | |
| 6416 if (value == min_jint) {addl(reg, value) ; return; } | |
| 6417 if (value < 0) { decrementl(reg, -value); return; } | |
| 6418 if (value == 0) { ; return; } | |
| 6419 if (value == 1 && UseIncDec) { incl(reg) ; return; } | |
| 6420 /* else */ { addl(reg, value) ; return; } | |
| 6421 } | |
| 6422 | |
| 6423 void MacroAssembler::incrementl(Address dst, int value) { | |
| 6424 if (value == min_jint) {addl(dst, value) ; return; } | |
| 6425 if (value < 0) { decrementl(dst, -value); return; } | |
| 6426 if (value == 0) { ; return; } | |
| 6427 if (value == 1 && UseIncDec) { incl(dst) ; return; } | |
| 6428 /* else */ { addl(dst, value) ; return; } | |
| 6429 } | |
| 6430 | |
| 6431 void MacroAssembler::jump(AddressLiteral dst) { | |
| 6432 if (reachable(dst)) { | |
| 6433 jmp_literal(dst.target(), dst.rspec()); | |
| 6434 } else { | |
| 6435 lea(rscratch1, dst); | |
| 6436 jmp(rscratch1); | |
| 6437 } | |
| 6438 } | |
| 6439 | |
| 6440 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) { | |
| 6441 if (reachable(dst)) { | |
| 6442 InstructionMark im(this); | |
| 6443 relocate(dst.reloc()); | |
| 6444 const int short_size = 2; | |
| 6445 const int long_size = 6; | |
| 6446 int offs = (intptr_t)dst.target() - ((intptr_t)_code_pos); | |
| 6447 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) { | |
| 6448 // 0111 tttn #8-bit disp | |
| 6449 emit_byte(0x70 | cc); | |
| 6450 emit_byte((offs - short_size) & 0xFF); | |
| 6451 } else { | |
| 6452 // 0000 1111 1000 tttn #32-bit disp | |
| 6453 emit_byte(0x0F); | |
| 6454 emit_byte(0x80 | cc); | |
| 6455 emit_long(offs - long_size); | |
| 6456 } | |
| 0 | 6457 } else { |
| 304 | 6458 #ifdef ASSERT |
| 6459 warning("reversing conditional branch"); | |
| 6460 #endif /* ASSERT */ | |
| 6461 Label skip; | |
| 6462 jccb(reverse[cc], skip); | |
| 6463 lea(rscratch1, dst); | |
| 6464 Assembler::jmp(rscratch1); | |
| 6465 bind(skip); | |
| 6466 } | |
| 6467 } | |
| 6468 | |
| 6469 void MacroAssembler::ldmxcsr(AddressLiteral src) { | |
| 6470 if (reachable(src)) { | |
| 6471 Assembler::ldmxcsr(as_Address(src)); | |
| 6472 } else { | |
| 6473 lea(rscratch1, src); | |
| 6474 Assembler::ldmxcsr(Address(rscratch1, 0)); | |
| 6475 } | |
| 6476 } | |
| 6477 | |
| 6478 int MacroAssembler::load_signed_byte(Register dst, Address src) { | |
| 6479 int off; | |
| 6480 if (LP64_ONLY(true ||) VM_Version::is_P6()) { | |
| 6481 off = offset(); | |
| 6482 movsbl(dst, src); // movsxb | |
| 6483 } else { | |
| 6484 off = load_unsigned_byte(dst, src); | |
| 6485 shll(dst, 24); | |
| 6486 sarl(dst, 24); | |
| 6487 } | |
| 6488 return off; | |
| 6489 } | |
| 6490 | |
|
622
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|
6491 // Note: load_signed_short used to be called load_signed_word. |
|
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diff
changeset
|
6492 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler |
|
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|
6493 // manual, which means 16 bits, that usage is found nowhere in HotSpot code. |
|
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diff
changeset
|
6494 // The term "word" in HotSpot means a 32- or 64-bit machine word. |
|
56aae7be60d4
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diff
changeset
|
6495 int MacroAssembler::load_signed_short(Register dst, Address src) { |
| 304 | 6496 int off; |
| 6497 if (LP64_ONLY(true ||) VM_Version::is_P6()) { | |
| 6498 // This is dubious to me since it seems safe to do a signed 16 => 64 bit | |
| 6499 // version but this is what 64bit has always done. This seems to imply | |
| 6500 // that users are only using 32bits worth. | |
| 6501 off = offset(); | |
| 6502 movswl(dst, src); // movsxw | |
| 6503 } else { | |
|
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|
6504 off = load_unsigned_short(dst, src); |
| 304 | 6505 shll(dst, 16); |
| 6506 sarl(dst, 16); | |
| 6507 } | |
| 6508 return off; | |
| 6509 } | |
| 6510 | |
| 6511 int MacroAssembler::load_unsigned_byte(Register dst, Address src) { | |
| 6512 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, | |
| 6513 // and "3.9 Partial Register Penalties", p. 22). | |
| 6514 int off; | |
| 6515 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) { | |
| 6516 off = offset(); | |
| 6517 movzbl(dst, src); // movzxb | |
| 6518 } else { | |
| 6519 xorl(dst, dst); | |
| 6520 off = offset(); | |
| 6521 movb(dst, src); | |
| 6522 } | |
| 6523 return off; | |
| 6524 } | |
| 6525 | |
|
622
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|
6526 // Note: load_unsigned_short used to be called load_unsigned_word. |
|
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changeset
|
6527 int MacroAssembler::load_unsigned_short(Register dst, Address src) { |
| 304 | 6528 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, |
| 6529 // and "3.9 Partial Register Penalties", p. 22). | |
| 6530 int off; | |
| 6531 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) { | |
| 6532 off = offset(); | |
| 6533 movzwl(dst, src); // movzxw | |
| 6534 } else { | |
| 6535 xorl(dst, dst); | |
| 6536 off = offset(); | |
| 6537 movw(dst, src); | |
| 6538 } | |
| 6539 return off; | |
| 6540 } | |
| 6541 | |
|
2258
28bf941f445e
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2100
diff
changeset
|
6542 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) { |
| 1503 | 6543 switch (size_in_bytes) { |
|
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diff
changeset
|
6544 #ifndef _LP64 |
|
2258
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
6545 case 8: |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
6546 assert(dst2 != noreg, "second dest register required"); |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
6547 movl(dst, src); |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
6548 movl(dst2, src.plus_disp(BytesPerInt)); |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
6549 break; |
|
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6550 #else |
|
2258
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
6551 case 8: movq(dst, src); break; |
|
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6552 #endif |
|
2258
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
6553 case 4: movl(dst, src); break; |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
6554 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break; |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
6555 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break; |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
6556 default: ShouldNotReachHere(); |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
6557 } |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
6558 } |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
6559 |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
6560 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) { |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
6561 switch (size_in_bytes) { |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
6562 #ifndef _LP64 |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
6563 case 8: |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
6564 assert(src2 != noreg, "second source register required"); |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
6565 movl(dst, src); |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
6566 movl(dst.plus_disp(BytesPerInt), src2); |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
6567 break; |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
6568 #else |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
6569 case 8: movq(dst, src); break; |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
6570 #endif |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
6571 case 4: movl(dst, src); break; |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
6572 case 2: movw(dst, src); break; |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
6573 case 1: movb(dst, src); break; |
|
28bf941f445e
7018378: JSR 292: _bound_int_mh produces wrong result on 64-bit SPARC
twisti
parents:
2100
diff
changeset
|
6574 default: ShouldNotReachHere(); |
|
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6575 } |
|
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6576 } |
|
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
606
diff
changeset
|
6577 |
| 304 | 6578 void MacroAssembler::mov32(AddressLiteral dst, Register src) { |
| 6579 if (reachable(dst)) { | |
| 6580 movl(as_Address(dst), src); | |
| 6581 } else { | |
| 6582 lea(rscratch1, dst); | |
| 6583 movl(Address(rscratch1, 0), src); | |
| 6584 } | |
| 6585 } | |
| 6586 | |
| 6587 void MacroAssembler::mov32(Register dst, AddressLiteral src) { | |
| 6588 if (reachable(src)) { | |
| 6589 movl(dst, as_Address(src)); | |
| 6590 } else { | |
| 6591 lea(rscratch1, src); | |
| 6592 movl(dst, Address(rscratch1, 0)); | |
| 6593 } | |
| 0 | 6594 } |
| 6595 | |
| 6596 // C++ bool manipulation | |
| 6597 | |
| 6598 void MacroAssembler::movbool(Register dst, Address src) { | |
| 6599 if(sizeof(bool) == 1) | |
| 6600 movb(dst, src); | |
| 6601 else if(sizeof(bool) == 2) | |
| 6602 movw(dst, src); | |
| 6603 else if(sizeof(bool) == 4) | |
| 6604 movl(dst, src); | |
| 6605 else | |
| 6606 // unsupported | |
| 6607 ShouldNotReachHere(); | |
| 6608 } | |
| 6609 | |
| 6610 void MacroAssembler::movbool(Address dst, bool boolconst) { | |
| 6611 if(sizeof(bool) == 1) | |
| 6612 movb(dst, (int) boolconst); | |
| 6613 else if(sizeof(bool) == 2) | |
| 6614 movw(dst, (int) boolconst); | |
| 6615 else if(sizeof(bool) == 4) | |
| 6616 movl(dst, (int) boolconst); | |
| 6617 else | |
| 6618 // unsupported | |
| 6619 ShouldNotReachHere(); | |
| 6620 } | |
| 6621 | |
| 6622 void MacroAssembler::movbool(Address dst, Register src) { | |
| 6623 if(sizeof(bool) == 1) | |
| 6624 movb(dst, src); | |
| 6625 else if(sizeof(bool) == 2) | |
| 6626 movw(dst, src); | |
| 6627 else if(sizeof(bool) == 4) | |
| 6628 movl(dst, src); | |
| 6629 else | |
| 6630 // unsupported | |
| 6631 ShouldNotReachHere(); | |
| 6632 } | |
| 6633 | |
| 304 | 6634 void MacroAssembler::movbyte(ArrayAddress dst, int src) { |
| 6635 movb(as_Address(dst), src); | |
| 6636 } | |
| 6637 | |
| 6638 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) { | |
| 6639 if (reachable(src)) { | |
| 6640 if (UseXmmLoadAndClearUpper) { | |
| 6641 movsd (dst, as_Address(src)); | |
| 6642 } else { | |
| 6643 movlpd(dst, as_Address(src)); | |
| 6644 } | |
| 6645 } else { | |
| 6646 lea(rscratch1, src); | |
| 6647 if (UseXmmLoadAndClearUpper) { | |
| 6648 movsd (dst, Address(rscratch1, 0)); | |
| 6649 } else { | |
| 6650 movlpd(dst, Address(rscratch1, 0)); | |
| 6651 } | |
| 6652 } | |
| 6653 } | |
| 6654 | |
| 6655 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) { | |
| 6656 if (reachable(src)) { | |
| 6657 movss(dst, as_Address(src)); | |
| 6658 } else { | |
| 6659 lea(rscratch1, src); | |
| 6660 movss(dst, Address(rscratch1, 0)); | |
| 6661 } | |
| 6662 } | |
| 6663 | |
| 6664 void MacroAssembler::movptr(Register dst, Register src) { | |
| 6665 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
| 6666 } | |
| 6667 | |
| 6668 void MacroAssembler::movptr(Register dst, Address src) { | |
| 6669 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
| 6670 } | |
| 6671 | |
| 6672 // src should NEVER be a real pointer. Use AddressLiteral for true pointers | |
| 6673 void MacroAssembler::movptr(Register dst, intptr_t src) { | |
| 6674 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src)); | |
| 6675 } | |
| 6676 | |
| 6677 void MacroAssembler::movptr(Address dst, Register src) { | |
| 6678 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
| 6679 } | |
| 6680 | |
| 6681 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) { | |
| 6682 if (reachable(src)) { | |
| 6683 movss(dst, as_Address(src)); | |
| 6684 } else { | |
| 6685 lea(rscratch1, src); | |
| 6686 movss(dst, Address(rscratch1, 0)); | |
| 6687 } | |
| 6688 } | |
| 6689 | |
| 6690 void MacroAssembler::null_check(Register reg, int offset) { | |
| 6691 if (needs_explicit_null_check(offset)) { | |
| 6692 // provoke OS NULL exception if reg = NULL by | |
| 6693 // accessing M[reg] w/o changing any (non-CC) registers | |
| 6694 // NOTE: cmpl is plenty here to provoke a segv | |
| 6695 cmpptr(rax, Address(reg, 0)); | |
| 6696 // Note: should probably use testl(rax, Address(reg, 0)); | |
| 6697 // may be shorter code (however, this version of | |
| 6698 // testl needs to be implemented first) | |
| 6699 } else { | |
| 6700 // nothing to do, (later) access of M[reg + offset] | |
| 6701 // will provoke OS NULL exception if reg = NULL | |
| 6702 } | |
| 6703 } | |
| 6704 | |
| 6705 void MacroAssembler::os_breakpoint() { | |
| 6706 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability | |
| 6707 // (e.g., MSVC can't call ps() otherwise) | |
| 6708 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint))); | |
| 6709 } | |
| 6710 | |
| 6711 void MacroAssembler::pop_CPU_state() { | |
| 6712 pop_FPU_state(); | |
| 6713 pop_IU_state(); | |
| 6714 } | |
| 6715 | |
| 6716 void MacroAssembler::pop_FPU_state() { | |
| 6717 NOT_LP64(frstor(Address(rsp, 0));) | |
| 6718 LP64_ONLY(fxrstor(Address(rsp, 0));) | |
| 6719 addptr(rsp, FPUStateSizeInWords * wordSize); | |
| 6720 } | |
| 6721 | |
| 6722 void MacroAssembler::pop_IU_state() { | |
| 6723 popa(); | |
| 6724 LP64_ONLY(addq(rsp, 8)); | |
| 6725 popf(); | |
| 6726 } | |
| 6727 | |
| 6728 // Save Integer and Float state | |
| 6729 // Warning: Stack must be 16 byte aligned (64bit) | |
| 6730 void MacroAssembler::push_CPU_state() { | |
| 6731 push_IU_state(); | |
| 6732 push_FPU_state(); | |
| 6733 } | |
| 6734 | |
| 6735 void MacroAssembler::push_FPU_state() { | |
| 6736 subptr(rsp, FPUStateSizeInWords * wordSize); | |
| 6737 #ifndef _LP64 | |
| 6738 fnsave(Address(rsp, 0)); | |
| 6739 fwait(); | |
| 6740 #else | |
| 6741 fxsave(Address(rsp, 0)); | |
| 6742 #endif // LP64 | |
| 6743 } | |
| 6744 | |
| 6745 void MacroAssembler::push_IU_state() { | |
| 6746 // Push flags first because pusha kills them | |
| 6747 pushf(); | |
| 6748 // Make sure rsp stays 16-byte aligned | |
| 6749 LP64_ONLY(subq(rsp, 8)); | |
| 6750 pusha(); | |
| 6751 } | |
| 6752 | |
| 6753 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) { | |
| 6754 // determine java_thread register | |
| 6755 if (!java_thread->is_valid()) { | |
| 6756 java_thread = rdi; | |
| 6757 get_thread(java_thread); | |
| 6758 } | |
| 6759 // we must set sp to zero to clear frame | |
|
512
db4caa99ef11
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents:
420
diff
changeset
|
6760 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); |
| 304 | 6761 if (clear_fp) { |
|
512
db4caa99ef11
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents:
420
diff
changeset
|
6762 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); |
| 304 | 6763 } |
| 6764 | |
| 6765 if (clear_pc) | |
|
512
db4caa99ef11
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents:
420
diff
changeset
|
6766 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); |
| 304 | 6767 |
| 6768 } | |
| 6769 | |
| 6770 void MacroAssembler::restore_rax(Register tmp) { | |
| 6771 if (tmp == noreg) pop(rax); | |
| 6772 else if (tmp != rax) mov(rax, tmp); | |
| 6773 } | |
| 6774 | |
| 6775 void MacroAssembler::round_to(Register reg, int modulus) { | |
| 6776 addptr(reg, modulus - 1); | |
| 6777 andptr(reg, -modulus); | |
| 6778 } | |
| 6779 | |
| 6780 void MacroAssembler::save_rax(Register tmp) { | |
| 6781 if (tmp == noreg) push(rax); | |
| 6782 else if (tmp != rax) mov(tmp, rax); | |
| 6783 } | |
| 6784 | |
| 6785 // Write serialization page so VM thread can do a pseudo remote membar. | |
| 6786 // We use the current thread pointer to calculate a thread specific | |
| 6787 // offset to write to within the page. This minimizes bus traffic | |
| 6788 // due to cache line collision. | |
| 6789 void MacroAssembler::serialize_memory(Register thread, Register tmp) { | |
| 6790 movl(tmp, thread); | |
| 6791 shrl(tmp, os::get_serialize_page_shift_count()); | |
| 6792 andl(tmp, (os::vm_page_size() - sizeof(int))); | |
| 6793 | |
| 6794 Address index(noreg, tmp, Address::times_1); | |
| 6795 ExternalAddress page(os::get_memory_serialize_page()); | |
| 6796 | |
|
606
19962e74284f
6811384: MacroAssembler::serialize_memory may touch next page on amd64
never
parents:
520
diff
changeset
|
6797 // Size of store must match masking code above |
|
19962e74284f
6811384: MacroAssembler::serialize_memory may touch next page on amd64
never
parents:
520
diff
changeset
|
6798 movl(as_Address(ArrayAddress(page, index)), tmp); |
| 304 | 6799 } |
| 6800 | |
| 6801 // Calls to C land | |
| 6802 // | |
| 6803 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded | |
| 6804 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp | |
| 6805 // has to be reset to 0. This is required to allow proper stack traversal. | |
| 6806 void MacroAssembler::set_last_Java_frame(Register java_thread, | |
| 6807 Register last_java_sp, | |
| 6808 Register last_java_fp, | |
| 6809 address last_java_pc) { | |
| 6810 // determine java_thread register | |
| 6811 if (!java_thread->is_valid()) { | |
| 6812 java_thread = rdi; | |
| 6813 get_thread(java_thread); | |
| 6814 } | |
| 6815 // determine last_java_sp register | |
| 6816 if (!last_java_sp->is_valid()) { | |
| 6817 last_java_sp = rsp; | |
| 6818 } | |
| 6819 | |
| 6820 // last_java_fp is optional | |
| 6821 | |
| 6822 if (last_java_fp->is_valid()) { | |
| 6823 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp); | |
| 6824 } | |
| 6825 | |
| 6826 // last_java_pc is optional | |
| 6827 | |
| 6828 if (last_java_pc != NULL) { | |
| 6829 lea(Address(java_thread, | |
| 6830 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()), | |
| 6831 InternalAddress(last_java_pc)); | |
| 6832 | |
| 6833 } | |
| 6834 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp); | |
| 6835 } | |
| 6836 | |
| 6837 void MacroAssembler::shlptr(Register dst, int imm8) { | |
| 6838 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8)); | |
| 6839 } | |
| 6840 | |
| 6841 void MacroAssembler::shrptr(Register dst, int imm8) { | |
| 6842 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8)); | |
| 6843 } | |
| 6844 | |
| 6845 void MacroAssembler::sign_extend_byte(Register reg) { | |
| 6846 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) { | |
| 6847 movsbl(reg, reg); // movsxb | |
| 6848 } else { | |
| 6849 shll(reg, 24); | |
| 6850 sarl(reg, 24); | |
| 6851 } | |
| 6852 } | |
| 6853 | |
| 6854 void MacroAssembler::sign_extend_short(Register reg) { | |
| 6855 if (LP64_ONLY(true ||) VM_Version::is_P6()) { | |
| 6856 movswl(reg, reg); // movsxw | |
| 6857 } else { | |
| 6858 shll(reg, 16); | |
| 6859 sarl(reg, 16); | |
| 6860 } | |
| 6861 } | |
| 6862 | |
| 362 | 6863 ////////////////////////////////////////////////////////////////////////////////// |
| 6864 #ifndef SERIALGC | |
| 6865 | |
| 6866 void MacroAssembler::g1_write_barrier_pre(Register obj, | |
| 6867 #ifndef _LP64 | |
| 6868 Register thread, | |
| 6869 #endif | |
| 6870 Register tmp, | |
| 6871 Register tmp2, | |
| 6872 bool tosca_live) { | |
| 6873 LP64_ONLY(Register thread = r15_thread;) | |
| 6874 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() + | |
| 6875 PtrQueue::byte_offset_of_active())); | |
| 6876 | |
| 6877 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() + | |
| 6878 PtrQueue::byte_offset_of_index())); | |
| 6879 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() + | |
| 6880 PtrQueue::byte_offset_of_buf())); | |
| 6881 | |
| 6882 | |
| 6883 Label done; | |
| 6884 Label runtime; | |
| 6885 | |
| 6886 // if (!marking_in_progress) goto done; | |
| 6887 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) { | |
| 6888 cmpl(in_progress, 0); | |
| 6889 } else { | |
| 6890 assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption"); | |
| 6891 cmpb(in_progress, 0); | |
| 6892 } | |
| 6893 jcc(Assembler::equal, done); | |
| 6894 | |
| 6895 // if (x.f == NULL) goto done; | |
|
845
df6caf649ff7
6700789: G1: Enable use of compressed oops with G1 heaps
ysr
parents:
775
diff
changeset
|
6896 #ifdef _LP64 |
|
df6caf649ff7
6700789: G1: Enable use of compressed oops with G1 heaps
ysr
parents:
775
diff
changeset
|
6897 load_heap_oop(tmp2, Address(obj, 0)); |
|
df6caf649ff7
6700789: G1: Enable use of compressed oops with G1 heaps
ysr
parents:
775
diff
changeset
|
6898 #else |
|
df6caf649ff7
6700789: G1: Enable use of compressed oops with G1 heaps
ysr
parents:
775
diff
changeset
|
6899 movptr(tmp2, Address(obj, 0)); |
|
df6caf649ff7
6700789: G1: Enable use of compressed oops with G1 heaps
ysr
parents:
775
diff
changeset
|
6900 #endif |
|
df6caf649ff7
6700789: G1: Enable use of compressed oops with G1 heaps
ysr
parents:
775
diff
changeset
|
6901 cmpptr(tmp2, (int32_t) NULL_WORD); |
| 362 | 6902 jcc(Assembler::equal, done); |
| 6903 | |
| 6904 // Can we store original value in the thread's buffer? | |
| 6905 | |
| 6906 #ifdef _LP64 | |
|
845
df6caf649ff7
6700789: G1: Enable use of compressed oops with G1 heaps
ysr
parents:
775
diff
changeset
|
6907 movslq(tmp, index); |
| 362 | 6908 cmpq(tmp, 0); |
| 6909 #else | |
| 6910 cmpl(index, 0); | |
| 6911 #endif | |
| 6912 jcc(Assembler::equal, runtime); | |
| 6913 #ifdef _LP64 | |
| 6914 subq(tmp, wordSize); | |
| 6915 movl(index, tmp); | |
| 6916 addq(tmp, buffer); | |
| 6917 #else | |
| 6918 subl(index, wordSize); | |
| 6919 movl(tmp, buffer); | |
| 6920 addl(tmp, index); | |
| 6921 #endif | |
| 6922 movptr(Address(tmp, 0), tmp2); | |
| 6923 jmp(done); | |
| 6924 bind(runtime); | |
| 6925 // save the live input values | |
| 6926 if(tosca_live) push(rax); | |
| 6927 push(obj); | |
| 6928 #ifdef _LP64 | |
|
845
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|
6929 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), tmp2, r15_thread); |
| 362 | 6930 #else |
| 6931 push(thread); | |
| 6932 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), tmp2, thread); | |
| 6933 pop(thread); | |
| 6934 #endif | |
| 6935 pop(obj); | |
| 6936 if(tosca_live) pop(rax); | |
| 6937 bind(done); | |
| 6938 | |
| 6939 } | |
| 6940 | |
| 6941 void MacroAssembler::g1_write_barrier_post(Register store_addr, | |
| 6942 Register new_val, | |
| 6943 #ifndef _LP64 | |
| 6944 Register thread, | |
| 6945 #endif | |
| 6946 Register tmp, | |
| 6947 Register tmp2) { | |
| 6948 | |
| 6949 LP64_ONLY(Register thread = r15_thread;) | |
| 6950 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() + | |
| 6951 PtrQueue::byte_offset_of_index())); | |
| 6952 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() + | |
| 6953 PtrQueue::byte_offset_of_buf())); | |
| 6954 BarrierSet* bs = Universe::heap()->barrier_set(); | |
| 6955 CardTableModRefBS* ct = (CardTableModRefBS*)bs; | |
| 6956 Label done; | |
| 6957 Label runtime; | |
| 6958 | |
| 6959 // Does store cross heap regions? | |
| 6960 | |
| 6961 movptr(tmp, store_addr); | |
| 6962 xorptr(tmp, new_val); | |
| 6963 shrptr(tmp, HeapRegion::LogOfHRGrainBytes); | |
| 6964 jcc(Assembler::equal, done); | |
| 6965 | |
| 6966 // crosses regions, storing NULL? | |
| 6967 | |
| 6968 cmpptr(new_val, (int32_t) NULL_WORD); | |
| 6969 jcc(Assembler::equal, done); | |
| 6970 | |
| 6971 // storing region crossing non-NULL, is card already dirty? | |
| 6972 | |
| 6973 ExternalAddress cardtable((address) ct->byte_map_base); | |
| 6974 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); | |
| 6975 #ifdef _LP64 | |
| 6976 const Register card_addr = tmp; | |
| 6977 | |
| 6978 movq(card_addr, store_addr); | |
| 6979 shrq(card_addr, CardTableModRefBS::card_shift); | |
| 6980 | |
| 6981 lea(tmp2, cardtable); | |
| 6982 | |
| 6983 // get the address of the card | |
| 6984 addq(card_addr, tmp2); | |
| 6985 #else | |
| 6986 const Register card_index = tmp; | |
| 6987 | |
| 6988 movl(card_index, store_addr); | |
| 6989 shrl(card_index, CardTableModRefBS::card_shift); | |
| 6990 | |
| 6991 Address index(noreg, card_index, Address::times_1); | |
| 6992 const Register card_addr = tmp; | |
| 6993 lea(card_addr, as_Address(ArrayAddress(cardtable, index))); | |
| 6994 #endif | |
| 6995 cmpb(Address(card_addr, 0), 0); | |
| 6996 jcc(Assembler::equal, done); | |
| 6997 | |
| 6998 // storing a region crossing, non-NULL oop, card is clean. | |
| 6999 // dirty card and log. | |
| 7000 | |
| 7001 movb(Address(card_addr, 0), 0); | |
| 7002 | |
| 7003 cmpl(queue_index, 0); | |
| 7004 jcc(Assembler::equal, runtime); | |
| 7005 subl(queue_index, wordSize); | |
| 7006 movptr(tmp2, buffer); | |
| 7007 #ifdef _LP64 | |
| 7008 movslq(rscratch1, queue_index); | |
| 7009 addq(tmp2, rscratch1); | |
| 7010 movq(Address(tmp2, 0), card_addr); | |
| 7011 #else | |
| 7012 addl(tmp2, queue_index); | |
| 7013 movl(Address(tmp2, 0), card_index); | |
| 7014 #endif | |
| 7015 jmp(done); | |
| 7016 | |
| 7017 bind(runtime); | |
| 7018 // save the live input values | |
| 7019 push(store_addr); | |
| 7020 push(new_val); | |
| 7021 #ifdef _LP64 | |
| 7022 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread); | |
| 7023 #else | |
| 7024 push(thread); | |
| 7025 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread); | |
| 7026 pop(thread); | |
| 7027 #endif | |
| 7028 pop(new_val); | |
| 7029 pop(store_addr); | |
| 7030 | |
| 7031 bind(done); | |
| 7032 | |
| 7033 } | |
| 7034 | |
| 7035 #endif // SERIALGC | |
| 7036 ////////////////////////////////////////////////////////////////////////////////// | |
| 7037 | |
| 7038 | |
| 304 | 7039 void MacroAssembler::store_check(Register obj) { |
| 7040 // Does a store check for the oop in register obj. The content of | |
| 7041 // register obj is destroyed afterwards. | |
| 7042 store_check_part_1(obj); | |
| 7043 store_check_part_2(obj); | |
| 7044 } | |
| 7045 | |
| 7046 void MacroAssembler::store_check(Register obj, Address dst) { | |
| 7047 store_check(obj); | |
| 7048 } | |
| 7049 | |
| 7050 | |
| 7051 // split the store check operation so that other instructions can be scheduled inbetween | |
| 7052 void MacroAssembler::store_check_part_1(Register obj) { | |
| 7053 BarrierSet* bs = Universe::heap()->barrier_set(); | |
| 7054 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind"); | |
| 7055 shrptr(obj, CardTableModRefBS::card_shift); | |
| 7056 } | |
| 7057 | |
| 7058 void MacroAssembler::store_check_part_2(Register obj) { | |
| 7059 BarrierSet* bs = Universe::heap()->barrier_set(); | |
| 7060 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind"); | |
| 7061 CardTableModRefBS* ct = (CardTableModRefBS*)bs; | |
| 7062 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); | |
| 7063 | |
| 7064 // The calculation for byte_map_base is as follows: | |
| 7065 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift); | |
| 7066 // So this essentially converts an address to a displacement and | |
| 7067 // it will never need to be relocated. On 64bit however the value may be too | |
| 7068 // large for a 32bit displacement | |
| 7069 | |
| 7070 intptr_t disp = (intptr_t) ct->byte_map_base; | |
| 7071 if (is_simm32(disp)) { | |
| 7072 Address cardtable(noreg, obj, Address::times_1, disp); | |
| 7073 movb(cardtable, 0); | |
| 7074 } else { | |
| 7075 // By doing it as an ExternalAddress disp could be converted to a rip-relative | |
| 7076 // displacement and done in a single instruction given favorable mapping and | |
| 7077 // a smarter version of as_Address. Worst case it is two instructions which | |
| 7078 // is no worse off then loading disp into a register and doing as a simple | |
| 7079 // Address() as above. | |
| 7080 // We can't do as ExternalAddress as the only style since if disp == 0 we'll | |
| 7081 // assert since NULL isn't acceptable in a reloci (see 6644928). In any case | |
| 7082 // in some cases we'll get a single instruction version. | |
| 7083 | |
| 7084 ExternalAddress cardtable((address)disp); | |
| 7085 Address index(noreg, obj, Address::times_1); | |
| 7086 movb(as_Address(ArrayAddress(cardtable, index)), 0); | |
| 7087 } | |
| 7088 } | |
| 7089 | |
| 7090 void MacroAssembler::subptr(Register dst, int32_t imm32) { | |
| 7091 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32)); | |
| 7092 } | |
| 7093 | |
| 7094 void MacroAssembler::subptr(Register dst, Register src) { | |
| 7095 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); | |
| 7096 } | |
| 7097 | |
| 7098 void MacroAssembler::test32(Register src1, AddressLiteral src2) { | |
| 7099 // src2 must be rval | |
| 7100 | |
| 7101 if (reachable(src2)) { | |
| 7102 testl(src1, as_Address(src2)); | |
| 7103 } else { | |
| 7104 lea(rscratch1, src2); | |
| 7105 testl(src1, Address(rscratch1, 0)); | |
| 7106 } | |
| 7107 } | |
| 7108 | |
| 7109 // C++ bool manipulation | |
| 0 | 7110 void MacroAssembler::testbool(Register dst) { |
| 7111 if(sizeof(bool) == 1) | |
| 304 | 7112 testb(dst, 0xff); |
| 0 | 7113 else if(sizeof(bool) == 2) { |
| 7114 // testw implementation needed for two byte bools | |
| 7115 ShouldNotReachHere(); | |
| 7116 } else if(sizeof(bool) == 4) | |
| 7117 testl(dst, dst); | |
| 7118 else | |
| 7119 // unsupported | |
| 7120 ShouldNotReachHere(); | |
| 7121 } | |
| 7122 | |
| 304 | 7123 void MacroAssembler::testptr(Register dst, Register src) { |
| 7124 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src)); | |
| 7125 } | |
| 7126 | |
| 7127 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. | |
| 7128 void MacroAssembler::tlab_allocate(Register obj, | |
| 7129 Register var_size_in_bytes, | |
| 7130 int con_size_in_bytes, | |
| 7131 Register t1, | |
| 7132 Register t2, | |
| 7133 Label& slow_case) { | |
| 7134 assert_different_registers(obj, t1, t2); | |
| 7135 assert_different_registers(obj, var_size_in_bytes, t1); | |
| 7136 Register end = t2; | |
| 7137 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread); | |
| 7138 | |
| 7139 verify_tlab(); | |
| 7140 | |
| 7141 NOT_LP64(get_thread(thread)); | |
| 7142 | |
| 7143 movptr(obj, Address(thread, JavaThread::tlab_top_offset())); | |
| 7144 if (var_size_in_bytes == noreg) { | |
| 7145 lea(end, Address(obj, con_size_in_bytes)); | |
| 7146 } else { | |
| 7147 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); | |
| 7148 } | |
| 7149 cmpptr(end, Address(thread, JavaThread::tlab_end_offset())); | |
| 7150 jcc(Assembler::above, slow_case); | |
| 7151 | |
| 7152 // update the tlab top pointer | |
| 7153 movptr(Address(thread, JavaThread::tlab_top_offset()), end); | |
| 7154 | |
| 7155 // recover var_size_in_bytes if necessary | |
| 7156 if (var_size_in_bytes == end) { | |
| 7157 subptr(var_size_in_bytes, obj); | |
| 7158 } | |
| 7159 verify_tlab(); | |
| 7160 } | |
| 7161 | |
| 7162 // Preserves rbx, and rdx. | |
|
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7163 Register MacroAssembler::tlab_refill(Label& retry, |
|
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7164 Label& try_eden, |
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7165 Label& slow_case) { |
| 304 | 7166 Register top = rax; |
| 7167 Register t1 = rcx; | |
| 7168 Register t2 = rsi; | |
| 7169 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread); | |
| 7170 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx); | |
| 7171 Label do_refill, discard_tlab; | |
| 7172 | |
| 7173 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { | |
| 7174 // No allocation in the shared eden. | |
| 7175 jmp(slow_case); | |
| 7176 } | |
| 7177 | |
| 7178 NOT_LP64(get_thread(thread_reg)); | |
| 7179 | |
| 7180 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); | |
| 7181 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); | |
| 7182 | |
| 7183 // calculate amount of free space | |
| 7184 subptr(t1, top); | |
| 7185 shrptr(t1, LogHeapWordSize); | |
| 7186 | |
| 7187 // Retain tlab and allocate object in shared space if | |
| 7188 // the amount free in the tlab is too large to discard. | |
| 7189 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); | |
| 7190 jcc(Assembler::lessEqual, discard_tlab); | |
| 7191 | |
| 7192 // Retain | |
| 7193 // %%% yuck as movptr... | |
| 7194 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment()); | |
| 7195 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2); | |
| 7196 if (TLABStats) { | |
| 7197 // increment number of slow_allocations | |
| 7198 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1); | |
| 7199 } | |
| 7200 jmp(try_eden); | |
| 7201 | |
| 7202 bind(discard_tlab); | |
| 7203 if (TLABStats) { | |
| 7204 // increment number of refills | |
| 7205 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1); | |
| 7206 // accumulate wastage -- t1 is amount free in tlab | |
| 7207 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1); | |
| 7208 } | |
| 7209 | |
| 7210 // if tlab is currently allocated (top or end != null) then | |
| 7211 // fill [top, end + alignment_reserve) with array object | |
|
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7212 testptr(top, top); |
| 304 | 7213 jcc(Assembler::zero, do_refill); |
| 7214 | |
| 7215 // set up the mark word | |
| 7216 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2)); | |
| 7217 // set the length to the remaining space | |
| 7218 subptr(t1, typeArrayOopDesc::header_size(T_INT)); | |
| 7219 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve()); | |
| 7220 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint))); | |
| 1690 | 7221 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1); |
| 304 | 7222 // set klass to intArrayKlass |
| 7223 // dubious reloc why not an oop reloc? | |
|
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7224 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr())); |
| 304 | 7225 // store klass last. concurrent gcs assumes klass length is valid if |
| 7226 // klass field is not null. | |
| 7227 store_klass(top, t1); | |
| 7228 | |
|
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7229 movptr(t1, top); |
|
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7230 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); |
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7231 incr_allocated_bytes(thread_reg, t1, 0); |
|
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|
7232 |
| 304 | 7233 // refill the tlab with an eden allocation |
| 7234 bind(do_refill); | |
| 7235 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); | |
| 7236 shlptr(t1, LogHeapWordSize); | |
|
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7237 // allocate new tlab, address returned in top |
| 304 | 7238 eden_allocate(top, t1, 0, t2, slow_case); |
| 7239 | |
| 7240 // Check that t1 was preserved in eden_allocate. | |
| 7241 #ifdef ASSERT | |
| 7242 if (UseTLAB) { | |
| 7243 Label ok; | |
| 7244 Register tsize = rsi; | |
| 7245 assert_different_registers(tsize, thread_reg, t1); | |
| 7246 push(tsize); | |
| 7247 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); | |
| 7248 shlptr(tsize, LogHeapWordSize); | |
| 7249 cmpptr(t1, tsize); | |
| 7250 jcc(Assembler::equal, ok); | |
| 7251 stop("assert(t1 != tlab size)"); | |
| 7252 should_not_reach_here(); | |
| 7253 | |
| 7254 bind(ok); | |
| 7255 pop(tsize); | |
| 7256 } | |
| 7257 #endif | |
| 7258 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top); | |
| 7259 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top); | |
| 7260 addptr(top, t1); | |
| 7261 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes()); | |
| 7262 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top); | |
| 7263 verify_tlab(); | |
| 7264 jmp(retry); | |
|
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7265 |
|
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7266 return thread_reg; // for use by caller |
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7267 } |
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7268 |
|
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7269 void MacroAssembler::incr_allocated_bytes(Register thread, |
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7270 Register var_size_in_bytes, |
|
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7271 int con_size_in_bytes, |
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|
7272 Register t1) { |
|
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7273 #ifdef _LP64 |
|
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7274 if (var_size_in_bytes->is_valid()) { |
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7275 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); |
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7276 } else { |
|
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7277 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); |
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7278 } |
|
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7279 #else |
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|
7280 if (!thread->is_valid()) { |
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|
7281 assert(t1->is_valid(), "need temp reg"); |
|
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7282 thread = t1; |
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|
7283 get_thread(thread); |
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7284 } |
|
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|
7285 |
|
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|
7286 if (var_size_in_bytes->is_valid()) { |
|
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|
7287 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); |
|
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7288 } else { |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7289 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7290 } |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7291 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0); |
|
b1a2afa37ec4
7003271: Hotspot should track cumulative Java heap bytes allocated on a per-thread basis
phh
parents:
2014
diff
changeset
|
7292 #endif |
| 304 | 7293 } |
| 7294 | |
| 7295 static const double pi_4 = 0.7853981633974483; | |
| 7296 | |
| 7297 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) { | |
| 7298 // A hand-coded argument reduction for values in fabs(pi/4, pi/2) | |
| 7299 // was attempted in this code; unfortunately it appears that the | |
| 7300 // switch to 80-bit precision and back causes this to be | |
| 7301 // unprofitable compared with simply performing a runtime call if | |
| 7302 // the argument is out of the (-pi/4, pi/4) range. | |
| 7303 | |
| 7304 Register tmp = noreg; | |
| 7305 if (!VM_Version::supports_cmov()) { | |
| 7306 // fcmp needs a temporary so preserve rbx, | |
| 7307 tmp = rbx; | |
| 7308 push(tmp); | |
| 7309 } | |
| 7310 | |
| 7311 Label slow_case, done; | |
| 7312 | |
|
520
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7313 ExternalAddress pi4_adr = (address)&pi_4; |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7314 if (reachable(pi4_adr)) { |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7315 // x ?<= pi/4 |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7316 fld_d(pi4_adr); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7317 fld_s(1); // Stack: X PI/4 X |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7318 fabs(); // Stack: |X| PI/4 X |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7319 fcmp(tmp); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7320 jcc(Assembler::above, slow_case); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7321 |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7322 // fastest case: -pi/4 <= x <= pi/4 |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7323 switch(trig) { |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7324 case 's': |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7325 fsin(); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7326 break; |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7327 case 'c': |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7328 fcos(); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7329 break; |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7330 case 't': |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7331 ftan(); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7332 break; |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7333 default: |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7334 assert(false, "bad intrinsic"); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7335 break; |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7336 } |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7337 jmp(done); |
|
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
parents:
512
diff
changeset
|
7338 } |
| 304 | 7339 |
| 7340 // slow case: runtime call | |
| 7341 bind(slow_case); | |
| 7342 // Preserve registers across runtime call | |
| 7343 pusha(); | |
| 7344 int incoming_argument_and_return_value_offset = -1; | |
| 7345 if (num_fpu_regs_in_use > 1) { | |
| 7346 // Must preserve all other FPU regs (could alternatively convert | |
| 7347 // SharedRuntime::dsin and dcos into assembly routines known not to trash | |
| 7348 // FPU state, but can not trust C compiler) | |
| 7349 NEEDS_CLEANUP; | |
| 7350 // NOTE that in this case we also push the incoming argument to | |
| 7351 // the stack and restore it later; we also use this stack slot to | |
| 7352 // hold the return value from dsin or dcos. | |
| 7353 for (int i = 0; i < num_fpu_regs_in_use; i++) { | |
| 7354 subptr(rsp, sizeof(jdouble)); | |
| 7355 fstp_d(Address(rsp, 0)); | |
| 7356 } | |
| 7357 incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1); | |
| 7358 fld_d(Address(rsp, incoming_argument_and_return_value_offset)); | |
| 7359 } | |
| 7360 subptr(rsp, sizeof(jdouble)); | |
| 7361 fstp_d(Address(rsp, 0)); | |
| 7362 #ifdef _LP64 | |
| 7363 movdbl(xmm0, Address(rsp, 0)); | |
| 7364 #endif // _LP64 | |
| 7365 | |
| 7366 // NOTE: we must not use call_VM_leaf here because that requires a | |
| 7367 // complete interpreter frame in debug mode -- same bug as 4387334 | |
| 7368 // MacroAssembler::call_VM_leaf_base is perfectly safe and will | |
| 7369 // do proper 64bit abi | |
| 7370 | |
| 7371 NEEDS_CLEANUP; | |
| 7372 // Need to add stack banging before this runtime call if it needs to | |
| 7373 // be taken; however, there is no generic stack banging routine at | |
| 7374 // the MacroAssembler level | |
| 7375 switch(trig) { | |
| 7376 case 's': | |
| 7377 { | |
| 7378 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 0); | |
| 7379 } | |
| 7380 break; | |
| 7381 case 'c': | |
| 7382 { | |
| 7383 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 0); | |
| 7384 } | |
| 7385 break; | |
| 7386 case 't': | |
| 7387 { | |
| 7388 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 0); | |
| 7389 } | |
| 7390 break; | |
| 7391 default: | |
| 7392 assert(false, "bad intrinsic"); | |
| 7393 break; | |
| 7394 } | |
| 7395 #ifdef _LP64 | |
| 7396 movsd(Address(rsp, 0), xmm0); | |
| 7397 fld_d(Address(rsp, 0)); | |
| 7398 #endif // _LP64 | |
| 7399 addptr(rsp, sizeof(jdouble)); | |
| 7400 if (num_fpu_regs_in_use > 1) { | |
| 7401 // Must save return value to stack and then restore entire FPU stack | |
| 7402 fstp_d(Address(rsp, incoming_argument_and_return_value_offset)); | |
| 7403 for (int i = 0; i < num_fpu_regs_in_use; i++) { | |
| 7404 fld_d(Address(rsp, 0)); | |
| 7405 addptr(rsp, sizeof(jdouble)); | |
| 7406 } | |
| 7407 } | |
| 7408 popa(); | |
| 7409 | |
| 7410 // Come here with result in F-TOS | |
| 7411 bind(done); | |
| 7412 | |
| 7413 if (tmp != noreg) { | |
| 7414 pop(tmp); | |
| 7415 } | |
| 7416 } | |
| 7417 | |
| 7418 | |
|
623
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7419 // Look up the method for a megamorphic invokeinterface call. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7420 // The target method is determined by <intf_klass, itable_index>. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7421 // The receiver klass is in recv_klass. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7422 // On success, the result will be in method_result, and execution falls through. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7423 // On failure, execution transfers to the given label. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7424 void MacroAssembler::lookup_interface_method(Register recv_klass, |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7425 Register intf_klass, |
|
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
7426 RegisterOrConstant itable_index, |
|
623
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7427 Register method_result, |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7428 Register scan_temp, |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7429 Label& L_no_such_interface) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7430 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7431 assert(itable_index.is_constant() || itable_index.as_register() == method_result, |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7432 "caller must use same register for non-constant itable index as for method"); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7433 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7434 // Compute start of first itableOffsetEntry (which is at the end of the vtable) |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7435 int vtable_base = instanceKlass::vtable_start_offset() * wordSize; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7436 int itentry_off = itableMethodEntry::method_offset_in_bytes(); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7437 int scan_step = itableOffsetEntry::size() * wordSize; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7438 int vte_size = vtableEntry::size() * wordSize; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7439 Address::ScaleFactor times_vte_scale = Address::times_ptr; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7440 assert(vte_size == wordSize, "else adjust times_vte_scale"); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7441 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7442 movl(scan_temp, Address(recv_klass, instanceKlass::vtable_length_offset() * wordSize)); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7443 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7444 // %%% Could store the aligned, prescaled offset in the klassoop. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7445 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base)); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7446 if (HeapWordsPerLong > 1) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7447 // Round up to align_object_offset boundary |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7448 // see code for instanceKlass::start_of_itable! |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7449 round_to(scan_temp, BytesPerLong); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7450 } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7451 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7452 // Adjust recv_klass by scaled itable_index, so we can free itable_index. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7453 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7454 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off)); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7455 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7456 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7457 // if (scan->interface() == intf) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7458 // result = (klass + scan->offset() + itable_index); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7459 // } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7460 // } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7461 Label search, found_method; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7462 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7463 for (int peel = 1; peel >= 0; peel--) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7464 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes())); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7465 cmpptr(intf_klass, method_result); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7466 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7467 if (peel) { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7468 jccb(Assembler::equal, found_method); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7469 } else { |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7470 jccb(Assembler::notEqual, search); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7471 // (invert the test to fall through to found_method...) |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7472 } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7473 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7474 if (!peel) break; |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7475 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7476 bind(search); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7477 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7478 // Check that the previous entry is non-null. A null entry means that |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7479 // the receiver class doesn't implement the interface, and wasn't the |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7480 // same as when the caller was compiled. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7481 testptr(method_result, method_result); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7482 jcc(Assembler::zero, L_no_such_interface); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7483 addptr(scan_temp, scan_step); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7484 } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7485 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7486 bind(found_method); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7487 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7488 // Got a hit. |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7489 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes())); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7490 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1)); |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7491 } |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7492 |
|
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7493 |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7494 void MacroAssembler::check_klass_subtype(Register sub_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7495 Register super_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7496 Register temp_reg, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7497 Label& L_success) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7498 Label L_failure; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7499 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7500 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7501 bind(L_failure); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7502 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7503 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7504 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7505 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7506 Register super_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7507 Register temp_reg, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7508 Label* L_success, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7509 Label* L_failure, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7510 Label* L_slow_path, |
|
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
7511 RegisterOrConstant super_check_offset) { |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7512 assert_different_registers(sub_klass, super_klass, temp_reg); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7513 bool must_load_sco = (super_check_offset.constant_or_zero() == -1); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7514 if (super_check_offset.is_register()) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7515 assert_different_registers(sub_klass, super_klass, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7516 super_check_offset.as_register()); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7517 } else if (must_load_sco) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7518 assert(temp_reg != noreg, "supply either a temp or a register offset"); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7519 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7520 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7521 Label L_fallthrough; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7522 int label_nulls = 0; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7523 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7524 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7525 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7526 assert(label_nulls <= 1, "at most one NULL in the batch"); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7527 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7528 int sc_offset = (klassOopDesc::header_size() * HeapWordSize + |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7529 Klass::secondary_super_cache_offset_in_bytes()); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7530 int sco_offset = (klassOopDesc::header_size() * HeapWordSize + |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7531 Klass::super_check_offset_offset_in_bytes()); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7532 Address super_check_offset_addr(super_klass, sco_offset); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7533 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7534 // Hacked jcc, which "knows" that L_fallthrough, at least, is in |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7535 // range of a jccb. If this routine grows larger, reconsider at |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7536 // least some of these. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7537 #define local_jcc(assembler_cond, label) \ |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7538 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \ |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7539 else jcc( assembler_cond, label) /*omit semi*/ |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7540 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7541 // Hacked jmp, which may only be used just before L_fallthrough. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7542 #define final_jmp(label) \ |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7543 if (&(label) == &L_fallthrough) { /*do nothing*/ } \ |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7544 else jmp(label) /*omit semi*/ |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7545 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7546 // If the pointers are equal, we are done (e.g., String[] elements). |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7547 // This self-check enables sharing of secondary supertype arrays among |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7548 // non-primary types such as array-of-interface. Otherwise, each such |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7549 // type would need its own customized SSA. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7550 // We move this check to the front of the fast path because many |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7551 // type checks are in fact trivially successful in this manner, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7552 // so we get a nicely predicted branch right at the start of the check. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7553 cmpptr(sub_klass, super_klass); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7554 local_jcc(Assembler::equal, *L_success); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7555 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7556 // Check the supertype display: |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7557 if (must_load_sco) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7558 // Positive movl does right thing on LP64. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7559 movl(temp_reg, super_check_offset_addr); |
|
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
7560 super_check_offset = RegisterOrConstant(temp_reg); |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7561 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7562 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7563 cmpptr(super_klass, super_check_addr); // load displayed supertype |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7564 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7565 // This check has worked decisively for primary supers. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7566 // Secondary supers are sought in the super_cache ('super_cache_addr'). |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7567 // (Secondary supers are interfaces and very deeply nested subtypes.) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7568 // This works in the same check above because of a tricky aliasing |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7569 // between the super_cache and the primary super display elements. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7570 // (The 'super_check_addr' can address either, as the case requires.) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7571 // Note that the cache is updated below if it does not help us find |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7572 // what we need immediately. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7573 // So if it was a primary super, we can just fail immediately. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7574 // Otherwise, it's the slow path for us (no success at this point). |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7575 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7576 if (super_check_offset.is_register()) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7577 local_jcc(Assembler::equal, *L_success); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7578 cmpl(super_check_offset.as_register(), sc_offset); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7579 if (L_failure == &L_fallthrough) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7580 local_jcc(Assembler::equal, *L_slow_path); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7581 } else { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7582 local_jcc(Assembler::notEqual, *L_failure); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7583 final_jmp(*L_slow_path); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7584 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7585 } else if (super_check_offset.as_constant() == sc_offset) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7586 // Need a slow path; fast failure is impossible. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7587 if (L_slow_path == &L_fallthrough) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7588 local_jcc(Assembler::equal, *L_success); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7589 } else { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7590 local_jcc(Assembler::notEqual, *L_slow_path); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7591 final_jmp(*L_success); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7592 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7593 } else { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7594 // No slow path; it's a fast decision. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7595 if (L_failure == &L_fallthrough) { |
|
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7596 local_jcc(Assembler::equal, *L_success); |
|
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7597 } else { |
|
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7598 local_jcc(Assembler::notEqual, *L_failure); |
|
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
7599 final_jmp(*L_success); |
|
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7600 } |
|
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7601 } |
|
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jrose
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643
diff
changeset
|
7602 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7603 bind(L_fallthrough); |
|
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7604 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7605 #undef local_jcc |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7606 #undef final_jmp |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7607 } |
|
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7608 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7609 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7610 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, |
|
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643
diff
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|
7611 Register super_klass, |
|
c517646eef23
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parents:
643
diff
changeset
|
7612 Register temp_reg, |
|
c517646eef23
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643
diff
changeset
|
7613 Register temp2_reg, |
|
c517646eef23
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jrose
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643
diff
changeset
|
7614 Label* L_success, |
|
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jrose
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643
diff
changeset
|
7615 Label* L_failure, |
|
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parents:
643
diff
changeset
|
7616 bool set_cond_codes) { |
|
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diff
changeset
|
7617 assert_different_registers(sub_klass, super_klass, temp_reg); |
|
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diff
changeset
|
7618 if (temp2_reg != noreg) |
|
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7619 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg); |
|
c517646eef23
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diff
changeset
|
7620 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg) |
|
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diff
changeset
|
7621 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
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643
diff
changeset
|
7622 Label L_fallthrough; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7623 int label_nulls = 0; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
7624 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7625 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7626 assert(label_nulls <= 1, "at most one NULL in the batch"); |
|
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643
diff
changeset
|
7627 |
|
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7628 // a couple of useful fields in sub_klass: |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7629 int ss_offset = (klassOopDesc::header_size() * HeapWordSize + |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
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643
diff
changeset
|
7630 Klass::secondary_supers_offset_in_bytes()); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7631 int sc_offset = (klassOopDesc::header_size() * HeapWordSize + |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7632 Klass::secondary_super_cache_offset_in_bytes()); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7633 Address secondary_supers_addr(sub_klass, ss_offset); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7634 Address super_cache_addr( sub_klass, sc_offset); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7635 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7636 // Do a linear scan of the secondary super-klass chain. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7637 // This code is rarely used, so simplicity is a virtue here. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7638 // The repne_scan instruction uses fixed registers, which we must spill. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7639 // Don't worry too much about pre-existing connections with the input regs. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7640 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7641 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7642 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7643 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7644 // Get super_klass value into rax (even if it was in rdi or rcx). |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7645 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7646 if (super_klass != rax || UseCompressedOops) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7647 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7648 mov(rax, super_klass); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7649 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7650 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7651 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7652 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7653 #ifndef PRODUCT |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7654 int* pst_counter = &SharedRuntime::_partial_subtype_ctr; |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7655 ExternalAddress pst_counter_addr((address) pst_counter); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7656 NOT_LP64( incrementl(pst_counter_addr) ); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7657 LP64_ONLY( lea(rcx, pst_counter_addr) ); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7658 LP64_ONLY( incrementl(Address(rcx, 0)) ); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7659 #endif //PRODUCT |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7660 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7661 // We will consult the secondary-super array. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7662 movptr(rdi, secondary_supers_addr); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7663 // Load the array length. (Positive movl does right thing on LP64.) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7664 movl(rcx, Address(rdi, arrayOopDesc::length_offset_in_bytes())); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7665 // Skip to start of data. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7666 addptr(rdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT)); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7667 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7668 // Scan RCX words at [RDI] for an occurrence of RAX. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7669 // Set NZ/Z based on last compare. |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
7670 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
7671 // not change flags (only scas instruction which is repeated sets flags). |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
7672 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found. |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7673 #ifdef _LP64 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7674 // This part is tricky, as values in supers array could be 32 or 64 bit wide |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7675 // and we store values in objArrays always encoded, thus we need to encode |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7676 // the value of rax before repne. Note that rax is dead after the repne. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7677 if (UseCompressedOops) { |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
7678 encode_heap_oop_not_null(rax); // Changes flags. |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7679 // The superclass is never null; it would be a basic system error if a null |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7680 // pointer were to sneak in here. Note that we have already loaded the |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7681 // Klass::super_check_offset from the super_klass in the fast path, |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7682 // so if there is a null in that register, we are already in the afterlife. |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
7683 testl(rax,rax); // Set Z = 0 |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7684 repne_scanl(); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7685 } else |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7686 #endif // _LP64 |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
7687 { |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
7688 testptr(rax,rax); // Set Z = 0 |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7689 repne_scan(); |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
7690 } |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7691 // Unspill the temp. registers: |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7692 if (pushed_rdi) pop(rdi); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7693 if (pushed_rcx) pop(rcx); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7694 if (pushed_rax) pop(rax); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7695 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7696 if (set_cond_codes) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7697 // Special hack for the AD files: rdi is guaranteed non-zero. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7698 assert(!pushed_rdi, "rdi must be left non-NULL"); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7699 // Also, the condition codes are properly set Z/NZ on succeed/failure. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7700 } |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7701 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7702 if (L_failure == &L_fallthrough) |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7703 jccb(Assembler::notEqual, *L_failure); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7704 else jcc(Assembler::notEqual, *L_failure); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7705 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7706 // Success. Cache the super we found and proceed in triumph. |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7707 movptr(super_cache_addr, super_klass); |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7708 |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7709 if (L_success != &L_fallthrough) { |
|
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7710 jmp(*L_success); |
|
c517646eef23
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7711 } |
|
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7712 |
|
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|
7713 #undef IS_A_TEMP |
|
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7714 |
|
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|
7715 bind(L_fallthrough); |
|
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|
7716 } |
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|
7717 |
|
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|
7718 |
| 304 | 7719 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) { |
| 7720 ucomisd(dst, as_Address(src)); | |
| 7721 } | |
| 7722 | |
| 7723 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) { | |
| 7724 ucomiss(dst, as_Address(src)); | |
| 7725 } | |
| 7726 | |
| 7727 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) { | |
| 7728 if (reachable(src)) { | |
| 7729 xorpd(dst, as_Address(src)); | |
| 7730 } else { | |
| 7731 lea(rscratch1, src); | |
| 7732 xorpd(dst, Address(rscratch1, 0)); | |
| 7733 } | |
| 7734 } | |
| 7735 | |
| 7736 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) { | |
| 7737 if (reachable(src)) { | |
| 7738 xorps(dst, as_Address(src)); | |
| 7739 } else { | |
| 7740 lea(rscratch1, src); | |
| 7741 xorps(dst, Address(rscratch1, 0)); | |
| 7742 } | |
| 7743 } | |
| 7744 | |
| 0 | 7745 void MacroAssembler::verify_oop(Register reg, const char* s) { |
| 7746 if (!VerifyOops) return; | |
| 304 | 7747 |
| 0 | 7748 // Pass register number to verify_oop_subroutine |
| 7749 char* b = new char[strlen(s) + 50]; | |
| 7750 sprintf(b, "verify_oop: %s: %s", reg->name(), s); | |
| 1583 | 7751 #ifdef _LP64 |
| 7752 push(rscratch1); // save r10, trashed by movptr() | |
| 7753 #endif | |
| 304 | 7754 push(rax); // save rax, |
| 7755 push(reg); // pass register argument | |
| 0 | 7756 ExternalAddress buffer((address) b); |
| 304 | 7757 // avoid using pushptr, as it modifies scratch registers |
| 7758 // and our contract is not to modify anything | |
| 7759 movptr(rax, buffer.addr()); | |
| 7760 push(rax); | |
| 0 | 7761 // call indirectly to solve generation ordering problem |
| 7762 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); | |
| 7763 call(rax); | |
| 1583 | 7764 // Caller pops the arguments (oop, message) and restores rax, r10 |
| 0 | 7765 } |
| 7766 | |
| 7767 | |
|
665
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7768 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, |
|
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7769 Register tmp, |
|
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7770 int offset) { |
|
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7771 intptr_t value = *delayed_value_addr; |
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7772 if (value != 0) |
|
665
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7773 return RegisterOrConstant(value + offset); |
|
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7774 |
|
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|
7775 // load indirectly to solve generation ordering problem |
|
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7776 movptr(tmp, ExternalAddress((address) delayed_value_addr)); |
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7777 |
|
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|
7778 #ifdef ASSERT |
|
1793
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|
7779 { Label L; |
|
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|
7780 testptr(tmp, tmp); |
|
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7781 if (WizardMode) { |
|
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7782 jcc(Assembler::notZero, L); |
|
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7783 char* buf = new char[40]; |
|
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7784 sprintf(buf, "DelayedValue="INTPTR_FORMAT, delayed_value_addr[1]); |
|
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|
7785 stop(buf); |
|
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|
7786 } else { |
|
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|
7787 jccb(Assembler::notZero, L); |
|
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|
7788 hlt(); |
|
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|
7789 } |
|
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|
7790 bind(L); |
|
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|
7791 } |
|
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7792 #endif |
|
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7793 |
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7794 if (offset != 0) |
|
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|
7795 addptr(tmp, offset); |
|
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7796 |
|
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7797 return RegisterOrConstant(tmp); |
|
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7798 } |
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7799 |
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|
7800 |
| 710 | 7801 // registers on entry: |
| 7802 // - rax ('check' register): required MethodType | |
| 7803 // - rcx: method handle | |
| 7804 // - rdx, rsi, or ?: killable temp | |
| 7805 void MacroAssembler::check_method_handle_type(Register mtype_reg, Register mh_reg, | |
| 7806 Register temp_reg, | |
| 7807 Label& wrong_method_type) { | |
| 1846 | 7808 Address type_addr(mh_reg, delayed_value(java_dyn_MethodHandle::type_offset_in_bytes, temp_reg)); |
| 710 | 7809 // compare method type against that of the receiver |
| 1846 | 7810 if (UseCompressedOops) { |
| 7811 load_heap_oop(temp_reg, type_addr); | |
| 7812 cmpptr(mtype_reg, temp_reg); | |
| 7813 } else { | |
| 7814 cmpptr(mtype_reg, type_addr); | |
| 7815 } | |
| 710 | 7816 jcc(Assembler::notEqual, wrong_method_type); |
| 7817 } | |
| 7818 | |
| 7819 | |
| 7820 // A method handle has a "vmslots" field which gives the size of its | |
| 7821 // argument list in JVM stack slots. This field is either located directly | |
| 7822 // in every method handle, or else is indirectly accessed through the | |
| 7823 // method handle's MethodType. This macro hides the distinction. | |
| 7824 void MacroAssembler::load_method_handle_vmslots(Register vmslots_reg, Register mh_reg, | |
| 7825 Register temp_reg) { | |
| 1503 | 7826 assert_different_registers(vmslots_reg, mh_reg, temp_reg); |
| 710 | 7827 // load mh.type.form.vmslots |
| 7828 if (java_dyn_MethodHandle::vmslots_offset_in_bytes() != 0) { | |
| 7829 // hoist vmslots into every mh to avoid dependent load chain | |
| 7830 movl(vmslots_reg, Address(mh_reg, delayed_value(java_dyn_MethodHandle::vmslots_offset_in_bytes, temp_reg))); | |
| 7831 } else { | |
| 7832 Register temp2_reg = vmslots_reg; | |
| 1846 | 7833 load_heap_oop(temp2_reg, Address(mh_reg, delayed_value(java_dyn_MethodHandle::type_offset_in_bytes, temp_reg))); |
| 7834 load_heap_oop(temp2_reg, Address(temp2_reg, delayed_value(java_dyn_MethodType::form_offset_in_bytes, temp_reg))); | |
| 710 | 7835 movl(vmslots_reg, Address(temp2_reg, delayed_value(java_dyn_MethodTypeForm::vmslots_offset_in_bytes, temp_reg))); |
| 7836 } | |
| 7837 } | |
| 7838 | |
| 7839 | |
| 7840 // registers on entry: | |
| 7841 // - rcx: method handle | |
| 7842 // - rdx: killable temp (interpreted only) | |
| 7843 // - rax: killable temp (compiled only) | |
| 7844 void MacroAssembler::jump_to_method_handle_entry(Register mh_reg, Register temp_reg) { | |
| 7845 assert(mh_reg == rcx, "caller must put MH object in rcx"); | |
| 7846 assert_different_registers(mh_reg, temp_reg); | |
| 7847 | |
| 7848 // pick out the interpreted side of the handler | |
| 1846 | 7849 // NOTE: vmentry is not an oop! |
| 710 | 7850 movptr(temp_reg, Address(mh_reg, delayed_value(java_dyn_MethodHandle::vmentry_offset_in_bytes, temp_reg))); |
| 7851 | |
| 7852 // off we go... | |
| 7853 jmp(Address(temp_reg, MethodHandleEntry::from_interpreted_entry_offset_in_bytes())); | |
| 7854 | |
| 7855 // for the various stubs which take control at this point, | |
| 7856 // see MethodHandles::generate_method_handle_stub | |
| 7857 } | |
| 7858 | |
| 7859 | |
| 7860 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, | |
| 7861 int extra_slot_offset) { | |
| 7862 // cf. TemplateTable::prepare_invoke(), if (load_receiver). | |
| 1506 | 7863 int stackElementSize = Interpreter::stackElementSize; |
| 710 | 7864 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0); |
| 7865 #ifdef ASSERT | |
| 7866 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1); | |
| 7867 assert(offset1 - offset == stackElementSize, "correct arithmetic"); | |
| 7868 #endif | |
| 7869 Register scale_reg = noreg; | |
| 7870 Address::ScaleFactor scale_factor = Address::no_scale; | |
| 7871 if (arg_slot.is_constant()) { | |
| 7872 offset += arg_slot.as_constant() * stackElementSize; | |
| 7873 } else { | |
| 7874 scale_reg = arg_slot.as_register(); | |
| 7875 scale_factor = Address::times(stackElementSize); | |
| 7876 } | |
| 7877 offset += wordSize; // return PC is on stack | |
| 7878 return Address(rsp, scale_reg, scale_factor, offset); | |
| 7879 } | |
| 7880 | |
| 7881 | |
| 0 | 7882 void MacroAssembler::verify_oop_addr(Address addr, const char* s) { |
| 7883 if (!VerifyOops) return; | |
| 304 | 7884 |
| 0 | 7885 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord); |
| 7886 // Pass register number to verify_oop_subroutine | |
| 7887 char* b = new char[strlen(s) + 50]; | |
| 7888 sprintf(b, "verify_oop_addr: %s", s); | |
| 304 | 7889 |
| 1583 | 7890 #ifdef _LP64 |
| 7891 push(rscratch1); // save r10, trashed by movptr() | |
| 7892 #endif | |
| 304 | 7893 push(rax); // save rax, |
| 0 | 7894 // addr may contain rsp so we will have to adjust it based on the push |
| 7895 // we just did | |
| 304 | 7896 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which |
| 7897 // stores rax into addr which is backwards of what was intended. | |
| 0 | 7898 if (addr.uses(rsp)) { |
| 304 | 7899 lea(rax, addr); |
| 7900 pushptr(Address(rax, BytesPerWord)); | |
| 0 | 7901 } else { |
| 304 | 7902 pushptr(addr); |
| 7903 } | |
| 7904 | |
| 0 | 7905 ExternalAddress buffer((address) b); |
| 7906 // pass msg argument | |
| 304 | 7907 // avoid using pushptr, as it modifies scratch registers |
| 7908 // and our contract is not to modify anything | |
| 7909 movptr(rax, buffer.addr()); | |
| 7910 push(rax); | |
| 7911 | |
| 0 | 7912 // call indirectly to solve generation ordering problem |
| 7913 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); | |
| 7914 call(rax); | |
| 1583 | 7915 // Caller pops the arguments (addr, message) and restores rax, r10. |
| 0 | 7916 } |
| 7917 | |
| 304 | 7918 void MacroAssembler::verify_tlab() { |
| 7919 #ifdef ASSERT | |
| 7920 if (UseTLAB && VerifyOops) { | |
| 7921 Label next, ok; | |
| 7922 Register t1 = rsi; | |
| 7923 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread); | |
| 7924 | |
| 7925 push(t1); | |
| 7926 NOT_LP64(push(thread_reg)); | |
| 7927 NOT_LP64(get_thread(thread_reg)); | |
| 7928 | |
| 7929 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); | |
| 7930 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); | |
| 7931 jcc(Assembler::aboveEqual, next); | |
| 7932 stop("assert(top >= start)"); | |
| 7933 should_not_reach_here(); | |
| 7934 | |
| 7935 bind(next); | |
| 7936 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); | |
| 7937 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); | |
| 7938 jcc(Assembler::aboveEqual, ok); | |
| 7939 stop("assert(top <= end)"); | |
| 7940 should_not_reach_here(); | |
| 7941 | |
| 7942 bind(ok); | |
| 7943 NOT_LP64(pop(thread_reg)); | |
| 7944 pop(t1); | |
| 7945 } | |
| 7946 #endif | |
| 7947 } | |
| 0 | 7948 |
| 7949 class ControlWord { | |
| 7950 public: | |
| 7951 int32_t _value; | |
| 7952 | |
| 7953 int rounding_control() const { return (_value >> 10) & 3 ; } | |
| 7954 int precision_control() const { return (_value >> 8) & 3 ; } | |
| 7955 bool precision() const { return ((_value >> 5) & 1) != 0; } | |
| 7956 bool underflow() const { return ((_value >> 4) & 1) != 0; } | |
| 7957 bool overflow() const { return ((_value >> 3) & 1) != 0; } | |
| 7958 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } | |
| 7959 bool denormalized() const { return ((_value >> 1) & 1) != 0; } | |
| 7960 bool invalid() const { return ((_value >> 0) & 1) != 0; } | |
| 7961 | |
| 7962 void print() const { | |
| 7963 // rounding control | |
| 7964 const char* rc; | |
| 7965 switch (rounding_control()) { | |
| 7966 case 0: rc = "round near"; break; | |
| 7967 case 1: rc = "round down"; break; | |
| 7968 case 2: rc = "round up "; break; | |
| 7969 case 3: rc = "chop "; break; | |
| 7970 }; | |
| 7971 // precision control | |
| 7972 const char* pc; | |
| 7973 switch (precision_control()) { | |
| 7974 case 0: pc = "24 bits "; break; | |
| 7975 case 1: pc = "reserved"; break; | |
| 7976 case 2: pc = "53 bits "; break; | |
| 7977 case 3: pc = "64 bits "; break; | |
| 7978 }; | |
| 7979 // flags | |
| 7980 char f[9]; | |
| 7981 f[0] = ' '; | |
| 7982 f[1] = ' '; | |
| 7983 f[2] = (precision ()) ? 'P' : 'p'; | |
| 7984 f[3] = (underflow ()) ? 'U' : 'u'; | |
| 7985 f[4] = (overflow ()) ? 'O' : 'o'; | |
| 7986 f[5] = (zero_divide ()) ? 'Z' : 'z'; | |
| 7987 f[6] = (denormalized()) ? 'D' : 'd'; | |
| 7988 f[7] = (invalid ()) ? 'I' : 'i'; | |
| 7989 f[8] = '\x0'; | |
| 7990 // output | |
| 7991 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc); | |
| 7992 } | |
| 7993 | |
| 7994 }; | |
| 7995 | |
| 7996 class StatusWord { | |
| 7997 public: | |
| 7998 int32_t _value; | |
| 7999 | |
| 8000 bool busy() const { return ((_value >> 15) & 1) != 0; } | |
| 8001 bool C3() const { return ((_value >> 14) & 1) != 0; } | |
| 8002 bool C2() const { return ((_value >> 10) & 1) != 0; } | |
| 8003 bool C1() const { return ((_value >> 9) & 1) != 0; } | |
| 8004 bool C0() const { return ((_value >> 8) & 1) != 0; } | |
| 8005 int top() const { return (_value >> 11) & 7 ; } | |
| 8006 bool error_status() const { return ((_value >> 7) & 1) != 0; } | |
| 8007 bool stack_fault() const { return ((_value >> 6) & 1) != 0; } | |
| 8008 bool precision() const { return ((_value >> 5) & 1) != 0; } | |
| 8009 bool underflow() const { return ((_value >> 4) & 1) != 0; } | |
| 8010 bool overflow() const { return ((_value >> 3) & 1) != 0; } | |
| 8011 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } | |
| 8012 bool denormalized() const { return ((_value >> 1) & 1) != 0; } | |
| 8013 bool invalid() const { return ((_value >> 0) & 1) != 0; } | |
| 8014 | |
| 8015 void print() const { | |
| 8016 // condition codes | |
| 8017 char c[5]; | |
| 8018 c[0] = (C3()) ? '3' : '-'; | |
| 8019 c[1] = (C2()) ? '2' : '-'; | |
| 8020 c[2] = (C1()) ? '1' : '-'; | |
| 8021 c[3] = (C0()) ? '0' : '-'; | |
| 8022 c[4] = '\x0'; | |
| 8023 // flags | |
| 8024 char f[9]; | |
| 8025 f[0] = (error_status()) ? 'E' : '-'; | |
| 8026 f[1] = (stack_fault ()) ? 'S' : '-'; | |
| 8027 f[2] = (precision ()) ? 'P' : '-'; | |
| 8028 f[3] = (underflow ()) ? 'U' : '-'; | |
| 8029 f[4] = (overflow ()) ? 'O' : '-'; | |
| 8030 f[5] = (zero_divide ()) ? 'Z' : '-'; | |
| 8031 f[6] = (denormalized()) ? 'D' : '-'; | |
| 8032 f[7] = (invalid ()) ? 'I' : '-'; | |
| 8033 f[8] = '\x0'; | |
| 8034 // output | |
| 8035 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top()); | |
| 8036 } | |
| 8037 | |
| 8038 }; | |
| 8039 | |
| 8040 class TagWord { | |
| 8041 public: | |
| 8042 int32_t _value; | |
| 8043 | |
| 8044 int tag_at(int i) const { return (_value >> (i*2)) & 3; } | |
| 8045 | |
| 8046 void print() const { | |
| 8047 printf("%04x", _value & 0xFFFF); | |
| 8048 } | |
| 8049 | |
| 8050 }; | |
| 8051 | |
| 8052 class FPU_Register { | |
| 8053 public: | |
| 8054 int32_t _m0; | |
| 8055 int32_t _m1; | |
| 8056 int16_t _ex; | |
| 8057 | |
| 8058 bool is_indefinite() const { | |
| 8059 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0; | |
| 8060 } | |
| 8061 | |
| 8062 void print() const { | |
| 8063 char sign = (_ex < 0) ? '-' : '+'; | |
| 8064 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " "; | |
| 8065 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind); | |
| 8066 }; | |
| 8067 | |
| 8068 }; | |
| 8069 | |
| 8070 class FPU_State { | |
| 8071 public: | |
| 8072 enum { | |
| 8073 register_size = 10, | |
| 8074 number_of_registers = 8, | |
| 8075 register_mask = 7 | |
| 8076 }; | |
| 8077 | |
| 8078 ControlWord _control_word; | |
| 8079 StatusWord _status_word; | |
| 8080 TagWord _tag_word; | |
| 8081 int32_t _error_offset; | |
| 8082 int32_t _error_selector; | |
| 8083 int32_t _data_offset; | |
| 8084 int32_t _data_selector; | |
| 8085 int8_t _register[register_size * number_of_registers]; | |
| 8086 | |
| 8087 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); } | |
| 8088 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; } | |
| 8089 | |
| 8090 const char* tag_as_string(int tag) const { | |
| 8091 switch (tag) { | |
| 8092 case 0: return "valid"; | |
| 8093 case 1: return "zero"; | |
| 8094 case 2: return "special"; | |
| 8095 case 3: return "empty"; | |
| 8096 } | |
|
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|
8097 ShouldNotReachHere(); |
| 0 | 8098 return NULL; |
| 8099 } | |
| 8100 | |
| 8101 void print() const { | |
| 8102 // print computation registers | |
| 8103 { int t = _status_word.top(); | |
| 8104 for (int i = 0; i < number_of_registers; i++) { | |
| 8105 int j = (i - t) & register_mask; | |
| 8106 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j); | |
| 8107 st(j)->print(); | |
| 8108 printf(" %s\n", tag_as_string(_tag_word.tag_at(i))); | |
| 8109 } | |
| 8110 } | |
| 8111 printf("\n"); | |
| 8112 // print control registers | |
| 8113 printf("ctrl = "); _control_word.print(); printf("\n"); | |
| 8114 printf("stat = "); _status_word .print(); printf("\n"); | |
| 8115 printf("tags = "); _tag_word .print(); printf("\n"); | |
| 8116 } | |
| 8117 | |
| 8118 }; | |
| 8119 | |
| 8120 class Flag_Register { | |
| 8121 public: | |
| 8122 int32_t _value; | |
| 8123 | |
| 8124 bool overflow() const { return ((_value >> 11) & 1) != 0; } | |
| 8125 bool direction() const { return ((_value >> 10) & 1) != 0; } | |
| 8126 bool sign() const { return ((_value >> 7) & 1) != 0; } | |
| 8127 bool zero() const { return ((_value >> 6) & 1) != 0; } | |
| 8128 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; } | |
| 8129 bool parity() const { return ((_value >> 2) & 1) != 0; } | |
| 8130 bool carry() const { return ((_value >> 0) & 1) != 0; } | |
| 8131 | |
| 8132 void print() const { | |
| 8133 // flags | |
| 8134 char f[8]; | |
| 8135 f[0] = (overflow ()) ? 'O' : '-'; | |
| 8136 f[1] = (direction ()) ? 'D' : '-'; | |
| 8137 f[2] = (sign ()) ? 'S' : '-'; | |
| 8138 f[3] = (zero ()) ? 'Z' : '-'; | |
| 8139 f[4] = (auxiliary_carry()) ? 'A' : '-'; | |
| 8140 f[5] = (parity ()) ? 'P' : '-'; | |
| 8141 f[6] = (carry ()) ? 'C' : '-'; | |
| 8142 f[7] = '\x0'; | |
| 8143 // output | |
| 8144 printf("%08x flags = %s", _value, f); | |
| 8145 } | |
| 8146 | |
| 8147 }; | |
| 8148 | |
| 8149 class IU_Register { | |
| 8150 public: | |
| 8151 int32_t _value; | |
| 8152 | |
| 8153 void print() const { | |
| 8154 printf("%08x %11d", _value, _value); | |
| 8155 } | |
| 8156 | |
| 8157 }; | |
| 8158 | |
| 8159 class IU_State { | |
| 8160 public: | |
| 8161 Flag_Register _eflags; | |
| 8162 IU_Register _rdi; | |
| 8163 IU_Register _rsi; | |
| 8164 IU_Register _rbp; | |
| 8165 IU_Register _rsp; | |
| 8166 IU_Register _rbx; | |
| 8167 IU_Register _rdx; | |
| 8168 IU_Register _rcx; | |
| 8169 IU_Register _rax; | |
| 8170 | |
| 8171 void print() const { | |
| 8172 // computation registers | |
| 8173 printf("rax, = "); _rax.print(); printf("\n"); | |
| 8174 printf("rbx, = "); _rbx.print(); printf("\n"); | |
| 8175 printf("rcx = "); _rcx.print(); printf("\n"); | |
| 8176 printf("rdx = "); _rdx.print(); printf("\n"); | |
| 8177 printf("rdi = "); _rdi.print(); printf("\n"); | |
| 8178 printf("rsi = "); _rsi.print(); printf("\n"); | |
| 8179 printf("rbp, = "); _rbp.print(); printf("\n"); | |
| 8180 printf("rsp = "); _rsp.print(); printf("\n"); | |
| 8181 printf("\n"); | |
| 8182 // control registers | |
| 8183 printf("flgs = "); _eflags.print(); printf("\n"); | |
| 8184 } | |
| 8185 }; | |
| 8186 | |
| 8187 | |
| 8188 class CPU_State { | |
| 8189 public: | |
| 8190 FPU_State _fpu_state; | |
| 8191 IU_State _iu_state; | |
| 8192 | |
| 8193 void print() const { | |
| 8194 printf("--------------------------------------------------\n"); | |
| 8195 _iu_state .print(); | |
| 8196 printf("\n"); | |
| 8197 _fpu_state.print(); | |
| 8198 printf("--------------------------------------------------\n"); | |
| 8199 } | |
| 8200 | |
| 8201 }; | |
| 8202 | |
| 8203 | |
| 8204 static void _print_CPU_state(CPU_State* state) { | |
| 8205 state->print(); | |
| 8206 }; | |
| 8207 | |
| 8208 | |
| 8209 void MacroAssembler::print_CPU_state() { | |
| 8210 push_CPU_state(); | |
| 304 | 8211 push(rsp); // pass CPU state |
| 0 | 8212 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state))); |
| 304 | 8213 addptr(rsp, wordSize); // discard argument |
| 0 | 8214 pop_CPU_state(); |
| 8215 } | |
| 8216 | |
| 8217 | |
| 8218 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) { | |
| 8219 static int counter = 0; | |
| 8220 FPU_State* fs = &state->_fpu_state; | |
| 8221 counter++; | |
| 8222 // For leaf calls, only verify that the top few elements remain empty. | |
| 8223 // We only need 1 empty at the top for C2 code. | |
| 8224 if( stack_depth < 0 ) { | |
| 8225 if( fs->tag_for_st(7) != 3 ) { | |
| 8226 printf("FPR7 not empty\n"); | |
| 8227 state->print(); | |
| 8228 assert(false, "error"); | |
| 8229 return false; | |
| 8230 } | |
| 8231 return true; // All other stack states do not matter | |
| 8232 } | |
| 8233 | |
| 8234 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std, | |
| 8235 "bad FPU control word"); | |
| 8236 | |
| 8237 // compute stack depth | |
| 8238 int i = 0; | |
| 8239 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++; | |
| 8240 int d = i; | |
| 8241 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++; | |
| 8242 // verify findings | |
| 8243 if (i != FPU_State::number_of_registers) { | |
| 8244 // stack not contiguous | |
| 8245 printf("%s: stack not contiguous at ST%d\n", s, i); | |
| 8246 state->print(); | |
| 8247 assert(false, "error"); | |
| 8248 return false; | |
| 8249 } | |
| 8250 // check if computed stack depth corresponds to expected stack depth | |
| 8251 if (stack_depth < 0) { | |
| 8252 // expected stack depth is -stack_depth or less | |
| 8253 if (d > -stack_depth) { | |
| 8254 // too many elements on the stack | |
| 8255 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d); | |
| 8256 state->print(); | |
| 8257 assert(false, "error"); | |
| 8258 return false; | |
| 8259 } | |
| 8260 } else { | |
| 8261 // expected stack depth is stack_depth | |
| 8262 if (d != stack_depth) { | |
| 8263 // wrong stack depth | |
| 8264 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d); | |
| 8265 state->print(); | |
| 8266 assert(false, "error"); | |
| 8267 return false; | |
| 8268 } | |
| 8269 } | |
| 8270 // everything is cool | |
| 8271 return true; | |
| 8272 } | |
| 8273 | |
| 8274 | |
| 8275 void MacroAssembler::verify_FPU(int stack_depth, const char* s) { | |
| 8276 if (!VerifyFPU) return; | |
| 8277 push_CPU_state(); | |
| 304 | 8278 push(rsp); // pass CPU state |
| 0 | 8279 ExternalAddress msg((address) s); |
| 8280 // pass message string s | |
| 8281 pushptr(msg.addr()); | |
| 304 | 8282 push(stack_depth); // pass stack depth |
| 0 | 8283 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU))); |
| 304 | 8284 addptr(rsp, 3 * wordSize); // discard arguments |
| 0 | 8285 // check for error |
| 8286 { Label L; | |
| 8287 testl(rax, rax); | |
| 8288 jcc(Assembler::notZero, L); | |
| 8289 int3(); // break if error condition | |
| 8290 bind(L); | |
| 8291 } | |
| 8292 pop_CPU_state(); | |
| 8293 } | |
| 8294 | |
| 304 | 8295 void MacroAssembler::load_klass(Register dst, Register src) { |
| 8296 #ifdef _LP64 | |
| 8297 if (UseCompressedOops) { | |
| 8298 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); | |
| 8299 decode_heap_oop_not_null(dst); | |
| 8300 } else | |
| 8301 #endif | |
| 8302 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); | |
| 8303 } | |
| 8304 | |
| 8305 void MacroAssembler::load_prototype_header(Register dst, Register src) { | |
| 8306 #ifdef _LP64 | |
| 8307 if (UseCompressedOops) { | |
|
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|
8308 assert (Universe::heap() != NULL, "java heap should be initialized"); |
| 304 | 8309 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); |
|
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|
8310 if (Universe::narrow_oop_shift() != 0) { |
|
1571
2d127394260e
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|
8311 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
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|
8312 if (LogMinObjAlignmentInBytes == Address::times_8) { |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
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|
8313 movq(dst, Address(r12_heapbase, dst, Address::times_8, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); |
|
2d127394260e
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diff
changeset
|
8314 } else { |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
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diff
changeset
|
8315 // OK to use shift since we don't need to preserve flags. |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
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1513
diff
changeset
|
8316 shlq(dst, LogMinObjAlignmentInBytes); |
|
2d127394260e
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|
8317 movq(dst, Address(r12_heapbase, dst, Address::times_1, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); |
|
2d127394260e
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diff
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|
8318 } |
|
642
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|
8319 } else { |
|
660978a2a31a
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|
8320 movq(dst, Address(dst, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); |
|
660978a2a31a
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|
8321 } |
| 304 | 8322 } else |
| 8323 #endif | |
|
642
660978a2a31a
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|
8324 { |
|
660978a2a31a
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diff
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|
8325 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); |
|
660978a2a31a
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624
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|
8326 movptr(dst, Address(dst, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); |
|
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|
8327 } |
| 304 | 8328 } |
| 8329 | |
| 8330 void MacroAssembler::store_klass(Register dst, Register src) { | |
| 8331 #ifdef _LP64 | |
| 8332 if (UseCompressedOops) { | |
| 8333 encode_heap_oop_not_null(src); | |
| 8334 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src); | |
| 8335 } else | |
| 8336 #endif | |
| 8337 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src); | |
| 8338 } | |
| 8339 | |
| 1846 | 8340 void MacroAssembler::load_heap_oop(Register dst, Address src) { |
| 8341 #ifdef _LP64 | |
| 8342 if (UseCompressedOops) { | |
| 8343 movl(dst, src); | |
| 8344 decode_heap_oop(dst); | |
| 8345 } else | |
| 8346 #endif | |
| 8347 movptr(dst, src); | |
| 8348 } | |
| 8349 | |
| 8350 void MacroAssembler::store_heap_oop(Address dst, Register src) { | |
| 8351 #ifdef _LP64 | |
| 8352 if (UseCompressedOops) { | |
| 8353 assert(!dst.uses(src), "not enough registers"); | |
| 8354 encode_heap_oop(src); | |
| 8355 movl(dst, src); | |
| 8356 } else | |
| 8357 #endif | |
| 8358 movptr(dst, src); | |
| 8359 } | |
| 8360 | |
| 8361 // Used for storing NULLs. | |
| 8362 void MacroAssembler::store_heap_oop_null(Address dst) { | |
| 8363 #ifdef _LP64 | |
| 8364 if (UseCompressedOops) { | |
| 8365 movl(dst, (int32_t)NULL_WORD); | |
| 8366 } else { | |
| 8367 movslq(dst, (int32_t)NULL_WORD); | |
| 8368 } | |
| 8369 #else | |
| 8370 movl(dst, (int32_t)NULL_WORD); | |
| 8371 #endif | |
| 8372 } | |
| 8373 | |
| 304 | 8374 #ifdef _LP64 |
| 8375 void MacroAssembler::store_klass_gap(Register dst, Register src) { | |
| 8376 if (UseCompressedOops) { | |
| 8377 // Store to klass gap in destination | |
| 8378 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src); | |
| 8379 } | |
| 8380 } | |
| 8381 | |
|
1684
66c5dadb4d61
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|
8382 #ifdef ASSERT |
|
66c5dadb4d61
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|
8383 void MacroAssembler::verify_heapbase(const char* msg) { |
|
66c5dadb4d61
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diff
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|
8384 assert (UseCompressedOops, "should be compressed"); |
|
66c5dadb4d61
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diff
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|
8385 assert (Universe::heap() != NULL, "java heap should be initialized"); |
|
66c5dadb4d61
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diff
changeset
|
8386 if (CheckCompressedOops) { |
|
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diff
changeset
|
8387 Label ok; |
|
66c5dadb4d61
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diff
changeset
|
8388 push(rscratch1); // cmpptr trashes rscratch1 |
|
66c5dadb4d61
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|
8389 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_oop_base_addr())); |
|
66c5dadb4d61
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|
8390 jcc(Assembler::equal, ok); |
|
66c5dadb4d61
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diff
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|
8391 stop(msg); |
|
66c5dadb4d61
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changeset
|
8392 bind(ok); |
|
66c5dadb4d61
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changeset
|
8393 pop(rscratch1); |
|
66c5dadb4d61
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|
8394 } |
|
66c5dadb4d61
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|
8395 } |
|
66c5dadb4d61
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changeset
|
8396 #endif |
|
66c5dadb4d61
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|
8397 |
| 304 | 8398 // Algorithm must match oop.inline.hpp encode_heap_oop. |
| 8399 void MacroAssembler::encode_heap_oop(Register r) { | |
|
1684
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|
8400 #ifdef ASSERT |
|
66c5dadb4d61
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changeset
|
8401 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?"); |
|
66c5dadb4d61
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changeset
|
8402 #endif |
|
66c5dadb4d61
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diff
changeset
|
8403 verify_oop(r, "broken oop in encode_heap_oop"); |
|
642
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|
8404 if (Universe::narrow_oop_base() == NULL) { |
|
660978a2a31a
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changeset
|
8405 if (Universe::narrow_oop_shift() != 0) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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diff
changeset
|
8406 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
660978a2a31a
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diff
changeset
|
8407 shrq(r, LogMinObjAlignmentInBytes); |
|
660978a2a31a
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|
8408 } |
|
660978a2a31a
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diff
changeset
|
8409 return; |
|
660978a2a31a
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diff
changeset
|
8410 } |
| 304 | 8411 testq(r, r); |
| 8412 cmovq(Assembler::equal, r, r12_heapbase); | |
| 8413 subq(r, r12_heapbase); | |
| 8414 shrq(r, LogMinObjAlignmentInBytes); | |
| 8415 } | |
| 8416 | |
| 8417 void MacroAssembler::encode_heap_oop_not_null(Register r) { | |
| 0 | 8418 #ifdef ASSERT |
|
1684
66c5dadb4d61
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kvn
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1583
diff
changeset
|
8419 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?"); |
| 304 | 8420 if (CheckCompressedOops) { |
| 0 | 8421 Label ok; |
| 304 | 8422 testq(r, r); |
| 8423 jcc(Assembler::notEqual, ok); | |
| 8424 stop("null oop passed to encode_heap_oop_not_null"); | |
| 0 | 8425 bind(ok); |
| 304 | 8426 } |
| 8427 #endif | |
| 8428 verify_oop(r, "broken oop in encode_heap_oop_not_null"); | |
|
642
660978a2a31a
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624
diff
changeset
|
8429 if (Universe::narrow_oop_base() != NULL) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8430 subq(r, r12_heapbase); |
|
660978a2a31a
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624
diff
changeset
|
8431 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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diff
changeset
|
8432 if (Universe::narrow_oop_shift() != 0) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8433 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
8434 shrq(r, LogMinObjAlignmentInBytes); |
|
660978a2a31a
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changeset
|
8435 } |
| 304 | 8436 } |
| 8437 | |
| 8438 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) { | |
| 8439 #ifdef ASSERT | |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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parents:
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diff
changeset
|
8440 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?"); |
| 304 | 8441 if (CheckCompressedOops) { |
| 8442 Label ok; | |
| 8443 testq(src, src); | |
| 8444 jcc(Assembler::notEqual, ok); | |
| 8445 stop("null oop passed to encode_heap_oop_not_null2"); | |
| 8446 bind(ok); | |
| 0 | 8447 } |
| 8448 #endif | |
| 304 | 8449 verify_oop(src, "broken oop in encode_heap_oop_not_null2"); |
| 8450 if (dst != src) { | |
| 8451 movq(dst, src); | |
| 8452 } | |
|
642
660978a2a31a
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624
diff
changeset
|
8453 if (Universe::narrow_oop_base() != NULL) { |
|
660978a2a31a
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parents:
624
diff
changeset
|
8454 subq(dst, r12_heapbase); |
|
660978a2a31a
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diff
changeset
|
8455 } |
|
660978a2a31a
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diff
changeset
|
8456 if (Universe::narrow_oop_shift() != 0) { |
|
660978a2a31a
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kvn
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624
diff
changeset
|
8457 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
660978a2a31a
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kvn
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624
diff
changeset
|
8458 shrq(dst, LogMinObjAlignmentInBytes); |
|
660978a2a31a
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624
diff
changeset
|
8459 } |
| 304 | 8460 } |
| 8461 | |
| 8462 void MacroAssembler::decode_heap_oop(Register r) { | |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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1583
diff
changeset
|
8463 #ifdef ASSERT |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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parents:
1583
diff
changeset
|
8464 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?"); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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1583
diff
changeset
|
8465 #endif |
|
642
660978a2a31a
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624
diff
changeset
|
8466 if (Universe::narrow_oop_base() == NULL) { |
|
660978a2a31a
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parents:
624
diff
changeset
|
8467 if (Universe::narrow_oop_shift() != 0) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8468 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8469 shlq(r, LogMinObjAlignmentInBytes); |
|
660978a2a31a
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624
diff
changeset
|
8470 } |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
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parents:
1583
diff
changeset
|
8471 } else { |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8472 Label done; |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8473 shlq(r, LogMinObjAlignmentInBytes); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8474 jccb(Assembler::equal, done); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8475 addq(r, r12_heapbase); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8476 bind(done); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8477 } |
| 304 | 8478 verify_oop(r, "broken oop in decode_heap_oop"); |
| 8479 } | |
| 8480 | |
| 8481 void MacroAssembler::decode_heap_oop_not_null(Register r) { | |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8482 // Note: it will change flags |
| 304 | 8483 assert (UseCompressedOops, "should only be used for compressed headers"); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8484 assert (Universe::heap() != NULL, "java heap should be initialized"); |
| 304 | 8485 // Cannot assert, unverified entry point counts instructions (see .ad file) |
| 8486 // vtableStubs also counts instructions in pd_code_size_limit. | |
| 8487 // Also do not verify_oop as this is called by verify_oop. | |
|
898
60fea60a6db5
6864914: SPECjvm2008 produces invalid result with zero based Compressed Oops
kvn
parents:
845
diff
changeset
|
8488 if (Universe::narrow_oop_shift() != 0) { |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8489 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8490 shlq(r, LogMinObjAlignmentInBytes); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8491 if (Universe::narrow_oop_base() != NULL) { |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8492 addq(r, r12_heapbase); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8493 } |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8494 } else { |
|
898
60fea60a6db5
6864914: SPECjvm2008 produces invalid result with zero based Compressed Oops
kvn
parents:
845
diff
changeset
|
8495 assert (Universe::narrow_oop_base() == NULL, "sanity"); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8496 } |
| 304 | 8497 } |
| 8498 | |
| 8499 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) { | |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8500 // Note: it will change flags |
| 304 | 8501 assert (UseCompressedOops, "should only be used for compressed headers"); |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8502 assert (Universe::heap() != NULL, "java heap should be initialized"); |
| 304 | 8503 // Cannot assert, unverified entry point counts instructions (see .ad file) |
| 8504 // vtableStubs also counts instructions in pd_code_size_limit. | |
| 8505 // Also do not verify_oop as this is called by verify_oop. | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8506 if (Universe::narrow_oop_shift() != 0) { |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8507 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8508 if (LogMinObjAlignmentInBytes == Address::times_8) { |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8509 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0)); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8510 } else { |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8511 if (dst != src) { |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8512 movq(dst, src); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8513 } |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8514 shlq(dst, LogMinObjAlignmentInBytes); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8515 if (Universe::narrow_oop_base() != NULL) { |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8516 addq(dst, r12_heapbase); |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8517 } |
|
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8518 } |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8519 } else { |
|
898
60fea60a6db5
6864914: SPECjvm2008 produces invalid result with zero based Compressed Oops
kvn
parents:
845
diff
changeset
|
8520 assert (Universe::narrow_oop_base() == NULL, "sanity"); |
|
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8521 if (dst != src) { |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8522 movq(dst, src); |
|
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8523 } |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8524 } |
| 304 | 8525 } |
| 8526 | |
| 8527 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) { | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8528 assert (UseCompressedOops, "should only be used for compressed headers"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8529 assert (Universe::heap() != NULL, "java heap should be initialized"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8530 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8531 int oop_index = oop_recorder()->find_index(obj); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8532 RelocationHolder rspec = oop_Relocation::spec(oop_index); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8533 mov_narrow_oop(dst, oop_index, rspec); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8534 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8535 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8536 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8537 assert (UseCompressedOops, "should only be used for compressed headers"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8538 assert (Universe::heap() != NULL, "java heap should be initialized"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8539 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
| 304 | 8540 int oop_index = oop_recorder()->find_index(obj); |
| 8541 RelocationHolder rspec = oop_Relocation::spec(oop_index); | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8542 mov_narrow_oop(dst, oop_index, rspec); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8543 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8544 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8545 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8546 assert (UseCompressedOops, "should only be used for compressed headers"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8547 assert (Universe::heap() != NULL, "java heap should be initialized"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8548 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8549 int oop_index = oop_recorder()->find_index(obj); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8550 RelocationHolder rspec = oop_Relocation::spec(oop_index); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8551 Assembler::cmp_narrow_oop(dst, oop_index, rspec); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8552 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8553 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8554 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8555 assert (UseCompressedOops, "should only be used for compressed headers"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8556 assert (Universe::heap() != NULL, "java heap should be initialized"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8557 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8558 int oop_index = oop_recorder()->find_index(obj); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8559 RelocationHolder rspec = oop_Relocation::spec(oop_index); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8560 Assembler::cmp_narrow_oop(dst, oop_index, rspec); |
| 304 | 8561 } |
| 8562 | |
| 8563 void MacroAssembler::reinit_heapbase() { | |
| 8564 if (UseCompressedOops) { | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8565 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_oop_base_addr())); |
| 304 | 8566 } |
| 8567 } | |
| 8568 #endif // _LP64 | |
| 0 | 8569 |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8570 // IndexOf substring. |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8571 void MacroAssembler::string_indexof(Register str1, Register str2, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8572 Register cnt1, Register cnt2, Register result, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8573 XMMRegister vec, Register tmp) { |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8574 assert(UseSSE42Intrinsics, "SSE4.2 is required"); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8575 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8576 Label RELOAD_SUBSTR, PREP_FOR_SCAN, SCAN_TO_SUBSTR, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8577 SCAN_SUBSTR, RET_NOT_FOUND, CLEANUP; |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8578 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8579 push(str1); // string addr |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8580 push(str2); // substr addr |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8581 push(cnt2); // substr count |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8582 jmpb(PREP_FOR_SCAN); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8583 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8584 // Substr count saved at sp |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8585 // Substr saved at sp+1*wordSize |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8586 // String saved at sp+2*wordSize |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8587 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8588 // Reload substr for rescan |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8589 bind(RELOAD_SUBSTR); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8590 movl(cnt2, Address(rsp, 0)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8591 movptr(str2, Address(rsp, wordSize)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8592 // We came here after the beginninig of the substring was |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8593 // matched but the rest of it was not so we need to search |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8594 // again. Start from the next element after the previous match. |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8595 subptr(str1, result); // Restore counter |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8596 shrl(str1, 1); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8597 addl(cnt1, str1); |
|
1302
2484f4d6a54e
6935535: String.indexOf() returns incorrect result on x86 with SSE4.2
kvn
parents:
1108
diff
changeset
|
8598 decrementl(cnt1); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8599 lea(str1, Address(result, 2)); // Reload string |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8600 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8601 // Load substr |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8602 bind(PREP_FOR_SCAN); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8603 movdqu(vec, Address(str2, 0)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8604 addl(cnt1, 8); // prime the loop |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8605 subptr(str1, 16); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8606 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8607 // Scan string for substr in 16-byte vectors |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8608 bind(SCAN_TO_SUBSTR); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8609 subl(cnt1, 8); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8610 addptr(str1, 16); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8611 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8612 // pcmpestri |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8613 // inputs: |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8614 // xmm - substring |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8615 // rax - substring length (elements count) |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8616 // mem - scaned string |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8617 // rdx - string length (elements count) |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8618 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8619 // outputs: |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8620 // rcx - matched index in string |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8621 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8622 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8623 pcmpestri(vec, Address(str1, 0), 0x0d); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8624 jcc(Assembler::above, SCAN_TO_SUBSTR); // CF == 0 && ZF == 0 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8625 jccb(Assembler::aboveEqual, RET_NOT_FOUND); // CF == 0 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8626 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8627 // Fallthrough: found a potential substr |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8628 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8629 // Make sure string is still long enough |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8630 subl(cnt1, tmp); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8631 cmpl(cnt1, cnt2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8632 jccb(Assembler::negative, RET_NOT_FOUND); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8633 // Compute start addr of substr |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8634 lea(str1, Address(str1, tmp, Address::times_2)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8635 movptr(result, str1); // save |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8636 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8637 // Compare potential substr |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8638 addl(cnt1, 8); // prime the loop |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8639 addl(cnt2, 8); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8640 subptr(str1, 16); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8641 subptr(str2, 16); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8642 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8643 // Scan 16-byte vectors of string and substr |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8644 bind(SCAN_SUBSTR); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8645 subl(cnt1, 8); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8646 subl(cnt2, 8); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8647 addptr(str1, 16); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8648 addptr(str2, 16); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8649 movdqu(vec, Address(str2, 0)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8650 pcmpestri(vec, Address(str1, 0), 0x0d); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8651 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8652 jcc(Assembler::positive, SCAN_SUBSTR); // SF == 0 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8653 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8654 // Compute substr offset |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8655 subptr(result, Address(rsp, 2*wordSize)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8656 shrl(result, 1); // index |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8657 jmpb(CLEANUP); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8658 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8659 bind(RET_NOT_FOUND); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8660 movl(result, -1); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8661 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8662 bind(CLEANUP); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8663 addptr(rsp, 3*wordSize); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8664 } |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8665 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8666 // Compare strings. |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8667 void MacroAssembler::string_compare(Register str1, Register str2, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8668 Register cnt1, Register cnt2, Register result, |
| 2262 | 8669 XMMRegister vec1) { |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8670 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL; |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8671 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8672 // Compute the minimum of the string lengths and the |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8673 // difference of the string lengths (stack). |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8674 // Do the conditional move stuff |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8675 movl(result, cnt1); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8676 subl(cnt1, cnt2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8677 push(cnt1); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8678 if (VM_Version::supports_cmov()) { |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8679 cmovl(Assembler::lessEqual, cnt2, result); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8680 } else { |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8681 Label GT_LABEL; |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8682 jccb(Assembler::greater, GT_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8683 movl(cnt2, result); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8684 bind(GT_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8685 } |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8686 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8687 // Is the minimum length zero? |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8688 testl(cnt2, cnt2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8689 jcc(Assembler::zero, LENGTH_DIFF_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8690 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8691 // Load first characters |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8692 load_unsigned_short(result, Address(str1, 0)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8693 load_unsigned_short(cnt1, Address(str2, 0)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8694 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8695 // Compare first characters |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8696 subl(result, cnt1); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8697 jcc(Assembler::notZero, POP_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8698 decrementl(cnt2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8699 jcc(Assembler::zero, LENGTH_DIFF_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8700 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8701 { |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8702 // Check after comparing first character to see if strings are equivalent |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8703 Label LSkip2; |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8704 // Check if the strings start at same location |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8705 cmpptr(str1, str2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8706 jccb(Assembler::notEqual, LSkip2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8707 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8708 // Check if the length difference is zero (from stack) |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
8709 cmpl(Address(rsp, 0), 0x0); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
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|
8710 jcc(Assembler::equal, LENGTH_DIFF_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
8711 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8712 // Strings might not be equivalent |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
8713 bind(LSkip2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8714 } |
|
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6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
8715 |
| 2262 | 8716 Address::ScaleFactor scale = Address::times_2; |
| 8717 int stride = 8; | |
| 8718 | |
| 8719 // Advance to next element | |
| 8720 addptr(str1, 16/stride); | |
| 8721 addptr(str2, 16/stride); | |
|
986
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6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
8722 |
|
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6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
8723 if (UseSSE42Intrinsics) { |
| 2262 | 8724 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL; |
| 8725 int pcmpmask = 0x19; | |
|
986
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6827605: new String intrinsics may prevent EA scalar replacement
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diff
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|
8726 // Setup to compare 16-byte vectors |
| 2262 | 8727 movl(result, cnt2); |
| 8728 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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|
8729 jccb(Assembler::zero, COMPARE_TAIL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
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|
8730 |
| 2262 | 8731 lea(str1, Address(str1, result, scale)); |
| 8732 lea(str2, Address(str2, result, scale)); | |
| 8733 negptr(result); | |
| 8734 | |
| 8735 // pcmpestri | |
| 8736 // inputs: | |
| 8737 // vec1- substring | |
| 8738 // rax - negative string length (elements count) | |
| 8739 // mem - scaned string | |
| 8740 // rdx - string length (elements count) | |
| 8741 // pcmpmask - cmp mode: 11000 (string compare with negated result) | |
| 8742 // + 00 (unsigned bytes) or + 01 (unsigned shorts) | |
| 8743 // outputs: | |
| 8744 // rcx - first mismatched element index | |
| 8745 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri"); | |
| 8746 | |
| 8747 bind(COMPARE_WIDE_VECTORS); | |
| 8748 movdqu(vec1, Address(str1, result, scale)); | |
| 8749 pcmpestri(vec1, Address(str2, result, scale), pcmpmask); | |
| 8750 // After pcmpestri cnt1(rcx) contains mismatched element index | |
| 8751 | |
| 8752 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1 | |
| 8753 addptr(result, stride); | |
| 8754 subptr(cnt2, stride); | |
| 8755 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS); | |
| 8756 | |
| 8757 // compare wide vectors tail | |
| 8758 testl(result, result); | |
| 8759 jccb(Assembler::zero, LENGTH_DIFF_LABEL); | |
| 8760 | |
| 8761 movl(cnt2, stride); | |
| 8762 movl(result, stride); | |
| 8763 negptr(result); | |
| 8764 movdqu(vec1, Address(str1, result, scale)); | |
| 8765 pcmpestri(vec1, Address(str2, result, scale), pcmpmask); | |
| 8766 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL); | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
8767 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
8768 // Mismatched characters in the vectors |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
8769 bind(VECTOR_NOT_EQUAL); |
| 2262 | 8770 addptr(result, cnt1); |
| 8771 movptr(cnt2, result); | |
| 8772 load_unsigned_short(result, Address(str1, cnt2, scale)); | |
| 8773 load_unsigned_short(cnt1, Address(str2, cnt2, scale)); | |
| 8774 subl(result, cnt1); | |
| 8775 jmpb(POP_LABEL); | |
| 8776 | |
| 8777 bind(COMPARE_TAIL); // limit is zero | |
| 8778 movl(cnt2, result); | |
|
986
62001a362ce9
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diff
changeset
|
8779 // Fallthru to tail compare |
|
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6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8780 } |
|
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6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
8781 |
|
62001a362ce9
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parents:
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diff
changeset
|
8782 // Shift str2 and str1 to the end of the arrays, negate min |
| 2262 | 8783 lea(str1, Address(str1, cnt2, scale, 0)); |
| 8784 lea(str2, Address(str2, cnt2, scale, 0)); | |
|
986
62001a362ce9
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diff
changeset
|
8785 negptr(cnt2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
8786 |
| 2262 | 8787 // Compare the rest of the elements |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
8788 bind(WHILE_HEAD_LABEL); |
| 2262 | 8789 load_unsigned_short(result, Address(str1, cnt2, scale, 0)); |
| 8790 load_unsigned_short(cnt1, Address(str2, cnt2, scale, 0)); | |
|
986
62001a362ce9
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diff
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|
8791 subl(result, cnt1); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
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|
8792 jccb(Assembler::notZero, POP_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
8793 increment(cnt2); |
| 2262 | 8794 jccb(Assembler::notZero, WHILE_HEAD_LABEL); |
|
986
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parents:
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diff
changeset
|
8795 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
8796 // Strings are equal up to min length. Return the length difference. |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
8797 bind(LENGTH_DIFF_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
8798 pop(result); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
8799 jmpb(DONE_LABEL); |
|
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6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
8800 |
|
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6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
8801 // Discard the stored length difference |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
8802 bind(POP_LABEL); |
| 2262 | 8803 pop(cnt1); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
8804 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8805 // That's it |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
8806 bind(DONE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
8807 } |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8808 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8809 // Compare char[] arrays aligned to 4 bytes or substrings. |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
8810 void MacroAssembler::char_arrays_equals(bool is_array_equ, Register ary1, Register ary2, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8811 Register limit, Register result, Register chr, |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8812 XMMRegister vec1, XMMRegister vec2) { |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
8813 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR; |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
8814 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
8815 int length_offset = arrayOopDesc::length_offset_in_bytes(); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8816 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8817 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8818 // Check the input args |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8819 cmpptr(ary1, ary2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8820 jcc(Assembler::equal, TRUE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
8821 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8822 if (is_array_equ) { |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8823 // Need additional checks for arrays_equals. |
| 1016 | 8824 testptr(ary1, ary1); |
| 8825 jcc(Assembler::zero, FALSE_LABEL); | |
| 8826 testptr(ary2, ary2); | |
| 8827 jcc(Assembler::zero, FALSE_LABEL); | |
|
986
62001a362ce9
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parents:
898
diff
changeset
|
8828 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8829 // Check the lengths |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8830 movl(limit, Address(ary1, length_offset)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
8831 cmpl(limit, Address(ary2, length_offset)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
8832 jcc(Assembler::notEqual, FALSE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
8833 } |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8834 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8835 // count == 0 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8836 testl(limit, limit); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8837 jcc(Assembler::zero, TRUE_LABEL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
8838 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8839 if (is_array_equ) { |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8840 // Load array address |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8841 lea(ary1, Address(ary1, base_offset)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8842 lea(ary2, Address(ary2, base_offset)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
8843 } |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8844 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8845 shll(limit, 1); // byte count != 0 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8846 movl(result, limit); // copy |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8847 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8848 if (UseSSE42Intrinsics) { |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8849 // With SSE4.2, use double quad vector compare |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
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diff
changeset
|
8850 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; |
| 2262 | 8851 |
|
986
62001a362ce9
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diff
changeset
|
8852 // Compare 16-byte vectors |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8853 andl(result, 0x0000000e); // tail count (in bytes) |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
8854 andl(limit, 0xfffffff0); // vector count (in bytes) |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
8855 jccb(Assembler::zero, COMPARE_TAIL); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
8856 |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8857 lea(ary1, Address(ary1, limit, Address::times_1)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
8858 lea(ary2, Address(ary2, limit, Address::times_1)); |
|
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parents:
898
diff
changeset
|
8859 negptr(limit); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
898
diff
changeset
|
8860 |
|
62001a362ce9
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parents:
898
diff
changeset
|
8861 bind(COMPARE_WIDE_VECTORS); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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parents:
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diff
changeset
|
8862 movdqu(vec1, Address(ary1, limit, Address::times_1)); |
|
62001a362ce9
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diff
changeset
|
8863 movdqu(vec2, Address(ary2, limit, Address::times_1)); |
|
62001a362ce9
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diff
changeset
|
8864 pxor(vec1, vec2); |
| 2262 | 8865 |
|
986
62001a362ce9
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parents:
898
diff
changeset
|
8866 ptest(vec1, vec1); |
|
62001a362ce9
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parents:
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diff
changeset
|
8867 jccb(Assembler::notZero, FALSE_LABEL); |
|
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diff
changeset
|
8868 addptr(limit, 16); |
|
62001a362ce9
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diff
changeset
|
8869 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); |
|
62001a362ce9
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diff
changeset
|
8870 |
| 2262 | 8871 testl(result, result); |
| 8872 jccb(Assembler::zero, TRUE_LABEL); | |
| 8873 | |
| 8874 movdqu(vec1, Address(ary1, result, Address::times_1, -16)); | |
| 8875 movdqu(vec2, Address(ary2, result, Address::times_1, -16)); | |
| 8876 pxor(vec1, vec2); | |
| 8877 | |
| 8878 ptest(vec1, vec1); | |
| 8879 jccb(Assembler::notZero, FALSE_LABEL); | |
| 8880 jmpb(TRUE_LABEL); | |
| 8881 | |
|
986
62001a362ce9
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parents:
898
diff
changeset
|
8882 bind(COMPARE_TAIL); // limit is zero |
|
62001a362ce9
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parents:
898
diff
changeset
|
8883 movl(limit, result); |
|
62001a362ce9
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parents:
898
diff
changeset
|
8884 // Fallthru to tail compare |
|
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parents:
898
diff
changeset
|
8885 } |
|
62001a362ce9
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parents:
898
diff
changeset
|
8886 |
|
62001a362ce9
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parents:
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diff
changeset
|
8887 // Compare 4-byte vectors |
|
62001a362ce9
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parents:
898
diff
changeset
|
8888 andl(limit, 0xfffffffc); // vector count (in bytes) |
|
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diff
changeset
|
8889 jccb(Assembler::zero, COMPARE_CHAR); |
|
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diff
changeset
|
8890 |
|
62001a362ce9
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diff
changeset
|
8891 lea(ary1, Address(ary1, limit, Address::times_1)); |
|
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diff
changeset
|
8892 lea(ary2, Address(ary2, limit, Address::times_1)); |
|
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898
diff
changeset
|
8893 negptr(limit); |
|
62001a362ce9
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parents:
898
diff
changeset
|
8894 |
|
62001a362ce9
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diff
changeset
|
8895 bind(COMPARE_VECTORS); |
|
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diff
changeset
|
8896 movl(chr, Address(ary1, limit, Address::times_1)); |
|
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898
diff
changeset
|
8897 cmpl(chr, Address(ary2, limit, Address::times_1)); |
|
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8898 jccb(Assembler::notEqual, FALSE_LABEL); |
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8899 addptr(limit, 4); |
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8900 jcc(Assembler::notZero, COMPARE_VECTORS); |
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8901 |
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8902 // Compare trailing char (final 2 bytes), if any |
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8903 bind(COMPARE_CHAR); |
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8904 testl(result, 0x2); // tail char |
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8905 jccb(Assembler::zero, TRUE_LABEL); |
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8906 load_unsigned_short(chr, Address(ary1, 0)); |
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8907 load_unsigned_short(limit, Address(ary2, 0)); |
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8908 cmpl(chr, limit); |
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8909 jccb(Assembler::notEqual, FALSE_LABEL); |
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8910 |
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8911 bind(TRUE_LABEL); |
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8912 movl(result, 1); // return true |
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8913 jmpb(DONE); |
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8914 |
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8915 bind(FALSE_LABEL); |
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8916 xorl(result, result); // return false |
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8917 |
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8918 // That's it |
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8919 bind(DONE); |
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8920 } |
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8921 |
| 1763 | 8922 #ifdef PRODUCT |
| 8923 #define BLOCK_COMMENT(str) /* nothing */ | |
| 8924 #else | |
| 8925 #define BLOCK_COMMENT(str) block_comment(str) | |
| 8926 #endif | |
| 8927 | |
| 8928 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") | |
| 8929 void MacroAssembler::generate_fill(BasicType t, bool aligned, | |
| 8930 Register to, Register value, Register count, | |
| 8931 Register rtmp, XMMRegister xtmp) { | |
| 8932 assert_different_registers(to, value, count, rtmp); | |
| 8933 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte; | |
| 8934 Label L_fill_2_bytes, L_fill_4_bytes; | |
| 8935 | |
| 8936 int shift = -1; | |
| 8937 switch (t) { | |
| 8938 case T_BYTE: | |
| 8939 shift = 2; | |
| 8940 break; | |
| 8941 case T_SHORT: | |
| 8942 shift = 1; | |
| 8943 break; | |
| 8944 case T_INT: | |
| 8945 shift = 0; | |
| 8946 break; | |
| 8947 default: ShouldNotReachHere(); | |
| 8948 } | |
| 8949 | |
| 8950 if (t == T_BYTE) { | |
| 8951 andl(value, 0xff); | |
| 8952 movl(rtmp, value); | |
| 8953 shll(rtmp, 8); | |
| 8954 orl(value, rtmp); | |
| 8955 } | |
| 8956 if (t == T_SHORT) { | |
| 8957 andl(value, 0xffff); | |
| 8958 } | |
| 8959 if (t == T_BYTE || t == T_SHORT) { | |
| 8960 movl(rtmp, value); | |
| 8961 shll(rtmp, 16); | |
| 8962 orl(value, rtmp); | |
| 8963 } | |
| 8964 | |
| 8965 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element | |
| 8966 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp | |
| 8967 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) { | |
| 8968 // align source address at 4 bytes address boundary | |
| 8969 if (t == T_BYTE) { | |
| 8970 // One byte misalignment happens only for byte arrays | |
| 8971 testptr(to, 1); | |
| 8972 jccb(Assembler::zero, L_skip_align1); | |
| 8973 movb(Address(to, 0), value); | |
| 8974 increment(to); | |
| 8975 decrement(count); | |
| 8976 BIND(L_skip_align1); | |
| 8977 } | |
| 8978 // Two bytes misalignment happens only for byte and short (char) arrays | |
| 8979 testptr(to, 2); | |
| 8980 jccb(Assembler::zero, L_skip_align2); | |
| 8981 movw(Address(to, 0), value); | |
| 8982 addptr(to, 2); | |
| 8983 subl(count, 1<<(shift-1)); | |
| 8984 BIND(L_skip_align2); | |
| 8985 } | |
| 8986 if (UseSSE < 2) { | |
| 8987 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; | |
| 8988 // Fill 32-byte chunks | |
| 8989 subl(count, 8 << shift); | |
| 8990 jcc(Assembler::less, L_check_fill_8_bytes); | |
| 8991 align(16); | |
| 8992 | |
| 8993 BIND(L_fill_32_bytes_loop); | |
| 8994 | |
| 8995 for (int i = 0; i < 32; i += 4) { | |
| 8996 movl(Address(to, i), value); | |
| 8997 } | |
| 8998 | |
| 8999 addptr(to, 32); | |
| 9000 subl(count, 8 << shift); | |
| 9001 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); | |
| 9002 BIND(L_check_fill_8_bytes); | |
| 9003 addl(count, 8 << shift); | |
| 9004 jccb(Assembler::zero, L_exit); | |
| 9005 jmpb(L_fill_8_bytes); | |
| 9006 | |
| 9007 // | |
| 9008 // length is too short, just fill qwords | |
| 9009 // | |
| 9010 BIND(L_fill_8_bytes_loop); | |
| 9011 movl(Address(to, 0), value); | |
| 9012 movl(Address(to, 4), value); | |
| 9013 addptr(to, 8); | |
| 9014 BIND(L_fill_8_bytes); | |
| 9015 subl(count, 1 << (shift + 1)); | |
| 9016 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); | |
| 9017 // fall through to fill 4 bytes | |
| 9018 } else { | |
| 9019 Label L_fill_32_bytes; | |
| 9020 if (!UseUnalignedLoadStores) { | |
| 9021 // align to 8 bytes, we know we are 4 byte aligned to start | |
| 9022 testptr(to, 4); | |
| 9023 jccb(Assembler::zero, L_fill_32_bytes); | |
| 9024 movl(Address(to, 0), value); | |
| 9025 addptr(to, 4); | |
| 9026 subl(count, 1<<shift); | |
| 9027 } | |
| 9028 BIND(L_fill_32_bytes); | |
| 9029 { | |
| 9030 assert( UseSSE >= 2, "supported cpu only" ); | |
| 9031 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; | |
| 9032 // Fill 32-byte chunks | |
| 9033 movdl(xtmp, value); | |
| 9034 pshufd(xtmp, xtmp, 0); | |
| 9035 | |
| 9036 subl(count, 8 << shift); | |
| 9037 jcc(Assembler::less, L_check_fill_8_bytes); | |
| 9038 align(16); | |
| 9039 | |
| 9040 BIND(L_fill_32_bytes_loop); | |
| 9041 | |
| 9042 if (UseUnalignedLoadStores) { | |
| 9043 movdqu(Address(to, 0), xtmp); | |
| 9044 movdqu(Address(to, 16), xtmp); | |
| 9045 } else { | |
| 9046 movq(Address(to, 0), xtmp); | |
| 9047 movq(Address(to, 8), xtmp); | |
| 9048 movq(Address(to, 16), xtmp); | |
| 9049 movq(Address(to, 24), xtmp); | |
| 9050 } | |
| 9051 | |
| 9052 addptr(to, 32); | |
| 9053 subl(count, 8 << shift); | |
| 9054 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); | |
| 9055 BIND(L_check_fill_8_bytes); | |
| 9056 addl(count, 8 << shift); | |
| 9057 jccb(Assembler::zero, L_exit); | |
| 9058 jmpb(L_fill_8_bytes); | |
| 9059 | |
| 9060 // | |
| 9061 // length is too short, just fill qwords | |
| 9062 // | |
| 9063 BIND(L_fill_8_bytes_loop); | |
| 9064 movq(Address(to, 0), xtmp); | |
| 9065 addptr(to, 8); | |
| 9066 BIND(L_fill_8_bytes); | |
| 9067 subl(count, 1 << (shift + 1)); | |
| 9068 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); | |
| 9069 } | |
| 9070 } | |
| 9071 // fill trailing 4 bytes | |
| 9072 BIND(L_fill_4_bytes); | |
| 9073 testl(count, 1<<shift); | |
| 9074 jccb(Assembler::zero, L_fill_2_bytes); | |
| 9075 movl(Address(to, 0), value); | |
| 9076 if (t == T_BYTE || t == T_SHORT) { | |
| 9077 addptr(to, 4); | |
| 9078 BIND(L_fill_2_bytes); | |
| 9079 // fill trailing 2 bytes | |
| 9080 testl(count, 1<<(shift-1)); | |
| 9081 jccb(Assembler::zero, L_fill_byte); | |
| 9082 movw(Address(to, 0), value); | |
| 9083 if (t == T_BYTE) { | |
| 9084 addptr(to, 2); | |
| 9085 BIND(L_fill_byte); | |
| 9086 // fill trailing byte | |
| 9087 testl(count, 1); | |
| 9088 jccb(Assembler::zero, L_exit); | |
| 9089 movb(Address(to, 0), value); | |
| 9090 } else { | |
| 9091 BIND(L_fill_byte); | |
| 9092 } | |
| 9093 } else { | |
| 9094 BIND(L_fill_2_bytes); | |
| 9095 } | |
| 9096 BIND(L_exit); | |
| 9097 } | |
| 9098 #undef BIND | |
| 9099 #undef BLOCK_COMMENT | |
| 9100 | |
| 9101 | |
| 0 | 9102 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { |
| 9103 switch (cond) { | |
| 9104 // Note some conditions are synonyms for others | |
| 9105 case Assembler::zero: return Assembler::notZero; | |
| 9106 case Assembler::notZero: return Assembler::zero; | |
| 9107 case Assembler::less: return Assembler::greaterEqual; | |
| 9108 case Assembler::lessEqual: return Assembler::greater; | |
| 9109 case Assembler::greater: return Assembler::lessEqual; | |
| 9110 case Assembler::greaterEqual: return Assembler::less; | |
| 9111 case Assembler::below: return Assembler::aboveEqual; | |
| 9112 case Assembler::belowEqual: return Assembler::above; | |
| 9113 case Assembler::above: return Assembler::belowEqual; | |
| 9114 case Assembler::aboveEqual: return Assembler::below; | |
| 9115 case Assembler::overflow: return Assembler::noOverflow; | |
| 9116 case Assembler::noOverflow: return Assembler::overflow; | |
| 9117 case Assembler::negative: return Assembler::positive; | |
| 9118 case Assembler::positive: return Assembler::negative; | |
| 9119 case Assembler::parity: return Assembler::noParity; | |
| 9120 case Assembler::noParity: return Assembler::parity; | |
| 9121 } | |
| 9122 ShouldNotReachHere(); return Assembler::overflow; | |
| 9123 } | |
| 9124 | |
| 9125 SkipIfEqual::SkipIfEqual( | |
| 9126 MacroAssembler* masm, const bool* flag_addr, bool value) { | |
| 9127 _masm = masm; | |
| 9128 _masm->cmp8(ExternalAddress((address)flag_addr), value); | |
| 9129 _masm->jcc(Assembler::equal, _label); | |
| 9130 } | |
| 9131 | |
| 9132 SkipIfEqual::~SkipIfEqual() { | |
| 9133 _masm->bind(_label); | |
| 9134 } |