annotate src/share/vm/opto/coalesce.cpp @ 10111:8373c19be854

8011621: live_ranges_in_separate_class.patch Reviewed-by: kvn, roland Contributed-by: niclas.adlertz@oracle.com
author neliasso
date Tue, 16 Apr 2013 10:08:41 +0200
parents c7b60b601eb4
children 693e4d04fd09
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1 /*
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2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
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6 * under the terms of the GNU General Public License version 2 only, as
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
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16 * 2 along with this work; if not, write to the Free Software Foundation,
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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20 * or visit www.oracle.com if you need additional information or have any
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21 * questions.
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22 *
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23 */
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24
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25 #include "precompiled.hpp"
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26 #include "memory/allocation.inline.hpp"
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27 #include "opto/block.hpp"
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28 #include "opto/cfgnode.hpp"
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29 #include "opto/chaitin.hpp"
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30 #include "opto/coalesce.hpp"
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31 #include "opto/connode.hpp"
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32 #include "opto/indexSet.hpp"
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33 #include "opto/machnode.hpp"
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34 #include "opto/matcher.hpp"
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35 #include "opto/regmask.hpp"
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36
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37 //=============================================================================
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38 //------------------------------Dump-------------------------------------------
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39 #ifndef PRODUCT
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40 void PhaseCoalesce::dump(Node *n) const {
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41 // Being a const function means I cannot use 'Find'
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42 uint r = _phc._lrg_map.find(n);
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43 tty->print("L%d/N%d ",r,n->_idx);
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44 }
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45
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46 //------------------------------dump-------------------------------------------
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47 void PhaseCoalesce::dump() const {
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48 // I know I have a block layout now, so I can print blocks in a loop
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49 for( uint i=0; i<_phc._cfg._num_blocks; i++ ) {
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50 uint j;
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51 Block *b = _phc._cfg._blocks[i];
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52 // Print a nice block header
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53 tty->print("B%d: ",b->_pre_order);
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54 for( j=1; j<b->num_preds(); j++ )
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55 tty->print("B%d ", _phc._cfg._bbs[b->pred(j)->_idx]->_pre_order);
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56 tty->print("-> ");
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57 for( j=0; j<b->_num_succs; j++ )
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58 tty->print("B%d ",b->_succs[j]->_pre_order);
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59 tty->print(" IDom: B%d/#%d\n", b->_idom ? b->_idom->_pre_order : 0, b->_dom_depth);
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60 uint cnt = b->_nodes.size();
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61 for( j=0; j<cnt; j++ ) {
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62 Node *n = b->_nodes[j];
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63 dump( n );
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64 tty->print("\t%s\t",n->Name());
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65
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66 // Dump the inputs
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67 uint k; // Exit value of loop
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68 for( k=0; k<n->req(); k++ ) // For all required inputs
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69 if( n->in(k) ) dump( n->in(k) );
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70 else tty->print("_ ");
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71 int any_prec = 0;
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72 for( ; k<n->len(); k++ ) // For all precedence inputs
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73 if( n->in(k) ) {
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74 if( !any_prec++ ) tty->print(" |");
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75 dump( n->in(k) );
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76 }
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77
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78 // Dump node-specific info
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79 n->dump_spec(tty);
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80 tty->print("\n");
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81
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82 }
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83 tty->print("\n");
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84 }
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85 }
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86 #endif
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87
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88 //------------------------------combine_these_two------------------------------
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89 // Combine the live ranges def'd by these 2 Nodes. N2 is an input to N1.
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90 void PhaseCoalesce::combine_these_two(Node *n1, Node *n2) {
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91 uint lr1 = _phc._lrg_map.find(n1);
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92 uint lr2 = _phc._lrg_map.find(n2);
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93 if( lr1 != lr2 && // Different live ranges already AND
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94 !_phc._ifg->test_edge_sq( lr1, lr2 ) ) { // Do not interfere
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95 LRG *lrg1 = &_phc.lrgs(lr1);
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96 LRG *lrg2 = &_phc.lrgs(lr2);
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97 // Not an oop->int cast; oop->oop, int->int, AND int->oop are OK.
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98
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99 // Now, why is int->oop OK? We end up declaring a raw-pointer as an oop
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100 // and in general that's a bad thing. However, int->oop conversions only
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101 // happen at GC points, so the lifetime of the misclassified raw-pointer
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102 // is from the CheckCastPP (that converts it to an oop) backwards up
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103 // through a merge point and into the slow-path call, and around the
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104 // diamond up to the heap-top check and back down into the slow-path call.
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105 // The misclassified raw pointer is NOT live across the slow-path call,
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106 // and so does not appear in any GC info, so the fact that it is
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107 // misclassified is OK.
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108
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109 if( (lrg1->_is_oop || !lrg2->_is_oop) && // not an oop->int cast AND
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110 // Compatible final mask
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111 lrg1->mask().overlap( lrg2->mask() ) ) {
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112 // Merge larger into smaller.
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113 if( lr1 > lr2 ) {
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114 uint tmp = lr1; lr1 = lr2; lr2 = tmp;
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115 Node *n = n1; n1 = n2; n2 = n;
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116 LRG *ltmp = lrg1; lrg1 = lrg2; lrg2 = ltmp;
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117 }
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118 // Union lr2 into lr1
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119 _phc.Union( n1, n2 );
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120 if (lrg1->_maxfreq < lrg2->_maxfreq)
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121 lrg1->_maxfreq = lrg2->_maxfreq;
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122 // Merge in the IFG
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123 _phc._ifg->Union( lr1, lr2 );
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124 // Combine register restrictions
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125 lrg1->AND(lrg2->mask());
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126 }
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127 }
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128 }
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129
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130 //------------------------------coalesce_driver--------------------------------
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131 // Copy coalescing
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132 void PhaseCoalesce::coalesce_driver( ) {
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133
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134 verify();
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135 // Coalesce from high frequency to low
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136 for( uint i=0; i<_phc._cfg._num_blocks; i++ )
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137 coalesce( _phc._blks[i] );
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138
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139 }
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140
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141 //------------------------------insert_copy_with_overlap-----------------------
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142 // I am inserting copies to come out of SSA form. In the general case, I am
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143 // doing a parallel renaming. I'm in the Named world now, so I can't do a
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144 // general parallel renaming. All the copies now use "names" (live-ranges)
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145 // to carry values instead of the explicit use-def chains. Suppose I need to
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146 // insert 2 copies into the same block. They copy L161->L128 and L128->L132.
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147 // If I insert them in the wrong order then L128 will get clobbered before it
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148 // can get used by the second copy. This cannot happen in the SSA model;
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149 // direct use-def chains get me the right value. It DOES happen in the named
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150 // model so I have to handle the reordering of copies.
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151 //
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152 // In general, I need to topo-sort the placed copies to avoid conflicts.
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153 // Its possible to have a closed cycle of copies (e.g., recirculating the same
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154 // values around a loop). In this case I need a temp to break the cycle.
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155 void PhaseAggressiveCoalesce::insert_copy_with_overlap( Block *b, Node *copy, uint dst_name, uint src_name ) {
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156
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157 // Scan backwards for the locations of the last use of the dst_name.
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158 // I am about to clobber the dst_name, so the copy must be inserted
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159 // after the last use. Last use is really first-use on a backwards scan.
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160 uint i = b->end_idx()-1;
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161 while(1) {
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162 Node *n = b->_nodes[i];
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163 // Check for end of virtual copies; this is also the end of the
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164 // parallel renaming effort.
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165 if (n->_idx < _unique) {
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166 break;
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167 }
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168 uint idx = n->is_Copy();
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169 assert( idx || n->is_Con() || n->is_MachProj(), "Only copies during parallel renaming" );
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170 if (idx && _phc._lrg_map.find(n->in(idx)) == dst_name) {
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171 break;
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172 }
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173 i--;
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174 }
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175 uint last_use_idx = i;
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176
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177 // Also search for any kill of src_name that exits the block.
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178 // Since the copy uses src_name, I have to come before any kill.
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179 uint kill_src_idx = b->end_idx();
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180 // There can be only 1 kill that exits any block and that is
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181 // the last kill. Thus it is the first kill on a backwards scan.
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182 i = b->end_idx()-1;
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183 while (1) {
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184 Node *n = b->_nodes[i];
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185 // Check for end of virtual copies; this is also the end of the
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186 // parallel renaming effort.
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187 if (n->_idx < _unique) {
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188 break;
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189 }
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190 assert( n->is_Copy() || n->is_Con() || n->is_MachProj(), "Only copies during parallel renaming" );
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191 if (_phc._lrg_map.find(n) == src_name) {
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192 kill_src_idx = i;
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193 break;
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194 }
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195 i--;
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196 }
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197 // Need a temp? Last use of dst comes after the kill of src?
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198 if (last_use_idx >= kill_src_idx) {
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199 // Need to break a cycle with a temp
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200 uint idx = copy->is_Copy();
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201 Node *tmp = copy->clone();
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202 uint max_lrg_id = _phc._lrg_map.max_lrg_id();
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203 _phc.new_lrg(tmp, max_lrg_id);
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diff changeset
204 _phc._lrg_map.set_max_lrg_id(max_lrg_id + 1);
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205
0
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206 // Insert new temp between copy and source
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207 tmp ->set_req(idx,copy->in(idx));
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208 copy->set_req(idx,tmp);
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209 // Save source in temp early, before source is killed
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210 b->_nodes.insert(kill_src_idx,tmp);
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211 _phc._cfg._bbs.map( tmp->_idx, b );
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212 last_use_idx++;
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213 }
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214
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215 // Insert just after last use
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216 b->_nodes.insert(last_use_idx+1,copy);
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217 }
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218
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219 //------------------------------insert_copies----------------------------------
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220 void PhaseAggressiveCoalesce::insert_copies( Matcher &matcher ) {
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221 // We do LRGs compressing and fix a liveout data only here since the other
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222 // place in Split() is guarded by the assert which we never hit.
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223 _phc._lrg_map.compress_uf_map_for_nodes();
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224 // Fix block's liveout data for compressed live ranges.
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225 for (uint lrg = 1; lrg < _phc._lrg_map.max_lrg_id(); lrg++) {
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226 uint compressed_lrg = _phc._lrg_map.find(lrg);
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227 if (lrg != compressed_lrg) {
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228 for (uint bidx = 0; bidx < _phc._cfg._num_blocks; bidx++) {
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229 IndexSet *liveout = _phc._live->live(_phc._cfg._blocks[bidx]);
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230 if (liveout->member(lrg)) {
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231 liveout->remove(lrg);
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232 liveout->insert(compressed_lrg);
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233 }
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234 }
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235 }
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236 }
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237
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238 // All new nodes added are actual copies to replace virtual copies.
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239 // Nodes with index less than '_unique' are original, non-virtual Nodes.
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240 _unique = C->unique();
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241
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242 for( uint i=0; i<_phc._cfg._num_blocks; i++ ) {
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243 Block *b = _phc._cfg._blocks[i];
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244 uint cnt = b->num_preds(); // Number of inputs to the Phi
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245
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246 for( uint l = 1; l<b->_nodes.size(); l++ ) {
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247 Node *n = b->_nodes[l];
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248
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249 // Do not use removed-copies, use copied value instead
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250 uint ncnt = n->req();
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251 for( uint k = 1; k<ncnt; k++ ) {
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252 Node *copy = n->in(k);
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253 uint cidx = copy->is_Copy();
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254 if( cidx ) {
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255 Node *def = copy->in(cidx);
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256 if (_phc._lrg_map.find(copy) == _phc._lrg_map.find(def)) {
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257 n->set_req(k, def);
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258 }
0
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259 }
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260 }
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261
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262 // Remove any explicit copies that get coalesced.
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263 uint cidx = n->is_Copy();
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264 if( cidx ) {
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265 Node *def = n->in(cidx);
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266 if (_phc._lrg_map.find(n) == _phc._lrg_map.find(def)) {
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267 n->replace_by(def);
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268 n->set_req(cidx,NULL);
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269 b->_nodes.remove(l);
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270 l--;
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271 continue;
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272 }
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273 }
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274
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275 if (n->is_Phi()) {
0
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276 // Get the chosen name for the Phi
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277 uint phi_name = _phc._lrg_map.find(n);
0
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278 // Ignore the pre-allocated specials
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279 if (!phi_name) {
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280 continue;
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281 }
0
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282 // Check for mismatch inputs to Phi
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283 for (uint j = 1; j < cnt; j++) {
0
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284 Node *m = n->in(j);
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285 uint src_name = _phc._lrg_map.find(m);
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286 if (src_name != phi_name) {
0
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287 Block *pred = _phc._cfg._bbs[b->pred(j)->_idx];
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288 Node *copy;
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289 assert(!m->is_Con() || m->is_Mach(), "all Con must be Mach");
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290 // Rematerialize constants instead of copying them
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291 if( m->is_Mach() && m->as_Mach()->is_Con() &&
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292 m->as_Mach()->rematerialize() ) {
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293 copy = m->clone();
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294 // Insert the copy in the predecessor basic block
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295 pred->add_inst(copy);
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296 // Copy any flags as well
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297 _phc.clone_projs(pred, pred->end_idx(), m, copy, _phc._lrg_map);
0
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298 } else {
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299 const RegMask *rm = C->matcher()->idealreg2spillmask[m->ideal_reg()];
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300 copy = new (C) MachSpillCopyNode(m, *rm, *rm);
0
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301 // Find a good place to insert. Kinda tricky, use a subroutine
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302 insert_copy_with_overlap(pred,copy,phi_name,src_name);
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diff changeset
303 }
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304 // Insert the copy in the use-def chain
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diff changeset
305 n->set_req(j, copy);
0
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306 _phc._cfg._bbs.map( copy->_idx, pred );
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307 // Extend ("register allocate") the names array for the copy.
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diff changeset
308 _phc._lrg_map.extend(copy->_idx, phi_name);
0
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309 } // End of if Phi names do not match
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310 } // End of for all inputs to Phi
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311 } else { // End of if Phi
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312
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313 // Now check for 2-address instructions
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314 uint idx;
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315 if( n->is_Mach() && (idx=n->as_Mach()->two_adr()) ) {
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316 // Get the chosen name for the Node
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8373c19be854 8011621: live_ranges_in_separate_class.patch
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diff changeset
317 uint name = _phc._lrg_map.find(n);
8373c19be854 8011621: live_ranges_in_separate_class.patch
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diff changeset
318 assert (name, "no 2-address specials");
0
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319 // Check for name mis-match on the 2-address input
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diff changeset
320 Node *m = n->in(idx);
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8373c19be854 8011621: live_ranges_in_separate_class.patch
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diff changeset
321 if (_phc._lrg_map.find(m) != name) {
0
a61af66fc99e Initial load
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diff changeset
322 Node *copy;
a61af66fc99e Initial load
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parents:
diff changeset
323 assert(!m->is_Con() || m->is_Mach(), "all Con must be Mach");
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diff changeset
324 // At this point it is unsafe to extend live ranges (6550579).
a61af66fc99e Initial load
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diff changeset
325 // Rematerialize only constants as we do for Phi above.
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8373c19be854 8011621: live_ranges_in_separate_class.patch
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diff changeset
326 if(m->is_Mach() && m->as_Mach()->is_Con() &&
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
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diff changeset
327 m->as_Mach()->rematerialize()) {
0
a61af66fc99e Initial load
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diff changeset
328 copy = m->clone();
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diff changeset
329 // Insert the copy in the basic block, just before us
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diff changeset
330 b->_nodes.insert(l++, copy);
8373c19be854 8011621: live_ranges_in_separate_class.patch
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diff changeset
331 if(_phc.clone_projs(b, l, m, copy, _phc._lrg_map)) {
0
a61af66fc99e Initial load
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diff changeset
332 l++;
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8373c19be854 8011621: live_ranges_in_separate_class.patch
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diff changeset
333 }
0
a61af66fc99e Initial load
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diff changeset
334 } else {
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335 const RegMask *rm = C->matcher()->idealreg2spillmask[m->ideal_reg()];
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8373c19be854 8011621: live_ranges_in_separate_class.patch
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diff changeset
336 copy = new (C) MachSpillCopyNode(m, *rm, *rm);
0
a61af66fc99e Initial load
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diff changeset
337 // Insert the copy in the basic block, just before us
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diff changeset
338 b->_nodes.insert(l++, copy);
0
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339 }
a61af66fc99e Initial load
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diff changeset
340 // Insert the copy in the use-def chain
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8373c19be854 8011621: live_ranges_in_separate_class.patch
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diff changeset
341 n->set_req(idx, copy);
0
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342 // Extend ("register allocate") the names array for the copy.
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8373c19be854 8011621: live_ranges_in_separate_class.patch
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diff changeset
343 _phc._lrg_map.extend(copy->_idx, name);
0
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diff changeset
344 _phc._cfg._bbs.map( copy->_idx, b );
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diff changeset
345 }
a61af66fc99e Initial load
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parents:
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346
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347 } // End of is two-adr
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diff changeset
348
a61af66fc99e Initial load
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diff changeset
349 // Insert a copy at a debug use for a lrg which has high frequency
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
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diff changeset
350 if (b->_freq < OPTO_DEBUG_SPLIT_FREQ || b->is_uncommon(_phc._cfg._bbs)) {
0
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parents:
diff changeset
351 // Walk the debug inputs to the node and check for lrg freq
a61af66fc99e Initial load
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parents:
diff changeset
352 JVMState* jvms = n->jvms();
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diff changeset
353 uint debug_start = jvms ? jvms->debug_start() : 999999;
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diff changeset
354 uint debug_end = jvms ? jvms->debug_end() : 999999;
a61af66fc99e Initial load
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diff changeset
355 for(uint inpidx = debug_start; inpidx < debug_end; inpidx++) {
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parents:
diff changeset
356 // Do not split monitors; they are only needed for debug table
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parents:
diff changeset
357 // entries and need no code.
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parents: 3842
diff changeset
358 if (jvms->is_monitor_use(inpidx)) {
8373c19be854 8011621: live_ranges_in_separate_class.patch
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parents: 3842
diff changeset
359 continue;
8373c19be854 8011621: live_ranges_in_separate_class.patch
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parents: 3842
diff changeset
360 }
0
a61af66fc99e Initial load
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parents:
diff changeset
361 Node *inp = n->in(inpidx);
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
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parents: 3842
diff changeset
362 uint nidx = _phc._lrg_map.live_range_id(inp);
0
a61af66fc99e Initial load
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parents:
diff changeset
363 LRG &lrg = lrgs(nidx);
a61af66fc99e Initial load
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parents:
diff changeset
364
a61af66fc99e Initial load
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parents:
diff changeset
365 // If this lrg has a high frequency use/def
673
fbc12e71c476 6810845: Performance regression in mpegaudio on x64
kvn
parents: 605
diff changeset
366 if( lrg._maxfreq >= _phc.high_frequency_lrg() ) {
0
a61af66fc99e Initial load
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parents:
diff changeset
367 // If the live range is also live out of this block (like it
a61af66fc99e Initial load
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parents:
diff changeset
368 // would be for a fast/slow idiom), the normal spill mechanism
a61af66fc99e Initial load
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parents:
diff changeset
369 // does an excellent job. If it is not live out of this block
a61af66fc99e Initial load
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parents:
diff changeset
370 // (like it would be for debug info to uncommon trap) splitting
a61af66fc99e Initial load
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parents:
diff changeset
371 // the live range now allows a better allocation in the high
a61af66fc99e Initial load
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parents:
diff changeset
372 // frequency blocks.
a61af66fc99e Initial load
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parents:
diff changeset
373 // Build_IFG_virtual has converted the live sets to
a61af66fc99e Initial load
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parents:
diff changeset
374 // live-IN info, not live-OUT info.
a61af66fc99e Initial load
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parents:
diff changeset
375 uint k;
a61af66fc99e Initial load
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parents:
diff changeset
376 for( k=0; k < b->_num_succs; k++ )
a61af66fc99e Initial load
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parents:
diff changeset
377 if( _phc._live->live(b->_succs[k])->member( nidx ) )
a61af66fc99e Initial load
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parents:
diff changeset
378 break; // Live in to some successor block?
a61af66fc99e Initial load
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parents:
diff changeset
379 if( k < b->_num_succs )
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parents:
diff changeset
380 continue; // Live out; do not pre-split
a61af66fc99e Initial load
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parents:
diff changeset
381 // Split the lrg at this use
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parents:
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382 const RegMask *rm = C->matcher()->idealreg2spillmask[inp->ideal_reg()];
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383 Node *copy = new (C) MachSpillCopyNode( inp, *rm, *rm );
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384 // Insert the copy in the use-def chain
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385 n->set_req(inpidx, copy );
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386 // Insert the copy in the basic block, just before us
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387 b->_nodes.insert( l++, copy );
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388 // Extend ("register allocate") the names array for the copy.
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389 uint max_lrg_id = _phc._lrg_map.max_lrg_id();
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390 _phc.new_lrg(copy, max_lrg_id);
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391 _phc._lrg_map.set_max_lrg_id(max_lrg_id + 1);
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392 _phc._cfg._bbs.map(copy->_idx, b);
0
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393 //tty->print_cr("Split a debug use in Aggressive Coalesce");
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394 } // End of if high frequency use/def
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395 } // End of for all debug inputs
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396 } // End of if low frequency safepoint
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397
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398 } // End of if Phi
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399
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400 } // End of for all instructions
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401 } // End of for all blocks
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402 }
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403
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404 //=============================================================================
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405 //------------------------------coalesce---------------------------------------
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406 // Aggressive (but pessimistic) copy coalescing of a single block
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407
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408 // The following coalesce pass represents a single round of aggressive
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409 // pessimistic coalesce. "Aggressive" means no attempt to preserve
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410 // colorability when coalescing. This occasionally means more spills, but
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411 // it also means fewer rounds of coalescing for better code - and that means
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412 // faster compiles.
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413
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414 // "Pessimistic" means we do not hit the fixed point in one pass (and we are
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415 // reaching for the least fixed point to boot). This is typically solved
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416 // with a few more rounds of coalescing, but the compiler must run fast. We
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417 // could optimistically coalescing everything touching PhiNodes together
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418 // into one big live range, then check for self-interference. Everywhere
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419 // the live range interferes with self it would have to be split. Finding
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420 // the right split points can be done with some heuristics (based on
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421 // expected frequency of edges in the live range). In short, it's a real
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422 // research problem and the timeline is too short to allow such research.
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423 // Further thoughts: (1) build the LR in a pass, (2) find self-interference
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424 // in another pass, (3) per each self-conflict, split, (4) split by finding
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425 // the low-cost cut (min-cut) of the LR, (5) edges in the LR are weighted
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426 // according to the GCM algorithm (or just exec freq on CFG edges).
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427
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428 void PhaseAggressiveCoalesce::coalesce( Block *b ) {
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429 // Copies are still "virtual" - meaning we have not made them explicitly
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430 // copies. Instead, Phi functions of successor blocks have mis-matched
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431 // live-ranges. If I fail to coalesce, I'll have to insert a copy to line
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432 // up the live-ranges. Check for Phis in successor blocks.
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433 uint i;
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434 for( i=0; i<b->_num_succs; i++ ) {
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435 Block *bs = b->_succs[i];
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parents:
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436 // Find index of 'b' in 'bs' predecessors
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437 uint j=1;
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438 while( _phc._cfg._bbs[bs->pred(j)->_idx] != b ) j++;
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439 // Visit all the Phis in successor block
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440 for( uint k = 1; k<bs->_nodes.size(); k++ ) {
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441 Node *n = bs->_nodes[k];
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442 if( !n->is_Phi() ) break;
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443 combine_these_two( n, n->in(j) );
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444 }
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445 } // End of for all successor blocks
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446
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447
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448 // Check _this_ block for 2-address instructions and copies.
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449 uint cnt = b->end_idx();
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450 for( i = 1; i<cnt; i++ ) {
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451 Node *n = b->_nodes[i];
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452 uint idx;
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453 // 2-address instructions have a virtual Copy matching their input
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454 // to their output
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diff changeset
455 if (n->is_Mach() && (idx = n->as_Mach()->two_adr())) {
0
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456 MachNode *mach = n->as_Mach();
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457 combine_these_two(mach, mach->in(idx));
0
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458 }
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459 } // End of for all instructions in block
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460 }
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461
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462 //=============================================================================
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463 //------------------------------PhaseConservativeCoalesce----------------------
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464 PhaseConservativeCoalesce::PhaseConservativeCoalesce(PhaseChaitin &chaitin) : PhaseCoalesce(chaitin) {
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diff changeset
465 _ulr.initialize(_phc._lrg_map.max_lrg_id());
0
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466 }
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467
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468 //------------------------------verify-----------------------------------------
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469 void PhaseConservativeCoalesce::verify() {
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470 #ifdef ASSERT
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471 _phc.set_was_low();
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472 #endif
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473 }
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474
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475 //------------------------------union_helper-----------------------------------
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476 void PhaseConservativeCoalesce::union_helper( Node *lr1_node, Node *lr2_node, uint lr1, uint lr2, Node *src_def, Node *dst_copy, Node *src_copy, Block *b, uint bindex ) {
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477 // Join live ranges. Merge larger into smaller. Union lr2 into lr1 in the
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478 // union-find tree
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479 _phc.Union( lr1_node, lr2_node );
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480
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diff changeset
481 // Single-def live range ONLY if both live ranges are single-def.
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482 // If both are single def, then src_def powers one live range
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483 // and def_copy powers the other. After merging, src_def powers
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484 // the combined live range.
295
ea18057223c4 6732194: Data corruption dependent on -server/-client/-Xbatch
never
parents: 0
diff changeset
485 lrgs(lr1)._def = (lrgs(lr1).is_multidef() ||
ea18057223c4 6732194: Data corruption dependent on -server/-client/-Xbatch
never
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diff changeset
486 lrgs(lr2).is_multidef() )
0
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parents:
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487 ? NodeSentinel : src_def;
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488 lrgs(lr2)._def = NULL; // No def for lrg 2
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489 lrgs(lr2).Clear(); // Force empty mask for LRG 2
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490 //lrgs(lr2)._size = 0; // Live-range 2 goes dead
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491 lrgs(lr1)._is_oop |= lrgs(lr2)._is_oop;
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492 lrgs(lr2)._is_oop = 0; // In particular, not an oop for GC info
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493
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494 if (lrgs(lr1)._maxfreq < lrgs(lr2)._maxfreq)
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parents:
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495 lrgs(lr1)._maxfreq = lrgs(lr2)._maxfreq;
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496
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497 // Copy original value instead. Intermediate copies go dead, and
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498 // the dst_copy becomes useless.
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diff changeset
499 int didx = dst_copy->is_Copy();
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diff changeset
500 dst_copy->set_req( didx, src_def );
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diff changeset
501 // Add copy to free list
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parents:
diff changeset
502 // _phc.free_spillcopy(b->_nodes[bindex]);
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503 assert( b->_nodes[bindex] == dst_copy, "" );
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504 dst_copy->replace_by( dst_copy->in(didx) );
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505 dst_copy->set_req( didx, NULL);
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parents:
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506 b->_nodes.remove(bindex);
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507 if( bindex < b->_ihrp_index ) b->_ihrp_index--;
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diff changeset
508 if( bindex < b->_fhrp_index ) b->_fhrp_index--;
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509
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diff changeset
510 // Stretched lr1; add it to liveness of intermediate blocks
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diff changeset
511 Block *b2 = _phc._cfg._bbs[src_copy->_idx];
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512 while( b != b2 ) {
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parents:
diff changeset
513 b = _phc._cfg._bbs[b->pred(1)->_idx];
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parents:
diff changeset
514 _phc._live->live(b)->insert(lr1);
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515 }
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diff changeset
516 }
a61af66fc99e Initial load
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517
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diff changeset
518 //------------------------------compute_separating_interferences---------------
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519 // Factored code from copy_copy that computes extra interferences from
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parents:
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520 // lengthening a live range by double-coalescing.
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diff changeset
521 uint PhaseConservativeCoalesce::compute_separating_interferences(Node *dst_copy, Node *src_copy, Block *b, uint bindex, RegMask &rm, uint reg_degree, uint rm_size, uint lr1, uint lr2 ) {
a61af66fc99e Initial load
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522
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diff changeset
523 assert(!lrgs(lr1)._fat_proj, "cannot coalesce fat_proj");
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parents:
diff changeset
524 assert(!lrgs(lr2)._fat_proj, "cannot coalesce fat_proj");
a61af66fc99e Initial load
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525 Node *prev_copy = dst_copy->in(dst_copy->is_Copy());
a61af66fc99e Initial load
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parents:
diff changeset
526 Block *b2 = b;
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parents:
diff changeset
527 uint bindex2 = bindex;
a61af66fc99e Initial load
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528 while( 1 ) {
a61af66fc99e Initial load
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parents:
diff changeset
529 // Find previous instruction
a61af66fc99e Initial load
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parents:
diff changeset
530 bindex2--; // Chain backwards 1 instruction
a61af66fc99e Initial load
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parents:
diff changeset
531 while( bindex2 == 0 ) { // At block start, find prior block
a61af66fc99e Initial load
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parents:
diff changeset
532 assert( b2->num_preds() == 2, "cannot double coalesce across c-flow" );
a61af66fc99e Initial load
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parents:
diff changeset
533 b2 = _phc._cfg._bbs[b2->pred(1)->_idx];
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534 bindex2 = b2->end_idx()-1;
a61af66fc99e Initial load
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parents:
diff changeset
535 }
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parents:
diff changeset
536 // Get prior instruction
a61af66fc99e Initial load
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parents:
diff changeset
537 assert(bindex2 < b2->_nodes.size(), "index out of bounds");
a61af66fc99e Initial load
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parents:
diff changeset
538 Node *x = b2->_nodes[bindex2];
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parents:
diff changeset
539 if( x == prev_copy ) { // Previous copy in copy chain?
a61af66fc99e Initial load
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parents:
diff changeset
540 if( prev_copy == src_copy)// Found end of chain and all interferences
a61af66fc99e Initial load
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parents:
diff changeset
541 break; // So break out of loop
a61af66fc99e Initial load
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parents:
diff changeset
542 // Else work back one in copy chain
a61af66fc99e Initial load
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parents:
diff changeset
543 prev_copy = prev_copy->in(prev_copy->is_Copy());
a61af66fc99e Initial load
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parents:
diff changeset
544 } else { // Else collect interferences
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8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
545 uint lidx = _phc._lrg_map.find(x);
0
a61af66fc99e Initial load
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parents:
diff changeset
546 // Found another def of live-range being stretched?
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
547 if(lidx == lr1) {
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
548 return max_juint;
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
549 }
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
550 if(lidx == lr2) {
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
551 return max_juint;
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
552 }
0
a61af66fc99e Initial load
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parents:
diff changeset
553
a61af66fc99e Initial load
duke
parents:
diff changeset
554 // If we attempt to coalesce across a bound def
a61af66fc99e Initial load
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parents:
diff changeset
555 if( lrgs(lidx).is_bound() ) {
a61af66fc99e Initial load
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parents:
diff changeset
556 // Do not let the coalesced LRG expect to get the bound color
a61af66fc99e Initial load
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parents:
diff changeset
557 rm.SUBTRACT( lrgs(lidx).mask() );
a61af66fc99e Initial load
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parents:
diff changeset
558 // Recompute rm_size
a61af66fc99e Initial load
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parents:
diff changeset
559 rm_size = rm.Size();
a61af66fc99e Initial load
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parents:
diff changeset
560 //if( rm._flags ) rm_size += 1000000;
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parents:
diff changeset
561 if( reg_degree >= rm_size ) return max_juint;
a61af66fc99e Initial load
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parents:
diff changeset
562 }
a61af66fc99e Initial load
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parents:
diff changeset
563 if( rm.overlap(lrgs(lidx).mask()) ) {
a61af66fc99e Initial load
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parents:
diff changeset
564 // Insert lidx into union LRG; returns TRUE if actually inserted
a61af66fc99e Initial load
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parents:
diff changeset
565 if( _ulr.insert(lidx) ) {
a61af66fc99e Initial load
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parents:
diff changeset
566 // Infinite-stack neighbors do not alter colorability, as they
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parents:
diff changeset
567 // can always color to some other color.
a61af66fc99e Initial load
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parents:
diff changeset
568 if( !lrgs(lidx).mask().is_AllStack() ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
569 // If this coalesce will make any new neighbor uncolorable,
a61af66fc99e Initial load
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parents:
diff changeset
570 // do not coalesce.
a61af66fc99e Initial load
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parents:
diff changeset
571 if( lrgs(lidx).just_lo_degree() )
a61af66fc99e Initial load
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parents:
diff changeset
572 return max_juint;
a61af66fc99e Initial load
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parents:
diff changeset
573 // Bump our degree
a61af66fc99e Initial load
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parents:
diff changeset
574 if( ++reg_degree >= rm_size )
a61af66fc99e Initial load
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parents:
diff changeset
575 return max_juint;
a61af66fc99e Initial load
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parents:
diff changeset
576 } // End of if not infinite-stack neighbor
a61af66fc99e Initial load
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parents:
diff changeset
577 } // End of if actually inserted
a61af66fc99e Initial load
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parents:
diff changeset
578 } // End of if live range overlaps
605
98cb887364d3 6810672: Comment typos
twisti
parents: 337
diff changeset
579 } // End of else collect interferences for 1 node
98cb887364d3 6810672: Comment typos
twisti
parents: 337
diff changeset
580 } // End of while forever, scan back for interferences
0
a61af66fc99e Initial load
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parents:
diff changeset
581 return reg_degree;
a61af66fc99e Initial load
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parents:
diff changeset
582 }
a61af66fc99e Initial load
duke
parents:
diff changeset
583
a61af66fc99e Initial load
duke
parents:
diff changeset
584 //------------------------------update_ifg-------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
585 void PhaseConservativeCoalesce::update_ifg(uint lr1, uint lr2, IndexSet *n_lr1, IndexSet *n_lr2) {
a61af66fc99e Initial load
duke
parents:
diff changeset
586 // Some original neighbors of lr1 might have gone away
a61af66fc99e Initial load
duke
parents:
diff changeset
587 // because the constrained register mask prevented them.
a61af66fc99e Initial load
duke
parents:
diff changeset
588 // Remove lr1 from such neighbors.
a61af66fc99e Initial load
duke
parents:
diff changeset
589 IndexSetIterator one(n_lr1);
a61af66fc99e Initial load
duke
parents:
diff changeset
590 uint neighbor;
a61af66fc99e Initial load
duke
parents:
diff changeset
591 LRG &lrg1 = lrgs(lr1);
a61af66fc99e Initial load
duke
parents:
diff changeset
592 while ((neighbor = one.next()) != 0)
a61af66fc99e Initial load
duke
parents:
diff changeset
593 if( !_ulr.member(neighbor) )
a61af66fc99e Initial load
duke
parents:
diff changeset
594 if( _phc._ifg->neighbors(neighbor)->remove(lr1) )
a61af66fc99e Initial load
duke
parents:
diff changeset
595 lrgs(neighbor).inc_degree( -lrg1.compute_degree(lrgs(neighbor)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
596
a61af66fc99e Initial load
duke
parents:
diff changeset
597
a61af66fc99e Initial load
duke
parents:
diff changeset
598 // lr2 is now called (coalesced into) lr1.
a61af66fc99e Initial load
duke
parents:
diff changeset
599 // Remove lr2 from the IFG.
a61af66fc99e Initial load
duke
parents:
diff changeset
600 IndexSetIterator two(n_lr2);
a61af66fc99e Initial load
duke
parents:
diff changeset
601 LRG &lrg2 = lrgs(lr2);
a61af66fc99e Initial load
duke
parents:
diff changeset
602 while ((neighbor = two.next()) != 0)
a61af66fc99e Initial load
duke
parents:
diff changeset
603 if( _phc._ifg->neighbors(neighbor)->remove(lr2) )
a61af66fc99e Initial load
duke
parents:
diff changeset
604 lrgs(neighbor).inc_degree( -lrg2.compute_degree(lrgs(neighbor)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
605
a61af66fc99e Initial load
duke
parents:
diff changeset
606 // Some neighbors of intermediate copies now interfere with the
a61af66fc99e Initial load
duke
parents:
diff changeset
607 // combined live range.
a61af66fc99e Initial load
duke
parents:
diff changeset
608 IndexSetIterator three(&_ulr);
a61af66fc99e Initial load
duke
parents:
diff changeset
609 while ((neighbor = three.next()) != 0)
a61af66fc99e Initial load
duke
parents:
diff changeset
610 if( _phc._ifg->neighbors(neighbor)->insert(lr1) )
a61af66fc99e Initial load
duke
parents:
diff changeset
611 lrgs(neighbor).inc_degree( lrg1.compute_degree(lrgs(neighbor)) );
a61af66fc99e Initial load
duke
parents:
diff changeset
612 }
a61af66fc99e Initial load
duke
parents:
diff changeset
613
a61af66fc99e Initial load
duke
parents:
diff changeset
614 //------------------------------record_bias------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
615 static void record_bias( const PhaseIFG *ifg, int lr1, int lr2 ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
616 // Tag copy bias here
a61af66fc99e Initial load
duke
parents:
diff changeset
617 if( !ifg->lrgs(lr1)._copy_bias )
a61af66fc99e Initial load
duke
parents:
diff changeset
618 ifg->lrgs(lr1)._copy_bias = lr2;
a61af66fc99e Initial load
duke
parents:
diff changeset
619 if( !ifg->lrgs(lr2)._copy_bias )
a61af66fc99e Initial load
duke
parents:
diff changeset
620 ifg->lrgs(lr2)._copy_bias = lr1;
a61af66fc99e Initial load
duke
parents:
diff changeset
621 }
a61af66fc99e Initial load
duke
parents:
diff changeset
622
a61af66fc99e Initial load
duke
parents:
diff changeset
623 //------------------------------copy_copy--------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
624 // See if I can coalesce a series of multiple copies together. I need the
a61af66fc99e Initial load
duke
parents:
diff changeset
625 // final dest copy and the original src copy. They can be the same Node.
a61af66fc99e Initial load
duke
parents:
diff changeset
626 // Compute the compatible register masks.
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
627 bool PhaseConservativeCoalesce::copy_copy(Node *dst_copy, Node *src_copy, Block *b, uint bindex) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
628
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
629 if (!dst_copy->is_SpillCopy()) {
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
630 return false;
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
631 }
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
632 if (!src_copy->is_SpillCopy()) {
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
633 return false;
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
634 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
635 Node *src_def = src_copy->in(src_copy->is_Copy());
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
636 uint lr1 = _phc._lrg_map.find(dst_copy);
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
637 uint lr2 = _phc._lrg_map.find(src_def);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
638
a61af66fc99e Initial load
duke
parents:
diff changeset
639 // Same live ranges already?
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
640 if (lr1 == lr2) {
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
641 return false;
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
642 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
643
a61af66fc99e Initial load
duke
parents:
diff changeset
644 // Interfere?
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
645 if (_phc._ifg->test_edge_sq(lr1, lr2)) {
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
646 return false;
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
647 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
648
a61af66fc99e Initial load
duke
parents:
diff changeset
649 // Not an oop->int cast; oop->oop, int->int, AND int->oop are OK.
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
650 if (!lrgs(lr1)._is_oop && lrgs(lr2)._is_oop) { // not an oop->int cast
0
a61af66fc99e Initial load
duke
parents:
diff changeset
651 return false;
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
652 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
653
a61af66fc99e Initial load
duke
parents:
diff changeset
654 // Coalescing between an aligned live range and a mis-aligned live range?
a61af66fc99e Initial load
duke
parents:
diff changeset
655 // No, no! Alignment changes how we count degree.
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
656 if (lrgs(lr1)._fat_proj != lrgs(lr2)._fat_proj) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
657 return false;
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
658 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
659
a61af66fc99e Initial load
duke
parents:
diff changeset
660 // Sort; use smaller live-range number
a61af66fc99e Initial load
duke
parents:
diff changeset
661 Node *lr1_node = dst_copy;
a61af66fc99e Initial load
duke
parents:
diff changeset
662 Node *lr2_node = src_def;
10111
8373c19be854 8011621: live_ranges_in_separate_class.patch
neliasso
parents: 3842
diff changeset
663 if (lr1 > lr2) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
664 uint tmp = lr1; lr1 = lr2; lr2 = tmp;
a61af66fc99e Initial load
duke
parents:
diff changeset
665 lr1_node = src_def; lr2_node = dst_copy;
a61af66fc99e Initial load
duke
parents:
diff changeset
666 }
a61af66fc99e Initial load
duke
parents:
diff changeset
667
a61af66fc99e Initial load
duke
parents:
diff changeset
668 // Check for compatibility of the 2 live ranges by
a61af66fc99e Initial load
duke
parents:
diff changeset
669 // intersecting their allowed register sets.
a61af66fc99e Initial load
duke
parents:
diff changeset
670 RegMask rm = lrgs(lr1).mask();
a61af66fc99e Initial load
duke
parents:
diff changeset
671 rm.AND(lrgs(lr2).mask());
a61af66fc99e Initial load
duke
parents:
diff changeset
672 // Number of bits free
a61af66fc99e Initial load
duke
parents:
diff changeset
673 uint rm_size = rm.Size();
a61af66fc99e Initial load
duke
parents:
diff changeset
674
1730
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 1552
diff changeset
675 if (UseFPUForSpilling && rm.is_AllStack() ) {
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 1552
diff changeset
676 // Don't coalesce when frequency difference is large
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 1552
diff changeset
677 Block *dst_b = _phc._cfg._bbs[dst_copy->_idx];
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 1552
diff changeset
678 Block *src_def_b = _phc._cfg._bbs[src_def->_idx];
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 1552
diff changeset
679 if (src_def_b->_freq > 10*dst_b->_freq )
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 1552
diff changeset
680 return false;
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 1552
diff changeset
681 }
f55c4f82ab9d 6978249: spill between cpu and fpu registers when those moves are fast
never
parents: 1552
diff changeset
682
0
a61af66fc99e Initial load
duke
parents:
diff changeset
683 // If we can use any stack slot, then effective size is infinite
a61af66fc99e Initial load
duke
parents:
diff changeset
684 if( rm.is_AllStack() ) rm_size += 1000000;
a61af66fc99e Initial load
duke
parents:
diff changeset
685 // Incompatible masks, no way to coalesce
a61af66fc99e Initial load
duke
parents:
diff changeset
686 if( rm_size == 0 ) return false;
a61af66fc99e Initial load
duke
parents:
diff changeset
687
a61af66fc99e Initial load
duke
parents:
diff changeset
688 // Another early bail-out test is when we are double-coalescing and the
605
98cb887364d3 6810672: Comment typos
twisti
parents: 337
diff changeset
689 // 2 copies are separated by some control flow.
0
a61af66fc99e Initial load
duke
parents:
diff changeset
690 if( dst_copy != src_copy ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
691 Block *src_b = _phc._cfg._bbs[src_copy->_idx];
a61af66fc99e Initial load
duke
parents:
diff changeset
692 Block *b2 = b;
a61af66fc99e Initial load
duke
parents:
diff changeset
693 while( b2 != src_b ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
694 if( b2->num_preds() > 2 ){// Found merge-point
a61af66fc99e Initial load
duke
parents:
diff changeset
695 _phc._lost_opp_cflow_coalesce++;
a61af66fc99e Initial load
duke
parents:
diff changeset
696 // extra record_bias commented out because Chris believes it is not
a61af66fc99e Initial load
duke
parents:
diff changeset
697 // productive. Since we can record only 1 bias, we want to choose one
a61af66fc99e Initial load
duke
parents:
diff changeset
698 // that stands a chance of working and this one probably does not.
a61af66fc99e Initial load
duke
parents:
diff changeset
699 //record_bias( _phc._lrgs, lr1, lr2 );
a61af66fc99e Initial load
duke
parents:
diff changeset
700 return false; // To hard to find all interferences
a61af66fc99e Initial load
duke
parents:
diff changeset
701 }
a61af66fc99e Initial load
duke
parents:
diff changeset
702 b2 = _phc._cfg._bbs[b2->pred(1)->_idx];
a61af66fc99e Initial load
duke
parents:
diff changeset
703 }
a61af66fc99e Initial load
duke
parents:
diff changeset
704 }
a61af66fc99e Initial load
duke
parents:
diff changeset
705
a61af66fc99e Initial load
duke
parents:
diff changeset
706 // Union the two interference sets together into '_ulr'
a61af66fc99e Initial load
duke
parents:
diff changeset
707 uint reg_degree = _ulr.lrg_union( lr1, lr2, rm_size, _phc._ifg, rm );
a61af66fc99e Initial load
duke
parents:
diff changeset
708
a61af66fc99e Initial load
duke
parents:
diff changeset
709 if( reg_degree >= rm_size ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
710 record_bias( _phc._ifg, lr1, lr2 );
a61af66fc99e Initial load
duke
parents:
diff changeset
711 return false;
a61af66fc99e Initial load
duke
parents:
diff changeset
712 }
a61af66fc99e Initial load
duke
parents:
diff changeset
713
a61af66fc99e Initial load
duke
parents:
diff changeset
714 // Now I need to compute all the interferences between dst_copy and
a61af66fc99e Initial load
duke
parents:
diff changeset
715 // src_copy. I'm not willing visit the entire interference graph, so
a61af66fc99e Initial load
duke
parents:
diff changeset
716 // I limit my search to things in dst_copy's block or in a straight
a61af66fc99e Initial load
duke
parents:
diff changeset
717 // line of previous blocks. I give up at merge points or when I get
a61af66fc99e Initial load
duke
parents:
diff changeset
718 // more interferences than my degree. I can stop when I find src_copy.
a61af66fc99e Initial load
duke
parents:
diff changeset
719 if( dst_copy != src_copy ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
720 reg_degree = compute_separating_interferences(dst_copy, src_copy, b, bindex, rm, rm_size, reg_degree, lr1, lr2 );
a61af66fc99e Initial load
duke
parents:
diff changeset
721 if( reg_degree == max_juint ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
722 record_bias( _phc._ifg, lr1, lr2 );
a61af66fc99e Initial load
duke
parents:
diff changeset
723 return false;
a61af66fc99e Initial load
duke
parents:
diff changeset
724 }
a61af66fc99e Initial load
duke
parents:
diff changeset
725 } // End of if dst_copy & src_copy are different
a61af66fc99e Initial load
duke
parents:
diff changeset
726
a61af66fc99e Initial load
duke
parents:
diff changeset
727
a61af66fc99e Initial load
duke
parents:
diff changeset
728 // ---- THE COMBINED LRG IS COLORABLE ----
a61af66fc99e Initial load
duke
parents:
diff changeset
729
a61af66fc99e Initial load
duke
parents:
diff changeset
730 // YEAH - Now coalesce this copy away
a61af66fc99e Initial load
duke
parents:
diff changeset
731 assert( lrgs(lr1).num_regs() == lrgs(lr2).num_regs(), "" );
a61af66fc99e Initial load
duke
parents:
diff changeset
732
a61af66fc99e Initial load
duke
parents:
diff changeset
733 IndexSet *n_lr1 = _phc._ifg->neighbors(lr1);
a61af66fc99e Initial load
duke
parents:
diff changeset
734 IndexSet *n_lr2 = _phc._ifg->neighbors(lr2);
a61af66fc99e Initial load
duke
parents:
diff changeset
735
a61af66fc99e Initial load
duke
parents:
diff changeset
736 // Update the interference graph
a61af66fc99e Initial load
duke
parents:
diff changeset
737 update_ifg(lr1, lr2, n_lr1, n_lr2);
a61af66fc99e Initial load
duke
parents:
diff changeset
738
a61af66fc99e Initial load
duke
parents:
diff changeset
739 _ulr.remove(lr1);
a61af66fc99e Initial load
duke
parents:
diff changeset
740
a61af66fc99e Initial load
duke
parents:
diff changeset
741 // Uncomment the following code to trace Coalescing in great detail.
a61af66fc99e Initial load
duke
parents:
diff changeset
742 //
a61af66fc99e Initial load
duke
parents:
diff changeset
743 //if (false) {
a61af66fc99e Initial load
duke
parents:
diff changeset
744 // tty->cr();
a61af66fc99e Initial load
duke
parents:
diff changeset
745 // tty->print_cr("#######################################");
a61af66fc99e Initial load
duke
parents:
diff changeset
746 // tty->print_cr("union %d and %d", lr1, lr2);
a61af66fc99e Initial load
duke
parents:
diff changeset
747 // n_lr1->dump();
a61af66fc99e Initial load
duke
parents:
diff changeset
748 // n_lr2->dump();
a61af66fc99e Initial load
duke
parents:
diff changeset
749 // tty->print_cr("resulting set is");
a61af66fc99e Initial load
duke
parents:
diff changeset
750 // _ulr.dump();
a61af66fc99e Initial load
duke
parents:
diff changeset
751 //}
a61af66fc99e Initial load
duke
parents:
diff changeset
752
a61af66fc99e Initial load
duke
parents:
diff changeset
753 // Replace n_lr1 with the new combined live range. _ulr will use
a61af66fc99e Initial load
duke
parents:
diff changeset
754 // n_lr1's old memory on the next iteration. n_lr2 is cleared to
a61af66fc99e Initial load
duke
parents:
diff changeset
755 // send its internal memory to the free list.
a61af66fc99e Initial load
duke
parents:
diff changeset
756 _ulr.swap(n_lr1);
a61af66fc99e Initial load
duke
parents:
diff changeset
757 _ulr.clear();
a61af66fc99e Initial load
duke
parents:
diff changeset
758 n_lr2->clear();
a61af66fc99e Initial load
duke
parents:
diff changeset
759
a61af66fc99e Initial load
duke
parents:
diff changeset
760 lrgs(lr1).set_degree( _phc._ifg->effective_degree(lr1) );
a61af66fc99e Initial load
duke
parents:
diff changeset
761 lrgs(lr2).set_degree( 0 );
a61af66fc99e Initial load
duke
parents:
diff changeset
762
a61af66fc99e Initial load
duke
parents:
diff changeset
763 // Join live ranges. Merge larger into smaller. Union lr2 into lr1 in the
a61af66fc99e Initial load
duke
parents:
diff changeset
764 // union-find tree
a61af66fc99e Initial load
duke
parents:
diff changeset
765 union_helper( lr1_node, lr2_node, lr1, lr2, src_def, dst_copy, src_copy, b, bindex );
a61af66fc99e Initial load
duke
parents:
diff changeset
766 // Combine register restrictions
a61af66fc99e Initial load
duke
parents:
diff changeset
767 lrgs(lr1).set_mask(rm);
a61af66fc99e Initial load
duke
parents:
diff changeset
768 lrgs(lr1).compute_set_mask_size();
a61af66fc99e Initial load
duke
parents:
diff changeset
769 lrgs(lr1)._cost += lrgs(lr2)._cost;
a61af66fc99e Initial load
duke
parents:
diff changeset
770 lrgs(lr1)._area += lrgs(lr2)._area;
a61af66fc99e Initial load
duke
parents:
diff changeset
771
a61af66fc99e Initial load
duke
parents:
diff changeset
772 // While its uncommon to successfully coalesce live ranges that started out
a61af66fc99e Initial load
duke
parents:
diff changeset
773 // being not-lo-degree, it can happen. In any case the combined coalesced
a61af66fc99e Initial load
duke
parents:
diff changeset
774 // live range better Simplify nicely.
a61af66fc99e Initial load
duke
parents:
diff changeset
775 lrgs(lr1)._was_lo = 1;
a61af66fc99e Initial load
duke
parents:
diff changeset
776
a61af66fc99e Initial load
duke
parents:
diff changeset
777 // kinda expensive to do all the time
a61af66fc99e Initial load
duke
parents:
diff changeset
778 //tty->print_cr("warning: slow verify happening");
a61af66fc99e Initial load
duke
parents:
diff changeset
779 //_phc._ifg->verify( &_phc );
a61af66fc99e Initial load
duke
parents:
diff changeset
780 return true;
a61af66fc99e Initial load
duke
parents:
diff changeset
781 }
a61af66fc99e Initial load
duke
parents:
diff changeset
782
a61af66fc99e Initial load
duke
parents:
diff changeset
783 //------------------------------coalesce---------------------------------------
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784 // Conservative (but pessimistic) copy coalescing of a single block
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785 void PhaseConservativeCoalesce::coalesce( Block *b ) {
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786 // Bail out on infrequent blocks
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787 if( b->is_uncommon(_phc._cfg._bbs) )
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788 return;
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789 // Check this block for copies.
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790 for( uint i = 1; i<b->end_idx(); i++ ) {
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791 // Check for actual copies on inputs. Coalesce a copy into its
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792 // input if use and copy's input are compatible.
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793 Node *copy1 = b->_nodes[i];
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794 uint idx1 = copy1->is_Copy();
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795 if( !idx1 ) continue; // Not a copy
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796
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797 if( copy_copy(copy1,copy1,b,i) ) {
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798 i--; // Retry, same location in block
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799 PhaseChaitin::_conserv_coalesce++; // Collect stats on success
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800 continue;
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801 }
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802 }
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803 }