graal-compiler: src/share/vm/opto/postaloc.cpp annotate

annotate src/share/vm/opto/postaloc.cpp @ 10111:8373c19be854

8011621: live_ranges_in_separate_class.patch Reviewed-by: kvn, roland Contributed-by: niclas.adlertz@oracle.com

author	neliasso
date	Tue, 16 Apr 2013 10:08:41 +0200
parents	2aff40cb4703
children	d1034bd8cefc

rev	line source
0 a61af66fc99e Initial load duke parents: diff changeset	1 /*
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	2 * Copyright (c) 1998, 2012, Oracle and/or its affiliates. All rights reserved.
0 a61af66fc99e Initial load duke parents: diff changeset	3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
a61af66fc99e Initial load duke parents: diff changeset	4 *
a61af66fc99e Initial load duke parents: diff changeset	5 * This code is free software; you can redistribute it and/or modify it
a61af66fc99e Initial load duke parents: diff changeset	6 * under the terms of the GNU General Public License version 2 only, as
a61af66fc99e Initial load duke parents: diff changeset	7 * published by the Free Software Foundation.
a61af66fc99e Initial load duke parents: diff changeset	8 *
a61af66fc99e Initial load duke parents: diff changeset	9 * This code is distributed in the hope that it will be useful, but WITHOUT
a61af66fc99e Initial load duke parents: diff changeset	10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
a61af66fc99e Initial load duke parents: diff changeset	11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
a61af66fc99e Initial load duke parents: diff changeset	12 * version 2 for more details (a copy is included in the LICENSE file that
a61af66fc99e Initial load duke parents: diff changeset	13 * accompanied this code).
a61af66fc99e Initial load duke parents: diff changeset	14 *
a61af66fc99e Initial load duke parents: diff changeset	15 * You should have received a copy of the GNU General Public License version
a61af66fc99e Initial load duke parents: diff changeset	16 * 2 along with this work; if not, write to the Free Software Foundation,
a61af66fc99e Initial load duke parents: diff changeset	17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
a61af66fc99e Initial load duke parents: diff changeset	18 *
1552 c18cbe5936b8 6941466: Oracle rebranding changes for Hotspot repositories trims parents: 948 diff changeset	19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
c18cbe5936b8 6941466: Oracle rebranding changes for Hotspot repositories trims parents: 948 diff changeset	20 * or visit www.oracle.com if you need additional information or have any
c18cbe5936b8 6941466: Oracle rebranding changes for Hotspot repositories trims parents: 948 diff changeset	21 * questions.
0 a61af66fc99e Initial load duke parents: diff changeset	22 *
a61af66fc99e Initial load duke parents: diff changeset	23 */
a61af66fc99e Initial load duke parents: diff changeset	24
1972 f95d63e2154a 6989984: Use standard include model for Hospot stefank parents: 1552 diff changeset	25 #include "precompiled.hpp"
f95d63e2154a 6989984: Use standard include model for Hospot stefank parents: 1552 diff changeset	26 #include "memory/allocation.inline.hpp"
f95d63e2154a 6989984: Use standard include model for Hospot stefank parents: 1552 diff changeset	27 #include "opto/chaitin.hpp"
f95d63e2154a 6989984: Use standard include model for Hospot stefank parents: 1552 diff changeset	28 #include "opto/machnode.hpp"
0 a61af66fc99e Initial load duke parents: diff changeset	29
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	30 // See if this register (or pairs, or vector) already contains the value.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	31 static bool register_contains_value(Node* val, OptoReg::Name reg, int n_regs,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	32 Node_List& value) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	33 for (int i = 0; i < n_regs; i++) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	34 OptoReg::Name nreg = OptoReg::add(reg,-i);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	35 if (value[nreg] != val)
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	36 return false;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	37 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	38 return true;
0 a61af66fc99e Initial load duke parents: diff changeset	39 }
a61af66fc99e Initial load duke parents: diff changeset	40
400 cc80376deb0c 6667595: Set probability FAIR for pre-, post- loops and ALWAYS for main loop kvn parents: 196 diff changeset	41 //---------------------------may_be_copy_of_callee-----------------------------
0 a61af66fc99e Initial load duke parents: diff changeset	42 // Check to see if we can possibly be a copy of a callee-save value.
a61af66fc99e Initial load duke parents: diff changeset	43 bool PhaseChaitin::may_be_copy_of_callee( Node *def ) const {
a61af66fc99e Initial load duke parents: diff changeset	44 // Short circuit if there are no callee save registers
a61af66fc99e Initial load duke parents: diff changeset	45 if (_matcher.number_of_saved_registers() == 0) return false;
a61af66fc99e Initial load duke parents: diff changeset	46
a61af66fc99e Initial load duke parents: diff changeset	47 // Expect only a spill-down and reload on exit for callee-save spills.
a61af66fc99e Initial load duke parents: diff changeset	48 // Chains of copies cannot be deep.
a61af66fc99e Initial load duke parents: diff changeset	49 // 5008997 - This is wishful thinking. Register allocator seems to
a61af66fc99e Initial load duke parents: diff changeset	50 // be splitting live ranges for callee save registers to such
a61af66fc99e Initial load duke parents: diff changeset	51 // an extent that in large methods the chains can be very long
a61af66fc99e Initial load duke parents: diff changeset	52 // (50+). The conservative answer is to return true if we don't
605 98cb887364d3 6810672: Comment typos twisti parents: 400 diff changeset	53 // know as this prevents optimizations from occurring.
0 a61af66fc99e Initial load duke parents: diff changeset	54
a61af66fc99e Initial load duke parents: diff changeset	55 const int limit = 60;
a61af66fc99e Initial load duke parents: diff changeset	56 int i;
a61af66fc99e Initial load duke parents: diff changeset	57 for( i=0; i < limit; i++ ) {
a61af66fc99e Initial load duke parents: diff changeset	58 if( def->is_Proj() && def->in(0)->is_Start() &&
10111 8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 7196 diff changeset	59 _matcher.is_save_on_entry(lrgs(_lrg_map.live_range_id(def)).reg()))
0 a61af66fc99e Initial load duke parents: diff changeset	60 return true; // Direct use of callee-save proj
a61af66fc99e Initial load duke parents: diff changeset	61 if( def->is_Copy() ) // Copies carry value through
a61af66fc99e Initial load duke parents: diff changeset	62 def = def->in(def->is_Copy());
a61af66fc99e Initial load duke parents: diff changeset	63 else if( def->is_Phi() ) // Phis can merge it from any direction
a61af66fc99e Initial load duke parents: diff changeset	64 def = def->in(1);
a61af66fc99e Initial load duke parents: diff changeset	65 else
a61af66fc99e Initial load duke parents: diff changeset	66 break;
a61af66fc99e Initial load duke parents: diff changeset	67 guarantee(def != NULL, "must not resurrect dead copy");
a61af66fc99e Initial load duke parents: diff changeset	68 }
a61af66fc99e Initial load duke parents: diff changeset	69 // If we reached the end and didn't find a callee save proj
a61af66fc99e Initial load duke parents: diff changeset	70 // then this may be a callee save proj so we return true
a61af66fc99e Initial load duke parents: diff changeset	71 // as the conservative answer. If we didn't reach then end
a61af66fc99e Initial load duke parents: diff changeset	72 // we must have discovered that it was not a callee save
a61af66fc99e Initial load duke parents: diff changeset	73 // else we would have returned.
a61af66fc99e Initial load duke parents: diff changeset	74 return i == limit;
a61af66fc99e Initial load duke parents: diff changeset	75 }
a61af66fc99e Initial load duke parents: diff changeset	76
3934 8f47d8870d9a 7087453: PhaseChaitin::yank_if_dead() should handle MachTemp inputs roland parents: 2008 diff changeset	77 //------------------------------yank-----------------------------------
8f47d8870d9a 7087453: PhaseChaitin::yank_if_dead() should handle MachTemp inputs roland parents: 2008 diff changeset	78 // Helper function for yank_if_dead
8f47d8870d9a 7087453: PhaseChaitin::yank_if_dead() should handle MachTemp inputs roland parents: 2008 diff changeset	79 int PhaseChaitin::yank( Node old, Block current_block, Node_List value, Node_List regnd ) {
8f47d8870d9a 7087453: PhaseChaitin::yank_if_dead() should handle MachTemp inputs roland parents: 2008 diff changeset	80 int blk_adjust=0;
8f47d8870d9a 7087453: PhaseChaitin::yank_if_dead() should handle MachTemp inputs roland parents: 2008 diff changeset	81 Block *oldb = _cfg._bbs[old->_idx];
8f47d8870d9a 7087453: PhaseChaitin::yank_if_dead() should handle MachTemp inputs roland parents: 2008 diff changeset	82 oldb->find_remove(old);
8f47d8870d9a 7087453: PhaseChaitin::yank_if_dead() should handle MachTemp inputs roland parents: 2008 diff changeset	83 // Count 1 if deleting an instruction from the current block
8f47d8870d9a 7087453: PhaseChaitin::yank_if_dead() should handle MachTemp inputs roland parents: 2008 diff changeset	84 if( oldb == current_block ) blk_adjust++;
8f47d8870d9a 7087453: PhaseChaitin::yank_if_dead() should handle MachTemp inputs roland parents: 2008 diff changeset	85 _cfg._bbs.map(old->_idx,NULL);
10111 8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 7196 diff changeset	86 OptoReg::Name old_reg = lrgs(_lrg_map.live_range_id(old)).reg();
3934 8f47d8870d9a 7087453: PhaseChaitin::yank_if_dead() should handle MachTemp inputs roland parents: 2008 diff changeset	87 if( regnd && (*regnd)[old_reg]==old ) { // Instruction is currently available?
8f47d8870d9a 7087453: PhaseChaitin::yank_if_dead() should handle MachTemp inputs roland parents: 2008 diff changeset	88 value->map(old_reg,NULL); // Yank from value/regnd maps
8f47d8870d9a 7087453: PhaseChaitin::yank_if_dead() should handle MachTemp inputs roland parents: 2008 diff changeset	89 regnd->map(old_reg,NULL); // This register's value is now unknown
8f47d8870d9a 7087453: PhaseChaitin::yank_if_dead() should handle MachTemp inputs roland parents: 2008 diff changeset	90 }
8f47d8870d9a 7087453: PhaseChaitin::yank_if_dead() should handle MachTemp inputs roland parents: 2008 diff changeset	91 return blk_adjust;
8f47d8870d9a 7087453: PhaseChaitin::yank_if_dead() should handle MachTemp inputs roland parents: 2008 diff changeset	92 }
0 a61af66fc99e Initial load duke parents: diff changeset	93
4776 5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	94 #ifdef ASSERT
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	95 static bool expected_yanked_node(Node old, Node orig_old) {
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	96 // This code is expected only next original nodes:
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	97 // - load from constant table node which may have next data input nodes:
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	98 // MachConstantBase, Phi, MachTemp, MachSpillCopy
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	99 // - load constant node which may have next data input nodes:
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	100 // MachTemp, MachSpillCopy
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	101 // - MachSpillCopy
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	102 // - MachProj and Copy dead nodes
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	103 if (old->is_MachSpillCopy()) {
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	104 return true;
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	105 } else if (old->is_Con()) {
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	106 return true;
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	107 } else if (old->is_MachProj()) { // Dead kills projection of Con node
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	108 return (old == orig_old);
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	109 } else if (old->is_Copy()) { // Dead copy of a callee-save value
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	110 return (old == orig_old);
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	111 } else if (old->is_MachTemp()) {
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	112 return orig_old->is_Con();
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	113 } else if (old->is_Phi() \|\| old->is_MachConstantBase()) {
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	114 return (orig_old->is_Con() && orig_old->is_MachConstant());
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	115 }
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	116 return false;
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	117 }
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	118 #endif
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	119
0 a61af66fc99e Initial load duke parents: diff changeset	120 //------------------------------yank_if_dead-----------------------------------
4776 5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	121 // Removed edges from 'old'. Yank if dead. Return adjustment counts to
0 a61af66fc99e Initial load duke parents: diff changeset	122 // iterators in the current block.
4776 5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	123 int PhaseChaitin::yank_if_dead_recurse(Node old, Node orig_old, Block *current_block,
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	124 Node_List value, Node_List regnd) {
0 a61af66fc99e Initial load duke parents: diff changeset	125 int blk_adjust=0;
4776 5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	126 if (old->outcnt() == 0 && old != C->top()) {
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	127 #ifdef ASSERT
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	128 if (!expected_yanked_node(old, orig_old)) {
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	129 tty->print_cr("==============================================");
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	130 tty->print_cr("orig_old:");
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	131 orig_old->dump();
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	132 tty->print_cr("old:");
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	133 old->dump();
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	134 assert(false, "unexpected yanked node");
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	135 }
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	136 if (old->is_Con())
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	137 orig_old = old; // Reset to satisfy expected nodes checks.
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	138 #endif
3934 8f47d8870d9a 7087453: PhaseChaitin::yank_if_dead() should handle MachTemp inputs roland parents: 2008 diff changeset	139 blk_adjust += yank(old, current_block, value, regnd);
8f47d8870d9a 7087453: PhaseChaitin::yank_if_dead() should handle MachTemp inputs roland parents: 2008 diff changeset	140
8f47d8870d9a 7087453: PhaseChaitin::yank_if_dead() should handle MachTemp inputs roland parents: 2008 diff changeset	141 for (uint i = 1; i < old->req(); i++) {
4776 5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	142 Node* n = old->in(i);
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	143 if (n != NULL) {
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	144 old->set_req(i, NULL);
5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	145 blk_adjust += yank_if_dead_recurse(n, orig_old, current_block, value, regnd);
3934 8f47d8870d9a 7087453: PhaseChaitin::yank_if_dead() should handle MachTemp inputs roland parents: 2008 diff changeset	146 }
0 a61af66fc99e Initial load duke parents: diff changeset	147 }
4776 5da7201222d5 7110824: ctw/jarfiles/GUI3rdParty_jar/ob_mask_DateField crashes VM kvn parents: 3941 diff changeset	148 // Disconnect control and remove precedence edges if any exist
7196 2aff40cb4703 7092905: C2: Keep track of the number of dead nodes bharadwaj parents: 6185 diff changeset	149 old->disconnect_inputs(NULL, C);
0 a61af66fc99e Initial load duke parents: diff changeset	150 }
a61af66fc99e Initial load duke parents: diff changeset	151 return blk_adjust;
a61af66fc99e Initial load duke parents: diff changeset	152 }
a61af66fc99e Initial load duke parents: diff changeset	153
a61af66fc99e Initial load duke parents: diff changeset	154 //------------------------------use_prior_register-----------------------------
a61af66fc99e Initial load duke parents: diff changeset	155 // Use the prior value instead of the current value, in an effort to make
a61af66fc99e Initial load duke parents: diff changeset	156 // the current value go dead. Return block iterator adjustment, in case
a61af66fc99e Initial load duke parents: diff changeset	157 // we yank some instructions from this block.
a61af66fc99e Initial load duke parents: diff changeset	158 int PhaseChaitin::use_prior_register( Node n, uint idx, Node def, Block *current_block, Node_List &value, Node_List &regnd ) {
a61af66fc99e Initial load duke parents: diff changeset	159 // No effect?
a61af66fc99e Initial load duke parents: diff changeset	160 if( def == n->in(idx) ) return 0;
a61af66fc99e Initial load duke parents: diff changeset	161 // Def is currently dead and can be removed? Do not resurrect
a61af66fc99e Initial load duke parents: diff changeset	162 if( def->outcnt() == 0 ) return 0;
a61af66fc99e Initial load duke parents: diff changeset	163
a61af66fc99e Initial load duke parents: diff changeset	164 // Not every pair of physical registers are assignment compatible,
a61af66fc99e Initial load duke parents: diff changeset	165 // e.g. on sparc floating point registers are not assignable to integer
a61af66fc99e Initial load duke parents: diff changeset	166 // registers.
10111 8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 7196 diff changeset	167 const LRG &def_lrg = lrgs(_lrg_map.live_range_id(def));
0 a61af66fc99e Initial load duke parents: diff changeset	168 OptoReg::Name def_reg = def_lrg.reg();
a61af66fc99e Initial load duke parents: diff changeset	169 const RegMask &use_mask = n->in_RegMask(idx);
a61af66fc99e Initial load duke parents: diff changeset	170 bool can_use = ( RegMask::can_represent(def_reg) ? (use_mask.Member(def_reg) != 0)
a61af66fc99e Initial load duke parents: diff changeset	171 : (use_mask.is_AllStack() != 0));
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	172 if (!RegMask::is_vector(def->ideal_reg())) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	173 // Check for a copy to or from a misaligned pair.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	174 // It is workaround for a sparc with misaligned pairs.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	175 can_use = can_use && !use_mask.is_misaligned_pair() && !def_lrg.mask().is_misaligned_pair();
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	176 }
0 a61af66fc99e Initial load duke parents: diff changeset	177 if (!can_use)
a61af66fc99e Initial load duke parents: diff changeset	178 return 0;
a61af66fc99e Initial load duke parents: diff changeset	179
a61af66fc99e Initial load duke parents: diff changeset	180 // Capture the old def in case it goes dead...
a61af66fc99e Initial load duke parents: diff changeset	181 Node *old = n->in(idx);
a61af66fc99e Initial load duke parents: diff changeset	182
a61af66fc99e Initial load duke parents: diff changeset	183 // Save-on-call copies can only be elided if the entire copy chain can go
a61af66fc99e Initial load duke parents: diff changeset	184 // away, lest we get the same callee-save value alive in 2 locations at
a61af66fc99e Initial load duke parents: diff changeset	185 // once. We check for the obvious trivial case here. Although it can
a61af66fc99e Initial load duke parents: diff changeset	186 // sometimes be elided with cooperation outside our scope, here we will just
a61af66fc99e Initial load duke parents: diff changeset	187 // miss the opportunity. :-(
a61af66fc99e Initial load duke parents: diff changeset	188 if( may_be_copy_of_callee(def) ) {
a61af66fc99e Initial load duke parents: diff changeset	189 if( old->outcnt() > 1 ) return 0; // We're the not last user
a61af66fc99e Initial load duke parents: diff changeset	190 int idx = old->is_Copy();
a61af66fc99e Initial load duke parents: diff changeset	191 assert( idx, "chain of copies being removed" );
a61af66fc99e Initial load duke parents: diff changeset	192 Node *old2 = old->in(idx); // Chain of copies
a61af66fc99e Initial load duke parents: diff changeset	193 if( old2->outcnt() > 1 ) return 0; // old is not the last user
a61af66fc99e Initial load duke parents: diff changeset	194 int idx2 = old2->is_Copy();
a61af66fc99e Initial load duke parents: diff changeset	195 if( !idx2 ) return 0; // Not a chain of 2 copies
a61af66fc99e Initial load duke parents: diff changeset	196 if( def != old2->in(idx2) ) return 0; // Chain of exactly 2 copies
a61af66fc99e Initial load duke parents: diff changeset	197 }
a61af66fc99e Initial load duke parents: diff changeset	198
a61af66fc99e Initial load duke parents: diff changeset	199 // Use the new def
a61af66fc99e Initial load duke parents: diff changeset	200 n->set_req(idx,def);
a61af66fc99e Initial load duke parents: diff changeset	201 _post_alloc++;
a61af66fc99e Initial load duke parents: diff changeset	202
a61af66fc99e Initial load duke parents: diff changeset	203 // Is old def now dead? We successfully yanked a copy?
a61af66fc99e Initial load duke parents: diff changeset	204 return yank_if_dead(old,current_block,&value,&regnd);
a61af66fc99e Initial load duke parents: diff changeset	205 }
a61af66fc99e Initial load duke parents: diff changeset	206
a61af66fc99e Initial load duke parents: diff changeset	207
a61af66fc99e Initial load duke parents: diff changeset	208 //------------------------------skip_copies------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	209 // Skip through any number of copies (that don't mod oop-i-ness)
a61af66fc99e Initial load duke parents: diff changeset	210 Node PhaseChaitin::skip_copies( Node c ) {
a61af66fc99e Initial load duke parents: diff changeset	211 int idx = c->is_Copy();
10111 8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 7196 diff changeset	212 uint is_oop = lrgs(_lrg_map.live_range_id(c))._is_oop;
0 a61af66fc99e Initial load duke parents: diff changeset	213 while (idx != 0) {
a61af66fc99e Initial load duke parents: diff changeset	214 guarantee(c->in(idx) != NULL, "must not resurrect dead copy");
10111 8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 7196 diff changeset	215 if (lrgs(_lrg_map.live_range_id(c->in(idx)))._is_oop != is_oop) {
0 a61af66fc99e Initial load duke parents: diff changeset	216 break; // casting copy, not the same value
10111 8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 7196 diff changeset	217 }
0 a61af66fc99e Initial load duke parents: diff changeset	218 c = c->in(idx);
a61af66fc99e Initial load duke parents: diff changeset	219 idx = c->is_Copy();
a61af66fc99e Initial load duke parents: diff changeset	220 }
a61af66fc99e Initial load duke parents: diff changeset	221 return c;
a61af66fc99e Initial load duke parents: diff changeset	222 }
a61af66fc99e Initial load duke parents: diff changeset	223
a61af66fc99e Initial load duke parents: diff changeset	224 //------------------------------elide_copy-------------------------------------
a61af66fc99e Initial load duke parents: diff changeset	225 // Remove (bypass) copies along Node n, edge k.
a61af66fc99e Initial load duke parents: diff changeset	226 int PhaseChaitin::elide_copy( Node n, int k, Block current_block, Node_List &value, Node_List &regnd, bool can_change_regs ) {
a61af66fc99e Initial load duke parents: diff changeset	227 int blk_adjust = 0;
a61af66fc99e Initial load duke parents: diff changeset	228
10111 8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 7196 diff changeset	229 uint nk_idx = _lrg_map.live_range_id(n->in(k));
8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 7196 diff changeset	230 OptoReg::Name nk_reg = lrgs(nk_idx).reg();
0 a61af66fc99e Initial load duke parents: diff changeset	231
a61af66fc99e Initial load duke parents: diff changeset	232 // Remove obvious same-register copies
a61af66fc99e Initial load duke parents: diff changeset	233 Node *x = n->in(k);
a61af66fc99e Initial load duke parents: diff changeset	234 int idx;
a61af66fc99e Initial load duke parents: diff changeset	235 while( (idx=x->is_Copy()) != 0 ) {
a61af66fc99e Initial load duke parents: diff changeset	236 Node *copy = x->in(idx);
a61af66fc99e Initial load duke parents: diff changeset	237 guarantee(copy != NULL, "must not resurrect dead copy");
10111 8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 7196 diff changeset	238 if(lrgs(_lrg_map.live_range_id(copy)).reg() != nk_reg) {
8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 7196 diff changeset	239 break;
8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 7196 diff changeset	240 }
0 a61af66fc99e Initial load duke parents: diff changeset	241 blk_adjust += use_prior_register(n,k,copy,current_block,value,regnd);
10111 8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 7196 diff changeset	242 if (n->in(k) != copy) {
8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 7196 diff changeset	243 break; // Failed for some cutout?
8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 7196 diff changeset	244 }
0 a61af66fc99e Initial load duke parents: diff changeset	245 x = copy; // Progress, try again
a61af66fc99e Initial load duke parents: diff changeset	246 }
a61af66fc99e Initial load duke parents: diff changeset	247
a61af66fc99e Initial load duke parents: diff changeset	248 // Phis and 2-address instructions cannot change registers so easily - their
a61af66fc99e Initial load duke parents: diff changeset	249 // outputs must match their input.
a61af66fc99e Initial load duke parents: diff changeset	250 if( !can_change_regs )
a61af66fc99e Initial load duke parents: diff changeset	251 return blk_adjust; // Only check stupid copies!
a61af66fc99e Initial load duke parents: diff changeset	252
a61af66fc99e Initial load duke parents: diff changeset	253 // Loop backedges won't have a value-mapping yet
a61af66fc99e Initial load duke parents: diff changeset	254 if( &value == NULL ) return blk_adjust;
a61af66fc99e Initial load duke parents: diff changeset	255
a61af66fc99e Initial load duke parents: diff changeset	256 // Skip through all copies to the _value_ being used. Do not change from
a61af66fc99e Initial load duke parents: diff changeset	257 // int to pointer. This attempts to jump through a chain of copies, where
a61af66fc99e Initial load duke parents: diff changeset	258 // intermediate copies might be illegal, i.e., value is stored down to stack
a61af66fc99e Initial load duke parents: diff changeset	259 // then reloaded BUT survives in a register the whole way.
a61af66fc99e Initial load duke parents: diff changeset	260 Node *val = skip_copies(n->in(k));
a61af66fc99e Initial load duke parents: diff changeset	261
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1972 diff changeset	262 if (val == x && nk_idx != 0 &&
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1972 diff changeset	263 regnd[nk_reg] != NULL && regnd[nk_reg] != x &&
10111 8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 7196 diff changeset	264 _lrg_map.live_range_id(x) == _lrg_map.live_range_id(regnd[nk_reg])) {
2008 2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1972 diff changeset	265 // When rematerialzing nodes and stretching lifetimes, the
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1972 diff changeset	266 // allocator will reuse the original def for multidef LRG instead
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1972 diff changeset	267 // of the current reaching def because it can't know it's safe to
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1972 diff changeset	268 // do so. After allocation completes if they are in the same LRG
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1972 diff changeset	269 // then it should use the current reaching def instead.
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1972 diff changeset	270 n->set_req(k, regnd[nk_reg]);
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1972 diff changeset	271 blk_adjust += yank_if_dead(val, current_block, &value, &regnd);
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1972 diff changeset	272 val = skip_copies(n->in(k));
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1972 diff changeset	273 }
2f644f85485d 6961690: load oops from constant table on SPARC twisti parents: 1972 diff changeset	274
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	275 if (val == x) return blk_adjust; // No progress?
0 a61af66fc99e Initial load duke parents: diff changeset	276
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	277 int n_regs = RegMask::num_registers(val->ideal_reg());
10111 8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 7196 diff changeset	278 uint val_idx = _lrg_map.live_range_id(val);
0 a61af66fc99e Initial load duke parents: diff changeset	279 OptoReg::Name val_reg = lrgs(val_idx).reg();
a61af66fc99e Initial load duke parents: diff changeset	280
a61af66fc99e Initial load duke parents: diff changeset	281 // See if it happens to already be in the correct register!
a61af66fc99e Initial load duke parents: diff changeset	282 // (either Phi's direct register, or the common case of the name
a61af66fc99e Initial load duke parents: diff changeset	283 // never-clobbered original-def register)
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	284 if (register_contains_value(val, val_reg, n_regs, value)) {
0 a61af66fc99e Initial load duke parents: diff changeset	285 blk_adjust += use_prior_register(n,k,regnd[val_reg],current_block,value,regnd);
a61af66fc99e Initial load duke parents: diff changeset	286 if( n->in(k) == regnd[val_reg] ) // Success! Quit trying
a61af66fc99e Initial load duke parents: diff changeset	287 return blk_adjust;
a61af66fc99e Initial load duke parents: diff changeset	288 }
a61af66fc99e Initial load duke parents: diff changeset	289
a61af66fc99e Initial load duke parents: diff changeset	290 // See if we can skip the copy by changing registers. Don't change from
a61af66fc99e Initial load duke parents: diff changeset	291 // using a register to using the stack unless we know we can remove a
a61af66fc99e Initial load duke parents: diff changeset	292 // copy-load. Otherwise we might end up making a pile of Intel cisc-spill
a61af66fc99e Initial load duke parents: diff changeset	293 // ops reading from memory instead of just loading once and using the
a61af66fc99e Initial load duke parents: diff changeset	294 // register.
a61af66fc99e Initial load duke parents: diff changeset	295
a61af66fc99e Initial load duke parents: diff changeset	296 // Also handle duplicate copies here.
a61af66fc99e Initial load duke parents: diff changeset	297 const Type *t = val->is_Con() ? val->bottom_type() : NULL;
a61af66fc99e Initial load duke parents: diff changeset	298
a61af66fc99e Initial load duke parents: diff changeset	299 // Scan all registers to see if this value is around already
a61af66fc99e Initial load duke parents: diff changeset	300 for( uint reg = 0; reg < (uint)_max_reg; reg++ ) {
400 cc80376deb0c 6667595: Set probability FAIR for pre-, post- loops and ALWAYS for main loop kvn parents: 196 diff changeset	301 if (reg == (uint)nk_reg) {
cc80376deb0c 6667595: Set probability FAIR for pre-, post- loops and ALWAYS for main loop kvn parents: 196 diff changeset	302 // Found ourselves so check if there is only one user of this
cc80376deb0c 6667595: Set probability FAIR for pre-, post- loops and ALWAYS for main loop kvn parents: 196 diff changeset	303 // copy and keep on searching for a better copy if so.
cc80376deb0c 6667595: Set probability FAIR for pre-, post- loops and ALWAYS for main loop kvn parents: 196 diff changeset	304 bool ignore_self = true;
cc80376deb0c 6667595: Set probability FAIR for pre-, post- loops and ALWAYS for main loop kvn parents: 196 diff changeset	305 x = n->in(k);
cc80376deb0c 6667595: Set probability FAIR for pre-, post- loops and ALWAYS for main loop kvn parents: 196 diff changeset	306 DUIterator_Fast imax, i = x->fast_outs(imax);
cc80376deb0c 6667595: Set probability FAIR for pre-, post- loops and ALWAYS for main loop kvn parents: 196 diff changeset	307 Node* first = x->fast_out(i); i++;
cc80376deb0c 6667595: Set probability FAIR for pre-, post- loops and ALWAYS for main loop kvn parents: 196 diff changeset	308 while (i < imax && ignore_self) {
cc80376deb0c 6667595: Set probability FAIR for pre-, post- loops and ALWAYS for main loop kvn parents: 196 diff changeset	309 Node* use = x->fast_out(i); i++;
cc80376deb0c 6667595: Set probability FAIR for pre-, post- loops and ALWAYS for main loop kvn parents: 196 diff changeset	310 if (use != first) ignore_self = false;
cc80376deb0c 6667595: Set probability FAIR for pre-, post- loops and ALWAYS for main loop kvn parents: 196 diff changeset	311 }
cc80376deb0c 6667595: Set probability FAIR for pre-, post- loops and ALWAYS for main loop kvn parents: 196 diff changeset	312 if (ignore_self) continue;
cc80376deb0c 6667595: Set probability FAIR for pre-, post- loops and ALWAYS for main loop kvn parents: 196 diff changeset	313 }
cc80376deb0c 6667595: Set probability FAIR for pre-, post- loops and ALWAYS for main loop kvn parents: 196 diff changeset	314
0 a61af66fc99e Initial load duke parents: diff changeset	315 Node *vv = value[reg];
6185 424142833d10 7178280: Failed new vector regression tests kvn parents: 6179 diff changeset	316 if (n_regs > 1) { // Doubles and vectors check for aligned-adjacent set
424142833d10 7178280: Failed new vector regression tests kvn parents: 6179 diff changeset	317 uint last = (n_regs-1); // Looking for the last part of a set
424142833d10 7178280: Failed new vector regression tests kvn parents: 6179 diff changeset	318 if ((reg&last) != last) continue; // Wrong part of a set
424142833d10 7178280: Failed new vector regression tests kvn parents: 6179 diff changeset	319 if (!register_contains_value(vv, reg, n_regs, value)) continue; // Different value
0 a61af66fc99e Initial load duke parents: diff changeset	320 }
a61af66fc99e Initial load duke parents: diff changeset	321 if( vv == val \|\| // Got a direct hit?
a61af66fc99e Initial load duke parents: diff changeset	322 (t && vv && vv->bottom_type() == t && vv->is_Mach() &&
a61af66fc99e Initial load duke parents: diff changeset	323 vv->as_Mach()->rule() == val->as_Mach()->rule()) ) { // Or same constant?
a61af66fc99e Initial load duke parents: diff changeset	324 assert( !n->is_Phi(), "cannot change registers at a Phi so easily" );
a61af66fc99e Initial load duke parents: diff changeset	325 if( OptoReg::is_stack(nk_reg) \|\| // CISC-loading from stack OR
a61af66fc99e Initial load duke parents: diff changeset	326 OptoReg::is_reg(reg) \|\| // turning into a register use OR
a61af66fc99e Initial load duke parents: diff changeset	327 regnd[reg]->outcnt()==1 ) { // last use of a spill-load turns into a CISC use
a61af66fc99e Initial load duke parents: diff changeset	328 blk_adjust += use_prior_register(n,k,regnd[reg],current_block,value,regnd);
a61af66fc99e Initial load duke parents: diff changeset	329 if( n->in(k) == regnd[reg] ) // Success! Quit trying
a61af66fc99e Initial load duke parents: diff changeset	330 return blk_adjust;
a61af66fc99e Initial load duke parents: diff changeset	331 } // End of if not degrading to a stack
a61af66fc99e Initial load duke parents: diff changeset	332 } // End of if found value in another register
a61af66fc99e Initial load duke parents: diff changeset	333 } // End of scan all machine registers
a61af66fc99e Initial load duke parents: diff changeset	334 return blk_adjust;
a61af66fc99e Initial load duke parents: diff changeset	335 }
a61af66fc99e Initial load duke parents: diff changeset	336
a61af66fc99e Initial load duke parents: diff changeset	337
a61af66fc99e Initial load duke parents: diff changeset	338 //
a61af66fc99e Initial load duke parents: diff changeset	339 // Check if nreg already contains the constant value val. Normal copy
a61af66fc99e Initial load duke parents: diff changeset	340 // elimination doesn't doesn't work on constants because multiple
a61af66fc99e Initial load duke parents: diff changeset	341 // nodes can represent the same constant so the type and rule of the
a61af66fc99e Initial load duke parents: diff changeset	342 // MachNode must be checked to ensure equivalence.
a61af66fc99e Initial load duke parents: diff changeset	343 //
70 b683f557224b 6661247: Internal bug in 32-bit HotSpot optimizer while bit manipulations never parents: 0 diff changeset	344 bool PhaseChaitin::eliminate_copy_of_constant(Node* val, Node* n,
b683f557224b 6661247: Internal bug in 32-bit HotSpot optimizer while bit manipulations never parents: 0 diff changeset	345 Block *current_block,
0 a61af66fc99e Initial load duke parents: diff changeset	346 Node_List& value, Node_List& regnd,
a61af66fc99e Initial load duke parents: diff changeset	347 OptoReg::Name nreg, OptoReg::Name nreg2) {
a61af66fc99e Initial load duke parents: diff changeset	348 if (value[nreg] != val && val->is_Con() &&
a61af66fc99e Initial load duke parents: diff changeset	349 value[nreg] != NULL && value[nreg]->is_Con() &&
a61af66fc99e Initial load duke parents: diff changeset	350 (nreg2 == OptoReg::Bad \|\| value[nreg] == value[nreg2]) &&
a61af66fc99e Initial load duke parents: diff changeset	351 value[nreg]->bottom_type() == val->bottom_type() &&
a61af66fc99e Initial load duke parents: diff changeset	352 value[nreg]->as_Mach()->rule() == val->as_Mach()->rule()) {
a61af66fc99e Initial load duke parents: diff changeset	353 // This code assumes that two MachNodes representing constants
a61af66fc99e Initial load duke parents: diff changeset	354 // which have the same rule and the same bottom type will produce
a61af66fc99e Initial load duke parents: diff changeset	355 // identical effects into a register. This seems like it must be
a61af66fc99e Initial load duke parents: diff changeset	356 // objectively true unless there are hidden inputs to the nodes
a61af66fc99e Initial load duke parents: diff changeset	357 // but if that were to change this code would need to updated.
a61af66fc99e Initial load duke parents: diff changeset	358 // Since they are equivalent the second one if redundant and can
a61af66fc99e Initial load duke parents: diff changeset	359 // be removed.
a61af66fc99e Initial load duke parents: diff changeset	360 //
70 b683f557224b 6661247: Internal bug in 32-bit HotSpot optimizer while bit manipulations never parents: 0 diff changeset	361 // n will be replaced with the old value but n might have
0 a61af66fc99e Initial load duke parents: diff changeset	362 // kills projections associated with it so remove them now so that
605 98cb887364d3 6810672: Comment typos twisti parents: 400 diff changeset	363 // yank_if_dead will be able to eliminate the copy once the uses
0 a61af66fc99e Initial load duke parents: diff changeset	364 // have been transferred to the old[value].
70 b683f557224b 6661247: Internal bug in 32-bit HotSpot optimizer while bit manipulations never parents: 0 diff changeset	365 for (DUIterator_Fast imax, i = n->fast_outs(imax); i < imax; i++) {
b683f557224b 6661247: Internal bug in 32-bit HotSpot optimizer while bit manipulations never parents: 0 diff changeset	366 Node* use = n->fast_out(i);
0 a61af66fc99e Initial load duke parents: diff changeset	367 if (use->is_Proj() && use->outcnt() == 0) {
a61af66fc99e Initial load duke parents: diff changeset	368 // Kill projections have no users and one input
a61af66fc99e Initial load duke parents: diff changeset	369 use->set_req(0, C->top());
a61af66fc99e Initial load duke parents: diff changeset	370 yank_if_dead(use, current_block, &value, &regnd);
a61af66fc99e Initial load duke parents: diff changeset	371 --i; --imax;
a61af66fc99e Initial load duke parents: diff changeset	372 }
a61af66fc99e Initial load duke parents: diff changeset	373 }
a61af66fc99e Initial load duke parents: diff changeset	374 _post_alloc++;
a61af66fc99e Initial load duke parents: diff changeset	375 return true;
a61af66fc99e Initial load duke parents: diff changeset	376 }
a61af66fc99e Initial load duke parents: diff changeset	377 return false;
a61af66fc99e Initial load duke parents: diff changeset	378 }
a61af66fc99e Initial load duke parents: diff changeset	379
a61af66fc99e Initial load duke parents: diff changeset	380
a61af66fc99e Initial load duke parents: diff changeset	381 //------------------------------post_allocate_copy_removal---------------------
a61af66fc99e Initial load duke parents: diff changeset	382 // Post-Allocation peephole copy removal. We do this in 1 pass over the
a61af66fc99e Initial load duke parents: diff changeset	383 // basic blocks. We maintain a mapping of registers to Nodes (an array of
a61af66fc99e Initial load duke parents: diff changeset	384 // Nodes indexed by machine register or stack slot number). NULL means that a
a61af66fc99e Initial load duke parents: diff changeset	385 // register is not mapped to any Node. We can (want to have!) have several
a61af66fc99e Initial load duke parents: diff changeset	386 // registers map to the same Node. We walk forward over the instructions
a61af66fc99e Initial load duke parents: diff changeset	387 // updating the mapping as we go. At merge points we force a NULL if we have
a61af66fc99e Initial load duke parents: diff changeset	388 // to merge 2 different Nodes into the same register. Phi functions will give
a61af66fc99e Initial load duke parents: diff changeset	389 // us a new Node if there is a proper value merging. Since the blocks are
a61af66fc99e Initial load duke parents: diff changeset	390 // arranged in some RPO, we will visit all parent blocks before visiting any
a61af66fc99e Initial load duke parents: diff changeset	391 // successor blocks (except at loops).
a61af66fc99e Initial load duke parents: diff changeset	392 //
a61af66fc99e Initial load duke parents: diff changeset	393 // If we find a Copy we look to see if the Copy's source register is a stack
a61af66fc99e Initial load duke parents: diff changeset	394 // slot and that value has already been loaded into some machine register; if
a61af66fc99e Initial load duke parents: diff changeset	395 // so we use machine register directly. This turns a Load into a reg-reg
a61af66fc99e Initial load duke parents: diff changeset	396 // Move. We also look for reloads of identical constants.
a61af66fc99e Initial load duke parents: diff changeset	397 //
a61af66fc99e Initial load duke parents: diff changeset	398 // When we see a use from a reg-reg Copy, we will attempt to use the copy's
a61af66fc99e Initial load duke parents: diff changeset	399 // source directly and make the copy go dead.
a61af66fc99e Initial load duke parents: diff changeset	400 void PhaseChaitin::post_allocate_copy_removal() {
a61af66fc99e Initial load duke parents: diff changeset	401 NOT_PRODUCT( Compile::TracePhase t3("postAllocCopyRemoval", &_t_postAllocCopyRemoval, TimeCompiler); )
a61af66fc99e Initial load duke parents: diff changeset	402 ResourceMark rm;
a61af66fc99e Initial load duke parents: diff changeset	403
a61af66fc99e Initial load duke parents: diff changeset	404 // Need a mapping from basic block Node_Lists. We need a Node_List to
a61af66fc99e Initial load duke parents: diff changeset	405 // map from register number to value-producing Node.
a61af66fc99e Initial load duke parents: diff changeset	406 Node_List *blk2value = NEW_RESOURCE_ARRAY( Node_List , _cfg._num_blocks+1);
a61af66fc99e Initial load duke parents: diff changeset	407 memset( blk2value, 0, sizeof(Node_List)(_cfg._num_blocks+1) );
a61af66fc99e Initial load duke parents: diff changeset	408 // Need a mapping from basic block Node_Lists. We need a Node_List to
a61af66fc99e Initial load duke parents: diff changeset	409 // map from register number to register-defining Node.
a61af66fc99e Initial load duke parents: diff changeset	410 Node_List *blk2regnd = NEW_RESOURCE_ARRAY( Node_List , _cfg._num_blocks+1);
a61af66fc99e Initial load duke parents: diff changeset	411 memset( blk2regnd, 0, sizeof(Node_List)(_cfg._num_blocks+1) );
a61af66fc99e Initial load duke parents: diff changeset	412
a61af66fc99e Initial load duke parents: diff changeset	413 // We keep unused Node_Lists on a free_list to avoid wasting
a61af66fc99e Initial load duke parents: diff changeset	414 // memory.
a61af66fc99e Initial load duke parents: diff changeset	415 GrowableArray<Node_List> free_list = GrowableArray<Node_List>(16);
a61af66fc99e Initial load duke parents: diff changeset	416
a61af66fc99e Initial load duke parents: diff changeset	417 // For all blocks
a61af66fc99e Initial load duke parents: diff changeset	418 for( uint i = 0; i < _cfg._num_blocks; i++ ) {
a61af66fc99e Initial load duke parents: diff changeset	419 uint j;
a61af66fc99e Initial load duke parents: diff changeset	420 Block *b = _cfg._blocks[i];
a61af66fc99e Initial load duke parents: diff changeset	421
a61af66fc99e Initial load duke parents: diff changeset	422 // Count of Phis in block
a61af66fc99e Initial load duke parents: diff changeset	423 uint phi_dex;
a61af66fc99e Initial load duke parents: diff changeset	424 for( phi_dex = 1; phi_dex < b->_nodes.size(); phi_dex++ ) {
a61af66fc99e Initial load duke parents: diff changeset	425 Node *phi = b->_nodes[phi_dex];
a61af66fc99e Initial load duke parents: diff changeset	426 if( !phi->is_Phi() )
a61af66fc99e Initial load duke parents: diff changeset	427 break;
a61af66fc99e Initial load duke parents: diff changeset	428 }
a61af66fc99e Initial load duke parents: diff changeset	429
a61af66fc99e Initial load duke parents: diff changeset	430 // If any predecessor has not been visited, we do not know the state
a61af66fc99e Initial load duke parents: diff changeset	431 // of registers at the start. Check for this, while updating copies
a61af66fc99e Initial load duke parents: diff changeset	432 // along Phi input edges
a61af66fc99e Initial load duke parents: diff changeset	433 bool missing_some_inputs = false;
a61af66fc99e Initial load duke parents: diff changeset	434 Block *freed = NULL;
a61af66fc99e Initial load duke parents: diff changeset	435 for( j = 1; j < b->num_preds(); j++ ) {
a61af66fc99e Initial load duke parents: diff changeset	436 Block *pb = _cfg._bbs[b->pred(j)->_idx];
a61af66fc99e Initial load duke parents: diff changeset	437 // Remove copies along phi edges
a61af66fc99e Initial load duke parents: diff changeset	438 for( uint k=1; k<phi_dex; k++ )
a61af66fc99e Initial load duke parents: diff changeset	439 elide_copy( b->_nodes[k], j, b, blk2value[pb->_pre_order], blk2regnd[pb->_pre_order], false );
a61af66fc99e Initial load duke parents: diff changeset	440 if( blk2value[pb->_pre_order] ) { // Have a mapping on this edge?
a61af66fc99e Initial load duke parents: diff changeset	441 // See if this predecessor's mappings have been used by everybody
a61af66fc99e Initial load duke parents: diff changeset	442 // who wants them. If so, free 'em.
a61af66fc99e Initial load duke parents: diff changeset	443 uint k;
a61af66fc99e Initial load duke parents: diff changeset	444 for( k=0; k<pb->_num_succs; k++ ) {
a61af66fc99e Initial load duke parents: diff changeset	445 Block *pbsucc = pb->_succs[k];
a61af66fc99e Initial load duke parents: diff changeset	446 if( !blk2value[pbsucc->_pre_order] && pbsucc != b )
a61af66fc99e Initial load duke parents: diff changeset	447 break; // Found a future user
a61af66fc99e Initial load duke parents: diff changeset	448 }
a61af66fc99e Initial load duke parents: diff changeset	449 if( k >= pb->_num_succs ) { // No more uses, free!
a61af66fc99e Initial load duke parents: diff changeset	450 freed = pb; // Record last block freed
a61af66fc99e Initial load duke parents: diff changeset	451 free_list.push(blk2value[pb->_pre_order]);
a61af66fc99e Initial load duke parents: diff changeset	452 free_list.push(blk2regnd[pb->_pre_order]);
a61af66fc99e Initial load duke parents: diff changeset	453 }
a61af66fc99e Initial load duke parents: diff changeset	454 } else { // This block has unvisited (loopback) inputs
a61af66fc99e Initial load duke parents: diff changeset	455 missing_some_inputs = true;
a61af66fc99e Initial load duke parents: diff changeset	456 }
a61af66fc99e Initial load duke parents: diff changeset	457 }
a61af66fc99e Initial load duke parents: diff changeset	458
a61af66fc99e Initial load duke parents: diff changeset	459
a61af66fc99e Initial load duke parents: diff changeset	460 // Extract Node_List mappings. If 'freed' is non-zero, we just popped
a61af66fc99e Initial load duke parents: diff changeset	461 // 'freed's blocks off the list
a61af66fc99e Initial load duke parents: diff changeset	462 Node_List &regnd = *(free_list.is_empty() ? new Node_List() : free_list.pop());
a61af66fc99e Initial load duke parents: diff changeset	463 Node_List &value = *(free_list.is_empty() ? new Node_List() : free_list.pop());
a61af66fc99e Initial load duke parents: diff changeset	464 assert( !freed \|\| blk2value[freed->_pre_order] == &value, "" );
a61af66fc99e Initial load duke parents: diff changeset	465 value.map(_max_reg,NULL);
a61af66fc99e Initial load duke parents: diff changeset	466 regnd.map(_max_reg,NULL);
a61af66fc99e Initial load duke parents: diff changeset	467 // Set mappings as OUR mappings
a61af66fc99e Initial load duke parents: diff changeset	468 blk2value[b->_pre_order] = &value;
a61af66fc99e Initial load duke parents: diff changeset	469 blk2regnd[b->_pre_order] = &regnd;
a61af66fc99e Initial load duke parents: diff changeset	470
a61af66fc99e Initial load duke parents: diff changeset	471 // Initialize value & regnd for this block
a61af66fc99e Initial load duke parents: diff changeset	472 if( missing_some_inputs ) {
a61af66fc99e Initial load duke parents: diff changeset	473 // Some predecessor has not yet been visited; zap map to empty
a61af66fc99e Initial load duke parents: diff changeset	474 for( uint k = 0; k < (uint)_max_reg; k++ ) {
a61af66fc99e Initial load duke parents: diff changeset	475 value.map(k,NULL);
a61af66fc99e Initial load duke parents: diff changeset	476 regnd.map(k,NULL);
a61af66fc99e Initial load duke parents: diff changeset	477 }
a61af66fc99e Initial load duke parents: diff changeset	478 } else {
a61af66fc99e Initial load duke parents: diff changeset	479 if( !freed ) { // Didn't get a freebie prior block
a61af66fc99e Initial load duke parents: diff changeset	480 // Must clone some data
a61af66fc99e Initial load duke parents: diff changeset	481 freed = _cfg._bbs[b->pred(1)->_idx];
a61af66fc99e Initial load duke parents: diff changeset	482 Node_List &f_value = *blk2value[freed->_pre_order];
a61af66fc99e Initial load duke parents: diff changeset	483 Node_List &f_regnd = *blk2regnd[freed->_pre_order];
a61af66fc99e Initial load duke parents: diff changeset	484 for( uint k = 0; k < (uint)_max_reg; k++ ) {
a61af66fc99e Initial load duke parents: diff changeset	485 value.map(k,f_value[k]);
a61af66fc99e Initial load duke parents: diff changeset	486 regnd.map(k,f_regnd[k]);
a61af66fc99e Initial load duke parents: diff changeset	487 }
a61af66fc99e Initial load duke parents: diff changeset	488 }
a61af66fc99e Initial load duke parents: diff changeset	489 // Merge all inputs together, setting to NULL any conflicts.
a61af66fc99e Initial load duke parents: diff changeset	490 for( j = 1; j < b->num_preds(); j++ ) {
a61af66fc99e Initial load duke parents: diff changeset	491 Block *pb = _cfg._bbs[b->pred(j)->_idx];
a61af66fc99e Initial load duke parents: diff changeset	492 if( pb == freed ) continue; // Did self already via freelist
a61af66fc99e Initial load duke parents: diff changeset	493 Node_List &p_regnd = *blk2regnd[pb->_pre_order];
a61af66fc99e Initial load duke parents: diff changeset	494 for( uint k = 0; k < (uint)_max_reg; k++ ) {
a61af66fc99e Initial load duke parents: diff changeset	495 if( regnd[k] != p_regnd[k] ) { // Conflict on reaching defs?
a61af66fc99e Initial load duke parents: diff changeset	496 value.map(k,NULL); // Then no value handy
a61af66fc99e Initial load duke parents: diff changeset	497 regnd.map(k,NULL);
a61af66fc99e Initial load duke parents: diff changeset	498 }
a61af66fc99e Initial load duke parents: diff changeset	499 }
a61af66fc99e Initial load duke parents: diff changeset	500 }
a61af66fc99e Initial load duke parents: diff changeset	501 }
a61af66fc99e Initial load duke parents: diff changeset	502
a61af66fc99e Initial load duke parents: diff changeset	503 // For all Phi's
a61af66fc99e Initial load duke parents: diff changeset	504 for( j = 1; j < phi_dex; j++ ) {
a61af66fc99e Initial load duke parents: diff changeset	505 uint k;
a61af66fc99e Initial load duke parents: diff changeset	506 Node *phi = b->_nodes[j];
10111 8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 7196 diff changeset	507 uint pidx = _lrg_map.live_range_id(phi);
8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 7196 diff changeset	508 OptoReg::Name preg = lrgs(_lrg_map.live_range_id(phi)).reg();
0 a61af66fc99e Initial load duke parents: diff changeset	509
a61af66fc99e Initial load duke parents: diff changeset	510 // Remove copies remaining on edges. Check for junk phi.
a61af66fc99e Initial load duke parents: diff changeset	511 Node *u = NULL;
10111 8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 7196 diff changeset	512 for (k = 1; k < phi->req(); k++) {
0 a61af66fc99e Initial load duke parents: diff changeset	513 Node *x = phi->in(k);
a61af66fc99e Initial load duke parents: diff changeset	514 if( phi != x && u != x ) // Found a different input
a61af66fc99e Initial load duke parents: diff changeset	515 u = u ? NodeSentinel : x; // Capture unique input, or NodeSentinel for 2nd input
a61af66fc99e Initial load duke parents: diff changeset	516 }
a61af66fc99e Initial load duke parents: diff changeset	517 if( u != NodeSentinel ) { // Junk Phi. Remove
a61af66fc99e Initial load duke parents: diff changeset	518 b->_nodes.remove(j--); phi_dex--;
a61af66fc99e Initial load duke parents: diff changeset	519 _cfg._bbs.map(phi->_idx,NULL);
a61af66fc99e Initial load duke parents: diff changeset	520 phi->replace_by(u);
7196 2aff40cb4703 7092905: C2: Keep track of the number of dead nodes bharadwaj parents: 6185 diff changeset	521 phi->disconnect_inputs(NULL, C);
0 a61af66fc99e Initial load duke parents: diff changeset	522 continue;
a61af66fc99e Initial load duke parents: diff changeset	523 }
a61af66fc99e Initial load duke parents: diff changeset	524 // Note that if value[pidx] exists, then we merged no new values here
a61af66fc99e Initial load duke parents: diff changeset	525 // and the phi is useless. This can happen even with the above phi
a61af66fc99e Initial load duke parents: diff changeset	526 // removal for complex flows. I cannot keep the better known value here
a61af66fc99e Initial load duke parents: diff changeset	527 // because locally the phi appears to define a new merged value. If I
a61af66fc99e Initial load duke parents: diff changeset	528 // keep the better value then a copy of the phi, being unable to use the
a61af66fc99e Initial load duke parents: diff changeset	529 // global flow analysis, can't "peek through" the phi to the original
a61af66fc99e Initial load duke parents: diff changeset	530 // reaching value and so will act like it's defining a new value. This
a61af66fc99e Initial load duke parents: diff changeset	531 // can lead to situations where some uses are from the old and some from
a61af66fc99e Initial load duke parents: diff changeset	532 // the new values. Not illegal by itself but throws the over-strong
a61af66fc99e Initial load duke parents: diff changeset	533 // assert in scheduling.
a61af66fc99e Initial load duke parents: diff changeset	534 if( pidx ) {
a61af66fc99e Initial load duke parents: diff changeset	535 value.map(preg,phi);
a61af66fc99e Initial load duke parents: diff changeset	536 regnd.map(preg,phi);
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	537 int n_regs = RegMask::num_registers(phi->ideal_reg());
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	538 for (int l = 1; l < n_regs; l++) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	539 OptoReg::Name preg_lo = OptoReg::add(preg,-l);
0 a61af66fc99e Initial load duke parents: diff changeset	540 value.map(preg_lo,phi);
a61af66fc99e Initial load duke parents: diff changeset	541 regnd.map(preg_lo,phi);
a61af66fc99e Initial load duke parents: diff changeset	542 }
a61af66fc99e Initial load duke parents: diff changeset	543 }
a61af66fc99e Initial load duke parents: diff changeset	544 }
a61af66fc99e Initial load duke parents: diff changeset	545
a61af66fc99e Initial load duke parents: diff changeset	546 // For all remaining instructions
a61af66fc99e Initial load duke parents: diff changeset	547 for( j = phi_dex; j < b->_nodes.size(); j++ ) {
a61af66fc99e Initial load duke parents: diff changeset	548 Node *n = b->_nodes[j];
a61af66fc99e Initial load duke parents: diff changeset	549
a61af66fc99e Initial load duke parents: diff changeset	550 if( n->outcnt() == 0 && // Dead?
a61af66fc99e Initial load duke parents: diff changeset	551 n != C->top() && // (ignore TOP, it has no du info)
a61af66fc99e Initial load duke parents: diff changeset	552 !n->is_Proj() ) { // fat-proj kills
a61af66fc99e Initial load duke parents: diff changeset	553 j -= yank_if_dead(n,b,&value,&regnd);
a61af66fc99e Initial load duke parents: diff changeset	554 continue;
a61af66fc99e Initial load duke parents: diff changeset	555 }
a61af66fc99e Initial load duke parents: diff changeset	556
a61af66fc99e Initial load duke parents: diff changeset	557 // Improve reaching-def info. Occasionally post-alloc's liveness gives
a61af66fc99e Initial load duke parents: diff changeset	558 // up (at loop backedges, because we aren't doing a full flow pass).
a61af66fc99e Initial load duke parents: diff changeset	559 // The presence of a live use essentially asserts that the use's def is
a61af66fc99e Initial load duke parents: diff changeset	560 // alive and well at the use (or else the allocator fubar'd). Take
a61af66fc99e Initial load duke parents: diff changeset	561 // advantage of this info to set a reaching def for the use-reg.
a61af66fc99e Initial load duke parents: diff changeset	562 uint k;
10111 8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 7196 diff changeset	563 for (k = 1; k < n->req(); k++) {
0 a61af66fc99e Initial load duke parents: diff changeset	564 Node *def = n->in(k); // n->in(k) is a USE; def is the DEF for this USE
a61af66fc99e Initial load duke parents: diff changeset	565 guarantee(def != NULL, "no disconnected nodes at this point");
10111 8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 7196 diff changeset	566 uint useidx = _lrg_map.live_range_id(def); // useidx is the live range index for this USE
0 a61af66fc99e Initial load duke parents: diff changeset	567
a61af66fc99e Initial load duke parents: diff changeset	568 if( useidx ) {
a61af66fc99e Initial load duke parents: diff changeset	569 OptoReg::Name ureg = lrgs(useidx).reg();
a61af66fc99e Initial load duke parents: diff changeset	570 if( !value[ureg] ) {
a61af66fc99e Initial load duke parents: diff changeset	571 int idx; // Skip occasional useless copy
a61af66fc99e Initial load duke parents: diff changeset	572 while( (idx=def->is_Copy()) != 0 &&
a61af66fc99e Initial load duke parents: diff changeset	573 def->in(idx) != NULL && // NULL should not happen
10111 8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 7196 diff changeset	574 ureg == lrgs(_lrg_map.live_range_id(def->in(idx))).reg())
0 a61af66fc99e Initial load duke parents: diff changeset	575 def = def->in(idx);
a61af66fc99e Initial load duke parents: diff changeset	576 Node *valdef = skip_copies(def); // tighten up val through non-useless copies
a61af66fc99e Initial load duke parents: diff changeset	577 value.map(ureg,valdef); // record improved reaching-def info
a61af66fc99e Initial load duke parents: diff changeset	578 regnd.map(ureg, def);
a61af66fc99e Initial load duke parents: diff changeset	579 // Record other half of doubles
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	580 uint def_ideal_reg = def->ideal_reg();
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	581 int n_regs = RegMask::num_registers(def_ideal_reg);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	582 for (int l = 1; l < n_regs; l++) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	583 OptoReg::Name ureg_lo = OptoReg::add(ureg,-l);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	584 if (!value[ureg_lo] &&
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	585 (!RegMask::can_represent(ureg_lo) \|\|
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	586 lrgs(useidx).mask().Member(ureg_lo))) { // Nearly always adjacent
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	587 value.map(ureg_lo,valdef); // record improved reaching-def info
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	588 regnd.map(ureg_lo, def);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	589 }
0 a61af66fc99e Initial load duke parents: diff changeset	590 }
a61af66fc99e Initial load duke parents: diff changeset	591 }
a61af66fc99e Initial load duke parents: diff changeset	592 }
a61af66fc99e Initial load duke parents: diff changeset	593 }
a61af66fc99e Initial load duke parents: diff changeset	594
a61af66fc99e Initial load duke parents: diff changeset	595 const uint two_adr = n->is_Mach() ? n->as_Mach()->two_adr() : 0;
a61af66fc99e Initial load duke parents: diff changeset	596
a61af66fc99e Initial load duke parents: diff changeset	597 // Remove copies along input edges
a61af66fc99e Initial load duke parents: diff changeset	598 for( k = 1; k < n->req(); k++ )
a61af66fc99e Initial load duke parents: diff changeset	599 j -= elide_copy( n, k, b, value, regnd, two_adr!=k );
a61af66fc99e Initial load duke parents: diff changeset	600
a61af66fc99e Initial load duke parents: diff changeset	601 // Unallocated Nodes define no registers
10111 8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 7196 diff changeset	602 uint lidx = _lrg_map.live_range_id(n);
8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 7196 diff changeset	603 if (!lidx) {
8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 7196 diff changeset	604 continue;
8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 7196 diff changeset	605 }
0 a61af66fc99e Initial load duke parents: diff changeset	606
a61af66fc99e Initial load duke parents: diff changeset	607 // Update the register defined by this instruction
a61af66fc99e Initial load duke parents: diff changeset	608 OptoReg::Name nreg = lrgs(lidx).reg();
a61af66fc99e Initial load duke parents: diff changeset	609 // Skip through all copies to the _value_ being defined.
a61af66fc99e Initial load duke parents: diff changeset	610 // Do not change from int to pointer
a61af66fc99e Initial load duke parents: diff changeset	611 Node *val = skip_copies(n);
a61af66fc99e Initial load duke parents: diff changeset	612
923 a70508bb21c3 6862863: C2 compiler fails in elide_copy() never parents: 605 diff changeset	613 // Clear out a dead definition before starting so that the
a70508bb21c3 6862863: C2 compiler fails in elide_copy() never parents: 605 diff changeset	614 // elimination code doesn't have to guard against it. The
a70508bb21c3 6862863: C2 compiler fails in elide_copy() never parents: 605 diff changeset	615 // definition could in fact be a kill projection with a count of
a70508bb21c3 6862863: C2 compiler fails in elide_copy() never parents: 605 diff changeset	616 // 0 which is safe but since those are uninteresting for copy
a70508bb21c3 6862863: C2 compiler fails in elide_copy() never parents: 605 diff changeset	617 // elimination just delete them as well.
a70508bb21c3 6862863: C2 compiler fails in elide_copy() never parents: 605 diff changeset	618 if (regnd[nreg] != NULL && regnd[nreg]->outcnt() == 0) {
a70508bb21c3 6862863: C2 compiler fails in elide_copy() never parents: 605 diff changeset	619 regnd.map(nreg, NULL);
a70508bb21c3 6862863: C2 compiler fails in elide_copy() never parents: 605 diff changeset	620 value.map(nreg, NULL);
a70508bb21c3 6862863: C2 compiler fails in elide_copy() never parents: 605 diff changeset	621 }
a70508bb21c3 6862863: C2 compiler fails in elide_copy() never parents: 605 diff changeset	622
0 a61af66fc99e Initial load duke parents: diff changeset	623 uint n_ideal_reg = n->ideal_reg();
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	624 int n_regs = RegMask::num_registers(n_ideal_reg);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	625 if (n_regs == 1) {
0 a61af66fc99e Initial load duke parents: diff changeset	626 // If Node 'n' does not change the value mapped by the register,
a61af66fc99e Initial load duke parents: diff changeset	627 // then 'n' is a useless copy. Do not update the register->node
a61af66fc99e Initial load duke parents: diff changeset	628 // mapping so 'n' will go dead.
a61af66fc99e Initial load duke parents: diff changeset	629 if( value[nreg] != val ) {
70 b683f557224b 6661247: Internal bug in 32-bit HotSpot optimizer while bit manipulations never parents: 0 diff changeset	630 if (eliminate_copy_of_constant(val, n, b, value, regnd, nreg, OptoReg::Bad)) {
923 a70508bb21c3 6862863: C2 compiler fails in elide_copy() never parents: 605 diff changeset	631 j -= replace_and_yank_if_dead(n, nreg, b, value, regnd);
0 a61af66fc99e Initial load duke parents: diff changeset	632 } else {
a61af66fc99e Initial load duke parents: diff changeset	633 // Update the mapping: record new Node defined by the register
a61af66fc99e Initial load duke parents: diff changeset	634 regnd.map(nreg,n);
a61af66fc99e Initial load duke parents: diff changeset	635 // Update mapping for defined value, which is the defined
a61af66fc99e Initial load duke parents: diff changeset	636 // Node after skipping all copies.
a61af66fc99e Initial load duke parents: diff changeset	637 value.map(nreg,val);
a61af66fc99e Initial load duke parents: diff changeset	638 }
923 a70508bb21c3 6862863: C2 compiler fails in elide_copy() never parents: 605 diff changeset	639 } else if( !may_be_copy_of_callee(n) ) {
0 a61af66fc99e Initial load duke parents: diff changeset	640 assert( n->is_Copy(), "" );
923 a70508bb21c3 6862863: C2 compiler fails in elide_copy() never parents: 605 diff changeset	641 j -= replace_and_yank_if_dead(n, nreg, b, value, regnd);
0 a61af66fc99e Initial load duke parents: diff changeset	642 }
6179 8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	643 } else if (RegMask::is_vector(n_ideal_reg)) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	644 // If Node 'n' does not change the value mapped by the register,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	645 // then 'n' is a useless copy. Do not update the register->node
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	646 // mapping so 'n' will go dead.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	647 if (!register_contains_value(val, nreg, n_regs, value)) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	648 // Update the mapping: record new Node defined by the register
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	649 regnd.map(nreg,n);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	650 // Update mapping for defined value, which is the defined
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	651 // Node after skipping all copies.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	652 value.map(nreg,val);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	653 for (int l = 1; l < n_regs; l++) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	654 OptoReg::Name nreg_lo = OptoReg::add(nreg,-l);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	655 regnd.map(nreg_lo, n );
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	656 value.map(nreg_lo,val);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	657 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	658 } else if (n->is_Copy()) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	659 // Note: vector can't be constant and can't be copy of calee.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	660 j -= replace_and_yank_if_dead(n, nreg, b, value, regnd);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits kvn parents: 4776 diff changeset	661 }
0 a61af66fc99e Initial load duke parents: diff changeset	662 } else {
a61af66fc99e Initial load duke parents: diff changeset	663 // If the value occupies a register pair, record same info
a61af66fc99e Initial load duke parents: diff changeset	664 // in both registers.
a61af66fc99e Initial load duke parents: diff changeset	665 OptoReg::Name nreg_lo = OptoReg::add(nreg,-1);
a61af66fc99e Initial load duke parents: diff changeset	666 if( RegMask::can_represent(nreg_lo) && // Either a spill slot, or
a61af66fc99e Initial load duke parents: diff changeset	667 !lrgs(lidx).mask().Member(nreg_lo) ) { // Nearly always adjacent
a61af66fc99e Initial load duke parents: diff changeset	668 // Sparc occasionally has non-adjacent pairs.
a61af66fc99e Initial load duke parents: diff changeset	669 // Find the actual other value
a61af66fc99e Initial load duke parents: diff changeset	670 RegMask tmp = lrgs(lidx).mask();
a61af66fc99e Initial load duke parents: diff changeset	671 tmp.Remove(nreg);
a61af66fc99e Initial load duke parents: diff changeset	672 nreg_lo = tmp.find_first_elem();
a61af66fc99e Initial load duke parents: diff changeset	673 }
a61af66fc99e Initial load duke parents: diff changeset	674 if( value[nreg] != val \|\| value[nreg_lo] != val ) {
70 b683f557224b 6661247: Internal bug in 32-bit HotSpot optimizer while bit manipulations never parents: 0 diff changeset	675 if (eliminate_copy_of_constant(val, n, b, value, regnd, nreg, nreg_lo)) {
923 a70508bb21c3 6862863: C2 compiler fails in elide_copy() never parents: 605 diff changeset	676 j -= replace_and_yank_if_dead(n, nreg, b, value, regnd);
0 a61af66fc99e Initial load duke parents: diff changeset	677 } else {
a61af66fc99e Initial load duke parents: diff changeset	678 regnd.map(nreg , n );
a61af66fc99e Initial load duke parents: diff changeset	679 regnd.map(nreg_lo, n );
a61af66fc99e Initial load duke parents: diff changeset	680 value.map(nreg ,val);
a61af66fc99e Initial load duke parents: diff changeset	681 value.map(nreg_lo,val);
a61af66fc99e Initial load duke parents: diff changeset	682 }
923 a70508bb21c3 6862863: C2 compiler fails in elide_copy() never parents: 605 diff changeset	683 } else if( !may_be_copy_of_callee(n) ) {
0 a61af66fc99e Initial load duke parents: diff changeset	684 assert( n->is_Copy(), "" );
923 a70508bb21c3 6862863: C2 compiler fails in elide_copy() never parents: 605 diff changeset	685 j -= replace_and_yank_if_dead(n, nreg, b, value, regnd);
0 a61af66fc99e Initial load duke parents: diff changeset	686 }
a61af66fc99e Initial load duke parents: diff changeset	687 }
a61af66fc99e Initial load duke parents: diff changeset	688
a61af66fc99e Initial load duke parents: diff changeset	689 // Fat projections kill many registers
a61af66fc99e Initial load duke parents: diff changeset	690 if( n_ideal_reg == MachProjNode::fat_proj ) {
a61af66fc99e Initial load duke parents: diff changeset	691 RegMask rm = n->out_RegMask();
a61af66fc99e Initial load duke parents: diff changeset	692 // wow, what an expensive iterator...
a61af66fc99e Initial load duke parents: diff changeset	693 nreg = rm.find_first_elem();
a61af66fc99e Initial load duke parents: diff changeset	694 while( OptoReg::is_valid(nreg)) {
a61af66fc99e Initial load duke parents: diff changeset	695 rm.Remove(nreg);
a61af66fc99e Initial load duke parents: diff changeset	696 value.map(nreg,n);
a61af66fc99e Initial load duke parents: diff changeset	697 regnd.map(nreg,n);
a61af66fc99e Initial load duke parents: diff changeset	698 nreg = rm.find_first_elem();
a61af66fc99e Initial load duke parents: diff changeset	699 }
a61af66fc99e Initial load duke parents: diff changeset	700 }
a61af66fc99e Initial load duke parents: diff changeset	701
a61af66fc99e Initial load duke parents: diff changeset	702 } // End of for all instructions in the block
a61af66fc99e Initial load duke parents: diff changeset	703
a61af66fc99e Initial load duke parents: diff changeset	704 } // End for all blocks
a61af66fc99e Initial load duke parents: diff changeset	705 }

Mercurial > hg > graal-compiler

annotate src/share/vm/opto/postaloc.cpp @ 10111:8373c19be854