Mercurial > hg > graal-compiler
annotate src/share/vm/opto/ifg.cpp @ 14692:8504393de66b
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Reviewed-by: kvn, coleenp
author | twisti |
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date | Tue, 11 Mar 2014 14:54:47 -0700 |
parents | 1077c8270209 |
children | 4ca6dc0799b6 |
rev | line source |
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0 | 1 /* |
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2 * Copyright (c) 1998, 2013, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #include "precompiled.hpp" |
26 #include "compiler/oopMap.hpp" | |
27 #include "memory/allocation.inline.hpp" | |
28 #include "opto/addnode.hpp" | |
29 #include "opto/block.hpp" | |
30 #include "opto/callnode.hpp" | |
31 #include "opto/cfgnode.hpp" | |
32 #include "opto/chaitin.hpp" | |
33 #include "opto/coalesce.hpp" | |
34 #include "opto/connode.hpp" | |
35 #include "opto/indexSet.hpp" | |
36 #include "opto/machnode.hpp" | |
37 #include "opto/memnode.hpp" | |
38 #include "opto/opcodes.hpp" | |
0 | 39 |
40 PhaseIFG::PhaseIFG( Arena *arena ) : Phase(Interference_Graph), _arena(arena) { | |
41 } | |
42 | |
43 void PhaseIFG::init( uint maxlrg ) { | |
44 _maxlrg = maxlrg; | |
45 _yanked = new (_arena) VectorSet(_arena); | |
46 _is_square = false; | |
47 // Make uninitialized adjacency lists | |
48 _adjs = (IndexSet*)_arena->Amalloc(sizeof(IndexSet)*maxlrg); | |
49 // Also make empty live range structures | |
50 _lrgs = (LRG *)_arena->Amalloc( maxlrg * sizeof(LRG) ); | |
51 memset(_lrgs,0,sizeof(LRG)*maxlrg); | |
52 // Init all to empty | |
53 for( uint i = 0; i < maxlrg; i++ ) { | |
54 _adjs[i].initialize(maxlrg); | |
55 _lrgs[i].Set_All(); | |
56 } | |
57 } | |
58 | |
59 // Add edge between vertices a & b. These are sorted (triangular matrix), | |
60 // then the smaller number is inserted in the larger numbered array. | |
61 int PhaseIFG::add_edge( uint a, uint b ) { | |
62 lrgs(a).invalid_degree(); | |
63 lrgs(b).invalid_degree(); | |
64 // Sort a and b, so that a is bigger | |
65 assert( !_is_square, "only on triangular" ); | |
66 if( a < b ) { uint tmp = a; a = b; b = tmp; } | |
67 return _adjs[a].insert( b ); | |
68 } | |
69 | |
70 // Add an edge between 'a' and everything in the vector. | |
71 void PhaseIFG::add_vector( uint a, IndexSet *vec ) { | |
72 // IFG is triangular, so do the inserts where 'a' < 'b'. | |
73 assert( !_is_square, "only on triangular" ); | |
74 IndexSet *adjs_a = &_adjs[a]; | |
75 if( !vec->count() ) return; | |
76 | |
77 IndexSetIterator elements(vec); | |
78 uint neighbor; | |
79 while ((neighbor = elements.next()) != 0) { | |
80 add_edge( a, neighbor ); | |
81 } | |
82 } | |
83 | |
84 // Is there an edge between a and b? | |
85 int PhaseIFG::test_edge( uint a, uint b ) const { | |
86 // Sort a and b, so that a is larger | |
87 assert( !_is_square, "only on triangular" ); | |
88 if( a < b ) { uint tmp = a; a = b; b = tmp; } | |
89 return _adjs[a].member(b); | |
90 } | |
91 | |
92 // Convert triangular matrix to square matrix | |
93 void PhaseIFG::SquareUp() { | |
94 assert( !_is_square, "only on triangular" ); | |
95 | |
96 // Simple transpose | |
97 for( uint i = 0; i < _maxlrg; i++ ) { | |
98 IndexSetIterator elements(&_adjs[i]); | |
99 uint datum; | |
100 while ((datum = elements.next()) != 0) { | |
101 _adjs[datum].insert( i ); | |
102 } | |
103 } | |
104 _is_square = true; | |
105 } | |
106 | |
107 // Compute effective degree in bulk | |
108 void PhaseIFG::Compute_Effective_Degree() { | |
109 assert( _is_square, "only on square" ); | |
110 | |
111 for( uint i = 0; i < _maxlrg; i++ ) | |
112 lrgs(i).set_degree(effective_degree(i)); | |
113 } | |
114 | |
115 int PhaseIFG::test_edge_sq( uint a, uint b ) const { | |
116 assert( _is_square, "only on square" ); | |
117 // Swap, so that 'a' has the lesser count. Then binary search is on | |
118 // the smaller of a's list and b's list. | |
119 if( neighbor_cnt(a) > neighbor_cnt(b) ) { uint tmp = a; a = b; b = tmp; } | |
120 //return _adjs[a].unordered_member(b); | |
121 return _adjs[a].member(b); | |
122 } | |
123 | |
124 // Union edges of B into A | |
125 void PhaseIFG::Union( uint a, uint b ) { | |
126 assert( _is_square, "only on square" ); | |
127 IndexSet *A = &_adjs[a]; | |
128 IndexSetIterator b_elements(&_adjs[b]); | |
129 uint datum; | |
130 while ((datum = b_elements.next()) != 0) { | |
131 if(A->insert(datum)) { | |
132 _adjs[datum].insert(a); | |
133 lrgs(a).invalid_degree(); | |
134 lrgs(datum).invalid_degree(); | |
135 } | |
136 } | |
137 } | |
138 | |
139 // Yank a Node and all connected edges from the IFG. Return a | |
140 // list of neighbors (edges) yanked. | |
141 IndexSet *PhaseIFG::remove_node( uint a ) { | |
142 assert( _is_square, "only on square" ); | |
143 assert( !_yanked->test(a), "" ); | |
144 _yanked->set(a); | |
145 | |
146 // I remove the LRG from all neighbors. | |
147 IndexSetIterator elements(&_adjs[a]); | |
148 LRG &lrg_a = lrgs(a); | |
149 uint datum; | |
150 while ((datum = elements.next()) != 0) { | |
151 _adjs[datum].remove(a); | |
152 lrgs(datum).inc_degree( -lrg_a.compute_degree(lrgs(datum)) ); | |
153 } | |
154 return neighbors(a); | |
155 } | |
156 | |
157 // Re-insert a yanked Node. | |
158 void PhaseIFG::re_insert( uint a ) { | |
159 assert( _is_square, "only on square" ); | |
160 assert( _yanked->test(a), "" ); | |
161 (*_yanked) >>= a; | |
162 | |
163 IndexSetIterator elements(&_adjs[a]); | |
164 uint datum; | |
165 while ((datum = elements.next()) != 0) { | |
166 _adjs[datum].insert(a); | |
167 lrgs(datum).invalid_degree(); | |
168 } | |
169 } | |
170 | |
171 // Compute the degree between 2 live ranges. If both live ranges are | |
172 // aligned-adjacent powers-of-2 then we use the MAX size. If either is | |
173 // mis-aligned (or for Fat-Projections, not-adjacent) then we have to | |
174 // MULTIPLY the sizes. Inspect Brigg's thesis on register pairs to see why | |
175 // this is so. | |
176 int LRG::compute_degree( LRG &l ) const { | |
177 int tmp; | |
178 int num_regs = _num_regs; | |
179 int nregs = l.num_regs(); | |
180 tmp = (_fat_proj || l._fat_proj) // either is a fat-proj? | |
181 ? (num_regs * nregs) // then use product | |
182 : MAX2(num_regs,nregs); // else use max | |
183 return tmp; | |
184 } | |
185 | |
186 // Compute effective degree for this live range. If both live ranges are | |
187 // aligned-adjacent powers-of-2 then we use the MAX size. If either is | |
188 // mis-aligned (or for Fat-Projections, not-adjacent) then we have to | |
189 // MULTIPLY the sizes. Inspect Brigg's thesis on register pairs to see why | |
190 // this is so. | |
191 int PhaseIFG::effective_degree( uint lidx ) const { | |
192 int eff = 0; | |
193 int num_regs = lrgs(lidx).num_regs(); | |
194 int fat_proj = lrgs(lidx)._fat_proj; | |
195 IndexSet *s = neighbors(lidx); | |
196 IndexSetIterator elements(s); | |
197 uint nidx; | |
198 while((nidx = elements.next()) != 0) { | |
199 LRG &lrgn = lrgs(nidx); | |
200 int nregs = lrgn.num_regs(); | |
201 eff += (fat_proj || lrgn._fat_proj) // either is a fat-proj? | |
202 ? (num_regs * nregs) // then use product | |
203 : MAX2(num_regs,nregs); // else use max | |
204 } | |
205 return eff; | |
206 } | |
207 | |
208 | |
209 #ifndef PRODUCT | |
210 void PhaseIFG::dump() const { | |
211 tty->print_cr("-- Interference Graph --%s--", | |
212 _is_square ? "square" : "triangular" ); | |
213 if( _is_square ) { | |
214 for( uint i = 0; i < _maxlrg; i++ ) { | |
215 tty->print( (*_yanked)[i] ? "XX " : " "); | |
216 tty->print("L%d: { ",i); | |
217 IndexSetIterator elements(&_adjs[i]); | |
218 uint datum; | |
219 while ((datum = elements.next()) != 0) { | |
220 tty->print("L%d ", datum); | |
221 } | |
222 tty->print_cr("}"); | |
223 | |
224 } | |
225 return; | |
226 } | |
227 | |
228 // Triangular | |
229 for( uint i = 0; i < _maxlrg; i++ ) { | |
230 uint j; | |
231 tty->print( (*_yanked)[i] ? "XX " : " "); | |
232 tty->print("L%d: { ",i); | |
233 for( j = _maxlrg; j > i; j-- ) | |
234 if( test_edge(j - 1,i) ) { | |
235 tty->print("L%d ",j - 1); | |
236 } | |
237 tty->print("| "); | |
238 IndexSetIterator elements(&_adjs[i]); | |
239 uint datum; | |
240 while ((datum = elements.next()) != 0) { | |
241 tty->print("L%d ", datum); | |
242 } | |
243 tty->print("}\n"); | |
244 } | |
245 tty->print("\n"); | |
246 } | |
247 | |
248 void PhaseIFG::stats() const { | |
249 ResourceMark rm; | |
250 int *h_cnt = NEW_RESOURCE_ARRAY(int,_maxlrg*2); | |
251 memset( h_cnt, 0, sizeof(int)*_maxlrg*2 ); | |
252 uint i; | |
253 for( i = 0; i < _maxlrg; i++ ) { | |
254 h_cnt[neighbor_cnt(i)]++; | |
255 } | |
256 tty->print_cr("--Histogram of counts--"); | |
257 for( i = 0; i < _maxlrg*2; i++ ) | |
258 if( h_cnt[i] ) | |
259 tty->print("%d/%d ",i,h_cnt[i]); | |
260 tty->print_cr(""); | |
261 } | |
262 | |
263 void PhaseIFG::verify( const PhaseChaitin *pc ) const { | |
264 // IFG is square, sorted and no need for Find | |
265 for( uint i = 0; i < _maxlrg; i++ ) { | |
266 assert(!((*_yanked)[i]) || !neighbor_cnt(i), "Is removed completely" ); | |
267 IndexSet *set = &_adjs[i]; | |
268 IndexSetIterator elements(set); | |
269 uint idx; | |
270 uint last = 0; | |
271 while ((idx = elements.next()) != 0) { | |
10111 | 272 assert(idx != i, "Must have empty diagonal"); |
273 assert(pc->_lrg_map.find_const(idx) == idx, "Must not need Find"); | |
274 assert(_adjs[idx].member(i), "IFG not square"); | |
275 assert(!(*_yanked)[idx], "No yanked neighbors"); | |
276 assert(last < idx, "not sorted increasing"); | |
0 | 277 last = idx; |
278 } | |
10111 | 279 assert(!lrgs(i)._degree_valid || effective_degree(i) == lrgs(i).degree(), "degree is valid but wrong"); |
0 | 280 } |
281 } | |
282 #endif | |
283 | |
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284 /* |
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285 * Interfere this register with everything currently live. |
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286 * Check for interference by checking overlap of regmasks. |
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287 * Only interfere if acceptable register masks overlap. |
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288 */ |
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289 void PhaseChaitin::interfere_with_live(uint lid, IndexSet* liveout) { |
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290 LRG& lrg = lrgs(lid); |
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291 const RegMask& rm = lrg.mask(); |
0 | 292 IndexSetIterator elements(liveout); |
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293 uint interfering_lid = elements.next(); |
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294 while (interfering_lid != 0) { |
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295 LRG& interfering_lrg = lrgs(interfering_lid); |
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296 if (rm.overlap(interfering_lrg.mask())) { |
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297 _ifg->add_edge(lid, interfering_lid); |
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298 } |
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299 interfering_lid = elements.next(); |
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300 } |
0 | 301 } |
302 | |
303 // Actually build the interference graph. Uses virtual registers only, no | |
304 // physical register masks. This allows me to be very aggressive when | |
305 // coalescing copies. Some of this aggressiveness will have to be undone | |
306 // later, but I'd rather get all the copies I can now (since unremoved copies | |
307 // at this point can end up in bad places). Copies I re-insert later I have | |
308 // more opportunity to insert them in low-frequency locations. | |
309 void PhaseChaitin::build_ifg_virtual( ) { | |
310 | |
311 // For all blocks (in any order) do... | |
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312 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
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313 Block* block = _cfg.get_block(i); |
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314 IndexSet* liveout = _live->live(block); |
0 | 315 |
316 // The IFG is built by a single reverse pass over each basic block. | |
317 // Starting with the known live-out set, we remove things that get | |
318 // defined and add things that become live (essentially executing one | |
319 // pass of a standard LIVE analysis). Just before a Node defines a value | |
320 // (and removes it from the live-ness set) that value is certainly live. | |
321 // The defined value interferes with everything currently live. The | |
322 // value is then removed from the live-ness set and it's inputs are | |
323 // added to the live-ness set. | |
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324 for (uint j = block->end_idx() + 1; j > 1; j--) { |
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325 Node* n = block->get_node(j - 1); |
0 | 326 |
327 // Get value being defined | |
10111 | 328 uint r = _lrg_map.live_range_id(n); |
0 | 329 |
330 // Some special values do not allocate | |
10111 | 331 if (r) { |
0 | 332 |
333 // Remove from live-out set | |
334 liveout->remove(r); | |
335 | |
336 // Copies do not define a new value and so do not interfere. | |
337 // Remove the copies source from the liveout set before interfering. | |
338 uint idx = n->is_Copy(); | |
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339 if (idx != 0) { |
10111 | 340 liveout->remove(_lrg_map.live_range_id(n->in(idx))); |
341 } | |
0 | 342 |
343 // Interfere with everything live | |
10111 | 344 interfere_with_live(r, liveout); |
0 | 345 } |
346 | |
347 // Make all inputs live | |
10111 | 348 if (!n->is_Phi()) { // Phi function uses come from prior block |
349 for(uint k = 1; k < n->req(); k++) { | |
350 liveout->insert(_lrg_map.live_range_id(n->in(k))); | |
351 } | |
0 | 352 } |
353 | |
354 // 2-address instructions always have the defined value live | |
355 // on entry to the instruction, even though it is being defined | |
356 // by the instruction. We pretend a virtual copy sits just prior | |
357 // to the instruction and kills the src-def'd register. | |
358 // In other words, for 2-address instructions the defined value | |
359 // interferes with all inputs. | |
360 uint idx; | |
361 if( n->is_Mach() && (idx = n->as_Mach()->two_adr()) ) { | |
362 const MachNode *mach = n->as_Mach(); | |
363 // Sometimes my 2-address ADDs are commuted in a bad way. | |
364 // We generally want the USE-DEF register to refer to the | |
365 // loop-varying quantity, to avoid a copy. | |
366 uint op = mach->ideal_Opcode(); | |
367 // Check that mach->num_opnds() == 3 to ensure instruction is | |
368 // not subsuming constants, effectively excludes addI_cin_imm | |
369 // Can NOT swap for instructions like addI_cin_imm since it | |
370 // is adding zero to yhi + carry and the second ideal-input | |
371 // points to the result of adding low-halves. | |
372 // Checking req() and num_opnds() does NOT distinguish addI_cout from addI_cout_imm | |
373 if( (op == Op_AddI && mach->req() == 3 && mach->num_opnds() == 3) && | |
374 n->in(1)->bottom_type()->base() == Type::Int && | |
375 // See if the ADD is involved in a tight data loop the wrong way | |
376 n->in(2)->is_Phi() && | |
377 n->in(2)->in(2) == n ) { | |
378 Node *tmp = n->in(1); | |
379 n->set_req( 1, n->in(2) ); | |
380 n->set_req( 2, tmp ); | |
381 } | |
382 // Defined value interferes with all inputs | |
10111 | 383 uint lidx = _lrg_map.live_range_id(n->in(idx)); |
384 for (uint k = 1; k < n->req(); k++) { | |
385 uint kidx = _lrg_map.live_range_id(n->in(k)); | |
386 if (kidx != lidx) { | |
387 _ifg->add_edge(r, kidx); | |
388 } | |
0 | 389 } |
390 } | |
391 } // End of forall instructions in block | |
392 } // End of forall blocks | |
393 } | |
394 | |
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395 #ifdef ASSERT |
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396 uint PhaseChaitin::count_int_pressure(IndexSet* liveout) { |
0 | 397 IndexSetIterator elements(liveout); |
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398 uint lidx = elements.next(); |
0 | 399 uint cnt = 0; |
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400 while (lidx != 0) { |
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401 LRG& lrg = lrgs(lidx); |
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402 if (lrg.mask_is_nonempty_and_up() && |
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403 !lrg.is_float_or_vector() && |
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404 lrg.mask().overlap(*Matcher::idealreg2regmask[Op_RegI])) { |
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405 cnt += lrg.reg_pressure(); |
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406 } |
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407 lidx = elements.next(); |
0 | 408 } |
409 return cnt; | |
410 } | |
411 | |
14388
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412 uint PhaseChaitin::count_float_pressure(IndexSet* liveout) { |
0 | 413 IndexSetIterator elements(liveout); |
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414 uint lidx = elements.next(); |
0 | 415 uint cnt = 0; |
14388
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416 while (lidx != 0) { |
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417 LRG& lrg = lrgs(lidx); |
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418 if (lrg.mask_is_nonempty_and_up() && lrg.is_float_or_vector()) { |
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419 cnt += lrg.reg_pressure(); |
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420 } |
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421 lidx = elements.next(); |
0 | 422 } |
423 return cnt; | |
424 } | |
14388
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425 #endif |
0 | 426 |
14388
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427 /* |
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428 * Adjust register pressure down by 1. Capture last hi-to-low transition, |
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429 */ |
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430 void PhaseChaitin::lower_pressure(Block* b, uint location, LRG& lrg, IndexSet* liveout, Pressure& int_pressure, Pressure& float_pressure) { |
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431 if (lrg.mask_is_nonempty_and_up()) { |
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432 if (lrg.is_float_or_vector()) { |
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433 float_pressure.lower(lrg, location); |
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434 } else { |
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435 // Do not count the SP and flag registers |
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436 const RegMask& r = lrg.mask(); |
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437 if (r.overlap(*Matcher::idealreg2regmask[Op_RegI])) { |
c84312468f5c
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438 int_pressure.lower(lrg, location); |
0 | 439 } |
14388
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440 } |
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441 } |
14496 | 442 assert(int_pressure.current_pressure() == count_int_pressure(liveout), "the int pressure is incorrect"); |
443 assert(float_pressure.current_pressure() == count_float_pressure(liveout), "the float pressure is incorrect"); | |
14388
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444 } |
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445 |
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446 /* Go to the first non-phi index in a block */ |
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447 static uint first_nonphi_index(Block* b) { |
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448 uint i; |
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449 uint end_idx = b->end_idx(); |
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450 for (i = 1; i < end_idx; i++) { |
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451 Node* n = b->get_node(i); |
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452 if (!n->is_Phi()) { |
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453 break; |
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454 } |
c84312468f5c
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455 } |
c84312468f5c
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456 return i; |
c84312468f5c
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457 } |
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458 |
c84312468f5c
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459 /* |
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460 * Spills could be inserted before a CreateEx node which should be the first |
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461 * instruction in a block after Phi nodes. If so, move the CreateEx node up. |
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462 */ |
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463 static void move_exception_node_up(Block* b, uint first_inst, uint last_inst) { |
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464 for (uint i = first_inst; i < last_inst; i++) { |
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465 Node* ex = b->get_node(i); |
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466 if (ex->is_SpillCopy()) { |
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467 continue; |
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468 } |
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469 |
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470 if (i > first_inst && |
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471 ex->is_Mach() && ex->as_Mach()->ideal_Opcode() == Op_CreateEx) { |
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472 b->remove_node(i); |
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473 b->insert_node(ex, first_inst); |
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474 } |
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475 // Stop once a CreateEx or any other node is found |
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476 break; |
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|
477 } |
c84312468f5c
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changeset
|
478 } |
c84312468f5c
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|
479 |
c84312468f5c
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|
480 /* |
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481 * When new live ranges are live, we raise the register pressure |
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|
482 */ |
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483 void PhaseChaitin::raise_pressure(Block* b, LRG& lrg, Pressure& int_pressure, Pressure& float_pressure) { |
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484 if (lrg.mask_is_nonempty_and_up()) { |
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485 if (lrg.is_float_or_vector()) { |
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486 float_pressure.raise(lrg); |
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487 } else { |
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|
488 // Do not count the SP and flag registers |
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489 const RegMask& rm = lrg.mask(); |
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490 if (rm.overlap(*Matcher::idealreg2regmask[Op_RegI])) { |
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491 int_pressure.raise(lrg); |
0 | 492 } |
493 } | |
494 } | |
495 } | |
496 | |
14388
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497 |
c84312468f5c
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|
498 /* |
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|
499 * Computes the initial register pressure of a block, looking at all live |
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500 * ranges in the liveout. The register pressure is computed for both float |
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501 * and int/pointer registers. |
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502 * Live ranges in the liveout are presumed live for the whole block. |
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503 * We add the cost for the whole block to the area of the live ranges initially. |
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504 * If a live range gets killed in the block, we'll subtract the unused part of |
c84312468f5c
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505 * the block from the area. |
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|
506 */ |
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507 void PhaseChaitin::compute_initial_block_pressure(Block* b, IndexSet* liveout, Pressure& int_pressure, Pressure& float_pressure, double cost) { |
c84312468f5c
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508 IndexSetIterator elements(liveout); |
c84312468f5c
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509 uint lid = elements.next(); |
c84312468f5c
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510 while (lid != 0) { |
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511 LRG& lrg = lrgs(lid); |
c84312468f5c
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512 lrg._area += cost; |
c84312468f5c
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513 raise_pressure(b, lrg, int_pressure, float_pressure); |
c84312468f5c
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514 lid = elements.next(); |
c84312468f5c
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515 } |
14496 | 516 assert(int_pressure.current_pressure() == count_int_pressure(liveout), "the int pressure is incorrect"); |
517 assert(float_pressure.current_pressure() == count_float_pressure(liveout), "the float pressure is incorrect"); | |
14388
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518 } |
0 | 519 |
14388
c84312468f5c
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adlertz
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|
520 /* |
c84312468f5c
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adlertz
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|
521 * Remove dead node if it's not used. |
c84312468f5c
8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical
adlertz
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522 * We only remove projection nodes if the node "defining" the projection is |
c84312468f5c
8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical
adlertz
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523 * dead, for example on x86, if we have a dead Add node we remove its |
c84312468f5c
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|
524 * RFLAGS node. |
c84312468f5c
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adlertz
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|
525 */ |
c84312468f5c
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|
526 bool PhaseChaitin::remove_node_if_not_used(Block* b, uint location, Node* n, uint lid, IndexSet* liveout) { |
c84312468f5c
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527 Node* def = n->in(0); |
c84312468f5c
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528 if (!n->is_Proj() || |
c84312468f5c
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adlertz
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529 (_lrg_map.live_range_id(def) && !liveout->member(_lrg_map.live_range_id(def)))) { |
c84312468f5c
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adlertz
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530 b->remove_node(location); |
c84312468f5c
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adlertz
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531 LRG& lrg = lrgs(lid); |
c84312468f5c
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532 if (lrg._def == n) { |
c84312468f5c
8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical
adlertz
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|
533 lrg._def = 0; |
c84312468f5c
8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical
adlertz
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|
534 } |
c84312468f5c
8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical
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|
535 n->disconnect_inputs(NULL, C); |
c84312468f5c
8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical
adlertz
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|
536 _cfg.unmap_node_from_block(n); |
c84312468f5c
8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical
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|
537 n->replace_by(C->top()); |
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538 return true; |
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539 } |
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540 return false; |
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541 } |
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542 |
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543 /* |
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544 * When encountering a fat projection, we might go from a low to high to low |
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545 * (since the fat proj only lives at this instruction) going backwards in the |
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546 * block. If we find a low to high transition, we record it. |
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547 */ |
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548 void PhaseChaitin::check_for_high_pressure_transition_at_fatproj(uint& block_reg_pressure, uint location, LRG& lrg, Pressure& pressure, const int op_regtype) { |
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549 RegMask mask_tmp = lrg.mask(); |
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550 mask_tmp.AND(*Matcher::idealreg2regmask[op_regtype]); |
14496 | 551 pressure.check_pressure_at_fatproj(location, mask_tmp); |
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552 } |
0 | 553 |
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554 /* |
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555 * Insure high score for immediate-use spill copies so they get a color. |
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556 * All single-use MachSpillCopy(s) that immediately precede their |
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557 * use must color early. If a longer live range steals their |
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558 * color, the spill copy will split and may push another spill copy |
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559 * further away resulting in an infinite spill-split-retry cycle. |
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560 * Assigning a zero area results in a high score() and a good |
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561 * location in the simplify list. |
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562 */ |
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563 void PhaseChaitin::assign_high_score_to_immediate_copies(Block* b, Node* n, LRG& lrg, uint next_inst, uint last_inst) { |
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564 if (n->is_SpillCopy() && |
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565 lrg.is_singledef() && // A multi defined live range can still split |
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566 n->outcnt() == 1 && // and use must be in this block |
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567 _cfg.get_block_for_node(n->unique_out()) == b) { |
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568 |
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569 Node* single_use = n->unique_out(); |
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570 assert(b->find_node(single_use) >= next_inst, "Use must be later in block"); |
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571 // Use can be earlier in block if it is a Phi, but then I should be a MultiDef |
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572 |
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573 // Find first non SpillCopy 'm' that follows the current instruction |
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574 // (current_inst - 1) is index for current instruction 'n' |
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575 Node* m = n; |
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576 for (uint i = next_inst; i <= last_inst && m->is_SpillCopy(); ++i) { |
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577 m = b->get_node(i); |
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578 } |
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579 if (m == single_use) { |
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580 lrg._area = 0.0; |
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581 } |
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582 } |
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583 } |
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584 |
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585 /* |
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586 * Copies do not define a new value and so do not interfere. |
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587 * Remove the copies source from the liveout set before interfering. |
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588 */ |
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589 void PhaseChaitin::remove_interference_from_copy(Block* b, uint location, uint lid_copy, IndexSet* liveout, double cost, Pressure& int_pressure, Pressure& float_pressure) { |
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590 if (liveout->remove(lid_copy)) { |
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591 LRG& lrg_copy = lrgs(lid_copy); |
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592 lrg_copy._area -= cost; |
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593 |
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594 // Lower register pressure since copy and definition can share the same register |
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595 lower_pressure(b, location, lrg_copy, liveout, int_pressure, float_pressure); |
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596 } |
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597 } |
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598 |
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599 /* |
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600 * The defined value must go in a particular register. Remove that register from |
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601 * all conflicting parties and avoid the interference. |
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602 */ |
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603 void PhaseChaitin::remove_bound_register_from_interfering_live_ranges(LRG& lrg, IndexSet* liveout, uint& must_spill) { |
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604 // Check for common case |
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605 const RegMask& rm = lrg.mask(); |
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606 int r_size = lrg.num_regs(); |
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607 // Smear odd bits |
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608 IndexSetIterator elements(liveout); |
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609 uint l = elements.next(); |
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610 while (l != 0) { |
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611 LRG& interfering_lrg = lrgs(l); |
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612 // If 'l' must spill already, do not further hack his bits. |
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613 // He'll get some interferences and be forced to spill later. |
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614 if (interfering_lrg._must_spill) { |
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615 l = elements.next(); |
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616 continue; |
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617 } |
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618 |
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619 // Remove bound register(s) from 'l's choices |
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620 RegMask old = interfering_lrg.mask(); |
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621 uint old_size = interfering_lrg.mask_size(); |
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622 |
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623 // Remove the bits from LRG 'rm' from LRG 'l' so 'l' no |
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624 // longer interferes with 'rm'. If 'l' requires aligned |
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625 // adjacent pairs, subtract out bit pairs. |
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626 assert(!interfering_lrg._is_vector || !interfering_lrg._fat_proj, "sanity"); |
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627 |
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628 if (interfering_lrg.num_regs() > 1 && !interfering_lrg._fat_proj) { |
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629 RegMask r2mask = rm; |
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630 // Leave only aligned set of bits. |
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631 r2mask.smear_to_sets(interfering_lrg.num_regs()); |
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632 // It includes vector case. |
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633 interfering_lrg.SUBTRACT(r2mask); |
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634 interfering_lrg.compute_set_mask_size(); |
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635 } else if (r_size != 1) { |
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636 // fat proj |
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637 interfering_lrg.SUBTRACT(rm); |
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638 interfering_lrg.compute_set_mask_size(); |
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639 } else { |
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640 // Common case: size 1 bound removal |
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641 OptoReg::Name r_reg = rm.find_first_elem(); |
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642 if (interfering_lrg.mask().Member(r_reg)) { |
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643 interfering_lrg.Remove(r_reg); |
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644 interfering_lrg.set_mask_size(interfering_lrg.mask().is_AllStack() ? LRG::AllStack_size : old_size - 1); |
12071
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645 } |
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646 } |
0 | 647 |
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648 // If 'l' goes completely dry, it must spill. |
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649 if (interfering_lrg.not_free()) { |
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650 // Give 'l' some kind of reasonable mask, so it picks up |
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651 // interferences (and will spill later). |
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652 interfering_lrg.set_mask(old); |
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653 interfering_lrg.set_mask_size(old_size); |
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654 must_spill++; |
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655 interfering_lrg._must_spill = 1; |
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656 interfering_lrg.set_reg(OptoReg::Name(LRG::SPILL_REG)); |
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657 } |
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658 l = elements.next(); |
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659 } |
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660 } |
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661 |
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662 /* |
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663 * Start loop at 1 (skip control edge) for most Nodes. SCMemProj's might be the |
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664 * sole use of a StoreLConditional. While StoreLConditionals set memory (the |
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665 * SCMemProj use) they also def flags; if that flag def is unused the allocator |
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666 * sees a flag-setting instruction with no use of the flags and assumes it's |
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667 * dead. This keeps the (useless) flag-setting behavior alive while also |
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668 * keeping the (useful) memory update effect. |
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669 */ |
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670 void PhaseChaitin::add_input_to_liveout(Block* b, Node* n, IndexSet* liveout, double cost, Pressure& int_pressure, Pressure& float_pressure) { |
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671 JVMState* jvms = n->jvms(); |
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672 uint debug_start = jvms ? jvms->debug_start() : 999999; |
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673 |
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674 for (uint k = ((n->Opcode() == Op_SCMemProj) ? 0:1); k < n->req(); k++) { |
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675 Node* def = n->in(k); |
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676 uint lid = _lrg_map.live_range_id(def); |
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677 if (!lid) { |
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678 continue; |
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679 } |
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680 LRG& lrg = lrgs(lid); |
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681 |
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682 // No use-side cost for spilling debug info |
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683 if (k < debug_start) { |
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684 // A USE costs twice block frequency (once for the Load, once |
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685 // for a Load-delay). Rematerialized uses only cost once. |
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686 lrg._cost += (def->rematerialize() ? b->_freq : (b->_freq * 2)); |
566
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687 } |
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688 |
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689 if (liveout->insert(lid)) { |
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690 // Newly live things assumed live from here to top of block |
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691 lrg._area += cost; |
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692 raise_pressure(b, lrg, int_pressure, float_pressure); |
14496 | 693 assert(int_pressure.current_pressure() == count_int_pressure(liveout), "the int pressure is incorrect"); |
694 assert(float_pressure.current_pressure() == count_float_pressure(liveout), "the float pressure is incorrect"); | |
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695 } |
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696 assert(lrg._area >= 0.0, "negative spill area" ); |
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697 } |
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698 } |
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699 |
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700 /* |
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701 * If we run off the top of the block with high pressure just record that the |
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702 * whole block is high pressure. (Even though we might have a transition |
14496 | 703 * later down in the block) |
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704 */ |
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705 void PhaseChaitin::check_for_high_pressure_block(Pressure& pressure) { |
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706 // current pressure now means the pressure before the first instruction in the block |
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707 // (since we have stepped through all instructions backwards) |
14496 | 708 if (pressure.current_pressure() > pressure.high_pressure_limit()) { |
709 pressure.set_high_pressure_index_to_block_start(); | |
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710 } |
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711 } |
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712 |
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713 /* |
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714 * Compute high pressure indice; avoid landing in the middle of projnodes |
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715 * and set the high pressure index for the block |
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716 */ |
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717 void PhaseChaitin::adjust_high_pressure_index(Block* b, uint& block_hrp_index, Pressure& pressure) { |
14496 | 718 uint i = pressure.high_pressure_index(); |
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719 if (i < b->number_of_nodes() && i < b->end_idx() + 1) { |
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720 Node* cur = b->get_node(i); |
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721 while (cur->is_Proj() || (cur->is_MachNullCheck()) || cur->is_Catch()) { |
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722 cur = b->get_node(--i); |
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723 } |
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724 } |
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725 block_hrp_index = i; |
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726 } |
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727 |
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728 /* Build an interference graph: |
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729 * That is, if 2 live ranges are simultaneously alive but in their acceptable |
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730 * register sets do not overlap, then they do not interfere. The IFG is built |
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731 * by a single reverse pass over each basic block. Starting with the known |
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732 * live-out set, we remove things that get defined and add things that become |
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733 * live (essentially executing one pass of a standard LIVE analysis). Just |
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734 * before a Node defines a value (and removes it from the live-ness set) that |
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735 * value is certainly live. The defined value interferes with everything |
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736 * currently live. The value is then removed from the live-ness set and it's |
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737 * inputs are added to the live-ness set. |
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738 * Compute register pressure for each block: |
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739 * We store the biggest register pressure for each block and also the first |
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740 * low to high register pressure transition within the block (if any). |
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741 */ |
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742 uint PhaseChaitin::build_ifg_physical( ResourceArea *a ) { |
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743 NOT_PRODUCT(Compile::TracePhase t3("buildIFG", &_t_buildIFGphysical, TimeCompiler);) |
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744 |
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745 uint must_spill = 0; |
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746 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
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747 Block* block = _cfg.get_block(i); |
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748 |
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749 // Clone (rather than smash in place) the liveout info, so it is alive |
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750 // for the "collect_gc_info" phase later. |
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751 IndexSet liveout(_live->live(block)); |
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752 |
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753 uint first_inst = first_nonphi_index(block); |
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754 uint last_inst = block->end_idx(); |
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755 |
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756 move_exception_node_up(block, first_inst, last_inst); |
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757 |
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758 Pressure int_pressure(last_inst + 1, INTPRESSURE); |
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759 Pressure float_pressure(last_inst + 1, FLOATPRESSURE); |
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760 block->_reg_pressure = 0; |
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761 block->_freg_pressure = 0; |
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762 |
566
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763 int inst_count = last_inst - first_inst; |
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764 double cost = (inst_count <= 0) ? 0.0 : block->_freq * double(inst_count); |
14499
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765 assert(cost >= 0.0, "negative spill cost" ); |
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766 |
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767 compute_initial_block_pressure(block, &liveout, int_pressure, float_pressure, cost); |
0 | 768 |
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769 for (uint location = last_inst; location > 0; location--) { |
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770 Node* n = block->get_node(location); |
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771 uint lid = _lrg_map.live_range_id(n); |
0 | 772 |
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773 if(lid) { |
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774 LRG& lrg = lrgs(lid); |
0 | 775 |
776 // A DEF normally costs block frequency; rematerialized values are | |
777 // removed from the DEF sight, so LOWER costs here. | |
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778 lrg._cost += n->rematerialize() ? 0 : block->_freq; |
0 | 779 |
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780 if (!liveout.member(lid) && n->Opcode() != Op_SafePoint) { |
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781 if (remove_node_if_not_used(block, location, n, lid, &liveout)) { |
14496 | 782 float_pressure.lower_high_pressure_index(); |
783 int_pressure.lower_high_pressure_index(); | |
0 | 784 continue; |
785 } | |
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786 if (lrg._fat_proj) { |
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787 check_for_high_pressure_transition_at_fatproj(block->_reg_pressure, location, lrg, int_pressure, Op_RegI); |
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788 check_for_high_pressure_transition_at_fatproj(block->_freg_pressure, location, lrg, float_pressure, Op_RegD); |
0 | 789 } |
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790 } else { |
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791 // A live range ends at its definition, remove the remaining area. |
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792 // If the cost is +Inf (which might happen in extreme cases), the lrg area will also be +Inf, |
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793 // and +Inf - +Inf = NaN. So let's not do that subtraction. |
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794 if (g_isfinite(cost)) { |
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795 lrg._area -= cost; |
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796 } |
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797 assert(lrg._area >= 0.0, "negative spill area" ); |
0 | 798 |
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799 assign_high_score_to_immediate_copies(block, n, lrg, location + 1, last_inst); |
0 | 800 |
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801 if (liveout.remove(lid)) { |
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802 lower_pressure(block, location, lrg, &liveout, int_pressure, float_pressure); |
0 | 803 } |
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804 uint copy_idx = n->is_Copy(); |
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805 if (copy_idx) { |
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806 uint lid_copy = _lrg_map.live_range_id(n->in(copy_idx)); |
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807 remove_interference_from_copy(block, location, lid_copy, &liveout, cost, int_pressure, float_pressure); |
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808 } |
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809 } |
0 | 810 |
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811 // Since rematerializable DEFs are not bound but the live range is, |
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812 // some uses must be bound. If we spill live range 'r', it can |
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813 // rematerialize at each use site according to its bindings. |
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814 if (lrg.is_bound() && !n->rematerialize() && lrg.mask().is_NotEmpty()) { |
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815 remove_bound_register_from_interfering_live_ranges(lrg, &liveout, must_spill); |
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816 } |
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817 interfere_with_live(lid, &liveout); |
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818 } |
0 | 819 |
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820 // Area remaining in the block |
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821 inst_count--; |
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822 cost = (inst_count <= 0) ? 0.0 : block->_freq * double(inst_count); |
0 | 823 |
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824 if (!n->is_Phi()) { |
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825 add_input_to_liveout(block, n, &liveout, cost, int_pressure, float_pressure); |
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826 } |
0 | 827 } |
828 | |
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829 check_for_high_pressure_block(int_pressure); |
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830 check_for_high_pressure_block(float_pressure); |
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831 adjust_high_pressure_index(block, block->_ihrp_index, int_pressure); |
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832 adjust_high_pressure_index(block, block->_fhrp_index, float_pressure); |
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833 // set the final_pressure as the register pressure for the block |
14496 | 834 block->_reg_pressure = int_pressure.final_pressure(); |
835 block->_freg_pressure = float_pressure.final_pressure(); | |
0 | 836 |
837 #ifndef PRODUCT | |
838 // Gather Register Pressure Statistics | |
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839 if (PrintOptoStatistics) { |
14496 | 840 if (block->_reg_pressure > int_pressure.high_pressure_limit() || block->_freg_pressure > float_pressure.high_pressure_limit()) { |
0 | 841 _high_pressure++; |
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842 } else { |
0 | 843 _low_pressure++; |
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844 } |
0 | 845 } |
846 #endif | |
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847 } |
0 | 848 |
849 return must_spill; | |
850 } |