graal-compiler: src/share/vm/opto/ifg.cpp annotate

annotate src/share/vm/opto/ifg.cpp @ 14496:99fc8c086679

8032894: Remove dead code in Pressure::lower Summary: Remove dead code in Pressure::lower Reviewed-by: kvn, roland

author	adlertz
date	Tue, 25 Feb 2014 10:26:21 +0100
parents	c84312468f5c
children	1077c8270209

rev	line source
0 a61af66fc99e Initial load duke parents: diff changeset	1 /*
14223 de6a9e811145 8029233: Update copyright year to match last edit in jdk8 hotspot repository for 2013 mikael parents: 12877 diff changeset	2 * Copyright (c) 1998, 2013, Oracle and/or its affiliates. All rights reserved.
0 a61af66fc99e Initial load duke parents: diff changeset	3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
a61af66fc99e Initial load duke parents: diff changeset	4 *
a61af66fc99e Initial load duke parents: diff changeset	5 * This code is free software; you can redistribute it and/or modify it
a61af66fc99e Initial load duke parents: diff changeset	6 * under the terms of the GNU General Public License version 2 only, as
a61af66fc99e Initial load duke parents: diff changeset	7 * published by the Free Software Foundation.
a61af66fc99e Initial load duke parents: diff changeset	8 *
a61af66fc99e Initial load duke parents: diff changeset	9 * This code is distributed in the hope that it will be useful, but WITHOUT
a61af66fc99e Initial load duke parents: diff changeset	10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
a61af66fc99e Initial load duke parents: diff changeset	11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
a61af66fc99e Initial load duke parents: diff changeset	12 * version 2 for more details (a copy is included in the LICENSE file that
a61af66fc99e Initial load duke parents: diff changeset	13 * accompanied this code).
a61af66fc99e Initial load duke parents: diff changeset	14 *
a61af66fc99e Initial load duke parents: diff changeset	15 * You should have received a copy of the GNU General Public License version
a61af66fc99e Initial load duke parents: diff changeset	16 * 2 along with this work; if not, write to the Free Software Foundation,
a61af66fc99e Initial load duke parents: diff changeset	17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
a61af66fc99e Initial load duke parents: diff changeset	18 *
1552 c18cbe5936b8 6941466: Oracle rebranding changes for Hotspot repositories trims parents: 1212 diff changeset	19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
c18cbe5936b8 6941466: Oracle rebranding changes for Hotspot repositories trims parents: 1212 diff changeset	20 * or visit www.oracle.com if you need additional information or have any
c18cbe5936b8 6941466: Oracle rebranding changes for Hotspot repositories trims parents: 1212 diff changeset	21 * questions.
0 a61af66fc99e Initial load duke parents: diff changeset	22 *
a61af66fc99e Initial load duke parents: diff changeset	23 */
a61af66fc99e Initial load duke parents: diff changeset	24
1972 f95d63e2154a 6989984: Use standard include model for Hospot stefank parents: 1552 diff changeset	25 #include "precompiled.hpp"
f95d63e2154a 6989984: Use standard include model for Hospot stefank parents: 1552 diff changeset	26 #include "compiler/oopMap.hpp"
f95d63e2154a 6989984: Use standard include model for Hospot stefank parents: 1552 diff changeset	27 #include "memory/allocation.inline.hpp"
f95d63e2154a 6989984: Use standard include model for Hospot stefank parents: 1552 diff changeset	28 #include "opto/addnode.hpp"
f95d63e2154a 6989984: Use standard include model for Hospot stefank parents: 1552 diff changeset	29 #include "opto/block.hpp"
f95d63e2154a 6989984: Use standard include model for Hospot stefank parents: 1552 diff changeset	30 #include "opto/callnode.hpp"
f95d63e2154a 6989984: Use standard include model for Hospot stefank parents: 1552 diff changeset	31 #include "opto/cfgnode.hpp"
f95d63e2154a 6989984: Use standard include model for Hospot stefank parents: 1552 diff changeset	32 #include "opto/chaitin.hpp"
f95d63e2154a 6989984: Use standard include model for Hospot stefank parents: 1552 diff changeset	33 #include "opto/coalesce.hpp"
f95d63e2154a 6989984: Use standard include model for Hospot stefank parents: 1552 diff changeset	34 #include "opto/connode.hpp"
f95d63e2154a 6989984: Use standard include model for Hospot stefank parents: 1552 diff changeset	35 #include "opto/indexSet.hpp"
f95d63e2154a 6989984: Use standard include model for Hospot stefank parents: 1552 diff changeset	36 #include "opto/machnode.hpp"
f95d63e2154a 6989984: Use standard include model for Hospot stefank parents: 1552 diff changeset	37 #include "opto/memnode.hpp"
f95d63e2154a 6989984: Use standard include model for Hospot stefank parents: 1552 diff changeset	38 #include "opto/opcodes.hpp"
0 a61af66fc99e Initial load duke parents: diff changeset	39
a61af66fc99e Initial load duke parents: diff changeset	40 PhaseIFG::PhaseIFG( Arena *arena ) : Phase(Interference_Graph), _arena(arena) {
a61af66fc99e Initial load duke parents: diff changeset	41 }
a61af66fc99e Initial load duke parents: diff changeset	42
a61af66fc99e Initial load duke parents: diff changeset	43 void PhaseIFG::init( uint maxlrg ) {
a61af66fc99e Initial load duke parents: diff changeset	44 _maxlrg = maxlrg;
a61af66fc99e Initial load duke parents: diff changeset	45 _yanked = new (_arena) VectorSet(_arena);
a61af66fc99e Initial load duke parents: diff changeset	46 _is_square = false;
a61af66fc99e Initial load duke parents: diff changeset	47 // Make uninitialized adjacency lists
a61af66fc99e Initial load duke parents: diff changeset	48 _adjs = (IndexSet)_arena->Amalloc(sizeof(IndexSet)maxlrg);
a61af66fc99e Initial load duke parents: diff changeset	49 // Also make empty live range structures
a61af66fc99e Initial load duke parents: diff changeset	50 _lrgs = (LRG )_arena->Amalloc( maxlrg sizeof(LRG) );
a61af66fc99e Initial load duke parents: diff changeset	51 memset(_lrgs,0,sizeof(LRG)*maxlrg);
a61af66fc99e Initial load duke parents: diff changeset	52 // Init all to empty
a61af66fc99e Initial load duke parents: diff changeset	53 for( uint i = 0; i < maxlrg; i++ ) {
a61af66fc99e Initial load duke parents: diff changeset	54 _adjs[i].initialize(maxlrg);
a61af66fc99e Initial load duke parents: diff changeset	55 _lrgs[i].Set_All();
a61af66fc99e Initial load duke parents: diff changeset	56 }
a61af66fc99e Initial load duke parents: diff changeset	57 }
a61af66fc99e Initial load duke parents: diff changeset	58
a61af66fc99e Initial load duke parents: diff changeset	59 // Add edge between vertices a & b. These are sorted (triangular matrix),
a61af66fc99e Initial load duke parents: diff changeset	60 // then the smaller number is inserted in the larger numbered array.
a61af66fc99e Initial load duke parents: diff changeset	61 int PhaseIFG::add_edge( uint a, uint b ) {
a61af66fc99e Initial load duke parents: diff changeset	62 lrgs(a).invalid_degree();
a61af66fc99e Initial load duke parents: diff changeset	63 lrgs(b).invalid_degree();
a61af66fc99e Initial load duke parents: diff changeset	64 // Sort a and b, so that a is bigger
a61af66fc99e Initial load duke parents: diff changeset	65 assert( !_is_square, "only on triangular" );
a61af66fc99e Initial load duke parents: diff changeset	66 if( a < b ) { uint tmp = a; a = b; b = tmp; }
a61af66fc99e Initial load duke parents: diff changeset	67 return _adjs[a].insert( b );
a61af66fc99e Initial load duke parents: diff changeset	68 }
a61af66fc99e Initial load duke parents: diff changeset	69
a61af66fc99e Initial load duke parents: diff changeset	70 // Add an edge between 'a' and everything in the vector.
a61af66fc99e Initial load duke parents: diff changeset	71 void PhaseIFG::add_vector( uint a, IndexSet *vec ) {
a61af66fc99e Initial load duke parents: diff changeset	72 // IFG is triangular, so do the inserts where 'a' < 'b'.
a61af66fc99e Initial load duke parents: diff changeset	73 assert( !_is_square, "only on triangular" );
a61af66fc99e Initial load duke parents: diff changeset	74 IndexSet *adjs_a = &_adjs[a];
a61af66fc99e Initial load duke parents: diff changeset	75 if( !vec->count() ) return;
a61af66fc99e Initial load duke parents: diff changeset	76
a61af66fc99e Initial load duke parents: diff changeset	77 IndexSetIterator elements(vec);
a61af66fc99e Initial load duke parents: diff changeset	78 uint neighbor;
a61af66fc99e Initial load duke parents: diff changeset	79 while ((neighbor = elements.next()) != 0) {
a61af66fc99e Initial load duke parents: diff changeset	80 add_edge( a, neighbor );
a61af66fc99e Initial load duke parents: diff changeset	81 }
a61af66fc99e Initial load duke parents: diff changeset	82 }
a61af66fc99e Initial load duke parents: diff changeset	83
a61af66fc99e Initial load duke parents: diff changeset	84 // Is there an edge between a and b?
a61af66fc99e Initial load duke parents: diff changeset	85 int PhaseIFG::test_edge( uint a, uint b ) const {
a61af66fc99e Initial load duke parents: diff changeset	86 // Sort a and b, so that a is larger
a61af66fc99e Initial load duke parents: diff changeset	87 assert( !_is_square, "only on triangular" );
a61af66fc99e Initial load duke parents: diff changeset	88 if( a < b ) { uint tmp = a; a = b; b = tmp; }
a61af66fc99e Initial load duke parents: diff changeset	89 return _adjs[a].member(b);
a61af66fc99e Initial load duke parents: diff changeset	90 }
a61af66fc99e Initial load duke parents: diff changeset	91
a61af66fc99e Initial load duke parents: diff changeset	92 // Convert triangular matrix to square matrix
a61af66fc99e Initial load duke parents: diff changeset	93 void PhaseIFG::SquareUp() {
a61af66fc99e Initial load duke parents: diff changeset	94 assert( !_is_square, "only on triangular" );
a61af66fc99e Initial load duke parents: diff changeset	95
a61af66fc99e Initial load duke parents: diff changeset	96 // Simple transpose
a61af66fc99e Initial load duke parents: diff changeset	97 for( uint i = 0; i < _maxlrg; i++ ) {
a61af66fc99e Initial load duke parents: diff changeset	98 IndexSetIterator elements(&_adjs[i]);
a61af66fc99e Initial load duke parents: diff changeset	99 uint datum;
a61af66fc99e Initial load duke parents: diff changeset	100 while ((datum = elements.next()) != 0) {
a61af66fc99e Initial load duke parents: diff changeset	101 _adjs[datum].insert( i );
a61af66fc99e Initial load duke parents: diff changeset	102 }
a61af66fc99e Initial load duke parents: diff changeset	103 }
a61af66fc99e Initial load duke parents: diff changeset	104 _is_square = true;
a61af66fc99e Initial load duke parents: diff changeset	105 }
a61af66fc99e Initial load duke parents: diff changeset	106
a61af66fc99e Initial load duke parents: diff changeset	107 // Compute effective degree in bulk
a61af66fc99e Initial load duke parents: diff changeset	108 void PhaseIFG::Compute_Effective_Degree() {
a61af66fc99e Initial load duke parents: diff changeset	109 assert( _is_square, "only on square" );
a61af66fc99e Initial load duke parents: diff changeset	110
a61af66fc99e Initial load duke parents: diff changeset	111 for( uint i = 0; i < _maxlrg; i++ )
a61af66fc99e Initial load duke parents: diff changeset	112 lrgs(i).set_degree(effective_degree(i));
a61af66fc99e Initial load duke parents: diff changeset	113 }
a61af66fc99e Initial load duke parents: diff changeset	114
a61af66fc99e Initial load duke parents: diff changeset	115 int PhaseIFG::test_edge_sq( uint a, uint b ) const {
a61af66fc99e Initial load duke parents: diff changeset	116 assert( _is_square, "only on square" );
a61af66fc99e Initial load duke parents: diff changeset	117 // Swap, so that 'a' has the lesser count. Then binary search is on
a61af66fc99e Initial load duke parents: diff changeset	118 // the smaller of a's list and b's list.
a61af66fc99e Initial load duke parents: diff changeset	119 if( neighbor_cnt(a) > neighbor_cnt(b) ) { uint tmp = a; a = b; b = tmp; }
a61af66fc99e Initial load duke parents: diff changeset	120 //return _adjs[a].unordered_member(b);
a61af66fc99e Initial load duke parents: diff changeset	121 return _adjs[a].member(b);
a61af66fc99e Initial load duke parents: diff changeset	122 }
a61af66fc99e Initial load duke parents: diff changeset	123
a61af66fc99e Initial load duke parents: diff changeset	124 // Union edges of B into A
a61af66fc99e Initial load duke parents: diff changeset	125 void PhaseIFG::Union( uint a, uint b ) {
a61af66fc99e Initial load duke parents: diff changeset	126 assert( _is_square, "only on square" );
a61af66fc99e Initial load duke parents: diff changeset	127 IndexSet *A = &_adjs[a];
a61af66fc99e Initial load duke parents: diff changeset	128 IndexSetIterator b_elements(&_adjs[b]);
a61af66fc99e Initial load duke parents: diff changeset	129 uint datum;
a61af66fc99e Initial load duke parents: diff changeset	130 while ((datum = b_elements.next()) != 0) {
a61af66fc99e Initial load duke parents: diff changeset	131 if(A->insert(datum)) {
a61af66fc99e Initial load duke parents: diff changeset	132 _adjs[datum].insert(a);
a61af66fc99e Initial load duke parents: diff changeset	133 lrgs(a).invalid_degree();
a61af66fc99e Initial load duke parents: diff changeset	134 lrgs(datum).invalid_degree();
a61af66fc99e Initial load duke parents: diff changeset	135 }
a61af66fc99e Initial load duke parents: diff changeset	136 }
a61af66fc99e Initial load duke parents: diff changeset	137 }
a61af66fc99e Initial load duke parents: diff changeset	138
a61af66fc99e Initial load duke parents: diff changeset	139 // Yank a Node and all connected edges from the IFG. Return a
a61af66fc99e Initial load duke parents: diff changeset	140 // list of neighbors (edges) yanked.
a61af66fc99e Initial load duke parents: diff changeset	141 IndexSet *PhaseIFG::remove_node( uint a ) {
a61af66fc99e Initial load duke parents: diff changeset	142 assert( _is_square, "only on square" );
a61af66fc99e Initial load duke parents: diff changeset	143 assert( !_yanked->test(a), "" );
a61af66fc99e Initial load duke parents: diff changeset	144 _yanked->set(a);
a61af66fc99e Initial load duke parents: diff changeset	145
a61af66fc99e Initial load duke parents: diff changeset	146 // I remove the LRG from all neighbors.
a61af66fc99e Initial load duke parents: diff changeset	147 IndexSetIterator elements(&_adjs[a]);
a61af66fc99e Initial load duke parents: diff changeset	148 LRG &lrg_a = lrgs(a);
a61af66fc99e Initial load duke parents: diff changeset	149 uint datum;
a61af66fc99e Initial load duke parents: diff changeset	150 while ((datum = elements.next()) != 0) {
a61af66fc99e Initial load duke parents: diff changeset	151 _adjs[datum].remove(a);
a61af66fc99e Initial load duke parents: diff changeset	152 lrgs(datum).inc_degree( -lrg_a.compute_degree(lrgs(datum)) );
a61af66fc99e Initial load duke parents: diff changeset	153 }
a61af66fc99e Initial load duke parents: diff changeset	154 return neighbors(a);
a61af66fc99e Initial load duke parents: diff changeset	155 }
a61af66fc99e Initial load duke parents: diff changeset	156
a61af66fc99e Initial load duke parents: diff changeset	157 // Re-insert a yanked Node.
a61af66fc99e Initial load duke parents: diff changeset	158 void PhaseIFG::re_insert( uint a ) {
a61af66fc99e Initial load duke parents: diff changeset	159 assert( _is_square, "only on square" );
a61af66fc99e Initial load duke parents: diff changeset	160 assert( _yanked->test(a), "" );
a61af66fc99e Initial load duke parents: diff changeset	161 (*_yanked) >>= a;
a61af66fc99e Initial load duke parents: diff changeset	162
a61af66fc99e Initial load duke parents: diff changeset	163 IndexSetIterator elements(&_adjs[a]);
a61af66fc99e Initial load duke parents: diff changeset	164 uint datum;
a61af66fc99e Initial load duke parents: diff changeset	165 while ((datum = elements.next()) != 0) {
a61af66fc99e Initial load duke parents: diff changeset	166 _adjs[datum].insert(a);
a61af66fc99e Initial load duke parents: diff changeset	167 lrgs(datum).invalid_degree();
a61af66fc99e Initial load duke parents: diff changeset	168 }
a61af66fc99e Initial load duke parents: diff changeset	169 }
a61af66fc99e Initial load duke parents: diff changeset	170
a61af66fc99e Initial load duke parents: diff changeset	171 // Compute the degree between 2 live ranges. If both live ranges are
a61af66fc99e Initial load duke parents: diff changeset	172 // aligned-adjacent powers-of-2 then we use the MAX size. If either is
a61af66fc99e Initial load duke parents: diff changeset	173 // mis-aligned (or for Fat-Projections, not-adjacent) then we have to
a61af66fc99e Initial load duke parents: diff changeset	174 // MULTIPLY the sizes. Inspect Brigg's thesis on register pairs to see why
a61af66fc99e Initial load duke parents: diff changeset	175 // this is so.
a61af66fc99e Initial load duke parents: diff changeset	176 int LRG::compute_degree( LRG &l ) const {
a61af66fc99e Initial load duke parents: diff changeset	177 int tmp;
a61af66fc99e Initial load duke parents: diff changeset	178 int num_regs = _num_regs;
a61af66fc99e Initial load duke parents: diff changeset	179 int nregs = l.num_regs();
a61af66fc99e Initial load duke parents: diff changeset	180 tmp = (_fat_proj \|\| l._fat_proj) // either is a fat-proj?
a61af66fc99e Initial load duke parents: diff changeset	181 ? (num_regs * nregs) // then use product
a61af66fc99e Initial load duke parents: diff changeset	182 : MAX2(num_regs,nregs); // else use max
a61af66fc99e Initial load duke parents: diff changeset	183 return tmp;
a61af66fc99e Initial load duke parents: diff changeset	184 }
a61af66fc99e Initial load duke parents: diff changeset	185
a61af66fc99e Initial load duke parents: diff changeset	186 // Compute effective degree for this live range. If both live ranges are
a61af66fc99e Initial load duke parents: diff changeset	187 // aligned-adjacent powers-of-2 then we use the MAX size. If either is
a61af66fc99e Initial load duke parents: diff changeset	188 // mis-aligned (or for Fat-Projections, not-adjacent) then we have to
a61af66fc99e Initial load duke parents: diff changeset	189 // MULTIPLY the sizes. Inspect Brigg's thesis on register pairs to see why
a61af66fc99e Initial load duke parents: diff changeset	190 // this is so.
a61af66fc99e Initial load duke parents: diff changeset	191 int PhaseIFG::effective_degree( uint lidx ) const {
a61af66fc99e Initial load duke parents: diff changeset	192 int eff = 0;
a61af66fc99e Initial load duke parents: diff changeset	193 int num_regs = lrgs(lidx).num_regs();
a61af66fc99e Initial load duke parents: diff changeset	194 int fat_proj = lrgs(lidx)._fat_proj;
a61af66fc99e Initial load duke parents: diff changeset	195 IndexSet *s = neighbors(lidx);
a61af66fc99e Initial load duke parents: diff changeset	196 IndexSetIterator elements(s);
a61af66fc99e Initial load duke parents: diff changeset	197 uint nidx;
a61af66fc99e Initial load duke parents: diff changeset	198 while((nidx = elements.next()) != 0) {
a61af66fc99e Initial load duke parents: diff changeset	199 LRG &lrgn = lrgs(nidx);
a61af66fc99e Initial load duke parents: diff changeset	200 int nregs = lrgn.num_regs();
a61af66fc99e Initial load duke parents: diff changeset	201 eff += (fat_proj \|\| lrgn._fat_proj) // either is a fat-proj?
a61af66fc99e Initial load duke parents: diff changeset	202 ? (num_regs * nregs) // then use product
a61af66fc99e Initial load duke parents: diff changeset	203 : MAX2(num_regs,nregs); // else use max
a61af66fc99e Initial load duke parents: diff changeset	204 }
a61af66fc99e Initial load duke parents: diff changeset	205 return eff;
a61af66fc99e Initial load duke parents: diff changeset	206 }
a61af66fc99e Initial load duke parents: diff changeset	207
a61af66fc99e Initial load duke parents: diff changeset	208
a61af66fc99e Initial load duke parents: diff changeset	209 #ifndef PRODUCT
a61af66fc99e Initial load duke parents: diff changeset	210 void PhaseIFG::dump() const {
a61af66fc99e Initial load duke parents: diff changeset	211 tty->print_cr("-- Interference Graph --%s--",
a61af66fc99e Initial load duke parents: diff changeset	212 _is_square ? "square" : "triangular" );
a61af66fc99e Initial load duke parents: diff changeset	213 if( _is_square ) {
a61af66fc99e Initial load duke parents: diff changeset	214 for( uint i = 0; i < _maxlrg; i++ ) {
a61af66fc99e Initial load duke parents: diff changeset	215 tty->print( (*_yanked)[i] ? "XX " : " ");
a61af66fc99e Initial load duke parents: diff changeset	216 tty->print("L%d: { ",i);
a61af66fc99e Initial load duke parents: diff changeset	217 IndexSetIterator elements(&_adjs[i]);
a61af66fc99e Initial load duke parents: diff changeset	218 uint datum;
a61af66fc99e Initial load duke parents: diff changeset	219 while ((datum = elements.next()) != 0) {
a61af66fc99e Initial load duke parents: diff changeset	220 tty->print("L%d ", datum);
a61af66fc99e Initial load duke parents: diff changeset	221 }
a61af66fc99e Initial load duke parents: diff changeset	222 tty->print_cr("}");
a61af66fc99e Initial load duke parents: diff changeset	223
a61af66fc99e Initial load duke parents: diff changeset	224 }
a61af66fc99e Initial load duke parents: diff changeset	225 return;
a61af66fc99e Initial load duke parents: diff changeset	226 }
a61af66fc99e Initial load duke parents: diff changeset	227
a61af66fc99e Initial load duke parents: diff changeset	228 // Triangular
a61af66fc99e Initial load duke parents: diff changeset	229 for( uint i = 0; i < _maxlrg; i++ ) {
a61af66fc99e Initial load duke parents: diff changeset	230 uint j;
a61af66fc99e Initial load duke parents: diff changeset	231 tty->print( (*_yanked)[i] ? "XX " : " ");
a61af66fc99e Initial load duke parents: diff changeset	232 tty->print("L%d: { ",i);
a61af66fc99e Initial load duke parents: diff changeset	233 for( j = _maxlrg; j > i; j-- )
a61af66fc99e Initial load duke parents: diff changeset	234 if( test_edge(j - 1,i) ) {
a61af66fc99e Initial load duke parents: diff changeset	235 tty->print("L%d ",j - 1);
a61af66fc99e Initial load duke parents: diff changeset	236 }
a61af66fc99e Initial load duke parents: diff changeset	237 tty->print("\| ");
a61af66fc99e Initial load duke parents: diff changeset	238 IndexSetIterator elements(&_adjs[i]);
a61af66fc99e Initial load duke parents: diff changeset	239 uint datum;
a61af66fc99e Initial load duke parents: diff changeset	240 while ((datum = elements.next()) != 0) {
a61af66fc99e Initial load duke parents: diff changeset	241 tty->print("L%d ", datum);
a61af66fc99e Initial load duke parents: diff changeset	242 }
a61af66fc99e Initial load duke parents: diff changeset	243 tty->print("}\n");
a61af66fc99e Initial load duke parents: diff changeset	244 }
a61af66fc99e Initial load duke parents: diff changeset	245 tty->print("\n");
a61af66fc99e Initial load duke parents: diff changeset	246 }
a61af66fc99e Initial load duke parents: diff changeset	247
a61af66fc99e Initial load duke parents: diff changeset	248 void PhaseIFG::stats() const {
a61af66fc99e Initial load duke parents: diff changeset	249 ResourceMark rm;
a61af66fc99e Initial load duke parents: diff changeset	250 int h_cnt = NEW_RESOURCE_ARRAY(int,_maxlrg2);
a61af66fc99e Initial load duke parents: diff changeset	251 memset( h_cnt, 0, sizeof(int)_maxlrg2 );
a61af66fc99e Initial load duke parents: diff changeset	252 uint i;
a61af66fc99e Initial load duke parents: diff changeset	253 for( i = 0; i < _maxlrg; i++ ) {
a61af66fc99e Initial load duke parents: diff changeset	254 h_cnt[neighbor_cnt(i)]++;
a61af66fc99e Initial load duke parents: diff changeset	255 }
a61af66fc99e Initial load duke parents: diff changeset	256 tty->print_cr("--Histogram of counts--");
a61af66fc99e Initial load duke parents: diff changeset	257 for( i = 0; i < _maxlrg*2; i++ )
a61af66fc99e Initial load duke parents: diff changeset	258 if( h_cnt[i] )
a61af66fc99e Initial load duke parents: diff changeset	259 tty->print("%d/%d ",i,h_cnt[i]);
a61af66fc99e Initial load duke parents: diff changeset	260 tty->print_cr("");
a61af66fc99e Initial load duke parents: diff changeset	261 }
a61af66fc99e Initial load duke parents: diff changeset	262
a61af66fc99e Initial load duke parents: diff changeset	263 void PhaseIFG::verify( const PhaseChaitin *pc ) const {
a61af66fc99e Initial load duke parents: diff changeset	264 // IFG is square, sorted and no need for Find
a61af66fc99e Initial load duke parents: diff changeset	265 for( uint i = 0; i < _maxlrg; i++ ) {
a61af66fc99e Initial load duke parents: diff changeset	266 assert(!((*_yanked)[i]) \|\| !neighbor_cnt(i), "Is removed completely" );
a61af66fc99e Initial load duke parents: diff changeset	267 IndexSet *set = &_adjs[i];
a61af66fc99e Initial load duke parents: diff changeset	268 IndexSetIterator elements(set);
a61af66fc99e Initial load duke parents: diff changeset	269 uint idx;
a61af66fc99e Initial load duke parents: diff changeset	270 uint last = 0;
a61af66fc99e Initial load duke parents: diff changeset	271 while ((idx = elements.next()) != 0) {
10111 8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 8867 diff changeset	272 assert(idx != i, "Must have empty diagonal");
8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 8867 diff changeset	273 assert(pc->_lrg_map.find_const(idx) == idx, "Must not need Find");
8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 8867 diff changeset	274 assert(_adjs[idx].member(i), "IFG not square");
8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 8867 diff changeset	275 assert(!(*_yanked)[idx], "No yanked neighbors");
8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 8867 diff changeset	276 assert(last < idx, "not sorted increasing");
0 a61af66fc99e Initial load duke parents: diff changeset	277 last = idx;
a61af66fc99e Initial load duke parents: diff changeset	278 }
10111 8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 8867 diff changeset	279 assert(!lrgs(i)._degree_valid \|\| effective_degree(i) == lrgs(i).degree(), "degree is valid but wrong");
0 a61af66fc99e Initial load duke parents: diff changeset	280 }
a61af66fc99e Initial load duke parents: diff changeset	281 }
a61af66fc99e Initial load duke parents: diff changeset	282 #endif
a61af66fc99e Initial load duke parents: diff changeset	283
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	284 /*
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	285 * Interfere this register with everything currently live.
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	286 * Check for interference by checking overlap of regmasks.
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	287 * Only interfere if acceptable register masks overlap.
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	288 */
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	289 void PhaseChaitin::interfere_with_live(uint lid, IndexSet* liveout) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	290 LRG& lrg = lrgs(lid);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	291 const RegMask& rm = lrg.mask();
0 a61af66fc99e Initial load duke parents: diff changeset	292 IndexSetIterator elements(liveout);
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	293 uint interfering_lid = elements.next();
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	294 while (interfering_lid != 0) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	295 LRG& interfering_lrg = lrgs(interfering_lid);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	296 if (rm.overlap(interfering_lrg.mask())) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	297 _ifg->add_edge(lid, interfering_lid);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	298 }
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	299 interfering_lid = elements.next();
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	300 }
0 a61af66fc99e Initial load duke parents: diff changeset	301 }
a61af66fc99e Initial load duke parents: diff changeset	302
a61af66fc99e Initial load duke parents: diff changeset	303 // Actually build the interference graph. Uses virtual registers only, no
a61af66fc99e Initial load duke parents: diff changeset	304 // physical register masks. This allows me to be very aggressive when
a61af66fc99e Initial load duke parents: diff changeset	305 // coalescing copies. Some of this aggressiveness will have to be undone
a61af66fc99e Initial load duke parents: diff changeset	306 // later, but I'd rather get all the copies I can now (since unremoved copies
a61af66fc99e Initial load duke parents: diff changeset	307 // at this point can end up in bad places). Copies I re-insert later I have
a61af66fc99e Initial load duke parents: diff changeset	308 // more opportunity to insert them in low-frequency locations.
a61af66fc99e Initial load duke parents: diff changeset	309 void PhaseChaitin::build_ifg_virtual( ) {
a61af66fc99e Initial load duke parents: diff changeset	310
a61af66fc99e Initial load duke parents: diff changeset	311 // For all blocks (in any order) do...
12071 adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG adlertz parents: 12023 diff changeset	312 for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG adlertz parents: 12023 diff changeset	313 Block* block = _cfg.get_block(i);
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG adlertz parents: 12023 diff changeset	314 IndexSet* liveout = _live->live(block);
0 a61af66fc99e Initial load duke parents: diff changeset	315
a61af66fc99e Initial load duke parents: diff changeset	316 // The IFG is built by a single reverse pass over each basic block.
a61af66fc99e Initial load duke parents: diff changeset	317 // Starting with the known live-out set, we remove things that get
a61af66fc99e Initial load duke parents: diff changeset	318 // defined and add things that become live (essentially executing one
a61af66fc99e Initial load duke parents: diff changeset	319 // pass of a standard LIVE analysis). Just before a Node defines a value
a61af66fc99e Initial load duke parents: diff changeset	320 // (and removes it from the live-ness set) that value is certainly live.
a61af66fc99e Initial load duke parents: diff changeset	321 // The defined value interferes with everything currently live. The
a61af66fc99e Initial load duke parents: diff changeset	322 // value is then removed from the live-ness set and it's inputs are
a61af66fc99e Initial load duke parents: diff changeset	323 // added to the live-ness set.
12071 adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG adlertz parents: 12023 diff changeset	324 for (uint j = block->end_idx() + 1; j > 1; j--) {
12167 650868c062a9 8023691: Create interface for nodes in class Block adlertz parents: 12071 diff changeset	325 Node* n = block->get_node(j - 1);
0 a61af66fc99e Initial load duke parents: diff changeset	326
a61af66fc99e Initial load duke parents: diff changeset	327 // Get value being defined
10111 8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 8867 diff changeset	328 uint r = _lrg_map.live_range_id(n);
0 a61af66fc99e Initial load duke parents: diff changeset	329
a61af66fc99e Initial load duke parents: diff changeset	330 // Some special values do not allocate
10111 8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 8867 diff changeset	331 if (r) {
0 a61af66fc99e Initial load duke parents: diff changeset	332
a61af66fc99e Initial load duke parents: diff changeset	333 // Remove from live-out set
a61af66fc99e Initial load duke parents: diff changeset	334 liveout->remove(r);
a61af66fc99e Initial load duke parents: diff changeset	335
a61af66fc99e Initial load duke parents: diff changeset	336 // Copies do not define a new value and so do not interfere.
a61af66fc99e Initial load duke parents: diff changeset	337 // Remove the copies source from the liveout set before interfering.
a61af66fc99e Initial load duke parents: diff changeset	338 uint idx = n->is_Copy();
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	339 if (idx != 0) {
10111 8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 8867 diff changeset	340 liveout->remove(_lrg_map.live_range_id(n->in(idx)));
8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 8867 diff changeset	341 }
0 a61af66fc99e Initial load duke parents: diff changeset	342
a61af66fc99e Initial load duke parents: diff changeset	343 // Interfere with everything live
10111 8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 8867 diff changeset	344 interfere_with_live(r, liveout);
0 a61af66fc99e Initial load duke parents: diff changeset	345 }
a61af66fc99e Initial load duke parents: diff changeset	346
a61af66fc99e Initial load duke parents: diff changeset	347 // Make all inputs live
10111 8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 8867 diff changeset	348 if (!n->is_Phi()) { // Phi function uses come from prior block
8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 8867 diff changeset	349 for(uint k = 1; k < n->req(); k++) {
8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 8867 diff changeset	350 liveout->insert(_lrg_map.live_range_id(n->in(k)));
8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 8867 diff changeset	351 }
0 a61af66fc99e Initial load duke parents: diff changeset	352 }
a61af66fc99e Initial load duke parents: diff changeset	353
a61af66fc99e Initial load duke parents: diff changeset	354 // 2-address instructions always have the defined value live
a61af66fc99e Initial load duke parents: diff changeset	355 // on entry to the instruction, even though it is being defined
a61af66fc99e Initial load duke parents: diff changeset	356 // by the instruction. We pretend a virtual copy sits just prior
a61af66fc99e Initial load duke parents: diff changeset	357 // to the instruction and kills the src-def'd register.
a61af66fc99e Initial load duke parents: diff changeset	358 // In other words, for 2-address instructions the defined value
a61af66fc99e Initial load duke parents: diff changeset	359 // interferes with all inputs.
a61af66fc99e Initial load duke parents: diff changeset	360 uint idx;
a61af66fc99e Initial load duke parents: diff changeset	361 if( n->is_Mach() && (idx = n->as_Mach()->two_adr()) ) {
a61af66fc99e Initial load duke parents: diff changeset	362 const MachNode *mach = n->as_Mach();
a61af66fc99e Initial load duke parents: diff changeset	363 // Sometimes my 2-address ADDs are commuted in a bad way.
a61af66fc99e Initial load duke parents: diff changeset	364 // We generally want the USE-DEF register to refer to the
a61af66fc99e Initial load duke parents: diff changeset	365 // loop-varying quantity, to avoid a copy.
a61af66fc99e Initial load duke parents: diff changeset	366 uint op = mach->ideal_Opcode();
a61af66fc99e Initial load duke parents: diff changeset	367 // Check that mach->num_opnds() == 3 to ensure instruction is
a61af66fc99e Initial load duke parents: diff changeset	368 // not subsuming constants, effectively excludes addI_cin_imm
a61af66fc99e Initial load duke parents: diff changeset	369 // Can NOT swap for instructions like addI_cin_imm since it
a61af66fc99e Initial load duke parents: diff changeset	370 // is adding zero to yhi + carry and the second ideal-input
a61af66fc99e Initial load duke parents: diff changeset	371 // points to the result of adding low-halves.
a61af66fc99e Initial load duke parents: diff changeset	372 // Checking req() and num_opnds() does NOT distinguish addI_cout from addI_cout_imm
a61af66fc99e Initial load duke parents: diff changeset	373 if( (op == Op_AddI && mach->req() == 3 && mach->num_opnds() == 3) &&
a61af66fc99e Initial load duke parents: diff changeset	374 n->in(1)->bottom_type()->base() == Type::Int &&
a61af66fc99e Initial load duke parents: diff changeset	375 // See if the ADD is involved in a tight data loop the wrong way
a61af66fc99e Initial load duke parents: diff changeset	376 n->in(2)->is_Phi() &&
a61af66fc99e Initial load duke parents: diff changeset	377 n->in(2)->in(2) == n ) {
a61af66fc99e Initial load duke parents: diff changeset	378 Node *tmp = n->in(1);
a61af66fc99e Initial load duke parents: diff changeset	379 n->set_req( 1, n->in(2) );
a61af66fc99e Initial load duke parents: diff changeset	380 n->set_req( 2, tmp );
a61af66fc99e Initial load duke parents: diff changeset	381 }
a61af66fc99e Initial load duke parents: diff changeset	382 // Defined value interferes with all inputs
10111 8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 8867 diff changeset	383 uint lidx = _lrg_map.live_range_id(n->in(idx));
8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 8867 diff changeset	384 for (uint k = 1; k < n->req(); k++) {
8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 8867 diff changeset	385 uint kidx = _lrg_map.live_range_id(n->in(k));
8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 8867 diff changeset	386 if (kidx != lidx) {
8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 8867 diff changeset	387 _ifg->add_edge(r, kidx);
8373c19be854 8011621: live_ranges_in_separate_class.patch neliasso parents: 8867 diff changeset	388 }
0 a61af66fc99e Initial load duke parents: diff changeset	389 }
a61af66fc99e Initial load duke parents: diff changeset	390 }
a61af66fc99e Initial load duke parents: diff changeset	391 } // End of forall instructions in block
a61af66fc99e Initial load duke parents: diff changeset	392 } // End of forall blocks
a61af66fc99e Initial load duke parents: diff changeset	393 }
a61af66fc99e Initial load duke parents: diff changeset	394
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	395 #ifdef ASSERT
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	396 uint PhaseChaitin::count_int_pressure(IndexSet* liveout) {
0 a61af66fc99e Initial load duke parents: diff changeset	397 IndexSetIterator elements(liveout);
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	398 uint lidx = elements.next();
0 a61af66fc99e Initial load duke parents: diff changeset	399 uint cnt = 0;
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	400 while (lidx != 0) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	401 LRG& lrg = lrgs(lidx);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	402 if (lrg.mask_is_nonempty_and_up() &&
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	403 !lrg.is_float_or_vector() &&
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	404 lrg.mask().overlap(*Matcher::idealreg2regmask[Op_RegI])) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	405 cnt += lrg.reg_pressure();
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	406 }
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	407 lidx = elements.next();
0 a61af66fc99e Initial load duke parents: diff changeset	408 }
a61af66fc99e Initial load duke parents: diff changeset	409 return cnt;
a61af66fc99e Initial load duke parents: diff changeset	410 }
a61af66fc99e Initial load duke parents: diff changeset	411
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	412 uint PhaseChaitin::count_float_pressure(IndexSet* liveout) {
0 a61af66fc99e Initial load duke parents: diff changeset	413 IndexSetIterator elements(liveout);
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	414 uint lidx = elements.next();
0 a61af66fc99e Initial load duke parents: diff changeset	415 uint cnt = 0;
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	416 while (lidx != 0) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	417 LRG& lrg = lrgs(lidx);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	418 if (lrg.mask_is_nonempty_and_up() && lrg.is_float_or_vector()) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	419 cnt += lrg.reg_pressure();
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	420 }
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	421 lidx = elements.next();
0 a61af66fc99e Initial load duke parents: diff changeset	422 }
a61af66fc99e Initial load duke parents: diff changeset	423 return cnt;
a61af66fc99e Initial load duke parents: diff changeset	424 }
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	425 #endif
0 a61af66fc99e Initial load duke parents: diff changeset	426
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	427 /*
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	428 * Adjust register pressure down by 1. Capture last hi-to-low transition,
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	429 */
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	430 void PhaseChaitin::lower_pressure(Block* b, uint location, LRG& lrg, IndexSet* liveout, Pressure& int_pressure, Pressure& float_pressure) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	431 if (lrg.mask_is_nonempty_and_up()) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	432 if (lrg.is_float_or_vector()) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	433 float_pressure.lower(lrg, location);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	434 } else {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	435 // Do not count the SP and flag registers
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	436 const RegMask& r = lrg.mask();
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	437 if (r.overlap(*Matcher::idealreg2regmask[Op_RegI])) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	438 int_pressure.lower(lrg, location);
0 a61af66fc99e Initial load duke parents: diff changeset	439 }
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	440 }
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	441 }
14496 99fc8c086679 8032894: Remove dead code in Pressure::lower adlertz parents: 14388 diff changeset	442 assert(int_pressure.current_pressure() == count_int_pressure(liveout), "the int pressure is incorrect");
99fc8c086679 8032894: Remove dead code in Pressure::lower adlertz parents: 14388 diff changeset	443 assert(float_pressure.current_pressure() == count_float_pressure(liveout), "the float pressure is incorrect");
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	444 }
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	445
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	446 /* Go to the first non-phi index in a block */
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	447 static uint first_nonphi_index(Block* b) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	448 uint i;
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	449 uint end_idx = b->end_idx();
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	450 for (i = 1; i < end_idx; i++) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	451 Node* n = b->get_node(i);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	452 if (!n->is_Phi()) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	453 break;
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	454 }
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	455 }
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	456 return i;
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	457 }
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	458
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	459 /*
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	460 * Spills could be inserted before a CreateEx node which should be the first
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	461 * instruction in a block after Phi nodes. If so, move the CreateEx node up.
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	462 */
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	463 static void move_exception_node_up(Block* b, uint first_inst, uint last_inst) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	464 for (uint i = first_inst; i < last_inst; i++) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	465 Node* ex = b->get_node(i);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	466 if (ex->is_SpillCopy()) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	467 continue;
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	468 }
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	469
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	470 if (i > first_inst &&
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	471 ex->is_Mach() && ex->as_Mach()->ideal_Opcode() == Op_CreateEx) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	472 b->remove_node(i);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	473 b->insert_node(ex, first_inst);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	474 }
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	475 // Stop once a CreateEx or any other node is found
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	476 break;
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	477 }
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	478 }
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	479
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	480 /*
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	481 * When new live ranges are live, we raise the register pressure
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	482 */
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	483 void PhaseChaitin::raise_pressure(Block* b, LRG& lrg, Pressure& int_pressure, Pressure& float_pressure) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	484 if (lrg.mask_is_nonempty_and_up()) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	485 if (lrg.is_float_or_vector()) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	486 float_pressure.raise(lrg);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	487 } else {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	488 // Do not count the SP and flag registers
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	489 const RegMask& rm = lrg.mask();
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	490 if (rm.overlap(*Matcher::idealreg2regmask[Op_RegI])) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	491 int_pressure.raise(lrg);
0 a61af66fc99e Initial load duke parents: diff changeset	492 }
a61af66fc99e Initial load duke parents: diff changeset	493 }
a61af66fc99e Initial load duke parents: diff changeset	494 }
a61af66fc99e Initial load duke parents: diff changeset	495 }
a61af66fc99e Initial load duke parents: diff changeset	496
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	497
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	498 /*
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	499 * Computes the initial register pressure of a block, looking at all live
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	500 * ranges in the liveout. The register pressure is computed for both float
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	501 * and int/pointer registers.
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	502 * Live ranges in the liveout are presumed live for the whole block.
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	503 * We add the cost for the whole block to the area of the live ranges initially.
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	504 * If a live range gets killed in the block, we'll subtract the unused part of
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	505 * the block from the area.
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	506 */
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	507 void PhaseChaitin::compute_initial_block_pressure(Block* b, IndexSet* liveout, Pressure& int_pressure, Pressure& float_pressure, double cost) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	508 IndexSetIterator elements(liveout);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	509 uint lid = elements.next();
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	510 while (lid != 0) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	511 LRG& lrg = lrgs(lid);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	512 lrg._area += cost;
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	513 raise_pressure(b, lrg, int_pressure, float_pressure);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	514 lid = elements.next();
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	515 }
14496 99fc8c086679 8032894: Remove dead code in Pressure::lower adlertz parents: 14388 diff changeset	516 assert(int_pressure.current_pressure() == count_int_pressure(liveout), "the int pressure is incorrect");
99fc8c086679 8032894: Remove dead code in Pressure::lower adlertz parents: 14388 diff changeset	517 assert(float_pressure.current_pressure() == count_float_pressure(liveout), "the float pressure is incorrect");
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	518 }
0 a61af66fc99e Initial load duke parents: diff changeset	519
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	520 /*
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	521 * Remove dead node if it's not used.
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	522 * We only remove projection nodes if the node "defining" the projection is
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	523 * dead, for example on x86, if we have a dead Add node we remove its
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	524 * RFLAGS node.
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	525 */
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	526 bool PhaseChaitin::remove_node_if_not_used(Block* b, uint location, Node* n, uint lid, IndexSet* liveout) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	527 Node* def = n->in(0);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	528 if (!n->is_Proj() \|\|
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	529 (_lrg_map.live_range_id(def) && !liveout->member(_lrg_map.live_range_id(def)))) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	530 b->remove_node(location);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	531 LRG& lrg = lrgs(lid);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	532 if (lrg._def == n) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	533 lrg._def = 0;
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	534 }
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	535 n->disconnect_inputs(NULL, C);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	536 _cfg.unmap_node_from_block(n);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	537 n->replace_by(C->top());
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	538 return true;
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	539 }
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	540 return false;
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	541 }
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	542
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	543 /*
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	544 * When encountering a fat projection, we might go from a low to high to low
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	545 * (since the fat proj only lives at this instruction) going backwards in the
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	546 * block. If we find a low to high transition, we record it.
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	547 */
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	548 void PhaseChaitin::check_for_high_pressure_transition_at_fatproj(uint& block_reg_pressure, uint location, LRG& lrg, Pressure& pressure, const int op_regtype) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	549 RegMask mask_tmp = lrg.mask();
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	550 mask_tmp.AND(*Matcher::idealreg2regmask[op_regtype]);
14496 99fc8c086679 8032894: Remove dead code in Pressure::lower adlertz parents: 14388 diff changeset	551 pressure.check_pressure_at_fatproj(location, mask_tmp);
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	552 }
0 a61af66fc99e Initial load duke parents: diff changeset	553
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	554 /*
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	555 * Insure high score for immediate-use spill copies so they get a color.
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	556 * All single-use MachSpillCopy(s) that immediately precede their
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	557 * use must color early. If a longer live range steals their
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	558 * color, the spill copy will split and may push another spill copy
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	559 * further away resulting in an infinite spill-split-retry cycle.
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	560 * Assigning a zero area results in a high score() and a good
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	561 * location in the simplify list.
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	562 */
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	563 void PhaseChaitin::assign_high_score_to_immediate_copies(Block* b, Node* n, LRG& lrg, uint next_inst, uint last_inst) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	564 if (n->is_SpillCopy() &&
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	565 lrg.is_singledef() && // A multi defined live range can still split
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	566 n->outcnt() == 1 && // and use must be in this block
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	567 _cfg.get_block_for_node(n->unique_out()) == b) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	568
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	569 Node* single_use = n->unique_out();
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	570 assert(b->find_node(single_use) >= next_inst, "Use must be later in block");
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	571 // Use can be earlier in block if it is a Phi, but then I should be a MultiDef
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	572
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	573 // Find first non SpillCopy 'm' that follows the current instruction
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	574 // (current_inst - 1) is index for current instruction 'n'
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	575 Node* m = n;
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	576 for (uint i = next_inst; i <= last_inst && m->is_SpillCopy(); ++i) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	577 m = b->get_node(i);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	578 }
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	579 if (m == single_use) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	580 lrg._area = 0.0;
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	581 }
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	582 }
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	583 }
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	584
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	585 /*
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	586 * Copies do not define a new value and so do not interfere.
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	587 * Remove the copies source from the liveout set before interfering.
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	588 */
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	589 void PhaseChaitin::remove_interference_from_copy(Block* b, uint location, uint lid_copy, IndexSet* liveout, double cost, Pressure& int_pressure, Pressure& float_pressure) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	590 if (liveout->remove(lid_copy)) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	591 LRG& lrg_copy = lrgs(lid_copy);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	592 lrg_copy._area -= cost;
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	593
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	594 // Lower register pressure since copy and definition can share the same register
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	595 lower_pressure(b, location, lrg_copy, liveout, int_pressure, float_pressure);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	596 }
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	597 }
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	598
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	599 /*
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	600 * The defined value must go in a particular register. Remove that register from
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	601 * all conflicting parties and avoid the interference.
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	602 */
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	603 void PhaseChaitin::remove_bound_register_from_interfering_live_ranges(LRG& lrg, IndexSet* liveout, uint& must_spill) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	604 // Check for common case
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	605 const RegMask& rm = lrg.mask();
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	606 int r_size = lrg.num_regs();
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	607 // Smear odd bits
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	608 IndexSetIterator elements(liveout);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	609 uint l = elements.next();
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	610 while (l != 0) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	611 LRG& interfering_lrg = lrgs(l);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	612 // If 'l' must spill already, do not further hack his bits.
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	613 // He'll get some interferences and be forced to spill later.
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	614 if (interfering_lrg._must_spill) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	615 l = elements.next();
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	616 continue;
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	617 }
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	618
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	619 // Remove bound register(s) from 'l's choices
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	620 RegMask old = interfering_lrg.mask();
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	621 uint old_size = interfering_lrg.mask_size();
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	622
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	623 // Remove the bits from LRG 'rm' from LRG 'l' so 'l' no
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	624 // longer interferes with 'rm'. If 'l' requires aligned
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	625 // adjacent pairs, subtract out bit pairs.
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	626 assert(!interfering_lrg._is_vector \|\| !interfering_lrg._fat_proj, "sanity");
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	627
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	628 if (interfering_lrg.num_regs() > 1 && !interfering_lrg._fat_proj) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	629 RegMask r2mask = rm;
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	630 // Leave only aligned set of bits.
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	631 r2mask.smear_to_sets(interfering_lrg.num_regs());
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	632 // It includes vector case.
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	633 interfering_lrg.SUBTRACT(r2mask);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	634 interfering_lrg.compute_set_mask_size();
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	635 } else if (r_size != 1) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	636 // fat proj
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	637 interfering_lrg.SUBTRACT(rm);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	638 interfering_lrg.compute_set_mask_size();
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	639 } else {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	640 // Common case: size 1 bound removal
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	641 OptoReg::Name r_reg = rm.find_first_elem();
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	642 if (interfering_lrg.mask().Member(r_reg)) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	643 interfering_lrg.Remove(r_reg);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	644 interfering_lrg.set_mask_size(interfering_lrg.mask().is_AllStack() ? LRG::AllStack_size : old_size - 1);
12071 adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG adlertz parents: 12023 diff changeset	645 }
adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG adlertz parents: 12023 diff changeset	646 }
0 a61af66fc99e Initial load duke parents: diff changeset	647
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	648 // If 'l' goes completely dry, it must spill.
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	649 if (interfering_lrg.not_free()) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	650 // Give 'l' some kind of reasonable mask, so it picks up
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	651 // interferences (and will spill later).
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	652 interfering_lrg.set_mask(old);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	653 interfering_lrg.set_mask_size(old_size);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	654 must_spill++;
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	655 interfering_lrg._must_spill = 1;
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	656 interfering_lrg.set_reg(OptoReg::Name(LRG::SPILL_REG));
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	657 }
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	658 l = elements.next();
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	659 }
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	660 }
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	661
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	662 /*
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	663 * Start loop at 1 (skip control edge) for most Nodes. SCMemProj's might be the
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	664 * sole use of a StoreLConditional. While StoreLConditionals set memory (the
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	665 * SCMemProj use) they also def flags; if that flag def is unused the allocator
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	666 * sees a flag-setting instruction with no use of the flags and assumes it's
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	667 * dead. This keeps the (useless) flag-setting behavior alive while also
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	668 * keeping the (useful) memory update effect.
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	669 */
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	670 void PhaseChaitin::add_input_to_liveout(Block* b, Node* n, IndexSet* liveout, double cost, Pressure& int_pressure, Pressure& float_pressure) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	671 JVMState* jvms = n->jvms();
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	672 uint debug_start = jvms ? jvms->debug_start() : 999999;
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	673
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	674 for (uint k = ((n->Opcode() == Op_SCMemProj) ? 0:1); k < n->req(); k++) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	675 Node* def = n->in(k);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	676 uint lid = _lrg_map.live_range_id(def);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	677 if (!lid) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	678 continue;
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	679 }
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	680 LRG& lrg = lrgs(lid);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	681
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	682 // No use-side cost for spilling debug info
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	683 if (k < debug_start) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	684 // A USE costs twice block frequency (once for the Load, once
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	685 // for a Load-delay). Rematerialized uses only cost once.
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	686 lrg._cost += (def->rematerialize() ? b->_freq : (b->_freq * 2));
566 91263420e1c6 6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly") kvn parents: 380 diff changeset	687 }
91263420e1c6 6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly") kvn parents: 380 diff changeset	688
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	689 if (liveout->insert(lid)) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	690 // Newly live things assumed live from here to top of block
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	691 lrg._area += cost;
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	692 raise_pressure(b, lrg, int_pressure, float_pressure);
14496 99fc8c086679 8032894: Remove dead code in Pressure::lower adlertz parents: 14388 diff changeset	693 assert(int_pressure.current_pressure() == count_int_pressure(liveout), "the int pressure is incorrect");
99fc8c086679 8032894: Remove dead code in Pressure::lower adlertz parents: 14388 diff changeset	694 assert(float_pressure.current_pressure() == count_float_pressure(liveout), "the float pressure is incorrect");
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	695 }
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	696 assert(!(lrg._area < 0.0), "negative spill area" );
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	697 }
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	698 }
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	699
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	700 /*
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	701 * If we run off the top of the block with high pressure just record that the
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	702 * whole block is high pressure. (Even though we might have a transition
14496 99fc8c086679 8032894: Remove dead code in Pressure::lower adlertz parents: 14388 diff changeset	703 * later down in the block)
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	704 */
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	705 void PhaseChaitin::check_for_high_pressure_block(Pressure& pressure) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	706 // current pressure now means the pressure before the first instruction in the block
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	707 // (since we have stepped through all instructions backwards)
14496 99fc8c086679 8032894: Remove dead code in Pressure::lower adlertz parents: 14388 diff changeset	708 if (pressure.current_pressure() > pressure.high_pressure_limit()) {
99fc8c086679 8032894: Remove dead code in Pressure::lower adlertz parents: 14388 diff changeset	709 pressure.set_high_pressure_index_to_block_start();
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	710 }
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	711 }
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	712
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	713 /*
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	714 * Compute high pressure indice; avoid landing in the middle of projnodes
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	715 * and set the high pressure index for the block
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	716 */
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	717 void PhaseChaitin::adjust_high_pressure_index(Block* b, uint& block_hrp_index, Pressure& pressure) {
14496 99fc8c086679 8032894: Remove dead code in Pressure::lower adlertz parents: 14388 diff changeset	718 uint i = pressure.high_pressure_index();
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	719 if (i < b->number_of_nodes() && i < b->end_idx() + 1) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	720 Node* cur = b->get_node(i);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	721 while (cur->is_Proj() \|\| (cur->is_MachNullCheck()) \|\| cur->is_Catch()) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	722 cur = b->get_node(--i);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	723 }
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	724 }
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	725 block_hrp_index = i;
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	726 }
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	727
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	728 /* Build an interference graph:
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	729 * That is, if 2 live ranges are simultaneously alive but in their acceptable
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	730 * register sets do not overlap, then they do not interfere. The IFG is built
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	731 * by a single reverse pass over each basic block. Starting with the known
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	732 * live-out set, we remove things that get defined and add things that become
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	733 * live (essentially executing one pass of a standard LIVE analysis). Just
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	734 * before a Node defines a value (and removes it from the live-ness set) that
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	735 * value is certainly live. The defined value interferes with everything
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	736 * currently live. The value is then removed from the live-ness set and it's
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	737 * inputs are added to the live-ness set.
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	738 * Compute register pressure for each block:
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	739 * We store the biggest register pressure for each block and also the first
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	740 * low to high register pressure transition within the block (if any).
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	741 */
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	742 uint PhaseChaitin::build_ifg_physical( ResourceArea *a ) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	743 NOT_PRODUCT(Compile::TracePhase t3("buildIFG", &_t_buildIFGphysical, TimeCompiler);)
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	744
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	745 uint must_spill = 0;
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	746 for (uint i = 0; i < _cfg.number_of_blocks(); i++) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	747 Block* block = _cfg.get_block(i);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	748
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	749 // Clone (rather than smash in place) the liveout info, so it is alive
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	750 // for the "collect_gc_info" phase later.
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	751 IndexSet liveout(_live->live(block));
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	752
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	753 uint first_inst = first_nonphi_index(block);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	754 uint last_inst = block->end_idx();
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	755
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	756 move_exception_node_up(block, first_inst, last_inst);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	757
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	758 Pressure int_pressure(last_inst + 1, INTPRESSURE);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	759 Pressure float_pressure(last_inst + 1, FLOATPRESSURE);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	760 block->_reg_pressure = 0;
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	761 block->_freg_pressure = 0;
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	762
566 91263420e1c6 6791852: assert(b->_nodes[insidx] == n,"got insidx set incorrectly") kvn parents: 380 diff changeset	763 int inst_count = last_inst - first_inst;
12071 adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG adlertz parents: 12023 diff changeset	764 double cost = (inst_count <= 0) ? 0.0 : block->_freq * double(inst_count);
369 5f85534046c2 6750588: assert(lrg._area >= 0,"negative spill area") running NSK stmp0101 test rasbold parents: 295 diff changeset	765 assert(!(cost < 0.0), "negative spill cost" );
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	766
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	767 compute_initial_block_pressure(block, &liveout, int_pressure, float_pressure, cost);
0 a61af66fc99e Initial load duke parents: diff changeset	768
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	769 for (uint location = last_inst; location > 0; location--) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	770 Node* n = block->get_node(location);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	771 uint lid = _lrg_map.live_range_id(n);
0 a61af66fc99e Initial load duke parents: diff changeset	772
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	773 if(lid) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	774 LRG& lrg = lrgs(lid);
0 a61af66fc99e Initial load duke parents: diff changeset	775
a61af66fc99e Initial load duke parents: diff changeset	776 // A DEF normally costs block frequency; rematerialized values are
a61af66fc99e Initial load duke parents: diff changeset	777 // removed from the DEF sight, so LOWER costs here.
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	778 lrg._cost += n->rematerialize() ? 0 : block->_freq;
0 a61af66fc99e Initial load duke parents: diff changeset	779
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	780 if (!liveout.member(lid) && n->Opcode() != Op_SafePoint) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	781 if (remove_node_if_not_used(block, location, n, lid, &liveout)) {
14496 99fc8c086679 8032894: Remove dead code in Pressure::lower adlertz parents: 14388 diff changeset	782 float_pressure.lower_high_pressure_index();
99fc8c086679 8032894: Remove dead code in Pressure::lower adlertz parents: 14388 diff changeset	783 int_pressure.lower_high_pressure_index();
0 a61af66fc99e Initial load duke parents: diff changeset	784 continue;
a61af66fc99e Initial load duke parents: diff changeset	785 }
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	786 if (lrg._fat_proj) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	787 check_for_high_pressure_transition_at_fatproj(block->_reg_pressure, location, lrg, int_pressure, Op_RegI);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	788 check_for_high_pressure_transition_at_fatproj(block->_freg_pressure, location, lrg, float_pressure, Op_RegD);
0 a61af66fc99e Initial load duke parents: diff changeset	789 }
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	790 } else {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	791 // A live range ends at its definition, remove the remaining area.
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	792 lrg._area -= cost;
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	793 assert(lrg._area >= 0.0, "negative spill area" );
0 a61af66fc99e Initial load duke parents: diff changeset	794
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	795 assign_high_score_to_immediate_copies(block, n, lrg, location + 1, last_inst);
0 a61af66fc99e Initial load duke parents: diff changeset	796
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	797 if (liveout.remove(lid)) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	798 lower_pressure(block, location, lrg, &liveout, int_pressure, float_pressure);
0 a61af66fc99e Initial load duke parents: diff changeset	799 }
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	800 uint copy_idx = n->is_Copy();
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	801 if (copy_idx) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	802 uint lid_copy = _lrg_map.live_range_id(n->in(copy_idx));
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	803 remove_interference_from_copy(block, location, lid_copy, &liveout, cost, int_pressure, float_pressure);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	804 }
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	805 }
0 a61af66fc99e Initial load duke parents: diff changeset	806
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	807 // Since rematerializable DEFs are not bound but the live range is,
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	808 // some uses must be bound. If we spill live range 'r', it can
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	809 // rematerialize at each use site according to its bindings.
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	810 if (lrg.is_bound() && !n->rematerialize() && lrg.mask().is_NotEmpty()) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	811 remove_bound_register_from_interfering_live_ranges(lrg, &liveout, must_spill);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	812 }
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	813 interfere_with_live(lid, &liveout);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	814 }
0 a61af66fc99e Initial load duke parents: diff changeset	815
369 5f85534046c2 6750588: assert(lrg._area >= 0,"negative spill area") running NSK stmp0101 test rasbold parents: 295 diff changeset	816 // Area remaining in the block
5f85534046c2 6750588: assert(lrg._area >= 0,"negative spill area") running NSK stmp0101 test rasbold parents: 295 diff changeset	817 inst_count--;
12071 adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG adlertz parents: 12023 diff changeset	818 cost = (inst_count <= 0) ? 0.0 : block->_freq * double(inst_count);
0 a61af66fc99e Initial load duke parents: diff changeset	819
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	820 if (!n->is_Phi()) {
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	821 add_input_to_liveout(block, n, &liveout, cost, int_pressure, float_pressure);
12071 adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG adlertz parents: 12023 diff changeset	822 }
0 a61af66fc99e Initial load duke parents: diff changeset	823 }
a61af66fc99e Initial load duke parents: diff changeset	824
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	825 check_for_high_pressure_block(int_pressure);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	826 check_for_high_pressure_block(float_pressure);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	827 adjust_high_pressure_index(block, block->_ihrp_index, int_pressure);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	828 adjust_high_pressure_index(block, block->_fhrp_index, float_pressure);
c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	829 // set the final_pressure as the register pressure for the block
14496 99fc8c086679 8032894: Remove dead code in Pressure::lower adlertz parents: 14388 diff changeset	830 block->_reg_pressure = int_pressure.final_pressure();
99fc8c086679 8032894: Remove dead code in Pressure::lower adlertz parents: 14388 diff changeset	831 block->_freg_pressure = float_pressure.final_pressure();
0 a61af66fc99e Initial load duke parents: diff changeset	832
a61af66fc99e Initial load duke parents: diff changeset	833 #ifndef PRODUCT
a61af66fc99e Initial load duke parents: diff changeset	834 // Gather Register Pressure Statistics
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	835 if (PrintOptoStatistics) {
14496 99fc8c086679 8032894: Remove dead code in Pressure::lower adlertz parents: 14388 diff changeset	836 if (block->_reg_pressure > int_pressure.high_pressure_limit() \|\| block->_freg_pressure > float_pressure.high_pressure_limit()) {
0 a61af66fc99e Initial load duke parents: diff changeset	837 _high_pressure++;
12071 adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG adlertz parents: 12023 diff changeset	838 } else {
0 a61af66fc99e Initial load duke parents: diff changeset	839 _low_pressure++;
12071 adb9a7d94cb5 8023003: Cleanup the public interface to PhaseCFG adlertz parents: 12023 diff changeset	840 }
0 a61af66fc99e Initial load duke parents: diff changeset	841 }
a61af66fc99e Initial load duke parents: diff changeset	842 #endif
14388 c84312468f5c 8031498: Cleanup and re-factorize PhaseChaitin::build_ifg_physical adlertz parents: 14223 diff changeset	843 }
0 a61af66fc99e Initial load duke parents: diff changeset	844
a61af66fc99e Initial load duke parents: diff changeset	845 return must_spill;
a61af66fc99e Initial load duke parents: diff changeset	846 }

Mercurial > hg > graal-compiler

annotate src/share/vm/opto/ifg.cpp @ 14496:99fc8c086679