Mercurial > hg > graal-compiler
annotate src/cpu/x86/vm/c1_LIRAssembler_x86.cpp @ 13994:989f58d6a0ca
Truffle: Added API for Node.getKind().
author | Christian Humer <christian.humer@gmail.com> |
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date | Fri, 21 Feb 2014 02:24:03 +0100 |
parents | 9acbfe04b5c3 |
children | 9bcf7b329013 |
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0 | 1 /* |
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2 * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #include "precompiled.hpp" |
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26 #include "asm/macroAssembler.hpp" |
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27 #include "asm/macroAssembler.inline.hpp" |
1972 | 28 #include "c1/c1_Compilation.hpp" |
29 #include "c1/c1_LIRAssembler.hpp" | |
30 #include "c1/c1_MacroAssembler.hpp" | |
31 #include "c1/c1_Runtime1.hpp" | |
32 #include "c1/c1_ValueStack.hpp" | |
33 #include "ci/ciArrayKlass.hpp" | |
34 #include "ci/ciInstance.hpp" | |
35 #include "gc_interface/collectedHeap.hpp" | |
36 #include "memory/barrierSet.hpp" | |
37 #include "memory/cardTableModRefBS.hpp" | |
38 #include "nativeInst_x86.hpp" | |
39 #include "oops/objArrayKlass.hpp" | |
40 #include "runtime/sharedRuntime.hpp" | |
0 | 41 |
42 | |
43 // These masks are used to provide 128-bit aligned bitmasks to the XMM | |
44 // instructions, to allow sign-masking or sign-bit flipping. They allow | |
45 // fast versions of NegF/NegD and AbsF/AbsD. | |
46 | |
47 // Note: 'double' and 'long long' have 32-bits alignment on x86. | |
48 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { | |
49 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address | |
50 // of 128-bits operands for SSE instructions. | |
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51 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF))); |
0 | 52 // Store the value to a 128-bits operand. |
53 operand[0] = lo; | |
54 operand[1] = hi; | |
55 return operand; | |
56 } | |
57 | |
58 // Buffer for 128-bits masks used by SSE instructions. | |
59 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) | |
60 | |
61 // Static initialization during VM startup. | |
62 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); | |
63 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); | |
64 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); | |
65 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); | |
66 | |
67 | |
68 | |
69 NEEDS_CLEANUP // remove this definitions ? | |
70 const Register IC_Klass = rax; // where the IC klass is cached | |
71 const Register SYNC_header = rax; // synchronization header | |
72 const Register SHIFT_count = rcx; // where count for shift operations must be | |
73 | |
74 #define __ _masm-> | |
75 | |
76 | |
77 static void select_different_registers(Register preserve, | |
78 Register extra, | |
79 Register &tmp1, | |
80 Register &tmp2) { | |
81 if (tmp1 == preserve) { | |
82 assert_different_registers(tmp1, tmp2, extra); | |
83 tmp1 = extra; | |
84 } else if (tmp2 == preserve) { | |
85 assert_different_registers(tmp1, tmp2, extra); | |
86 tmp2 = extra; | |
87 } | |
88 assert_different_registers(preserve, tmp1, tmp2); | |
89 } | |
90 | |
91 | |
92 | |
93 static void select_different_registers(Register preserve, | |
94 Register extra, | |
95 Register &tmp1, | |
96 Register &tmp2, | |
97 Register &tmp3) { | |
98 if (tmp1 == preserve) { | |
99 assert_different_registers(tmp1, tmp2, tmp3, extra); | |
100 tmp1 = extra; | |
101 } else if (tmp2 == preserve) { | |
102 assert_different_registers(tmp1, tmp2, tmp3, extra); | |
103 tmp2 = extra; | |
104 } else if (tmp3 == preserve) { | |
105 assert_different_registers(tmp1, tmp2, tmp3, extra); | |
106 tmp3 = extra; | |
107 } | |
108 assert_different_registers(preserve, tmp1, tmp2, tmp3); | |
109 } | |
110 | |
111 | |
112 | |
113 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { | |
114 if (opr->is_constant()) { | |
115 LIR_Const* constant = opr->as_constant_ptr(); | |
116 switch (constant->type()) { | |
117 case T_INT: { | |
118 return true; | |
119 } | |
120 | |
121 default: | |
122 return false; | |
123 } | |
124 } | |
125 return false; | |
126 } | |
127 | |
128 | |
129 LIR_Opr LIR_Assembler::receiverOpr() { | |
304 | 130 return FrameMap::receiver_opr; |
0 | 131 } |
132 | |
133 LIR_Opr LIR_Assembler::osrBufferPointer() { | |
304 | 134 return FrameMap::as_pointer_opr(receiverOpr()->as_register()); |
0 | 135 } |
136 | |
137 //--------------fpu register translations----------------------- | |
138 | |
139 | |
140 address LIR_Assembler::float_constant(float f) { | |
141 address const_addr = __ float_constant(f); | |
142 if (const_addr == NULL) { | |
143 bailout("const section overflow"); | |
144 return __ code()->consts()->start(); | |
145 } else { | |
146 return const_addr; | |
147 } | |
148 } | |
149 | |
150 | |
151 address LIR_Assembler::double_constant(double d) { | |
152 address const_addr = __ double_constant(d); | |
153 if (const_addr == NULL) { | |
154 bailout("const section overflow"); | |
155 return __ code()->consts()->start(); | |
156 } else { | |
157 return const_addr; | |
158 } | |
159 } | |
160 | |
161 | |
162 void LIR_Assembler::set_24bit_FPU() { | |
163 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
164 } | |
165 | |
166 void LIR_Assembler::reset_FPU() { | |
167 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
168 } | |
169 | |
170 void LIR_Assembler::fpop() { | |
171 __ fpop(); | |
172 } | |
173 | |
174 void LIR_Assembler::fxch(int i) { | |
175 __ fxch(i); | |
176 } | |
177 | |
178 void LIR_Assembler::fld(int i) { | |
179 __ fld_s(i); | |
180 } | |
181 | |
182 void LIR_Assembler::ffree(int i) { | |
183 __ ffree(i); | |
184 } | |
185 | |
186 void LIR_Assembler::breakpoint() { | |
187 __ int3(); | |
188 } | |
189 | |
190 void LIR_Assembler::push(LIR_Opr opr) { | |
191 if (opr->is_single_cpu()) { | |
192 __ push_reg(opr->as_register()); | |
193 } else if (opr->is_double_cpu()) { | |
304 | 194 NOT_LP64(__ push_reg(opr->as_register_hi())); |
0 | 195 __ push_reg(opr->as_register_lo()); |
196 } else if (opr->is_stack()) { | |
197 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix())); | |
198 } else if (opr->is_constant()) { | |
199 LIR_Const* const_opr = opr->as_constant_ptr(); | |
200 if (const_opr->type() == T_OBJECT) { | |
201 __ push_oop(const_opr->as_jobject()); | |
202 } else if (const_opr->type() == T_INT) { | |
203 __ push_jint(const_opr->as_jint()); | |
204 } else { | |
205 ShouldNotReachHere(); | |
206 } | |
207 | |
208 } else { | |
209 ShouldNotReachHere(); | |
210 } | |
211 } | |
212 | |
213 void LIR_Assembler::pop(LIR_Opr opr) { | |
214 if (opr->is_single_cpu()) { | |
304 | 215 __ pop_reg(opr->as_register()); |
0 | 216 } else { |
217 ShouldNotReachHere(); | |
218 } | |
219 } | |
220 | |
304 | 221 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { |
222 return addr->base()->is_illegal() && addr->index()->is_illegal(); | |
223 } | |
224 | |
0 | 225 //------------------------------------------- |
304 | 226 |
0 | 227 Address LIR_Assembler::as_Address(LIR_Address* addr) { |
304 | 228 return as_Address(addr, rscratch1); |
229 } | |
230 | |
231 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) { | |
0 | 232 if (addr->base()->is_illegal()) { |
233 assert(addr->index()->is_illegal(), "must be illegal too"); | |
304 | 234 AddressLiteral laddr((address)addr->disp(), relocInfo::none); |
235 if (! __ reachable(laddr)) { | |
236 __ movptr(tmp, laddr.addr()); | |
237 Address res(tmp, 0); | |
238 return res; | |
239 } else { | |
240 return __ as_Address(laddr); | |
241 } | |
0 | 242 } |
243 | |
304 | 244 Register base = addr->base()->as_pointer_register(); |
0 | 245 |
246 if (addr->index()->is_illegal()) { | |
247 return Address( base, addr->disp()); | |
304 | 248 } else if (addr->index()->is_cpu_register()) { |
249 Register index = addr->index()->as_pointer_register(); | |
0 | 250 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp()); |
251 } else if (addr->index()->is_constant()) { | |
304 | 252 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp(); |
253 assert(Assembler::is_simm32(addr_offset), "must be"); | |
0 | 254 |
255 return Address(base, addr_offset); | |
256 } else { | |
257 Unimplemented(); | |
258 return Address(); | |
259 } | |
260 } | |
261 | |
262 | |
263 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { | |
264 Address base = as_Address(addr); | |
265 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord); | |
266 } | |
267 | |
268 | |
269 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { | |
270 return as_Address(addr); | |
271 } | |
272 | |
273 | |
274 void LIR_Assembler::osr_entry() { | |
275 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); | |
276 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); | |
277 ValueStack* entry_state = osr_entry->state(); | |
278 int number_of_locks = entry_state->locks_size(); | |
279 | |
280 // we jump here if osr happens with the interpreter | |
281 // state set up to continue at the beginning of the | |
282 // loop that triggered osr - in particular, we have | |
283 // the following registers setup: | |
284 // | |
285 // rcx: osr buffer | |
286 // | |
287 | |
288 // build frame | |
289 ciMethod* m = compilation()->method(); | |
290 __ build_frame(initial_frame_size_in_bytes()); | |
291 | |
292 // OSR buffer is | |
293 // | |
294 // locals[nlocals-1..0] | |
295 // monitors[0..number_of_locks] | |
296 // | |
297 // locals is a direct copy of the interpreter frame so in the osr buffer | |
298 // so first slot in the local array is the last local from the interpreter | |
299 // and last slot is local[0] (receiver) from the interpreter | |
300 // | |
301 // Similarly with locks. The first lock slot in the osr buffer is the nth lock | |
302 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock | |
303 // in the interpreter frame (the method lock if a sync method) | |
304 | |
305 // Initialize monitors in the compiled activation. | |
306 // rcx: pointer to osr buffer | |
307 // | |
308 // All other registers are dead at this point and the locals will be | |
309 // copied into place by code emitted in the IR. | |
310 | |
304 | 311 Register OSR_buf = osrBufferPointer()->as_pointer_register(); |
0 | 312 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); |
313 int monitor_offset = BytesPerWord * method()->max_locals() + | |
1060 | 314 (2 * BytesPerWord) * (number_of_locks - 1); |
315 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in | |
316 // the OSR buffer using 2 word entries: first the lock and then | |
317 // the oop. | |
0 | 318 for (int i = 0; i < number_of_locks; i++) { |
1060 | 319 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); |
0 | 320 #ifdef ASSERT |
321 // verify the interpreter's monitor has a non-null object | |
322 { | |
323 Label L; | |
1060 | 324 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD); |
0 | 325 __ jcc(Assembler::notZero, L); |
326 __ stop("locked object is NULL"); | |
327 __ bind(L); | |
328 } | |
329 #endif | |
1060 | 330 __ movptr(rbx, Address(OSR_buf, slot_offset + 0)); |
304 | 331 __ movptr(frame_map()->address_for_monitor_lock(i), rbx); |
1060 | 332 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord)); |
304 | 333 __ movptr(frame_map()->address_for_monitor_object(i), rbx); |
0 | 334 } |
335 } | |
336 } | |
337 | |
338 | |
339 // inline cache check; done before the frame is built. | |
340 int LIR_Assembler::check_icache() { | |
341 Register receiver = FrameMap::receiver_opr->as_register(); | |
342 Register ic_klass = IC_Klass; | |
304 | 343 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9); |
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344 const bool do_post_padding = VerifyOops || UseCompressedClassPointers; |
2002 | 345 if (!do_post_padding) { |
0 | 346 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment |
304 | 347 while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) { |
0 | 348 __ nop(); |
349 } | |
350 } | |
351 int offset = __ offset(); | |
352 __ inline_cache_check(receiver, IC_Klass); | |
2002 | 353 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct"); |
354 if (do_post_padding) { | |
0 | 355 // force alignment after the cache check. |
356 // It's been verified to be aligned if !VerifyOops | |
357 __ align(CodeEntryAlignment); | |
358 } | |
359 return offset; | |
360 } | |
361 | |
362 | |
363 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) { | |
364 jobject o = NULL; | |
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365 PatchingStub* patch = new PatchingStub(_masm, patching_id(info)); |
0 | 366 __ movoop(reg, o); |
367 patching_epilog(patch, lir_patch_normal, reg, info); | |
368 } | |
369 | |
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370 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) { |
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371 Metadata* o = NULL; |
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372 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id); |
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373 __ mov_metadata(reg, o); |
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374 patching_epilog(patch, lir_patch_normal, reg, info); |
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375 } |
0 | 376 |
377 // This specifies the rsp decrement needed to build the frame | |
378 int LIR_Assembler::initial_frame_size_in_bytes() { | |
379 // if rounding, must let FrameMap know! | |
304 | 380 |
381 // The frame_map records size in slots (32bit word) | |
382 | |
383 // subtract two words to account for return address and link | |
384 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size; | |
0 | 385 } |
386 | |
387 | |
1204 | 388 int LIR_Assembler::emit_exception_handler() { |
0 | 389 // if the last instruction is a call (typically to do a throw which |
390 // is coming at the end after block reordering) the return address | |
391 // must still point into the code area in order to avoid assertion | |
392 // failures when searching for the corresponding bci => add a nop | |
393 // (was bug 5/14/1999 - gri) | |
394 __ nop(); | |
395 | |
396 // generate code for exception handler | |
397 address handler_base = __ start_a_stub(exception_handler_size); | |
398 if (handler_base == NULL) { | |
399 // not enough space left for the handler | |
400 bailout("exception handler overflow"); | |
1204 | 401 return -1; |
0 | 402 } |
1204 | 403 |
0 | 404 int offset = code_offset(); |
405 | |
1295 | 406 // the exception oop and pc are in rax, and rdx |
0 | 407 // no other registers need to be preserved, so invalidate them |
1295 | 408 __ invalidate_registers(false, true, true, false, true, true); |
0 | 409 |
410 // check that there is really an exception | |
411 __ verify_not_null_oop(rax); | |
412 | |
1295 | 413 // search an exception handler (rax: exception oop, rdx: throwing pc) |
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414 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id))); |
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415 __ should_not_reach_here(); |
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416 guarantee(code_offset() - offset <= exception_handler_size, "overflow"); |
0 | 417 __ end_a_stub(); |
1204 | 418 |
419 return offset; | |
0 | 420 } |
421 | |
1204 | 422 |
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423 // Emit the code to remove the frame from the stack in the exception |
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424 // unwind path. |
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425 int LIR_Assembler::emit_unwind_handler() { |
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426 #ifndef PRODUCT |
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427 if (CommentedAssembly) { |
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428 _masm->block_comment("Unwind handler"); |
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429 } |
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430 #endif |
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431 |
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432 int offset = code_offset(); |
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433 |
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434 // Fetch the exception from TLS and clear out exception related thread state |
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435 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread); |
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436 NOT_LP64(__ get_thread(rsi)); |
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437 __ movptr(rax, Address(thread, JavaThread::exception_oop_offset())); |
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438 __ movptr(Address(thread, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD); |
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439 __ movptr(Address(thread, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD); |
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440 |
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441 __ bind(_unwind_handler_entry); |
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442 __ verify_not_null_oop(rax); |
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443 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { |
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444 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved) |
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445 } |
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446 |
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447 // Preform needed unlocking |
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448 MonitorExitStub* stub = NULL; |
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449 if (method()->is_synchronized()) { |
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450 monitor_address(0, FrameMap::rax_opr); |
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451 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0); |
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452 __ unlock_object(rdi, rsi, rax, *stub->entry()); |
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453 __ bind(*stub->continuation()); |
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454 } |
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455 |
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456 if (compilation()->env()->dtrace_method_probes()) { |
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457 #ifdef _LP64 |
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458 __ mov(rdi, r15_thread); |
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459 __ mov_metadata(rsi, method()->constant_encoding()); |
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460 #else |
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461 __ get_thread(rax); |
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462 __ movptr(Address(rsp, 0), rax); |
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463 __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding()); |
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464 #endif |
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465 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit))); |
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466 } |
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467 |
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468 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { |
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469 __ mov(rax, rbx); // Restore the exception |
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470 } |
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471 |
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472 // remove the activation and dispatch to the unwind handler |
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473 __ remove_frame(initial_frame_size_in_bytes()); |
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474 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id))); |
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475 |
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476 // Emit the slow path assembly |
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477 if (stub != NULL) { |
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478 stub->emit_code(this); |
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479 } |
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480 |
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481 return offset; |
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482 } |
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483 |
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484 |
1204 | 485 int LIR_Assembler::emit_deopt_handler() { |
0 | 486 // if the last instruction is a call (typically to do a throw which |
487 // is coming at the end after block reordering) the return address | |
488 // must still point into the code area in order to avoid assertion | |
489 // failures when searching for the corresponding bci => add a nop | |
490 // (was bug 5/14/1999 - gri) | |
491 __ nop(); | |
492 | |
493 // generate code for exception handler | |
494 address handler_base = __ start_a_stub(deopt_handler_size); | |
495 if (handler_base == NULL) { | |
496 // not enough space left for the handler | |
497 bailout("deopt handler overflow"); | |
1204 | 498 return -1; |
0 | 499 } |
1204 | 500 |
0 | 501 int offset = code_offset(); |
502 InternalAddress here(__ pc()); | |
1295 | 503 |
0 | 504 __ pushptr(here.addr()); |
505 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); | |
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506 guarantee(code_offset() - offset <= deopt_handler_size, "overflow"); |
0 | 507 __ end_a_stub(); |
508 | |
1204 | 509 return offset; |
0 | 510 } |
511 | |
512 | |
513 // This is the fast version of java.lang.String.compare; it has not | |
514 // OSR-entry and therefore, we generate a slow version for OSR's | |
515 void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) { | |
304 | 516 __ movptr (rbx, rcx); // receiver is in rcx |
517 __ movptr (rax, arg1->as_register()); | |
0 | 518 |
519 // Get addresses of first characters from both Strings | |
2002 | 520 __ load_heap_oop(rsi, Address(rax, java_lang_String::value_offset_in_bytes())); |
6057 | 521 if (java_lang_String::has_offset_field()) { |
522 __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes())); | |
523 __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes())); | |
524 __ lea (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); | |
525 } else { | |
526 __ movl (rax, Address(rsi, arrayOopDesc::length_offset_in_bytes())); | |
527 __ lea (rsi, Address(rsi, arrayOopDesc::base_offset_in_bytes(T_CHAR))); | |
528 } | |
0 | 529 |
530 // rbx, may be NULL | |
531 add_debug_info_for_null_check_here(info); | |
2002 | 532 __ load_heap_oop(rdi, Address(rbx, java_lang_String::value_offset_in_bytes())); |
6057 | 533 if (java_lang_String::has_offset_field()) { |
534 __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes())); | |
535 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes())); | |
536 __ lea (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); | |
537 } else { | |
538 __ movl (rbx, Address(rdi, arrayOopDesc::length_offset_in_bytes())); | |
539 __ lea (rdi, Address(rdi, arrayOopDesc::base_offset_in_bytes(T_CHAR))); | |
540 } | |
0 | 541 |
542 // compute minimum length (in rax) and difference of lengths (on top of stack) | |
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543 __ mov (rcx, rbx); |
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544 __ subptr(rbx, rax); // subtract lengths |
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545 __ push (rbx); // result |
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546 __ cmov (Assembler::lessEqual, rax, rcx); |
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547 |
0 | 548 // is minimum length 0? |
549 Label noLoop, haveResult; | |
304 | 550 __ testptr (rax, rax); |
0 | 551 __ jcc (Assembler::zero, noLoop); |
552 | |
553 // compare first characters | |
622
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554 __ load_unsigned_short(rcx, Address(rdi, 0)); |
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555 __ load_unsigned_short(rbx, Address(rsi, 0)); |
0 | 556 __ subl(rcx, rbx); |
557 __ jcc(Assembler::notZero, haveResult); | |
558 // starting loop | |
559 __ decrement(rax); // we already tested index: skip one | |
560 __ jcc(Assembler::zero, noLoop); | |
561 | |
562 // set rsi.edi to the end of the arrays (arrays have same length) | |
563 // negate the index | |
564 | |
304 | 565 __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR))); |
566 __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR))); | |
567 __ negptr(rax); | |
0 | 568 |
569 // compare the strings in a loop | |
570 | |
571 Label loop; | |
572 __ align(wordSize); | |
573 __ bind(loop); | |
622
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574 __ load_unsigned_short(rcx, Address(rdi, rax, Address::times_2, 0)); |
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575 __ load_unsigned_short(rbx, Address(rsi, rax, Address::times_2, 0)); |
0 | 576 __ subl(rcx, rbx); |
577 __ jcc(Assembler::notZero, haveResult); | |
578 __ increment(rax); | |
579 __ jcc(Assembler::notZero, loop); | |
580 | |
581 // strings are equal up to min length | |
582 | |
583 __ bind(noLoop); | |
304 | 584 __ pop(rax); |
0 | 585 return_op(LIR_OprFact::illegalOpr); |
586 | |
587 __ bind(haveResult); | |
588 // leave instruction is going to discard the TOS value | |
304 | 589 __ mov (rax, rcx); // result of call is in rax, |
0 | 590 } |
591 | |
592 | |
593 void LIR_Assembler::return_op(LIR_Opr result) { | |
594 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,"); | |
595 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) { | |
596 assert(result->fpu() == 0, "result must already be on TOS"); | |
597 } | |
598 | |
599 // Pop the stack before the safepoint code | |
1295 | 600 __ remove_frame(initial_frame_size_in_bytes()); |
0 | 601 |
602 bool result_is_oop = result->is_valid() ? result->is_oop() : false; | |
603 | |
604 // Note: we do not need to round double result; float result has the right precision | |
605 // the poll sets the condition code, but no data registers | |
606 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), | |
607 relocInfo::poll_return_type); | |
304 | 608 |
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609 if (Assembler::is_polling_page_far()) { |
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610 __ lea(rscratch1, polling_page); |
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611 __ relocate(relocInfo::poll_return_type); |
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612 __ testl(rax, Address(rscratch1, 0)); |
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613 } else { |
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614 __ testl(rax, polling_page); |
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615 } |
0 | 616 __ ret(0); |
617 } | |
618 | |
619 | |
620 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { | |
621 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), | |
622 relocInfo::poll_type); | |
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623 guarantee(info != NULL, "Shouldn't be NULL"); |
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624 int offset = __ offset(); |
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625 if (Assembler::is_polling_page_far()) { |
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626 __ lea(rscratch1, polling_page); |
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627 offset = __ offset(); |
0 | 628 add_debug_info_for_branch(info); |
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629 __ testl(rax, Address(rscratch1, 0)); |
0 | 630 } else { |
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631 add_debug_info_for_branch(info); |
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632 __ testl(rax, polling_page); |
0 | 633 } |
634 return offset; | |
635 } | |
636 | |
637 | |
638 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) { | |
304 | 639 if (from_reg != to_reg) __ mov(to_reg, from_reg); |
0 | 640 } |
641 | |
642 void LIR_Assembler::swap_reg(Register a, Register b) { | |
304 | 643 __ xchgptr(a, b); |
0 | 644 } |
645 | |
646 | |
647 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { | |
648 assert(src->is_constant(), "should not call otherwise"); | |
649 assert(dest->is_register(), "should not call otherwise"); | |
650 LIR_Const* c = src->as_constant_ptr(); | |
651 | |
652 switch (c->type()) { | |
2002 | 653 case T_INT: { |
654 assert(patch_code == lir_patch_none, "no patching handled here"); | |
655 __ movl(dest->as_register(), c->as_jint()); | |
656 break; | |
657 } | |
658 | |
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659 case T_ADDRESS: { |
0 | 660 assert(patch_code == lir_patch_none, "no patching handled here"); |
2002 | 661 __ movptr(dest->as_register(), c->as_jint()); |
0 | 662 break; |
663 } | |
664 | |
665 case T_LONG: { | |
666 assert(patch_code == lir_patch_none, "no patching handled here"); | |
304 | 667 #ifdef _LP64 |
668 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong()); | |
669 #else | |
670 __ movptr(dest->as_register_lo(), c->as_jint_lo()); | |
671 __ movptr(dest->as_register_hi(), c->as_jint_hi()); | |
672 #endif // _LP64 | |
0 | 673 break; |
674 } | |
675 | |
676 case T_OBJECT: { | |
677 if (patch_code != lir_patch_none) { | |
678 jobject2reg_with_patching(dest->as_register(), info); | |
679 } else { | |
680 __ movoop(dest->as_register(), c->as_jobject()); | |
681 } | |
682 break; | |
683 } | |
684 | |
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685 case T_METADATA: { |
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686 if (patch_code != lir_patch_none) { |
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687 klass2reg_with_patching(dest->as_register(), info); |
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688 } else { |
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689 __ mov_metadata(dest->as_register(), c->as_metadata()); |
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690 } |
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691 break; |
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692 } |
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693 |
0 | 694 case T_FLOAT: { |
695 if (dest->is_single_xmm()) { | |
696 if (c->is_zero_float()) { | |
697 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg()); | |
698 } else { | |
699 __ movflt(dest->as_xmm_float_reg(), | |
700 InternalAddress(float_constant(c->as_jfloat()))); | |
701 } | |
702 } else { | |
703 assert(dest->is_single_fpu(), "must be"); | |
704 assert(dest->fpu_regnr() == 0, "dest must be TOS"); | |
705 if (c->is_zero_float()) { | |
706 __ fldz(); | |
707 } else if (c->is_one_float()) { | |
708 __ fld1(); | |
709 } else { | |
710 __ fld_s (InternalAddress(float_constant(c->as_jfloat()))); | |
711 } | |
712 } | |
713 break; | |
714 } | |
715 | |
716 case T_DOUBLE: { | |
717 if (dest->is_double_xmm()) { | |
718 if (c->is_zero_double()) { | |
719 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg()); | |
720 } else { | |
721 __ movdbl(dest->as_xmm_double_reg(), | |
722 InternalAddress(double_constant(c->as_jdouble()))); | |
723 } | |
724 } else { | |
725 assert(dest->is_double_fpu(), "must be"); | |
726 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); | |
727 if (c->is_zero_double()) { | |
728 __ fldz(); | |
729 } else if (c->is_one_double()) { | |
730 __ fld1(); | |
731 } else { | |
732 __ fld_d (InternalAddress(double_constant(c->as_jdouble()))); | |
733 } | |
734 } | |
735 break; | |
736 } | |
737 | |
738 default: | |
739 ShouldNotReachHere(); | |
740 } | |
741 } | |
742 | |
743 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { | |
744 assert(src->is_constant(), "should not call otherwise"); | |
745 assert(dest->is_stack(), "should not call otherwise"); | |
746 LIR_Const* c = src->as_constant_ptr(); | |
747 | |
748 switch (c->type()) { | |
749 case T_INT: // fall through | |
750 case T_FLOAT: | |
2002 | 751 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); |
752 break; | |
753 | |
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754 case T_ADDRESS: |
2002 | 755 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); |
0 | 756 break; |
757 | |
758 case T_OBJECT: | |
759 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject()); | |
760 break; | |
761 | |
762 case T_LONG: // fall through | |
763 case T_DOUBLE: | |
304 | 764 #ifdef _LP64 |
765 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), | |
766 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits()); | |
767 #else | |
768 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), | |
769 lo_word_offset_in_bytes), c->as_jint_lo_bits()); | |
770 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), | |
771 hi_word_offset_in_bytes), c->as_jint_hi_bits()); | |
772 #endif // _LP64 | |
0 | 773 break; |
774 | |
775 default: | |
776 ShouldNotReachHere(); | |
777 } | |
778 } | |
779 | |
2002 | 780 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) { |
0 | 781 assert(src->is_constant(), "should not call otherwise"); |
782 assert(dest->is_address(), "should not call otherwise"); | |
783 LIR_Const* c = src->as_constant_ptr(); | |
784 LIR_Address* addr = dest->as_address_ptr(); | |
785 | |
304 | 786 int null_check_here = code_offset(); |
0 | 787 switch (type) { |
788 case T_INT: // fall through | |
789 case T_FLOAT: | |
2002 | 790 __ movl(as_Address(addr), c->as_jint_bits()); |
791 break; | |
792 | |
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793 case T_ADDRESS: |
2002 | 794 __ movptr(as_Address(addr), c->as_jint_bits()); |
0 | 795 break; |
796 | |
797 case T_OBJECT: // fall through | |
798 case T_ARRAY: | |
799 if (c->as_jobject() == NULL) { | |
2002 | 800 if (UseCompressedOops && !wide) { |
801 __ movl(as_Address(addr), (int32_t)NULL_WORD); | |
802 } else { | |
803 __ movptr(as_Address(addr), NULL_WORD); | |
804 } | |
0 | 805 } else { |
304 | 806 if (is_literal_address(addr)) { |
807 ShouldNotReachHere(); | |
808 __ movoop(as_Address(addr, noreg), c->as_jobject()); | |
809 } else { | |
1060 | 810 #ifdef _LP64 |
811 __ movoop(rscratch1, c->as_jobject()); | |
2002 | 812 if (UseCompressedOops && !wide) { |
813 __ encode_heap_oop(rscratch1); | |
814 null_check_here = code_offset(); | |
815 __ movl(as_Address_lo(addr), rscratch1); | |
816 } else { | |
817 null_check_here = code_offset(); | |
818 __ movptr(as_Address_lo(addr), rscratch1); | |
819 } | |
1060 | 820 #else |
304 | 821 __ movoop(as_Address(addr), c->as_jobject()); |
1060 | 822 #endif |
304 | 823 } |
0 | 824 } |
825 break; | |
826 | |
827 case T_LONG: // fall through | |
828 case T_DOUBLE: | |
304 | 829 #ifdef _LP64 |
830 if (is_literal_address(addr)) { | |
831 ShouldNotReachHere(); | |
832 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits()); | |
833 } else { | |
834 __ movptr(r10, (intptr_t)c->as_jlong_bits()); | |
835 null_check_here = code_offset(); | |
836 __ movptr(as_Address_lo(addr), r10); | |
837 } | |
838 #else | |
839 // Always reachable in 32bit so this doesn't produce useless move literal | |
840 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits()); | |
841 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits()); | |
842 #endif // _LP64 | |
0 | 843 break; |
844 | |
845 case T_BOOLEAN: // fall through | |
846 case T_BYTE: | |
847 __ movb(as_Address(addr), c->as_jint() & 0xFF); | |
848 break; | |
849 | |
850 case T_CHAR: // fall through | |
851 case T_SHORT: | |
852 __ movw(as_Address(addr), c->as_jint() & 0xFFFF); | |
853 break; | |
854 | |
855 default: | |
856 ShouldNotReachHere(); | |
857 }; | |
304 | 858 |
859 if (info != NULL) { | |
860 add_debug_info_for_null_check(null_check_here, info); | |
861 } | |
0 | 862 } |
863 | |
864 | |
865 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { | |
866 assert(src->is_register(), "should not call otherwise"); | |
867 assert(dest->is_register(), "should not call otherwise"); | |
868 | |
869 // move between cpu-registers | |
870 if (dest->is_single_cpu()) { | |
304 | 871 #ifdef _LP64 |
872 if (src->type() == T_LONG) { | |
873 // Can do LONG -> OBJECT | |
874 move_regs(src->as_register_lo(), dest->as_register()); | |
875 return; | |
876 } | |
877 #endif | |
0 | 878 assert(src->is_single_cpu(), "must match"); |
879 if (src->type() == T_OBJECT) { | |
880 __ verify_oop(src->as_register()); | |
881 } | |
882 move_regs(src->as_register(), dest->as_register()); | |
883 | |
884 } else if (dest->is_double_cpu()) { | |
304 | 885 #ifdef _LP64 |
886 if (src->type() == T_OBJECT || src->type() == T_ARRAY) { | |
887 // Surprising to me but we can see move of a long to t_object | |
888 __ verify_oop(src->as_register()); | |
889 move_regs(src->as_register(), dest->as_register_lo()); | |
890 return; | |
891 } | |
892 #endif | |
0 | 893 assert(src->is_double_cpu(), "must match"); |
894 Register f_lo = src->as_register_lo(); | |
895 Register f_hi = src->as_register_hi(); | |
896 Register t_lo = dest->as_register_lo(); | |
897 Register t_hi = dest->as_register_hi(); | |
304 | 898 #ifdef _LP64 |
899 assert(f_hi == f_lo, "must be same"); | |
900 assert(t_hi == t_lo, "must be same"); | |
901 move_regs(f_lo, t_lo); | |
902 #else | |
0 | 903 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation"); |
904 | |
304 | 905 |
0 | 906 if (f_lo == t_hi && f_hi == t_lo) { |
907 swap_reg(f_lo, f_hi); | |
908 } else if (f_hi == t_lo) { | |
909 assert(f_lo != t_hi, "overwriting register"); | |
910 move_regs(f_hi, t_hi); | |
911 move_regs(f_lo, t_lo); | |
912 } else { | |
913 assert(f_hi != t_lo, "overwriting register"); | |
914 move_regs(f_lo, t_lo); | |
915 move_regs(f_hi, t_hi); | |
916 } | |
304 | 917 #endif // LP64 |
0 | 918 |
919 // special moves from fpu-register to xmm-register | |
920 // necessary for method results | |
921 } else if (src->is_single_xmm() && !dest->is_single_xmm()) { | |
922 __ movflt(Address(rsp, 0), src->as_xmm_float_reg()); | |
923 __ fld_s(Address(rsp, 0)); | |
924 } else if (src->is_double_xmm() && !dest->is_double_xmm()) { | |
925 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg()); | |
926 __ fld_d(Address(rsp, 0)); | |
927 } else if (dest->is_single_xmm() && !src->is_single_xmm()) { | |
928 __ fstp_s(Address(rsp, 0)); | |
929 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0)); | |
930 } else if (dest->is_double_xmm() && !src->is_double_xmm()) { | |
931 __ fstp_d(Address(rsp, 0)); | |
932 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0)); | |
933 | |
934 // move between xmm-registers | |
935 } else if (dest->is_single_xmm()) { | |
936 assert(src->is_single_xmm(), "must match"); | |
937 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg()); | |
938 } else if (dest->is_double_xmm()) { | |
939 assert(src->is_double_xmm(), "must match"); | |
940 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg()); | |
941 | |
942 // move between fpu-registers (no instruction necessary because of fpu-stack) | |
943 } else if (dest->is_single_fpu() || dest->is_double_fpu()) { | |
944 assert(src->is_single_fpu() || src->is_double_fpu(), "must match"); | |
945 assert(src->fpu() == dest->fpu(), "currently should be nothing to do"); | |
946 } else { | |
947 ShouldNotReachHere(); | |
948 } | |
949 } | |
950 | |
951 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { | |
952 assert(src->is_register(), "should not call otherwise"); | |
953 assert(dest->is_stack(), "should not call otherwise"); | |
954 | |
955 if (src->is_single_cpu()) { | |
956 Address dst = frame_map()->address_for_slot(dest->single_stack_ix()); | |
957 if (type == T_OBJECT || type == T_ARRAY) { | |
958 __ verify_oop(src->as_register()); | |
304 | 959 __ movptr (dst, src->as_register()); |
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960 } else if (type == T_METADATA) { |
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961 __ movptr (dst, src->as_register()); |
304 | 962 } else { |
963 __ movl (dst, src->as_register()); | |
0 | 964 } |
965 | |
966 } else if (src->is_double_cpu()) { | |
967 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes); | |
968 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes); | |
304 | 969 __ movptr (dstLO, src->as_register_lo()); |
970 NOT_LP64(__ movptr (dstHI, src->as_register_hi())); | |
0 | 971 |
972 } else if (src->is_single_xmm()) { | |
973 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); | |
974 __ movflt(dst_addr, src->as_xmm_float_reg()); | |
975 | |
976 } else if (src->is_double_xmm()) { | |
977 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); | |
978 __ movdbl(dst_addr, src->as_xmm_double_reg()); | |
979 | |
980 } else if (src->is_single_fpu()) { | |
981 assert(src->fpu_regnr() == 0, "argument must be on TOS"); | |
982 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); | |
983 if (pop_fpu_stack) __ fstp_s (dst_addr); | |
984 else __ fst_s (dst_addr); | |
985 | |
986 } else if (src->is_double_fpu()) { | |
987 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); | |
988 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); | |
989 if (pop_fpu_stack) __ fstp_d (dst_addr); | |
990 else __ fst_d (dst_addr); | |
991 | |
992 } else { | |
993 ShouldNotReachHere(); | |
994 } | |
995 } | |
996 | |
997 | |
2002 | 998 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) { |
0 | 999 LIR_Address* to_addr = dest->as_address_ptr(); |
1000 PatchingStub* patch = NULL; | |
2002 | 1001 Register compressed_src = rscratch1; |
0 | 1002 |
1003 if (type == T_ARRAY || type == T_OBJECT) { | |
1004 __ verify_oop(src->as_register()); | |
2002 | 1005 #ifdef _LP64 |
1006 if (UseCompressedOops && !wide) { | |
1007 __ movptr(compressed_src, src->as_register()); | |
1008 __ encode_heap_oop(compressed_src); | |
1009 } | |
1010 #endif | |
0 | 1011 } |
2002 | 1012 |
0 | 1013 if (patch_code != lir_patch_none) { |
1014 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
304 | 1015 Address toa = as_Address(to_addr); |
1016 assert(toa.disp() != 0, "must have"); | |
0 | 1017 } |
2002 | 1018 |
1019 int null_check_here = code_offset(); | |
0 | 1020 switch (type) { |
1021 case T_FLOAT: { | |
1022 if (src->is_single_xmm()) { | |
1023 __ movflt(as_Address(to_addr), src->as_xmm_float_reg()); | |
1024 } else { | |
1025 assert(src->is_single_fpu(), "must be"); | |
1026 assert(src->fpu_regnr() == 0, "argument must be on TOS"); | |
1027 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr)); | |
1028 else __ fst_s (as_Address(to_addr)); | |
1029 } | |
1030 break; | |
1031 } | |
1032 | |
1033 case T_DOUBLE: { | |
1034 if (src->is_double_xmm()) { | |
1035 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg()); | |
1036 } else { | |
1037 assert(src->is_double_fpu(), "must be"); | |
1038 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); | |
1039 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr)); | |
1040 else __ fst_d (as_Address(to_addr)); | |
1041 } | |
1042 break; | |
1043 } | |
1044 | |
1045 case T_ARRAY: // fall through | |
1046 case T_OBJECT: // fall through | |
2002 | 1047 if (UseCompressedOops && !wide) { |
1048 __ movl(as_Address(to_addr), compressed_src); | |
1049 } else { | |
1050 __ movptr(as_Address(to_addr), src->as_register()); | |
1051 } | |
1052 break; | |
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1053 case T_METADATA: |
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1054 // We get here to store a method pointer to the stack to pass to |
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1055 // a dtrace runtime call. This can't work on 64 bit with |
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1056 // compressed klass ptrs: T_METADATA can be a compressed klass |
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1057 // ptr or a 64 bit method pointer. |
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1058 LP64_ONLY(ShouldNotReachHere()); |
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1059 __ movptr(as_Address(to_addr), src->as_register()); |
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1060 break; |
2002 | 1061 case T_ADDRESS: |
304 | 1062 __ movptr(as_Address(to_addr), src->as_register()); |
1063 break; | |
0 | 1064 case T_INT: |
1065 __ movl(as_Address(to_addr), src->as_register()); | |
1066 break; | |
1067 | |
1068 case T_LONG: { | |
1069 Register from_lo = src->as_register_lo(); | |
1070 Register from_hi = src->as_register_hi(); | |
304 | 1071 #ifdef _LP64 |
1072 __ movptr(as_Address_lo(to_addr), from_lo); | |
1073 #else | |
0 | 1074 Register base = to_addr->base()->as_register(); |
1075 Register index = noreg; | |
1076 if (to_addr->index()->is_register()) { | |
1077 index = to_addr->index()->as_register(); | |
1078 } | |
1079 if (base == from_lo || index == from_lo) { | |
1080 assert(base != from_hi, "can't be"); | |
1081 assert(index == noreg || (index != base && index != from_hi), "can't handle this"); | |
1082 __ movl(as_Address_hi(to_addr), from_hi); | |
1083 if (patch != NULL) { | |
1084 patching_epilog(patch, lir_patch_high, base, info); | |
1085 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
1086 patch_code = lir_patch_low; | |
1087 } | |
1088 __ movl(as_Address_lo(to_addr), from_lo); | |
1089 } else { | |
1090 assert(index == noreg || (index != base && index != from_lo), "can't handle this"); | |
1091 __ movl(as_Address_lo(to_addr), from_lo); | |
1092 if (patch != NULL) { | |
1093 patching_epilog(patch, lir_patch_low, base, info); | |
1094 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
1095 patch_code = lir_patch_high; | |
1096 } | |
1097 __ movl(as_Address_hi(to_addr), from_hi); | |
1098 } | |
304 | 1099 #endif // _LP64 |
0 | 1100 break; |
1101 } | |
1102 | |
1103 case T_BYTE: // fall through | |
1104 case T_BOOLEAN: { | |
1105 Register src_reg = src->as_register(); | |
1106 Address dst_addr = as_Address(to_addr); | |
1107 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6"); | |
1108 __ movb(dst_addr, src_reg); | |
1109 break; | |
1110 } | |
1111 | |
1112 case T_CHAR: // fall through | |
1113 case T_SHORT: | |
1114 __ movw(as_Address(to_addr), src->as_register()); | |
1115 break; | |
1116 | |
1117 default: | |
1118 ShouldNotReachHere(); | |
1119 } | |
2002 | 1120 if (info != NULL) { |
1121 add_debug_info_for_null_check(null_check_here, info); | |
1122 } | |
0 | 1123 |
1124 if (patch_code != lir_patch_none) { | |
1125 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info); | |
1126 } | |
1127 } | |
1128 | |
1129 | |
1130 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { | |
1131 assert(src->is_stack(), "should not call otherwise"); | |
1132 assert(dest->is_register(), "should not call otherwise"); | |
1133 | |
1134 if (dest->is_single_cpu()) { | |
1135 if (type == T_ARRAY || type == T_OBJECT) { | |
304 | 1136 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); |
0 | 1137 __ verify_oop(dest->as_register()); |
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1138 } else if (type == T_METADATA) { |
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1139 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); |
304 | 1140 } else { |
1141 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); | |
0 | 1142 } |
1143 | |
1144 } else if (dest->is_double_cpu()) { | |
1145 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes); | |
1146 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes); | |
304 | 1147 __ movptr(dest->as_register_lo(), src_addr_LO); |
1148 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI)); | |
0 | 1149 |
1150 } else if (dest->is_single_xmm()) { | |
1151 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); | |
1152 __ movflt(dest->as_xmm_float_reg(), src_addr); | |
1153 | |
1154 } else if (dest->is_double_xmm()) { | |
1155 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); | |
1156 __ movdbl(dest->as_xmm_double_reg(), src_addr); | |
1157 | |
1158 } else if (dest->is_single_fpu()) { | |
1159 assert(dest->fpu_regnr() == 0, "dest must be TOS"); | |
1160 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); | |
1161 __ fld_s(src_addr); | |
1162 | |
1163 } else if (dest->is_double_fpu()) { | |
1164 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); | |
1165 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); | |
1166 __ fld_d(src_addr); | |
1167 | |
1168 } else { | |
1169 ShouldNotReachHere(); | |
1170 } | |
1171 } | |
1172 | |
1173 | |
1174 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { | |
1175 if (src->is_single_stack()) { | |
304 | 1176 if (type == T_OBJECT || type == T_ARRAY) { |
1177 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix())); | |
1178 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix())); | |
1179 } else { | |
1060 | 1180 #ifndef _LP64 |
304 | 1181 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix())); |
1182 __ popl (frame_map()->address_for_slot(dest->single_stack_ix())); | |
1060 | 1183 #else |
1184 //no pushl on 64bits | |
1185 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix())); | |
1186 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1); | |
1187 #endif | |
304 | 1188 } |
0 | 1189 |
1190 } else if (src->is_double_stack()) { | |
304 | 1191 #ifdef _LP64 |
1192 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix())); | |
1193 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix())); | |
1194 #else | |
0 | 1195 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0)); |
304 | 1196 // push and pop the part at src + wordSize, adding wordSize for the previous push |
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1197 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize)); |
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1198 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize)); |
0 | 1199 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0)); |
304 | 1200 #endif // _LP64 |
0 | 1201 |
1202 } else { | |
1203 ShouldNotReachHere(); | |
1204 } | |
1205 } | |
1206 | |
1207 | |
2002 | 1208 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) { |
0 | 1209 assert(src->is_address(), "should not call otherwise"); |
1210 assert(dest->is_register(), "should not call otherwise"); | |
1211 | |
1212 LIR_Address* addr = src->as_address_ptr(); | |
1213 Address from_addr = as_Address(addr); | |
1214 | |
12955 | 1215 if (addr->base()->type() == T_OBJECT) { |
1216 __ verify_oop(addr->base()->as_pointer_register()); | |
1217 } | |
1218 | |
0 | 1219 switch (type) { |
1220 case T_BOOLEAN: // fall through | |
1221 case T_BYTE: // fall through | |
1222 case T_CHAR: // fall through | |
1223 case T_SHORT: | |
1224 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) { | |
1225 // on pre P6 processors we may get partial register stalls | |
1226 // so blow away the value of to_rinfo before loading a | |
1227 // partial word into it. Do it here so that it precedes | |
1228 // the potential patch point below. | |
304 | 1229 __ xorptr(dest->as_register(), dest->as_register()); |
0 | 1230 } |
1231 break; | |
1232 } | |
1233 | |
1234 PatchingStub* patch = NULL; | |
1235 if (patch_code != lir_patch_none) { | |
1236 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
304 | 1237 assert(from_addr.disp() != 0, "must have"); |
0 | 1238 } |
1239 if (info != NULL) { | |
1240 add_debug_info_for_null_check_here(info); | |
1241 } | |
1242 | |
1243 switch (type) { | |
1244 case T_FLOAT: { | |
1245 if (dest->is_single_xmm()) { | |
1246 __ movflt(dest->as_xmm_float_reg(), from_addr); | |
1247 } else { | |
1248 assert(dest->is_single_fpu(), "must be"); | |
1249 assert(dest->fpu_regnr() == 0, "dest must be TOS"); | |
1250 __ fld_s(from_addr); | |
1251 } | |
1252 break; | |
1253 } | |
1254 | |
1255 case T_DOUBLE: { | |
1256 if (dest->is_double_xmm()) { | |
1257 __ movdbl(dest->as_xmm_double_reg(), from_addr); | |
1258 } else { | |
1259 assert(dest->is_double_fpu(), "must be"); | |
1260 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); | |
1261 __ fld_d(from_addr); | |
1262 } | |
1263 break; | |
1264 } | |
1265 | |
1266 case T_OBJECT: // fall through | |
1267 case T_ARRAY: // fall through | |
2002 | 1268 if (UseCompressedOops && !wide) { |
1269 __ movl(dest->as_register(), from_addr); | |
1270 } else { | |
1271 __ movptr(dest->as_register(), from_addr); | |
1272 } | |
1273 break; | |
1274 | |
1275 case T_ADDRESS: | |
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1276 if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) { |
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1277 __ movl(dest->as_register(), from_addr); |
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1278 } else { |
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1279 __ movptr(dest->as_register(), from_addr); |
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1280 } |
304 | 1281 break; |
0 | 1282 case T_INT: |
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1283 __ movl(dest->as_register(), from_addr); |
0 | 1284 break; |
1285 | |
1286 case T_LONG: { | |
1287 Register to_lo = dest->as_register_lo(); | |
1288 Register to_hi = dest->as_register_hi(); | |
304 | 1289 #ifdef _LP64 |
1290 __ movptr(to_lo, as_Address_lo(addr)); | |
1291 #else | |
0 | 1292 Register base = addr->base()->as_register(); |
1293 Register index = noreg; | |
1294 if (addr->index()->is_register()) { | |
1295 index = addr->index()->as_register(); | |
1296 } | |
1297 if ((base == to_lo && index == to_hi) || | |
1298 (base == to_hi && index == to_lo)) { | |
1299 // addresses with 2 registers are only formed as a result of | |
1300 // array access so this code will never have to deal with | |
1301 // patches or null checks. | |
1302 assert(info == NULL && patch == NULL, "must be"); | |
304 | 1303 __ lea(to_hi, as_Address(addr)); |
0 | 1304 __ movl(to_lo, Address(to_hi, 0)); |
1305 __ movl(to_hi, Address(to_hi, BytesPerWord)); | |
1306 } else if (base == to_lo || index == to_lo) { | |
1307 assert(base != to_hi, "can't be"); | |
1308 assert(index == noreg || (index != base && index != to_hi), "can't handle this"); | |
1309 __ movl(to_hi, as_Address_hi(addr)); | |
1310 if (patch != NULL) { | |
1311 patching_epilog(patch, lir_patch_high, base, info); | |
1312 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
1313 patch_code = lir_patch_low; | |
1314 } | |
1315 __ movl(to_lo, as_Address_lo(addr)); | |
1316 } else { | |
1317 assert(index == noreg || (index != base && index != to_lo), "can't handle this"); | |
1318 __ movl(to_lo, as_Address_lo(addr)); | |
1319 if (patch != NULL) { | |
1320 patching_epilog(patch, lir_patch_low, base, info); | |
1321 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
1322 patch_code = lir_patch_high; | |
1323 } | |
1324 __ movl(to_hi, as_Address_hi(addr)); | |
1325 } | |
304 | 1326 #endif // _LP64 |
0 | 1327 break; |
1328 } | |
1329 | |
1330 case T_BOOLEAN: // fall through | |
1331 case T_BYTE: { | |
1332 Register dest_reg = dest->as_register(); | |
1333 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); | |
1334 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { | |
304 | 1335 __ movsbl(dest_reg, from_addr); |
0 | 1336 } else { |
1337 __ movb(dest_reg, from_addr); | |
1338 __ shll(dest_reg, 24); | |
1339 __ sarl(dest_reg, 24); | |
1340 } | |
1341 break; | |
1342 } | |
1343 | |
1344 case T_CHAR: { | |
1345 Register dest_reg = dest->as_register(); | |
1346 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); | |
1347 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { | |
304 | 1348 __ movzwl(dest_reg, from_addr); |
0 | 1349 } else { |
1350 __ movw(dest_reg, from_addr); | |
1351 } | |
1352 break; | |
1353 } | |
1354 | |
1355 case T_SHORT: { | |
1356 Register dest_reg = dest->as_register(); | |
1357 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { | |
304 | 1358 __ movswl(dest_reg, from_addr); |
0 | 1359 } else { |
1360 __ movw(dest_reg, from_addr); | |
1361 __ shll(dest_reg, 16); | |
1362 __ sarl(dest_reg, 16); | |
1363 } | |
1364 break; | |
1365 } | |
1366 | |
1367 default: | |
1368 ShouldNotReachHere(); | |
1369 } | |
1370 | |
1371 if (patch != NULL) { | |
1372 patching_epilog(patch, patch_code, addr->base()->as_register(), info); | |
1373 } | |
1374 | |
1375 if (type == T_ARRAY || type == T_OBJECT) { | |
2002 | 1376 #ifdef _LP64 |
1377 if (UseCompressedOops && !wide) { | |
1378 __ decode_heap_oop(dest->as_register()); | |
1379 } | |
1380 #endif | |
0 | 1381 __ verify_oop(dest->as_register()); |
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1382 } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) { |
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1383 #ifdef _LP64 |
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1384 if (UseCompressedClassPointers) { |
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1385 __ decode_klass_not_null(dest->as_register()); |
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1386 } |
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1387 #endif |
0 | 1388 } |
1389 } | |
1390 | |
1391 | |
1392 void LIR_Assembler::prefetchr(LIR_Opr src) { | |
1393 LIR_Address* addr = src->as_address_ptr(); | |
1394 Address from_addr = as_Address(addr); | |
1395 | |
1396 if (VM_Version::supports_sse()) { | |
1397 switch (ReadPrefetchInstr) { | |
1398 case 0: | |
1399 __ prefetchnta(from_addr); break; | |
1400 case 1: | |
1401 __ prefetcht0(from_addr); break; | |
1402 case 2: | |
1403 __ prefetcht2(from_addr); break; | |
1404 default: | |
1405 ShouldNotReachHere(); break; | |
1406 } | |
2479 | 1407 } else if (VM_Version::supports_3dnow_prefetch()) { |
0 | 1408 __ prefetchr(from_addr); |
1409 } | |
1410 } | |
1411 | |
1412 | |
1413 void LIR_Assembler::prefetchw(LIR_Opr src) { | |
1414 LIR_Address* addr = src->as_address_ptr(); | |
1415 Address from_addr = as_Address(addr); | |
1416 | |
1417 if (VM_Version::supports_sse()) { | |
1418 switch (AllocatePrefetchInstr) { | |
1419 case 0: | |
1420 __ prefetchnta(from_addr); break; | |
1421 case 1: | |
1422 __ prefetcht0(from_addr); break; | |
1423 case 2: | |
1424 __ prefetcht2(from_addr); break; | |
1425 case 3: | |
1426 __ prefetchw(from_addr); break; | |
1427 default: | |
1428 ShouldNotReachHere(); break; | |
1429 } | |
2479 | 1430 } else if (VM_Version::supports_3dnow_prefetch()) { |
0 | 1431 __ prefetchw(from_addr); |
1432 } | |
1433 } | |
1434 | |
1435 | |
1436 NEEDS_CLEANUP; // This could be static? | |
1437 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const { | |
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1438 int elem_size = type2aelembytes(type); |
0 | 1439 switch (elem_size) { |
1440 case 1: return Address::times_1; | |
1441 case 2: return Address::times_2; | |
1442 case 4: return Address::times_4; | |
1443 case 8: return Address::times_8; | |
1444 } | |
1445 ShouldNotReachHere(); | |
1446 return Address::no_scale; | |
1447 } | |
1448 | |
1449 | |
1450 void LIR_Assembler::emit_op3(LIR_Op3* op) { | |
1451 switch (op->code()) { | |
1452 case lir_idiv: | |
1453 case lir_irem: | |
1454 arithmetic_idiv(op->code(), | |
1455 op->in_opr1(), | |
1456 op->in_opr2(), | |
1457 op->in_opr3(), | |
1458 op->result_opr(), | |
1459 op->info()); | |
1460 break; | |
1461 default: ShouldNotReachHere(); break; | |
1462 } | |
1463 } | |
1464 | |
1465 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { | |
1466 #ifdef ASSERT | |
1467 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); | |
1468 if (op->block() != NULL) _branch_target_blocks.append(op->block()); | |
1469 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); | |
1470 #endif | |
1471 | |
1472 if (op->cond() == lir_cond_always) { | |
1473 if (op->info() != NULL) add_debug_info_for_branch(op->info()); | |
1474 __ jmp (*(op->label())); | |
1475 } else { | |
1476 Assembler::Condition acond = Assembler::zero; | |
1477 if (op->code() == lir_cond_float_branch) { | |
1478 assert(op->ublock() != NULL, "must have unordered successor"); | |
1479 __ jcc(Assembler::parity, *(op->ublock()->label())); | |
1480 switch(op->cond()) { | |
1481 case lir_cond_equal: acond = Assembler::equal; break; | |
1482 case lir_cond_notEqual: acond = Assembler::notEqual; break; | |
1483 case lir_cond_less: acond = Assembler::below; break; | |
1484 case lir_cond_lessEqual: acond = Assembler::belowEqual; break; | |
1485 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break; | |
1486 case lir_cond_greater: acond = Assembler::above; break; | |
1487 default: ShouldNotReachHere(); | |
1488 } | |
1489 } else { | |
1490 switch (op->cond()) { | |
1491 case lir_cond_equal: acond = Assembler::equal; break; | |
1492 case lir_cond_notEqual: acond = Assembler::notEqual; break; | |
1493 case lir_cond_less: acond = Assembler::less; break; | |
1494 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; | |
1495 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; | |
1496 case lir_cond_greater: acond = Assembler::greater; break; | |
1497 case lir_cond_belowEqual: acond = Assembler::belowEqual; break; | |
1498 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; | |
1499 default: ShouldNotReachHere(); | |
1500 } | |
1501 } | |
1502 __ jcc(acond,*(op->label())); | |
1503 } | |
1504 } | |
1505 | |
1506 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { | |
1507 LIR_Opr src = op->in_opr(); | |
1508 LIR_Opr dest = op->result_opr(); | |
1509 | |
1510 switch (op->bytecode()) { | |
1511 case Bytecodes::_i2l: | |
304 | 1512 #ifdef _LP64 |
1513 __ movl2ptr(dest->as_register_lo(), src->as_register()); | |
1514 #else | |
0 | 1515 move_regs(src->as_register(), dest->as_register_lo()); |
1516 move_regs(src->as_register(), dest->as_register_hi()); | |
1517 __ sarl(dest->as_register_hi(), 31); | |
304 | 1518 #endif // LP64 |
0 | 1519 break; |
1520 | |
1521 case Bytecodes::_l2i: | |
6041 | 1522 #ifdef _LP64 |
1523 __ movl(dest->as_register(), src->as_register_lo()); | |
1524 #else | |
0 | 1525 move_regs(src->as_register_lo(), dest->as_register()); |
6041 | 1526 #endif |
0 | 1527 break; |
1528 | |
1529 case Bytecodes::_i2b: | |
1530 move_regs(src->as_register(), dest->as_register()); | |
1531 __ sign_extend_byte(dest->as_register()); | |
1532 break; | |
1533 | |
1534 case Bytecodes::_i2c: | |
1535 move_regs(src->as_register(), dest->as_register()); | |
1536 __ andl(dest->as_register(), 0xFFFF); | |
1537 break; | |
1538 | |
1539 case Bytecodes::_i2s: | |
1540 move_regs(src->as_register(), dest->as_register()); | |
1541 __ sign_extend_short(dest->as_register()); | |
1542 break; | |
1543 | |
1544 | |
1545 case Bytecodes::_f2d: | |
1546 case Bytecodes::_d2f: | |
1547 if (dest->is_single_xmm()) { | |
1548 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg()); | |
1549 } else if (dest->is_double_xmm()) { | |
1550 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg()); | |
1551 } else { | |
1552 assert(src->fpu() == dest->fpu(), "register must be equal"); | |
1553 // do nothing (float result is rounded later through spilling) | |
1554 } | |
1555 break; | |
1556 | |
1557 case Bytecodes::_i2f: | |
1558 case Bytecodes::_i2d: | |
1559 if (dest->is_single_xmm()) { | |
304 | 1560 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register()); |
0 | 1561 } else if (dest->is_double_xmm()) { |
304 | 1562 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register()); |
0 | 1563 } else { |
1564 assert(dest->fpu() == 0, "result must be on TOS"); | |
1565 __ movl(Address(rsp, 0), src->as_register()); | |
1566 __ fild_s(Address(rsp, 0)); | |
1567 } | |
1568 break; | |
1569 | |
1570 case Bytecodes::_f2i: | |
1571 case Bytecodes::_d2i: | |
1572 if (src->is_single_xmm()) { | |
304 | 1573 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg()); |
0 | 1574 } else if (src->is_double_xmm()) { |
304 | 1575 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg()); |
0 | 1576 } else { |
1577 assert(src->fpu() == 0, "input must be on TOS"); | |
1578 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); | |
1579 __ fist_s(Address(rsp, 0)); | |
1580 __ movl(dest->as_register(), Address(rsp, 0)); | |
1581 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
1582 } | |
1583 | |
1584 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub | |
1585 assert(op->stub() != NULL, "stub required"); | |
1586 __ cmpl(dest->as_register(), 0x80000000); | |
1587 __ jcc(Assembler::equal, *op->stub()->entry()); | |
1588 __ bind(*op->stub()->continuation()); | |
1589 break; | |
1590 | |
1591 case Bytecodes::_l2f: | |
1592 case Bytecodes::_l2d: | |
1593 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)"); | |
1594 assert(dest->fpu() == 0, "result must be on TOS"); | |
1595 | |
304 | 1596 __ movptr(Address(rsp, 0), src->as_register_lo()); |
1597 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi())); | |
0 | 1598 __ fild_d(Address(rsp, 0)); |
1599 // float result is rounded later through spilling | |
1600 break; | |
1601 | |
1602 case Bytecodes::_f2l: | |
1603 case Bytecodes::_d2l: | |
1604 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)"); | |
1605 assert(src->fpu() == 0, "input must be on TOS"); | |
304 | 1606 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers"); |
0 | 1607 |
1608 // instruction sequence too long to inline it here | |
1609 { | |
1610 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id))); | |
1611 } | |
1612 break; | |
1613 | |
1614 default: ShouldNotReachHere(); | |
1615 } | |
1616 } | |
1617 | |
1618 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { | |
1619 if (op->init_check()) { | |
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1620 __ cmpb(Address(op->klass()->as_register(), |
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1621 InstanceKlass::init_state_offset()), |
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1622 InstanceKlass::fully_initialized); |
0 | 1623 add_debug_info_for_null_check_here(op->stub()->info()); |
1624 __ jcc(Assembler::notEqual, *op->stub()->entry()); | |
1625 } | |
1626 __ allocate_object(op->obj()->as_register(), | |
1627 op->tmp1()->as_register(), | |
1628 op->tmp2()->as_register(), | |
1629 op->header_size(), | |
1630 op->object_size(), | |
1631 op->klass()->as_register(), | |
1632 *op->stub()->entry()); | |
1633 __ bind(*op->stub()->continuation()); | |
1634 } | |
1635 | |
1636 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { | |
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1637 Register len = op->len()->as_register(); |
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1638 LP64_ONLY( __ movslq(len, len); ) |
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1639 |
0 | 1640 if (UseSlowPath || |
1641 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || | |
1642 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { | |
1643 __ jmp(*op->stub()->entry()); | |
1644 } else { | |
1645 Register tmp1 = op->tmp1()->as_register(); | |
1646 Register tmp2 = op->tmp2()->as_register(); | |
1647 Register tmp3 = op->tmp3()->as_register(); | |
1648 if (len == tmp1) { | |
1649 tmp1 = tmp3; | |
1650 } else if (len == tmp2) { | |
1651 tmp2 = tmp3; | |
1652 } else if (len == tmp3) { | |
1653 // everything is ok | |
1654 } else { | |
304 | 1655 __ mov(tmp3, len); |
0 | 1656 } |
1657 __ allocate_array(op->obj()->as_register(), | |
1658 len, | |
1659 tmp1, | |
1660 tmp2, | |
1661 arrayOopDesc::header_size(op->type()), | |
1662 array_element_size(op->type()), | |
1663 op->klass()->as_register(), | |
1664 *op->stub()->entry()); | |
1665 } | |
1666 __ bind(*op->stub()->continuation()); | |
1667 } | |
1668 | |
1783 | 1669 void LIR_Assembler::type_profile_helper(Register mdo, |
1670 ciMethodData *md, ciProfileData *data, | |
1671 Register recv, Label* update_done) { | |
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1672 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { |
1783 | 1673 Label next_test; |
1674 // See if the receiver is receiver[n]. | |
1675 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)))); | |
1676 __ jccb(Assembler::notEqual, next_test); | |
1677 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))); | |
1678 __ addptr(data_addr, DataLayout::counter_increment); | |
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1679 __ jmp(*update_done); |
1783 | 1680 __ bind(next_test); |
1681 } | |
1682 | |
1683 // Didn't find receiver; find next empty slot and fill it in | |
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1684 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { |
1783 | 1685 Label next_test; |
1686 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))); | |
1687 __ cmpptr(recv_addr, (intptr_t)NULL_WORD); | |
1688 __ jccb(Assembler::notEqual, next_test); | |
1689 __ movptr(recv_addr, recv); | |
1690 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment); | |
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1691 __ jmp(*update_done); |
1783 | 1692 __ bind(next_test); |
1693 } | |
1694 } | |
1695 | |
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1696 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { |
1783 | 1697 // we always need a stub for the failure case. |
1698 CodeStub* stub = op->stub(); | |
1699 Register obj = op->object()->as_register(); | |
1700 Register k_RInfo = op->tmp1()->as_register(); | |
1701 Register klass_RInfo = op->tmp2()->as_register(); | |
1702 Register dst = op->result_opr()->as_register(); | |
1703 ciKlass* k = op->klass(); | |
1704 Register Rtmp1 = noreg; | |
1705 | |
1706 // check if it needs to be profiled | |
1707 ciMethodData* md; | |
1708 ciProfileData* data; | |
1709 | |
1710 if (op->should_profile()) { | |
1711 ciMethod* method = op->profiled_method(); | |
1712 assert(method != NULL, "Should have method"); | |
1713 int bci = op->profiled_bci(); | |
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1714 md = method->method_data_or_null(); |
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1715 assert(md != NULL, "Sanity"); |
1783 | 1716 data = md->bci_to_data(bci); |
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1717 assert(data != NULL, "need data for type check"); |
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1718 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); |
1783 | 1719 } |
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1720 Label profile_cast_success, profile_cast_failure; |
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1721 Label *success_target = op->should_profile() ? &profile_cast_success : success; |
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1722 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure; |
1783 | 1723 |
1724 if (obj == k_RInfo) { | |
1725 k_RInfo = dst; | |
1726 } else if (obj == klass_RInfo) { | |
1727 klass_RInfo = dst; | |
1728 } | |
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1729 if (k->is_loaded() && !UseCompressedClassPointers) { |
1783 | 1730 select_different_registers(obj, dst, k_RInfo, klass_RInfo); |
1731 } else { | |
1732 Rtmp1 = op->tmp3()->as_register(); | |
1733 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1); | |
1734 } | |
1735 | |
1736 assert_different_registers(obj, k_RInfo, klass_RInfo); | |
1737 | |
1738 __ cmpptr(obj, (int32_t)NULL_WORD); | |
1739 if (op->should_profile()) { | |
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1740 Label not_null; |
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1741 __ jccb(Assembler::notEqual, not_null); |
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1742 // Object is null; update MDO and exit |
1783 | 1743 Register mdo = klass_RInfo; |
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1744 __ mov_metadata(mdo, md->constant_encoding()); |
1783 | 1745 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); |
1746 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); | |
1747 __ orl(data_addr, header_bits); | |
1791
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1748 __ jmp(*obj_is_null); |
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1749 __ bind(not_null); |
1783 | 1750 } else { |
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1751 __ jcc(Assembler::equal, *obj_is_null); |
1783 | 1752 } |
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1753 |
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1754 if (!k->is_loaded()) { |
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1755 klass2reg_with_patching(k_RInfo, op->info_for_patch()); |
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1756 } else { |
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1757 #ifdef _LP64 |
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1758 __ mov_metadata(k_RInfo, k->constant_encoding()); |
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1759 #endif // _LP64 |
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1760 } |
1783 | 1761 __ verify_oop(obj); |
1762 | |
1763 if (op->fast_check()) { | |
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1764 // get object class |
1783 | 1765 // not a safepoint as obj null check happens earlier |
1766 #ifdef _LP64 | |
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1767 if (UseCompressedClassPointers) { |
2002 | 1768 __ load_klass(Rtmp1, obj); |
1769 __ cmpptr(k_RInfo, Rtmp1); | |
1783 | 1770 } else { |
1771 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); | |
1772 } | |
2002 | 1773 #else |
1774 if (k->is_loaded()) { | |
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1775 __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding()); |
2002 | 1776 } else { |
1777 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); | |
1778 } | |
1779 #endif | |
1783 | 1780 __ jcc(Assembler::notEqual, *failure_target); |
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1781 // successful cast, fall through to profile or jump |
1783 | 1782 } else { |
1783 // get object class | |
1784 // not a safepoint as obj null check happens earlier | |
2002 | 1785 __ load_klass(klass_RInfo, obj); |
1783 | 1786 if (k->is_loaded()) { |
1787 // See if we get an immediate positive hit | |
1788 #ifdef _LP64 | |
1789 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset())); | |
1790 #else | |
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1791 __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding()); |
1783 | 1792 #endif // _LP64 |
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1793 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) { |
1783 | 1794 __ jcc(Assembler::notEqual, *failure_target); |
1791
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1795 // successful cast, fall through to profile or jump |
1783 | 1796 } else { |
1797 // See if we get an immediate positive hit | |
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1798 __ jcc(Assembler::equal, *success_target); |
1783 | 1799 // check for self |
1800 #ifdef _LP64 | |
1801 __ cmpptr(klass_RInfo, k_RInfo); | |
1802 #else | |
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1803 __ cmpklass(klass_RInfo, k->constant_encoding()); |
1783 | 1804 #endif // _LP64 |
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1805 __ jcc(Assembler::equal, *success_target); |
1783 | 1806 |
1807 __ push(klass_RInfo); | |
1808 #ifdef _LP64 | |
1809 __ push(k_RInfo); | |
1810 #else | |
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1811 __ pushklass(k->constant_encoding()); |
1783 | 1812 #endif // _LP64 |
1813 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); | |
1814 __ pop(klass_RInfo); | |
1815 __ pop(klass_RInfo); | |
1816 // result is a boolean | |
1817 __ cmpl(klass_RInfo, 0); | |
1818 __ jcc(Assembler::equal, *failure_target); | |
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1819 // successful cast, fall through to profile or jump |
1783 | 1820 } |
1821 } else { | |
1822 // perform the fast part of the checking logic | |
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1823 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); |
1783 | 1824 // call out-of-line instance of __ check_klass_subtype_slow_path(...): |
1825 __ push(klass_RInfo); | |
1826 __ push(k_RInfo); | |
1827 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); | |
1828 __ pop(klass_RInfo); | |
1829 __ pop(k_RInfo); | |
1830 // result is a boolean | |
1831 __ cmpl(k_RInfo, 0); | |
1832 __ jcc(Assembler::equal, *failure_target); | |
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1833 // successful cast, fall through to profile or jump |
1783 | 1834 } |
1835 } | |
1836 if (op->should_profile()) { | |
1837 Register mdo = klass_RInfo, recv = k_RInfo; | |
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1838 __ bind(profile_cast_success); |
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1839 __ mov_metadata(mdo, md->constant_encoding()); |
2002 | 1840 __ load_klass(recv, obj); |
1783 | 1841 Label update_done; |
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1842 type_profile_helper(mdo, md, data, recv, success); |
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1843 __ jmp(*success); |
1783 | 1844 |
1845 __ bind(profile_cast_failure); | |
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1846 __ mov_metadata(mdo, md->constant_encoding()); |
1783 | 1847 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); |
1848 __ subptr(counter_addr, DataLayout::counter_increment); | |
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1849 __ jmp(*failure); |
1783 | 1850 } |
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1851 __ jmp(*success); |
1783 | 1852 } |
0 | 1853 |
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1854 |
0 | 1855 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { |
1856 LIR_Code code = op->code(); | |
1857 if (code == lir_store_check) { | |
1858 Register value = op->object()->as_register(); | |
1859 Register array = op->array()->as_register(); | |
1860 Register k_RInfo = op->tmp1()->as_register(); | |
1861 Register klass_RInfo = op->tmp2()->as_register(); | |
1862 Register Rtmp1 = op->tmp3()->as_register(); | |
1863 | |
1864 CodeStub* stub = op->stub(); | |
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1865 |
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1866 // check if it needs to be profiled |
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1867 ciMethodData* md; |
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1868 ciProfileData* data; |
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1869 |
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1870 if (op->should_profile()) { |
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1871 ciMethod* method = op->profiled_method(); |
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1872 assert(method != NULL, "Should have method"); |
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1873 int bci = op->profiled_bci(); |
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1874 md = method->method_data_or_null(); |
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1875 assert(md != NULL, "Sanity"); |
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1876 data = md->bci_to_data(bci); |
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1877 assert(data != NULL, "need data for type check"); |
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1878 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); |
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1879 } |
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1880 Label profile_cast_success, profile_cast_failure, done; |
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1881 Label *success_target = op->should_profile() ? &profile_cast_success : &done; |
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1882 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry(); |
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1883 |
304 | 1884 __ cmpptr(value, (int32_t)NULL_WORD); |
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1885 if (op->should_profile()) { |
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1886 Label not_null; |
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1887 __ jccb(Assembler::notEqual, not_null); |
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1888 // Object is null; update MDO and exit |
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1889 Register mdo = klass_RInfo; |
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1890 __ mov_metadata(mdo, md->constant_encoding()); |
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1891 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); |
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1892 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); |
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1893 __ orl(data_addr, header_bits); |
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1894 __ jmp(done); |
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1895 __ bind(not_null); |
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1896 } else { |
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1897 __ jcc(Assembler::equal, done); |
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1898 } |
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1899 |
0 | 1900 add_debug_info_for_null_check_here(op->info_for_exception()); |
2002 | 1901 __ load_klass(k_RInfo, array); |
1902 __ load_klass(klass_RInfo, value); | |
1903 | |
1904 // get instance klass (it's already uncompressed) | |
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1905 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset())); |
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1906 // perform the fast part of the checking logic |
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1907 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); |
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1908 // call out-of-line instance of __ check_klass_subtype_slow_path(...): |
304 | 1909 __ push(klass_RInfo); |
1910 __ push(k_RInfo); | |
0 | 1911 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); |
304 | 1912 __ pop(klass_RInfo); |
1913 __ pop(k_RInfo); | |
1914 // result is a boolean | |
0 | 1915 __ cmpl(k_RInfo, 0); |
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1916 __ jcc(Assembler::equal, *failure_target); |
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1917 // fall through to the success case |
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1918 |
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1919 if (op->should_profile()) { |
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1920 Register mdo = klass_RInfo, recv = k_RInfo; |
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1921 __ bind(profile_cast_success); |
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1922 __ mov_metadata(mdo, md->constant_encoding()); |
2002 | 1923 __ load_klass(recv, value); |
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1924 Label update_done; |
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1925 type_profile_helper(mdo, md, data, recv, &done); |
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1926 __ jmpb(done); |
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1927 |
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1928 __ bind(profile_cast_failure); |
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1929 __ mov_metadata(mdo, md->constant_encoding()); |
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1930 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); |
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1931 __ subptr(counter_addr, DataLayout::counter_increment); |
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1932 __ jmp(*stub->entry()); |
0 | 1933 } |
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1934 |
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1935 __ bind(done); |
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1936 } else |
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1937 if (code == lir_checkcast) { |
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1938 Register obj = op->object()->as_register(); |
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1939 Register dst = op->result_opr()->as_register(); |
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1940 Label success; |
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1941 emit_typecheck_helper(op, &success, op->stub()->entry(), &success); |
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1942 __ bind(success); |
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1943 if (dst != obj) { |
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1944 __ mov(dst, obj); |
0 | 1945 } |
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1946 } else |
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1947 if (code == lir_instanceof) { |
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1948 Register obj = op->object()->as_register(); |
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1949 Register dst = op->result_opr()->as_register(); |
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1950 Label success, failure, done; |
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1951 emit_typecheck_helper(op, &success, &failure, &failure); |
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1952 __ bind(failure); |
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1953 __ xorptr(dst, dst); |
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1954 __ jmpb(done); |
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1955 __ bind(success); |
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1956 __ movptr(dst, 1); |
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1957 __ bind(done); |
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1958 } else { |
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1959 ShouldNotReachHere(); |
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1960 } |
0 | 1961 |
1962 } | |
1963 | |
1964 | |
1965 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { | |
304 | 1966 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) { |
0 | 1967 assert(op->cmp_value()->as_register_lo() == rax, "wrong register"); |
1968 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register"); | |
1969 assert(op->new_value()->as_register_lo() == rbx, "wrong register"); | |
1970 assert(op->new_value()->as_register_hi() == rcx, "wrong register"); | |
1971 Register addr = op->addr()->as_register(); | |
1972 if (os::is_MP()) { | |
1973 __ lock(); | |
1974 } | |
304 | 1975 NOT_LP64(__ cmpxchg8(Address(addr, 0))); |
1976 | |
1977 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) { | |
1978 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");) | |
1979 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); | |
0 | 1980 Register newval = op->new_value()->as_register(); |
1981 Register cmpval = op->cmp_value()->as_register(); | |
1982 assert(cmpval == rax, "wrong register"); | |
1983 assert(newval != NULL, "new val must be register"); | |
1984 assert(cmpval != newval, "cmp and new values must be in different registers"); | |
1985 assert(cmpval != addr, "cmp and addr must be in different registers"); | |
1986 assert(newval != addr, "new value and addr must be in different registers"); | |
2002 | 1987 |
304 | 1988 if ( op->code() == lir_cas_obj) { |
2002 | 1989 #ifdef _LP64 |
1990 if (UseCompressedOops) { | |
1991 __ encode_heap_oop(cmpval); | |
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1992 __ mov(rscratch1, newval); |
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1993 __ encode_heap_oop(rscratch1); |
2002 | 1994 if (os::is_MP()) { |
1995 __ lock(); | |
1996 } | |
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1997 // cmpval (rax) is implicitly used by this instruction |
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1998 __ cmpxchgl(rscratch1, Address(addr, 0)); |
2002 | 1999 } else |
2000 #endif | |
2001 { | |
2002 if (os::is_MP()) { | |
2003 __ lock(); | |
2004 } | |
2005 __ cmpxchgptr(newval, Address(addr, 0)); | |
2006 } | |
2007 } else { | |
2008 assert(op->code() == lir_cas_int, "lir_cas_int expected"); | |
2009 if (os::is_MP()) { | |
2010 __ lock(); | |
2011 } | |
304 | 2012 __ cmpxchgl(newval, Address(addr, 0)); |
2013 } | |
2014 #ifdef _LP64 | |
2015 } else if (op->code() == lir_cas_long) { | |
2016 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); | |
2017 Register newval = op->new_value()->as_register_lo(); | |
2018 Register cmpval = op->cmp_value()->as_register_lo(); | |
2019 assert(cmpval == rax, "wrong register"); | |
2020 assert(newval != NULL, "new val must be register"); | |
2021 assert(cmpval != newval, "cmp and new values must be in different registers"); | |
2022 assert(cmpval != addr, "cmp and addr must be in different registers"); | |
2023 assert(newval != addr, "new value and addr must be in different registers"); | |
2024 if (os::is_MP()) { | |
2025 __ lock(); | |
2026 } | |
2027 __ cmpxchgq(newval, Address(addr, 0)); | |
2028 #endif // _LP64 | |
0 | 2029 } else { |
2030 Unimplemented(); | |
2031 } | |
2032 } | |
2033 | |
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2034 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) { |
0 | 2035 Assembler::Condition acond, ncond; |
2036 switch (condition) { | |
2037 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break; | |
2038 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break; | |
2039 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break; | |
2040 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break; | |
2041 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break; | |
2042 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break; | |
2043 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break; | |
2044 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break; | |
2045 default: ShouldNotReachHere(); | |
2046 } | |
2047 | |
2048 if (opr1->is_cpu_register()) { | |
2049 reg2reg(opr1, result); | |
2050 } else if (opr1->is_stack()) { | |
2051 stack2reg(opr1, result, result->type()); | |
2052 } else if (opr1->is_constant()) { | |
2053 const2reg(opr1, result, lir_patch_none, NULL); | |
2054 } else { | |
2055 ShouldNotReachHere(); | |
2056 } | |
2057 | |
2058 if (VM_Version::supports_cmov() && !opr2->is_constant()) { | |
2059 // optimized version that does not require a branch | |
2060 if (opr2->is_single_cpu()) { | |
2061 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move"); | |
304 | 2062 __ cmov(ncond, result->as_register(), opr2->as_register()); |
0 | 2063 } else if (opr2->is_double_cpu()) { |
2064 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); | |
2065 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); | |
304 | 2066 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo()); |
2067 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());) | |
0 | 2068 } else if (opr2->is_single_stack()) { |
2069 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix())); | |
2070 } else if (opr2->is_double_stack()) { | |
304 | 2071 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes)); |
2072 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));) | |
0 | 2073 } else { |
2074 ShouldNotReachHere(); | |
2075 } | |
2076 | |
2077 } else { | |
2078 Label skip; | |
2079 __ jcc (acond, skip); | |
2080 if (opr2->is_cpu_register()) { | |
2081 reg2reg(opr2, result); | |
2082 } else if (opr2->is_stack()) { | |
2083 stack2reg(opr2, result, result->type()); | |
2084 } else if (opr2->is_constant()) { | |
2085 const2reg(opr2, result, lir_patch_none, NULL); | |
2086 } else { | |
2087 ShouldNotReachHere(); | |
2088 } | |
2089 __ bind(skip); | |
2090 } | |
2091 } | |
2092 | |
2093 | |
2094 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { | |
2095 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); | |
2096 | |
2097 if (left->is_single_cpu()) { | |
2098 assert(left == dest, "left and dest must be equal"); | |
2099 Register lreg = left->as_register(); | |
2100 | |
2101 if (right->is_single_cpu()) { | |
2102 // cpu register - cpu register | |
2103 Register rreg = right->as_register(); | |
2104 switch (code) { | |
2105 case lir_add: __ addl (lreg, rreg); break; | |
2106 case lir_sub: __ subl (lreg, rreg); break; | |
2107 case lir_mul: __ imull(lreg, rreg); break; | |
2108 default: ShouldNotReachHere(); | |
2109 } | |
2110 | |
2111 } else if (right->is_stack()) { | |
2112 // cpu register - stack | |
2113 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); | |
2114 switch (code) { | |
2115 case lir_add: __ addl(lreg, raddr); break; | |
2116 case lir_sub: __ subl(lreg, raddr); break; | |
2117 default: ShouldNotReachHere(); | |
2118 } | |
2119 | |
2120 } else if (right->is_constant()) { | |
2121 // cpu register - constant | |
2122 jint c = right->as_constant_ptr()->as_jint(); | |
2123 switch (code) { | |
2124 case lir_add: { | |
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|
2125 __ incrementl(lreg, c); |
0 | 2126 break; |
2127 } | |
2128 case lir_sub: { | |
1790
7f9553bedfd5
6984056: C1: incorrect code for integer constant addition on x64
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1783
diff
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2129 __ decrementl(lreg, c); |
0 | 2130 break; |
2131 } | |
2132 default: ShouldNotReachHere(); | |
2133 } | |
2134 | |
2135 } else { | |
2136 ShouldNotReachHere(); | |
2137 } | |
2138 | |
2139 } else if (left->is_double_cpu()) { | |
2140 assert(left == dest, "left and dest must be equal"); | |
2141 Register lreg_lo = left->as_register_lo(); | |
2142 Register lreg_hi = left->as_register_hi(); | |
2143 | |
2144 if (right->is_double_cpu()) { | |
2145 // cpu register - cpu register | |
2146 Register rreg_lo = right->as_register_lo(); | |
2147 Register rreg_hi = right->as_register_hi(); | |
304 | 2148 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi)); |
2149 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo)); | |
0 | 2150 switch (code) { |
2151 case lir_add: | |
304 | 2152 __ addptr(lreg_lo, rreg_lo); |
2153 NOT_LP64(__ adcl(lreg_hi, rreg_hi)); | |
0 | 2154 break; |
2155 case lir_sub: | |
304 | 2156 __ subptr(lreg_lo, rreg_lo); |
2157 NOT_LP64(__ sbbl(lreg_hi, rreg_hi)); | |
0 | 2158 break; |
2159 case lir_mul: | |
304 | 2160 #ifdef _LP64 |
2161 __ imulq(lreg_lo, rreg_lo); | |
2162 #else | |
0 | 2163 assert(lreg_lo == rax && lreg_hi == rdx, "must be"); |
2164 __ imull(lreg_hi, rreg_lo); | |
2165 __ imull(rreg_hi, lreg_lo); | |
2166 __ addl (rreg_hi, lreg_hi); | |
2167 __ mull (rreg_lo); | |
2168 __ addl (lreg_hi, rreg_hi); | |
304 | 2169 #endif // _LP64 |
0 | 2170 break; |
2171 default: | |
2172 ShouldNotReachHere(); | |
2173 } | |
2174 | |
2175 } else if (right->is_constant()) { | |
2176 // cpu register - constant | |
304 | 2177 #ifdef _LP64 |
2178 jlong c = right->as_constant_ptr()->as_jlong_bits(); | |
2179 __ movptr(r10, (intptr_t) c); | |
2180 switch (code) { | |
2181 case lir_add: | |
2182 __ addptr(lreg_lo, r10); | |
2183 break; | |
2184 case lir_sub: | |
2185 __ subptr(lreg_lo, r10); | |
2186 break; | |
2187 default: | |
2188 ShouldNotReachHere(); | |
2189 } | |
2190 #else | |
0 | 2191 jint c_lo = right->as_constant_ptr()->as_jint_lo(); |
2192 jint c_hi = right->as_constant_ptr()->as_jint_hi(); | |
2193 switch (code) { | |
2194 case lir_add: | |
304 | 2195 __ addptr(lreg_lo, c_lo); |
0 | 2196 __ adcl(lreg_hi, c_hi); |
2197 break; | |
2198 case lir_sub: | |
304 | 2199 __ subptr(lreg_lo, c_lo); |
0 | 2200 __ sbbl(lreg_hi, c_hi); |
2201 break; | |
2202 default: | |
2203 ShouldNotReachHere(); | |
2204 } | |
304 | 2205 #endif // _LP64 |
0 | 2206 |
2207 } else { | |
2208 ShouldNotReachHere(); | |
2209 } | |
2210 | |
2211 } else if (left->is_single_xmm()) { | |
2212 assert(left == dest, "left and dest must be equal"); | |
2213 XMMRegister lreg = left->as_xmm_float_reg(); | |
2214 | |
2215 if (right->is_single_xmm()) { | |
2216 XMMRegister rreg = right->as_xmm_float_reg(); | |
2217 switch (code) { | |
2218 case lir_add: __ addss(lreg, rreg); break; | |
2219 case lir_sub: __ subss(lreg, rreg); break; | |
2220 case lir_mul_strictfp: // fall through | |
2221 case lir_mul: __ mulss(lreg, rreg); break; | |
2222 case lir_div_strictfp: // fall through | |
2223 case lir_div: __ divss(lreg, rreg); break; | |
2224 default: ShouldNotReachHere(); | |
2225 } | |
2226 } else { | |
2227 Address raddr; | |
2228 if (right->is_single_stack()) { | |
2229 raddr = frame_map()->address_for_slot(right->single_stack_ix()); | |
2230 } else if (right->is_constant()) { | |
2231 // hack for now | |
2232 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat()))); | |
2233 } else { | |
2234 ShouldNotReachHere(); | |
2235 } | |
2236 switch (code) { | |
2237 case lir_add: __ addss(lreg, raddr); break; | |
2238 case lir_sub: __ subss(lreg, raddr); break; | |
2239 case lir_mul_strictfp: // fall through | |
2240 case lir_mul: __ mulss(lreg, raddr); break; | |
2241 case lir_div_strictfp: // fall through | |
2242 case lir_div: __ divss(lreg, raddr); break; | |
2243 default: ShouldNotReachHere(); | |
2244 } | |
2245 } | |
2246 | |
2247 } else if (left->is_double_xmm()) { | |
2248 assert(left == dest, "left and dest must be equal"); | |
2249 | |
2250 XMMRegister lreg = left->as_xmm_double_reg(); | |
2251 if (right->is_double_xmm()) { | |
2252 XMMRegister rreg = right->as_xmm_double_reg(); | |
2253 switch (code) { | |
2254 case lir_add: __ addsd(lreg, rreg); break; | |
2255 case lir_sub: __ subsd(lreg, rreg); break; | |
2256 case lir_mul_strictfp: // fall through | |
2257 case lir_mul: __ mulsd(lreg, rreg); break; | |
2258 case lir_div_strictfp: // fall through | |
2259 case lir_div: __ divsd(lreg, rreg); break; | |
2260 default: ShouldNotReachHere(); | |
2261 } | |
2262 } else { | |
2263 Address raddr; | |
2264 if (right->is_double_stack()) { | |
2265 raddr = frame_map()->address_for_slot(right->double_stack_ix()); | |
2266 } else if (right->is_constant()) { | |
2267 // hack for now | |
2268 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); | |
2269 } else { | |
2270 ShouldNotReachHere(); | |
2271 } | |
2272 switch (code) { | |
2273 case lir_add: __ addsd(lreg, raddr); break; | |
2274 case lir_sub: __ subsd(lreg, raddr); break; | |
2275 case lir_mul_strictfp: // fall through | |
2276 case lir_mul: __ mulsd(lreg, raddr); break; | |
2277 case lir_div_strictfp: // fall through | |
2278 case lir_div: __ divsd(lreg, raddr); break; | |
2279 default: ShouldNotReachHere(); | |
2280 } | |
2281 } | |
2282 | |
2283 } else if (left->is_single_fpu()) { | |
2284 assert(dest->is_single_fpu(), "fpu stack allocation required"); | |
2285 | |
2286 if (right->is_single_fpu()) { | |
2287 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack); | |
2288 | |
2289 } else { | |
2290 assert(left->fpu_regnr() == 0, "left must be on TOS"); | |
2291 assert(dest->fpu_regnr() == 0, "dest must be on TOS"); | |
2292 | |
2293 Address raddr; | |
2294 if (right->is_single_stack()) { | |
2295 raddr = frame_map()->address_for_slot(right->single_stack_ix()); | |
2296 } else if (right->is_constant()) { | |
2297 address const_addr = float_constant(right->as_jfloat()); | |
2298 assert(const_addr != NULL, "incorrect float/double constant maintainance"); | |
2299 // hack for now | |
2300 raddr = __ as_Address(InternalAddress(const_addr)); | |
2301 } else { | |
2302 ShouldNotReachHere(); | |
2303 } | |
2304 | |
2305 switch (code) { | |
2306 case lir_add: __ fadd_s(raddr); break; | |
2307 case lir_sub: __ fsub_s(raddr); break; | |
2308 case lir_mul_strictfp: // fall through | |
2309 case lir_mul: __ fmul_s(raddr); break; | |
2310 case lir_div_strictfp: // fall through | |
2311 case lir_div: __ fdiv_s(raddr); break; | |
2312 default: ShouldNotReachHere(); | |
2313 } | |
2314 } | |
2315 | |
2316 } else if (left->is_double_fpu()) { | |
2317 assert(dest->is_double_fpu(), "fpu stack allocation required"); | |
2318 | |
2319 if (code == lir_mul_strictfp || code == lir_div_strictfp) { | |
2320 // Double values require special handling for strictfp mul/div on x86 | |
2321 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1())); | |
2322 __ fmulp(left->fpu_regnrLo() + 1); | |
2323 } | |
2324 | |
2325 if (right->is_double_fpu()) { | |
2326 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack); | |
2327 | |
2328 } else { | |
2329 assert(left->fpu_regnrLo() == 0, "left must be on TOS"); | |
2330 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS"); | |
2331 | |
2332 Address raddr; | |
2333 if (right->is_double_stack()) { | |
2334 raddr = frame_map()->address_for_slot(right->double_stack_ix()); | |
2335 } else if (right->is_constant()) { | |
2336 // hack for now | |
2337 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); | |
2338 } else { | |
2339 ShouldNotReachHere(); | |
2340 } | |
2341 | |
2342 switch (code) { | |
2343 case lir_add: __ fadd_d(raddr); break; | |
2344 case lir_sub: __ fsub_d(raddr); break; | |
2345 case lir_mul_strictfp: // fall through | |
2346 case lir_mul: __ fmul_d(raddr); break; | |
2347 case lir_div_strictfp: // fall through | |
2348 case lir_div: __ fdiv_d(raddr); break; | |
2349 default: ShouldNotReachHere(); | |
2350 } | |
2351 } | |
2352 | |
2353 if (code == lir_mul_strictfp || code == lir_div_strictfp) { | |
2354 // Double values require special handling for strictfp mul/div on x86 | |
2355 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2())); | |
2356 __ fmulp(dest->fpu_regnrLo() + 1); | |
2357 } | |
2358 | |
2359 } else if (left->is_single_stack() || left->is_address()) { | |
2360 assert(left == dest, "left and dest must be equal"); | |
2361 | |
2362 Address laddr; | |
2363 if (left->is_single_stack()) { | |
2364 laddr = frame_map()->address_for_slot(left->single_stack_ix()); | |
2365 } else if (left->is_address()) { | |
2366 laddr = as_Address(left->as_address_ptr()); | |
2367 } else { | |
2368 ShouldNotReachHere(); | |
2369 } | |
2370 | |
2371 if (right->is_single_cpu()) { | |
2372 Register rreg = right->as_register(); | |
2373 switch (code) { | |
2374 case lir_add: __ addl(laddr, rreg); break; | |
2375 case lir_sub: __ subl(laddr, rreg); break; | |
2376 default: ShouldNotReachHere(); | |
2377 } | |
2378 } else if (right->is_constant()) { | |
2379 jint c = right->as_constant_ptr()->as_jint(); | |
2380 switch (code) { | |
2381 case lir_add: { | |
304 | 2382 __ incrementl(laddr, c); |
0 | 2383 break; |
2384 } | |
2385 case lir_sub: { | |
304 | 2386 __ decrementl(laddr, c); |
0 | 2387 break; |
2388 } | |
2389 default: ShouldNotReachHere(); | |
2390 } | |
2391 } else { | |
2392 ShouldNotReachHere(); | |
2393 } | |
2394 | |
2395 } else { | |
2396 ShouldNotReachHere(); | |
2397 } | |
2398 } | |
2399 | |
2400 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { | |
2401 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR"); | |
2402 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR"); | |
2403 assert(left_index == 0 || right_index == 0, "either must be on top of stack"); | |
2404 | |
2405 bool left_is_tos = (left_index == 0); | |
2406 bool dest_is_tos = (dest_index == 0); | |
2407 int non_tos_index = (left_is_tos ? right_index : left_index); | |
2408 | |
2409 switch (code) { | |
2410 case lir_add: | |
2411 if (pop_fpu_stack) __ faddp(non_tos_index); | |
2412 else if (dest_is_tos) __ fadd (non_tos_index); | |
2413 else __ fadda(non_tos_index); | |
2414 break; | |
2415 | |
2416 case lir_sub: | |
2417 if (left_is_tos) { | |
2418 if (pop_fpu_stack) __ fsubrp(non_tos_index); | |
2419 else if (dest_is_tos) __ fsub (non_tos_index); | |
2420 else __ fsubra(non_tos_index); | |
2421 } else { | |
2422 if (pop_fpu_stack) __ fsubp (non_tos_index); | |
2423 else if (dest_is_tos) __ fsubr (non_tos_index); | |
2424 else __ fsuba (non_tos_index); | |
2425 } | |
2426 break; | |
2427 | |
2428 case lir_mul_strictfp: // fall through | |
2429 case lir_mul: | |
2430 if (pop_fpu_stack) __ fmulp(non_tos_index); | |
2431 else if (dest_is_tos) __ fmul (non_tos_index); | |
2432 else __ fmula(non_tos_index); | |
2433 break; | |
2434 | |
2435 case lir_div_strictfp: // fall through | |
2436 case lir_div: | |
2437 if (left_is_tos) { | |
2438 if (pop_fpu_stack) __ fdivrp(non_tos_index); | |
2439 else if (dest_is_tos) __ fdiv (non_tos_index); | |
2440 else __ fdivra(non_tos_index); | |
2441 } else { | |
2442 if (pop_fpu_stack) __ fdivp (non_tos_index); | |
2443 else if (dest_is_tos) __ fdivr (non_tos_index); | |
2444 else __ fdiva (non_tos_index); | |
2445 } | |
2446 break; | |
2447 | |
2448 case lir_rem: | |
2449 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation"); | |
2450 __ fremr(noreg); | |
2451 break; | |
2452 | |
2453 default: | |
2454 ShouldNotReachHere(); | |
2455 } | |
2456 } | |
2457 | |
2458 | |
2459 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) { | |
2460 if (value->is_double_xmm()) { | |
2461 switch(code) { | |
2462 case lir_abs : | |
2463 { | |
2464 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) { | |
2465 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); | |
2466 } | |
2467 __ andpd(dest->as_xmm_double_reg(), | |
2468 ExternalAddress((address)double_signmask_pool)); | |
2469 } | |
2470 break; | |
2471 | |
2472 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break; | |
2473 // all other intrinsics are not available in the SSE instruction set, so FPU is used | |
2474 default : ShouldNotReachHere(); | |
2475 } | |
2476 | |
2477 } else if (value->is_double_fpu()) { | |
2478 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS"); | |
2479 switch(code) { | |
2480 case lir_log : __ flog() ; break; | |
2481 case lir_log10 : __ flog10() ; break; | |
2482 case lir_abs : __ fabs() ; break; | |
2483 case lir_sqrt : __ fsqrt(); break; | |
2484 case lir_sin : | |
2485 // Should consider not saving rbx, if not necessary | |
2486 __ trigfunc('s', op->as_Op2()->fpu_stack_size()); | |
2487 break; | |
2488 case lir_cos : | |
2489 // Should consider not saving rbx, if not necessary | |
2490 assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots"); | |
2491 __ trigfunc('c', op->as_Op2()->fpu_stack_size()); | |
2492 break; | |
2493 case lir_tan : | |
2494 // Should consider not saving rbx, if not necessary | |
2495 __ trigfunc('t', op->as_Op2()->fpu_stack_size()); | |
2496 break; | |
6084
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|
2497 case lir_exp : |
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|
2498 __ exp_with_fallback(op->as_Op2()->fpu_stack_size()); |
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|
2499 break; |
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|
2500 case lir_pow : |
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2501 __ pow_with_fallback(op->as_Op2()->fpu_stack_size()); |
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|
2502 break; |
0 | 2503 default : ShouldNotReachHere(); |
2504 } | |
2505 } else { | |
2506 Unimplemented(); | |
2507 } | |
2508 } | |
2509 | |
2510 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { | |
2511 // assert(left->destroys_register(), "check"); | |
2512 if (left->is_single_cpu()) { | |
2513 Register reg = left->as_register(); | |
2514 if (right->is_constant()) { | |
2515 int val = right->as_constant_ptr()->as_jint(); | |
2516 switch (code) { | |
2517 case lir_logic_and: __ andl (reg, val); break; | |
2518 case lir_logic_or: __ orl (reg, val); break; | |
2519 case lir_logic_xor: __ xorl (reg, val); break; | |
2520 default: ShouldNotReachHere(); | |
2521 } | |
2522 } else if (right->is_stack()) { | |
2523 // added support for stack operands | |
2524 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); | |
2525 switch (code) { | |
2526 case lir_logic_and: __ andl (reg, raddr); break; | |
2527 case lir_logic_or: __ orl (reg, raddr); break; | |
2528 case lir_logic_xor: __ xorl (reg, raddr); break; | |
2529 default: ShouldNotReachHere(); | |
2530 } | |
2531 } else { | |
2532 Register rright = right->as_register(); | |
2533 switch (code) { | |
304 | 2534 case lir_logic_and: __ andptr (reg, rright); break; |
2535 case lir_logic_or : __ orptr (reg, rright); break; | |
2536 case lir_logic_xor: __ xorptr (reg, rright); break; | |
0 | 2537 default: ShouldNotReachHere(); |
2538 } | |
2539 } | |
2540 move_regs(reg, dst->as_register()); | |
2541 } else { | |
2542 Register l_lo = left->as_register_lo(); | |
2543 Register l_hi = left->as_register_hi(); | |
2544 if (right->is_constant()) { | |
304 | 2545 #ifdef _LP64 |
2546 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong()); | |
2547 switch (code) { | |
2548 case lir_logic_and: | |
2549 __ andq(l_lo, rscratch1); | |
2550 break; | |
2551 case lir_logic_or: | |
2552 __ orq(l_lo, rscratch1); | |
2553 break; | |
2554 case lir_logic_xor: | |
2555 __ xorq(l_lo, rscratch1); | |
2556 break; | |
2557 default: ShouldNotReachHere(); | |
2558 } | |
2559 #else | |
0 | 2560 int r_lo = right->as_constant_ptr()->as_jint_lo(); |
2561 int r_hi = right->as_constant_ptr()->as_jint_hi(); | |
2562 switch (code) { | |
2563 case lir_logic_and: | |
2564 __ andl(l_lo, r_lo); | |
2565 __ andl(l_hi, r_hi); | |
2566 break; | |
2567 case lir_logic_or: | |
2568 __ orl(l_lo, r_lo); | |
2569 __ orl(l_hi, r_hi); | |
2570 break; | |
2571 case lir_logic_xor: | |
2572 __ xorl(l_lo, r_lo); | |
2573 __ xorl(l_hi, r_hi); | |
2574 break; | |
2575 default: ShouldNotReachHere(); | |
2576 } | |
304 | 2577 #endif // _LP64 |
0 | 2578 } else { |
1572 | 2579 #ifdef _LP64 |
2580 Register r_lo; | |
2581 if (right->type() == T_OBJECT || right->type() == T_ARRAY) { | |
2582 r_lo = right->as_register(); | |
2583 } else { | |
2584 r_lo = right->as_register_lo(); | |
2585 } | |
2586 #else | |
0 | 2587 Register r_lo = right->as_register_lo(); |
2588 Register r_hi = right->as_register_hi(); | |
2589 assert(l_lo != r_hi, "overwriting registers"); | |
1572 | 2590 #endif |
0 | 2591 switch (code) { |
2592 case lir_logic_and: | |
304 | 2593 __ andptr(l_lo, r_lo); |
2594 NOT_LP64(__ andptr(l_hi, r_hi);) | |
0 | 2595 break; |
2596 case lir_logic_or: | |
304 | 2597 __ orptr(l_lo, r_lo); |
2598 NOT_LP64(__ orptr(l_hi, r_hi);) | |
0 | 2599 break; |
2600 case lir_logic_xor: | |
304 | 2601 __ xorptr(l_lo, r_lo); |
2602 NOT_LP64(__ xorptr(l_hi, r_hi);) | |
0 | 2603 break; |
2604 default: ShouldNotReachHere(); | |
2605 } | |
2606 } | |
2607 | |
2608 Register dst_lo = dst->as_register_lo(); | |
2609 Register dst_hi = dst->as_register_hi(); | |
2610 | |
304 | 2611 #ifdef _LP64 |
2612 move_regs(l_lo, dst_lo); | |
2613 #else | |
0 | 2614 if (dst_lo == l_hi) { |
2615 assert(dst_hi != l_lo, "overwriting registers"); | |
2616 move_regs(l_hi, dst_hi); | |
2617 move_regs(l_lo, dst_lo); | |
2618 } else { | |
2619 assert(dst_lo != l_hi, "overwriting registers"); | |
2620 move_regs(l_lo, dst_lo); | |
2621 move_regs(l_hi, dst_hi); | |
2622 } | |
304 | 2623 #endif // _LP64 |
0 | 2624 } |
2625 } | |
2626 | |
2627 | |
2628 // we assume that rax, and rdx can be overwritten | |
2629 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { | |
2630 | |
2631 assert(left->is_single_cpu(), "left must be register"); | |
2632 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant"); | |
2633 assert(result->is_single_cpu(), "result must be register"); | |
2634 | |
2635 // assert(left->destroys_register(), "check"); | |
2636 // assert(right->destroys_register(), "check"); | |
2637 | |
2638 Register lreg = left->as_register(); | |
2639 Register dreg = result->as_register(); | |
2640 | |
2641 if (right->is_constant()) { | |
2642 int divisor = right->as_constant_ptr()->as_jint(); | |
2643 assert(divisor > 0 && is_power_of_2(divisor), "must be"); | |
2644 if (code == lir_idiv) { | |
2645 assert(lreg == rax, "must be rax,"); | |
2646 assert(temp->as_register() == rdx, "tmp register must be rdx"); | |
2647 __ cdql(); // sign extend into rdx:rax | |
2648 if (divisor == 2) { | |
2649 __ subl(lreg, rdx); | |
2650 } else { | |
2651 __ andl(rdx, divisor - 1); | |
2652 __ addl(lreg, rdx); | |
2653 } | |
2654 __ sarl(lreg, log2_intptr(divisor)); | |
2655 move_regs(lreg, dreg); | |
2656 } else if (code == lir_irem) { | |
2657 Label done; | |
304 | 2658 __ mov(dreg, lreg); |
0 | 2659 __ andl(dreg, 0x80000000 | (divisor - 1)); |
2660 __ jcc(Assembler::positive, done); | |
2661 __ decrement(dreg); | |
2662 __ orl(dreg, ~(divisor - 1)); | |
2663 __ increment(dreg); | |
2664 __ bind(done); | |
2665 } else { | |
2666 ShouldNotReachHere(); | |
2667 } | |
2668 } else { | |
2669 Register rreg = right->as_register(); | |
2670 assert(lreg == rax, "left register must be rax,"); | |
2671 assert(rreg != rdx, "right register must not be rdx"); | |
2672 assert(temp->as_register() == rdx, "tmp register must be rdx"); | |
2673 | |
2674 move_regs(lreg, rax); | |
2675 | |
2676 int idivl_offset = __ corrected_idivl(rreg); | |
2677 add_debug_info_for_div0(idivl_offset, info); | |
2678 if (code == lir_irem) { | |
2679 move_regs(rdx, dreg); // result is in rdx | |
2680 } else { | |
2681 move_regs(rax, dreg); | |
2682 } | |
2683 } | |
2684 } | |
2685 | |
2686 | |
2687 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { | |
2688 if (opr1->is_single_cpu()) { | |
2689 Register reg1 = opr1->as_register(); | |
2690 if (opr2->is_single_cpu()) { | |
2691 // cpu register - cpu register | |
304 | 2692 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { |
2693 __ cmpptr(reg1, opr2->as_register()); | |
2694 } else { | |
2695 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?"); | |
2696 __ cmpl(reg1, opr2->as_register()); | |
2697 } | |
0 | 2698 } else if (opr2->is_stack()) { |
2699 // cpu register - stack | |
304 | 2700 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { |
2701 __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); | |
2702 } else { | |
2703 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); | |
2704 } | |
0 | 2705 } else if (opr2->is_constant()) { |
2706 // cpu register - constant | |
2707 LIR_Const* c = opr2->as_constant_ptr(); | |
2708 if (c->type() == T_INT) { | |
2709 __ cmpl(reg1, c->as_jint()); | |
304 | 2710 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { |
2711 // In 64bit oops are single register | |
0 | 2712 jobject o = c->as_jobject(); |
2713 if (o == NULL) { | |
304 | 2714 __ cmpptr(reg1, (int32_t)NULL_WORD); |
0 | 2715 } else { |
304 | 2716 #ifdef _LP64 |
2717 __ movoop(rscratch1, o); | |
2718 __ cmpptr(reg1, rscratch1); | |
2719 #else | |
0 | 2720 __ cmpoop(reg1, c->as_jobject()); |
304 | 2721 #endif // _LP64 |
0 | 2722 } |
2723 } else { | |
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2724 fatal(err_msg("unexpected type: %s", basictype_to_str(c->type()))); |
0 | 2725 } |
2726 // cpu register - address | |
2727 } else if (opr2->is_address()) { | |
2728 if (op->info() != NULL) { | |
2729 add_debug_info_for_null_check_here(op->info()); | |
2730 } | |
2731 __ cmpl(reg1, as_Address(opr2->as_address_ptr())); | |
2732 } else { | |
2733 ShouldNotReachHere(); | |
2734 } | |
2735 | |
2736 } else if(opr1->is_double_cpu()) { | |
2737 Register xlo = opr1->as_register_lo(); | |
2738 Register xhi = opr1->as_register_hi(); | |
2739 if (opr2->is_double_cpu()) { | |
304 | 2740 #ifdef _LP64 |
2741 __ cmpptr(xlo, opr2->as_register_lo()); | |
2742 #else | |
0 | 2743 // cpu register - cpu register |
2744 Register ylo = opr2->as_register_lo(); | |
2745 Register yhi = opr2->as_register_hi(); | |
2746 __ subl(xlo, ylo); | |
2747 __ sbbl(xhi, yhi); | |
2748 if (condition == lir_cond_equal || condition == lir_cond_notEqual) { | |
2749 __ orl(xhi, xlo); | |
2750 } | |
304 | 2751 #endif // _LP64 |
0 | 2752 } else if (opr2->is_constant()) { |
2753 // cpu register - constant 0 | |
2754 assert(opr2->as_jlong() == (jlong)0, "only handles zero"); | |
304 | 2755 #ifdef _LP64 |
2756 __ cmpptr(xlo, (int32_t)opr2->as_jlong()); | |
2757 #else | |
0 | 2758 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case"); |
2759 __ orl(xhi, xlo); | |
304 | 2760 #endif // _LP64 |
0 | 2761 } else { |
2762 ShouldNotReachHere(); | |
2763 } | |
2764 | |
2765 } else if (opr1->is_single_xmm()) { | |
2766 XMMRegister reg1 = opr1->as_xmm_float_reg(); | |
2767 if (opr2->is_single_xmm()) { | |
2768 // xmm register - xmm register | |
2769 __ ucomiss(reg1, opr2->as_xmm_float_reg()); | |
2770 } else if (opr2->is_stack()) { | |
2771 // xmm register - stack | |
2772 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); | |
2773 } else if (opr2->is_constant()) { | |
2774 // xmm register - constant | |
2775 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat()))); | |
2776 } else if (opr2->is_address()) { | |
2777 // xmm register - address | |
2778 if (op->info() != NULL) { | |
2779 add_debug_info_for_null_check_here(op->info()); | |
2780 } | |
2781 __ ucomiss(reg1, as_Address(opr2->as_address_ptr())); | |
2782 } else { | |
2783 ShouldNotReachHere(); | |
2784 } | |
2785 | |
2786 } else if (opr1->is_double_xmm()) { | |
2787 XMMRegister reg1 = opr1->as_xmm_double_reg(); | |
2788 if (opr2->is_double_xmm()) { | |
2789 // xmm register - xmm register | |
2790 __ ucomisd(reg1, opr2->as_xmm_double_reg()); | |
2791 } else if (opr2->is_stack()) { | |
2792 // xmm register - stack | |
2793 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix())); | |
2794 } else if (opr2->is_constant()) { | |
2795 // xmm register - constant | |
2796 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble()))); | |
2797 } else if (opr2->is_address()) { | |
2798 // xmm register - address | |
2799 if (op->info() != NULL) { | |
2800 add_debug_info_for_null_check_here(op->info()); | |
2801 } | |
2802 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address())); | |
2803 } else { | |
2804 ShouldNotReachHere(); | |
2805 } | |
2806 | |
2807 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) { | |
2808 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)"); | |
2809 assert(opr2->is_fpu_register(), "both must be registers"); | |
2810 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); | |
2811 | |
2812 } else if (opr1->is_address() && opr2->is_constant()) { | |
304 | 2813 LIR_Const* c = opr2->as_constant_ptr(); |
2814 #ifdef _LP64 | |
2815 if (c->type() == T_OBJECT || c->type() == T_ARRAY) { | |
2816 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse"); | |
2817 __ movoop(rscratch1, c->as_jobject()); | |
2818 } | |
2819 #endif // LP64 | |
0 | 2820 if (op->info() != NULL) { |
2821 add_debug_info_for_null_check_here(op->info()); | |
2822 } | |
2823 // special case: address - constant | |
2824 LIR_Address* addr = opr1->as_address_ptr(); | |
2825 if (c->type() == T_INT) { | |
2826 __ cmpl(as_Address(addr), c->as_jint()); | |
304 | 2827 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { |
2828 #ifdef _LP64 | |
2829 // %%% Make this explode if addr isn't reachable until we figure out a | |
2830 // better strategy by giving noreg as the temp for as_Address | |
2831 __ cmpptr(rscratch1, as_Address(addr, noreg)); | |
2832 #else | |
0 | 2833 __ cmpoop(as_Address(addr), c->as_jobject()); |
304 | 2834 #endif // _LP64 |
0 | 2835 } else { |
2836 ShouldNotReachHere(); | |
2837 } | |
2838 | |
2839 } else { | |
2840 ShouldNotReachHere(); | |
2841 } | |
2842 } | |
2843 | |
2844 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) { | |
2845 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { | |
2846 if (left->is_single_xmm()) { | |
2847 assert(right->is_single_xmm(), "must match"); | |
2848 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i); | |
2849 } else if (left->is_double_xmm()) { | |
2850 assert(right->is_double_xmm(), "must match"); | |
2851 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i); | |
2852 | |
2853 } else { | |
2854 assert(left->is_single_fpu() || left->is_double_fpu(), "must be"); | |
2855 assert(right->is_single_fpu() || right->is_double_fpu(), "must match"); | |
2856 | |
2857 assert(left->fpu() == 0, "left must be on TOS"); | |
2858 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(), | |
2859 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); | |
2860 } | |
2861 } else { | |
2862 assert(code == lir_cmp_l2i, "check"); | |
304 | 2863 #ifdef _LP64 |
1369 | 2864 Label done; |
2865 Register dest = dst->as_register(); | |
2866 __ cmpptr(left->as_register_lo(), right->as_register_lo()); | |
2867 __ movl(dest, -1); | |
2868 __ jccb(Assembler::less, done); | |
2869 __ set_byte_if_not_zero(dest); | |
2870 __ movzbl(dest, dest); | |
2871 __ bind(done); | |
304 | 2872 #else |
0 | 2873 __ lcmp2int(left->as_register_hi(), |
2874 left->as_register_lo(), | |
2875 right->as_register_hi(), | |
2876 right->as_register_lo()); | |
2877 move_regs(left->as_register_hi(), dst->as_register()); | |
304 | 2878 #endif // _LP64 |
0 | 2879 } |
2880 } | |
2881 | |
2882 | |
2883 void LIR_Assembler::align_call(LIR_Code code) { | |
2884 if (os::is_MP()) { | |
2885 // make sure that the displacement word of the call ends up word aligned | |
2886 int offset = __ offset(); | |
2887 switch (code) { | |
2888 case lir_static_call: | |
2889 case lir_optvirtual_call: | |
1295 | 2890 case lir_dynamic_call: |
0 | 2891 offset += NativeCall::displacement_offset; |
2892 break; | |
2893 case lir_icvirtual_call: | |
2894 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size; | |
2895 break; | |
2896 case lir_virtual_call: // currently, sparc-specific for niagara | |
2897 default: ShouldNotReachHere(); | |
2898 } | |
2899 while (offset++ % BytesPerWord != 0) { | |
2900 __ nop(); | |
2901 } | |
2902 } | |
2903 } | |
2904 | |
2905 | |
1295 | 2906 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { |
0 | 2907 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, |
2908 "must be aligned"); | |
1295 | 2909 __ call(AddressLiteral(op->addr(), rtype)); |
1564 | 2910 add_call_info(code_offset(), op->info()); |
0 | 2911 } |
2912 | |
2913 | |
1295 | 2914 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { |
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2915 __ ic_call(op->addr()); |
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2916 add_call_info(code_offset(), op->info()); |
0 | 2917 assert(!os::is_MP() || |
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2918 (__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0, |
0 | 2919 "must be aligned"); |
2920 } | |
2921 | |
2922 | |
2923 /* Currently, vtable-dispatch is only enabled for sparc platforms */ | |
1295 | 2924 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) { |
0 | 2925 ShouldNotReachHere(); |
2926 } | |
2927 | |
1295 | 2928 |
0 | 2929 void LIR_Assembler::emit_static_call_stub() { |
2930 address call_pc = __ pc(); | |
2931 address stub = __ start_a_stub(call_stub_size); | |
2932 if (stub == NULL) { | |
2933 bailout("static call stub overflow"); | |
2934 return; | |
2935 } | |
2936 | |
2937 int start = __ offset(); | |
2938 if (os::is_MP()) { | |
2939 // make sure that the displacement word of the call ends up word aligned | |
2940 int offset = __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset; | |
2941 while (offset++ % BytesPerWord != 0) { | |
2942 __ nop(); | |
2943 } | |
2944 } | |
2945 __ relocate(static_stub_Relocation::spec(call_pc)); | |
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2946 __ mov_metadata(rbx, (Metadata*)NULL); |
0 | 2947 // must be set to -1 at code generation time |
2948 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP"); | |
304 | 2949 // On 64bit this will die since it will take a movq & jmp, must be only a jmp |
2950 __ jump(RuntimeAddress(__ pc())); | |
0 | 2951 |
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2952 assert(__ offset() - start <= call_stub_size, "stub too big"); |
0 | 2953 __ end_a_stub(); |
2954 } | |
2955 | |
2956 | |
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2957 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { |
0 | 2958 assert(exceptionOop->as_register() == rax, "must match"); |
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2959 assert(exceptionPC->as_register() == rdx, "must match"); |
0 | 2960 |
2961 // exception object is not added to oop map by LinearScan | |
2962 // (LinearScan assumes that no oops are in fixed registers) | |
2963 info->add_register_oop(exceptionOop); | |
2964 Runtime1::StubID unwind_id; | |
2965 | |
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2966 // get current pc information |
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2967 // pc is only needed if the method has an exception handler, the unwind code does not need it. |
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2968 int pc_for_athrow_offset = __ offset(); |
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2969 InternalAddress pc_for_athrow(__ pc()); |
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2970 __ lea(exceptionPC->as_register(), pc_for_athrow); |
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2971 add_call_info(pc_for_athrow_offset, info); // for exception handler |
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2972 |
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2973 __ verify_not_null_oop(rax); |
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2974 // search an exception handler (rax: exception oop, rdx: throwing pc) |
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2975 if (compilation()->has_fpu_code()) { |
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2976 unwind_id = Runtime1::handle_exception_id; |
0 | 2977 } else { |
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2978 unwind_id = Runtime1::handle_exception_nofpu_id; |
0 | 2979 } |
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2980 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id))); |
0 | 2981 |
2982 // enough room for two byte trap | |
2983 __ nop(); | |
2984 } | |
2985 | |
2986 | |
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2987 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { |
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2988 assert(exceptionOop->as_register() == rax, "must match"); |
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2989 |
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2990 __ jmp(_unwind_handler_entry); |
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2991 } |
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2992 |
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2993 |
0 | 2994 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { |
2995 | |
2996 // optimized version for linear scan: | |
2997 // * count must be already in ECX (guaranteed by LinearScan) | |
2998 // * left and dest must be equal | |
2999 // * tmp must be unused | |
3000 assert(count->as_register() == SHIFT_count, "count must be in ECX"); | |
3001 assert(left == dest, "left and dest must be equal"); | |
3002 assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); | |
3003 | |
3004 if (left->is_single_cpu()) { | |
3005 Register value = left->as_register(); | |
3006 assert(value != SHIFT_count, "left cannot be ECX"); | |
3007 | |
3008 switch (code) { | |
3009 case lir_shl: __ shll(value); break; | |
3010 case lir_shr: __ sarl(value); break; | |
3011 case lir_ushr: __ shrl(value); break; | |
3012 default: ShouldNotReachHere(); | |
3013 } | |
3014 } else if (left->is_double_cpu()) { | |
3015 Register lo = left->as_register_lo(); | |
3016 Register hi = left->as_register_hi(); | |
3017 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX"); | |
304 | 3018 #ifdef _LP64 |
3019 switch (code) { | |
3020 case lir_shl: __ shlptr(lo); break; | |
3021 case lir_shr: __ sarptr(lo); break; | |
3022 case lir_ushr: __ shrptr(lo); break; | |
3023 default: ShouldNotReachHere(); | |
3024 } | |
3025 #else | |
0 | 3026 |
3027 switch (code) { | |
3028 case lir_shl: __ lshl(hi, lo); break; | |
3029 case lir_shr: __ lshr(hi, lo, true); break; | |
3030 case lir_ushr: __ lshr(hi, lo, false); break; | |
3031 default: ShouldNotReachHere(); | |
3032 } | |
304 | 3033 #endif // LP64 |
0 | 3034 } else { |
3035 ShouldNotReachHere(); | |
3036 } | |
3037 } | |
3038 | |
3039 | |
3040 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { | |
3041 if (dest->is_single_cpu()) { | |
3042 // first move left into dest so that left is not destroyed by the shift | |
3043 Register value = dest->as_register(); | |
3044 count = count & 0x1F; // Java spec | |
3045 | |
3046 move_regs(left->as_register(), value); | |
3047 switch (code) { | |
3048 case lir_shl: __ shll(value, count); break; | |
3049 case lir_shr: __ sarl(value, count); break; | |
3050 case lir_ushr: __ shrl(value, count); break; | |
3051 default: ShouldNotReachHere(); | |
3052 } | |
3053 } else if (dest->is_double_cpu()) { | |
304 | 3054 #ifndef _LP64 |
0 | 3055 Unimplemented(); |
304 | 3056 #else |
3057 // first move left into dest so that left is not destroyed by the shift | |
3058 Register value = dest->as_register_lo(); | |
3059 count = count & 0x1F; // Java spec | |
3060 | |
3061 move_regs(left->as_register_lo(), value); | |
3062 switch (code) { | |
3063 case lir_shl: __ shlptr(value, count); break; | |
3064 case lir_shr: __ sarptr(value, count); break; | |
3065 case lir_ushr: __ shrptr(value, count); break; | |
3066 default: ShouldNotReachHere(); | |
3067 } | |
3068 #endif // _LP64 | |
0 | 3069 } else { |
3070 ShouldNotReachHere(); | |
3071 } | |
3072 } | |
3073 | |
3074 | |
3075 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) { | |
3076 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); | |
3077 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; | |
3078 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); | |
304 | 3079 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r); |
0 | 3080 } |
3081 | |
3082 | |
3083 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) { | |
3084 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); | |
3085 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; | |
3086 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); | |
304 | 3087 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c); |
0 | 3088 } |
3089 | |
3090 | |
3091 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) { | |
3092 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); | |
3093 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; | |
3094 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); | |
3095 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o); | |
3096 } | |
3097 | |
3098 | |
3099 // This code replaces a call to arraycopy; no exception may | |
3100 // be thrown in this code, they must be thrown in the System.arraycopy | |
3101 // activation frame; we could save some checks if this would not be the case | |
3102 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { | |
3103 ciArrayKlass* default_type = op->expected_type(); | |
3104 Register src = op->src()->as_register(); | |
3105 Register dst = op->dst()->as_register(); | |
3106 Register src_pos = op->src_pos()->as_register(); | |
3107 Register dst_pos = op->dst_pos()->as_register(); | |
3108 Register length = op->length()->as_register(); | |
3109 Register tmp = op->tmp()->as_register(); | |
3110 | |
3111 CodeStub* stub = op->stub(); | |
3112 int flags = op->flags(); | |
3113 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; | |
3114 if (basic_type == T_ARRAY) basic_type = T_OBJECT; | |
3115 | |
2446 | 3116 // if we don't know anything, just go through the generic arraycopy |
0 | 3117 if (default_type == NULL) { |
3118 Label done; | |
3119 // save outgoing arguments on stack in case call to System.arraycopy is needed | |
3120 // HACK ALERT. This code used to push the parameters in a hardwired fashion | |
3121 // for interpreter calling conventions. Now we have to do it in new style conventions. | |
3122 // For the moment until C1 gets the new register allocator I just force all the | |
3123 // args to the right place (except the register args) and then on the back side | |
3124 // reload the register args properly if we go slow path. Yuck | |
3125 | |
3126 // These are proper for the calling convention | |
3127 store_parameter(length, 2); | |
3128 store_parameter(dst_pos, 1); | |
3129 store_parameter(dst, 0); | |
3130 | |
3131 // these are just temporary placements until we need to reload | |
3132 store_parameter(src_pos, 3); | |
3133 store_parameter(src, 4); | |
304 | 3134 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");) |
3135 | |
2446 | 3136 address C_entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy); |
3137 | |
3138 address copyfunc_addr = StubRoutines::generic_arraycopy(); | |
0 | 3139 |
3140 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint | |
304 | 3141 #ifdef _LP64 |
3142 // The arguments are in java calling convention so we can trivially shift them to C | |
3143 // convention | |
3144 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4); | |
3145 __ mov(c_rarg0, j_rarg0); | |
3146 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4); | |
3147 __ mov(c_rarg1, j_rarg1); | |
3148 assert_different_registers(c_rarg2, j_rarg3, j_rarg4); | |
3149 __ mov(c_rarg2, j_rarg2); | |
3150 assert_different_registers(c_rarg3, j_rarg4); | |
3151 __ mov(c_rarg3, j_rarg3); | |
3152 #ifdef _WIN64 | |
3153 // Allocate abi space for args but be sure to keep stack aligned | |
3154 __ subptr(rsp, 6*wordSize); | |
3155 store_parameter(j_rarg4, 4); | |
2446 | 3156 if (copyfunc_addr == NULL) { // Use C version if stub was not generated |
3157 __ call(RuntimeAddress(C_entry)); | |
3158 } else { | |
3159 #ifndef PRODUCT | |
3160 if (PrintC1Statistics) { | |
3161 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); | |
3162 } | |
3163 #endif | |
3164 __ call(RuntimeAddress(copyfunc_addr)); | |
3165 } | |
304 | 3166 __ addptr(rsp, 6*wordSize); |
3167 #else | |
3168 __ mov(c_rarg4, j_rarg4); | |
2446 | 3169 if (copyfunc_addr == NULL) { // Use C version if stub was not generated |
3170 __ call(RuntimeAddress(C_entry)); | |
3171 } else { | |
3172 #ifndef PRODUCT | |
3173 if (PrintC1Statistics) { | |
3174 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); | |
3175 } | |
3176 #endif | |
3177 __ call(RuntimeAddress(copyfunc_addr)); | |
3178 } | |
304 | 3179 #endif // _WIN64 |
3180 #else | |
3181 __ push(length); | |
3182 __ push(dst_pos); | |
3183 __ push(dst); | |
3184 __ push(src_pos); | |
3185 __ push(src); | |
2446 | 3186 |
3187 if (copyfunc_addr == NULL) { // Use C version if stub was not generated | |
3188 __ call_VM_leaf(C_entry, 5); // removes pushed parameter from the stack | |
3189 } else { | |
3190 #ifndef PRODUCT | |
3191 if (PrintC1Statistics) { | |
3192 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); | |
3193 } | |
3194 #endif | |
3195 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack | |
3196 } | |
0 | 3197 |
304 | 3198 #endif // _LP64 |
3199 | |
0 | 3200 __ cmpl(rax, 0); |
3201 __ jcc(Assembler::equal, *stub->continuation()); | |
3202 | |
2446 | 3203 if (copyfunc_addr != NULL) { |
3204 __ mov(tmp, rax); | |
3205 __ xorl(tmp, -1); | |
3206 } | |
3207 | |
0 | 3208 // Reload values from the stack so they are where the stub |
3209 // expects them. | |
304 | 3210 __ movptr (dst, Address(rsp, 0*BytesPerWord)); |
3211 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); | |
3212 __ movptr (length, Address(rsp, 2*BytesPerWord)); | |
3213 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); | |
3214 __ movptr (src, Address(rsp, 4*BytesPerWord)); | |
2446 | 3215 |
3216 if (copyfunc_addr != NULL) { | |
3217 __ subl(length, tmp); | |
3218 __ addl(src_pos, tmp); | |
3219 __ addl(dst_pos, tmp); | |
3220 } | |
0 | 3221 __ jmp(*stub->entry()); |
3222 | |
3223 __ bind(*stub->continuation()); | |
3224 return; | |
3225 } | |
3226 | |
3227 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); | |
3228 | |
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diff
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3229 int elem_size = type2aelembytes(basic_type); |
0 | 3230 int shift_amount; |
3231 Address::ScaleFactor scale; | |
3232 | |
3233 switch (elem_size) { | |
3234 case 1 : | |
3235 shift_amount = 0; | |
3236 scale = Address::times_1; | |
3237 break; | |
3238 case 2 : | |
3239 shift_amount = 1; | |
3240 scale = Address::times_2; | |
3241 break; | |
3242 case 4 : | |
3243 shift_amount = 2; | |
3244 scale = Address::times_4; | |
3245 break; | |
3246 case 8 : | |
3247 shift_amount = 3; | |
3248 scale = Address::times_8; | |
3249 break; | |
3250 default: | |
3251 ShouldNotReachHere(); | |
3252 } | |
3253 | |
3254 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); | |
3255 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes()); | |
3256 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes()); | |
3257 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes()); | |
3258 | |
304 | 3259 // length and pos's are all sign extended at this point on 64bit |
3260 | |
0 | 3261 // test for NULL |
3262 if (flags & LIR_OpArrayCopy::src_null_check) { | |
304 | 3263 __ testptr(src, src); |
0 | 3264 __ jcc(Assembler::zero, *stub->entry()); |
3265 } | |
3266 if (flags & LIR_OpArrayCopy::dst_null_check) { | |
304 | 3267 __ testptr(dst, dst); |
0 | 3268 __ jcc(Assembler::zero, *stub->entry()); |
3269 } | |
3270 | |
3271 // check if negative | |
3272 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { | |
3273 __ testl(src_pos, src_pos); | |
3274 __ jcc(Assembler::less, *stub->entry()); | |
3275 } | |
3276 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { | |
3277 __ testl(dst_pos, dst_pos); | |
3278 __ jcc(Assembler::less, *stub->entry()); | |
3279 } | |
3280 | |
3281 if (flags & LIR_OpArrayCopy::src_range_check) { | |
304 | 3282 __ lea(tmp, Address(src_pos, length, Address::times_1, 0)); |
0 | 3283 __ cmpl(tmp, src_length_addr); |
3284 __ jcc(Assembler::above, *stub->entry()); | |
3285 } | |
3286 if (flags & LIR_OpArrayCopy::dst_range_check) { | |
304 | 3287 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0)); |
0 | 3288 __ cmpl(tmp, dst_length_addr); |
3289 __ jcc(Assembler::above, *stub->entry()); | |
3290 } | |
3291 | |
2446 | 3292 if (flags & LIR_OpArrayCopy::length_positive_check) { |
3293 __ testl(length, length); | |
3294 __ jcc(Assembler::less, *stub->entry()); | |
3295 __ jcc(Assembler::zero, *stub->continuation()); | |
3296 } | |
3297 | |
3298 #ifdef _LP64 | |
3299 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null | |
3300 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null | |
3301 #endif | |
3302 | |
0 | 3303 if (flags & LIR_OpArrayCopy::type_check) { |
2446 | 3304 // We don't know the array types are compatible |
3305 if (basic_type != T_OBJECT) { | |
3306 // Simple test for basic type arrays | |
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3307 if (UseCompressedClassPointers) { |
2446 | 3308 __ movl(tmp, src_klass_addr); |
3309 __ cmpl(tmp, dst_klass_addr); | |
3310 } else { | |
3311 __ movptr(tmp, src_klass_addr); | |
3312 __ cmpptr(tmp, dst_klass_addr); | |
3313 } | |
3314 __ jcc(Assembler::notEqual, *stub->entry()); | |
2002 | 3315 } else { |
2446 | 3316 // For object arrays, if src is a sub class of dst then we can |
3317 // safely do the copy. | |
3318 Label cont, slow; | |
3319 | |
3320 __ push(src); | |
3321 __ push(dst); | |
3322 | |
3323 __ load_klass(src, src); | |
3324 __ load_klass(dst, dst); | |
3325 | |
3326 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL); | |
3327 | |
3328 __ push(src); | |
3329 __ push(dst); | |
3330 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); | |
3331 __ pop(dst); | |
3332 __ pop(src); | |
3333 | |
3334 __ cmpl(src, 0); | |
3335 __ jcc(Assembler::notEqual, cont); | |
3336 | |
3337 __ bind(slow); | |
3338 __ pop(dst); | |
3339 __ pop(src); | |
3340 | |
3341 address copyfunc_addr = StubRoutines::checkcast_arraycopy(); | |
3342 if (copyfunc_addr != NULL) { // use stub if available | |
3343 // src is not a sub class of dst so we have to do a | |
3344 // per-element check. | |
3345 | |
3346 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray; | |
3347 if ((flags & mask) != mask) { | |
3348 // Check that at least both of them object arrays. | |
3349 assert(flags & mask, "one of the two should be known to be an object array"); | |
3350 | |
3351 if (!(flags & LIR_OpArrayCopy::src_objarray)) { | |
3352 __ load_klass(tmp, src); | |
3353 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) { | |
3354 __ load_klass(tmp, dst); | |
3355 } | |
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3356 int lh_offset = in_bytes(Klass::layout_helper_offset()); |
2446 | 3357 Address klass_lh_addr(tmp, lh_offset); |
3358 jint objArray_lh = Klass::array_layout_helper(T_OBJECT); | |
3359 __ cmpl(klass_lh_addr, objArray_lh); | |
3360 __ jcc(Assembler::notEqual, *stub->entry()); | |
3361 } | |
3362 | |
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3363 // Spill because stubs can use any register they like and it's |
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3364 // easier to restore just those that we care about. |
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3365 store_parameter(dst, 0); |
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3366 store_parameter(dst_pos, 1); |
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3367 store_parameter(length, 2); |
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3368 store_parameter(src_pos, 3); |
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3369 store_parameter(src, 4); |
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3370 |
2446 | 3371 #ifndef _LP64 |
3372 __ movptr(tmp, dst_klass_addr); | |
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3373 __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset())); |
2446 | 3374 __ push(tmp); |
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3375 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset())); |
2446 | 3376 __ push(tmp); |
3377 __ push(length); | |
3378 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); | |
3379 __ push(tmp); | |
3380 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); | |
3381 __ push(tmp); | |
3382 | |
3383 __ call_VM_leaf(copyfunc_addr, 5); | |
3384 #else | |
3385 __ movl2ptr(length, length); //higher 32bits must be null | |
3386 | |
3387 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); | |
3388 assert_different_registers(c_rarg0, dst, dst_pos, length); | |
3389 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); | |
3390 assert_different_registers(c_rarg1, dst, length); | |
3391 | |
3392 __ mov(c_rarg2, length); | |
3393 assert_different_registers(c_rarg2, dst); | |
3394 | |
3395 #ifdef _WIN64 | |
3396 // Allocate abi space for args but be sure to keep stack aligned | |
3397 __ subptr(rsp, 6*wordSize); | |
3398 __ load_klass(c_rarg3, dst); | |
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3399 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset())); |
2446 | 3400 store_parameter(c_rarg3, 4); |
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3401 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset())); |
2446 | 3402 __ call(RuntimeAddress(copyfunc_addr)); |
3403 __ addptr(rsp, 6*wordSize); | |
3404 #else | |
3405 __ load_klass(c_rarg4, dst); | |
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3406 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset())); |
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3407 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset())); |
2446 | 3408 __ call(RuntimeAddress(copyfunc_addr)); |
3409 #endif | |
3410 | |
3411 #endif | |
3412 | |
3413 #ifndef PRODUCT | |
3414 if (PrintC1Statistics) { | |
3415 Label failed; | |
3416 __ testl(rax, rax); | |
3417 __ jcc(Assembler::notZero, failed); | |
3418 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt)); | |
3419 __ bind(failed); | |
3420 } | |
3421 #endif | |
3422 | |
3423 __ testl(rax, rax); | |
3424 __ jcc(Assembler::zero, *stub->continuation()); | |
3425 | |
3426 #ifndef PRODUCT | |
3427 if (PrintC1Statistics) { | |
3428 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt)); | |
3429 } | |
3430 #endif | |
3431 | |
3432 __ mov(tmp, rax); | |
3433 | |
3434 __ xorl(tmp, -1); | |
3435 | |
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3436 // Restore previously spilled arguments |
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3437 __ movptr (dst, Address(rsp, 0*BytesPerWord)); |
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3438 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); |
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3439 __ movptr (length, Address(rsp, 2*BytesPerWord)); |
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3440 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); |
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3441 __ movptr (src, Address(rsp, 4*BytesPerWord)); |
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3401
diff
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|
3442 |
2446 | 3443 |
3444 __ subl(length, tmp); | |
3445 __ addl(src_pos, tmp); | |
3446 __ addl(dst_pos, tmp); | |
3447 } | |
3448 | |
3449 __ jmp(*stub->entry()); | |
3450 | |
3451 __ bind(cont); | |
3452 __ pop(dst); | |
3453 __ pop(src); | |
2002 | 3454 } |
0 | 3455 } |
3456 | |
3457 #ifdef ASSERT | |
3458 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { | |
3459 // Sanity check the known type with the incoming class. For the | |
3460 // primitive case the types must match exactly with src.klass and | |
3461 // dst.klass each exactly matching the default type. For the | |
3462 // object array case, if no type check is needed then either the | |
3463 // dst type is exactly the expected type and the src type is a | |
3464 // subtype which we can't check or src is the same array as dst | |
3465 // but not necessarily exactly of type default_type. | |
3466 Label known_ok, halt; | |
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da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
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|
3467 __ mov_metadata(tmp, default_type->constant_encoding()); |
2002 | 3468 #ifdef _LP64 |
12226
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8015107: NPG: Use consistent naming for metaspace concepts
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|
3469 if (UseCompressedClassPointers) { |
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6795
diff
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|
3470 __ encode_klass_not_null(tmp); |
2002 | 3471 } |
3472 #endif | |
3473 | |
0 | 3474 if (basic_type != T_OBJECT) { |
2002 | 3475 |
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8015107: NPG: Use consistent naming for metaspace concepts
ehelin
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12160
diff
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|
3476 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr); |
2002 | 3477 else __ cmpptr(tmp, dst_klass_addr); |
0 | 3478 __ jcc(Assembler::notEqual, halt); |
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diff
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|
3479 if (UseCompressedClassPointers) __ cmpl(tmp, src_klass_addr); |
2002 | 3480 else __ cmpptr(tmp, src_klass_addr); |
0 | 3481 __ jcc(Assembler::equal, known_ok); |
3482 } else { | |
12226
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diff
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|
3483 if (UseCompressedClassPointers) __ cmpl(tmp, dst_klass_addr); |
2002 | 3484 else __ cmpptr(tmp, dst_klass_addr); |
0 | 3485 __ jcc(Assembler::equal, known_ok); |
304 | 3486 __ cmpptr(src, dst); |
0 | 3487 __ jcc(Assembler::equal, known_ok); |
3488 } | |
3489 __ bind(halt); | |
3490 __ stop("incorrect type information in arraycopy"); | |
3491 __ bind(known_ok); | |
3492 } | |
3493 #endif | |
3494 | |
2446 | 3495 #ifndef PRODUCT |
3496 if (PrintC1Statistics) { | |
3497 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type))); | |
304 | 3498 } |
2446 | 3499 #endif |
304 | 3500 |
3501 #ifdef _LP64 | |
3502 assert_different_registers(c_rarg0, dst, dst_pos, length); | |
3503 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); | |
3504 assert_different_registers(c_rarg1, length); | |
3505 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); | |
3506 __ mov(c_rarg2, length); | |
3507 | |
3508 #else | |
3509 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); | |
0 | 3510 store_parameter(tmp, 0); |
304 | 3511 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); |
0 | 3512 store_parameter(tmp, 1); |
3513 store_parameter(length, 2); | |
304 | 3514 #endif // _LP64 |
2446 | 3515 |
3516 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0; | |
3517 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0; | |
3518 const char *name; | |
3519 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false); | |
3520 __ call_VM_leaf(entry, 0); | |
0 | 3521 |
3522 __ bind(*stub->continuation()); | |
3523 } | |
3524 | |
11080
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|
3525 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) { |
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7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
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diff
changeset
|
3526 assert(op->crc()->is_single_cpu(), "crc must be register"); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
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diff
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|
3527 assert(op->val()->is_single_cpu(), "byte value must be register"); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
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diff
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|
3528 assert(op->result_opr()->is_single_cpu(), "result must be register"); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
drchase
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diff
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|
3529 Register crc = op->crc()->as_register(); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
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diff
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|
3530 Register val = op->val()->as_register(); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
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diff
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|
3531 Register res = op->result_opr()->as_register(); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
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|
3532 |
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7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
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|
3533 assert_different_registers(val, crc, res); |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
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diff
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|
3534 |
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7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
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|
3535 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr())); |
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7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
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8860
diff
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|
3536 __ notl(crc); // ~crc |
b800986664f4
7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
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8860
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|
3537 __ update_byte_crc32(crc, val, res); |
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7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
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8860
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|
3538 __ notl(crc); // ~crc |
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7088419: Use x86 Hardware CRC32 Instruction with java.util.zip.CRC32
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8860
diff
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|
3539 __ mov(res, crc); |
b800986664f4
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8860
diff
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|
3540 } |
0 | 3541 |
3542 void LIR_Assembler::emit_lock(LIR_OpLock* op) { | |
3543 Register obj = op->obj_opr()->as_register(); // may not be an oop | |
3544 Register hdr = op->hdr_opr()->as_register(); | |
3545 Register lock = op->lock_opr()->as_register(); | |
3546 if (!UseFastLocking) { | |
3547 __ jmp(*op->stub()->entry()); | |
3548 } else if (op->code() == lir_lock) { | |
3549 Register scratch = noreg; | |
3550 if (UseBiasedLocking) { | |
3551 scratch = op->scratch_opr()->as_register(); | |
3552 } | |
3553 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); | |
3554 // add debug info for NullPointerException only if one is possible | |
3555 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry()); | |
3556 if (op->info() != NULL) { | |
3557 add_debug_info_for_null_check(null_check_offset, op->info()); | |
3558 } | |
3559 // done | |
3560 } else if (op->code() == lir_unlock) { | |
3561 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); | |
3562 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); | |
3563 } else { | |
3564 Unimplemented(); | |
3565 } | |
3566 __ bind(*op->stub()->continuation()); | |
3567 } | |
3568 | |
3569 | |
3570 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { | |
3571 ciMethod* method = op->profiled_method(); | |
3572 int bci = op->profiled_bci(); | |
6266
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
twisti
parents:
6145
diff
changeset
|
3573 ciMethod* callee = op->profiled_callee(); |
0 | 3574 |
3575 // Update counter for all call types | |
2007
5ddfcf4b079e
7003554: (tiered) assert(is_null_object() || handle() != NULL) failed: cannot embed null pointer
iveresov
parents:
2002
diff
changeset
|
3576 ciMethodData* md = method->method_data_or_null(); |
5ddfcf4b079e
7003554: (tiered) assert(is_null_object() || handle() != NULL) failed: cannot embed null pointer
iveresov
parents:
2002
diff
changeset
|
3577 assert(md != NULL, "Sanity"); |
0 | 3578 ciProfileData* data = md->bci_to_data(bci); |
3579 assert(data->is_CounterData(), "need CounterData for calls"); | |
3580 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); | |
3581 Register mdo = op->mdo()->as_register(); | |
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6266
diff
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|
3582 __ mov_metadata(mdo, md->constant_encoding()); |
0 | 3583 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); |
3584 Bytecodes::Code bc = method->java_code_at_bci(bci); | |
6266
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
twisti
parents:
6145
diff
changeset
|
3585 const bool callee_is_static = callee->is_loaded() && callee->is_static(); |
0 | 3586 // Perform additional virtual call profiling for invokevirtual and |
3587 // invokeinterface bytecodes | |
3588 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) && | |
6266
1d7922586cf6
7023639: JSR 292 method handle invocation needs a fast path for compiled code
twisti
parents:
6145
diff
changeset
|
3589 !callee_is_static && // required for optimized MH invokes |
1783 | 3590 C1ProfileVirtualCalls) { |
0 | 3591 assert(op->recv()->is_single_cpu(), "recv must be allocated"); |
3592 Register recv = op->recv()->as_register(); | |
3593 assert_different_registers(mdo, recv); | |
3594 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); | |
3595 ciKlass* known_klass = op->known_holder(); | |
1783 | 3596 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) { |
0 | 3597 // We know the type that will be seen at this call site; we can |
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da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6266
diff
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|
3598 // statically update the MethodData* rather than needing to do |
0 | 3599 // dynamic tests on the receiver type |
3600 | |
3601 // NOTE: we should probably put a lock around this search to | |
3602 // avoid collisions by concurrent compilations | |
3603 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; | |
3604 uint i; | |
3605 for (i = 0; i < VirtualCallData::row_limit(); i++) { | |
3606 ciKlass* receiver = vc_data->receiver(i); | |
3607 if (known_klass->equals(receiver)) { | |
3608 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); | |
1783 | 3609 __ addptr(data_addr, DataLayout::counter_increment); |
0 | 3610 return; |
3611 } | |
3612 } | |
3613 | |
3614 // Receiver type not found in profile data; select an empty slot | |
3615 | |
3616 // Note that this is less efficient than it should be because it | |
3617 // always does a write to the receiver part of the | |
3618 // VirtualCallData rather than just the first time | |
3619 for (i = 0; i < VirtualCallData::row_limit(); i++) { | |
3620 ciKlass* receiver = vc_data->receiver(i); | |
3621 if (receiver == NULL) { | |
3622 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); | |
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
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6266
diff
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|
3623 __ mov_metadata(recv_addr, known_klass->constant_encoding()); |
0 | 3624 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); |
1783 | 3625 __ addptr(data_addr, DataLayout::counter_increment); |
0 | 3626 return; |
3627 } | |
3628 } | |
3629 } else { | |
2002 | 3630 __ load_klass(recv, recv); |
0 | 3631 Label update_done; |
1783 | 3632 type_profile_helper(mdo, md, data, recv, &update_done); |
1206
87684f1a88b5
6614597: Performance variability in jvm2008 xml.validation
kvn
parents:
1204
diff
changeset
|
3633 // Receiver did not match any saved receiver and there is no empty row for it. |
1251
576e77447e3c
6923002: assert(false,"this call site should not be polymorphic")
kvn
parents:
1206
diff
changeset
|
3634 // Increment total counter to indicate polymorphic case. |
1783 | 3635 __ addptr(counter_addr, DataLayout::counter_increment); |
0 | 3636 |
3637 __ bind(update_done); | |
3638 } | |
1206
87684f1a88b5
6614597: Performance variability in jvm2008 xml.validation
kvn
parents:
1204
diff
changeset
|
3639 } else { |
87684f1a88b5
6614597: Performance variability in jvm2008 xml.validation
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parents:
1204
diff
changeset
|
3640 // Static call |
1783 | 3641 __ addptr(counter_addr, DataLayout::counter_increment); |
0 | 3642 } |
3643 } | |
3644 | |
12875
d13d7aba8c12
8023657: New type profiling points: arguments to call
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parents:
12269
diff
changeset
|
3645 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) { |
d13d7aba8c12
8023657: New type profiling points: arguments to call
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parents:
12269
diff
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|
3646 Register obj = op->obj()->as_register(); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
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parents:
12269
diff
changeset
|
3647 Register tmp = op->tmp()->as_pointer_register(); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
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parents:
12269
diff
changeset
|
3648 Address mdo_addr = as_Address(op->mdp()->as_address_ptr()); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
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parents:
12269
diff
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|
3649 ciKlass* exact_klass = op->exact_klass(); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
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parents:
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diff
changeset
|
3650 intptr_t current_klass = op->current_klass(); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
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parents:
12269
diff
changeset
|
3651 bool not_null = op->not_null(); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
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parents:
12269
diff
changeset
|
3652 bool no_conflict = op->no_conflict(); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
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parents:
12269
diff
changeset
|
3653 |
d13d7aba8c12
8023657: New type profiling points: arguments to call
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parents:
12269
diff
changeset
|
3654 Label update, next, none; |
d13d7aba8c12
8023657: New type profiling points: arguments to call
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parents:
12269
diff
changeset
|
3655 |
d13d7aba8c12
8023657: New type profiling points: arguments to call
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parents:
12269
diff
changeset
|
3656 bool do_null = !not_null; |
d13d7aba8c12
8023657: New type profiling points: arguments to call
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parents:
12269
diff
changeset
|
3657 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass; |
d13d7aba8c12
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parents:
12269
diff
changeset
|
3658 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set; |
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diff
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|
3659 |
d13d7aba8c12
8023657: New type profiling points: arguments to call
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diff
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|
3660 assert(do_null || do_update, "why are we here?"); |
d13d7aba8c12
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parents:
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diff
changeset
|
3661 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?"); |
d13d7aba8c12
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|
3662 |
d13d7aba8c12
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diff
changeset
|
3663 __ verify_oop(obj); |
d13d7aba8c12
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parents:
12269
diff
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|
3664 |
d13d7aba8c12
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|
3665 if (tmp != obj) { |
d13d7aba8c12
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parents:
12269
diff
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|
3666 __ mov(tmp, obj); |
d13d7aba8c12
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12269
diff
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|
3667 } |
d13d7aba8c12
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|
3668 if (do_null) { |
d13d7aba8c12
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diff
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|
3669 __ testptr(tmp, tmp); |
d13d7aba8c12
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diff
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|
3670 __ jccb(Assembler::notZero, update); |
d13d7aba8c12
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diff
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|
3671 if (!TypeEntries::was_null_seen(current_klass)) { |
d13d7aba8c12
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diff
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|
3672 __ orptr(mdo_addr, TypeEntries::null_seen); |
d13d7aba8c12
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12269
diff
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|
3673 } |
d13d7aba8c12
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|
3674 if (do_update) { |
d13d7aba8c12
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parents:
12269
diff
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|
3675 #ifndef ASSERT |
d13d7aba8c12
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parents:
12269
diff
changeset
|
3676 __ jmpb(next); |
d13d7aba8c12
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parents:
12269
diff
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|
3677 } |
d13d7aba8c12
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parents:
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diff
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|
3678 #else |
d13d7aba8c12
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12269
diff
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|
3679 __ jmp(next); |
d13d7aba8c12
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12269
diff
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|
3680 } |
d13d7aba8c12
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|
3681 } else { |
d13d7aba8c12
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diff
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|
3682 __ testptr(tmp, tmp); |
d13d7aba8c12
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12269
diff
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|
3683 __ jccb(Assembler::notZero, update); |
d13d7aba8c12
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|
3684 __ stop("unexpect null obj"); |
d13d7aba8c12
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12269
diff
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|
3685 #endif |
d13d7aba8c12
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diff
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|
3686 } |
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|
3687 |
d13d7aba8c12
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|
3688 __ bind(update); |
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|
3689 |
d13d7aba8c12
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|
3690 if (do_update) { |
d13d7aba8c12
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parents:
12269
diff
changeset
|
3691 #ifdef ASSERT |
d13d7aba8c12
8023657: New type profiling points: arguments to call
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parents:
12269
diff
changeset
|
3692 if (exact_klass != NULL) { |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3693 Label ok; |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3694 __ load_klass(tmp, tmp); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3695 __ push(tmp); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
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parents:
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diff
changeset
|
3696 __ mov_metadata(tmp, exact_klass->constant_encoding()); |
d13d7aba8c12
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parents:
12269
diff
changeset
|
3697 __ cmpptr(tmp, Address(rsp, 0)); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3698 __ jccb(Assembler::equal, ok); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3699 __ stop("exact klass and actual klass differ"); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3700 __ bind(ok); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3701 __ pop(tmp); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3702 } |
d13d7aba8c12
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parents:
12269
diff
changeset
|
3703 #endif |
d13d7aba8c12
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parents:
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diff
changeset
|
3704 if (!no_conflict) { |
d13d7aba8c12
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parents:
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diff
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|
3705 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) { |
d13d7aba8c12
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parents:
12269
diff
changeset
|
3706 if (exact_klass != NULL) { |
d13d7aba8c12
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roland
parents:
12269
diff
changeset
|
3707 __ mov_metadata(tmp, exact_klass->constant_encoding()); |
d13d7aba8c12
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parents:
12269
diff
changeset
|
3708 } else { |
d13d7aba8c12
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roland
parents:
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diff
changeset
|
3709 __ load_klass(tmp, tmp); |
d13d7aba8c12
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roland
parents:
12269
diff
changeset
|
3710 } |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3711 |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3712 __ xorptr(tmp, mdo_addr); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
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parents:
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diff
changeset
|
3713 __ testptr(tmp, TypeEntries::type_klass_mask); |
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parents:
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diff
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|
3714 // klass seen before, nothing to do. The unknown bit may have been |
d13d7aba8c12
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parents:
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diff
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|
3715 // set already but no need to check. |
d13d7aba8c12
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roland
parents:
12269
diff
changeset
|
3716 __ jccb(Assembler::zero, next); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3717 |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3718 __ testptr(tmp, TypeEntries::type_unknown); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
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parents:
12269
diff
changeset
|
3719 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. |
d13d7aba8c12
8023657: New type profiling points: arguments to call
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parents:
12269
diff
changeset
|
3720 |
d13d7aba8c12
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parents:
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diff
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|
3721 if (TypeEntries::is_type_none(current_klass)) { |
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parents:
12269
diff
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|
3722 __ cmpptr(mdo_addr, 0); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3723 __ jccb(Assembler::equal, none); |
d13d7aba8c12
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parents:
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diff
changeset
|
3724 __ cmpptr(mdo_addr, TypeEntries::null_seen); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
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parents:
12269
diff
changeset
|
3725 __ jccb(Assembler::equal, none); |
d13d7aba8c12
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parents:
12269
diff
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|
3726 // There is a chance that the checks above (re-reading profiling |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
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|
3727 // data from memory) fail if another thread has just set the |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3728 // profiling to this obj's klass |
d13d7aba8c12
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roland
parents:
12269
diff
changeset
|
3729 __ xorptr(tmp, mdo_addr); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
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parents:
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diff
changeset
|
3730 __ testptr(tmp, TypeEntries::type_klass_mask); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3731 __ jccb(Assembler::zero, next); |
d13d7aba8c12
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roland
parents:
12269
diff
changeset
|
3732 } |
d13d7aba8c12
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parents:
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diff
changeset
|
3733 } else { |
d13d7aba8c12
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parents:
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diff
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|
3734 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && |
d13d7aba8c12
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parents:
12269
diff
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|
3735 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only"); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
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parents:
12269
diff
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|
3736 |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3737 __ movptr(tmp, mdo_addr); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3738 __ testptr(tmp, TypeEntries::type_unknown); |
d13d7aba8c12
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parents:
12269
diff
changeset
|
3739 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. |
d13d7aba8c12
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parents:
12269
diff
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|
3740 } |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3741 |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3742 // different than before. Cannot keep accurate profile. |
d13d7aba8c12
8023657: New type profiling points: arguments to call
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parents:
12269
diff
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|
3743 __ orptr(mdo_addr, TypeEntries::type_unknown); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
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parents:
12269
diff
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|
3744 |
d13d7aba8c12
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parents:
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diff
changeset
|
3745 if (TypeEntries::is_type_none(current_klass)) { |
d13d7aba8c12
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roland
parents:
12269
diff
changeset
|
3746 __ jmpb(next); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3747 |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3748 __ bind(none); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3749 // first time here. Set profile type. |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3750 __ movptr(mdo_addr, tmp); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3751 } |
d13d7aba8c12
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roland
parents:
12269
diff
changeset
|
3752 } else { |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3753 // There's a single possible klass at this profile point |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3754 assert(exact_klass != NULL, "should be"); |
d13d7aba8c12
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parents:
12269
diff
changeset
|
3755 if (TypeEntries::is_type_none(current_klass)) { |
d13d7aba8c12
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parents:
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diff
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|
3756 __ mov_metadata(tmp, exact_klass->constant_encoding()); |
d13d7aba8c12
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parents:
12269
diff
changeset
|
3757 __ xorptr(tmp, mdo_addr); |
d13d7aba8c12
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roland
parents:
12269
diff
changeset
|
3758 __ testptr(tmp, TypeEntries::type_klass_mask); |
d13d7aba8c12
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parents:
12269
diff
changeset
|
3759 #ifdef ASSERT |
d13d7aba8c12
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parents:
12269
diff
changeset
|
3760 __ jcc(Assembler::zero, next); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3761 |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3762 { |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3763 Label ok; |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3764 __ push(tmp); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3765 __ cmpptr(mdo_addr, 0); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3766 __ jcc(Assembler::equal, ok); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3767 __ cmpptr(mdo_addr, TypeEntries::null_seen); |
d13d7aba8c12
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roland
parents:
12269
diff
changeset
|
3768 __ jcc(Assembler::equal, ok); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3769 // may have been set by another thread |
d13d7aba8c12
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roland
parents:
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diff
changeset
|
3770 __ mov_metadata(tmp, exact_klass->constant_encoding()); |
d13d7aba8c12
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roland
parents:
12269
diff
changeset
|
3771 __ xorptr(tmp, mdo_addr); |
d13d7aba8c12
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roland
parents:
12269
diff
changeset
|
3772 __ testptr(tmp, TypeEntries::type_mask); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3773 __ jcc(Assembler::zero, ok); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3774 |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3775 __ stop("unexpected profiling mismatch"); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3776 __ bind(ok); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3777 __ pop(tmp); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3778 } |
d13d7aba8c12
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roland
parents:
12269
diff
changeset
|
3779 #else |
d13d7aba8c12
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roland
parents:
12269
diff
changeset
|
3780 __ jccb(Assembler::zero, next); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3781 #endif |
d13d7aba8c12
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roland
parents:
12269
diff
changeset
|
3782 // first time here. Set profile type. |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3783 __ movptr(mdo_addr, tmp); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3784 } else { |
d13d7aba8c12
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roland
parents:
12269
diff
changeset
|
3785 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && |
d13d7aba8c12
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roland
parents:
12269
diff
changeset
|
3786 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent"); |
d13d7aba8c12
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roland
parents:
12269
diff
changeset
|
3787 |
d13d7aba8c12
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roland
parents:
12269
diff
changeset
|
3788 __ movptr(tmp, mdo_addr); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3789 __ testptr(tmp, TypeEntries::type_unknown); |
d13d7aba8c12
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roland
parents:
12269
diff
changeset
|
3790 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore. |
d13d7aba8c12
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roland
parents:
12269
diff
changeset
|
3791 |
d13d7aba8c12
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roland
parents:
12269
diff
changeset
|
3792 __ orptr(mdo_addr, TypeEntries::type_unknown); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3793 } |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3794 } |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3795 |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3796 __ bind(next); |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3797 } |
d13d7aba8c12
8023657: New type profiling points: arguments to call
roland
parents:
12269
diff
changeset
|
3798 } |
d13d7aba8c12
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|
3799 |
0 | 3800 void LIR_Assembler::emit_delay(LIR_OpDelay*) { |
3801 Unimplemented(); | |
3802 } | |
3803 | |
3804 | |
3805 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) { | |
304 | 3806 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no)); |
0 | 3807 } |
3808 | |
3809 | |
3810 void LIR_Assembler::align_backward_branch_target() { | |
3811 __ align(BytesPerWord); | |
3812 } | |
3813 | |
3814 | |
3815 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { | |
3816 if (left->is_single_cpu()) { | |
3817 __ negl(left->as_register()); | |
3818 move_regs(left->as_register(), dest->as_register()); | |
3819 | |
3820 } else if (left->is_double_cpu()) { | |
3821 Register lo = left->as_register_lo(); | |
304 | 3822 #ifdef _LP64 |
3823 Register dst = dest->as_register_lo(); | |
3824 __ movptr(dst, lo); | |
3825 __ negptr(dst); | |
3826 #else | |
0 | 3827 Register hi = left->as_register_hi(); |
3828 __ lneg(hi, lo); | |
3829 if (dest->as_register_lo() == hi) { | |
3830 assert(dest->as_register_hi() != lo, "destroying register"); | |
3831 move_regs(hi, dest->as_register_hi()); | |
3832 move_regs(lo, dest->as_register_lo()); | |
3833 } else { | |
3834 move_regs(lo, dest->as_register_lo()); | |
3835 move_regs(hi, dest->as_register_hi()); | |
3836 } | |
304 | 3837 #endif // _LP64 |
0 | 3838 |
3839 } else if (dest->is_single_xmm()) { | |
3840 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) { | |
3841 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg()); | |
3842 } | |
3843 __ xorps(dest->as_xmm_float_reg(), | |
3844 ExternalAddress((address)float_signflip_pool)); | |
3845 | |
3846 } else if (dest->is_double_xmm()) { | |
3847 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) { | |
3848 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg()); | |
3849 } | |
3850 __ xorpd(dest->as_xmm_double_reg(), | |
3851 ExternalAddress((address)double_signflip_pool)); | |
3852 | |
3853 } else if (left->is_single_fpu() || left->is_double_fpu()) { | |
3854 assert(left->fpu() == 0, "arg must be on TOS"); | |
3855 assert(dest->fpu() == 0, "dest must be TOS"); | |
3856 __ fchs(); | |
3857 | |
3858 } else { | |
3859 ShouldNotReachHere(); | |
3860 } | |
3861 } | |
3862 | |
3863 | |
3864 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) { | |
3865 assert(addr->is_address() && dest->is_register(), "check"); | |
304 | 3866 Register reg; |
3867 reg = dest->as_pointer_register(); | |
3868 __ lea(reg, as_Address(addr->as_address_ptr())); | |
0 | 3869 } |
3870 | |
3871 | |
3872 | |
3873 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { | |
3874 assert(!tmp->is_valid(), "don't need temporary"); | |
3875 __ call(RuntimeAddress(dest)); | |
3876 if (info != NULL) { | |
3877 add_call_info_here(info); | |
3878 } | |
3879 } | |
3880 | |
3881 | |
3882 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { | |
3883 assert(type == T_LONG, "only for volatile long fields"); | |
3884 | |
3885 if (info != NULL) { | |
3886 add_debug_info_for_null_check_here(info); | |
3887 } | |
3888 | |
3889 if (src->is_double_xmm()) { | |
3890 if (dest->is_double_cpu()) { | |
304 | 3891 #ifdef _LP64 |
3892 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg()); | |
3893 #else | |
3894 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg()); | |
0 | 3895 __ psrlq(src->as_xmm_double_reg(), 32); |
304 | 3896 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg()); |
3897 #endif // _LP64 | |
0 | 3898 } else if (dest->is_double_stack()) { |
3899 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg()); | |
3900 } else if (dest->is_address()) { | |
3901 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg()); | |
3902 } else { | |
3903 ShouldNotReachHere(); | |
3904 } | |
3905 | |
3906 } else if (dest->is_double_xmm()) { | |
3907 if (src->is_double_stack()) { | |
3908 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix())); | |
3909 } else if (src->is_address()) { | |
3910 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr())); | |
3911 } else { | |
3912 ShouldNotReachHere(); | |
3913 } | |
3914 | |
3915 } else if (src->is_double_fpu()) { | |
3916 assert(src->fpu_regnrLo() == 0, "must be TOS"); | |
3917 if (dest->is_double_stack()) { | |
3918 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix())); | |
3919 } else if (dest->is_address()) { | |
3920 __ fistp_d(as_Address(dest->as_address_ptr())); | |
3921 } else { | |
3922 ShouldNotReachHere(); | |
3923 } | |
3924 | |
3925 } else if (dest->is_double_fpu()) { | |
3926 assert(dest->fpu_regnrLo() == 0, "must be TOS"); | |
3927 if (src->is_double_stack()) { | |
3928 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix())); | |
3929 } else if (src->is_address()) { | |
3930 __ fild_d(as_Address(src->as_address_ptr())); | |
3931 } else { | |
3932 ShouldNotReachHere(); | |
3933 } | |
3934 } else { | |
3935 ShouldNotReachHere(); | |
3936 } | |
3937 } | |
3938 | |
8860 | 3939 #ifdef ASSERT |
3940 // emit run-time assertion | |
3941 void LIR_Assembler::emit_assert(LIR_OpAssert* op) { | |
3942 assert(op->code() == lir_assert, "must be"); | |
3943 | |
3944 if (op->in_opr1()->is_valid()) { | |
3945 assert(op->in_opr2()->is_valid(), "both operands must be valid"); | |
3946 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op); | |
3947 } else { | |
3948 assert(op->in_opr2()->is_illegal(), "both operands must be illegal"); | |
3949 assert(op->condition() == lir_cond_always, "no other conditions allowed"); | |
3950 } | |
3951 | |
3952 Label ok; | |
3953 if (op->condition() != lir_cond_always) { | |
3954 Assembler::Condition acond = Assembler::zero; | |
3955 switch (op->condition()) { | |
3956 case lir_cond_equal: acond = Assembler::equal; break; | |
3957 case lir_cond_notEqual: acond = Assembler::notEqual; break; | |
3958 case lir_cond_less: acond = Assembler::less; break; | |
3959 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; | |
3960 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; | |
3961 case lir_cond_greater: acond = Assembler::greater; break; | |
3962 case lir_cond_belowEqual: acond = Assembler::belowEqual; break; | |
3963 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; | |
3964 default: ShouldNotReachHere(); | |
3965 } | |
3966 __ jcc(acond, ok); | |
3967 } | |
3968 if (op->halt()) { | |
3969 const char* str = __ code_string(op->msg()); | |
3970 __ stop(str); | |
3971 } else { | |
3972 breakpoint(); | |
3973 } | |
3974 __ bind(ok); | |
3975 } | |
3976 #endif | |
0 | 3977 |
3978 void LIR_Assembler::membar() { | |
304 | 3979 // QQQ sparc TSO uses this, |
3980 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad)); | |
0 | 3981 } |
3982 | |
3983 void LIR_Assembler::membar_acquire() { | |
3984 // No x86 machines currently require load fences | |
3985 // __ load_fence(); | |
3986 } | |
3987 | |
3988 void LIR_Assembler::membar_release() { | |
3989 // No x86 machines currently require store fences | |
3990 // __ store_fence(); | |
3991 } | |
3992 | |
4966
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3993 void LIR_Assembler::membar_loadload() { |
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3994 // no-op |
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3995 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload)); |
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3996 } |
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|
3997 |
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3998 void LIR_Assembler::membar_storestore() { |
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3999 // no-op |
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4000 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore)); |
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|
4001 } |
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|
4002 |
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4003 void LIR_Assembler::membar_loadstore() { |
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4004 // no-op |
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4005 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore)); |
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|
4006 } |
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4007 |
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4008 void LIR_Assembler::membar_storeload() { |
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4009 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad)); |
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4010 } |
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|
4011 |
0 | 4012 void LIR_Assembler::get_thread(LIR_Opr result_reg) { |
4013 assert(result_reg->is_register(), "check"); | |
304 | 4014 #ifdef _LP64 |
4015 // __ get_thread(result_reg->as_register_lo()); | |
4016 __ mov(result_reg->as_register(), r15_thread); | |
4017 #else | |
0 | 4018 __ get_thread(result_reg->as_register()); |
304 | 4019 #endif // _LP64 |
0 | 4020 } |
4021 | |
4022 | |
4023 void LIR_Assembler::peephole(LIR_List*) { | |
4024 // do nothing for now | |
4025 } | |
4026 | |
6795
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4027 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) { |
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4028 assert(data == dest, "xchg/xadd uses only 2 operands"); |
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|
4029 |
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|
4030 if (data->type() == T_INT) { |
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4031 if (code == lir_xadd) { |
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4032 if (os::is_MP()) { |
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4033 __ lock(); |
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|
4034 } |
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4035 __ xaddl(as_Address(src->as_address_ptr()), data->as_register()); |
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4036 } else { |
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4037 __ xchgl(data->as_register(), as_Address(src->as_address_ptr())); |
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4038 } |
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|
4039 } else if (data->is_oop()) { |
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4040 assert (code == lir_xchg, "xadd for oops"); |
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4041 Register obj = data->as_register(); |
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|
4042 #ifdef _LP64 |
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4043 if (UseCompressedOops) { |
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|
4044 __ encode_heap_oop(obj); |
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4045 __ xchgl(obj, as_Address(src->as_address_ptr())); |
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4046 __ decode_heap_oop(obj); |
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|
4047 } else { |
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|
4048 __ xchgptr(obj, as_Address(src->as_address_ptr())); |
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4049 } |
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|
4050 #else |
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|
4051 __ xchgl(obj, as_Address(src->as_address_ptr())); |
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4052 #endif |
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|
4053 } else if (data->type() == T_LONG) { |
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diff
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|
4054 #ifdef _LP64 |
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|
4055 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register"); |
7eca5de9e0b6
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|
4056 if (code == lir_xadd) { |
7eca5de9e0b6
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diff
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|
4057 if (os::is_MP()) { |
7eca5de9e0b6
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diff
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|
4058 __ lock(); |
7eca5de9e0b6
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diff
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|
4059 } |
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diff
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|
4060 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo()); |
7eca5de9e0b6
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diff
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|
4061 } else { |
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diff
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|
4062 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr())); |
7eca5de9e0b6
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|
4063 } |
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diff
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|
4064 #else |
7eca5de9e0b6
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6739
diff
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|
4065 ShouldNotReachHere(); |
7eca5de9e0b6
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roland
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6739
diff
changeset
|
4066 #endif |
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diff
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|
4067 } else { |
7eca5de9e0b6
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6739
diff
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|
4068 ShouldNotReachHere(); |
7eca5de9e0b6
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roland
parents:
6739
diff
changeset
|
4069 } |
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|
4070 } |
0 | 4071 |
4072 #undef __ |