Mercurial > hg > graal-compiler
annotate src/cpu/x86/vm/c1_LIRAssembler_x86.cpp @ 2404:b40d4fa697bf
6964776: c2 should ensure the polling page is reachable on 64 bit
Summary: Materialize the pointer to the polling page in a register instead of using rip-relative addressing when the distance from the code cache is larger than disp32.
Reviewed-by: never, kvn
| author | iveresov |
|---|---|
| date | Sun, 27 Mar 2011 13:17:37 -0700 |
| parents | 1b4e6a5d98e0 |
| children | 09f96c3ff1ad |
| rev | line source |
|---|---|
| 0 | 1 /* |
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2 * Copyright (c) 2000, 2011, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
|
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20 * or visit www.oracle.com if you need additional information or have any |
|
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21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #include "precompiled.hpp" |
| 26 #include "c1/c1_Compilation.hpp" | |
| 27 #include "c1/c1_LIRAssembler.hpp" | |
| 28 #include "c1/c1_MacroAssembler.hpp" | |
| 29 #include "c1/c1_Runtime1.hpp" | |
| 30 #include "c1/c1_ValueStack.hpp" | |
| 31 #include "ci/ciArrayKlass.hpp" | |
| 32 #include "ci/ciInstance.hpp" | |
| 33 #include "gc_interface/collectedHeap.hpp" | |
| 34 #include "memory/barrierSet.hpp" | |
| 35 #include "memory/cardTableModRefBS.hpp" | |
| 36 #include "nativeInst_x86.hpp" | |
| 37 #include "oops/objArrayKlass.hpp" | |
| 38 #include "runtime/sharedRuntime.hpp" | |
| 0 | 39 |
| 40 | |
| 41 // These masks are used to provide 128-bit aligned bitmasks to the XMM | |
| 42 // instructions, to allow sign-masking or sign-bit flipping. They allow | |
| 43 // fast versions of NegF/NegD and AbsF/AbsD. | |
| 44 | |
| 45 // Note: 'double' and 'long long' have 32-bits alignment on x86. | |
| 46 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { | |
| 47 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address | |
| 48 // of 128-bits operands for SSE instructions. | |
| 49 jlong *operand = (jlong*)(((long)adr)&((long)(~0xF))); | |
| 50 // Store the value to a 128-bits operand. | |
| 51 operand[0] = lo; | |
| 52 operand[1] = hi; | |
| 53 return operand; | |
| 54 } | |
| 55 | |
| 56 // Buffer for 128-bits masks used by SSE instructions. | |
| 57 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) | |
| 58 | |
| 59 // Static initialization during VM startup. | |
| 60 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); | |
| 61 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); | |
| 62 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); | |
| 63 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); | |
| 64 | |
| 65 | |
| 66 | |
| 67 NEEDS_CLEANUP // remove this definitions ? | |
| 68 const Register IC_Klass = rax; // where the IC klass is cached | |
| 69 const Register SYNC_header = rax; // synchronization header | |
| 70 const Register SHIFT_count = rcx; // where count for shift operations must be | |
| 71 | |
| 72 #define __ _masm-> | |
| 73 | |
| 74 | |
| 75 static void select_different_registers(Register preserve, | |
| 76 Register extra, | |
| 77 Register &tmp1, | |
| 78 Register &tmp2) { | |
| 79 if (tmp1 == preserve) { | |
| 80 assert_different_registers(tmp1, tmp2, extra); | |
| 81 tmp1 = extra; | |
| 82 } else if (tmp2 == preserve) { | |
| 83 assert_different_registers(tmp1, tmp2, extra); | |
| 84 tmp2 = extra; | |
| 85 } | |
| 86 assert_different_registers(preserve, tmp1, tmp2); | |
| 87 } | |
| 88 | |
| 89 | |
| 90 | |
| 91 static void select_different_registers(Register preserve, | |
| 92 Register extra, | |
| 93 Register &tmp1, | |
| 94 Register &tmp2, | |
| 95 Register &tmp3) { | |
| 96 if (tmp1 == preserve) { | |
| 97 assert_different_registers(tmp1, tmp2, tmp3, extra); | |
| 98 tmp1 = extra; | |
| 99 } else if (tmp2 == preserve) { | |
| 100 assert_different_registers(tmp1, tmp2, tmp3, extra); | |
| 101 tmp2 = extra; | |
| 102 } else if (tmp3 == preserve) { | |
| 103 assert_different_registers(tmp1, tmp2, tmp3, extra); | |
| 104 tmp3 = extra; | |
| 105 } | |
| 106 assert_different_registers(preserve, tmp1, tmp2, tmp3); | |
| 107 } | |
| 108 | |
| 109 | |
| 110 | |
| 111 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { | |
| 112 if (opr->is_constant()) { | |
| 113 LIR_Const* constant = opr->as_constant_ptr(); | |
| 114 switch (constant->type()) { | |
| 115 case T_INT: { | |
| 116 return true; | |
| 117 } | |
| 118 | |
| 119 default: | |
| 120 return false; | |
| 121 } | |
| 122 } | |
| 123 return false; | |
| 124 } | |
| 125 | |
| 126 | |
| 127 LIR_Opr LIR_Assembler::receiverOpr() { | |
| 304 | 128 return FrameMap::receiver_opr; |
| 0 | 129 } |
| 130 | |
| 131 LIR_Opr LIR_Assembler::incomingReceiverOpr() { | |
| 132 return receiverOpr(); | |
| 133 } | |
| 134 | |
| 135 LIR_Opr LIR_Assembler::osrBufferPointer() { | |
| 304 | 136 return FrameMap::as_pointer_opr(receiverOpr()->as_register()); |
| 0 | 137 } |
| 138 | |
| 139 //--------------fpu register translations----------------------- | |
| 140 | |
| 141 | |
| 142 address LIR_Assembler::float_constant(float f) { | |
| 143 address const_addr = __ float_constant(f); | |
| 144 if (const_addr == NULL) { | |
| 145 bailout("const section overflow"); | |
| 146 return __ code()->consts()->start(); | |
| 147 } else { | |
| 148 return const_addr; | |
| 149 } | |
| 150 } | |
| 151 | |
| 152 | |
| 153 address LIR_Assembler::double_constant(double d) { | |
| 154 address const_addr = __ double_constant(d); | |
| 155 if (const_addr == NULL) { | |
| 156 bailout("const section overflow"); | |
| 157 return __ code()->consts()->start(); | |
| 158 } else { | |
| 159 return const_addr; | |
| 160 } | |
| 161 } | |
| 162 | |
| 163 | |
| 164 void LIR_Assembler::set_24bit_FPU() { | |
| 165 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 166 } | |
| 167 | |
| 168 void LIR_Assembler::reset_FPU() { | |
| 169 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 170 } | |
| 171 | |
| 172 void LIR_Assembler::fpop() { | |
| 173 __ fpop(); | |
| 174 } | |
| 175 | |
| 176 void LIR_Assembler::fxch(int i) { | |
| 177 __ fxch(i); | |
| 178 } | |
| 179 | |
| 180 void LIR_Assembler::fld(int i) { | |
| 181 __ fld_s(i); | |
| 182 } | |
| 183 | |
| 184 void LIR_Assembler::ffree(int i) { | |
| 185 __ ffree(i); | |
| 186 } | |
| 187 | |
| 188 void LIR_Assembler::breakpoint() { | |
| 189 __ int3(); | |
| 190 } | |
| 191 | |
| 192 void LIR_Assembler::push(LIR_Opr opr) { | |
| 193 if (opr->is_single_cpu()) { | |
| 194 __ push_reg(opr->as_register()); | |
| 195 } else if (opr->is_double_cpu()) { | |
| 304 | 196 NOT_LP64(__ push_reg(opr->as_register_hi())); |
| 0 | 197 __ push_reg(opr->as_register_lo()); |
| 198 } else if (opr->is_stack()) { | |
| 199 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix())); | |
| 200 } else if (opr->is_constant()) { | |
| 201 LIR_Const* const_opr = opr->as_constant_ptr(); | |
| 202 if (const_opr->type() == T_OBJECT) { | |
| 203 __ push_oop(const_opr->as_jobject()); | |
| 204 } else if (const_opr->type() == T_INT) { | |
| 205 __ push_jint(const_opr->as_jint()); | |
| 206 } else { | |
| 207 ShouldNotReachHere(); | |
| 208 } | |
| 209 | |
| 210 } else { | |
| 211 ShouldNotReachHere(); | |
| 212 } | |
| 213 } | |
| 214 | |
| 215 void LIR_Assembler::pop(LIR_Opr opr) { | |
| 216 if (opr->is_single_cpu()) { | |
| 304 | 217 __ pop_reg(opr->as_register()); |
| 0 | 218 } else { |
| 219 ShouldNotReachHere(); | |
| 220 } | |
| 221 } | |
| 222 | |
| 304 | 223 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { |
| 224 return addr->base()->is_illegal() && addr->index()->is_illegal(); | |
| 225 } | |
| 226 | |
| 0 | 227 //------------------------------------------- |
| 304 | 228 |
| 0 | 229 Address LIR_Assembler::as_Address(LIR_Address* addr) { |
| 304 | 230 return as_Address(addr, rscratch1); |
| 231 } | |
| 232 | |
| 233 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) { | |
| 0 | 234 if (addr->base()->is_illegal()) { |
| 235 assert(addr->index()->is_illegal(), "must be illegal too"); | |
| 304 | 236 AddressLiteral laddr((address)addr->disp(), relocInfo::none); |
| 237 if (! __ reachable(laddr)) { | |
| 238 __ movptr(tmp, laddr.addr()); | |
| 239 Address res(tmp, 0); | |
| 240 return res; | |
| 241 } else { | |
| 242 return __ as_Address(laddr); | |
| 243 } | |
| 0 | 244 } |
| 245 | |
| 304 | 246 Register base = addr->base()->as_pointer_register(); |
| 0 | 247 |
| 248 if (addr->index()->is_illegal()) { | |
| 249 return Address( base, addr->disp()); | |
| 304 | 250 } else if (addr->index()->is_cpu_register()) { |
| 251 Register index = addr->index()->as_pointer_register(); | |
| 0 | 252 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp()); |
| 253 } else if (addr->index()->is_constant()) { | |
| 304 | 254 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp(); |
| 255 assert(Assembler::is_simm32(addr_offset), "must be"); | |
| 0 | 256 |
| 257 return Address(base, addr_offset); | |
| 258 } else { | |
| 259 Unimplemented(); | |
| 260 return Address(); | |
| 261 } | |
| 262 } | |
| 263 | |
| 264 | |
| 265 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { | |
| 266 Address base = as_Address(addr); | |
| 267 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord); | |
| 268 } | |
| 269 | |
| 270 | |
| 271 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { | |
| 272 return as_Address(addr); | |
| 273 } | |
| 274 | |
| 275 | |
| 276 void LIR_Assembler::osr_entry() { | |
| 277 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); | |
| 278 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); | |
| 279 ValueStack* entry_state = osr_entry->state(); | |
| 280 int number_of_locks = entry_state->locks_size(); | |
| 281 | |
| 282 // we jump here if osr happens with the interpreter | |
| 283 // state set up to continue at the beginning of the | |
| 284 // loop that triggered osr - in particular, we have | |
| 285 // the following registers setup: | |
| 286 // | |
| 287 // rcx: osr buffer | |
| 288 // | |
| 289 | |
| 290 // build frame | |
| 291 ciMethod* m = compilation()->method(); | |
| 292 __ build_frame(initial_frame_size_in_bytes()); | |
| 293 | |
| 294 // OSR buffer is | |
| 295 // | |
| 296 // locals[nlocals-1..0] | |
| 297 // monitors[0..number_of_locks] | |
| 298 // | |
| 299 // locals is a direct copy of the interpreter frame so in the osr buffer | |
| 300 // so first slot in the local array is the last local from the interpreter | |
| 301 // and last slot is local[0] (receiver) from the interpreter | |
| 302 // | |
| 303 // Similarly with locks. The first lock slot in the osr buffer is the nth lock | |
| 304 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock | |
| 305 // in the interpreter frame (the method lock if a sync method) | |
| 306 | |
| 307 // Initialize monitors in the compiled activation. | |
| 308 // rcx: pointer to osr buffer | |
| 309 // | |
| 310 // All other registers are dead at this point and the locals will be | |
| 311 // copied into place by code emitted in the IR. | |
| 312 | |
| 304 | 313 Register OSR_buf = osrBufferPointer()->as_pointer_register(); |
| 0 | 314 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); |
| 315 int monitor_offset = BytesPerWord * method()->max_locals() + | |
| 1060 | 316 (2 * BytesPerWord) * (number_of_locks - 1); |
| 317 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in | |
| 318 // the OSR buffer using 2 word entries: first the lock and then | |
| 319 // the oop. | |
| 0 | 320 for (int i = 0; i < number_of_locks; i++) { |
| 1060 | 321 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); |
| 0 | 322 #ifdef ASSERT |
| 323 // verify the interpreter's monitor has a non-null object | |
| 324 { | |
| 325 Label L; | |
| 1060 | 326 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD); |
| 0 | 327 __ jcc(Assembler::notZero, L); |
| 328 __ stop("locked object is NULL"); | |
| 329 __ bind(L); | |
| 330 } | |
| 331 #endif | |
| 1060 | 332 __ movptr(rbx, Address(OSR_buf, slot_offset + 0)); |
| 304 | 333 __ movptr(frame_map()->address_for_monitor_lock(i), rbx); |
| 1060 | 334 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord)); |
| 304 | 335 __ movptr(frame_map()->address_for_monitor_object(i), rbx); |
| 0 | 336 } |
| 337 } | |
| 338 } | |
| 339 | |
| 340 | |
| 341 // inline cache check; done before the frame is built. | |
| 342 int LIR_Assembler::check_icache() { | |
| 343 Register receiver = FrameMap::receiver_opr->as_register(); | |
| 344 Register ic_klass = IC_Klass; | |
| 304 | 345 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9); |
| 2002 | 346 const bool do_post_padding = VerifyOops || UseCompressedOops; |
| 347 if (!do_post_padding) { | |
| 0 | 348 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment |
| 304 | 349 while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) { |
| 0 | 350 __ nop(); |
| 351 } | |
| 352 } | |
| 353 int offset = __ offset(); | |
| 354 __ inline_cache_check(receiver, IC_Klass); | |
| 2002 | 355 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct"); |
| 356 if (do_post_padding) { | |
| 0 | 357 // force alignment after the cache check. |
| 358 // It's been verified to be aligned if !VerifyOops | |
| 359 __ align(CodeEntryAlignment); | |
| 360 } | |
| 361 return offset; | |
| 362 } | |
| 363 | |
| 364 | |
| 365 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) { | |
| 366 jobject o = NULL; | |
| 367 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id); | |
| 368 __ movoop(reg, o); | |
| 369 patching_epilog(patch, lir_patch_normal, reg, info); | |
| 370 } | |
| 371 | |
| 372 | |
| 373 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register new_hdr, int monitor_no, Register exception) { | |
| 374 if (exception->is_valid()) { | |
| 375 // preserve exception | |
| 376 // note: the monitor_exit runtime call is a leaf routine | |
| 377 // and cannot block => no GC can happen | |
| 378 // The slow case (MonitorAccessStub) uses the first two stack slots | |
| 379 // ([esp+0] and [esp+4]), therefore we store the exception at [esp+8] | |
| 304 | 380 __ movptr (Address(rsp, 2*wordSize), exception); |
| 0 | 381 } |
| 382 | |
| 383 Register obj_reg = obj_opr->as_register(); | |
| 384 Register lock_reg = lock_opr->as_register(); | |
| 385 | |
| 386 // setup registers (lock_reg must be rax, for lock_object) | |
| 387 assert(obj_reg != SYNC_header && lock_reg != SYNC_header, "rax, must be available here"); | |
| 388 Register hdr = lock_reg; | |
| 389 assert(new_hdr == SYNC_header, "wrong register"); | |
| 390 lock_reg = new_hdr; | |
| 391 // compute pointer to BasicLock | |
| 392 Address lock_addr = frame_map()->address_for_monitor_lock(monitor_no); | |
| 304 | 393 __ lea(lock_reg, lock_addr); |
| 0 | 394 // unlock object |
| 395 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, true, monitor_no); | |
| 396 // _slow_case_stubs->append(slow_case); | |
| 397 // temporary fix: must be created after exceptionhandler, therefore as call stub | |
| 398 _slow_case_stubs->append(slow_case); | |
| 399 if (UseFastLocking) { | |
| 400 // try inlined fast unlocking first, revert to slow locking if it fails | |
| 401 // note: lock_reg points to the displaced header since the displaced header offset is 0! | |
| 402 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); | |
| 403 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry()); | |
| 404 } else { | |
| 405 // always do slow unlocking | |
| 406 // note: the slow unlocking code could be inlined here, however if we use | |
| 407 // slow unlocking, speed doesn't matter anyway and this solution is | |
| 408 // simpler and requires less duplicated code - additionally, the | |
| 409 // slow unlocking code is the same in either case which simplifies | |
| 410 // debugging | |
| 411 __ jmp(*slow_case->entry()); | |
| 412 } | |
| 413 // done | |
| 414 __ bind(*slow_case->continuation()); | |
| 415 | |
| 416 if (exception->is_valid()) { | |
| 417 // restore exception | |
| 304 | 418 __ movptr (exception, Address(rsp, 2 * wordSize)); |
| 0 | 419 } |
| 420 } | |
| 421 | |
| 422 // This specifies the rsp decrement needed to build the frame | |
| 423 int LIR_Assembler::initial_frame_size_in_bytes() { | |
| 424 // if rounding, must let FrameMap know! | |
| 304 | 425 |
| 426 // The frame_map records size in slots (32bit word) | |
| 427 | |
| 428 // subtract two words to account for return address and link | |
| 429 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size; | |
| 0 | 430 } |
| 431 | |
| 432 | |
| 1204 | 433 int LIR_Assembler::emit_exception_handler() { |
| 0 | 434 // if the last instruction is a call (typically to do a throw which |
| 435 // is coming at the end after block reordering) the return address | |
| 436 // must still point into the code area in order to avoid assertion | |
| 437 // failures when searching for the corresponding bci => add a nop | |
| 438 // (was bug 5/14/1999 - gri) | |
| 439 __ nop(); | |
| 440 | |
| 441 // generate code for exception handler | |
| 442 address handler_base = __ start_a_stub(exception_handler_size); | |
| 443 if (handler_base == NULL) { | |
| 444 // not enough space left for the handler | |
| 445 bailout("exception handler overflow"); | |
| 1204 | 446 return -1; |
| 0 | 447 } |
| 1204 | 448 |
| 0 | 449 int offset = code_offset(); |
| 450 | |
| 1295 | 451 // the exception oop and pc are in rax, and rdx |
| 0 | 452 // no other registers need to be preserved, so invalidate them |
| 1295 | 453 __ invalidate_registers(false, true, true, false, true, true); |
| 0 | 454 |
| 455 // check that there is really an exception | |
| 456 __ verify_not_null_oop(rax); | |
| 457 | |
| 1295 | 458 // search an exception handler (rax: exception oop, rdx: throwing pc) |
|
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459 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id))); |
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460 __ should_not_reach_here(); |
| 0 | 461 assert(code_offset() - offset <= exception_handler_size, "overflow"); |
| 462 __ end_a_stub(); | |
| 1204 | 463 |
| 464 return offset; | |
| 0 | 465 } |
| 466 | |
| 1204 | 467 |
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468 // Emit the code to remove the frame from the stack in the exception |
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469 // unwind path. |
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470 int LIR_Assembler::emit_unwind_handler() { |
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471 #ifndef PRODUCT |
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472 if (CommentedAssembly) { |
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473 _masm->block_comment("Unwind handler"); |
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474 } |
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475 #endif |
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476 |
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477 int offset = code_offset(); |
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478 |
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479 // Fetch the exception from TLS and clear out exception related thread state |
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480 __ get_thread(rsi); |
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481 __ movptr(rax, Address(rsi, JavaThread::exception_oop_offset())); |
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482 __ movptr(Address(rsi, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD); |
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483 __ movptr(Address(rsi, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD); |
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484 |
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485 __ bind(_unwind_handler_entry); |
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486 __ verify_not_null_oop(rax); |
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487 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { |
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488 __ mov(rsi, rax); // Preserve the exception |
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489 } |
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490 |
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491 // Preform needed unlocking |
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492 MonitorExitStub* stub = NULL; |
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493 if (method()->is_synchronized()) { |
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494 monitor_address(0, FrameMap::rax_opr); |
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495 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0); |
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496 __ unlock_object(rdi, rbx, rax, *stub->entry()); |
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497 __ bind(*stub->continuation()); |
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498 } |
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499 |
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500 if (compilation()->env()->dtrace_method_probes()) { |
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501 __ get_thread(rax); |
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502 __ movptr(Address(rsp, 0), rax); |
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503 __ movoop(Address(rsp, sizeof(void*)), method()->constant_encoding()); |
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504 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit))); |
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505 } |
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506 |
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507 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { |
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508 __ mov(rax, rsi); // Restore the exception |
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509 } |
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510 |
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511 // remove the activation and dispatch to the unwind handler |
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512 __ remove_frame(initial_frame_size_in_bytes()); |
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513 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id))); |
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514 |
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515 // Emit the slow path assembly |
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516 if (stub != NULL) { |
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517 stub->emit_code(this); |
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518 } |
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519 |
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520 return offset; |
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521 } |
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522 |
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523 |
| 1204 | 524 int LIR_Assembler::emit_deopt_handler() { |
| 0 | 525 // if the last instruction is a call (typically to do a throw which |
| 526 // is coming at the end after block reordering) the return address | |
| 527 // must still point into the code area in order to avoid assertion | |
| 528 // failures when searching for the corresponding bci => add a nop | |
| 529 // (was bug 5/14/1999 - gri) | |
| 530 __ nop(); | |
| 531 | |
| 532 // generate code for exception handler | |
| 533 address handler_base = __ start_a_stub(deopt_handler_size); | |
| 534 if (handler_base == NULL) { | |
| 535 // not enough space left for the handler | |
| 536 bailout("deopt handler overflow"); | |
| 1204 | 537 return -1; |
| 0 | 538 } |
| 1204 | 539 |
| 0 | 540 int offset = code_offset(); |
| 541 InternalAddress here(__ pc()); | |
| 1295 | 542 |
| 0 | 543 __ pushptr(here.addr()); |
| 544 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); | |
| 1295 | 545 |
| 0 | 546 assert(code_offset() - offset <= deopt_handler_size, "overflow"); |
| 547 __ end_a_stub(); | |
| 548 | |
| 1204 | 549 return offset; |
| 0 | 550 } |
| 551 | |
| 552 | |
| 553 // This is the fast version of java.lang.String.compare; it has not | |
| 554 // OSR-entry and therefore, we generate a slow version for OSR's | |
| 555 void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) { | |
| 304 | 556 __ movptr (rbx, rcx); // receiver is in rcx |
| 557 __ movptr (rax, arg1->as_register()); | |
| 0 | 558 |
| 559 // Get addresses of first characters from both Strings | |
| 2002 | 560 __ load_heap_oop(rsi, Address(rax, java_lang_String::value_offset_in_bytes())); |
| 561 __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes())); | |
| 562 __ lea (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); | |
| 0 | 563 |
| 564 | |
| 565 // rbx, may be NULL | |
| 566 add_debug_info_for_null_check_here(info); | |
| 2002 | 567 __ load_heap_oop(rdi, Address(rbx, java_lang_String::value_offset_in_bytes())); |
| 568 __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes())); | |
| 569 __ lea (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); | |
| 0 | 570 |
| 571 // compute minimum length (in rax) and difference of lengths (on top of stack) | |
| 572 if (VM_Version::supports_cmov()) { | |
| 304 | 573 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes())); |
| 574 __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes())); | |
| 575 __ mov (rcx, rbx); | |
| 576 __ subptr (rbx, rax); // subtract lengths | |
| 577 __ push (rbx); // result | |
| 578 __ cmov (Assembler::lessEqual, rax, rcx); | |
| 0 | 579 } else { |
| 580 Label L; | |
| 304 | 581 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes())); |
| 582 __ movl (rcx, Address(rax, java_lang_String::count_offset_in_bytes())); | |
| 583 __ mov (rax, rbx); | |
| 584 __ subptr (rbx, rcx); | |
| 585 __ push (rbx); | |
| 586 __ jcc (Assembler::lessEqual, L); | |
| 587 __ mov (rax, rcx); | |
| 0 | 588 __ bind (L); |
| 589 } | |
| 590 // is minimum length 0? | |
| 591 Label noLoop, haveResult; | |
| 304 | 592 __ testptr (rax, rax); |
| 0 | 593 __ jcc (Assembler::zero, noLoop); |
| 594 | |
| 595 // compare first characters | |
|
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596 __ load_unsigned_short(rcx, Address(rdi, 0)); |
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597 __ load_unsigned_short(rbx, Address(rsi, 0)); |
| 0 | 598 __ subl(rcx, rbx); |
| 599 __ jcc(Assembler::notZero, haveResult); | |
| 600 // starting loop | |
| 601 __ decrement(rax); // we already tested index: skip one | |
| 602 __ jcc(Assembler::zero, noLoop); | |
| 603 | |
| 604 // set rsi.edi to the end of the arrays (arrays have same length) | |
| 605 // negate the index | |
| 606 | |
| 304 | 607 __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR))); |
| 608 __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR))); | |
| 609 __ negptr(rax); | |
| 0 | 610 |
| 611 // compare the strings in a loop | |
| 612 | |
| 613 Label loop; | |
| 614 __ align(wordSize); | |
| 615 __ bind(loop); | |
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616 __ load_unsigned_short(rcx, Address(rdi, rax, Address::times_2, 0)); |
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617 __ load_unsigned_short(rbx, Address(rsi, rax, Address::times_2, 0)); |
| 0 | 618 __ subl(rcx, rbx); |
| 619 __ jcc(Assembler::notZero, haveResult); | |
| 620 __ increment(rax); | |
| 621 __ jcc(Assembler::notZero, loop); | |
| 622 | |
| 623 // strings are equal up to min length | |
| 624 | |
| 625 __ bind(noLoop); | |
| 304 | 626 __ pop(rax); |
| 0 | 627 return_op(LIR_OprFact::illegalOpr); |
| 628 | |
| 629 __ bind(haveResult); | |
| 630 // leave instruction is going to discard the TOS value | |
| 304 | 631 __ mov (rax, rcx); // result of call is in rax, |
| 0 | 632 } |
| 633 | |
| 634 | |
| 635 void LIR_Assembler::return_op(LIR_Opr result) { | |
| 636 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,"); | |
| 637 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) { | |
| 638 assert(result->fpu() == 0, "result must already be on TOS"); | |
| 639 } | |
| 640 | |
| 641 // Pop the stack before the safepoint code | |
| 1295 | 642 __ remove_frame(initial_frame_size_in_bytes()); |
| 0 | 643 |
| 644 bool result_is_oop = result->is_valid() ? result->is_oop() : false; | |
| 645 | |
| 646 // Note: we do not need to round double result; float result has the right precision | |
| 647 // the poll sets the condition code, but no data registers | |
| 648 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), | |
| 649 relocInfo::poll_return_type); | |
| 304 | 650 |
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651 if (Assembler::is_polling_page_far()) { |
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652 __ lea(rscratch1, polling_page); |
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653 __ relocate(relocInfo::poll_return_type); |
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654 __ testl(rax, Address(rscratch1, 0)); |
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655 } else { |
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656 __ testl(rax, polling_page); |
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657 } |
| 0 | 658 __ ret(0); |
| 659 } | |
| 660 | |
| 661 | |
| 662 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { | |
| 663 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), | |
| 664 relocInfo::poll_type); | |
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665 guarantee(info != NULL, "Shouldn't be NULL"); |
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666 int offset = __ offset(); |
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667 if (Assembler::is_polling_page_far()) { |
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668 __ lea(rscratch1, polling_page); |
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669 offset = __ offset(); |
| 0 | 670 add_debug_info_for_branch(info); |
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671 __ testl(rax, Address(rscratch1, 0)); |
| 0 | 672 } else { |
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673 add_debug_info_for_branch(info); |
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674 __ testl(rax, polling_page); |
| 0 | 675 } |
| 676 return offset; | |
| 677 } | |
| 678 | |
| 679 | |
| 680 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) { | |
| 304 | 681 if (from_reg != to_reg) __ mov(to_reg, from_reg); |
| 0 | 682 } |
| 683 | |
| 684 void LIR_Assembler::swap_reg(Register a, Register b) { | |
| 304 | 685 __ xchgptr(a, b); |
| 0 | 686 } |
| 687 | |
| 688 | |
| 689 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { | |
| 690 assert(src->is_constant(), "should not call otherwise"); | |
| 691 assert(dest->is_register(), "should not call otherwise"); | |
| 692 LIR_Const* c = src->as_constant_ptr(); | |
| 693 | |
| 694 switch (c->type()) { | |
| 2002 | 695 case T_INT: { |
| 696 assert(patch_code == lir_patch_none, "no patching handled here"); | |
| 697 __ movl(dest->as_register(), c->as_jint()); | |
| 698 break; | |
| 699 } | |
| 700 | |
|
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701 case T_ADDRESS: { |
| 0 | 702 assert(patch_code == lir_patch_none, "no patching handled here"); |
| 2002 | 703 __ movptr(dest->as_register(), c->as_jint()); |
| 0 | 704 break; |
| 705 } | |
| 706 | |
| 707 case T_LONG: { | |
| 708 assert(patch_code == lir_patch_none, "no patching handled here"); | |
| 304 | 709 #ifdef _LP64 |
| 710 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong()); | |
| 711 #else | |
| 712 __ movptr(dest->as_register_lo(), c->as_jint_lo()); | |
| 713 __ movptr(dest->as_register_hi(), c->as_jint_hi()); | |
| 714 #endif // _LP64 | |
| 0 | 715 break; |
| 716 } | |
| 717 | |
| 718 case T_OBJECT: { | |
| 719 if (patch_code != lir_patch_none) { | |
| 720 jobject2reg_with_patching(dest->as_register(), info); | |
| 721 } else { | |
| 722 __ movoop(dest->as_register(), c->as_jobject()); | |
| 723 } | |
| 724 break; | |
| 725 } | |
| 726 | |
| 727 case T_FLOAT: { | |
| 728 if (dest->is_single_xmm()) { | |
| 729 if (c->is_zero_float()) { | |
| 730 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg()); | |
| 731 } else { | |
| 732 __ movflt(dest->as_xmm_float_reg(), | |
| 733 InternalAddress(float_constant(c->as_jfloat()))); | |
| 734 } | |
| 735 } else { | |
| 736 assert(dest->is_single_fpu(), "must be"); | |
| 737 assert(dest->fpu_regnr() == 0, "dest must be TOS"); | |
| 738 if (c->is_zero_float()) { | |
| 739 __ fldz(); | |
| 740 } else if (c->is_one_float()) { | |
| 741 __ fld1(); | |
| 742 } else { | |
| 743 __ fld_s (InternalAddress(float_constant(c->as_jfloat()))); | |
| 744 } | |
| 745 } | |
| 746 break; | |
| 747 } | |
| 748 | |
| 749 case T_DOUBLE: { | |
| 750 if (dest->is_double_xmm()) { | |
| 751 if (c->is_zero_double()) { | |
| 752 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg()); | |
| 753 } else { | |
| 754 __ movdbl(dest->as_xmm_double_reg(), | |
| 755 InternalAddress(double_constant(c->as_jdouble()))); | |
| 756 } | |
| 757 } else { | |
| 758 assert(dest->is_double_fpu(), "must be"); | |
| 759 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); | |
| 760 if (c->is_zero_double()) { | |
| 761 __ fldz(); | |
| 762 } else if (c->is_one_double()) { | |
| 763 __ fld1(); | |
| 764 } else { | |
| 765 __ fld_d (InternalAddress(double_constant(c->as_jdouble()))); | |
| 766 } | |
| 767 } | |
| 768 break; | |
| 769 } | |
| 770 | |
| 771 default: | |
| 772 ShouldNotReachHere(); | |
| 773 } | |
| 774 } | |
| 775 | |
| 776 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { | |
| 777 assert(src->is_constant(), "should not call otherwise"); | |
| 778 assert(dest->is_stack(), "should not call otherwise"); | |
| 779 LIR_Const* c = src->as_constant_ptr(); | |
| 780 | |
| 781 switch (c->type()) { | |
| 782 case T_INT: // fall through | |
| 783 case T_FLOAT: | |
| 2002 | 784 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); |
| 785 break; | |
| 786 | |
|
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787 case T_ADDRESS: |
| 2002 | 788 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); |
| 0 | 789 break; |
| 790 | |
| 791 case T_OBJECT: | |
| 792 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject()); | |
| 793 break; | |
| 794 | |
| 795 case T_LONG: // fall through | |
| 796 case T_DOUBLE: | |
| 304 | 797 #ifdef _LP64 |
| 798 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), | |
| 799 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits()); | |
| 800 #else | |
| 801 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), | |
| 802 lo_word_offset_in_bytes), c->as_jint_lo_bits()); | |
| 803 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), | |
| 804 hi_word_offset_in_bytes), c->as_jint_hi_bits()); | |
| 805 #endif // _LP64 | |
| 0 | 806 break; |
| 807 | |
| 808 default: | |
| 809 ShouldNotReachHere(); | |
| 810 } | |
| 811 } | |
| 812 | |
| 2002 | 813 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) { |
| 0 | 814 assert(src->is_constant(), "should not call otherwise"); |
| 815 assert(dest->is_address(), "should not call otherwise"); | |
| 816 LIR_Const* c = src->as_constant_ptr(); | |
| 817 LIR_Address* addr = dest->as_address_ptr(); | |
| 818 | |
| 304 | 819 int null_check_here = code_offset(); |
| 0 | 820 switch (type) { |
| 821 case T_INT: // fall through | |
| 822 case T_FLOAT: | |
| 2002 | 823 __ movl(as_Address(addr), c->as_jint_bits()); |
| 824 break; | |
| 825 | |
|
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826 case T_ADDRESS: |
| 2002 | 827 __ movptr(as_Address(addr), c->as_jint_bits()); |
| 0 | 828 break; |
| 829 | |
| 830 case T_OBJECT: // fall through | |
| 831 case T_ARRAY: | |
| 832 if (c->as_jobject() == NULL) { | |
| 2002 | 833 if (UseCompressedOops && !wide) { |
| 834 __ movl(as_Address(addr), (int32_t)NULL_WORD); | |
| 835 } else { | |
| 836 __ movptr(as_Address(addr), NULL_WORD); | |
| 837 } | |
| 0 | 838 } else { |
| 304 | 839 if (is_literal_address(addr)) { |
| 840 ShouldNotReachHere(); | |
| 841 __ movoop(as_Address(addr, noreg), c->as_jobject()); | |
| 842 } else { | |
| 1060 | 843 #ifdef _LP64 |
| 844 __ movoop(rscratch1, c->as_jobject()); | |
| 2002 | 845 if (UseCompressedOops && !wide) { |
| 846 __ encode_heap_oop(rscratch1); | |
| 847 null_check_here = code_offset(); | |
| 848 __ movl(as_Address_lo(addr), rscratch1); | |
| 849 } else { | |
| 850 null_check_here = code_offset(); | |
| 851 __ movptr(as_Address_lo(addr), rscratch1); | |
| 852 } | |
| 1060 | 853 #else |
| 304 | 854 __ movoop(as_Address(addr), c->as_jobject()); |
| 1060 | 855 #endif |
| 304 | 856 } |
| 0 | 857 } |
| 858 break; | |
| 859 | |
| 860 case T_LONG: // fall through | |
| 861 case T_DOUBLE: | |
| 304 | 862 #ifdef _LP64 |
| 863 if (is_literal_address(addr)) { | |
| 864 ShouldNotReachHere(); | |
| 865 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits()); | |
| 866 } else { | |
| 867 __ movptr(r10, (intptr_t)c->as_jlong_bits()); | |
| 868 null_check_here = code_offset(); | |
| 869 __ movptr(as_Address_lo(addr), r10); | |
| 870 } | |
| 871 #else | |
| 872 // Always reachable in 32bit so this doesn't produce useless move literal | |
| 873 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits()); | |
| 874 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits()); | |
| 875 #endif // _LP64 | |
| 0 | 876 break; |
| 877 | |
| 878 case T_BOOLEAN: // fall through | |
| 879 case T_BYTE: | |
| 880 __ movb(as_Address(addr), c->as_jint() & 0xFF); | |
| 881 break; | |
| 882 | |
| 883 case T_CHAR: // fall through | |
| 884 case T_SHORT: | |
| 885 __ movw(as_Address(addr), c->as_jint() & 0xFFFF); | |
| 886 break; | |
| 887 | |
| 888 default: | |
| 889 ShouldNotReachHere(); | |
| 890 }; | |
| 304 | 891 |
| 892 if (info != NULL) { | |
| 893 add_debug_info_for_null_check(null_check_here, info); | |
| 894 } | |
| 0 | 895 } |
| 896 | |
| 897 | |
| 898 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { | |
| 899 assert(src->is_register(), "should not call otherwise"); | |
| 900 assert(dest->is_register(), "should not call otherwise"); | |
| 901 | |
| 902 // move between cpu-registers | |
| 903 if (dest->is_single_cpu()) { | |
| 304 | 904 #ifdef _LP64 |
| 905 if (src->type() == T_LONG) { | |
| 906 // Can do LONG -> OBJECT | |
| 907 move_regs(src->as_register_lo(), dest->as_register()); | |
| 908 return; | |
| 909 } | |
| 910 #endif | |
| 0 | 911 assert(src->is_single_cpu(), "must match"); |
| 912 if (src->type() == T_OBJECT) { | |
| 913 __ verify_oop(src->as_register()); | |
| 914 } | |
| 915 move_regs(src->as_register(), dest->as_register()); | |
| 916 | |
| 917 } else if (dest->is_double_cpu()) { | |
| 304 | 918 #ifdef _LP64 |
| 919 if (src->type() == T_OBJECT || src->type() == T_ARRAY) { | |
| 920 // Surprising to me but we can see move of a long to t_object | |
| 921 __ verify_oop(src->as_register()); | |
| 922 move_regs(src->as_register(), dest->as_register_lo()); | |
| 923 return; | |
| 924 } | |
| 925 #endif | |
| 0 | 926 assert(src->is_double_cpu(), "must match"); |
| 927 Register f_lo = src->as_register_lo(); | |
| 928 Register f_hi = src->as_register_hi(); | |
| 929 Register t_lo = dest->as_register_lo(); | |
| 930 Register t_hi = dest->as_register_hi(); | |
| 304 | 931 #ifdef _LP64 |
| 932 assert(f_hi == f_lo, "must be same"); | |
| 933 assert(t_hi == t_lo, "must be same"); | |
| 934 move_regs(f_lo, t_lo); | |
| 935 #else | |
| 0 | 936 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation"); |
| 937 | |
| 304 | 938 |
| 0 | 939 if (f_lo == t_hi && f_hi == t_lo) { |
| 940 swap_reg(f_lo, f_hi); | |
| 941 } else if (f_hi == t_lo) { | |
| 942 assert(f_lo != t_hi, "overwriting register"); | |
| 943 move_regs(f_hi, t_hi); | |
| 944 move_regs(f_lo, t_lo); | |
| 945 } else { | |
| 946 assert(f_hi != t_lo, "overwriting register"); | |
| 947 move_regs(f_lo, t_lo); | |
| 948 move_regs(f_hi, t_hi); | |
| 949 } | |
| 304 | 950 #endif // LP64 |
| 0 | 951 |
| 952 // special moves from fpu-register to xmm-register | |
| 953 // necessary for method results | |
| 954 } else if (src->is_single_xmm() && !dest->is_single_xmm()) { | |
| 955 __ movflt(Address(rsp, 0), src->as_xmm_float_reg()); | |
| 956 __ fld_s(Address(rsp, 0)); | |
| 957 } else if (src->is_double_xmm() && !dest->is_double_xmm()) { | |
| 958 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg()); | |
| 959 __ fld_d(Address(rsp, 0)); | |
| 960 } else if (dest->is_single_xmm() && !src->is_single_xmm()) { | |
| 961 __ fstp_s(Address(rsp, 0)); | |
| 962 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0)); | |
| 963 } else if (dest->is_double_xmm() && !src->is_double_xmm()) { | |
| 964 __ fstp_d(Address(rsp, 0)); | |
| 965 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0)); | |
| 966 | |
| 967 // move between xmm-registers | |
| 968 } else if (dest->is_single_xmm()) { | |
| 969 assert(src->is_single_xmm(), "must match"); | |
| 970 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg()); | |
| 971 } else if (dest->is_double_xmm()) { | |
| 972 assert(src->is_double_xmm(), "must match"); | |
| 973 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg()); | |
| 974 | |
| 975 // move between fpu-registers (no instruction necessary because of fpu-stack) | |
| 976 } else if (dest->is_single_fpu() || dest->is_double_fpu()) { | |
| 977 assert(src->is_single_fpu() || src->is_double_fpu(), "must match"); | |
| 978 assert(src->fpu() == dest->fpu(), "currently should be nothing to do"); | |
| 979 } else { | |
| 980 ShouldNotReachHere(); | |
| 981 } | |
| 982 } | |
| 983 | |
| 984 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { | |
| 985 assert(src->is_register(), "should not call otherwise"); | |
| 986 assert(dest->is_stack(), "should not call otherwise"); | |
| 987 | |
| 988 if (src->is_single_cpu()) { | |
| 989 Address dst = frame_map()->address_for_slot(dest->single_stack_ix()); | |
| 990 if (type == T_OBJECT || type == T_ARRAY) { | |
| 991 __ verify_oop(src->as_register()); | |
| 304 | 992 __ movptr (dst, src->as_register()); |
| 993 } else { | |
| 994 __ movl (dst, src->as_register()); | |
| 0 | 995 } |
| 996 | |
| 997 } else if (src->is_double_cpu()) { | |
| 998 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes); | |
| 999 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes); | |
| 304 | 1000 __ movptr (dstLO, src->as_register_lo()); |
| 1001 NOT_LP64(__ movptr (dstHI, src->as_register_hi())); | |
| 0 | 1002 |
| 1003 } else if (src->is_single_xmm()) { | |
| 1004 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); | |
| 1005 __ movflt(dst_addr, src->as_xmm_float_reg()); | |
| 1006 | |
| 1007 } else if (src->is_double_xmm()) { | |
| 1008 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); | |
| 1009 __ movdbl(dst_addr, src->as_xmm_double_reg()); | |
| 1010 | |
| 1011 } else if (src->is_single_fpu()) { | |
| 1012 assert(src->fpu_regnr() == 0, "argument must be on TOS"); | |
| 1013 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); | |
| 1014 if (pop_fpu_stack) __ fstp_s (dst_addr); | |
| 1015 else __ fst_s (dst_addr); | |
| 1016 | |
| 1017 } else if (src->is_double_fpu()) { | |
| 1018 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); | |
| 1019 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); | |
| 1020 if (pop_fpu_stack) __ fstp_d (dst_addr); | |
| 1021 else __ fst_d (dst_addr); | |
| 1022 | |
| 1023 } else { | |
| 1024 ShouldNotReachHere(); | |
| 1025 } | |
| 1026 } | |
| 1027 | |
| 1028 | |
| 2002 | 1029 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) { |
| 0 | 1030 LIR_Address* to_addr = dest->as_address_ptr(); |
| 1031 PatchingStub* patch = NULL; | |
| 2002 | 1032 Register compressed_src = rscratch1; |
| 0 | 1033 |
| 1034 if (type == T_ARRAY || type == T_OBJECT) { | |
| 1035 __ verify_oop(src->as_register()); | |
| 2002 | 1036 #ifdef _LP64 |
| 1037 if (UseCompressedOops && !wide) { | |
| 1038 __ movptr(compressed_src, src->as_register()); | |
| 1039 __ encode_heap_oop(compressed_src); | |
| 1040 } | |
| 1041 #endif | |
| 0 | 1042 } |
| 2002 | 1043 |
| 0 | 1044 if (patch_code != lir_patch_none) { |
| 1045 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
| 304 | 1046 Address toa = as_Address(to_addr); |
| 1047 assert(toa.disp() != 0, "must have"); | |
| 0 | 1048 } |
| 2002 | 1049 |
| 1050 int null_check_here = code_offset(); | |
| 0 | 1051 switch (type) { |
| 1052 case T_FLOAT: { | |
| 1053 if (src->is_single_xmm()) { | |
| 1054 __ movflt(as_Address(to_addr), src->as_xmm_float_reg()); | |
| 1055 } else { | |
| 1056 assert(src->is_single_fpu(), "must be"); | |
| 1057 assert(src->fpu_regnr() == 0, "argument must be on TOS"); | |
| 1058 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr)); | |
| 1059 else __ fst_s (as_Address(to_addr)); | |
| 1060 } | |
| 1061 break; | |
| 1062 } | |
| 1063 | |
| 1064 case T_DOUBLE: { | |
| 1065 if (src->is_double_xmm()) { | |
| 1066 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg()); | |
| 1067 } else { | |
| 1068 assert(src->is_double_fpu(), "must be"); | |
| 1069 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); | |
| 1070 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr)); | |
| 1071 else __ fst_d (as_Address(to_addr)); | |
| 1072 } | |
| 1073 break; | |
| 1074 } | |
| 1075 | |
| 1076 case T_ARRAY: // fall through | |
| 1077 case T_OBJECT: // fall through | |
| 2002 | 1078 if (UseCompressedOops && !wide) { |
| 1079 __ movl(as_Address(to_addr), compressed_src); | |
| 1080 } else { | |
| 1081 __ movptr(as_Address(to_addr), src->as_register()); | |
| 1082 } | |
| 1083 break; | |
| 1084 case T_ADDRESS: | |
| 304 | 1085 __ movptr(as_Address(to_addr), src->as_register()); |
| 1086 break; | |
| 0 | 1087 case T_INT: |
| 1088 __ movl(as_Address(to_addr), src->as_register()); | |
| 1089 break; | |
| 1090 | |
| 1091 case T_LONG: { | |
| 1092 Register from_lo = src->as_register_lo(); | |
| 1093 Register from_hi = src->as_register_hi(); | |
| 304 | 1094 #ifdef _LP64 |
| 1095 __ movptr(as_Address_lo(to_addr), from_lo); | |
| 1096 #else | |
| 0 | 1097 Register base = to_addr->base()->as_register(); |
| 1098 Register index = noreg; | |
| 1099 if (to_addr->index()->is_register()) { | |
| 1100 index = to_addr->index()->as_register(); | |
| 1101 } | |
| 1102 if (base == from_lo || index == from_lo) { | |
| 1103 assert(base != from_hi, "can't be"); | |
| 1104 assert(index == noreg || (index != base && index != from_hi), "can't handle this"); | |
| 1105 __ movl(as_Address_hi(to_addr), from_hi); | |
| 1106 if (patch != NULL) { | |
| 1107 patching_epilog(patch, lir_patch_high, base, info); | |
| 1108 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
| 1109 patch_code = lir_patch_low; | |
| 1110 } | |
| 1111 __ movl(as_Address_lo(to_addr), from_lo); | |
| 1112 } else { | |
| 1113 assert(index == noreg || (index != base && index != from_lo), "can't handle this"); | |
| 1114 __ movl(as_Address_lo(to_addr), from_lo); | |
| 1115 if (patch != NULL) { | |
| 1116 patching_epilog(patch, lir_patch_low, base, info); | |
| 1117 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
| 1118 patch_code = lir_patch_high; | |
| 1119 } | |
| 1120 __ movl(as_Address_hi(to_addr), from_hi); | |
| 1121 } | |
| 304 | 1122 #endif // _LP64 |
| 0 | 1123 break; |
| 1124 } | |
| 1125 | |
| 1126 case T_BYTE: // fall through | |
| 1127 case T_BOOLEAN: { | |
| 1128 Register src_reg = src->as_register(); | |
| 1129 Address dst_addr = as_Address(to_addr); | |
| 1130 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6"); | |
| 1131 __ movb(dst_addr, src_reg); | |
| 1132 break; | |
| 1133 } | |
| 1134 | |
| 1135 case T_CHAR: // fall through | |
| 1136 case T_SHORT: | |
| 1137 __ movw(as_Address(to_addr), src->as_register()); | |
| 1138 break; | |
| 1139 | |
| 1140 default: | |
| 1141 ShouldNotReachHere(); | |
| 1142 } | |
| 2002 | 1143 if (info != NULL) { |
| 1144 add_debug_info_for_null_check(null_check_here, info); | |
| 1145 } | |
| 0 | 1146 |
| 1147 if (patch_code != lir_patch_none) { | |
| 1148 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info); | |
| 1149 } | |
| 1150 } | |
| 1151 | |
| 1152 | |
| 1153 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { | |
| 1154 assert(src->is_stack(), "should not call otherwise"); | |
| 1155 assert(dest->is_register(), "should not call otherwise"); | |
| 1156 | |
| 1157 if (dest->is_single_cpu()) { | |
| 1158 if (type == T_ARRAY || type == T_OBJECT) { | |
| 304 | 1159 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); |
| 0 | 1160 __ verify_oop(dest->as_register()); |
| 304 | 1161 } else { |
| 1162 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); | |
| 0 | 1163 } |
| 1164 | |
| 1165 } else if (dest->is_double_cpu()) { | |
| 1166 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes); | |
| 1167 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes); | |
| 304 | 1168 __ movptr(dest->as_register_lo(), src_addr_LO); |
| 1169 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI)); | |
| 0 | 1170 |
| 1171 } else if (dest->is_single_xmm()) { | |
| 1172 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); | |
| 1173 __ movflt(dest->as_xmm_float_reg(), src_addr); | |
| 1174 | |
| 1175 } else if (dest->is_double_xmm()) { | |
| 1176 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); | |
| 1177 __ movdbl(dest->as_xmm_double_reg(), src_addr); | |
| 1178 | |
| 1179 } else if (dest->is_single_fpu()) { | |
| 1180 assert(dest->fpu_regnr() == 0, "dest must be TOS"); | |
| 1181 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); | |
| 1182 __ fld_s(src_addr); | |
| 1183 | |
| 1184 } else if (dest->is_double_fpu()) { | |
| 1185 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); | |
| 1186 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); | |
| 1187 __ fld_d(src_addr); | |
| 1188 | |
| 1189 } else { | |
| 1190 ShouldNotReachHere(); | |
| 1191 } | |
| 1192 } | |
| 1193 | |
| 1194 | |
| 1195 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { | |
| 1196 if (src->is_single_stack()) { | |
| 304 | 1197 if (type == T_OBJECT || type == T_ARRAY) { |
| 1198 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix())); | |
| 1199 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix())); | |
| 1200 } else { | |
| 1060 | 1201 #ifndef _LP64 |
| 304 | 1202 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix())); |
| 1203 __ popl (frame_map()->address_for_slot(dest->single_stack_ix())); | |
| 1060 | 1204 #else |
| 1205 //no pushl on 64bits | |
| 1206 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix())); | |
| 1207 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1); | |
| 1208 #endif | |
| 304 | 1209 } |
| 0 | 1210 |
| 1211 } else if (src->is_double_stack()) { | |
| 304 | 1212 #ifdef _LP64 |
| 1213 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix())); | |
| 1214 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix())); | |
| 1215 #else | |
| 0 | 1216 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0)); |
| 304 | 1217 // push and pop the part at src + wordSize, adding wordSize for the previous push |
|
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1218 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize)); |
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1219 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize)); |
| 0 | 1220 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0)); |
| 304 | 1221 #endif // _LP64 |
| 0 | 1222 |
| 1223 } else { | |
| 1224 ShouldNotReachHere(); | |
| 1225 } | |
| 1226 } | |
| 1227 | |
| 1228 | |
| 2002 | 1229 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) { |
| 0 | 1230 assert(src->is_address(), "should not call otherwise"); |
| 1231 assert(dest->is_register(), "should not call otherwise"); | |
| 1232 | |
| 1233 LIR_Address* addr = src->as_address_ptr(); | |
| 1234 Address from_addr = as_Address(addr); | |
| 1235 | |
| 1236 switch (type) { | |
| 1237 case T_BOOLEAN: // fall through | |
| 1238 case T_BYTE: // fall through | |
| 1239 case T_CHAR: // fall through | |
| 1240 case T_SHORT: | |
| 1241 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) { | |
| 1242 // on pre P6 processors we may get partial register stalls | |
| 1243 // so blow away the value of to_rinfo before loading a | |
| 1244 // partial word into it. Do it here so that it precedes | |
| 1245 // the potential patch point below. | |
| 304 | 1246 __ xorptr(dest->as_register(), dest->as_register()); |
| 0 | 1247 } |
| 1248 break; | |
| 1249 } | |
| 1250 | |
| 1251 PatchingStub* patch = NULL; | |
| 1252 if (patch_code != lir_patch_none) { | |
| 1253 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
| 304 | 1254 assert(from_addr.disp() != 0, "must have"); |
| 0 | 1255 } |
| 1256 if (info != NULL) { | |
| 1257 add_debug_info_for_null_check_here(info); | |
| 1258 } | |
| 1259 | |
| 1260 switch (type) { | |
| 1261 case T_FLOAT: { | |
| 1262 if (dest->is_single_xmm()) { | |
| 1263 __ movflt(dest->as_xmm_float_reg(), from_addr); | |
| 1264 } else { | |
| 1265 assert(dest->is_single_fpu(), "must be"); | |
| 1266 assert(dest->fpu_regnr() == 0, "dest must be TOS"); | |
| 1267 __ fld_s(from_addr); | |
| 1268 } | |
| 1269 break; | |
| 1270 } | |
| 1271 | |
| 1272 case T_DOUBLE: { | |
| 1273 if (dest->is_double_xmm()) { | |
| 1274 __ movdbl(dest->as_xmm_double_reg(), from_addr); | |
| 1275 } else { | |
| 1276 assert(dest->is_double_fpu(), "must be"); | |
| 1277 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); | |
| 1278 __ fld_d(from_addr); | |
| 1279 } | |
| 1280 break; | |
| 1281 } | |
| 1282 | |
| 1283 case T_OBJECT: // fall through | |
| 1284 case T_ARRAY: // fall through | |
| 2002 | 1285 if (UseCompressedOops && !wide) { |
| 1286 __ movl(dest->as_register(), from_addr); | |
| 1287 } else { | |
| 1288 __ movptr(dest->as_register(), from_addr); | |
| 1289 } | |
| 1290 break; | |
| 1291 | |
| 1292 case T_ADDRESS: | |
| 304 | 1293 __ movptr(dest->as_register(), from_addr); |
| 1294 break; | |
| 0 | 1295 case T_INT: |
|
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1296 __ movl(dest->as_register(), from_addr); |
| 0 | 1297 break; |
| 1298 | |
| 1299 case T_LONG: { | |
| 1300 Register to_lo = dest->as_register_lo(); | |
| 1301 Register to_hi = dest->as_register_hi(); | |
| 304 | 1302 #ifdef _LP64 |
| 1303 __ movptr(to_lo, as_Address_lo(addr)); | |
| 1304 #else | |
| 0 | 1305 Register base = addr->base()->as_register(); |
| 1306 Register index = noreg; | |
| 1307 if (addr->index()->is_register()) { | |
| 1308 index = addr->index()->as_register(); | |
| 1309 } | |
| 1310 if ((base == to_lo && index == to_hi) || | |
| 1311 (base == to_hi && index == to_lo)) { | |
| 1312 // addresses with 2 registers are only formed as a result of | |
| 1313 // array access so this code will never have to deal with | |
| 1314 // patches or null checks. | |
| 1315 assert(info == NULL && patch == NULL, "must be"); | |
| 304 | 1316 __ lea(to_hi, as_Address(addr)); |
| 0 | 1317 __ movl(to_lo, Address(to_hi, 0)); |
| 1318 __ movl(to_hi, Address(to_hi, BytesPerWord)); | |
| 1319 } else if (base == to_lo || index == to_lo) { | |
| 1320 assert(base != to_hi, "can't be"); | |
| 1321 assert(index == noreg || (index != base && index != to_hi), "can't handle this"); | |
| 1322 __ movl(to_hi, as_Address_hi(addr)); | |
| 1323 if (patch != NULL) { | |
| 1324 patching_epilog(patch, lir_patch_high, base, info); | |
| 1325 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
| 1326 patch_code = lir_patch_low; | |
| 1327 } | |
| 1328 __ movl(to_lo, as_Address_lo(addr)); | |
| 1329 } else { | |
| 1330 assert(index == noreg || (index != base && index != to_lo), "can't handle this"); | |
| 1331 __ movl(to_lo, as_Address_lo(addr)); | |
| 1332 if (patch != NULL) { | |
| 1333 patching_epilog(patch, lir_patch_low, base, info); | |
| 1334 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
| 1335 patch_code = lir_patch_high; | |
| 1336 } | |
| 1337 __ movl(to_hi, as_Address_hi(addr)); | |
| 1338 } | |
| 304 | 1339 #endif // _LP64 |
| 0 | 1340 break; |
| 1341 } | |
| 1342 | |
| 1343 case T_BOOLEAN: // fall through | |
| 1344 case T_BYTE: { | |
| 1345 Register dest_reg = dest->as_register(); | |
| 1346 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); | |
| 1347 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { | |
| 304 | 1348 __ movsbl(dest_reg, from_addr); |
| 0 | 1349 } else { |
| 1350 __ movb(dest_reg, from_addr); | |
| 1351 __ shll(dest_reg, 24); | |
| 1352 __ sarl(dest_reg, 24); | |
| 1353 } | |
| 1354 break; | |
| 1355 } | |
| 1356 | |
| 1357 case T_CHAR: { | |
| 1358 Register dest_reg = dest->as_register(); | |
| 1359 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); | |
| 1360 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { | |
| 304 | 1361 __ movzwl(dest_reg, from_addr); |
| 0 | 1362 } else { |
| 1363 __ movw(dest_reg, from_addr); | |
| 1364 } | |
| 1365 break; | |
| 1366 } | |
| 1367 | |
| 1368 case T_SHORT: { | |
| 1369 Register dest_reg = dest->as_register(); | |
| 1370 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { | |
| 304 | 1371 __ movswl(dest_reg, from_addr); |
| 0 | 1372 } else { |
| 1373 __ movw(dest_reg, from_addr); | |
| 1374 __ shll(dest_reg, 16); | |
| 1375 __ sarl(dest_reg, 16); | |
| 1376 } | |
| 1377 break; | |
| 1378 } | |
| 1379 | |
| 1380 default: | |
| 1381 ShouldNotReachHere(); | |
| 1382 } | |
| 1383 | |
| 1384 if (patch != NULL) { | |
| 1385 patching_epilog(patch, patch_code, addr->base()->as_register(), info); | |
| 1386 } | |
| 1387 | |
| 1388 if (type == T_ARRAY || type == T_OBJECT) { | |
| 2002 | 1389 #ifdef _LP64 |
| 1390 if (UseCompressedOops && !wide) { | |
| 1391 __ decode_heap_oop(dest->as_register()); | |
| 1392 } | |
| 1393 #endif | |
| 0 | 1394 __ verify_oop(dest->as_register()); |
| 1395 } | |
| 1396 } | |
| 1397 | |
| 1398 | |
| 1399 void LIR_Assembler::prefetchr(LIR_Opr src) { | |
| 1400 LIR_Address* addr = src->as_address_ptr(); | |
| 1401 Address from_addr = as_Address(addr); | |
| 1402 | |
| 1403 if (VM_Version::supports_sse()) { | |
| 1404 switch (ReadPrefetchInstr) { | |
| 1405 case 0: | |
| 1406 __ prefetchnta(from_addr); break; | |
| 1407 case 1: | |
| 1408 __ prefetcht0(from_addr); break; | |
| 1409 case 2: | |
| 1410 __ prefetcht2(from_addr); break; | |
| 1411 default: | |
| 1412 ShouldNotReachHere(); break; | |
| 1413 } | |
| 1414 } else if (VM_Version::supports_3dnow()) { | |
| 1415 __ prefetchr(from_addr); | |
| 1416 } | |
| 1417 } | |
| 1418 | |
| 1419 | |
| 1420 void LIR_Assembler::prefetchw(LIR_Opr src) { | |
| 1421 LIR_Address* addr = src->as_address_ptr(); | |
| 1422 Address from_addr = as_Address(addr); | |
| 1423 | |
| 1424 if (VM_Version::supports_sse()) { | |
| 1425 switch (AllocatePrefetchInstr) { | |
| 1426 case 0: | |
| 1427 __ prefetchnta(from_addr); break; | |
| 1428 case 1: | |
| 1429 __ prefetcht0(from_addr); break; | |
| 1430 case 2: | |
| 1431 __ prefetcht2(from_addr); break; | |
| 1432 case 3: | |
| 1433 __ prefetchw(from_addr); break; | |
| 1434 default: | |
| 1435 ShouldNotReachHere(); break; | |
| 1436 } | |
| 1437 } else if (VM_Version::supports_3dnow()) { | |
| 1438 __ prefetchw(from_addr); | |
| 1439 } | |
| 1440 } | |
| 1441 | |
| 1442 | |
| 1443 NEEDS_CLEANUP; // This could be static? | |
| 1444 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const { | |
|
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1445 int elem_size = type2aelembytes(type); |
| 0 | 1446 switch (elem_size) { |
| 1447 case 1: return Address::times_1; | |
| 1448 case 2: return Address::times_2; | |
| 1449 case 4: return Address::times_4; | |
| 1450 case 8: return Address::times_8; | |
| 1451 } | |
| 1452 ShouldNotReachHere(); | |
| 1453 return Address::no_scale; | |
| 1454 } | |
| 1455 | |
| 1456 | |
| 1457 void LIR_Assembler::emit_op3(LIR_Op3* op) { | |
| 1458 switch (op->code()) { | |
| 1459 case lir_idiv: | |
| 1460 case lir_irem: | |
| 1461 arithmetic_idiv(op->code(), | |
| 1462 op->in_opr1(), | |
| 1463 op->in_opr2(), | |
| 1464 op->in_opr3(), | |
| 1465 op->result_opr(), | |
| 1466 op->info()); | |
| 1467 break; | |
| 1468 default: ShouldNotReachHere(); break; | |
| 1469 } | |
| 1470 } | |
| 1471 | |
| 1472 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { | |
| 1473 #ifdef ASSERT | |
| 1474 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); | |
| 1475 if (op->block() != NULL) _branch_target_blocks.append(op->block()); | |
| 1476 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); | |
| 1477 #endif | |
| 1478 | |
| 1479 if (op->cond() == lir_cond_always) { | |
| 1480 if (op->info() != NULL) add_debug_info_for_branch(op->info()); | |
| 1481 __ jmp (*(op->label())); | |
| 1482 } else { | |
| 1483 Assembler::Condition acond = Assembler::zero; | |
| 1484 if (op->code() == lir_cond_float_branch) { | |
| 1485 assert(op->ublock() != NULL, "must have unordered successor"); | |
| 1486 __ jcc(Assembler::parity, *(op->ublock()->label())); | |
| 1487 switch(op->cond()) { | |
| 1488 case lir_cond_equal: acond = Assembler::equal; break; | |
| 1489 case lir_cond_notEqual: acond = Assembler::notEqual; break; | |
| 1490 case lir_cond_less: acond = Assembler::below; break; | |
| 1491 case lir_cond_lessEqual: acond = Assembler::belowEqual; break; | |
| 1492 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break; | |
| 1493 case lir_cond_greater: acond = Assembler::above; break; | |
| 1494 default: ShouldNotReachHere(); | |
| 1495 } | |
| 1496 } else { | |
| 1497 switch (op->cond()) { | |
| 1498 case lir_cond_equal: acond = Assembler::equal; break; | |
| 1499 case lir_cond_notEqual: acond = Assembler::notEqual; break; | |
| 1500 case lir_cond_less: acond = Assembler::less; break; | |
| 1501 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; | |
| 1502 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; | |
| 1503 case lir_cond_greater: acond = Assembler::greater; break; | |
| 1504 case lir_cond_belowEqual: acond = Assembler::belowEqual; break; | |
| 1505 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; | |
| 1506 default: ShouldNotReachHere(); | |
| 1507 } | |
| 1508 } | |
| 1509 __ jcc(acond,*(op->label())); | |
| 1510 } | |
| 1511 } | |
| 1512 | |
| 1513 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { | |
| 1514 LIR_Opr src = op->in_opr(); | |
| 1515 LIR_Opr dest = op->result_opr(); | |
| 1516 | |
| 1517 switch (op->bytecode()) { | |
| 1518 case Bytecodes::_i2l: | |
| 304 | 1519 #ifdef _LP64 |
| 1520 __ movl2ptr(dest->as_register_lo(), src->as_register()); | |
| 1521 #else | |
| 0 | 1522 move_regs(src->as_register(), dest->as_register_lo()); |
| 1523 move_regs(src->as_register(), dest->as_register_hi()); | |
| 1524 __ sarl(dest->as_register_hi(), 31); | |
| 304 | 1525 #endif // LP64 |
| 0 | 1526 break; |
| 1527 | |
| 1528 case Bytecodes::_l2i: | |
| 1529 move_regs(src->as_register_lo(), dest->as_register()); | |
| 1530 break; | |
| 1531 | |
| 1532 case Bytecodes::_i2b: | |
| 1533 move_regs(src->as_register(), dest->as_register()); | |
| 1534 __ sign_extend_byte(dest->as_register()); | |
| 1535 break; | |
| 1536 | |
| 1537 case Bytecodes::_i2c: | |
| 1538 move_regs(src->as_register(), dest->as_register()); | |
| 1539 __ andl(dest->as_register(), 0xFFFF); | |
| 1540 break; | |
| 1541 | |
| 1542 case Bytecodes::_i2s: | |
| 1543 move_regs(src->as_register(), dest->as_register()); | |
| 1544 __ sign_extend_short(dest->as_register()); | |
| 1545 break; | |
| 1546 | |
| 1547 | |
| 1548 case Bytecodes::_f2d: | |
| 1549 case Bytecodes::_d2f: | |
| 1550 if (dest->is_single_xmm()) { | |
| 1551 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg()); | |
| 1552 } else if (dest->is_double_xmm()) { | |
| 1553 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg()); | |
| 1554 } else { | |
| 1555 assert(src->fpu() == dest->fpu(), "register must be equal"); | |
| 1556 // do nothing (float result is rounded later through spilling) | |
| 1557 } | |
| 1558 break; | |
| 1559 | |
| 1560 case Bytecodes::_i2f: | |
| 1561 case Bytecodes::_i2d: | |
| 1562 if (dest->is_single_xmm()) { | |
| 304 | 1563 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register()); |
| 0 | 1564 } else if (dest->is_double_xmm()) { |
| 304 | 1565 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register()); |
| 0 | 1566 } else { |
| 1567 assert(dest->fpu() == 0, "result must be on TOS"); | |
| 1568 __ movl(Address(rsp, 0), src->as_register()); | |
| 1569 __ fild_s(Address(rsp, 0)); | |
| 1570 } | |
| 1571 break; | |
| 1572 | |
| 1573 case Bytecodes::_f2i: | |
| 1574 case Bytecodes::_d2i: | |
| 1575 if (src->is_single_xmm()) { | |
| 304 | 1576 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg()); |
| 0 | 1577 } else if (src->is_double_xmm()) { |
| 304 | 1578 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg()); |
| 0 | 1579 } else { |
| 1580 assert(src->fpu() == 0, "input must be on TOS"); | |
| 1581 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); | |
| 1582 __ fist_s(Address(rsp, 0)); | |
| 1583 __ movl(dest->as_register(), Address(rsp, 0)); | |
| 1584 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 1585 } | |
| 1586 | |
| 1587 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub | |
| 1588 assert(op->stub() != NULL, "stub required"); | |
| 1589 __ cmpl(dest->as_register(), 0x80000000); | |
| 1590 __ jcc(Assembler::equal, *op->stub()->entry()); | |
| 1591 __ bind(*op->stub()->continuation()); | |
| 1592 break; | |
| 1593 | |
| 1594 case Bytecodes::_l2f: | |
| 1595 case Bytecodes::_l2d: | |
| 1596 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)"); | |
| 1597 assert(dest->fpu() == 0, "result must be on TOS"); | |
| 1598 | |
| 304 | 1599 __ movptr(Address(rsp, 0), src->as_register_lo()); |
| 1600 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi())); | |
| 0 | 1601 __ fild_d(Address(rsp, 0)); |
| 1602 // float result is rounded later through spilling | |
| 1603 break; | |
| 1604 | |
| 1605 case Bytecodes::_f2l: | |
| 1606 case Bytecodes::_d2l: | |
| 1607 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)"); | |
| 1608 assert(src->fpu() == 0, "input must be on TOS"); | |
| 304 | 1609 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers"); |
| 0 | 1610 |
| 1611 // instruction sequence too long to inline it here | |
| 1612 { | |
| 1613 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id))); | |
| 1614 } | |
| 1615 break; | |
| 1616 | |
| 1617 default: ShouldNotReachHere(); | |
| 1618 } | |
| 1619 } | |
| 1620 | |
| 1621 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { | |
| 1622 if (op->init_check()) { | |
| 1623 __ cmpl(Address(op->klass()->as_register(), | |
| 1624 instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc)), | |
| 1625 instanceKlass::fully_initialized); | |
| 1626 add_debug_info_for_null_check_here(op->stub()->info()); | |
| 1627 __ jcc(Assembler::notEqual, *op->stub()->entry()); | |
| 1628 } | |
| 1629 __ allocate_object(op->obj()->as_register(), | |
| 1630 op->tmp1()->as_register(), | |
| 1631 op->tmp2()->as_register(), | |
| 1632 op->header_size(), | |
| 1633 op->object_size(), | |
| 1634 op->klass()->as_register(), | |
| 1635 *op->stub()->entry()); | |
| 1636 __ bind(*op->stub()->continuation()); | |
| 1637 } | |
| 1638 | |
| 1639 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { | |
|
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1640 Register len = op->len()->as_register(); |
|
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1641 LP64_ONLY( __ movslq(len, len); ) |
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1642 |
| 0 | 1643 if (UseSlowPath || |
| 1644 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || | |
| 1645 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { | |
| 1646 __ jmp(*op->stub()->entry()); | |
| 1647 } else { | |
| 1648 Register tmp1 = op->tmp1()->as_register(); | |
| 1649 Register tmp2 = op->tmp2()->as_register(); | |
| 1650 Register tmp3 = op->tmp3()->as_register(); | |
| 1651 if (len == tmp1) { | |
| 1652 tmp1 = tmp3; | |
| 1653 } else if (len == tmp2) { | |
| 1654 tmp2 = tmp3; | |
| 1655 } else if (len == tmp3) { | |
| 1656 // everything is ok | |
| 1657 } else { | |
| 304 | 1658 __ mov(tmp3, len); |
| 0 | 1659 } |
| 1660 __ allocate_array(op->obj()->as_register(), | |
| 1661 len, | |
| 1662 tmp1, | |
| 1663 tmp2, | |
| 1664 arrayOopDesc::header_size(op->type()), | |
| 1665 array_element_size(op->type()), | |
| 1666 op->klass()->as_register(), | |
| 1667 *op->stub()->entry()); | |
| 1668 } | |
| 1669 __ bind(*op->stub()->continuation()); | |
| 1670 } | |
| 1671 | |
| 1783 | 1672 void LIR_Assembler::type_profile_helper(Register mdo, |
| 1673 ciMethodData *md, ciProfileData *data, | |
| 1674 Register recv, Label* update_done) { | |
|
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1675 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { |
| 1783 | 1676 Label next_test; |
| 1677 // See if the receiver is receiver[n]. | |
| 1678 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)))); | |
| 1679 __ jccb(Assembler::notEqual, next_test); | |
| 1680 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))); | |
| 1681 __ addptr(data_addr, DataLayout::counter_increment); | |
|
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1682 __ jmp(*update_done); |
| 1783 | 1683 __ bind(next_test); |
| 1684 } | |
| 1685 | |
| 1686 // Didn't find receiver; find next empty slot and fill it in | |
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1687 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { |
| 1783 | 1688 Label next_test; |
| 1689 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))); | |
| 1690 __ cmpptr(recv_addr, (intptr_t)NULL_WORD); | |
| 1691 __ jccb(Assembler::notEqual, next_test); | |
| 1692 __ movptr(recv_addr, recv); | |
| 1693 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment); | |
|
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1694 __ jmp(*update_done); |
| 1783 | 1695 __ bind(next_test); |
| 1696 } | |
| 1697 } | |
| 1698 | |
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1699 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { |
| 1783 | 1700 // we always need a stub for the failure case. |
| 1701 CodeStub* stub = op->stub(); | |
| 1702 Register obj = op->object()->as_register(); | |
| 1703 Register k_RInfo = op->tmp1()->as_register(); | |
| 1704 Register klass_RInfo = op->tmp2()->as_register(); | |
| 1705 Register dst = op->result_opr()->as_register(); | |
| 1706 ciKlass* k = op->klass(); | |
| 1707 Register Rtmp1 = noreg; | |
| 1708 | |
| 1709 // check if it needs to be profiled | |
| 1710 ciMethodData* md; | |
| 1711 ciProfileData* data; | |
| 1712 | |
| 1713 if (op->should_profile()) { | |
| 1714 ciMethod* method = op->profiled_method(); | |
| 1715 assert(method != NULL, "Should have method"); | |
| 1716 int bci = op->profiled_bci(); | |
|
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1717 md = method->method_data_or_null(); |
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1718 assert(md != NULL, "Sanity"); |
| 1783 | 1719 data = md->bci_to_data(bci); |
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1720 assert(data != NULL, "need data for type check"); |
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1721 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); |
| 1783 | 1722 } |
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1723 Label profile_cast_success, profile_cast_failure; |
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1724 Label *success_target = op->should_profile() ? &profile_cast_success : success; |
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1725 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure; |
| 1783 | 1726 |
| 1727 if (obj == k_RInfo) { | |
| 1728 k_RInfo = dst; | |
| 1729 } else if (obj == klass_RInfo) { | |
| 1730 klass_RInfo = dst; | |
| 1731 } | |
| 2002 | 1732 if (k->is_loaded() && !UseCompressedOops) { |
| 1783 | 1733 select_different_registers(obj, dst, k_RInfo, klass_RInfo); |
| 1734 } else { | |
| 1735 Rtmp1 = op->tmp3()->as_register(); | |
| 1736 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1); | |
| 1737 } | |
| 1738 | |
| 1739 assert_different_registers(obj, k_RInfo, klass_RInfo); | |
| 1740 if (!k->is_loaded()) { | |
| 1741 jobject2reg_with_patching(k_RInfo, op->info_for_patch()); | |
| 1742 } else { | |
| 1743 #ifdef _LP64 | |
| 1744 __ movoop(k_RInfo, k->constant_encoding()); | |
| 1745 #endif // _LP64 | |
| 1746 } | |
| 1747 assert(obj != k_RInfo, "must be different"); | |
| 1748 | |
| 1749 __ cmpptr(obj, (int32_t)NULL_WORD); | |
| 1750 if (op->should_profile()) { | |
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1751 Label not_null; |
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1752 __ jccb(Assembler::notEqual, not_null); |
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1753 // Object is null; update MDO and exit |
| 1783 | 1754 Register mdo = klass_RInfo; |
| 1755 __ movoop(mdo, md->constant_encoding()); | |
| 1756 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); | |
| 1757 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); | |
| 1758 __ orl(data_addr, header_bits); | |
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1759 __ jmp(*obj_is_null); |
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1760 __ bind(not_null); |
| 1783 | 1761 } else { |
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1762 __ jcc(Assembler::equal, *obj_is_null); |
| 1783 | 1763 } |
| 1764 __ verify_oop(obj); | |
| 1765 | |
| 1766 if (op->fast_check()) { | |
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1767 // get object class |
| 1783 | 1768 // not a safepoint as obj null check happens earlier |
| 1769 #ifdef _LP64 | |
| 2002 | 1770 if (UseCompressedOops) { |
| 1771 __ load_klass(Rtmp1, obj); | |
| 1772 __ cmpptr(k_RInfo, Rtmp1); | |
| 1783 | 1773 } else { |
| 1774 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); | |
| 1775 } | |
| 2002 | 1776 #else |
| 1777 if (k->is_loaded()) { | |
| 1778 __ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding()); | |
| 1779 } else { | |
| 1780 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); | |
| 1781 } | |
| 1782 #endif | |
| 1783 | 1783 __ jcc(Assembler::notEqual, *failure_target); |
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1784 // successful cast, fall through to profile or jump |
| 1783 | 1785 } else { |
| 1786 // get object class | |
| 1787 // not a safepoint as obj null check happens earlier | |
| 2002 | 1788 __ load_klass(klass_RInfo, obj); |
| 1783 | 1789 if (k->is_loaded()) { |
| 1790 // See if we get an immediate positive hit | |
| 1791 #ifdef _LP64 | |
| 1792 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset())); | |
| 1793 #else | |
| 1794 __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding()); | |
| 1795 #endif // _LP64 | |
| 1796 if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() != k->super_check_offset()) { | |
| 1797 __ jcc(Assembler::notEqual, *failure_target); | |
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1798 // successful cast, fall through to profile or jump |
| 1783 | 1799 } else { |
| 1800 // See if we get an immediate positive hit | |
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1801 __ jcc(Assembler::equal, *success_target); |
| 1783 | 1802 // check for self |
| 1803 #ifdef _LP64 | |
| 1804 __ cmpptr(klass_RInfo, k_RInfo); | |
| 1805 #else | |
| 1806 __ cmpoop(klass_RInfo, k->constant_encoding()); | |
| 1807 #endif // _LP64 | |
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1808 __ jcc(Assembler::equal, *success_target); |
| 1783 | 1809 |
| 1810 __ push(klass_RInfo); | |
| 1811 #ifdef _LP64 | |
| 1812 __ push(k_RInfo); | |
| 1813 #else | |
| 1814 __ pushoop(k->constant_encoding()); | |
| 1815 #endif // _LP64 | |
| 1816 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); | |
| 1817 __ pop(klass_RInfo); | |
| 1818 __ pop(klass_RInfo); | |
| 1819 // result is a boolean | |
| 1820 __ cmpl(klass_RInfo, 0); | |
| 1821 __ jcc(Assembler::equal, *failure_target); | |
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1822 // successful cast, fall through to profile or jump |
| 1783 | 1823 } |
| 1824 } else { | |
| 1825 // perform the fast part of the checking logic | |
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1826 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); |
| 1783 | 1827 // call out-of-line instance of __ check_klass_subtype_slow_path(...): |
| 1828 __ push(klass_RInfo); | |
| 1829 __ push(k_RInfo); | |
| 1830 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); | |
| 1831 __ pop(klass_RInfo); | |
| 1832 __ pop(k_RInfo); | |
| 1833 // result is a boolean | |
| 1834 __ cmpl(k_RInfo, 0); | |
| 1835 __ jcc(Assembler::equal, *failure_target); | |
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1836 // successful cast, fall through to profile or jump |
| 1783 | 1837 } |
| 1838 } | |
| 1839 if (op->should_profile()) { | |
| 1840 Register mdo = klass_RInfo, recv = k_RInfo; | |
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1841 __ bind(profile_cast_success); |
| 1783 | 1842 __ movoop(mdo, md->constant_encoding()); |
| 2002 | 1843 __ load_klass(recv, obj); |
| 1783 | 1844 Label update_done; |
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1845 type_profile_helper(mdo, md, data, recv, success); |
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1846 __ jmp(*success); |
| 1783 | 1847 |
| 1848 __ bind(profile_cast_failure); | |
| 1849 __ movoop(mdo, md->constant_encoding()); | |
| 1850 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); | |
| 1851 __ subptr(counter_addr, DataLayout::counter_increment); | |
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1852 __ jmp(*failure); |
| 1783 | 1853 } |
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1854 __ jmp(*success); |
| 1783 | 1855 } |
| 0 | 1856 |
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1857 |
| 0 | 1858 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { |
| 1859 LIR_Code code = op->code(); | |
| 1860 if (code == lir_store_check) { | |
| 1861 Register value = op->object()->as_register(); | |
| 1862 Register array = op->array()->as_register(); | |
| 1863 Register k_RInfo = op->tmp1()->as_register(); | |
| 1864 Register klass_RInfo = op->tmp2()->as_register(); | |
| 1865 Register Rtmp1 = op->tmp3()->as_register(); | |
| 1866 | |
| 1867 CodeStub* stub = op->stub(); | |
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1868 |
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1869 // check if it needs to be profiled |
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1870 ciMethodData* md; |
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1871 ciProfileData* data; |
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1872 |
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1873 if (op->should_profile()) { |
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1874 ciMethod* method = op->profiled_method(); |
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1875 assert(method != NULL, "Should have method"); |
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1876 int bci = op->profiled_bci(); |
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1877 md = method->method_data_or_null(); |
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1878 assert(md != NULL, "Sanity"); |
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1879 data = md->bci_to_data(bci); |
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1880 assert(data != NULL, "need data for type check"); |
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1881 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); |
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1882 } |
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1883 Label profile_cast_success, profile_cast_failure, done; |
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1884 Label *success_target = op->should_profile() ? &profile_cast_success : &done; |
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1885 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry(); |
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1886 |
| 304 | 1887 __ cmpptr(value, (int32_t)NULL_WORD); |
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1888 if (op->should_profile()) { |
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1889 Label not_null; |
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1890 __ jccb(Assembler::notEqual, not_null); |
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1891 // Object is null; update MDO and exit |
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1892 Register mdo = klass_RInfo; |
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1893 __ movoop(mdo, md->constant_encoding()); |
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1894 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); |
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1895 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); |
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1896 __ orl(data_addr, header_bits); |
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1897 __ jmp(done); |
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1898 __ bind(not_null); |
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1899 } else { |
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1900 __ jcc(Assembler::equal, done); |
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1901 } |
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1902 |
| 0 | 1903 add_debug_info_for_null_check_here(op->info_for_exception()); |
| 2002 | 1904 __ load_klass(k_RInfo, array); |
| 1905 __ load_klass(klass_RInfo, value); | |
| 1906 | |
| 1907 // get instance klass (it's already uncompressed) | |
| 304 | 1908 __ movptr(k_RInfo, Address(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc))); |
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1909 // perform the fast part of the checking logic |
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1910 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); |
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1911 // call out-of-line instance of __ check_klass_subtype_slow_path(...): |
| 304 | 1912 __ push(klass_RInfo); |
| 1913 __ push(k_RInfo); | |
| 0 | 1914 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); |
| 304 | 1915 __ pop(klass_RInfo); |
| 1916 __ pop(k_RInfo); | |
| 1917 // result is a boolean | |
| 0 | 1918 __ cmpl(k_RInfo, 0); |
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1919 __ jcc(Assembler::equal, *failure_target); |
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1920 // fall through to the success case |
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1921 |
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1922 if (op->should_profile()) { |
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1923 Register mdo = klass_RInfo, recv = k_RInfo; |
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1924 __ bind(profile_cast_success); |
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1925 __ movoop(mdo, md->constant_encoding()); |
| 2002 | 1926 __ load_klass(recv, value); |
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1927 Label update_done; |
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1928 type_profile_helper(mdo, md, data, recv, &done); |
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1929 __ jmpb(done); |
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1930 |
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1931 __ bind(profile_cast_failure); |
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1932 __ movoop(mdo, md->constant_encoding()); |
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1933 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); |
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1934 __ subptr(counter_addr, DataLayout::counter_increment); |
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1935 __ jmp(*stub->entry()); |
| 0 | 1936 } |
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1937 |
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1938 __ bind(done); |
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1939 } else |
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1940 if (code == lir_checkcast) { |
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1941 Register obj = op->object()->as_register(); |
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1942 Register dst = op->result_opr()->as_register(); |
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1943 Label success; |
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1944 emit_typecheck_helper(op, &success, op->stub()->entry(), &success); |
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1945 __ bind(success); |
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1946 if (dst != obj) { |
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1947 __ mov(dst, obj); |
| 0 | 1948 } |
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1949 } else |
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1950 if (code == lir_instanceof) { |
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1951 Register obj = op->object()->as_register(); |
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1952 Register dst = op->result_opr()->as_register(); |
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1953 Label success, failure, done; |
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1954 emit_typecheck_helper(op, &success, &failure, &failure); |
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1955 __ bind(failure); |
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1956 __ xorptr(dst, dst); |
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1957 __ jmpb(done); |
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1958 __ bind(success); |
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1959 __ movptr(dst, 1); |
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1960 __ bind(done); |
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1961 } else { |
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1962 ShouldNotReachHere(); |
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1963 } |
| 0 | 1964 |
| 1965 } | |
| 1966 | |
| 1967 | |
| 1968 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { | |
| 304 | 1969 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) { |
| 0 | 1970 assert(op->cmp_value()->as_register_lo() == rax, "wrong register"); |
| 1971 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register"); | |
| 1972 assert(op->new_value()->as_register_lo() == rbx, "wrong register"); | |
| 1973 assert(op->new_value()->as_register_hi() == rcx, "wrong register"); | |
| 1974 Register addr = op->addr()->as_register(); | |
| 1975 if (os::is_MP()) { | |
| 1976 __ lock(); | |
| 1977 } | |
| 304 | 1978 NOT_LP64(__ cmpxchg8(Address(addr, 0))); |
| 1979 | |
| 1980 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) { | |
| 1981 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");) | |
| 1982 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); | |
| 0 | 1983 Register newval = op->new_value()->as_register(); |
| 1984 Register cmpval = op->cmp_value()->as_register(); | |
| 1985 assert(cmpval == rax, "wrong register"); | |
| 1986 assert(newval != NULL, "new val must be register"); | |
| 1987 assert(cmpval != newval, "cmp and new values must be in different registers"); | |
| 1988 assert(cmpval != addr, "cmp and addr must be in different registers"); | |
| 1989 assert(newval != addr, "new value and addr must be in different registers"); | |
| 2002 | 1990 |
| 304 | 1991 if ( op->code() == lir_cas_obj) { |
| 2002 | 1992 #ifdef _LP64 |
| 1993 if (UseCompressedOops) { | |
| 1994 __ encode_heap_oop(cmpval); | |
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1995 __ mov(rscratch1, newval); |
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1996 __ encode_heap_oop(rscratch1); |
| 2002 | 1997 if (os::is_MP()) { |
| 1998 __ lock(); | |
| 1999 } | |
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2000 // cmpval (rax) is implicitly used by this instruction |
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2001 __ cmpxchgl(rscratch1, Address(addr, 0)); |
| 2002 | 2002 } else |
| 2003 #endif | |
| 2004 { | |
| 2005 if (os::is_MP()) { | |
| 2006 __ lock(); | |
| 2007 } | |
| 2008 __ cmpxchgptr(newval, Address(addr, 0)); | |
| 2009 } | |
| 2010 } else { | |
| 2011 assert(op->code() == lir_cas_int, "lir_cas_int expected"); | |
| 2012 if (os::is_MP()) { | |
| 2013 __ lock(); | |
| 2014 } | |
| 304 | 2015 __ cmpxchgl(newval, Address(addr, 0)); |
| 2016 } | |
| 2017 #ifdef _LP64 | |
| 2018 } else if (op->code() == lir_cas_long) { | |
| 2019 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); | |
| 2020 Register newval = op->new_value()->as_register_lo(); | |
| 2021 Register cmpval = op->cmp_value()->as_register_lo(); | |
| 2022 assert(cmpval == rax, "wrong register"); | |
| 2023 assert(newval != NULL, "new val must be register"); | |
| 2024 assert(cmpval != newval, "cmp and new values must be in different registers"); | |
| 2025 assert(cmpval != addr, "cmp and addr must be in different registers"); | |
| 2026 assert(newval != addr, "new value and addr must be in different registers"); | |
| 2027 if (os::is_MP()) { | |
| 2028 __ lock(); | |
| 2029 } | |
| 2030 __ cmpxchgq(newval, Address(addr, 0)); | |
| 2031 #endif // _LP64 | |
| 0 | 2032 } else { |
| 2033 Unimplemented(); | |
| 2034 } | |
| 2035 } | |
| 2036 | |
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2037 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) { |
| 0 | 2038 Assembler::Condition acond, ncond; |
| 2039 switch (condition) { | |
| 2040 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break; | |
| 2041 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break; | |
| 2042 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break; | |
| 2043 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break; | |
| 2044 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break; | |
| 2045 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break; | |
| 2046 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break; | |
| 2047 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break; | |
| 2048 default: ShouldNotReachHere(); | |
| 2049 } | |
| 2050 | |
| 2051 if (opr1->is_cpu_register()) { | |
| 2052 reg2reg(opr1, result); | |
| 2053 } else if (opr1->is_stack()) { | |
| 2054 stack2reg(opr1, result, result->type()); | |
| 2055 } else if (opr1->is_constant()) { | |
| 2056 const2reg(opr1, result, lir_patch_none, NULL); | |
| 2057 } else { | |
| 2058 ShouldNotReachHere(); | |
| 2059 } | |
| 2060 | |
| 2061 if (VM_Version::supports_cmov() && !opr2->is_constant()) { | |
| 2062 // optimized version that does not require a branch | |
| 2063 if (opr2->is_single_cpu()) { | |
| 2064 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move"); | |
| 304 | 2065 __ cmov(ncond, result->as_register(), opr2->as_register()); |
| 0 | 2066 } else if (opr2->is_double_cpu()) { |
| 2067 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); | |
| 2068 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); | |
| 304 | 2069 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo()); |
| 2070 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());) | |
| 0 | 2071 } else if (opr2->is_single_stack()) { |
| 2072 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix())); | |
| 2073 } else if (opr2->is_double_stack()) { | |
| 304 | 2074 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes)); |
| 2075 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));) | |
| 0 | 2076 } else { |
| 2077 ShouldNotReachHere(); | |
| 2078 } | |
| 2079 | |
| 2080 } else { | |
| 2081 Label skip; | |
| 2082 __ jcc (acond, skip); | |
| 2083 if (opr2->is_cpu_register()) { | |
| 2084 reg2reg(opr2, result); | |
| 2085 } else if (opr2->is_stack()) { | |
| 2086 stack2reg(opr2, result, result->type()); | |
| 2087 } else if (opr2->is_constant()) { | |
| 2088 const2reg(opr2, result, lir_patch_none, NULL); | |
| 2089 } else { | |
| 2090 ShouldNotReachHere(); | |
| 2091 } | |
| 2092 __ bind(skip); | |
| 2093 } | |
| 2094 } | |
| 2095 | |
| 2096 | |
| 2097 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { | |
| 2098 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); | |
| 2099 | |
| 2100 if (left->is_single_cpu()) { | |
| 2101 assert(left == dest, "left and dest must be equal"); | |
| 2102 Register lreg = left->as_register(); | |
| 2103 | |
| 2104 if (right->is_single_cpu()) { | |
| 2105 // cpu register - cpu register | |
| 2106 Register rreg = right->as_register(); | |
| 2107 switch (code) { | |
| 2108 case lir_add: __ addl (lreg, rreg); break; | |
| 2109 case lir_sub: __ subl (lreg, rreg); break; | |
| 2110 case lir_mul: __ imull(lreg, rreg); break; | |
| 2111 default: ShouldNotReachHere(); | |
| 2112 } | |
| 2113 | |
| 2114 } else if (right->is_stack()) { | |
| 2115 // cpu register - stack | |
| 2116 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); | |
| 2117 switch (code) { | |
| 2118 case lir_add: __ addl(lreg, raddr); break; | |
| 2119 case lir_sub: __ subl(lreg, raddr); break; | |
| 2120 default: ShouldNotReachHere(); | |
| 2121 } | |
| 2122 | |
| 2123 } else if (right->is_constant()) { | |
| 2124 // cpu register - constant | |
| 2125 jint c = right->as_constant_ptr()->as_jint(); | |
| 2126 switch (code) { | |
| 2127 case lir_add: { | |
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2128 __ incrementl(lreg, c); |
| 0 | 2129 break; |
| 2130 } | |
| 2131 case lir_sub: { | |
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2132 __ decrementl(lreg, c); |
| 0 | 2133 break; |
| 2134 } | |
| 2135 default: ShouldNotReachHere(); | |
| 2136 } | |
| 2137 | |
| 2138 } else { | |
| 2139 ShouldNotReachHere(); | |
| 2140 } | |
| 2141 | |
| 2142 } else if (left->is_double_cpu()) { | |
| 2143 assert(left == dest, "left and dest must be equal"); | |
| 2144 Register lreg_lo = left->as_register_lo(); | |
| 2145 Register lreg_hi = left->as_register_hi(); | |
| 2146 | |
| 2147 if (right->is_double_cpu()) { | |
| 2148 // cpu register - cpu register | |
| 2149 Register rreg_lo = right->as_register_lo(); | |
| 2150 Register rreg_hi = right->as_register_hi(); | |
| 304 | 2151 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi)); |
| 2152 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo)); | |
| 0 | 2153 switch (code) { |
| 2154 case lir_add: | |
| 304 | 2155 __ addptr(lreg_lo, rreg_lo); |
| 2156 NOT_LP64(__ adcl(lreg_hi, rreg_hi)); | |
| 0 | 2157 break; |
| 2158 case lir_sub: | |
| 304 | 2159 __ subptr(lreg_lo, rreg_lo); |
| 2160 NOT_LP64(__ sbbl(lreg_hi, rreg_hi)); | |
| 0 | 2161 break; |
| 2162 case lir_mul: | |
| 304 | 2163 #ifdef _LP64 |
| 2164 __ imulq(lreg_lo, rreg_lo); | |
| 2165 #else | |
| 0 | 2166 assert(lreg_lo == rax && lreg_hi == rdx, "must be"); |
| 2167 __ imull(lreg_hi, rreg_lo); | |
| 2168 __ imull(rreg_hi, lreg_lo); | |
| 2169 __ addl (rreg_hi, lreg_hi); | |
| 2170 __ mull (rreg_lo); | |
| 2171 __ addl (lreg_hi, rreg_hi); | |
| 304 | 2172 #endif // _LP64 |
| 0 | 2173 break; |
| 2174 default: | |
| 2175 ShouldNotReachHere(); | |
| 2176 } | |
| 2177 | |
| 2178 } else if (right->is_constant()) { | |
| 2179 // cpu register - constant | |
| 304 | 2180 #ifdef _LP64 |
| 2181 jlong c = right->as_constant_ptr()->as_jlong_bits(); | |
| 2182 __ movptr(r10, (intptr_t) c); | |
| 2183 switch (code) { | |
| 2184 case lir_add: | |
| 2185 __ addptr(lreg_lo, r10); | |
| 2186 break; | |
| 2187 case lir_sub: | |
| 2188 __ subptr(lreg_lo, r10); | |
| 2189 break; | |
| 2190 default: | |
| 2191 ShouldNotReachHere(); | |
| 2192 } | |
| 2193 #else | |
| 0 | 2194 jint c_lo = right->as_constant_ptr()->as_jint_lo(); |
| 2195 jint c_hi = right->as_constant_ptr()->as_jint_hi(); | |
| 2196 switch (code) { | |
| 2197 case lir_add: | |
| 304 | 2198 __ addptr(lreg_lo, c_lo); |
| 0 | 2199 __ adcl(lreg_hi, c_hi); |
| 2200 break; | |
| 2201 case lir_sub: | |
| 304 | 2202 __ subptr(lreg_lo, c_lo); |
| 0 | 2203 __ sbbl(lreg_hi, c_hi); |
| 2204 break; | |
| 2205 default: | |
| 2206 ShouldNotReachHere(); | |
| 2207 } | |
| 304 | 2208 #endif // _LP64 |
| 0 | 2209 |
| 2210 } else { | |
| 2211 ShouldNotReachHere(); | |
| 2212 } | |
| 2213 | |
| 2214 } else if (left->is_single_xmm()) { | |
| 2215 assert(left == dest, "left and dest must be equal"); | |
| 2216 XMMRegister lreg = left->as_xmm_float_reg(); | |
| 2217 | |
| 2218 if (right->is_single_xmm()) { | |
| 2219 XMMRegister rreg = right->as_xmm_float_reg(); | |
| 2220 switch (code) { | |
| 2221 case lir_add: __ addss(lreg, rreg); break; | |
| 2222 case lir_sub: __ subss(lreg, rreg); break; | |
| 2223 case lir_mul_strictfp: // fall through | |
| 2224 case lir_mul: __ mulss(lreg, rreg); break; | |
| 2225 case lir_div_strictfp: // fall through | |
| 2226 case lir_div: __ divss(lreg, rreg); break; | |
| 2227 default: ShouldNotReachHere(); | |
| 2228 } | |
| 2229 } else { | |
| 2230 Address raddr; | |
| 2231 if (right->is_single_stack()) { | |
| 2232 raddr = frame_map()->address_for_slot(right->single_stack_ix()); | |
| 2233 } else if (right->is_constant()) { | |
| 2234 // hack for now | |
| 2235 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat()))); | |
| 2236 } else { | |
| 2237 ShouldNotReachHere(); | |
| 2238 } | |
| 2239 switch (code) { | |
| 2240 case lir_add: __ addss(lreg, raddr); break; | |
| 2241 case lir_sub: __ subss(lreg, raddr); break; | |
| 2242 case lir_mul_strictfp: // fall through | |
| 2243 case lir_mul: __ mulss(lreg, raddr); break; | |
| 2244 case lir_div_strictfp: // fall through | |
| 2245 case lir_div: __ divss(lreg, raddr); break; | |
| 2246 default: ShouldNotReachHere(); | |
| 2247 } | |
| 2248 } | |
| 2249 | |
| 2250 } else if (left->is_double_xmm()) { | |
| 2251 assert(left == dest, "left and dest must be equal"); | |
| 2252 | |
| 2253 XMMRegister lreg = left->as_xmm_double_reg(); | |
| 2254 if (right->is_double_xmm()) { | |
| 2255 XMMRegister rreg = right->as_xmm_double_reg(); | |
| 2256 switch (code) { | |
| 2257 case lir_add: __ addsd(lreg, rreg); break; | |
| 2258 case lir_sub: __ subsd(lreg, rreg); break; | |
| 2259 case lir_mul_strictfp: // fall through | |
| 2260 case lir_mul: __ mulsd(lreg, rreg); break; | |
| 2261 case lir_div_strictfp: // fall through | |
| 2262 case lir_div: __ divsd(lreg, rreg); break; | |
| 2263 default: ShouldNotReachHere(); | |
| 2264 } | |
| 2265 } else { | |
| 2266 Address raddr; | |
| 2267 if (right->is_double_stack()) { | |
| 2268 raddr = frame_map()->address_for_slot(right->double_stack_ix()); | |
| 2269 } else if (right->is_constant()) { | |
| 2270 // hack for now | |
| 2271 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); | |
| 2272 } else { | |
| 2273 ShouldNotReachHere(); | |
| 2274 } | |
| 2275 switch (code) { | |
| 2276 case lir_add: __ addsd(lreg, raddr); break; | |
| 2277 case lir_sub: __ subsd(lreg, raddr); break; | |
| 2278 case lir_mul_strictfp: // fall through | |
| 2279 case lir_mul: __ mulsd(lreg, raddr); break; | |
| 2280 case lir_div_strictfp: // fall through | |
| 2281 case lir_div: __ divsd(lreg, raddr); break; | |
| 2282 default: ShouldNotReachHere(); | |
| 2283 } | |
| 2284 } | |
| 2285 | |
| 2286 } else if (left->is_single_fpu()) { | |
| 2287 assert(dest->is_single_fpu(), "fpu stack allocation required"); | |
| 2288 | |
| 2289 if (right->is_single_fpu()) { | |
| 2290 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack); | |
| 2291 | |
| 2292 } else { | |
| 2293 assert(left->fpu_regnr() == 0, "left must be on TOS"); | |
| 2294 assert(dest->fpu_regnr() == 0, "dest must be on TOS"); | |
| 2295 | |
| 2296 Address raddr; | |
| 2297 if (right->is_single_stack()) { | |
| 2298 raddr = frame_map()->address_for_slot(right->single_stack_ix()); | |
| 2299 } else if (right->is_constant()) { | |
| 2300 address const_addr = float_constant(right->as_jfloat()); | |
| 2301 assert(const_addr != NULL, "incorrect float/double constant maintainance"); | |
| 2302 // hack for now | |
| 2303 raddr = __ as_Address(InternalAddress(const_addr)); | |
| 2304 } else { | |
| 2305 ShouldNotReachHere(); | |
| 2306 } | |
| 2307 | |
| 2308 switch (code) { | |
| 2309 case lir_add: __ fadd_s(raddr); break; | |
| 2310 case lir_sub: __ fsub_s(raddr); break; | |
| 2311 case lir_mul_strictfp: // fall through | |
| 2312 case lir_mul: __ fmul_s(raddr); break; | |
| 2313 case lir_div_strictfp: // fall through | |
| 2314 case lir_div: __ fdiv_s(raddr); break; | |
| 2315 default: ShouldNotReachHere(); | |
| 2316 } | |
| 2317 } | |
| 2318 | |
| 2319 } else if (left->is_double_fpu()) { | |
| 2320 assert(dest->is_double_fpu(), "fpu stack allocation required"); | |
| 2321 | |
| 2322 if (code == lir_mul_strictfp || code == lir_div_strictfp) { | |
| 2323 // Double values require special handling for strictfp mul/div on x86 | |
| 2324 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1())); | |
| 2325 __ fmulp(left->fpu_regnrLo() + 1); | |
| 2326 } | |
| 2327 | |
| 2328 if (right->is_double_fpu()) { | |
| 2329 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack); | |
| 2330 | |
| 2331 } else { | |
| 2332 assert(left->fpu_regnrLo() == 0, "left must be on TOS"); | |
| 2333 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS"); | |
| 2334 | |
| 2335 Address raddr; | |
| 2336 if (right->is_double_stack()) { | |
| 2337 raddr = frame_map()->address_for_slot(right->double_stack_ix()); | |
| 2338 } else if (right->is_constant()) { | |
| 2339 // hack for now | |
| 2340 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); | |
| 2341 } else { | |
| 2342 ShouldNotReachHere(); | |
| 2343 } | |
| 2344 | |
| 2345 switch (code) { | |
| 2346 case lir_add: __ fadd_d(raddr); break; | |
| 2347 case lir_sub: __ fsub_d(raddr); break; | |
| 2348 case lir_mul_strictfp: // fall through | |
| 2349 case lir_mul: __ fmul_d(raddr); break; | |
| 2350 case lir_div_strictfp: // fall through | |
| 2351 case lir_div: __ fdiv_d(raddr); break; | |
| 2352 default: ShouldNotReachHere(); | |
| 2353 } | |
| 2354 } | |
| 2355 | |
| 2356 if (code == lir_mul_strictfp || code == lir_div_strictfp) { | |
| 2357 // Double values require special handling for strictfp mul/div on x86 | |
| 2358 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2())); | |
| 2359 __ fmulp(dest->fpu_regnrLo() + 1); | |
| 2360 } | |
| 2361 | |
| 2362 } else if (left->is_single_stack() || left->is_address()) { | |
| 2363 assert(left == dest, "left and dest must be equal"); | |
| 2364 | |
| 2365 Address laddr; | |
| 2366 if (left->is_single_stack()) { | |
| 2367 laddr = frame_map()->address_for_slot(left->single_stack_ix()); | |
| 2368 } else if (left->is_address()) { | |
| 2369 laddr = as_Address(left->as_address_ptr()); | |
| 2370 } else { | |
| 2371 ShouldNotReachHere(); | |
| 2372 } | |
| 2373 | |
| 2374 if (right->is_single_cpu()) { | |
| 2375 Register rreg = right->as_register(); | |
| 2376 switch (code) { | |
| 2377 case lir_add: __ addl(laddr, rreg); break; | |
| 2378 case lir_sub: __ subl(laddr, rreg); break; | |
| 2379 default: ShouldNotReachHere(); | |
| 2380 } | |
| 2381 } else if (right->is_constant()) { | |
| 2382 jint c = right->as_constant_ptr()->as_jint(); | |
| 2383 switch (code) { | |
| 2384 case lir_add: { | |
| 304 | 2385 __ incrementl(laddr, c); |
| 0 | 2386 break; |
| 2387 } | |
| 2388 case lir_sub: { | |
| 304 | 2389 __ decrementl(laddr, c); |
| 0 | 2390 break; |
| 2391 } | |
| 2392 default: ShouldNotReachHere(); | |
| 2393 } | |
| 2394 } else { | |
| 2395 ShouldNotReachHere(); | |
| 2396 } | |
| 2397 | |
| 2398 } else { | |
| 2399 ShouldNotReachHere(); | |
| 2400 } | |
| 2401 } | |
| 2402 | |
| 2403 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { | |
| 2404 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR"); | |
| 2405 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR"); | |
| 2406 assert(left_index == 0 || right_index == 0, "either must be on top of stack"); | |
| 2407 | |
| 2408 bool left_is_tos = (left_index == 0); | |
| 2409 bool dest_is_tos = (dest_index == 0); | |
| 2410 int non_tos_index = (left_is_tos ? right_index : left_index); | |
| 2411 | |
| 2412 switch (code) { | |
| 2413 case lir_add: | |
| 2414 if (pop_fpu_stack) __ faddp(non_tos_index); | |
| 2415 else if (dest_is_tos) __ fadd (non_tos_index); | |
| 2416 else __ fadda(non_tos_index); | |
| 2417 break; | |
| 2418 | |
| 2419 case lir_sub: | |
| 2420 if (left_is_tos) { | |
| 2421 if (pop_fpu_stack) __ fsubrp(non_tos_index); | |
| 2422 else if (dest_is_tos) __ fsub (non_tos_index); | |
| 2423 else __ fsubra(non_tos_index); | |
| 2424 } else { | |
| 2425 if (pop_fpu_stack) __ fsubp (non_tos_index); | |
| 2426 else if (dest_is_tos) __ fsubr (non_tos_index); | |
| 2427 else __ fsuba (non_tos_index); | |
| 2428 } | |
| 2429 break; | |
| 2430 | |
| 2431 case lir_mul_strictfp: // fall through | |
| 2432 case lir_mul: | |
| 2433 if (pop_fpu_stack) __ fmulp(non_tos_index); | |
| 2434 else if (dest_is_tos) __ fmul (non_tos_index); | |
| 2435 else __ fmula(non_tos_index); | |
| 2436 break; | |
| 2437 | |
| 2438 case lir_div_strictfp: // fall through | |
| 2439 case lir_div: | |
| 2440 if (left_is_tos) { | |
| 2441 if (pop_fpu_stack) __ fdivrp(non_tos_index); | |
| 2442 else if (dest_is_tos) __ fdiv (non_tos_index); | |
| 2443 else __ fdivra(non_tos_index); | |
| 2444 } else { | |
| 2445 if (pop_fpu_stack) __ fdivp (non_tos_index); | |
| 2446 else if (dest_is_tos) __ fdivr (non_tos_index); | |
| 2447 else __ fdiva (non_tos_index); | |
| 2448 } | |
| 2449 break; | |
| 2450 | |
| 2451 case lir_rem: | |
| 2452 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation"); | |
| 2453 __ fremr(noreg); | |
| 2454 break; | |
| 2455 | |
| 2456 default: | |
| 2457 ShouldNotReachHere(); | |
| 2458 } | |
| 2459 } | |
| 2460 | |
| 2461 | |
| 2462 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) { | |
| 2463 if (value->is_double_xmm()) { | |
| 2464 switch(code) { | |
| 2465 case lir_abs : | |
| 2466 { | |
| 2467 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) { | |
| 2468 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); | |
| 2469 } | |
| 2470 __ andpd(dest->as_xmm_double_reg(), | |
| 2471 ExternalAddress((address)double_signmask_pool)); | |
| 2472 } | |
| 2473 break; | |
| 2474 | |
| 2475 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break; | |
| 2476 // all other intrinsics are not available in the SSE instruction set, so FPU is used | |
| 2477 default : ShouldNotReachHere(); | |
| 2478 } | |
| 2479 | |
| 2480 } else if (value->is_double_fpu()) { | |
| 2481 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS"); | |
| 2482 switch(code) { | |
| 2483 case lir_log : __ flog() ; break; | |
| 2484 case lir_log10 : __ flog10() ; break; | |
| 2485 case lir_abs : __ fabs() ; break; | |
| 2486 case lir_sqrt : __ fsqrt(); break; | |
| 2487 case lir_sin : | |
| 2488 // Should consider not saving rbx, if not necessary | |
| 2489 __ trigfunc('s', op->as_Op2()->fpu_stack_size()); | |
| 2490 break; | |
| 2491 case lir_cos : | |
| 2492 // Should consider not saving rbx, if not necessary | |
| 2493 assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots"); | |
| 2494 __ trigfunc('c', op->as_Op2()->fpu_stack_size()); | |
| 2495 break; | |
| 2496 case lir_tan : | |
| 2497 // Should consider not saving rbx, if not necessary | |
| 2498 __ trigfunc('t', op->as_Op2()->fpu_stack_size()); | |
| 2499 break; | |
| 2500 default : ShouldNotReachHere(); | |
| 2501 } | |
| 2502 } else { | |
| 2503 Unimplemented(); | |
| 2504 } | |
| 2505 } | |
| 2506 | |
| 2507 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { | |
| 2508 // assert(left->destroys_register(), "check"); | |
| 2509 if (left->is_single_cpu()) { | |
| 2510 Register reg = left->as_register(); | |
| 2511 if (right->is_constant()) { | |
| 2512 int val = right->as_constant_ptr()->as_jint(); | |
| 2513 switch (code) { | |
| 2514 case lir_logic_and: __ andl (reg, val); break; | |
| 2515 case lir_logic_or: __ orl (reg, val); break; | |
| 2516 case lir_logic_xor: __ xorl (reg, val); break; | |
| 2517 default: ShouldNotReachHere(); | |
| 2518 } | |
| 2519 } else if (right->is_stack()) { | |
| 2520 // added support for stack operands | |
| 2521 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); | |
| 2522 switch (code) { | |
| 2523 case lir_logic_and: __ andl (reg, raddr); break; | |
| 2524 case lir_logic_or: __ orl (reg, raddr); break; | |
| 2525 case lir_logic_xor: __ xorl (reg, raddr); break; | |
| 2526 default: ShouldNotReachHere(); | |
| 2527 } | |
| 2528 } else { | |
| 2529 Register rright = right->as_register(); | |
| 2530 switch (code) { | |
| 304 | 2531 case lir_logic_and: __ andptr (reg, rright); break; |
| 2532 case lir_logic_or : __ orptr (reg, rright); break; | |
| 2533 case lir_logic_xor: __ xorptr (reg, rright); break; | |
| 0 | 2534 default: ShouldNotReachHere(); |
| 2535 } | |
| 2536 } | |
| 2537 move_regs(reg, dst->as_register()); | |
| 2538 } else { | |
| 2539 Register l_lo = left->as_register_lo(); | |
| 2540 Register l_hi = left->as_register_hi(); | |
| 2541 if (right->is_constant()) { | |
| 304 | 2542 #ifdef _LP64 |
| 2543 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong()); | |
| 2544 switch (code) { | |
| 2545 case lir_logic_and: | |
| 2546 __ andq(l_lo, rscratch1); | |
| 2547 break; | |
| 2548 case lir_logic_or: | |
| 2549 __ orq(l_lo, rscratch1); | |
| 2550 break; | |
| 2551 case lir_logic_xor: | |
| 2552 __ xorq(l_lo, rscratch1); | |
| 2553 break; | |
| 2554 default: ShouldNotReachHere(); | |
| 2555 } | |
| 2556 #else | |
| 0 | 2557 int r_lo = right->as_constant_ptr()->as_jint_lo(); |
| 2558 int r_hi = right->as_constant_ptr()->as_jint_hi(); | |
| 2559 switch (code) { | |
| 2560 case lir_logic_and: | |
| 2561 __ andl(l_lo, r_lo); | |
| 2562 __ andl(l_hi, r_hi); | |
| 2563 break; | |
| 2564 case lir_logic_or: | |
| 2565 __ orl(l_lo, r_lo); | |
| 2566 __ orl(l_hi, r_hi); | |
| 2567 break; | |
| 2568 case lir_logic_xor: | |
| 2569 __ xorl(l_lo, r_lo); | |
| 2570 __ xorl(l_hi, r_hi); | |
| 2571 break; | |
| 2572 default: ShouldNotReachHere(); | |
| 2573 } | |
| 304 | 2574 #endif // _LP64 |
| 0 | 2575 } else { |
| 1572 | 2576 #ifdef _LP64 |
| 2577 Register r_lo; | |
| 2578 if (right->type() == T_OBJECT || right->type() == T_ARRAY) { | |
| 2579 r_lo = right->as_register(); | |
| 2580 } else { | |
| 2581 r_lo = right->as_register_lo(); | |
| 2582 } | |
| 2583 #else | |
| 0 | 2584 Register r_lo = right->as_register_lo(); |
| 2585 Register r_hi = right->as_register_hi(); | |
| 2586 assert(l_lo != r_hi, "overwriting registers"); | |
| 1572 | 2587 #endif |
| 0 | 2588 switch (code) { |
| 2589 case lir_logic_and: | |
| 304 | 2590 __ andptr(l_lo, r_lo); |
| 2591 NOT_LP64(__ andptr(l_hi, r_hi);) | |
| 0 | 2592 break; |
| 2593 case lir_logic_or: | |
| 304 | 2594 __ orptr(l_lo, r_lo); |
| 2595 NOT_LP64(__ orptr(l_hi, r_hi);) | |
| 0 | 2596 break; |
| 2597 case lir_logic_xor: | |
| 304 | 2598 __ xorptr(l_lo, r_lo); |
| 2599 NOT_LP64(__ xorptr(l_hi, r_hi);) | |
| 0 | 2600 break; |
| 2601 default: ShouldNotReachHere(); | |
| 2602 } | |
| 2603 } | |
| 2604 | |
| 2605 Register dst_lo = dst->as_register_lo(); | |
| 2606 Register dst_hi = dst->as_register_hi(); | |
| 2607 | |
| 304 | 2608 #ifdef _LP64 |
| 2609 move_regs(l_lo, dst_lo); | |
| 2610 #else | |
| 0 | 2611 if (dst_lo == l_hi) { |
| 2612 assert(dst_hi != l_lo, "overwriting registers"); | |
| 2613 move_regs(l_hi, dst_hi); | |
| 2614 move_regs(l_lo, dst_lo); | |
| 2615 } else { | |
| 2616 assert(dst_lo != l_hi, "overwriting registers"); | |
| 2617 move_regs(l_lo, dst_lo); | |
| 2618 move_regs(l_hi, dst_hi); | |
| 2619 } | |
| 304 | 2620 #endif // _LP64 |
| 0 | 2621 } |
| 2622 } | |
| 2623 | |
| 2624 | |
| 2625 // we assume that rax, and rdx can be overwritten | |
| 2626 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { | |
| 2627 | |
| 2628 assert(left->is_single_cpu(), "left must be register"); | |
| 2629 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant"); | |
| 2630 assert(result->is_single_cpu(), "result must be register"); | |
| 2631 | |
| 2632 // assert(left->destroys_register(), "check"); | |
| 2633 // assert(right->destroys_register(), "check"); | |
| 2634 | |
| 2635 Register lreg = left->as_register(); | |
| 2636 Register dreg = result->as_register(); | |
| 2637 | |
| 2638 if (right->is_constant()) { | |
| 2639 int divisor = right->as_constant_ptr()->as_jint(); | |
| 2640 assert(divisor > 0 && is_power_of_2(divisor), "must be"); | |
| 2641 if (code == lir_idiv) { | |
| 2642 assert(lreg == rax, "must be rax,"); | |
| 2643 assert(temp->as_register() == rdx, "tmp register must be rdx"); | |
| 2644 __ cdql(); // sign extend into rdx:rax | |
| 2645 if (divisor == 2) { | |
| 2646 __ subl(lreg, rdx); | |
| 2647 } else { | |
| 2648 __ andl(rdx, divisor - 1); | |
| 2649 __ addl(lreg, rdx); | |
| 2650 } | |
| 2651 __ sarl(lreg, log2_intptr(divisor)); | |
| 2652 move_regs(lreg, dreg); | |
| 2653 } else if (code == lir_irem) { | |
| 2654 Label done; | |
| 304 | 2655 __ mov(dreg, lreg); |
| 0 | 2656 __ andl(dreg, 0x80000000 | (divisor - 1)); |
| 2657 __ jcc(Assembler::positive, done); | |
| 2658 __ decrement(dreg); | |
| 2659 __ orl(dreg, ~(divisor - 1)); | |
| 2660 __ increment(dreg); | |
| 2661 __ bind(done); | |
| 2662 } else { | |
| 2663 ShouldNotReachHere(); | |
| 2664 } | |
| 2665 } else { | |
| 2666 Register rreg = right->as_register(); | |
| 2667 assert(lreg == rax, "left register must be rax,"); | |
| 2668 assert(rreg != rdx, "right register must not be rdx"); | |
| 2669 assert(temp->as_register() == rdx, "tmp register must be rdx"); | |
| 2670 | |
| 2671 move_regs(lreg, rax); | |
| 2672 | |
| 2673 int idivl_offset = __ corrected_idivl(rreg); | |
| 2674 add_debug_info_for_div0(idivl_offset, info); | |
| 2675 if (code == lir_irem) { | |
| 2676 move_regs(rdx, dreg); // result is in rdx | |
| 2677 } else { | |
| 2678 move_regs(rax, dreg); | |
| 2679 } | |
| 2680 } | |
| 2681 } | |
| 2682 | |
| 2683 | |
| 2684 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { | |
| 2685 if (opr1->is_single_cpu()) { | |
| 2686 Register reg1 = opr1->as_register(); | |
| 2687 if (opr2->is_single_cpu()) { | |
| 2688 // cpu register - cpu register | |
| 304 | 2689 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { |
| 2690 __ cmpptr(reg1, opr2->as_register()); | |
| 2691 } else { | |
| 2692 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?"); | |
| 2693 __ cmpl(reg1, opr2->as_register()); | |
| 2694 } | |
| 0 | 2695 } else if (opr2->is_stack()) { |
| 2696 // cpu register - stack | |
| 304 | 2697 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { |
| 2698 __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); | |
| 2699 } else { | |
| 2700 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); | |
| 2701 } | |
| 0 | 2702 } else if (opr2->is_constant()) { |
| 2703 // cpu register - constant | |
| 2704 LIR_Const* c = opr2->as_constant_ptr(); | |
| 2705 if (c->type() == T_INT) { | |
| 2706 __ cmpl(reg1, c->as_jint()); | |
| 304 | 2707 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { |
| 2708 // In 64bit oops are single register | |
| 0 | 2709 jobject o = c->as_jobject(); |
| 2710 if (o == NULL) { | |
| 304 | 2711 __ cmpptr(reg1, (int32_t)NULL_WORD); |
| 0 | 2712 } else { |
| 304 | 2713 #ifdef _LP64 |
| 2714 __ movoop(rscratch1, o); | |
| 2715 __ cmpptr(reg1, rscratch1); | |
| 2716 #else | |
| 0 | 2717 __ cmpoop(reg1, c->as_jobject()); |
| 304 | 2718 #endif // _LP64 |
| 0 | 2719 } |
| 2720 } else { | |
| 2721 ShouldNotReachHere(); | |
| 2722 } | |
| 2723 // cpu register - address | |
| 2724 } else if (opr2->is_address()) { | |
| 2725 if (op->info() != NULL) { | |
| 2726 add_debug_info_for_null_check_here(op->info()); | |
| 2727 } | |
| 2728 __ cmpl(reg1, as_Address(opr2->as_address_ptr())); | |
| 2729 } else { | |
| 2730 ShouldNotReachHere(); | |
| 2731 } | |
| 2732 | |
| 2733 } else if(opr1->is_double_cpu()) { | |
| 2734 Register xlo = opr1->as_register_lo(); | |
| 2735 Register xhi = opr1->as_register_hi(); | |
| 2736 if (opr2->is_double_cpu()) { | |
| 304 | 2737 #ifdef _LP64 |
| 2738 __ cmpptr(xlo, opr2->as_register_lo()); | |
| 2739 #else | |
| 0 | 2740 // cpu register - cpu register |
| 2741 Register ylo = opr2->as_register_lo(); | |
| 2742 Register yhi = opr2->as_register_hi(); | |
| 2743 __ subl(xlo, ylo); | |
| 2744 __ sbbl(xhi, yhi); | |
| 2745 if (condition == lir_cond_equal || condition == lir_cond_notEqual) { | |
| 2746 __ orl(xhi, xlo); | |
| 2747 } | |
| 304 | 2748 #endif // _LP64 |
| 0 | 2749 } else if (opr2->is_constant()) { |
| 2750 // cpu register - constant 0 | |
| 2751 assert(opr2->as_jlong() == (jlong)0, "only handles zero"); | |
| 304 | 2752 #ifdef _LP64 |
| 2753 __ cmpptr(xlo, (int32_t)opr2->as_jlong()); | |
| 2754 #else | |
| 0 | 2755 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case"); |
| 2756 __ orl(xhi, xlo); | |
| 304 | 2757 #endif // _LP64 |
| 0 | 2758 } else { |
| 2759 ShouldNotReachHere(); | |
| 2760 } | |
| 2761 | |
| 2762 } else if (opr1->is_single_xmm()) { | |
| 2763 XMMRegister reg1 = opr1->as_xmm_float_reg(); | |
| 2764 if (opr2->is_single_xmm()) { | |
| 2765 // xmm register - xmm register | |
| 2766 __ ucomiss(reg1, opr2->as_xmm_float_reg()); | |
| 2767 } else if (opr2->is_stack()) { | |
| 2768 // xmm register - stack | |
| 2769 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); | |
| 2770 } else if (opr2->is_constant()) { | |
| 2771 // xmm register - constant | |
| 2772 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat()))); | |
| 2773 } else if (opr2->is_address()) { | |
| 2774 // xmm register - address | |
| 2775 if (op->info() != NULL) { | |
| 2776 add_debug_info_for_null_check_here(op->info()); | |
| 2777 } | |
| 2778 __ ucomiss(reg1, as_Address(opr2->as_address_ptr())); | |
| 2779 } else { | |
| 2780 ShouldNotReachHere(); | |
| 2781 } | |
| 2782 | |
| 2783 } else if (opr1->is_double_xmm()) { | |
| 2784 XMMRegister reg1 = opr1->as_xmm_double_reg(); | |
| 2785 if (opr2->is_double_xmm()) { | |
| 2786 // xmm register - xmm register | |
| 2787 __ ucomisd(reg1, opr2->as_xmm_double_reg()); | |
| 2788 } else if (opr2->is_stack()) { | |
| 2789 // xmm register - stack | |
| 2790 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix())); | |
| 2791 } else if (opr2->is_constant()) { | |
| 2792 // xmm register - constant | |
| 2793 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble()))); | |
| 2794 } else if (opr2->is_address()) { | |
| 2795 // xmm register - address | |
| 2796 if (op->info() != NULL) { | |
| 2797 add_debug_info_for_null_check_here(op->info()); | |
| 2798 } | |
| 2799 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address())); | |
| 2800 } else { | |
| 2801 ShouldNotReachHere(); | |
| 2802 } | |
| 2803 | |
| 2804 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) { | |
| 2805 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)"); | |
| 2806 assert(opr2->is_fpu_register(), "both must be registers"); | |
| 2807 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); | |
| 2808 | |
| 2809 } else if (opr1->is_address() && opr2->is_constant()) { | |
| 304 | 2810 LIR_Const* c = opr2->as_constant_ptr(); |
| 2811 #ifdef _LP64 | |
| 2812 if (c->type() == T_OBJECT || c->type() == T_ARRAY) { | |
| 2813 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse"); | |
| 2814 __ movoop(rscratch1, c->as_jobject()); | |
| 2815 } | |
| 2816 #endif // LP64 | |
| 0 | 2817 if (op->info() != NULL) { |
| 2818 add_debug_info_for_null_check_here(op->info()); | |
| 2819 } | |
| 2820 // special case: address - constant | |
| 2821 LIR_Address* addr = opr1->as_address_ptr(); | |
| 2822 if (c->type() == T_INT) { | |
| 2823 __ cmpl(as_Address(addr), c->as_jint()); | |
| 304 | 2824 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { |
| 2825 #ifdef _LP64 | |
| 2826 // %%% Make this explode if addr isn't reachable until we figure out a | |
| 2827 // better strategy by giving noreg as the temp for as_Address | |
| 2828 __ cmpptr(rscratch1, as_Address(addr, noreg)); | |
| 2829 #else | |
| 0 | 2830 __ cmpoop(as_Address(addr), c->as_jobject()); |
| 304 | 2831 #endif // _LP64 |
| 0 | 2832 } else { |
| 2833 ShouldNotReachHere(); | |
| 2834 } | |
| 2835 | |
| 2836 } else { | |
| 2837 ShouldNotReachHere(); | |
| 2838 } | |
| 2839 } | |
| 2840 | |
| 2841 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) { | |
| 2842 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { | |
| 2843 if (left->is_single_xmm()) { | |
| 2844 assert(right->is_single_xmm(), "must match"); | |
| 2845 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i); | |
| 2846 } else if (left->is_double_xmm()) { | |
| 2847 assert(right->is_double_xmm(), "must match"); | |
| 2848 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i); | |
| 2849 | |
| 2850 } else { | |
| 2851 assert(left->is_single_fpu() || left->is_double_fpu(), "must be"); | |
| 2852 assert(right->is_single_fpu() || right->is_double_fpu(), "must match"); | |
| 2853 | |
| 2854 assert(left->fpu() == 0, "left must be on TOS"); | |
| 2855 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(), | |
| 2856 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); | |
| 2857 } | |
| 2858 } else { | |
| 2859 assert(code == lir_cmp_l2i, "check"); | |
| 304 | 2860 #ifdef _LP64 |
| 1369 | 2861 Label done; |
| 2862 Register dest = dst->as_register(); | |
| 2863 __ cmpptr(left->as_register_lo(), right->as_register_lo()); | |
| 2864 __ movl(dest, -1); | |
| 2865 __ jccb(Assembler::less, done); | |
| 2866 __ set_byte_if_not_zero(dest); | |
| 2867 __ movzbl(dest, dest); | |
| 2868 __ bind(done); | |
| 304 | 2869 #else |
| 0 | 2870 __ lcmp2int(left->as_register_hi(), |
| 2871 left->as_register_lo(), | |
| 2872 right->as_register_hi(), | |
| 2873 right->as_register_lo()); | |
| 2874 move_regs(left->as_register_hi(), dst->as_register()); | |
| 304 | 2875 #endif // _LP64 |
| 0 | 2876 } |
| 2877 } | |
| 2878 | |
| 2879 | |
| 2880 void LIR_Assembler::align_call(LIR_Code code) { | |
| 2881 if (os::is_MP()) { | |
| 2882 // make sure that the displacement word of the call ends up word aligned | |
| 2883 int offset = __ offset(); | |
| 2884 switch (code) { | |
| 2885 case lir_static_call: | |
| 2886 case lir_optvirtual_call: | |
| 1295 | 2887 case lir_dynamic_call: |
| 0 | 2888 offset += NativeCall::displacement_offset; |
| 2889 break; | |
| 2890 case lir_icvirtual_call: | |
| 2891 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size; | |
| 2892 break; | |
| 2893 case lir_virtual_call: // currently, sparc-specific for niagara | |
| 2894 default: ShouldNotReachHere(); | |
| 2895 } | |
| 2896 while (offset++ % BytesPerWord != 0) { | |
| 2897 __ nop(); | |
| 2898 } | |
| 2899 } | |
| 2900 } | |
| 2901 | |
| 2902 | |
| 1295 | 2903 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { |
| 0 | 2904 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, |
| 2905 "must be aligned"); | |
| 1295 | 2906 __ call(AddressLiteral(op->addr(), rtype)); |
| 1564 | 2907 add_call_info(code_offset(), op->info()); |
| 0 | 2908 } |
| 2909 | |
| 2910 | |
| 1295 | 2911 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { |
| 0 | 2912 RelocationHolder rh = virtual_call_Relocation::spec(pc()); |
| 2913 __ movoop(IC_Klass, (jobject)Universe::non_oop_word()); | |
| 2914 assert(!os::is_MP() || | |
| 2915 (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, | |
| 2916 "must be aligned"); | |
| 1295 | 2917 __ call(AddressLiteral(op->addr(), rh)); |
| 1564 | 2918 add_call_info(code_offset(), op->info()); |
| 0 | 2919 } |
| 2920 | |
| 2921 | |
| 2922 /* Currently, vtable-dispatch is only enabled for sparc platforms */ | |
| 1295 | 2923 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) { |
| 0 | 2924 ShouldNotReachHere(); |
| 2925 } | |
| 2926 | |
| 1295 | 2927 |
| 0 | 2928 void LIR_Assembler::emit_static_call_stub() { |
| 2929 address call_pc = __ pc(); | |
| 2930 address stub = __ start_a_stub(call_stub_size); | |
| 2931 if (stub == NULL) { | |
| 2932 bailout("static call stub overflow"); | |
| 2933 return; | |
| 2934 } | |
| 2935 | |
| 2936 int start = __ offset(); | |
| 2937 if (os::is_MP()) { | |
| 2938 // make sure that the displacement word of the call ends up word aligned | |
| 2939 int offset = __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset; | |
| 2940 while (offset++ % BytesPerWord != 0) { | |
| 2941 __ nop(); | |
| 2942 } | |
| 2943 } | |
| 2944 __ relocate(static_stub_Relocation::spec(call_pc)); | |
| 2945 __ movoop(rbx, (jobject)NULL); | |
| 2946 // must be set to -1 at code generation time | |
| 2947 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP"); | |
| 304 | 2948 // On 64bit this will die since it will take a movq & jmp, must be only a jmp |
| 2949 __ jump(RuntimeAddress(__ pc())); | |
| 0 | 2950 |
|
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2951 assert(__ offset() - start <= call_stub_size, "stub too big"); |
| 0 | 2952 __ end_a_stub(); |
| 2953 } | |
| 2954 | |
| 2955 | |
|
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2956 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { |
| 0 | 2957 assert(exceptionOop->as_register() == rax, "must match"); |
|
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2958 assert(exceptionPC->as_register() == rdx, "must match"); |
| 0 | 2959 |
| 2960 // exception object is not added to oop map by LinearScan | |
| 2961 // (LinearScan assumes that no oops are in fixed registers) | |
| 2962 info->add_register_oop(exceptionOop); | |
| 2963 Runtime1::StubID unwind_id; | |
| 2964 | |
|
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2965 // get current pc information |
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2966 // pc is only needed if the method has an exception handler, the unwind code does not need it. |
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2967 int pc_for_athrow_offset = __ offset(); |
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2968 InternalAddress pc_for_athrow(__ pc()); |
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2969 __ lea(exceptionPC->as_register(), pc_for_athrow); |
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2970 add_call_info(pc_for_athrow_offset, info); // for exception handler |
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2971 |
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2972 __ verify_not_null_oop(rax); |
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2973 // search an exception handler (rax: exception oop, rdx: throwing pc) |
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2974 if (compilation()->has_fpu_code()) { |
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2975 unwind_id = Runtime1::handle_exception_id; |
| 0 | 2976 } else { |
|
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2977 unwind_id = Runtime1::handle_exception_nofpu_id; |
| 0 | 2978 } |
|
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2979 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id))); |
| 0 | 2980 |
| 2981 // enough room for two byte trap | |
| 2982 __ nop(); | |
| 2983 } | |
| 2984 | |
| 2985 | |
|
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2986 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { |
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2987 assert(exceptionOop->as_register() == rax, "must match"); |
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2988 |
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2989 __ jmp(_unwind_handler_entry); |
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2990 } |
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2991 |
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2992 |
| 0 | 2993 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { |
| 2994 | |
| 2995 // optimized version for linear scan: | |
| 2996 // * count must be already in ECX (guaranteed by LinearScan) | |
| 2997 // * left and dest must be equal | |
| 2998 // * tmp must be unused | |
| 2999 assert(count->as_register() == SHIFT_count, "count must be in ECX"); | |
| 3000 assert(left == dest, "left and dest must be equal"); | |
| 3001 assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); | |
| 3002 | |
| 3003 if (left->is_single_cpu()) { | |
| 3004 Register value = left->as_register(); | |
| 3005 assert(value != SHIFT_count, "left cannot be ECX"); | |
| 3006 | |
| 3007 switch (code) { | |
| 3008 case lir_shl: __ shll(value); break; | |
| 3009 case lir_shr: __ sarl(value); break; | |
| 3010 case lir_ushr: __ shrl(value); break; | |
| 3011 default: ShouldNotReachHere(); | |
| 3012 } | |
| 3013 } else if (left->is_double_cpu()) { | |
| 3014 Register lo = left->as_register_lo(); | |
| 3015 Register hi = left->as_register_hi(); | |
| 3016 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX"); | |
| 304 | 3017 #ifdef _LP64 |
| 3018 switch (code) { | |
| 3019 case lir_shl: __ shlptr(lo); break; | |
| 3020 case lir_shr: __ sarptr(lo); break; | |
| 3021 case lir_ushr: __ shrptr(lo); break; | |
| 3022 default: ShouldNotReachHere(); | |
| 3023 } | |
| 3024 #else | |
| 0 | 3025 |
| 3026 switch (code) { | |
| 3027 case lir_shl: __ lshl(hi, lo); break; | |
| 3028 case lir_shr: __ lshr(hi, lo, true); break; | |
| 3029 case lir_ushr: __ lshr(hi, lo, false); break; | |
| 3030 default: ShouldNotReachHere(); | |
| 3031 } | |
| 304 | 3032 #endif // LP64 |
| 0 | 3033 } else { |
| 3034 ShouldNotReachHere(); | |
| 3035 } | |
| 3036 } | |
| 3037 | |
| 3038 | |
| 3039 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { | |
| 3040 if (dest->is_single_cpu()) { | |
| 3041 // first move left into dest so that left is not destroyed by the shift | |
| 3042 Register value = dest->as_register(); | |
| 3043 count = count & 0x1F; // Java spec | |
| 3044 | |
| 3045 move_regs(left->as_register(), value); | |
| 3046 switch (code) { | |
| 3047 case lir_shl: __ shll(value, count); break; | |
| 3048 case lir_shr: __ sarl(value, count); break; | |
| 3049 case lir_ushr: __ shrl(value, count); break; | |
| 3050 default: ShouldNotReachHere(); | |
| 3051 } | |
| 3052 } else if (dest->is_double_cpu()) { | |
| 304 | 3053 #ifndef _LP64 |
| 0 | 3054 Unimplemented(); |
| 304 | 3055 #else |
| 3056 // first move left into dest so that left is not destroyed by the shift | |
| 3057 Register value = dest->as_register_lo(); | |
| 3058 count = count & 0x1F; // Java spec | |
| 3059 | |
| 3060 move_regs(left->as_register_lo(), value); | |
| 3061 switch (code) { | |
| 3062 case lir_shl: __ shlptr(value, count); break; | |
| 3063 case lir_shr: __ sarptr(value, count); break; | |
| 3064 case lir_ushr: __ shrptr(value, count); break; | |
| 3065 default: ShouldNotReachHere(); | |
| 3066 } | |
| 3067 #endif // _LP64 | |
| 0 | 3068 } else { |
| 3069 ShouldNotReachHere(); | |
| 3070 } | |
| 3071 } | |
| 3072 | |
| 3073 | |
| 3074 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) { | |
| 3075 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); | |
| 3076 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; | |
| 3077 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); | |
| 304 | 3078 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r); |
| 0 | 3079 } |
| 3080 | |
| 3081 | |
| 3082 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) { | |
| 3083 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); | |
| 3084 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; | |
| 3085 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); | |
| 304 | 3086 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c); |
| 0 | 3087 } |
| 3088 | |
| 3089 | |
| 3090 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) { | |
| 3091 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); | |
| 3092 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; | |
| 3093 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); | |
| 3094 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o); | |
| 3095 } | |
| 3096 | |
| 3097 | |
| 3098 // This code replaces a call to arraycopy; no exception may | |
| 3099 // be thrown in this code, they must be thrown in the System.arraycopy | |
| 3100 // activation frame; we could save some checks if this would not be the case | |
| 3101 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { | |
| 3102 ciArrayKlass* default_type = op->expected_type(); | |
| 3103 Register src = op->src()->as_register(); | |
| 3104 Register dst = op->dst()->as_register(); | |
| 3105 Register src_pos = op->src_pos()->as_register(); | |
| 3106 Register dst_pos = op->dst_pos()->as_register(); | |
| 3107 Register length = op->length()->as_register(); | |
| 3108 Register tmp = op->tmp()->as_register(); | |
| 3109 | |
| 3110 CodeStub* stub = op->stub(); | |
| 3111 int flags = op->flags(); | |
| 3112 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; | |
| 3113 if (basic_type == T_ARRAY) basic_type = T_OBJECT; | |
| 3114 | |
| 3115 // if we don't know anything or it's an object array, just go through the generic arraycopy | |
| 3116 if (default_type == NULL) { | |
| 3117 Label done; | |
| 3118 // save outgoing arguments on stack in case call to System.arraycopy is needed | |
| 3119 // HACK ALERT. This code used to push the parameters in a hardwired fashion | |
| 3120 // for interpreter calling conventions. Now we have to do it in new style conventions. | |
| 3121 // For the moment until C1 gets the new register allocator I just force all the | |
| 3122 // args to the right place (except the register args) and then on the back side | |
| 3123 // reload the register args properly if we go slow path. Yuck | |
| 3124 | |
| 3125 // These are proper for the calling convention | |
| 3126 | |
| 3127 store_parameter(length, 2); | |
| 3128 store_parameter(dst_pos, 1); | |
| 3129 store_parameter(dst, 0); | |
| 3130 | |
| 3131 // these are just temporary placements until we need to reload | |
| 3132 store_parameter(src_pos, 3); | |
| 3133 store_parameter(src, 4); | |
| 304 | 3134 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");) |
| 3135 | |
| 3136 address entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy); | |
| 0 | 3137 |
| 3138 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint | |
| 304 | 3139 #ifdef _LP64 |
| 3140 // The arguments are in java calling convention so we can trivially shift them to C | |
| 3141 // convention | |
| 3142 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4); | |
| 3143 __ mov(c_rarg0, j_rarg0); | |
| 3144 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4); | |
| 3145 __ mov(c_rarg1, j_rarg1); | |
| 3146 assert_different_registers(c_rarg2, j_rarg3, j_rarg4); | |
| 3147 __ mov(c_rarg2, j_rarg2); | |
| 3148 assert_different_registers(c_rarg3, j_rarg4); | |
| 3149 __ mov(c_rarg3, j_rarg3); | |
| 3150 #ifdef _WIN64 | |
| 3151 // Allocate abi space for args but be sure to keep stack aligned | |
| 3152 __ subptr(rsp, 6*wordSize); | |
| 3153 store_parameter(j_rarg4, 4); | |
| 3154 __ call(RuntimeAddress(entry)); | |
| 3155 __ addptr(rsp, 6*wordSize); | |
| 3156 #else | |
| 3157 __ mov(c_rarg4, j_rarg4); | |
| 3158 __ call(RuntimeAddress(entry)); | |
| 3159 #endif // _WIN64 | |
| 3160 #else | |
| 3161 __ push(length); | |
| 3162 __ push(dst_pos); | |
| 3163 __ push(dst); | |
| 3164 __ push(src_pos); | |
| 3165 __ push(src); | |
| 0 | 3166 __ call_VM_leaf(entry, 5); // removes pushed parameter from the stack |
| 3167 | |
| 304 | 3168 #endif // _LP64 |
| 3169 | |
| 0 | 3170 __ cmpl(rax, 0); |
| 3171 __ jcc(Assembler::equal, *stub->continuation()); | |
| 3172 | |
| 3173 // Reload values from the stack so they are where the stub | |
| 3174 // expects them. | |
| 304 | 3175 __ movptr (dst, Address(rsp, 0*BytesPerWord)); |
| 3176 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); | |
| 3177 __ movptr (length, Address(rsp, 2*BytesPerWord)); | |
| 3178 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); | |
| 3179 __ movptr (src, Address(rsp, 4*BytesPerWord)); | |
| 0 | 3180 __ jmp(*stub->entry()); |
| 3181 | |
| 3182 __ bind(*stub->continuation()); | |
| 3183 return; | |
| 3184 } | |
| 3185 | |
| 3186 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); | |
| 3187 | |
|
29
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0
diff
changeset
|
3188 int elem_size = type2aelembytes(basic_type); |
| 0 | 3189 int shift_amount; |
| 3190 Address::ScaleFactor scale; | |
| 3191 | |
| 3192 switch (elem_size) { | |
| 3193 case 1 : | |
| 3194 shift_amount = 0; | |
| 3195 scale = Address::times_1; | |
| 3196 break; | |
| 3197 case 2 : | |
| 3198 shift_amount = 1; | |
| 3199 scale = Address::times_2; | |
| 3200 break; | |
| 3201 case 4 : | |
| 3202 shift_amount = 2; | |
| 3203 scale = Address::times_4; | |
| 3204 break; | |
| 3205 case 8 : | |
| 3206 shift_amount = 3; | |
| 3207 scale = Address::times_8; | |
| 3208 break; | |
| 3209 default: | |
| 3210 ShouldNotReachHere(); | |
| 3211 } | |
| 3212 | |
| 3213 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); | |
| 3214 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes()); | |
| 3215 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes()); | |
| 3216 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes()); | |
| 3217 | |
| 304 | 3218 // length and pos's are all sign extended at this point on 64bit |
| 3219 | |
| 0 | 3220 // test for NULL |
| 3221 if (flags & LIR_OpArrayCopy::src_null_check) { | |
| 304 | 3222 __ testptr(src, src); |
| 0 | 3223 __ jcc(Assembler::zero, *stub->entry()); |
| 3224 } | |
| 3225 if (flags & LIR_OpArrayCopy::dst_null_check) { | |
| 304 | 3226 __ testptr(dst, dst); |
| 0 | 3227 __ jcc(Assembler::zero, *stub->entry()); |
| 3228 } | |
| 3229 | |
| 3230 // check if negative | |
| 3231 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { | |
| 3232 __ testl(src_pos, src_pos); | |
| 3233 __ jcc(Assembler::less, *stub->entry()); | |
| 3234 } | |
| 3235 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { | |
| 3236 __ testl(dst_pos, dst_pos); | |
| 3237 __ jcc(Assembler::less, *stub->entry()); | |
| 3238 } | |
| 3239 if (flags & LIR_OpArrayCopy::length_positive_check) { | |
| 3240 __ testl(length, length); | |
| 3241 __ jcc(Assembler::less, *stub->entry()); | |
| 3242 } | |
| 3243 | |
| 3244 if (flags & LIR_OpArrayCopy::src_range_check) { | |
| 304 | 3245 __ lea(tmp, Address(src_pos, length, Address::times_1, 0)); |
| 0 | 3246 __ cmpl(tmp, src_length_addr); |
| 3247 __ jcc(Assembler::above, *stub->entry()); | |
| 3248 } | |
| 3249 if (flags & LIR_OpArrayCopy::dst_range_check) { | |
| 304 | 3250 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0)); |
| 0 | 3251 __ cmpl(tmp, dst_length_addr); |
| 3252 __ jcc(Assembler::above, *stub->entry()); | |
| 3253 } | |
| 3254 | |
| 3255 if (flags & LIR_OpArrayCopy::type_check) { | |
| 2002 | 3256 if (UseCompressedOops) { |
| 3257 __ movl(tmp, src_klass_addr); | |
| 3258 __ cmpl(tmp, dst_klass_addr); | |
| 3259 } else { | |
| 3260 __ movptr(tmp, src_klass_addr); | |
| 3261 __ cmpptr(tmp, dst_klass_addr); | |
| 3262 } | |
| 0 | 3263 __ jcc(Assembler::notEqual, *stub->entry()); |
| 3264 } | |
| 3265 | |
| 3266 #ifdef ASSERT | |
| 3267 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { | |
| 3268 // Sanity check the known type with the incoming class. For the | |
| 3269 // primitive case the types must match exactly with src.klass and | |
| 3270 // dst.klass each exactly matching the default type. For the | |
| 3271 // object array case, if no type check is needed then either the | |
| 3272 // dst type is exactly the expected type and the src type is a | |
| 3273 // subtype which we can't check or src is the same array as dst | |
| 3274 // but not necessarily exactly of type default_type. | |
| 3275 Label known_ok, halt; | |
|
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780
diff
changeset
|
3276 __ movoop(tmp, default_type->constant_encoding()); |
| 2002 | 3277 #ifdef _LP64 |
| 3278 if (UseCompressedOops) { | |
| 3279 __ encode_heap_oop(tmp); | |
| 3280 } | |
| 3281 #endif | |
| 3282 | |
| 0 | 3283 if (basic_type != T_OBJECT) { |
| 2002 | 3284 |
| 3285 if (UseCompressedOops) __ cmpl(tmp, dst_klass_addr); | |
| 3286 else __ cmpptr(tmp, dst_klass_addr); | |
| 0 | 3287 __ jcc(Assembler::notEqual, halt); |
| 2002 | 3288 if (UseCompressedOops) __ cmpl(tmp, src_klass_addr); |
| 3289 else __ cmpptr(tmp, src_klass_addr); | |
| 0 | 3290 __ jcc(Assembler::equal, known_ok); |
| 3291 } else { | |
| 2002 | 3292 if (UseCompressedOops) __ cmpl(tmp, dst_klass_addr); |
| 3293 else __ cmpptr(tmp, dst_klass_addr); | |
| 0 | 3294 __ jcc(Assembler::equal, known_ok); |
| 304 | 3295 __ cmpptr(src, dst); |
| 0 | 3296 __ jcc(Assembler::equal, known_ok); |
| 3297 } | |
| 3298 __ bind(halt); | |
| 3299 __ stop("incorrect type information in arraycopy"); | |
| 3300 __ bind(known_ok); | |
| 3301 } | |
| 3302 #endif | |
| 3303 | |
| 304 | 3304 if (shift_amount > 0 && basic_type != T_OBJECT) { |
| 3305 __ shlptr(length, shift_amount); | |
| 3306 } | |
| 3307 | |
| 3308 #ifdef _LP64 | |
| 3309 assert_different_registers(c_rarg0, dst, dst_pos, length); | |
| 1060 | 3310 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null |
| 304 | 3311 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); |
| 3312 assert_different_registers(c_rarg1, length); | |
| 1060 | 3313 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null |
| 304 | 3314 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); |
| 3315 __ mov(c_rarg2, length); | |
| 3316 | |
| 3317 #else | |
| 3318 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); | |
| 0 | 3319 store_parameter(tmp, 0); |
| 304 | 3320 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); |
| 0 | 3321 store_parameter(tmp, 1); |
| 3322 store_parameter(length, 2); | |
| 304 | 3323 #endif // _LP64 |
| 0 | 3324 if (basic_type == T_OBJECT) { |
| 3325 __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy), 0); | |
| 3326 } else { | |
| 3327 __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::primitive_arraycopy), 0); | |
| 3328 } | |
| 3329 | |
| 3330 __ bind(*stub->continuation()); | |
| 3331 } | |
| 3332 | |
| 3333 | |
| 3334 void LIR_Assembler::emit_lock(LIR_OpLock* op) { | |
| 3335 Register obj = op->obj_opr()->as_register(); // may not be an oop | |
| 3336 Register hdr = op->hdr_opr()->as_register(); | |
| 3337 Register lock = op->lock_opr()->as_register(); | |
| 3338 if (!UseFastLocking) { | |
| 3339 __ jmp(*op->stub()->entry()); | |
| 3340 } else if (op->code() == lir_lock) { | |
| 3341 Register scratch = noreg; | |
| 3342 if (UseBiasedLocking) { | |
| 3343 scratch = op->scratch_opr()->as_register(); | |
| 3344 } | |
| 3345 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); | |
| 3346 // add debug info for NullPointerException only if one is possible | |
| 3347 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry()); | |
| 3348 if (op->info() != NULL) { | |
| 3349 add_debug_info_for_null_check(null_check_offset, op->info()); | |
| 3350 } | |
| 3351 // done | |
| 3352 } else if (op->code() == lir_unlock) { | |
| 3353 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); | |
| 3354 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); | |
| 3355 } else { | |
| 3356 Unimplemented(); | |
| 3357 } | |
| 3358 __ bind(*op->stub()->continuation()); | |
| 3359 } | |
| 3360 | |
| 3361 | |
| 3362 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { | |
| 3363 ciMethod* method = op->profiled_method(); | |
| 3364 int bci = op->profiled_bci(); | |
| 3365 | |
| 3366 // Update counter for all call types | |
|
2007
5ddfcf4b079e
7003554: (tiered) assert(is_null_object() || handle() != NULL) failed: cannot embed null pointer
iveresov
parents:
2002
diff
changeset
|
3367 ciMethodData* md = method->method_data_or_null(); |
|
5ddfcf4b079e
7003554: (tiered) assert(is_null_object() || handle() != NULL) failed: cannot embed null pointer
iveresov
parents:
2002
diff
changeset
|
3368 assert(md != NULL, "Sanity"); |
| 0 | 3369 ciProfileData* data = md->bci_to_data(bci); |
| 3370 assert(data->is_CounterData(), "need CounterData for calls"); | |
| 3371 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); | |
| 3372 Register mdo = op->mdo()->as_register(); | |
|
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parents:
780
diff
changeset
|
3373 __ movoop(mdo, md->constant_encoding()); |
| 0 | 3374 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); |
| 3375 Bytecodes::Code bc = method->java_code_at_bci(bci); | |
| 3376 // Perform additional virtual call profiling for invokevirtual and | |
| 3377 // invokeinterface bytecodes | |
| 3378 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) && | |
| 1783 | 3379 C1ProfileVirtualCalls) { |
| 0 | 3380 assert(op->recv()->is_single_cpu(), "recv must be allocated"); |
| 3381 Register recv = op->recv()->as_register(); | |
| 3382 assert_different_registers(mdo, recv); | |
| 3383 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); | |
| 3384 ciKlass* known_klass = op->known_holder(); | |
| 1783 | 3385 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) { |
| 0 | 3386 // We know the type that will be seen at this call site; we can |
| 3387 // statically update the methodDataOop rather than needing to do | |
| 3388 // dynamic tests on the receiver type | |
| 3389 | |
| 3390 // NOTE: we should probably put a lock around this search to | |
| 3391 // avoid collisions by concurrent compilations | |
| 3392 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; | |
| 3393 uint i; | |
| 3394 for (i = 0; i < VirtualCallData::row_limit(); i++) { | |
| 3395 ciKlass* receiver = vc_data->receiver(i); | |
| 3396 if (known_klass->equals(receiver)) { | |
| 3397 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); | |
| 1783 | 3398 __ addptr(data_addr, DataLayout::counter_increment); |
| 0 | 3399 return; |
| 3400 } | |
| 3401 } | |
| 3402 | |
| 3403 // Receiver type not found in profile data; select an empty slot | |
| 3404 | |
| 3405 // Note that this is less efficient than it should be because it | |
| 3406 // always does a write to the receiver part of the | |
| 3407 // VirtualCallData rather than just the first time | |
| 3408 for (i = 0; i < VirtualCallData::row_limit(); i++) { | |
| 3409 ciKlass* receiver = vc_data->receiver(i); | |
| 3410 if (receiver == NULL) { | |
| 3411 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); | |
|
989
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jrose
parents:
780
diff
changeset
|
3412 __ movoop(recv_addr, known_klass->constant_encoding()); |
| 0 | 3413 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); |
| 1783 | 3414 __ addptr(data_addr, DataLayout::counter_increment); |
| 0 | 3415 return; |
| 3416 } | |
| 3417 } | |
| 3418 } else { | |
| 2002 | 3419 __ load_klass(recv, recv); |
| 0 | 3420 Label update_done; |
| 1783 | 3421 type_profile_helper(mdo, md, data, recv, &update_done); |
|
1206
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1204
diff
changeset
|
3422 // Receiver did not match any saved receiver and there is no empty row for it. |
|
1251
576e77447e3c
6923002: assert(false,"this call site should not be polymorphic")
kvn
parents:
1206
diff
changeset
|
3423 // Increment total counter to indicate polymorphic case. |
| 1783 | 3424 __ addptr(counter_addr, DataLayout::counter_increment); |
| 0 | 3425 |
| 3426 __ bind(update_done); | |
| 3427 } | |
|
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diff
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|
3428 } else { |
|
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diff
changeset
|
3429 // Static call |
| 1783 | 3430 __ addptr(counter_addr, DataLayout::counter_increment); |
| 0 | 3431 } |
| 3432 } | |
| 3433 | |
| 3434 void LIR_Assembler::emit_delay(LIR_OpDelay*) { | |
| 3435 Unimplemented(); | |
| 3436 } | |
| 3437 | |
| 3438 | |
| 3439 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) { | |
| 304 | 3440 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no)); |
| 0 | 3441 } |
| 3442 | |
| 3443 | |
| 3444 void LIR_Assembler::align_backward_branch_target() { | |
| 3445 __ align(BytesPerWord); | |
| 3446 } | |
| 3447 | |
| 3448 | |
| 3449 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { | |
| 3450 if (left->is_single_cpu()) { | |
| 3451 __ negl(left->as_register()); | |
| 3452 move_regs(left->as_register(), dest->as_register()); | |
| 3453 | |
| 3454 } else if (left->is_double_cpu()) { | |
| 3455 Register lo = left->as_register_lo(); | |
| 304 | 3456 #ifdef _LP64 |
| 3457 Register dst = dest->as_register_lo(); | |
| 3458 __ movptr(dst, lo); | |
| 3459 __ negptr(dst); | |
| 3460 #else | |
| 0 | 3461 Register hi = left->as_register_hi(); |
| 3462 __ lneg(hi, lo); | |
| 3463 if (dest->as_register_lo() == hi) { | |
| 3464 assert(dest->as_register_hi() != lo, "destroying register"); | |
| 3465 move_regs(hi, dest->as_register_hi()); | |
| 3466 move_regs(lo, dest->as_register_lo()); | |
| 3467 } else { | |
| 3468 move_regs(lo, dest->as_register_lo()); | |
| 3469 move_regs(hi, dest->as_register_hi()); | |
| 3470 } | |
| 304 | 3471 #endif // _LP64 |
| 0 | 3472 |
| 3473 } else if (dest->is_single_xmm()) { | |
| 3474 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) { | |
| 3475 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg()); | |
| 3476 } | |
| 3477 __ xorps(dest->as_xmm_float_reg(), | |
| 3478 ExternalAddress((address)float_signflip_pool)); | |
| 3479 | |
| 3480 } else if (dest->is_double_xmm()) { | |
| 3481 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) { | |
| 3482 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg()); | |
| 3483 } | |
| 3484 __ xorpd(dest->as_xmm_double_reg(), | |
| 3485 ExternalAddress((address)double_signflip_pool)); | |
| 3486 | |
| 3487 } else if (left->is_single_fpu() || left->is_double_fpu()) { | |
| 3488 assert(left->fpu() == 0, "arg must be on TOS"); | |
| 3489 assert(dest->fpu() == 0, "dest must be TOS"); | |
| 3490 __ fchs(); | |
| 3491 | |
| 3492 } else { | |
| 3493 ShouldNotReachHere(); | |
| 3494 } | |
| 3495 } | |
| 3496 | |
| 3497 | |
| 3498 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) { | |
| 3499 assert(addr->is_address() && dest->is_register(), "check"); | |
| 304 | 3500 Register reg; |
| 3501 reg = dest->as_pointer_register(); | |
| 3502 __ lea(reg, as_Address(addr->as_address_ptr())); | |
| 0 | 3503 } |
| 3504 | |
| 3505 | |
| 3506 | |
| 3507 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { | |
| 3508 assert(!tmp->is_valid(), "don't need temporary"); | |
| 3509 __ call(RuntimeAddress(dest)); | |
| 3510 if (info != NULL) { | |
| 3511 add_call_info_here(info); | |
| 3512 } | |
| 3513 } | |
| 3514 | |
| 3515 | |
| 3516 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { | |
| 3517 assert(type == T_LONG, "only for volatile long fields"); | |
| 3518 | |
| 3519 if (info != NULL) { | |
| 3520 add_debug_info_for_null_check_here(info); | |
| 3521 } | |
| 3522 | |
| 3523 if (src->is_double_xmm()) { | |
| 3524 if (dest->is_double_cpu()) { | |
| 304 | 3525 #ifdef _LP64 |
| 3526 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg()); | |
| 3527 #else | |
| 3528 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg()); | |
| 0 | 3529 __ psrlq(src->as_xmm_double_reg(), 32); |
| 304 | 3530 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg()); |
| 3531 #endif // _LP64 | |
| 0 | 3532 } else if (dest->is_double_stack()) { |
| 3533 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg()); | |
| 3534 } else if (dest->is_address()) { | |
| 3535 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg()); | |
| 3536 } else { | |
| 3537 ShouldNotReachHere(); | |
| 3538 } | |
| 3539 | |
| 3540 } else if (dest->is_double_xmm()) { | |
| 3541 if (src->is_double_stack()) { | |
| 3542 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix())); | |
| 3543 } else if (src->is_address()) { | |
| 3544 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr())); | |
| 3545 } else { | |
| 3546 ShouldNotReachHere(); | |
| 3547 } | |
| 3548 | |
| 3549 } else if (src->is_double_fpu()) { | |
| 3550 assert(src->fpu_regnrLo() == 0, "must be TOS"); | |
| 3551 if (dest->is_double_stack()) { | |
| 3552 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix())); | |
| 3553 } else if (dest->is_address()) { | |
| 3554 __ fistp_d(as_Address(dest->as_address_ptr())); | |
| 3555 } else { | |
| 3556 ShouldNotReachHere(); | |
| 3557 } | |
| 3558 | |
| 3559 } else if (dest->is_double_fpu()) { | |
| 3560 assert(dest->fpu_regnrLo() == 0, "must be TOS"); | |
| 3561 if (src->is_double_stack()) { | |
| 3562 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix())); | |
| 3563 } else if (src->is_address()) { | |
| 3564 __ fild_d(as_Address(src->as_address_ptr())); | |
| 3565 } else { | |
| 3566 ShouldNotReachHere(); | |
| 3567 } | |
| 3568 } else { | |
| 3569 ShouldNotReachHere(); | |
| 3570 } | |
| 3571 } | |
| 3572 | |
| 3573 | |
| 3574 void LIR_Assembler::membar() { | |
| 304 | 3575 // QQQ sparc TSO uses this, |
| 3576 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad)); | |
| 0 | 3577 } |
| 3578 | |
| 3579 void LIR_Assembler::membar_acquire() { | |
| 3580 // No x86 machines currently require load fences | |
| 3581 // __ load_fence(); | |
| 3582 } | |
| 3583 | |
| 3584 void LIR_Assembler::membar_release() { | |
| 3585 // No x86 machines currently require store fences | |
| 3586 // __ store_fence(); | |
| 3587 } | |
| 3588 | |
| 3589 void LIR_Assembler::get_thread(LIR_Opr result_reg) { | |
| 3590 assert(result_reg->is_register(), "check"); | |
| 304 | 3591 #ifdef _LP64 |
| 3592 // __ get_thread(result_reg->as_register_lo()); | |
| 3593 __ mov(result_reg->as_register(), r15_thread); | |
| 3594 #else | |
| 0 | 3595 __ get_thread(result_reg->as_register()); |
| 304 | 3596 #endif // _LP64 |
| 0 | 3597 } |
| 3598 | |
| 3599 | |
| 3600 void LIR_Assembler::peephole(LIR_List*) { | |
| 3601 // do nothing for now | |
| 3602 } | |
| 3603 | |
| 3604 | |
| 3605 #undef __ |