Mercurial > hg > graal-compiler
annotate src/cpu/x86/vm/vm_version_x86.hpp @ 20374:999824269b71
8055069: TSX and RTM should be deprecated more strongly until hardware is corrected
Summary: Require to specify UnlockExperimentalVMOptions flag together with UseRTMLocking flag on un-patched systems where CPUID allows it but is unsupported otherwise.
Reviewed-by: iveresov, fzhinkin
author | kvn |
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date | Fri, 22 Aug 2014 12:03:49 -0700 |
parents | 0118c8c7b80f |
children | 166d744df0de |
rev | line source |
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585 | 1 /* |
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2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. |
585 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
585 | 22 * |
23 */ | |
24 | |
1972 | 25 #ifndef CPU_X86_VM_VM_VERSION_X86_HPP |
26 #define CPU_X86_VM_VM_VERSION_X86_HPP | |
27 | |
28 #include "runtime/globals_extension.hpp" | |
29 #include "runtime/vm_version.hpp" | |
30 | |
585 | 31 class VM_Version : public Abstract_VM_Version { |
32 public: | |
33 // cpuid result register layouts. These are all unions of a uint32_t | |
34 // (in case anyone wants access to the register as a whole) and a bitfield. | |
35 | |
36 union StdCpuid1Eax { | |
37 uint32_t value; | |
38 struct { | |
39 uint32_t stepping : 4, | |
40 model : 4, | |
41 family : 4, | |
42 proc_type : 2, | |
43 : 2, | |
44 ext_model : 4, | |
45 ext_family : 8, | |
46 : 4; | |
47 } bits; | |
48 }; | |
49 | |
50 union StdCpuid1Ebx { // example, unused | |
51 uint32_t value; | |
52 struct { | |
53 uint32_t brand_id : 8, | |
54 clflush_size : 8, | |
55 threads_per_cpu : 8, | |
56 apic_id : 8; | |
57 } bits; | |
58 }; | |
59 | |
60 union StdCpuid1Ecx { | |
61 uint32_t value; | |
62 struct { | |
63 uint32_t sse3 : 1, | |
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64 clmul : 1, |
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65 : 1, |
585 | 66 monitor : 1, |
67 : 1, | |
68 vmx : 1, | |
69 : 1, | |
70 est : 1, | |
71 : 1, | |
72 ssse3 : 1, | |
73 cid : 1, | |
74 : 2, | |
75 cmpxchg16: 1, | |
76 : 4, | |
77 dca : 1, | |
78 sse4_1 : 1, | |
79 sse4_2 : 1, | |
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80 : 2, |
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81 popcnt : 1, |
6894 | 82 : 1, |
83 aes : 1, | |
84 : 1, | |
4759 | 85 osxsave : 1, |
86 avx : 1, | |
87 : 3; | |
585 | 88 } bits; |
89 }; | |
90 | |
91 union StdCpuid1Edx { | |
92 uint32_t value; | |
93 struct { | |
94 uint32_t : 4, | |
95 tsc : 1, | |
96 : 3, | |
97 cmpxchg8 : 1, | |
98 : 6, | |
99 cmov : 1, | |
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100 : 3, |
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101 clflush : 1, |
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102 : 3, |
585 | 103 mmx : 1, |
104 fxsr : 1, | |
105 sse : 1, | |
106 sse2 : 1, | |
107 : 1, | |
108 ht : 1, | |
109 : 3; | |
110 } bits; | |
111 }; | |
112 | |
113 union DcpCpuid4Eax { | |
114 uint32_t value; | |
115 struct { | |
116 uint32_t cache_type : 5, | |
117 : 21, | |
118 cores_per_cpu : 6; | |
119 } bits; | |
120 }; | |
121 | |
122 union DcpCpuid4Ebx { | |
123 uint32_t value; | |
124 struct { | |
125 uint32_t L1_line_size : 12, | |
126 partitions : 10, | |
127 associativity : 10; | |
128 } bits; | |
129 }; | |
130 | |
1622 | 131 union TplCpuidBEbx { |
132 uint32_t value; | |
133 struct { | |
134 uint32_t logical_cpus : 16, | |
135 : 16; | |
136 } bits; | |
137 }; | |
138 | |
585 | 139 union ExtCpuid1Ecx { |
140 uint32_t value; | |
141 struct { | |
142 uint32_t LahfSahf : 1, | |
143 CmpLegacy : 1, | |
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144 : 3, |
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145 lzcnt_intel : 1, |
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146 lzcnt : 1, |
585 | 147 sse4a : 1, |
148 misalignsse : 1, | |
149 prefetchw : 1, | |
150 : 22; | |
151 } bits; | |
152 }; | |
153 | |
154 union ExtCpuid1Edx { | |
155 uint32_t value; | |
156 struct { | |
157 uint32_t : 22, | |
158 mmx_amd : 1, | |
159 mmx : 1, | |
160 fxsr : 1, | |
161 : 4, | |
162 long_mode : 1, | |
163 tdnow2 : 1, | |
164 tdnow : 1; | |
165 } bits; | |
166 }; | |
167 | |
168 union ExtCpuid5Ex { | |
169 uint32_t value; | |
170 struct { | |
171 uint32_t L1_line_size : 8, | |
172 L1_tag_lines : 8, | |
173 L1_assoc : 8, | |
174 L1_size : 8; | |
175 } bits; | |
176 }; | |
177 | |
4771 | 178 union ExtCpuid7Edx { |
179 uint32_t value; | |
180 struct { | |
181 uint32_t : 8, | |
182 tsc_invariance : 1, | |
183 : 23; | |
184 } bits; | |
185 }; | |
186 | |
585 | 187 union ExtCpuid8Ecx { |
188 uint32_t value; | |
189 struct { | |
190 uint32_t cores_per_cpu : 8, | |
191 : 24; | |
192 } bits; | |
193 }; | |
194 | |
4759 | 195 union SefCpuid7Eax { |
196 uint32_t value; | |
197 }; | |
198 | |
199 union SefCpuid7Ebx { | |
200 uint32_t value; | |
201 struct { | |
202 uint32_t fsgsbase : 1, | |
203 : 2, | |
204 bmi1 : 1, | |
205 : 1, | |
206 avx2 : 1, | |
207 : 2, | |
208 bmi2 : 1, | |
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209 erms : 1, |
17780 | 210 : 1, |
211 rtm : 1, | |
212 : 20; | |
4759 | 213 } bits; |
214 }; | |
215 | |
216 union XemXcr0Eax { | |
217 uint32_t value; | |
218 struct { | |
219 uint32_t x87 : 1, | |
220 sse : 1, | |
221 ymm : 1, | |
222 : 29; | |
223 } bits; | |
224 }; | |
225 | |
585 | 226 protected: |
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227 static int _cpu; |
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228 static int _model; |
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229 static int _stepping; |
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230 static int _cpuFeatures; // features returned by the "cpuid" instruction |
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231 // 0 if this instruction is not available |
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232 static const char* _features_str; |
585 | 233 |
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234 static address _cpuinfo_segv_addr; // address of instruction which causes SEGV |
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235 static address _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV |
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236 |
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237 enum { |
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238 CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX) |
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239 CPU_CMOV = (1 << 1), |
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240 CPU_FXSR = (1 << 2), |
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241 CPU_HT = (1 << 3), |
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242 CPU_MMX = (1 << 4), |
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243 CPU_3DNOW_PREFETCH = (1 << 5), // Processor supports 3dnow prefetch and prefetchw instructions |
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244 // may not necessarily support other 3dnow instructions |
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245 CPU_SSE = (1 << 6), |
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246 CPU_SSE2 = (1 << 7), |
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247 CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX) |
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248 CPU_SSSE3 = (1 << 9), |
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249 CPU_SSE4A = (1 << 10), |
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250 CPU_SSE4_1 = (1 << 11), |
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251 CPU_SSE4_2 = (1 << 12), |
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252 CPU_POPCNT = (1 << 13), |
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253 CPU_LZCNT = (1 << 14), |
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254 CPU_TSC = (1 << 15), |
4771 | 255 CPU_TSCINV = (1 << 16), |
256 CPU_AVX = (1 << 17), | |
6894 | 257 CPU_AVX2 = (1 << 18), |
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258 CPU_AES = (1 << 19), |
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259 CPU_ERMS = (1 << 20), // enhanced 'rep movsb/stosb' instructions |
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260 CPU_CLMUL = (1 << 21), // carryless multiply for CRC |
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261 CPU_BMI1 = (1 << 22), |
17780 | 262 CPU_BMI2 = (1 << 23), |
263 CPU_RTM = (1 << 24) // Restricted Transactional Memory instructions | |
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264 } cpuFeatureFlags; |
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265 |
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266 enum { |
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267 // AMD |
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268 CPU_FAMILY_AMD_11H = 0x11, |
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269 // Intel |
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270 CPU_FAMILY_INTEL_CORE = 6, |
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271 CPU_MODEL_NEHALEM = 0x1e, |
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272 CPU_MODEL_NEHALEM_EP = 0x1a, |
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273 CPU_MODEL_NEHALEM_EX = 0x2e, |
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274 CPU_MODEL_WESTMERE = 0x25, |
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275 CPU_MODEL_WESTMERE_EP = 0x2c, |
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276 CPU_MODEL_WESTMERE_EX = 0x2f, |
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277 CPU_MODEL_SANDYBRIDGE = 0x2a, |
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278 CPU_MODEL_SANDYBRIDGE_EP = 0x2d, |
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279 CPU_MODEL_IVYBRIDGE_EP = 0x3a, |
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280 CPU_MODEL_HASWELL_E3 = 0x3c, |
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281 CPU_MODEL_HASWELL_E7 = 0x3f, |
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282 CPU_MODEL_BROADWELL = 0x3d |
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283 } cpuExtendedFamily; |
585 | 284 |
285 // cpuid information block. All info derived from executing cpuid with | |
286 // various function numbers is stored here. Intel and AMD info is | |
287 // merged in this block: accessor methods disentangle it. | |
288 // | |
289 // The info block is laid out in subblocks of 4 dwords corresponding to | |
290 // eax, ebx, ecx and edx, whether or not they contain anything useful. | |
291 struct CpuidInfo { | |
292 // cpuid function 0 | |
293 uint32_t std_max_function; | |
294 uint32_t std_vendor_name_0; | |
295 uint32_t std_vendor_name_1; | |
296 uint32_t std_vendor_name_2; | |
297 | |
298 // cpuid function 1 | |
299 StdCpuid1Eax std_cpuid1_eax; | |
300 StdCpuid1Ebx std_cpuid1_ebx; | |
301 StdCpuid1Ecx std_cpuid1_ecx; | |
302 StdCpuid1Edx std_cpuid1_edx; | |
303 | |
304 // cpuid function 4 (deterministic cache parameters) | |
305 DcpCpuid4Eax dcp_cpuid4_eax; | |
306 DcpCpuid4Ebx dcp_cpuid4_ebx; | |
307 uint32_t dcp_cpuid4_ecx; // unused currently | |
308 uint32_t dcp_cpuid4_edx; // unused currently | |
309 | |
4759 | 310 // cpuid function 7 (structured extended features) |
311 SefCpuid7Eax sef_cpuid7_eax; | |
312 SefCpuid7Ebx sef_cpuid7_ebx; | |
313 uint32_t sef_cpuid7_ecx; // unused currently | |
314 uint32_t sef_cpuid7_edx; // unused currently | |
315 | |
1622 | 316 // cpuid function 0xB (processor topology) |
317 // ecx = 0 | |
318 uint32_t tpl_cpuidB0_eax; | |
319 TplCpuidBEbx tpl_cpuidB0_ebx; | |
320 uint32_t tpl_cpuidB0_ecx; // unused currently | |
321 uint32_t tpl_cpuidB0_edx; // unused currently | |
322 | |
323 // ecx = 1 | |
324 uint32_t tpl_cpuidB1_eax; | |
325 TplCpuidBEbx tpl_cpuidB1_ebx; | |
326 uint32_t tpl_cpuidB1_ecx; // unused currently | |
327 uint32_t tpl_cpuidB1_edx; // unused currently | |
328 | |
329 // ecx = 2 | |
330 uint32_t tpl_cpuidB2_eax; | |
331 TplCpuidBEbx tpl_cpuidB2_ebx; | |
332 uint32_t tpl_cpuidB2_ecx; // unused currently | |
333 uint32_t tpl_cpuidB2_edx; // unused currently | |
334 | |
585 | 335 // cpuid function 0x80000000 // example, unused |
336 uint32_t ext_max_function; | |
337 uint32_t ext_vendor_name_0; | |
338 uint32_t ext_vendor_name_1; | |
339 uint32_t ext_vendor_name_2; | |
340 | |
341 // cpuid function 0x80000001 | |
342 uint32_t ext_cpuid1_eax; // reserved | |
343 uint32_t ext_cpuid1_ebx; // reserved | |
344 ExtCpuid1Ecx ext_cpuid1_ecx; | |
345 ExtCpuid1Edx ext_cpuid1_edx; | |
346 | |
347 // cpuid functions 0x80000002 thru 0x80000004: example, unused | |
348 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3; | |
349 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7; | |
350 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11; | |
351 | |
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352 // cpuid function 0x80000005 // AMD L1, Intel reserved |
585 | 353 uint32_t ext_cpuid5_eax; // unused currently |
354 uint32_t ext_cpuid5_ebx; // reserved | |
355 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD) | |
356 ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD) | |
357 | |
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358 // cpuid function 0x80000007 |
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359 uint32_t ext_cpuid7_eax; // reserved |
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360 uint32_t ext_cpuid7_ebx; // reserved |
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361 uint32_t ext_cpuid7_ecx; // reserved |
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362 ExtCpuid7Edx ext_cpuid7_edx; // tscinv |
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363 |
585 | 364 // cpuid function 0x80000008 |
365 uint32_t ext_cpuid8_eax; // unused currently | |
366 uint32_t ext_cpuid8_ebx; // reserved | |
367 ExtCpuid8Ecx ext_cpuid8_ecx; | |
368 uint32_t ext_cpuid8_edx; // reserved | |
4759 | 369 |
370 // extended control register XCR0 (the XFEATURE_ENABLED_MASK register) | |
371 XemXcr0Eax xem_xcr0_eax; | |
372 uint32_t xem_xcr0_edx; // reserved | |
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373 |
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374 // Space to save ymm registers after signal handle |
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375 int ymm_save[8*4]; // Save ymm0, ymm7, ymm8, ymm15 |
585 | 376 }; |
377 | |
378 // The actual cpuid info block | |
379 static CpuidInfo _cpuid_info; | |
380 | |
381 // Extractors and predicates | |
382 static uint32_t extended_cpu_family() { | |
383 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family; | |
384 result += _cpuid_info.std_cpuid1_eax.bits.ext_family; | |
385 return result; | |
386 } | |
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387 |
585 | 388 static uint32_t extended_cpu_model() { |
389 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model; | |
390 result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4; | |
391 return result; | |
392 } | |
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393 |
585 | 394 static uint32_t cpu_stepping() { |
395 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping; | |
396 return result; | |
397 } | |
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398 |
585 | 399 static uint logical_processor_count() { |
400 uint result = threads_per_core(); | |
401 return result; | |
402 } | |
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403 |
585 | 404 static uint32_t feature_flags() { |
405 uint32_t result = 0; | |
406 if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0) | |
407 result |= CPU_CX8; | |
408 if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0) | |
409 result |= CPU_CMOV; | |
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410 if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() && |
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411 _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0)) |
585 | 412 result |= CPU_FXSR; |
413 // HT flag is set for multi-core processors also. | |
414 if (threads_per_core() > 1) | |
415 result |= CPU_HT; | |
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416 if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd() && |
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417 _cpuid_info.ext_cpuid1_edx.bits.mmx != 0)) |
585 | 418 result |= CPU_MMX; |
419 if (_cpuid_info.std_cpuid1_edx.bits.sse != 0) | |
420 result |= CPU_SSE; | |
421 if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0) | |
422 result |= CPU_SSE2; | |
423 if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0) | |
424 result |= CPU_SSE3; | |
425 if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0) | |
426 result |= CPU_SSSE3; | |
427 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0) | |
428 result |= CPU_SSE4_1; | |
429 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0) | |
430 result |= CPU_SSE4_2; | |
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431 if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0) |
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432 result |= CPU_POPCNT; |
4759 | 433 if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 && |
434 _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 && | |
435 _cpuid_info.xem_xcr0_eax.bits.sse != 0 && | |
436 _cpuid_info.xem_xcr0_eax.bits.ymm != 0) { | |
437 result |= CPU_AVX; | |
438 if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0) | |
439 result |= CPU_AVX2; | |
440 } | |
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441 if(_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0) |
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442 result |= CPU_BMI1; |
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443 if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0) |
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444 result |= CPU_TSC; |
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445 if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0) |
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446 result |= CPU_TSCINV; |
6894 | 447 if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0) |
448 result |= CPU_AES; | |
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449 if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0) |
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450 result |= CPU_ERMS; |
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451 if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0) |
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452 result |= CPU_CLMUL; |
17780 | 453 if (_cpuid_info.sef_cpuid7_ebx.bits.rtm != 0) |
454 result |= CPU_RTM; | |
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455 |
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456 // AMD features. |
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457 if (is_amd()) { |
2479 | 458 if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) || |
459 (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0)) | |
460 result |= CPU_3DNOW_PREFETCH; | |
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461 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0) |
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462 result |= CPU_LZCNT; |
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463 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0) |
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464 result |= CPU_SSE4A; |
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465 } |
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466 // Intel features. |
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467 if(is_intel()) { |
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468 if(_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0) |
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469 result |= CPU_BMI2; |
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470 if(_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0) |
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471 result |= CPU_LZCNT; |
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472 } |
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473 |
585 | 474 return result; |
475 } | |
476 | |
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477 static bool os_supports_avx_vectors() { |
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478 if (!supports_avx()) { |
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479 return false; |
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480 } |
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481 // Verify that OS save/restore all bits of AVX registers |
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482 // during signal processing. |
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483 int nreg = 2 LP64_ONLY(+2); |
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484 for (int i = 0; i < 8 * nreg; i++) { // 32 bytes per ymm register |
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485 if (_cpuid_info.ymm_save[i] != ymm_test_value()) { |
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486 return false; |
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487 } |
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488 } |
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489 return true; |
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490 } |
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491 |
585 | 492 static void get_processor_features(); |
493 | |
494 public: | |
495 // Offsets for cpuid asm stub | |
496 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); } | |
497 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); } | |
498 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); } | |
4759 | 499 static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); } |
585 | 500 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); } |
501 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); } | |
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502 static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); } |
585 | 503 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); } |
1622 | 504 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); } |
505 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); } | |
506 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); } | |
4759 | 507 static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); } |
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508 static ByteSize ymm_save_offset() { return byte_offset_of(CpuidInfo, ymm_save); } |
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509 |
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510 // The value used to check ymm register after signal handle |
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511 static int ymm_test_value() { return 0xCAFEBABE; } |
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512 |
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513 static void get_cpu_info_wrapper(); |
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514 static void set_cpuinfo_segv_addr(address pc) { _cpuinfo_segv_addr = pc; } |
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515 static bool is_cpuinfo_segv_addr(address pc) { return _cpuinfo_segv_addr == pc; } |
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516 static void set_cpuinfo_cont_addr(address pc) { _cpuinfo_cont_addr = pc; } |
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517 static address cpuinfo_cont_addr() { return _cpuinfo_cont_addr; } |
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518 |
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519 static void clean_cpuFeatures() { _cpuFeatures = 0; } |
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520 static void set_avx_cpuFeatures() { _cpuFeatures = (CPU_SSE | CPU_SSE2 | CPU_AVX); } |
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521 |
585 | 522 |
523 // Initialization | |
524 static void initialize(); | |
525 | |
17780 | 526 // Override Abstract_VM_Version implementation |
527 static bool use_biased_locking(); | |
528 | |
585 | 529 // Asserts |
530 static void assert_is_initialized() { | |
531 assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized"); | |
532 } | |
533 | |
534 // | |
535 // Processor family: | |
536 // 3 - 386 | |
537 // 4 - 486 | |
538 // 5 - Pentium | |
539 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon, | |
540 // Pentium M, Core Solo, Core Duo, Core2 Duo | |
541 // family 6 model: 9, 13, 14, 15 | |
542 // 0x0f - Pentium 4, Opteron | |
543 // | |
544 // Note: The cpu family should be used to select between | |
545 // instruction sequences which are valid on all Intel | |
546 // processors. Use the feature test functions below to | |
547 // determine whether a particular instruction is supported. | |
548 // | |
549 static int cpu_family() { return _cpu;} | |
550 static bool is_P6() { return cpu_family() >= 6; } | |
551 static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA' | |
552 static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG' | |
553 | |
1647 | 554 static bool supports_processor_topology() { |
555 return (_cpuid_info.std_max_function >= 0xB) && | |
556 // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level. | |
557 // Some cpus have max cpuid >= 0xB but do not support processor topology. | |
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558 (((_cpuid_info.tpl_cpuidB0_eax & 0x1f) | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0); |
1647 | 559 } |
560 | |
585 | 561 static uint cores_per_cpu() { |
562 uint result = 1; | |
563 if (is_intel()) { | |
1647 | 564 if (supports_processor_topology()) { |
1622 | 565 result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus / |
566 _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; | |
567 } else { | |
568 result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1); | |
569 } | |
585 | 570 } else if (is_amd()) { |
571 result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1); | |
572 } | |
573 return result; | |
574 } | |
575 | |
576 static uint threads_per_core() { | |
577 uint result = 1; | |
1647 | 578 if (is_intel() && supports_processor_topology()) { |
1622 | 579 result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; |
580 } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) { | |
585 | 581 result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu / |
582 cores_per_cpu(); | |
583 } | |
584 return result; | |
585 } | |
586 | |
3854 | 587 static intx prefetch_data_size() { |
585 | 588 intx result = 0; |
589 if (is_intel()) { | |
590 result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1); | |
591 } else if (is_amd()) { | |
592 result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size; | |
593 } | |
594 if (result < 32) // not defined ? | |
595 result = 32; // 32 bytes by default on x86 and other x64 | |
596 return result; | |
597 } | |
598 | |
599 // | |
600 // Feature identification | |
601 // | |
602 static bool supports_cpuid() { return _cpuFeatures != 0; } | |
603 static bool supports_cmpxchg8() { return (_cpuFeatures & CPU_CX8) != 0; } | |
604 static bool supports_cmov() { return (_cpuFeatures & CPU_CMOV) != 0; } | |
605 static bool supports_fxsr() { return (_cpuFeatures & CPU_FXSR) != 0; } | |
606 static bool supports_ht() { return (_cpuFeatures & CPU_HT) != 0; } | |
607 static bool supports_mmx() { return (_cpuFeatures & CPU_MMX) != 0; } | |
608 static bool supports_sse() { return (_cpuFeatures & CPU_SSE) != 0; } | |
609 static bool supports_sse2() { return (_cpuFeatures & CPU_SSE2) != 0; } | |
610 static bool supports_sse3() { return (_cpuFeatures & CPU_SSE3) != 0; } | |
611 static bool supports_ssse3() { return (_cpuFeatures & CPU_SSSE3)!= 0; } | |
612 static bool supports_sse4_1() { return (_cpuFeatures & CPU_SSE4_1) != 0; } | |
613 static bool supports_sse4_2() { return (_cpuFeatures & CPU_SSE4_2) != 0; } | |
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614 static bool supports_popcnt() { return (_cpuFeatures & CPU_POPCNT) != 0; } |
4759 | 615 static bool supports_avx() { return (_cpuFeatures & CPU_AVX) != 0; } |
616 static bool supports_avx2() { return (_cpuFeatures & CPU_AVX2) != 0; } | |
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617 static bool supports_tsc() { return (_cpuFeatures & CPU_TSC) != 0; } |
6894 | 618 static bool supports_aes() { return (_cpuFeatures & CPU_AES) != 0; } |
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619 static bool supports_erms() { return (_cpuFeatures & CPU_ERMS) != 0; } |
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620 static bool supports_clmul() { return (_cpuFeatures & CPU_CLMUL) != 0; } |
17780 | 621 static bool supports_rtm() { return (_cpuFeatures & CPU_RTM) != 0; } |
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622 static bool supports_bmi1() { return (_cpuFeatures & CPU_BMI1) != 0; } |
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623 static bool supports_bmi2() { return (_cpuFeatures & CPU_BMI2) != 0; } |
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624 // Intel features |
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625 static bool is_intel_family_core() { return is_intel() && |
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626 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; } |
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627 |
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628 static bool is_intel_tsc_synched_at_init() { |
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629 if (is_intel_family_core()) { |
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630 uint32_t ext_model = extended_cpu_model(); |
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631 if (ext_model == CPU_MODEL_NEHALEM_EP || |
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632 ext_model == CPU_MODEL_WESTMERE_EP || |
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633 ext_model == CPU_MODEL_SANDYBRIDGE_EP || |
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634 ext_model == CPU_MODEL_IVYBRIDGE_EP) { |
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635 // <= 2-socket invariant tsc support. EX versions are usually used |
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636 // in > 2-socket systems and likely don't synchronize tscs at |
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637 // initialization. |
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638 // Code that uses tsc values must be prepared for them to arbitrarily |
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639 // jump forward or backward. |
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640 return true; |
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641 } |
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642 } |
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643 return false; |
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644 } |
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645 |
585 | 646 // AMD features |
2479 | 647 static bool supports_3dnow_prefetch() { return (_cpuFeatures & CPU_3DNOW_PREFETCH) != 0; } |
585 | 648 static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; } |
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649 static bool supports_lzcnt() { return (_cpuFeatures & CPU_LZCNT) != 0; } |
585 | 650 static bool supports_sse4a() { return (_cpuFeatures & CPU_SSE4A) != 0; } |
651 | |
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652 static bool is_amd_Barcelona() { return is_amd() && |
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653 extended_cpu_family() == CPU_FAMILY_AMD_11H; } |
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654 |
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655 // Intel and AMD newer cores support fast timestamps well |
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656 static bool supports_tscinv_bit() { |
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657 return (_cpuFeatures & CPU_TSCINV) != 0; |
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658 } |
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659 static bool supports_tscinv() { |
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660 return supports_tscinv_bit() && |
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661 ( (is_amd() && !is_amd_Barcelona()) || |
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662 is_intel_tsc_synched_at_init() ); |
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663 } |
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664 |
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665 // Intel Core and newer cpus have fast IDIV instruction (excluding Atom). |
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666 static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 && |
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667 supports_sse3() && _model != 0x1C; } |
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668 |
585 | 669 static bool supports_compare_and_exchange() { return true; } |
670 | |
671 static const char* cpu_features() { return _features_str; } | |
672 | |
673 static intx allocate_prefetch_distance() { | |
674 // This method should be called before allocate_prefetch_style(). | |
675 // | |
676 // Hardware prefetching (distance/size in bytes): | |
677 // Pentium 3 - 64 / 32 | |
678 // Pentium 4 - 256 / 128 | |
679 // Athlon - 64 / 32 ???? | |
680 // Opteron - 128 / 64 only when 2 sequential cache lines accessed | |
681 // Core - 128 / 64 | |
682 // | |
683 // Software prefetching (distance in bytes / instruction with best score): | |
684 // Pentium 3 - 128 / prefetchnta | |
685 // Pentium 4 - 512 / prefetchnta | |
686 // Athlon - 128 / prefetchnta | |
687 // Opteron - 256 / prefetchnta | |
688 // Core - 256 / prefetchnta | |
689 // It will be used only when AllocatePrefetchStyle > 0 | |
690 | |
691 intx count = AllocatePrefetchDistance; | |
692 if (count < 0) { // default ? | |
693 if (is_amd()) { // AMD | |
694 if (supports_sse2()) | |
695 count = 256; // Opteron | |
696 else | |
697 count = 128; // Athlon | |
698 } else { // Intel | |
699 if (supports_sse2()) | |
700 if (cpu_family() == 6) { | |
701 count = 256; // Pentium M, Core, Core2 | |
702 } else { | |
703 count = 512; // Pentium 4 | |
704 } | |
705 else | |
706 count = 128; // Pentium 3 (and all other old CPUs) | |
707 } | |
708 } | |
709 return count; | |
710 } | |
711 static intx allocate_prefetch_style() { | |
712 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive"); | |
713 // Return 0 if AllocatePrefetchDistance was not defined. | |
714 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0; | |
715 } | |
716 | |
717 // Prefetch interval for gc copy/scan == 9 dcache lines. Derived from | |
718 // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap. | |
719 // Tested intervals from 128 to 2048 in increments of 64 == one cache line. | |
720 // 256 bytes (4 dcache lines) was the nearest runner-up to 576. | |
721 | |
722 // gc copy/scan is disabled if prefetchw isn't supported, because | |
723 // Prefetch::write emits an inlined prefetchw on Linux. | |
724 // Do not use the 3dnow prefetchw instruction. It isn't supported on em64t. | |
725 // The used prefetcht0 instruction works for both amd64 and em64t. | |
726 static intx prefetch_copy_interval_in_bytes() { | |
727 intx interval = PrefetchCopyIntervalInBytes; | |
728 return interval >= 0 ? interval : 576; | |
729 } | |
730 static intx prefetch_scan_interval_in_bytes() { | |
731 intx interval = PrefetchScanIntervalInBytes; | |
732 return interval >= 0 ? interval : 576; | |
733 } | |
734 static intx prefetch_fields_ahead() { | |
735 intx count = PrefetchFieldsAhead; | |
736 return count >= 0 ? count : 1; | |
737 } | |
738 }; | |
1972 | 739 |
740 #endif // CPU_X86_VM_VM_VERSION_X86_HPP |