Mercurial > hg > graal-compiler
annotate src/share/vm/c1/c1_LIR.cpp @ 6781:b711844284e2
7200092: Make NMT a bit friendlier to work with
Reviewed-by: kvn, ysr, azeemj
author | nloodin |
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date | Fri, 21 Sep 2012 10:56:28 +0200 |
parents | 8a02ca5e5576 |
children | 7eca5de9e0b6 |
rev | line source |
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0 | 1 /* |
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2 * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #include "precompiled.hpp" |
26 #include "c1/c1_InstructionPrinter.hpp" | |
27 #include "c1/c1_LIR.hpp" | |
28 #include "c1/c1_LIRAssembler.hpp" | |
29 #include "c1/c1_ValueStack.hpp" | |
30 #include "ci/ciInstance.hpp" | |
31 #include "runtime/sharedRuntime.hpp" | |
0 | 32 |
33 Register LIR_OprDesc::as_register() const { | |
34 return FrameMap::cpu_rnr2reg(cpu_regnr()); | |
35 } | |
36 | |
37 Register LIR_OprDesc::as_register_lo() const { | |
38 return FrameMap::cpu_rnr2reg(cpu_regnrLo()); | |
39 } | |
40 | |
41 Register LIR_OprDesc::as_register_hi() const { | |
42 return FrameMap::cpu_rnr2reg(cpu_regnrHi()); | |
43 } | |
44 | |
304 | 45 #if defined(X86) |
0 | 46 |
47 XMMRegister LIR_OprDesc::as_xmm_float_reg() const { | |
48 return FrameMap::nr2xmmreg(xmm_regnr()); | |
49 } | |
50 | |
51 XMMRegister LIR_OprDesc::as_xmm_double_reg() const { | |
52 assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation"); | |
53 return FrameMap::nr2xmmreg(xmm_regnrLo()); | |
54 } | |
55 | |
304 | 56 #endif // X86 |
0 | 57 |
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58 #if defined(SPARC) || defined(PPC) |
0 | 59 |
60 FloatRegister LIR_OprDesc::as_float_reg() const { | |
61 return FrameMap::nr2floatreg(fpu_regnr()); | |
62 } | |
63 | |
64 FloatRegister LIR_OprDesc::as_double_reg() const { | |
65 return FrameMap::nr2floatreg(fpu_regnrHi()); | |
66 } | |
67 | |
68 #endif | |
69 | |
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70 #ifdef ARM |
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71 |
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72 FloatRegister LIR_OprDesc::as_float_reg() const { |
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73 return as_FloatRegister(fpu_regnr()); |
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74 } |
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75 |
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76 FloatRegister LIR_OprDesc::as_double_reg() const { |
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77 return as_FloatRegister(fpu_regnrLo()); |
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78 } |
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79 |
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80 #endif |
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81 |
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82 |
0 | 83 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal(); |
84 | |
85 LIR_Opr LIR_OprFact::value_type(ValueType* type) { | |
86 ValueTag tag = type->tag(); | |
87 switch (tag) { | |
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88 case metaDataTag : { |
0 | 89 ClassConstant* c = type->as_ClassConstant(); |
90 if (c != NULL && !c->value()->is_loaded()) { | |
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91 return LIR_OprFact::metadataConst(NULL); |
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92 } else if (c != NULL) { |
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93 return LIR_OprFact::metadataConst(c->value()->constant_encoding()); |
0 | 94 } else { |
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95 MethodConstant* m = type->as_MethodConstant(); |
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96 assert (m != NULL, "not a class or a method?"); |
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97 return LIR_OprFact::metadataConst(m->value()->constant_encoding()); |
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98 } |
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99 } |
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100 case objectTag : { |
0 | 101 return LIR_OprFact::oopConst(type->as_ObjectType()->encoding()); |
102 } | |
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103 case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value()); |
0 | 104 case intTag : return LIR_OprFact::intConst(type->as_IntConstant()->value()); |
105 case floatTag : return LIR_OprFact::floatConst(type->as_FloatConstant()->value()); | |
106 case longTag : return LIR_OprFact::longConst(type->as_LongConstant()->value()); | |
107 case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value()); | |
304 | 108 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1); |
0 | 109 } |
110 } | |
111 | |
112 | |
113 LIR_Opr LIR_OprFact::dummy_value_type(ValueType* type) { | |
114 switch (type->tag()) { | |
115 case objectTag: return LIR_OprFact::oopConst(NULL); | |
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116 case addressTag:return LIR_OprFact::addressConst(0); |
0 | 117 case intTag: return LIR_OprFact::intConst(0); |
118 case floatTag: return LIR_OprFact::floatConst(0.0); | |
119 case longTag: return LIR_OprFact::longConst(0); | |
120 case doubleTag: return LIR_OprFact::doubleConst(0.0); | |
304 | 121 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1); |
0 | 122 } |
123 return illegalOpr; | |
124 } | |
125 | |
126 | |
127 | |
128 //--------------------------------------------------- | |
129 | |
130 | |
131 LIR_Address::Scale LIR_Address::scale(BasicType type) { | |
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132 int elem_size = type2aelembytes(type); |
0 | 133 switch (elem_size) { |
134 case 1: return LIR_Address::times_1; | |
135 case 2: return LIR_Address::times_2; | |
136 case 4: return LIR_Address::times_4; | |
137 case 8: return LIR_Address::times_8; | |
138 } | |
139 ShouldNotReachHere(); | |
140 return LIR_Address::times_1; | |
141 } | |
142 | |
143 | |
144 #ifndef PRODUCT | |
145 void LIR_Address::verify() const { | |
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146 #if defined(SPARC) || defined(PPC) |
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147 assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used"); |
0 | 148 assert(disp() == 0 || index()->is_illegal(), "can't have both"); |
149 #endif | |
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150 #ifdef ARM |
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151 assert(disp() == 0 || index()->is_illegal(), "can't have both"); |
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152 // Note: offsets higher than 4096 must not be rejected here. They can |
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153 // be handled by the back-end or will be rejected if not. |
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154 #endif |
0 | 155 #ifdef _LP64 |
156 assert(base()->is_cpu_register(), "wrong base operand"); | |
157 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand"); | |
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158 assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA, |
0 | 159 "wrong type for addresses"); |
160 #else | |
161 assert(base()->is_single_cpu(), "wrong base operand"); | |
162 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand"); | |
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163 assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA, |
0 | 164 "wrong type for addresses"); |
165 #endif | |
166 } | |
167 #endif | |
168 | |
169 | |
170 //--------------------------------------------------- | |
171 | |
172 char LIR_OprDesc::type_char(BasicType t) { | |
173 switch (t) { | |
174 case T_ARRAY: | |
175 t = T_OBJECT; | |
176 case T_BOOLEAN: | |
177 case T_CHAR: | |
178 case T_FLOAT: | |
179 case T_DOUBLE: | |
180 case T_BYTE: | |
181 case T_SHORT: | |
182 case T_INT: | |
183 case T_LONG: | |
184 case T_OBJECT: | |
185 case T_ADDRESS: | |
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186 case T_METADATA: |
0 | 187 case T_VOID: |
188 return ::type2char(t); | |
189 | |
190 case T_ILLEGAL: | |
191 return '?'; | |
192 | |
193 default: | |
194 ShouldNotReachHere(); | |
304 | 195 return '?'; |
0 | 196 } |
197 } | |
198 | |
199 #ifndef PRODUCT | |
200 void LIR_OprDesc::validate_type() const { | |
201 | |
202 #ifdef ASSERT | |
203 if (!is_pointer() && !is_illegal()) { | |
204 switch (as_BasicType(type_field())) { | |
205 case T_LONG: | |
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206 assert((kind_field() == cpu_register || kind_field() == stack_value) && |
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207 size_field() == double_size, "must match"); |
0 | 208 break; |
209 case T_FLOAT: | |
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210 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI) |
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211 assert((kind_field() == fpu_register || kind_field() == stack_value |
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212 ARM_ONLY(|| kind_field() == cpu_register) |
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213 PPC_ONLY(|| kind_field() == cpu_register) ) && |
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214 size_field() == single_size, "must match"); |
0 | 215 break; |
216 case T_DOUBLE: | |
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217 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI) |
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218 assert((kind_field() == fpu_register || kind_field() == stack_value |
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219 ARM_ONLY(|| kind_field() == cpu_register) |
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220 PPC_ONLY(|| kind_field() == cpu_register) ) && |
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221 size_field() == double_size, "must match"); |
0 | 222 break; |
223 case T_BOOLEAN: | |
224 case T_CHAR: | |
225 case T_BYTE: | |
226 case T_SHORT: | |
227 case T_INT: | |
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228 case T_ADDRESS: |
0 | 229 case T_OBJECT: |
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230 case T_METADATA: |
0 | 231 case T_ARRAY: |
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232 assert((kind_field() == cpu_register || kind_field() == stack_value) && |
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233 size_field() == single_size, "must match"); |
0 | 234 break; |
235 | |
236 case T_ILLEGAL: | |
237 // XXX TKR also means unknown right now | |
238 // assert(is_illegal(), "must match"); | |
239 break; | |
240 | |
241 default: | |
242 ShouldNotReachHere(); | |
243 } | |
244 } | |
245 #endif | |
246 | |
247 } | |
248 #endif // PRODUCT | |
249 | |
250 | |
251 bool LIR_OprDesc::is_oop() const { | |
252 if (is_pointer()) { | |
253 return pointer()->is_oop_pointer(); | |
254 } else { | |
255 OprType t= type_field(); | |
256 assert(t != unknown_type, "not set"); | |
257 return t == object_type; | |
258 } | |
259 } | |
260 | |
261 | |
262 | |
263 void LIR_Op2::verify() const { | |
264 #ifdef ASSERT | |
265 switch (code()) { | |
266 case lir_cmove: | |
267 break; | |
268 | |
269 default: | |
270 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(), | |
271 "can't produce oops from arith"); | |
272 } | |
273 | |
274 if (TwoOperandLIRForm) { | |
275 switch (code()) { | |
276 case lir_add: | |
277 case lir_sub: | |
278 case lir_mul: | |
279 case lir_mul_strictfp: | |
280 case lir_div: | |
281 case lir_div_strictfp: | |
282 case lir_rem: | |
283 case lir_logic_and: | |
284 case lir_logic_or: | |
285 case lir_logic_xor: | |
286 case lir_shl: | |
287 case lir_shr: | |
288 assert(in_opr1() == result_opr(), "opr1 and result must match"); | |
289 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid"); | |
290 break; | |
291 | |
292 // special handling for lir_ushr because of write barriers | |
293 case lir_ushr: | |
294 assert(in_opr1() == result_opr() || in_opr2()->is_constant(), "opr1 and result must match or shift count is constant"); | |
295 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid"); | |
296 break; | |
297 | |
298 } | |
299 } | |
300 #endif | |
301 } | |
302 | |
303 | |
304 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block) | |
305 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) | |
306 , _cond(cond) | |
307 , _type(type) | |
308 , _label(block->label()) | |
309 , _block(block) | |
310 , _ublock(NULL) | |
311 , _stub(NULL) { | |
312 } | |
313 | |
314 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) : | |
315 LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) | |
316 , _cond(cond) | |
317 , _type(type) | |
318 , _label(stub->entry()) | |
319 , _block(NULL) | |
320 , _ublock(NULL) | |
321 , _stub(stub) { | |
322 } | |
323 | |
324 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock) | |
325 : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) | |
326 , _cond(cond) | |
327 , _type(type) | |
328 , _label(block->label()) | |
329 , _block(block) | |
330 , _ublock(ublock) | |
331 , _stub(NULL) | |
332 { | |
333 } | |
334 | |
335 void LIR_OpBranch::change_block(BlockBegin* b) { | |
336 assert(_block != NULL, "must have old block"); | |
337 assert(_block->label() == label(), "must be equal"); | |
338 | |
339 _block = b; | |
340 _label = b->label(); | |
341 } | |
342 | |
343 void LIR_OpBranch::change_ublock(BlockBegin* b) { | |
344 assert(_ublock != NULL, "must have old block"); | |
345 _ublock = b; | |
346 } | |
347 | |
348 void LIR_OpBranch::negate_cond() { | |
349 switch (_cond) { | |
350 case lir_cond_equal: _cond = lir_cond_notEqual; break; | |
351 case lir_cond_notEqual: _cond = lir_cond_equal; break; | |
352 case lir_cond_less: _cond = lir_cond_greaterEqual; break; | |
353 case lir_cond_lessEqual: _cond = lir_cond_greater; break; | |
354 case lir_cond_greaterEqual: _cond = lir_cond_less; break; | |
355 case lir_cond_greater: _cond = lir_cond_lessEqual; break; | |
356 default: ShouldNotReachHere(); | |
357 } | |
358 } | |
359 | |
360 | |
361 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass, | |
362 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, | |
363 bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, | |
1783 | 364 CodeStub* stub) |
365 | |
0 | 366 : LIR_Op(code, result, NULL) |
367 , _object(object) | |
368 , _array(LIR_OprFact::illegalOpr) | |
369 , _klass(klass) | |
370 , _tmp1(tmp1) | |
371 , _tmp2(tmp2) | |
372 , _tmp3(tmp3) | |
373 , _fast_check(fast_check) | |
374 , _stub(stub) | |
375 , _info_for_patch(info_for_patch) | |
376 , _info_for_exception(info_for_exception) | |
1783 | 377 , _profiled_method(NULL) |
378 , _profiled_bci(-1) | |
379 , _should_profile(false) | |
380 { | |
0 | 381 if (code == lir_checkcast) { |
382 assert(info_for_exception != NULL, "checkcast throws exceptions"); | |
383 } else if (code == lir_instanceof) { | |
384 assert(info_for_exception == NULL, "instanceof throws no exceptions"); | |
385 } else { | |
386 ShouldNotReachHere(); | |
387 } | |
388 } | |
389 | |
390 | |
391 | |
1783 | 392 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception) |
0 | 393 : LIR_Op(code, LIR_OprFact::illegalOpr, NULL) |
394 , _object(object) | |
395 , _array(array) | |
396 , _klass(NULL) | |
397 , _tmp1(tmp1) | |
398 , _tmp2(tmp2) | |
399 , _tmp3(tmp3) | |
400 , _fast_check(false) | |
401 , _stub(NULL) | |
402 , _info_for_patch(NULL) | |
403 , _info_for_exception(info_for_exception) | |
1783 | 404 , _profiled_method(NULL) |
405 , _profiled_bci(-1) | |
406 , _should_profile(false) | |
407 { | |
0 | 408 if (code == lir_store_check) { |
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409 _stub = new ArrayStoreExceptionStub(object, info_for_exception); |
0 | 410 assert(info_for_exception != NULL, "store_check throws exceptions"); |
411 } else { | |
412 ShouldNotReachHere(); | |
413 } | |
414 } | |
415 | |
416 | |
417 LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length, | |
418 LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info) | |
419 : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info) | |
420 , _tmp(tmp) | |
421 , _src(src) | |
422 , _src_pos(src_pos) | |
423 , _dst(dst) | |
424 , _dst_pos(dst_pos) | |
425 , _flags(flags) | |
426 , _expected_type(expected_type) | |
427 , _length(length) { | |
428 _stub = new ArrayCopyStub(this); | |
429 } | |
430 | |
431 | |
432 //-------------------verify-------------------------- | |
433 | |
434 void LIR_Op1::verify() const { | |
435 switch(code()) { | |
436 case lir_move: | |
437 assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be"); | |
438 break; | |
439 case lir_null_check: | |
440 assert(in_opr()->is_register(), "must be"); | |
441 break; | |
442 case lir_return: | |
443 assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be"); | |
444 break; | |
445 } | |
446 } | |
447 | |
448 void LIR_OpRTCall::verify() const { | |
449 assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function"); | |
450 } | |
451 | |
452 //-------------------visits-------------------------- | |
453 | |
454 // complete rework of LIR instruction visitor. | |
455 // The virtual calls for each instruction type is replaced by a big | |
456 // switch that adds the operands for each instruction | |
457 | |
458 void LIR_OpVisitState::visit(LIR_Op* op) { | |
459 // copy information from the LIR_Op | |
460 reset(); | |
461 set_op(op); | |
462 | |
463 switch (op->code()) { | |
464 | |
465 // LIR_Op0 | |
466 case lir_word_align: // result and info always invalid | |
467 case lir_backwardbranch_target: // result and info always invalid | |
468 case lir_build_frame: // result and info always invalid | |
469 case lir_fpop_raw: // result and info always invalid | |
470 case lir_24bit_FPU: // result and info always invalid | |
471 case lir_reset_FPU: // result and info always invalid | |
472 case lir_breakpoint: // result and info always invalid | |
473 case lir_membar: // result and info always invalid | |
474 case lir_membar_acquire: // result and info always invalid | |
475 case lir_membar_release: // result and info always invalid | |
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476 case lir_membar_loadload: // result and info always invalid |
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477 case lir_membar_storestore: // result and info always invalid |
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478 case lir_membar_loadstore: // result and info always invalid |
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479 case lir_membar_storeload: // result and info always invalid |
0 | 480 { |
481 assert(op->as_Op0() != NULL, "must be"); | |
482 assert(op->_info == NULL, "info not used by this instruction"); | |
483 assert(op->_result->is_illegal(), "not used"); | |
484 break; | |
485 } | |
486 | |
487 case lir_nop: // may have info, result always invalid | |
488 case lir_std_entry: // may have result, info always invalid | |
489 case lir_osr_entry: // may have result, info always invalid | |
490 case lir_get_thread: // may have result, info always invalid | |
491 { | |
492 assert(op->as_Op0() != NULL, "must be"); | |
493 if (op->_info != NULL) do_info(op->_info); | |
494 if (op->_result->is_valid()) do_output(op->_result); | |
495 break; | |
496 } | |
497 | |
498 | |
499 // LIR_OpLabel | |
500 case lir_label: // result and info always invalid | |
501 { | |
502 assert(op->as_OpLabel() != NULL, "must be"); | |
503 assert(op->_info == NULL, "info not used by this instruction"); | |
504 assert(op->_result->is_illegal(), "not used"); | |
505 break; | |
506 } | |
507 | |
508 | |
509 // LIR_Op1 | |
510 case lir_fxch: // input always valid, result and info always invalid | |
511 case lir_fld: // input always valid, result and info always invalid | |
512 case lir_ffree: // input always valid, result and info always invalid | |
513 case lir_push: // input always valid, result and info always invalid | |
514 case lir_pop: // input always valid, result and info always invalid | |
515 case lir_return: // input always valid, result and info always invalid | |
516 case lir_leal: // input and result always valid, info always invalid | |
517 case lir_neg: // input and result always valid, info always invalid | |
518 case lir_monaddr: // input and result always valid, info always invalid | |
519 case lir_null_check: // input and info always valid, result always invalid | |
520 case lir_move: // input and result always valid, may have info | |
1783 | 521 case lir_pack64: // input and result always valid |
522 case lir_unpack64: // input and result always valid | |
0 | 523 case lir_prefetchr: // input always valid, result and info always invalid |
524 case lir_prefetchw: // input always valid, result and info always invalid | |
525 { | |
526 assert(op->as_Op1() != NULL, "must be"); | |
527 LIR_Op1* op1 = (LIR_Op1*)op; | |
528 | |
529 if (op1->_info) do_info(op1->_info); | |
530 if (op1->_opr->is_valid()) do_input(op1->_opr); | |
531 if (op1->_result->is_valid()) do_output(op1->_result); | |
532 | |
533 break; | |
534 } | |
535 | |
536 case lir_safepoint: | |
537 { | |
538 assert(op->as_Op1() != NULL, "must be"); | |
539 LIR_Op1* op1 = (LIR_Op1*)op; | |
540 | |
541 assert(op1->_info != NULL, ""); do_info(op1->_info); | |
542 if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register | |
543 assert(op1->_result->is_illegal(), "safepoint does not produce value"); | |
544 | |
545 break; | |
546 } | |
547 | |
548 // LIR_OpConvert; | |
549 case lir_convert: // input and result always valid, info always invalid | |
550 { | |
551 assert(op->as_OpConvert() != NULL, "must be"); | |
552 LIR_OpConvert* opConvert = (LIR_OpConvert*)op; | |
553 | |
554 assert(opConvert->_info == NULL, "must be"); | |
555 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr); | |
556 if (opConvert->_result->is_valid()) do_output(opConvert->_result); | |
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557 #ifdef PPC |
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558 if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1); |
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559 if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2); |
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560 #endif |
0 | 561 do_stub(opConvert->_stub); |
562 | |
563 break; | |
564 } | |
565 | |
566 // LIR_OpBranch; | |
567 case lir_branch: // may have info, input and result register always invalid | |
568 case lir_cond_float_branch: // may have info, input and result register always invalid | |
569 { | |
570 assert(op->as_OpBranch() != NULL, "must be"); | |
571 LIR_OpBranch* opBranch = (LIR_OpBranch*)op; | |
572 | |
573 if (opBranch->_info != NULL) do_info(opBranch->_info); | |
574 assert(opBranch->_result->is_illegal(), "not used"); | |
575 if (opBranch->_stub != NULL) opBranch->stub()->visit(this); | |
576 | |
577 break; | |
578 } | |
579 | |
580 | |
581 // LIR_OpAllocObj | |
582 case lir_alloc_object: | |
583 { | |
584 assert(op->as_OpAllocObj() != NULL, "must be"); | |
585 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op; | |
586 | |
587 if (opAllocObj->_info) do_info(opAllocObj->_info); | |
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588 if (opAllocObj->_opr->is_valid()) { do_input(opAllocObj->_opr); |
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589 do_temp(opAllocObj->_opr); |
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590 } |
0 | 591 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1); |
592 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2); | |
593 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3); | |
594 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4); | |
595 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result); | |
596 do_stub(opAllocObj->_stub); | |
597 break; | |
598 } | |
599 | |
600 | |
601 // LIR_OpRoundFP; | |
602 case lir_roundfp: { | |
603 assert(op->as_OpRoundFP() != NULL, "must be"); | |
604 LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op; | |
605 | |
606 assert(op->_info == NULL, "info not used by this instruction"); | |
607 assert(opRoundFP->_tmp->is_illegal(), "not used"); | |
608 do_input(opRoundFP->_opr); | |
609 do_output(opRoundFP->_result); | |
610 | |
611 break; | |
612 } | |
613 | |
614 | |
615 // LIR_Op2 | |
616 case lir_cmp: | |
617 case lir_cmp_l2i: | |
618 case lir_ucmp_fd2i: | |
619 case lir_cmp_fd2i: | |
620 case lir_add: | |
621 case lir_sub: | |
622 case lir_mul: | |
623 case lir_div: | |
624 case lir_rem: | |
625 case lir_sqrt: | |
626 case lir_abs: | |
627 case lir_logic_and: | |
628 case lir_logic_or: | |
629 case lir_logic_xor: | |
630 case lir_shl: | |
631 case lir_shr: | |
632 case lir_ushr: | |
633 { | |
634 assert(op->as_Op2() != NULL, "must be"); | |
635 LIR_Op2* op2 = (LIR_Op2*)op; | |
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636 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() && |
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637 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); |
0 | 638 |
639 if (op2->_info) do_info(op2->_info); | |
640 if (op2->_opr1->is_valid()) do_input(op2->_opr1); | |
641 if (op2->_opr2->is_valid()) do_input(op2->_opr2); | |
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642 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1); |
0 | 643 if (op2->_result->is_valid()) do_output(op2->_result); |
644 | |
645 break; | |
646 } | |
647 | |
648 // special handling for cmove: right input operand must not be equal | |
649 // to the result operand, otherwise the backend fails | |
650 case lir_cmove: | |
651 { | |
652 assert(op->as_Op2() != NULL, "must be"); | |
653 LIR_Op2* op2 = (LIR_Op2*)op; | |
654 | |
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655 assert(op2->_info == NULL && op2->_tmp1->is_illegal() && op2->_tmp2->is_illegal() && |
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656 op2->_tmp3->is_illegal() && op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); |
0 | 657 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used"); |
658 | |
659 do_input(op2->_opr1); | |
660 do_input(op2->_opr2); | |
661 do_temp(op2->_opr2); | |
662 do_output(op2->_result); | |
663 | |
664 break; | |
665 } | |
666 | |
667 // vspecial handling for strict operations: register input operands | |
668 // as temp to guarantee that they do not overlap with other | |
669 // registers | |
670 case lir_mul_strictfp: | |
671 case lir_div_strictfp: | |
672 { | |
673 assert(op->as_Op2() != NULL, "must be"); | |
674 LIR_Op2* op2 = (LIR_Op2*)op; | |
675 | |
676 assert(op2->_info == NULL, "not used"); | |
677 assert(op2->_opr1->is_valid(), "used"); | |
678 assert(op2->_opr2->is_valid(), "used"); | |
679 assert(op2->_result->is_valid(), "used"); | |
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680 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() && |
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681 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); |
0 | 682 |
683 do_input(op2->_opr1); do_temp(op2->_opr1); | |
684 do_input(op2->_opr2); do_temp(op2->_opr2); | |
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685 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1); |
0 | 686 do_output(op2->_result); |
687 | |
688 break; | |
689 } | |
690 | |
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691 case lir_throw: { |
0 | 692 assert(op->as_Op2() != NULL, "must be"); |
693 LIR_Op2* op2 = (LIR_Op2*)op; | |
694 | |
695 if (op2->_info) do_info(op2->_info); | |
696 if (op2->_opr1->is_valid()) do_temp(op2->_opr1); | |
697 if (op2->_opr2->is_valid()) do_input(op2->_opr2); // exception object is input parameter | |
698 assert(op2->_result->is_illegal(), "no result"); | |
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699 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() && |
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700 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); |
0 | 701 |
702 break; | |
703 } | |
704 | |
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705 case lir_unwind: { |
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706 assert(op->as_Op1() != NULL, "must be"); |
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707 LIR_Op1* op1 = (LIR_Op1*)op; |
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708 |
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709 assert(op1->_info == NULL, "no info"); |
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710 assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr); |
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711 assert(op1->_result->is_illegal(), "no result"); |
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712 |
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713 break; |
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714 } |
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715 |
0 | 716 |
717 case lir_tan: | |
718 case lir_sin: | |
953
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719 case lir_cos: |
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720 case lir_log: |
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721 case lir_log10: |
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722 case lir_exp: { |
0 | 723 assert(op->as_Op2() != NULL, "must be"); |
724 LIR_Op2* op2 = (LIR_Op2*)op; | |
725 | |
953
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726 // On x86 tan/sin/cos need two temporary fpu stack slots and |
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727 // log/log10 need one so handle opr2 and tmp as temp inputs. |
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728 // Register input operand as temp to guarantee that it doesn't |
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729 // overlap with the input. |
0 | 730 assert(op2->_info == NULL, "not used"); |
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731 assert(op2->_tmp5->is_illegal(), "not used"); |
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732 assert(op2->_tmp2->is_valid() == (op->code() == lir_exp), "not used"); |
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733 assert(op2->_tmp3->is_valid() == (op->code() == lir_exp), "not used"); |
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734 assert(op2->_tmp4->is_valid() == (op->code() == lir_exp), "not used"); |
0 | 735 assert(op2->_opr1->is_valid(), "used"); |
736 do_input(op2->_opr1); do_temp(op2->_opr1); | |
737 | |
738 if (op2->_opr2->is_valid()) do_temp(op2->_opr2); | |
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739 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1); |
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740 if (op2->_tmp2->is_valid()) do_temp(op2->_tmp2); |
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741 if (op2->_tmp3->is_valid()) do_temp(op2->_tmp3); |
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742 if (op2->_tmp4->is_valid()) do_temp(op2->_tmp4); |
0 | 743 if (op2->_result->is_valid()) do_output(op2->_result); |
744 | |
745 break; | |
746 } | |
747 | |
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748 case lir_pow: { |
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749 assert(op->as_Op2() != NULL, "must be"); |
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750 LIR_Op2* op2 = (LIR_Op2*)op; |
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751 |
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752 // On x86 pow needs two temporary fpu stack slots: tmp1 and |
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753 // tmp2. Register input operands as temps to guarantee that it |
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754 // doesn't overlap with the temporary slots. |
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755 assert(op2->_info == NULL, "not used"); |
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756 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid(), "used"); |
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757 assert(op2->_tmp1->is_valid() && op2->_tmp2->is_valid() && op2->_tmp3->is_valid() |
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758 && op2->_tmp4->is_valid() && op2->_tmp5->is_valid(), "used"); |
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759 assert(op2->_result->is_valid(), "used"); |
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760 |
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761 do_input(op2->_opr1); do_temp(op2->_opr1); |
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762 do_input(op2->_opr2); do_temp(op2->_opr2); |
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763 do_temp(op2->_tmp1); |
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764 do_temp(op2->_tmp2); |
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765 do_temp(op2->_tmp3); |
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766 do_temp(op2->_tmp4); |
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767 do_temp(op2->_tmp5); |
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768 do_output(op2->_result); |
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769 |
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770 break; |
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771 } |
0 | 772 |
773 // LIR_Op3 | |
774 case lir_idiv: | |
775 case lir_irem: { | |
776 assert(op->as_Op3() != NULL, "must be"); | |
777 LIR_Op3* op3= (LIR_Op3*)op; | |
778 | |
779 if (op3->_info) do_info(op3->_info); | |
780 if (op3->_opr1->is_valid()) do_input(op3->_opr1); | |
781 | |
782 // second operand is input and temp, so ensure that second operand | |
783 // and third operand get not the same register | |
784 if (op3->_opr2->is_valid()) do_input(op3->_opr2); | |
785 if (op3->_opr2->is_valid()) do_temp(op3->_opr2); | |
786 if (op3->_opr3->is_valid()) do_temp(op3->_opr3); | |
787 | |
788 if (op3->_result->is_valid()) do_output(op3->_result); | |
789 | |
790 break; | |
791 } | |
792 | |
793 | |
794 // LIR_OpJavaCall | |
795 case lir_static_call: | |
796 case lir_optvirtual_call: | |
797 case lir_icvirtual_call: | |
1295 | 798 case lir_virtual_call: |
799 case lir_dynamic_call: { | |
800 LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall(); | |
801 assert(opJavaCall != NULL, "must be"); | |
0 | 802 |
803 if (opJavaCall->_receiver->is_valid()) do_input(opJavaCall->_receiver); | |
804 | |
805 // only visit register parameters | |
806 int n = opJavaCall->_arguments->length(); | |
807 for (int i = 0; i < n; i++) { | |
808 if (!opJavaCall->_arguments->at(i)->is_pointer()) { | |
809 do_input(*opJavaCall->_arguments->adr_at(i)); | |
810 } | |
811 } | |
812 | |
813 if (opJavaCall->_info) do_info(opJavaCall->_info); | |
1564 | 814 if (opJavaCall->is_method_handle_invoke()) { |
815 opJavaCall->_method_handle_invoke_SP_save_opr = FrameMap::method_handle_invoke_SP_save_opr(); | |
816 do_temp(opJavaCall->_method_handle_invoke_SP_save_opr); | |
817 } | |
0 | 818 do_call(); |
819 if (opJavaCall->_result->is_valid()) do_output(opJavaCall->_result); | |
820 | |
821 break; | |
822 } | |
823 | |
824 | |
825 // LIR_OpRTCall | |
826 case lir_rtcall: { | |
827 assert(op->as_OpRTCall() != NULL, "must be"); | |
828 LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op; | |
829 | |
830 // only visit register parameters | |
831 int n = opRTCall->_arguments->length(); | |
832 for (int i = 0; i < n; i++) { | |
833 if (!opRTCall->_arguments->at(i)->is_pointer()) { | |
834 do_input(*opRTCall->_arguments->adr_at(i)); | |
835 } | |
836 } | |
837 if (opRTCall->_info) do_info(opRTCall->_info); | |
838 if (opRTCall->_tmp->is_valid()) do_temp(opRTCall->_tmp); | |
839 do_call(); | |
840 if (opRTCall->_result->is_valid()) do_output(opRTCall->_result); | |
841 | |
842 break; | |
843 } | |
844 | |
845 | |
846 // LIR_OpArrayCopy | |
847 case lir_arraycopy: { | |
848 assert(op->as_OpArrayCopy() != NULL, "must be"); | |
849 LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op; | |
850 | |
851 assert(opArrayCopy->_result->is_illegal(), "unused"); | |
852 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src); | |
853 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos); | |
854 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst); | |
855 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos); | |
856 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length); | |
857 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp); | |
858 if (opArrayCopy->_info) do_info(opArrayCopy->_info); | |
859 | |
860 // the implementation of arraycopy always has a call into the runtime | |
861 do_call(); | |
862 | |
863 break; | |
864 } | |
865 | |
866 | |
867 // LIR_OpLock | |
868 case lir_lock: | |
869 case lir_unlock: { | |
870 assert(op->as_OpLock() != NULL, "must be"); | |
871 LIR_OpLock* opLock = (LIR_OpLock*)op; | |
872 | |
873 if (opLock->_info) do_info(opLock->_info); | |
874 | |
875 // TODO: check if these operands really have to be temp | |
876 // (or if input is sufficient). This may have influence on the oop map! | |
877 assert(opLock->_lock->is_valid(), "used"); do_temp(opLock->_lock); | |
878 assert(opLock->_hdr->is_valid(), "used"); do_temp(opLock->_hdr); | |
879 assert(opLock->_obj->is_valid(), "used"); do_temp(opLock->_obj); | |
880 | |
881 if (opLock->_scratch->is_valid()) do_temp(opLock->_scratch); | |
882 assert(opLock->_result->is_illegal(), "unused"); | |
883 | |
884 do_stub(opLock->_stub); | |
885 | |
886 break; | |
887 } | |
888 | |
889 | |
890 // LIR_OpDelay | |
891 case lir_delay_slot: { | |
892 assert(op->as_OpDelay() != NULL, "must be"); | |
893 LIR_OpDelay* opDelay = (LIR_OpDelay*)op; | |
894 | |
895 visit(opDelay->delay_op()); | |
896 break; | |
897 } | |
898 | |
899 // LIR_OpTypeCheck | |
900 case lir_instanceof: | |
901 case lir_checkcast: | |
902 case lir_store_check: { | |
903 assert(op->as_OpTypeCheck() != NULL, "must be"); | |
904 LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op; | |
905 | |
906 if (opTypeCheck->_info_for_exception) do_info(opTypeCheck->_info_for_exception); | |
907 if (opTypeCheck->_info_for_patch) do_info(opTypeCheck->_info_for_patch); | |
908 if (opTypeCheck->_object->is_valid()) do_input(opTypeCheck->_object); | |
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909 if (op->code() == lir_store_check && opTypeCheck->_object->is_valid()) { |
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910 do_temp(opTypeCheck->_object); |
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911 } |
0 | 912 if (opTypeCheck->_array->is_valid()) do_input(opTypeCheck->_array); |
913 if (opTypeCheck->_tmp1->is_valid()) do_temp(opTypeCheck->_tmp1); | |
914 if (opTypeCheck->_tmp2->is_valid()) do_temp(opTypeCheck->_tmp2); | |
915 if (opTypeCheck->_tmp3->is_valid()) do_temp(opTypeCheck->_tmp3); | |
916 if (opTypeCheck->_result->is_valid()) do_output(opTypeCheck->_result); | |
917 do_stub(opTypeCheck->_stub); | |
918 break; | |
919 } | |
920 | |
921 // LIR_OpCompareAndSwap | |
922 case lir_cas_long: | |
923 case lir_cas_obj: | |
924 case lir_cas_int: { | |
925 assert(op->as_OpCompareAndSwap() != NULL, "must be"); | |
926 LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op; | |
927 | |
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928 assert(opCompareAndSwap->_addr->is_valid(), "used"); |
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929 assert(opCompareAndSwap->_cmp_value->is_valid(), "used"); |
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930 assert(opCompareAndSwap->_new_value->is_valid(), "used"); |
0 | 931 if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info); |
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932 do_input(opCompareAndSwap->_addr); |
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933 do_temp(opCompareAndSwap->_addr); |
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934 do_input(opCompareAndSwap->_cmp_value); |
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935 do_temp(opCompareAndSwap->_cmp_value); |
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936 do_input(opCompareAndSwap->_new_value); |
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937 do_temp(opCompareAndSwap->_new_value); |
0 | 938 if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1); |
939 if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2); | |
940 if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result); | |
941 | |
942 break; | |
943 } | |
944 | |
945 | |
946 // LIR_OpAllocArray; | |
947 case lir_alloc_array: { | |
948 assert(op->as_OpAllocArray() != NULL, "must be"); | |
949 LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op; | |
950 | |
951 if (opAllocArray->_info) do_info(opAllocArray->_info); | |
952 if (opAllocArray->_klass->is_valid()) do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass); | |
953 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len); | |
954 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1); | |
955 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2); | |
956 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3); | |
957 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4); | |
958 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result); | |
959 do_stub(opAllocArray->_stub); | |
960 break; | |
961 } | |
962 | |
963 // LIR_OpProfileCall: | |
964 case lir_profile_call: { | |
965 assert(op->as_OpProfileCall() != NULL, "must be"); | |
966 LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op; | |
967 | |
968 if (opProfileCall->_recv->is_valid()) do_temp(opProfileCall->_recv); | |
969 assert(opProfileCall->_mdo->is_valid(), "used"); do_temp(opProfileCall->_mdo); | |
970 assert(opProfileCall->_tmp1->is_valid(), "used"); do_temp(opProfileCall->_tmp1); | |
971 break; | |
972 } | |
973 default: | |
974 ShouldNotReachHere(); | |
975 } | |
976 } | |
977 | |
978 | |
979 void LIR_OpVisitState::do_stub(CodeStub* stub) { | |
980 if (stub != NULL) { | |
981 stub->visit(this); | |
982 } | |
983 } | |
984 | |
985 XHandlers* LIR_OpVisitState::all_xhandler() { | |
986 XHandlers* result = NULL; | |
987 | |
988 int i; | |
989 for (i = 0; i < info_count(); i++) { | |
990 if (info_at(i)->exception_handlers() != NULL) { | |
991 result = info_at(i)->exception_handlers(); | |
992 break; | |
993 } | |
994 } | |
995 | |
996 #ifdef ASSERT | |
997 for (i = 0; i < info_count(); i++) { | |
998 assert(info_at(i)->exception_handlers() == NULL || | |
999 info_at(i)->exception_handlers() == result, | |
1000 "only one xhandler list allowed per LIR-operation"); | |
1001 } | |
1002 #endif | |
1003 | |
1004 if (result != NULL) { | |
1005 return result; | |
1006 } else { | |
1007 return new XHandlers(); | |
1008 } | |
1009 | |
1010 return result; | |
1011 } | |
1012 | |
1013 | |
1014 #ifdef ASSERT | |
1015 bool LIR_OpVisitState::no_operands(LIR_Op* op) { | |
1016 visit(op); | |
1017 | |
1018 return opr_count(inputMode) == 0 && | |
1019 opr_count(outputMode) == 0 && | |
1020 opr_count(tempMode) == 0 && | |
1021 info_count() == 0 && | |
1022 !has_call() && | |
1023 !has_slow_case(); | |
1024 } | |
1025 #endif | |
1026 | |
1027 //--------------------------------------------------- | |
1028 | |
1029 | |
1030 void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) { | |
1031 masm->emit_call(this); | |
1032 } | |
1033 | |
1034 void LIR_OpRTCall::emit_code(LIR_Assembler* masm) { | |
1035 masm->emit_rtcall(this); | |
1036 } | |
1037 | |
1038 void LIR_OpLabel::emit_code(LIR_Assembler* masm) { | |
1039 masm->emit_opLabel(this); | |
1040 } | |
1041 | |
1042 void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) { | |
1043 masm->emit_arraycopy(this); | |
1044 masm->emit_code_stub(stub()); | |
1045 } | |
1046 | |
1047 void LIR_Op0::emit_code(LIR_Assembler* masm) { | |
1048 masm->emit_op0(this); | |
1049 } | |
1050 | |
1051 void LIR_Op1::emit_code(LIR_Assembler* masm) { | |
1052 masm->emit_op1(this); | |
1053 } | |
1054 | |
1055 void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) { | |
1056 masm->emit_alloc_obj(this); | |
1057 masm->emit_code_stub(stub()); | |
1058 } | |
1059 | |
1060 void LIR_OpBranch::emit_code(LIR_Assembler* masm) { | |
1061 masm->emit_opBranch(this); | |
1062 if (stub()) { | |
1063 masm->emit_code_stub(stub()); | |
1064 } | |
1065 } | |
1066 | |
1067 void LIR_OpConvert::emit_code(LIR_Assembler* masm) { | |
1068 masm->emit_opConvert(this); | |
1069 if (stub() != NULL) { | |
1070 masm->emit_code_stub(stub()); | |
1071 } | |
1072 } | |
1073 | |
1074 void LIR_Op2::emit_code(LIR_Assembler* masm) { | |
1075 masm->emit_op2(this); | |
1076 } | |
1077 | |
1078 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) { | |
1079 masm->emit_alloc_array(this); | |
1080 masm->emit_code_stub(stub()); | |
1081 } | |
1082 | |
1083 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) { | |
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1084 masm->emit_opTypeCheck(this); |
0 | 1085 if (stub()) { |
1086 masm->emit_code_stub(stub()); | |
1087 } | |
1088 } | |
1089 | |
1090 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) { | |
1091 masm->emit_compare_and_swap(this); | |
1092 } | |
1093 | |
1094 void LIR_Op3::emit_code(LIR_Assembler* masm) { | |
1095 masm->emit_op3(this); | |
1096 } | |
1097 | |
1098 void LIR_OpLock::emit_code(LIR_Assembler* masm) { | |
1099 masm->emit_lock(this); | |
1100 if (stub()) { | |
1101 masm->emit_code_stub(stub()); | |
1102 } | |
1103 } | |
1104 | |
1105 | |
1106 void LIR_OpDelay::emit_code(LIR_Assembler* masm) { | |
1107 masm->emit_delay(this); | |
1108 } | |
1109 | |
1110 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) { | |
1111 masm->emit_profile_call(this); | |
1112 } | |
1113 | |
1114 // LIR_List | |
1115 LIR_List::LIR_List(Compilation* compilation, BlockBegin* block) | |
1116 : _operations(8) | |
1117 , _compilation(compilation) | |
1118 #ifndef PRODUCT | |
1119 , _block(block) | |
1120 #endif | |
1121 #ifdef ASSERT | |
1122 , _file(NULL) | |
1123 , _line(0) | |
1124 #endif | |
1125 { } | |
1126 | |
1127 | |
1128 #ifdef ASSERT | |
1129 void LIR_List::set_file_and_line(const char * file, int line) { | |
1130 const char * f = strrchr(file, '/'); | |
1131 if (f == NULL) f = strrchr(file, '\\'); | |
1132 if (f == NULL) { | |
1133 f = file; | |
1134 } else { | |
1135 f++; | |
1136 } | |
1137 _file = f; | |
1138 _line = line; | |
1139 } | |
1140 #endif | |
1141 | |
1142 | |
1143 void LIR_List::append(LIR_InsertionBuffer* buffer) { | |
1144 assert(this == buffer->lir_list(), "wrong lir list"); | |
1145 const int n = _operations.length(); | |
1146 | |
1147 if (buffer->number_of_ops() > 0) { | |
1148 // increase size of instructions list | |
1149 _operations.at_grow(n + buffer->number_of_ops() - 1, NULL); | |
1150 // insert ops from buffer into instructions list | |
1151 int op_index = buffer->number_of_ops() - 1; | |
1152 int ip_index = buffer->number_of_insertion_points() - 1; | |
1153 int from_index = n - 1; | |
1154 int to_index = _operations.length() - 1; | |
1155 for (; ip_index >= 0; ip_index --) { | |
1156 int index = buffer->index_at(ip_index); | |
1157 // make room after insertion point | |
1158 while (index < from_index) { | |
1159 _operations.at_put(to_index --, _operations.at(from_index --)); | |
1160 } | |
1161 // insert ops from buffer | |
1162 for (int i = buffer->count_at(ip_index); i > 0; i --) { | |
1163 _operations.at_put(to_index --, buffer->op_at(op_index --)); | |
1164 } | |
1165 } | |
1166 } | |
1167 | |
1168 buffer->finish(); | |
1169 } | |
1170 | |
1171 | |
1172 void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) { | |
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1173 assert(reg->type() == T_OBJECT, "bad reg"); |
0 | 1174 append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg, T_OBJECT, lir_patch_normal, info)); |
1175 } | |
1176 | |
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1177 void LIR_List::klass2reg_patch(Metadata* o, LIR_Opr reg, CodeEmitInfo* info) { |
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1178 assert(reg->type() == T_METADATA, "bad reg"); |
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1179 append(new LIR_Op1(lir_move, LIR_OprFact::metadataConst(o), reg, T_METADATA, lir_patch_normal, info)); |
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1180 } |
0 | 1181 |
1182 void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) { | |
1183 append(new LIR_Op1( | |
1184 lir_move, | |
1185 LIR_OprFact::address(addr), | |
1186 src, | |
1187 addr->type(), | |
1188 patch_code, | |
1189 info)); | |
1190 } | |
1191 | |
1192 | |
1193 void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) { | |
1194 append(new LIR_Op1( | |
1195 lir_move, | |
1196 LIR_OprFact::address(address), | |
1197 dst, | |
1198 address->type(), | |
1199 patch_code, | |
1200 info, lir_move_volatile)); | |
1201 } | |
1202 | |
1203 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { | |
1204 append(new LIR_Op1( | |
1205 lir_move, | |
1206 LIR_OprFact::address(new LIR_Address(base, offset, type)), | |
1207 dst, | |
1208 type, | |
1209 patch_code, | |
1210 info, lir_move_volatile)); | |
1211 } | |
1212 | |
1213 | |
1214 void LIR_List::prefetch(LIR_Address* addr, bool is_store) { | |
1215 append(new LIR_Op1( | |
1216 is_store ? lir_prefetchw : lir_prefetchr, | |
1217 LIR_OprFact::address(addr))); | |
1218 } | |
1219 | |
1220 | |
1221 void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { | |
1222 append(new LIR_Op1( | |
1223 lir_move, | |
1224 LIR_OprFact::intConst(v), | |
1225 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)), | |
1226 type, | |
1227 patch_code, | |
1228 info)); | |
1229 } | |
1230 | |
1231 | |
1232 void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { | |
1233 append(new LIR_Op1( | |
1234 lir_move, | |
1235 LIR_OprFact::oopConst(o), | |
1236 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)), | |
1237 type, | |
1238 patch_code, | |
1239 info)); | |
1240 } | |
1241 | |
1242 | |
1243 void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) { | |
1244 append(new LIR_Op1( | |
1245 lir_move, | |
1246 src, | |
1247 LIR_OprFact::address(addr), | |
1248 addr->type(), | |
1249 patch_code, | |
1250 info)); | |
1251 } | |
1252 | |
1253 | |
1254 void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) { | |
1255 append(new LIR_Op1( | |
1256 lir_move, | |
1257 src, | |
1258 LIR_OprFact::address(addr), | |
1259 addr->type(), | |
1260 patch_code, | |
1261 info, | |
1262 lir_move_volatile)); | |
1263 } | |
1264 | |
1265 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { | |
1266 append(new LIR_Op1( | |
1267 lir_move, | |
1268 src, | |
1269 LIR_OprFact::address(new LIR_Address(base, offset, type)), | |
1270 type, | |
1271 patch_code, | |
1272 info, lir_move_volatile)); | |
1273 } | |
1274 | |
1275 | |
1276 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { | |
1277 append(new LIR_Op3( | |
1278 lir_idiv, | |
1279 left, | |
1280 right, | |
1281 tmp, | |
1282 res, | |
1283 info)); | |
1284 } | |
1285 | |
1286 | |
1287 void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { | |
1288 append(new LIR_Op3( | |
1289 lir_idiv, | |
1290 left, | |
1291 LIR_OprFact::intConst(right), | |
1292 tmp, | |
1293 res, | |
1294 info)); | |
1295 } | |
1296 | |
1297 | |
1298 void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { | |
1299 append(new LIR_Op3( | |
1300 lir_irem, | |
1301 left, | |
1302 right, | |
1303 tmp, | |
1304 res, | |
1305 info)); | |
1306 } | |
1307 | |
1308 | |
1309 void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { | |
1310 append(new LIR_Op3( | |
1311 lir_irem, | |
1312 left, | |
1313 LIR_OprFact::intConst(right), | |
1314 tmp, | |
1315 res, | |
1316 info)); | |
1317 } | |
1318 | |
1319 | |
1320 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) { | |
1321 append(new LIR_Op2( | |
1322 lir_cmp, | |
1323 condition, | |
1324 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)), | |
1325 LIR_OprFact::intConst(c), | |
1326 info)); | |
1327 } | |
1328 | |
1329 | |
1330 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) { | |
1331 append(new LIR_Op2( | |
1332 lir_cmp, | |
1333 condition, | |
1334 reg, | |
1335 LIR_OprFact::address(addr), | |
1336 info)); | |
1337 } | |
1338 | |
1339 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4, | |
1340 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) { | |
1341 append(new LIR_OpAllocObj( | |
1342 klass, | |
1343 dst, | |
1344 t1, | |
1345 t2, | |
1346 t3, | |
1347 t4, | |
1348 header_size, | |
1349 object_size, | |
1350 init_check, | |
1351 stub)); | |
1352 } | |
1353 | |
1354 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) { | |
1355 append(new LIR_OpAllocArray( | |
1356 klass, | |
1357 len, | |
1358 dst, | |
1359 t1, | |
1360 t2, | |
1361 t3, | |
1362 t4, | |
1363 type, | |
1364 stub)); | |
1365 } | |
1366 | |
1367 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { | |
1368 append(new LIR_Op2( | |
1369 lir_shl, | |
1370 value, | |
1371 count, | |
1372 dst, | |
1373 tmp)); | |
1374 } | |
1375 | |
1376 void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { | |
1377 append(new LIR_Op2( | |
1378 lir_shr, | |
1379 value, | |
1380 count, | |
1381 dst, | |
1382 tmp)); | |
1383 } | |
1384 | |
1385 | |
1386 void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { | |
1387 append(new LIR_Op2( | |
1388 lir_ushr, | |
1389 value, | |
1390 count, | |
1391 dst, | |
1392 tmp)); | |
1393 } | |
1394 | |
1395 void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) { | |
1396 append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i, | |
1397 left, | |
1398 right, | |
1399 dst)); | |
1400 } | |
1401 | |
1402 void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) { | |
1403 append(new LIR_OpLock( | |
1404 lir_lock, | |
1405 hdr, | |
1406 obj, | |
1407 lock, | |
1408 scratch, | |
1409 stub, | |
1410 info)); | |
1411 } | |
1412 | |
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1413 void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub) { |
0 | 1414 append(new LIR_OpLock( |
1415 lir_unlock, | |
1416 hdr, | |
1417 obj, | |
1418 lock, | |
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1419 scratch, |
0 | 1420 stub, |
1421 NULL)); | |
1422 } | |
1423 | |
1424 | |
1425 void check_LIR() { | |
1426 // cannot do the proper checking as PRODUCT and other modes return different results | |
1427 // guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table"); | |
1428 } | |
1429 | |
1430 | |
1431 | |
1432 void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass, | |
1433 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, | |
1434 CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub, | |
1435 ciMethod* profiled_method, int profiled_bci) { | |
1783 | 1436 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_checkcast, result, object, klass, |
1437 tmp1, tmp2, tmp3, fast_check, info_for_exception, info_for_patch, stub); | |
1438 if (profiled_method != NULL) { | |
1439 c->set_profiled_method(profiled_method); | |
1440 c->set_profiled_bci(profiled_bci); | |
1441 c->set_should_profile(true); | |
1442 } | |
1443 append(c); | |
0 | 1444 } |
1445 | |
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1446 void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch, ciMethod* profiled_method, int profiled_bci) { |
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1447 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, NULL, info_for_patch, NULL); |
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1448 if (profiled_method != NULL) { |
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1449 c->set_profiled_method(profiled_method); |
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1450 c->set_profiled_bci(profiled_bci); |
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1451 c->set_should_profile(true); |
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1452 } |
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1453 append(c); |
0 | 1454 } |
1455 | |
1456 | |
3957 | 1457 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, |
1458 CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) { | |
1459 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception); | |
1460 if (profiled_method != NULL) { | |
1461 c->set_profiled_method(profiled_method); | |
1462 c->set_profiled_bci(profiled_bci); | |
1463 c->set_should_profile(true); | |
1464 } | |
1465 append(c); | |
0 | 1466 } |
1467 | |
1468 | |
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1469 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, |
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1470 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { |
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1471 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result)); |
0 | 1472 } |
1473 | |
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1474 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, |
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1475 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { |
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1476 append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result)); |
0 | 1477 } |
1478 | |
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1479 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, |
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1480 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { |
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1481 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result)); |
0 | 1482 } |
1483 | |
1484 | |
1485 #ifdef PRODUCT | |
1486 | |
1487 void print_LIR(BlockList* blocks) { | |
1488 } | |
1489 | |
1490 #else | |
1491 // LIR_OprDesc | |
1492 void LIR_OprDesc::print() const { | |
1493 print(tty); | |
1494 } | |
1495 | |
1496 void LIR_OprDesc::print(outputStream* out) const { | |
1497 if (is_illegal()) { | |
1498 return; | |
1499 } | |
1500 | |
1501 out->print("["); | |
1502 if (is_pointer()) { | |
1503 pointer()->print_value_on(out); | |
1504 } else if (is_single_stack()) { | |
1505 out->print("stack:%d", single_stack_ix()); | |
1506 } else if (is_double_stack()) { | |
1507 out->print("dbl_stack:%d",double_stack_ix()); | |
1508 } else if (is_virtual()) { | |
1509 out->print("R%d", vreg_number()); | |
1510 } else if (is_single_cpu()) { | |
1511 out->print(as_register()->name()); | |
1512 } else if (is_double_cpu()) { | |
1513 out->print(as_register_hi()->name()); | |
1514 out->print(as_register_lo()->name()); | |
304 | 1515 #if defined(X86) |
0 | 1516 } else if (is_single_xmm()) { |
1517 out->print(as_xmm_float_reg()->name()); | |
1518 } else if (is_double_xmm()) { | |
1519 out->print(as_xmm_double_reg()->name()); | |
1520 } else if (is_single_fpu()) { | |
1521 out->print("fpu%d", fpu_regnr()); | |
1522 } else if (is_double_fpu()) { | |
1523 out->print("fpu%d", fpu_regnrLo()); | |
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1524 #elif defined(ARM) |
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1525 } else if (is_single_fpu()) { |
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1526 out->print("s%d", fpu_regnr()); |
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1527 } else if (is_double_fpu()) { |
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1528 out->print("d%d", fpu_regnrLo() >> 1); |
0 | 1529 #else |
1530 } else if (is_single_fpu()) { | |
1531 out->print(as_float_reg()->name()); | |
1532 } else if (is_double_fpu()) { | |
1533 out->print(as_double_reg()->name()); | |
1534 #endif | |
1535 | |
1536 } else if (is_illegal()) { | |
1537 out->print("-"); | |
1538 } else { | |
1539 out->print("Unknown Operand"); | |
1540 } | |
1541 if (!is_illegal()) { | |
1542 out->print("|%c", type_char()); | |
1543 } | |
1544 if (is_register() && is_last_use()) { | |
1545 out->print("(last_use)"); | |
1546 } | |
1547 out->print("]"); | |
1548 } | |
1549 | |
1550 | |
1551 // LIR_Address | |
1552 void LIR_Const::print_value_on(outputStream* out) const { | |
1553 switch (type()) { | |
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1554 case T_ADDRESS:out->print("address:%d",as_jint()); break; |
0 | 1555 case T_INT: out->print("int:%d", as_jint()); break; |
1556 case T_LONG: out->print("lng:%lld", as_jlong()); break; | |
1557 case T_FLOAT: out->print("flt:%f", as_jfloat()); break; | |
1558 case T_DOUBLE: out->print("dbl:%f", as_jdouble()); break; | |
1559 case T_OBJECT: out->print("obj:0x%x", as_jobject()); break; | |
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1560 case T_METADATA: out->print("metadata:0x%x", as_metadata());break; |
0 | 1561 default: out->print("%3d:0x%x",type(), as_jdouble()); break; |
1562 } | |
1563 } | |
1564 | |
1565 // LIR_Address | |
1566 void LIR_Address::print_value_on(outputStream* out) const { | |
1567 out->print("Base:"); _base->print(out); | |
1568 if (!_index->is_illegal()) { | |
1569 out->print(" Index:"); _index->print(out); | |
1570 switch (scale()) { | |
1571 case times_1: break; | |
1572 case times_2: out->print(" * 2"); break; | |
1573 case times_4: out->print(" * 4"); break; | |
1574 case times_8: out->print(" * 8"); break; | |
1575 } | |
1576 } | |
1577 out->print(" Disp: %d", _disp); | |
1578 } | |
1579 | |
1580 // debug output of block header without InstructionPrinter | |
1581 // (because phi functions are not necessary for LIR) | |
1582 static void print_block(BlockBegin* x) { | |
1583 // print block id | |
1584 BlockEnd* end = x->end(); | |
1585 tty->print("B%d ", x->block_id()); | |
1586 | |
1587 // print flags | |
1588 if (x->is_set(BlockBegin::std_entry_flag)) tty->print("std "); | |
1589 if (x->is_set(BlockBegin::osr_entry_flag)) tty->print("osr "); | |
1590 if (x->is_set(BlockBegin::exception_entry_flag)) tty->print("ex "); | |
1591 if (x->is_set(BlockBegin::subroutine_entry_flag)) tty->print("jsr "); | |
1592 if (x->is_set(BlockBegin::backward_branch_target_flag)) tty->print("bb "); | |
1593 if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh "); | |
1594 if (x->is_set(BlockBegin::linear_scan_loop_end_flag)) tty->print("le "); | |
1595 | |
1596 // print block bci range | |
1819 | 1597 tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->printable_bci())); |
0 | 1598 |
1599 // print predecessors and successors | |
1600 if (x->number_of_preds() > 0) { | |
1601 tty->print("preds: "); | |
1602 for (int i = 0; i < x->number_of_preds(); i ++) { | |
1603 tty->print("B%d ", x->pred_at(i)->block_id()); | |
1604 } | |
1605 } | |
1606 | |
1607 if (x->number_of_sux() > 0) { | |
1608 tty->print("sux: "); | |
1609 for (int i = 0; i < x->number_of_sux(); i ++) { | |
1610 tty->print("B%d ", x->sux_at(i)->block_id()); | |
1611 } | |
1612 } | |
1613 | |
1614 // print exception handlers | |
1615 if (x->number_of_exception_handlers() > 0) { | |
1616 tty->print("xhandler: "); | |
1617 for (int i = 0; i < x->number_of_exception_handlers(); i++) { | |
1618 tty->print("B%d ", x->exception_handler_at(i)->block_id()); | |
1619 } | |
1620 } | |
1621 | |
1622 tty->cr(); | |
1623 } | |
1624 | |
1625 void print_LIR(BlockList* blocks) { | |
1626 tty->print_cr("LIR:"); | |
1627 int i; | |
1628 for (i = 0; i < blocks->length(); i++) { | |
1629 BlockBegin* bb = blocks->at(i); | |
1630 print_block(bb); | |
1631 tty->print("__id_Instruction___________________________________________"); tty->cr(); | |
1632 bb->lir()->print_instructions(); | |
1633 } | |
1634 } | |
1635 | |
1636 void LIR_List::print_instructions() { | |
1637 for (int i = 0; i < _operations.length(); i++) { | |
1638 _operations.at(i)->print(); tty->cr(); | |
1639 } | |
1640 tty->cr(); | |
1641 } | |
1642 | |
1643 // LIR_Ops printing routines | |
1644 // LIR_Op | |
1645 void LIR_Op::print_on(outputStream* out) const { | |
1646 if (id() != -1 || PrintCFGToFile) { | |
1647 out->print("%4d ", id()); | |
1648 } else { | |
1649 out->print(" "); | |
1650 } | |
1651 out->print(name()); out->print(" "); | |
1652 print_instr(out); | |
1819 | 1653 if (info() != NULL) out->print(" [bci:%d]", info()->stack()->bci()); |
0 | 1654 #ifdef ASSERT |
1655 if (Verbose && _file != NULL) { | |
1656 out->print(" (%s:%d)", _file, _line); | |
1657 } | |
1658 #endif | |
1659 } | |
1660 | |
1661 const char * LIR_Op::name() const { | |
1662 const char* s = NULL; | |
1663 switch(code()) { | |
1664 // LIR_Op0 | |
1665 case lir_membar: s = "membar"; break; | |
1666 case lir_membar_acquire: s = "membar_acquire"; break; | |
1667 case lir_membar_release: s = "membar_release"; break; | |
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1668 case lir_membar_loadload: s = "membar_loadload"; break; |
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1669 case lir_membar_storestore: s = "membar_storestore"; break; |
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1670 case lir_membar_loadstore: s = "membar_loadstore"; break; |
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1671 case lir_membar_storeload: s = "membar_storeload"; break; |
0 | 1672 case lir_word_align: s = "word_align"; break; |
1673 case lir_label: s = "label"; break; | |
1674 case lir_nop: s = "nop"; break; | |
1675 case lir_backwardbranch_target: s = "backbranch"; break; | |
1676 case lir_std_entry: s = "std_entry"; break; | |
1677 case lir_osr_entry: s = "osr_entry"; break; | |
1678 case lir_build_frame: s = "build_frm"; break; | |
1679 case lir_fpop_raw: s = "fpop_raw"; break; | |
1680 case lir_24bit_FPU: s = "24bit_FPU"; break; | |
1681 case lir_reset_FPU: s = "reset_FPU"; break; | |
1682 case lir_breakpoint: s = "breakpoint"; break; | |
1683 case lir_get_thread: s = "get_thread"; break; | |
1684 // LIR_Op1 | |
1685 case lir_fxch: s = "fxch"; break; | |
1686 case lir_fld: s = "fld"; break; | |
1687 case lir_ffree: s = "ffree"; break; | |
1688 case lir_push: s = "push"; break; | |
1689 case lir_pop: s = "pop"; break; | |
1690 case lir_null_check: s = "null_check"; break; | |
1691 case lir_return: s = "return"; break; | |
1692 case lir_safepoint: s = "safepoint"; break; | |
1693 case lir_neg: s = "neg"; break; | |
1694 case lir_leal: s = "leal"; break; | |
1695 case lir_branch: s = "branch"; break; | |
1696 case lir_cond_float_branch: s = "flt_cond_br"; break; | |
1697 case lir_move: s = "move"; break; | |
1698 case lir_roundfp: s = "roundfp"; break; | |
1699 case lir_rtcall: s = "rtcall"; break; | |
1700 case lir_throw: s = "throw"; break; | |
1701 case lir_unwind: s = "unwind"; break; | |
1702 case lir_convert: s = "convert"; break; | |
1703 case lir_alloc_object: s = "alloc_obj"; break; | |
1704 case lir_monaddr: s = "mon_addr"; break; | |
1783 | 1705 case lir_pack64: s = "pack64"; break; |
1706 case lir_unpack64: s = "unpack64"; break; | |
0 | 1707 // LIR_Op2 |
1708 case lir_cmp: s = "cmp"; break; | |
1709 case lir_cmp_l2i: s = "cmp_l2i"; break; | |
1710 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break; | |
1711 case lir_cmp_fd2i: s = "comp_fd2i"; break; | |
1712 case lir_cmove: s = "cmove"; break; | |
1713 case lir_add: s = "add"; break; | |
1714 case lir_sub: s = "sub"; break; | |
1715 case lir_mul: s = "mul"; break; | |
1716 case lir_mul_strictfp: s = "mul_strictfp"; break; | |
1717 case lir_div: s = "div"; break; | |
1718 case lir_div_strictfp: s = "div_strictfp"; break; | |
1719 case lir_rem: s = "rem"; break; | |
1720 case lir_abs: s = "abs"; break; | |
1721 case lir_sqrt: s = "sqrt"; break; | |
1722 case lir_sin: s = "sin"; break; | |
1723 case lir_cos: s = "cos"; break; | |
1724 case lir_tan: s = "tan"; break; | |
1725 case lir_log: s = "log"; break; | |
1726 case lir_log10: s = "log10"; break; | |
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1727 case lir_exp: s = "exp"; break; |
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1728 case lir_pow: s = "pow"; break; |
0 | 1729 case lir_logic_and: s = "logic_and"; break; |
1730 case lir_logic_or: s = "logic_or"; break; | |
1731 case lir_logic_xor: s = "logic_xor"; break; | |
1732 case lir_shl: s = "shift_left"; break; | |
1733 case lir_shr: s = "shift_right"; break; | |
1734 case lir_ushr: s = "ushift_right"; break; | |
1735 case lir_alloc_array: s = "alloc_array"; break; | |
1736 // LIR_Op3 | |
1737 case lir_idiv: s = "idiv"; break; | |
1738 case lir_irem: s = "irem"; break; | |
1739 // LIR_OpJavaCall | |
1740 case lir_static_call: s = "static"; break; | |
1741 case lir_optvirtual_call: s = "optvirtual"; break; | |
1742 case lir_icvirtual_call: s = "icvirtual"; break; | |
1743 case lir_virtual_call: s = "virtual"; break; | |
1295 | 1744 case lir_dynamic_call: s = "dynamic"; break; |
0 | 1745 // LIR_OpArrayCopy |
1746 case lir_arraycopy: s = "arraycopy"; break; | |
1747 // LIR_OpLock | |
1748 case lir_lock: s = "lock"; break; | |
1749 case lir_unlock: s = "unlock"; break; | |
1750 // LIR_OpDelay | |
1751 case lir_delay_slot: s = "delay"; break; | |
1752 // LIR_OpTypeCheck | |
1753 case lir_instanceof: s = "instanceof"; break; | |
1754 case lir_checkcast: s = "checkcast"; break; | |
1755 case lir_store_check: s = "store_check"; break; | |
1756 // LIR_OpCompareAndSwap | |
1757 case lir_cas_long: s = "cas_long"; break; | |
1758 case lir_cas_obj: s = "cas_obj"; break; | |
1759 case lir_cas_int: s = "cas_int"; break; | |
1760 // LIR_OpProfileCall | |
1761 case lir_profile_call: s = "profile_call"; break; | |
1762 case lir_none: ShouldNotReachHere();break; | |
1763 default: s = "illegal_op"; break; | |
1764 } | |
1765 return s; | |
1766 } | |
1767 | |
1768 // LIR_OpJavaCall | |
1769 void LIR_OpJavaCall::print_instr(outputStream* out) const { | |
1770 out->print("call: "); | |
1771 out->print("[addr: 0x%x]", address()); | |
1772 if (receiver()->is_valid()) { | |
1773 out->print(" [recv: "); receiver()->print(out); out->print("]"); | |
1774 } | |
1775 if (result_opr()->is_valid()) { | |
1776 out->print(" [result: "); result_opr()->print(out); out->print("]"); | |
1777 } | |
1778 } | |
1779 | |
1780 // LIR_OpLabel | |
1781 void LIR_OpLabel::print_instr(outputStream* out) const { | |
1782 out->print("[label:0x%x]", _label); | |
1783 } | |
1784 | |
1785 // LIR_OpArrayCopy | |
1786 void LIR_OpArrayCopy::print_instr(outputStream* out) const { | |
1787 src()->print(out); out->print(" "); | |
1788 src_pos()->print(out); out->print(" "); | |
1789 dst()->print(out); out->print(" "); | |
1790 dst_pos()->print(out); out->print(" "); | |
1791 length()->print(out); out->print(" "); | |
1792 tmp()->print(out); out->print(" "); | |
1793 } | |
1794 | |
1795 // LIR_OpCompareAndSwap | |
1796 void LIR_OpCompareAndSwap::print_instr(outputStream* out) const { | |
1797 addr()->print(out); out->print(" "); | |
1798 cmp_value()->print(out); out->print(" "); | |
1799 new_value()->print(out); out->print(" "); | |
1800 tmp1()->print(out); out->print(" "); | |
1801 tmp2()->print(out); out->print(" "); | |
1802 | |
1803 } | |
1804 | |
1805 // LIR_Op0 | |
1806 void LIR_Op0::print_instr(outputStream* out) const { | |
1807 result_opr()->print(out); | |
1808 } | |
1809 | |
1810 // LIR_Op1 | |
1811 const char * LIR_Op1::name() const { | |
1812 if (code() == lir_move) { | |
1813 switch (move_kind()) { | |
1814 case lir_move_normal: | |
1815 return "move"; | |
1816 case lir_move_unaligned: | |
1817 return "unaligned move"; | |
1818 case lir_move_volatile: | |
1819 return "volatile_move"; | |
2002 | 1820 case lir_move_wide: |
1821 return "wide_move"; | |
0 | 1822 default: |
1823 ShouldNotReachHere(); | |
1824 return "illegal_op"; | |
1825 } | |
1826 } else { | |
1827 return LIR_Op::name(); | |
1828 } | |
1829 } | |
1830 | |
1831 | |
1832 void LIR_Op1::print_instr(outputStream* out) const { | |
1833 _opr->print(out); out->print(" "); | |
1834 result_opr()->print(out); out->print(" "); | |
1835 print_patch_code(out, patch_code()); | |
1836 } | |
1837 | |
1838 | |
1839 // LIR_Op1 | |
1840 void LIR_OpRTCall::print_instr(outputStream* out) const { | |
1841 intx a = (intx)addr(); | |
1842 out->print(Runtime1::name_for_address(addr())); | |
1843 out->print(" "); | |
1844 tmp()->print(out); | |
1845 } | |
1846 | |
1847 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) { | |
1848 switch(code) { | |
1849 case lir_patch_none: break; | |
1850 case lir_patch_low: out->print("[patch_low]"); break; | |
1851 case lir_patch_high: out->print("[patch_high]"); break; | |
1852 case lir_patch_normal: out->print("[patch_normal]"); break; | |
1853 default: ShouldNotReachHere(); | |
1854 } | |
1855 } | |
1856 | |
1857 // LIR_OpBranch | |
1858 void LIR_OpBranch::print_instr(outputStream* out) const { | |
1859 print_condition(out, cond()); out->print(" "); | |
1860 if (block() != NULL) { | |
1861 out->print("[B%d] ", block()->block_id()); | |
1862 } else if (stub() != NULL) { | |
1863 out->print("["); | |
1864 stub()->print_name(out); | |
1865 out->print(": 0x%x]", stub()); | |
1819 | 1866 if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->stack()->bci()); |
0 | 1867 } else { |
1868 out->print("[label:0x%x] ", label()); | |
1869 } | |
1870 if (ublock() != NULL) { | |
1871 out->print("unordered: [B%d] ", ublock()->block_id()); | |
1872 } | |
1873 } | |
1874 | |
1875 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) { | |
1876 switch(cond) { | |
1877 case lir_cond_equal: out->print("[EQ]"); break; | |
1878 case lir_cond_notEqual: out->print("[NE]"); break; | |
1879 case lir_cond_less: out->print("[LT]"); break; | |
1880 case lir_cond_lessEqual: out->print("[LE]"); break; | |
1881 case lir_cond_greaterEqual: out->print("[GE]"); break; | |
1882 case lir_cond_greater: out->print("[GT]"); break; | |
1883 case lir_cond_belowEqual: out->print("[BE]"); break; | |
1884 case lir_cond_aboveEqual: out->print("[AE]"); break; | |
1885 case lir_cond_always: out->print("[AL]"); break; | |
1886 default: out->print("[%d]",cond); break; | |
1887 } | |
1888 } | |
1889 | |
1890 // LIR_OpConvert | |
1891 void LIR_OpConvert::print_instr(outputStream* out) const { | |
1892 print_bytecode(out, bytecode()); | |
1893 in_opr()->print(out); out->print(" "); | |
1894 result_opr()->print(out); out->print(" "); | |
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1896 if(tmp1()->is_valid()) { |
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1897 tmp1()->print(out); out->print(" "); |
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1898 tmp2()->print(out); out->print(" "); |
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1899 } |
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1900 #endif |
0 | 1901 } |
1902 | |
1903 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) { | |
1904 switch(code) { | |
1905 case Bytecodes::_d2f: out->print("[d2f] "); break; | |
1906 case Bytecodes::_d2i: out->print("[d2i] "); break; | |
1907 case Bytecodes::_d2l: out->print("[d2l] "); break; | |
1908 case Bytecodes::_f2d: out->print("[f2d] "); break; | |
1909 case Bytecodes::_f2i: out->print("[f2i] "); break; | |
1910 case Bytecodes::_f2l: out->print("[f2l] "); break; | |
1911 case Bytecodes::_i2b: out->print("[i2b] "); break; | |
1912 case Bytecodes::_i2c: out->print("[i2c] "); break; | |
1913 case Bytecodes::_i2d: out->print("[i2d] "); break; | |
1914 case Bytecodes::_i2f: out->print("[i2f] "); break; | |
1915 case Bytecodes::_i2l: out->print("[i2l] "); break; | |
1916 case Bytecodes::_i2s: out->print("[i2s] "); break; | |
1917 case Bytecodes::_l2i: out->print("[l2i] "); break; | |
1918 case Bytecodes::_l2f: out->print("[l2f] "); break; | |
1919 case Bytecodes::_l2d: out->print("[l2d] "); break; | |
1920 default: | |
1921 out->print("[?%d]",code); | |
1922 break; | |
1923 } | |
1924 } | |
1925 | |
1926 void LIR_OpAllocObj::print_instr(outputStream* out) const { | |
1927 klass()->print(out); out->print(" "); | |
1928 obj()->print(out); out->print(" "); | |
1929 tmp1()->print(out); out->print(" "); | |
1930 tmp2()->print(out); out->print(" "); | |
1931 tmp3()->print(out); out->print(" "); | |
1932 tmp4()->print(out); out->print(" "); | |
1933 out->print("[hdr:%d]", header_size()); out->print(" "); | |
1934 out->print("[obj:%d]", object_size()); out->print(" "); | |
1935 out->print("[lbl:0x%x]", stub()->entry()); | |
1936 } | |
1937 | |
1938 void LIR_OpRoundFP::print_instr(outputStream* out) const { | |
1939 _opr->print(out); out->print(" "); | |
1940 tmp()->print(out); out->print(" "); | |
1941 result_opr()->print(out); out->print(" "); | |
1942 } | |
1943 | |
1944 // LIR_Op2 | |
1945 void LIR_Op2::print_instr(outputStream* out) const { | |
1946 if (code() == lir_cmove) { | |
1947 print_condition(out, condition()); out->print(" "); | |
1948 } | |
1949 in_opr1()->print(out); out->print(" "); | |
1950 in_opr2()->print(out); out->print(" "); | |
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1951 if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out); out->print(" "); } |
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1952 if (tmp2_opr()->is_valid()) { tmp2_opr()->print(out); out->print(" "); } |
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1953 if (tmp3_opr()->is_valid()) { tmp3_opr()->print(out); out->print(" "); } |
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1954 if (tmp4_opr()->is_valid()) { tmp4_opr()->print(out); out->print(" "); } |
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1955 if (tmp5_opr()->is_valid()) { tmp5_opr()->print(out); out->print(" "); } |
0 | 1956 result_opr()->print(out); |
1957 } | |
1958 | |
1959 void LIR_OpAllocArray::print_instr(outputStream* out) const { | |
1960 klass()->print(out); out->print(" "); | |
1961 len()->print(out); out->print(" "); | |
1962 obj()->print(out); out->print(" "); | |
1963 tmp1()->print(out); out->print(" "); | |
1964 tmp2()->print(out); out->print(" "); | |
1965 tmp3()->print(out); out->print(" "); | |
1966 tmp4()->print(out); out->print(" "); | |
1967 out->print("[type:0x%x]", type()); out->print(" "); | |
1968 out->print("[label:0x%x]", stub()->entry()); | |
1969 } | |
1970 | |
1971 | |
1972 void LIR_OpTypeCheck::print_instr(outputStream* out) const { | |
1973 object()->print(out); out->print(" "); | |
1974 if (code() == lir_store_check) { | |
1975 array()->print(out); out->print(" "); | |
1976 } | |
1977 if (code() != lir_store_check) { | |
1978 klass()->print_name_on(out); out->print(" "); | |
1979 if (fast_check()) out->print("fast_check "); | |
1980 } | |
1981 tmp1()->print(out); out->print(" "); | |
1982 tmp2()->print(out); out->print(" "); | |
1983 tmp3()->print(out); out->print(" "); | |
1984 result_opr()->print(out); out->print(" "); | |
1819 | 1985 if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->stack()->bci()); |
0 | 1986 } |
1987 | |
1988 | |
1989 // LIR_Op3 | |
1990 void LIR_Op3::print_instr(outputStream* out) const { | |
1991 in_opr1()->print(out); out->print(" "); | |
1992 in_opr2()->print(out); out->print(" "); | |
1993 in_opr3()->print(out); out->print(" "); | |
1994 result_opr()->print(out); | |
1995 } | |
1996 | |
1997 | |
1998 void LIR_OpLock::print_instr(outputStream* out) const { | |
1999 hdr_opr()->print(out); out->print(" "); | |
2000 obj_opr()->print(out); out->print(" "); | |
2001 lock_opr()->print(out); out->print(" "); | |
2002 if (_scratch->is_valid()) { | |
2003 _scratch->print(out); out->print(" "); | |
2004 } | |
2005 out->print("[lbl:0x%x]", stub()->entry()); | |
2006 } | |
2007 | |
2008 | |
2009 void LIR_OpDelay::print_instr(outputStream* out) const { | |
2010 _op->print_on(out); | |
2011 } | |
2012 | |
2013 | |
2014 // LIR_OpProfileCall | |
2015 void LIR_OpProfileCall::print_instr(outputStream* out) const { | |
2016 profiled_method()->name()->print_symbol_on(out); | |
2017 out->print("."); | |
2018 profiled_method()->holder()->name()->print_symbol_on(out); | |
2019 out->print(" @ %d ", profiled_bci()); | |
2020 mdo()->print(out); out->print(" "); | |
2021 recv()->print(out); out->print(" "); | |
2022 tmp1()->print(out); out->print(" "); | |
2023 } | |
2024 | |
2025 #endif // PRODUCT | |
2026 | |
2027 // Implementation of LIR_InsertionBuffer | |
2028 | |
2029 void LIR_InsertionBuffer::append(int index, LIR_Op* op) { | |
2030 assert(_index_and_count.length() % 2 == 0, "must have a count for each index"); | |
2031 | |
2032 int i = number_of_insertion_points() - 1; | |
2033 if (i < 0 || index_at(i) < index) { | |
2034 append_new(index, 1); | |
2035 } else { | |
2036 assert(index_at(i) == index, "can append LIR_Ops in ascending order only"); | |
2037 assert(count_at(i) > 0, "check"); | |
2038 set_count_at(i, count_at(i) + 1); | |
2039 } | |
2040 _ops.push(op); | |
2041 | |
2042 DEBUG_ONLY(verify()); | |
2043 } | |
2044 | |
2045 #ifdef ASSERT | |
2046 void LIR_InsertionBuffer::verify() { | |
2047 int sum = 0; | |
2048 int prev_idx = -1; | |
2049 | |
2050 for (int i = 0; i < number_of_insertion_points(); i++) { | |
2051 assert(prev_idx < index_at(i), "index must be ordered ascending"); | |
2052 sum += count_at(i); | |
2053 } | |
2054 assert(sum == number_of_ops(), "wrong total sum"); | |
2055 } | |
2056 #endif |