Mercurial > hg > graal-compiler
annotate src/share/vm/c1/c1_LinearScan.hpp @ 2192:b92c45f2bc75
7016023: Enable building ARM and PPC from src/closed repository
Reviewed-by: dholmes, bdelsart
| author | bobv |
|---|---|
| date | Wed, 02 Feb 2011 11:35:26 -0500 |
| parents | 7223744c2784 |
| children | 1d1603768966 |
| rev | line source |
|---|---|
| 0 | 1 /* |
| 1972 | 2 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #ifndef SHARE_VM_C1_C1_LINEARSCAN_HPP |
| 26 #define SHARE_VM_C1_C1_LINEARSCAN_HPP | |
| 27 | |
| 28 #include "c1/c1_FpuStackSim.hpp" | |
| 29 #include "c1/c1_FrameMap.hpp" | |
| 30 #include "c1/c1_IR.hpp" | |
| 31 #include "c1/c1_Instruction.hpp" | |
| 32 #include "c1/c1_LIR.hpp" | |
| 33 #include "c1/c1_LIRGenerator.hpp" | |
| 34 | |
| 0 | 35 class DebugInfoCache; |
| 36 class FpuStackAllocator; | |
| 37 class IRScopeDebugInfo; | |
| 38 class Interval; | |
| 39 class IntervalWalker; | |
| 40 class LIRGenerator; | |
| 41 class LinearScan; | |
| 42 class MoveResolver; | |
| 43 class Range; | |
| 44 | |
| 45 define_array(IntervalArray, Interval*) | |
| 46 define_stack(IntervalList, IntervalArray) | |
| 47 | |
| 48 define_array(IntervalsArray, IntervalList*) | |
| 49 define_stack(IntervalsList, IntervalsArray) | |
| 50 | |
| 51 define_array(OopMapArray, OopMap*) | |
| 52 define_stack(OopMapList, OopMapArray) | |
| 53 | |
| 54 define_array(ScopeValueArray, ScopeValue*) | |
| 55 | |
| 56 define_array(LIR_OpListArray, LIR_OpList*); | |
| 57 define_stack(LIR_OpListStack, LIR_OpListArray); | |
| 58 | |
| 59 | |
| 60 enum IntervalUseKind { | |
| 61 // priority of use kinds must be ascending | |
| 62 noUse = 0, | |
| 63 loopEndMarker = 1, | |
| 64 shouldHaveRegister = 2, | |
| 65 mustHaveRegister = 3, | |
| 66 | |
| 67 firstValidKind = 1, | |
| 68 lastValidKind = 3 | |
| 69 }; | |
| 70 define_array(UseKindArray, IntervalUseKind) | |
| 71 define_stack(UseKindStack, UseKindArray) | |
| 72 | |
| 73 | |
| 74 enum IntervalKind { | |
| 75 fixedKind = 0, // interval pre-colored by LIR_Generator | |
| 76 anyKind = 1, // no register/memory allocated by LIR_Generator | |
| 77 nofKinds, | |
| 78 firstKind = fixedKind | |
| 79 }; | |
| 80 | |
| 81 | |
| 82 // during linear scan an interval is in one of four states in | |
| 83 enum IntervalState { | |
| 84 unhandledState = 0, // unhandled state (not processed yet) | |
| 85 activeState = 1, // life and is in a physical register | |
| 86 inactiveState = 2, // in a life time hole and is in a physical register | |
| 87 handledState = 3, // spilled or not life again | |
| 88 invalidState = -1 | |
| 89 }; | |
| 90 | |
| 91 | |
| 92 enum IntervalSpillState { | |
| 93 noDefinitionFound, // starting state of calculation: no definition found yet | |
| 94 oneDefinitionFound, // one definition has already been found. | |
| 95 // Note: two consecutive definitions are treated as one (e.g. consecutive move and add because of two-operand LIR form) | |
| 96 // the position of this definition is stored in _definition_pos | |
| 97 oneMoveInserted, // one spill move has already been inserted. | |
| 98 storeAtDefinition, // the interval should be stored immediately after its definition because otherwise | |
| 99 // there would be multiple redundant stores | |
| 100 startInMemory, // the interval starts in memory (e.g. method parameter), so a store is never necessary | |
| 101 noOptimization // the interval has more then one definition (e.g. resulting from phi moves), so stores to memory are not optimized | |
| 102 }; | |
| 103 | |
| 104 | |
| 105 #define for_each_interval_kind(kind) \ | |
| 106 for (IntervalKind kind = firstKind; kind < nofKinds; kind = (IntervalKind)(kind + 1)) | |
| 107 | |
| 108 #define for_each_visitor_mode(mode) \ | |
| 109 for (LIR_OpVisitState::OprMode mode = LIR_OpVisitState::firstMode; mode < LIR_OpVisitState::numModes; mode = (LIR_OpVisitState::OprMode)(mode + 1)) | |
| 110 | |
| 111 | |
| 112 class LinearScan : public CompilationResourceObj { | |
| 113 // declare classes used by LinearScan as friends because they | |
| 114 // need a wide variety of functions declared here | |
| 115 // | |
| 116 // Only the small interface to the rest of the compiler is public | |
| 117 friend class Interval; | |
| 118 friend class IntervalWalker; | |
| 119 friend class LinearScanWalker; | |
| 120 friend class FpuStackAllocator; | |
| 121 friend class MoveResolver; | |
| 122 friend class LinearScanStatistic; | |
| 123 friend class LinearScanTimers; | |
| 124 friend class RegisterVerifier; | |
| 125 | |
| 126 public: | |
| 127 enum { | |
| 128 any_reg = -1, | |
| 129 nof_cpu_regs = pd_nof_cpu_regs_linearscan, | |
| 130 nof_fpu_regs = pd_nof_fpu_regs_linearscan, | |
| 131 nof_xmm_regs = pd_nof_xmm_regs_linearscan, | |
| 132 nof_regs = nof_cpu_regs + nof_fpu_regs + nof_xmm_regs | |
| 133 }; | |
| 134 | |
| 135 private: | |
| 136 Compilation* _compilation; | |
| 137 IR* _ir; | |
| 138 LIRGenerator* _gen; | |
| 139 FrameMap* _frame_map; | |
| 140 | |
| 141 BlockList _cached_blocks; // cached list with all blocks in linear-scan order (only correct if original list keeps unchanged) | |
| 142 int _num_virtual_regs; // number of virtual registers (without new registers introduced because of splitting intervals) | |
| 143 bool _has_fpu_registers; // true if this method uses any floating point registers (and so fpu stack allocation is necessary) | |
| 144 int _num_calls; // total number of calls in this method | |
| 145 int _max_spills; // number of stack slots used for intervals allocated to memory | |
| 146 int _unused_spill_slot; // unused spill slot for a single-word value because of alignment of a double-word value | |
| 147 | |
| 148 IntervalList _intervals; // mapping from register number to interval | |
| 149 IntervalList* _new_intervals_from_allocation; // list with all intervals created during allocation when an existing interval is split | |
| 150 IntervalArray* _sorted_intervals; // intervals sorted by Interval::from() | |
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151 bool _needs_full_resort; // set to true if an Interval::from() is changed and _sorted_intervals must be resorted |
| 0 | 152 |
| 153 LIR_OpArray _lir_ops; // mapping from LIR_Op id to LIR_Op node | |
| 154 BlockBeginArray _block_of_op; // mapping from LIR_Op id to the BlockBegin containing this instruction | |
| 155 BitMap _has_info; // bit set for each LIR_Op id that has a CodeEmitInfo | |
| 156 BitMap _has_call; // bit set for each LIR_Op id that destroys all caller save registers | |
| 157 BitMap2D _interval_in_loop; // bit set for each virtual register that is contained in each loop | |
| 158 | |
| 159 // cached debug info to prevent multiple creation of same object | |
| 160 // TODO: cached scope values for registers could be static | |
| 161 ScopeValueArray _scope_value_cache; | |
| 162 | |
| 163 static ConstantOopWriteValue _oop_null_scope_value; | |
| 164 static ConstantIntValue _int_m1_scope_value; | |
| 165 static ConstantIntValue _int_0_scope_value; | |
| 166 static ConstantIntValue _int_1_scope_value; | |
| 167 static ConstantIntValue _int_2_scope_value; | |
| 168 | |
| 169 // accessors | |
| 170 IR* ir() const { return _ir; } | |
| 171 Compilation* compilation() const { return _compilation; } | |
| 172 LIRGenerator* gen() const { return _gen; } | |
| 173 FrameMap* frame_map() const { return _frame_map; } | |
| 174 | |
| 175 // unified bailout support | |
| 176 void bailout(const char* msg) const { compilation()->bailout(msg); } | |
| 177 bool bailed_out() const { return compilation()->bailed_out(); } | |
| 178 | |
| 179 // access to block list (sorted in linear scan order) | |
| 180 int block_count() const { assert(_cached_blocks.length() == ir()->linear_scan_order()->length(), "invalid cached block list"); return _cached_blocks.length(); } | |
| 181 BlockBegin* block_at(int idx) const { assert(_cached_blocks.at(idx) == ir()->linear_scan_order()->at(idx), "invalid cached block list"); return _cached_blocks.at(idx); } | |
| 182 | |
| 183 int num_virtual_regs() const { return _num_virtual_regs; } | |
| 184 // size of live_in and live_out sets of BasicBlocks (BitMap needs rounded size for iteration) | |
| 185 int live_set_size() const { return round_to(_num_virtual_regs, BitsPerWord); } | |
| 186 bool has_fpu_registers() const { return _has_fpu_registers; } | |
| 187 int num_loops() const { return ir()->num_loops(); } | |
| 188 bool is_interval_in_loop(int interval, int loop) const { return _interval_in_loop.at(interval, loop); } | |
| 189 | |
| 190 // handling of fpu stack allocation (platform dependent, needed for debug information generation) | |
| 304 | 191 #ifdef X86 |
| 0 | 192 FpuStackAllocator* _fpu_stack_allocator; |
| 193 bool use_fpu_stack_allocation() const { return UseSSE < 2 && has_fpu_registers(); } | |
| 194 #else | |
| 195 bool use_fpu_stack_allocation() const { return false; } | |
| 196 #endif | |
| 197 | |
| 198 | |
| 199 // access to interval list | |
| 200 int interval_count() const { return _intervals.length(); } | |
| 201 Interval* interval_at(int reg_num) const { return _intervals.at(reg_num); } | |
| 202 | |
| 203 IntervalList* new_intervals_from_allocation() const { return _new_intervals_from_allocation; } | |
| 204 | |
| 205 // access to LIR_Ops and Blocks indexed by op_id | |
| 206 int max_lir_op_id() const { assert(_lir_ops.length() > 0, "no operations"); return (_lir_ops.length() - 1) << 1; } | |
| 207 LIR_Op* lir_op_with_id(int op_id) const { assert(op_id >= 0 && op_id <= max_lir_op_id() && op_id % 2 == 0, "op_id out of range or not even"); return _lir_ops.at(op_id >> 1); } | |
| 208 BlockBegin* block_of_op_with_id(int op_id) const { assert(_block_of_op.length() > 0 && op_id >= 0 && op_id <= max_lir_op_id() + 1, "op_id out of range"); return _block_of_op.at(op_id >> 1); } | |
| 209 | |
| 210 bool is_block_begin(int op_id) { return op_id == 0 || block_of_op_with_id(op_id) != block_of_op_with_id(op_id - 1); } | |
| 211 bool covers_block_begin(int op_id_1, int op_id_2) { return block_of_op_with_id(op_id_1) != block_of_op_with_id(op_id_2); } | |
| 212 | |
| 213 bool has_call(int op_id) { assert(op_id % 2 == 0, "must be even"); return _has_call.at(op_id >> 1); } | |
| 214 bool has_info(int op_id) { assert(op_id % 2 == 0, "must be even"); return _has_info.at(op_id >> 1); } | |
| 215 | |
| 216 | |
| 217 // functions for converting LIR-Operands to register numbers | |
| 218 static bool is_valid_reg_num(int reg_num) { return reg_num >= 0; } | |
| 219 static int reg_num(LIR_Opr opr); | |
| 220 static int reg_numHi(LIR_Opr opr); | |
| 221 | |
| 222 // functions for classification of intervals | |
| 223 static bool is_precolored_interval(const Interval* i); | |
| 224 static bool is_virtual_interval(const Interval* i); | |
| 225 | |
| 226 static bool is_precolored_cpu_interval(const Interval* i); | |
| 227 static bool is_virtual_cpu_interval(const Interval* i); | |
| 228 static bool is_precolored_fpu_interval(const Interval* i); | |
| 229 static bool is_virtual_fpu_interval(const Interval* i); | |
| 230 | |
| 231 static bool is_in_fpu_register(const Interval* i); | |
| 232 static bool is_oop_interval(const Interval* i); | |
| 233 | |
| 234 | |
| 235 // General helper functions | |
| 236 int allocate_spill_slot(bool double_word); | |
| 237 void assign_spill_slot(Interval* it); | |
| 238 void propagate_spill_slots(); | |
| 239 | |
| 240 Interval* create_interval(int reg_num); | |
| 241 void append_interval(Interval* it); | |
| 242 void copy_register_flags(Interval* from, Interval* to); | |
| 243 | |
| 244 // platform dependent functions | |
| 245 static bool is_processed_reg_num(int reg_num); | |
| 246 static int num_physical_regs(BasicType type); | |
| 247 static bool requires_adjacent_regs(BasicType type); | |
| 248 static bool is_caller_save(int assigned_reg); | |
| 249 | |
| 250 // spill move optimization: eliminate moves from register to stack if | |
| 251 // stack slot is known to be correct | |
| 252 void change_spill_definition_pos(Interval* interval, int def_pos); | |
| 253 void change_spill_state(Interval* interval, int spill_pos); | |
| 254 static bool must_store_at_definition(const Interval* i); | |
| 255 void eliminate_spill_moves(); | |
| 256 | |
| 257 // Phase 1: number all instructions in all blocks | |
| 258 void number_instructions(); | |
| 259 | |
| 260 // Phase 2: compute local live sets separately for each block | |
| 261 // (sets live_gen and live_kill for each block) | |
| 262 // | |
| 263 // helper methods used by compute_local_live_sets() | |
| 264 void set_live_gen_kill(Value value, LIR_Op* op, BitMap& live_gen, BitMap& live_kill); | |
| 265 | |
| 266 void compute_local_live_sets(); | |
| 267 | |
| 268 // Phase 3: perform a backward dataflow analysis to compute global live sets | |
| 269 // (sets live_in and live_out for each block) | |
| 270 void compute_global_live_sets(); | |
| 271 | |
| 272 | |
| 273 // Phase 4: build intervals | |
| 274 // (fills the list _intervals) | |
| 275 // | |
| 276 // helper methods used by build_intervals() | |
| 277 void add_use (Value value, int from, int to, IntervalUseKind use_kind); | |
| 278 | |
| 279 void add_def (LIR_Opr opr, int def_pos, IntervalUseKind use_kind); | |
| 280 void add_use (LIR_Opr opr, int from, int to, IntervalUseKind use_kind); | |
| 281 void add_temp(LIR_Opr opr, int temp_pos, IntervalUseKind use_kind); | |
| 282 | |
| 283 void add_def (int reg_num, int def_pos, IntervalUseKind use_kind, BasicType type); | |
| 284 void add_use (int reg_num, int from, int to, IntervalUseKind use_kind, BasicType type); | |
| 285 void add_temp(int reg_num, int temp_pos, IntervalUseKind use_kind, BasicType type); | |
| 286 | |
| 287 // Add platform dependent kills for particular LIR ops. Can be used | |
| 288 // to add platform dependent behaviour for some operations. | |
| 289 void pd_add_temps(LIR_Op* op); | |
| 290 | |
| 291 IntervalUseKind use_kind_of_output_operand(LIR_Op* op, LIR_Opr opr); | |
| 292 IntervalUseKind use_kind_of_input_operand(LIR_Op* op, LIR_Opr opr); | |
| 293 void handle_method_arguments(LIR_Op* op); | |
| 294 void handle_doubleword_moves(LIR_Op* op); | |
| 295 void add_register_hints(LIR_Op* op); | |
| 296 | |
| 297 void build_intervals(); | |
| 298 | |
| 299 | |
| 300 // Phase 5: actual register allocation | |
| 301 // (Uses LinearScanWalker) | |
| 302 // | |
| 303 // helper functions for building a sorted list of intervals | |
| 304 NOT_PRODUCT(bool is_sorted(IntervalArray* intervals);) | |
| 305 static int interval_cmp(Interval** a, Interval** b); | |
| 306 void add_to_list(Interval** first, Interval** prev, Interval* interval); | |
| 307 void create_unhandled_lists(Interval** list1, Interval** list2, bool (is_list1)(const Interval* i), bool (is_list2)(const Interval* i)); | |
| 308 | |
| 309 void sort_intervals_before_allocation(); | |
| 310 void sort_intervals_after_allocation(); | |
| 311 void allocate_registers(); | |
| 312 | |
| 313 | |
| 314 // Phase 6: resolve data flow | |
| 315 // (insert moves at edges between blocks if intervals have been split) | |
| 316 // | |
| 317 // helper functions for resolve_data_flow() | |
| 318 Interval* split_child_at_op_id(Interval* interval, int op_id, LIR_OpVisitState::OprMode mode); | |
| 319 Interval* interval_at_block_begin(BlockBegin* block, int reg_num); | |
| 320 Interval* interval_at_block_end(BlockBegin* block, int reg_num); | |
| 321 Interval* interval_at_op_id(int reg_num, int op_id); | |
| 322 void resolve_collect_mappings(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver); | |
| 323 void resolve_find_insert_pos(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver); | |
| 324 void resolve_data_flow(); | |
| 325 | |
| 326 void resolve_exception_entry(BlockBegin* block, int reg_num, MoveResolver &move_resolver); | |
| 327 void resolve_exception_entry(BlockBegin* block, MoveResolver &move_resolver); | |
| 328 void resolve_exception_edge(XHandler* handler, int throwing_op_id, int reg_num, Phi* phi, MoveResolver &move_resolver); | |
| 329 void resolve_exception_edge(XHandler* handler, int throwing_op_id, MoveResolver &move_resolver); | |
| 330 void resolve_exception_handlers(); | |
| 331 | |
| 332 // Phase 7: assign register numbers back to LIR | |
| 333 // (includes computation of debug information and oop maps) | |
| 334 // | |
| 335 // helper functions for assign_reg_num() | |
| 336 VMReg vm_reg_for_interval(Interval* interval); | |
| 337 VMReg vm_reg_for_operand(LIR_Opr opr); | |
| 338 | |
| 339 static LIR_Opr operand_for_interval(Interval* interval); | |
| 340 static LIR_Opr calc_operand_for_interval(const Interval* interval); | |
| 341 LIR_Opr canonical_spill_opr(Interval* interval); | |
| 342 | |
| 343 LIR_Opr color_lir_opr(LIR_Opr opr, int id, LIR_OpVisitState::OprMode); | |
| 344 | |
| 345 // methods used for oop map computation | |
| 346 IntervalWalker* init_compute_oop_maps(); | |
| 347 OopMap* compute_oop_map(IntervalWalker* iw, LIR_Op* op, CodeEmitInfo* info, bool is_call_site); | |
| 348 void compute_oop_map(IntervalWalker* iw, const LIR_OpVisitState &visitor, LIR_Op* op); | |
| 349 | |
| 350 // methods used for debug information computation | |
| 351 void init_compute_debug_info(); | |
| 352 | |
| 353 MonitorValue* location_for_monitor_index(int monitor_index); | |
| 354 LocationValue* location_for_name(int name, Location::Type loc_type); | |
| 355 | |
| 356 int append_scope_value_for_constant(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values); | |
| 357 int append_scope_value_for_operand(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values); | |
| 358 int append_scope_value(int op_id, Value value, GrowableArray<ScopeValue*>* scope_values); | |
| 359 | |
| 1819 | 360 IRScopeDebugInfo* compute_debug_info_for_scope(int op_id, IRScope* cur_scope, ValueStack* cur_state, ValueStack* innermost_state); |
| 0 | 361 void compute_debug_info(CodeEmitInfo* info, int op_id); |
| 362 | |
| 363 void assign_reg_num(LIR_OpList* instructions, IntervalWalker* iw); | |
| 364 void assign_reg_num(); | |
| 365 | |
| 366 | |
| 367 // Phase 8: fpu stack allocation | |
| 368 // (Used only on x86 when fpu operands are present) | |
| 369 void allocate_fpu_stack(); | |
| 370 | |
| 371 | |
| 372 // helper functions for printing state | |
| 373 #ifndef PRODUCT | |
| 374 static void print_bitmap(BitMap& bitmap); | |
| 375 void print_intervals(const char* label); | |
| 376 void print_lir(int level, const char* label, bool hir_valid = true); | |
| 377 #endif | |
| 378 | |
| 379 #ifdef ASSERT | |
| 380 // verification functions for allocation | |
| 381 // (check that all intervals have a correct register and that no registers are overwritten) | |
| 382 void verify(); | |
| 383 void verify_intervals(); | |
| 384 void verify_no_oops_in_fixed_intervals(); | |
| 385 void verify_constants(); | |
| 386 void verify_registers(); | |
| 387 #endif | |
| 388 | |
| 389 public: | |
| 390 // creation | |
| 391 LinearScan(IR* ir, LIRGenerator* gen, FrameMap* frame_map); | |
| 392 | |
| 393 // main entry function: perform linear scan register allocation | |
| 394 void do_linear_scan(); | |
| 395 | |
| 396 // accessors used by Compilation | |
| 397 int max_spills() const { return _max_spills; } | |
| 398 int num_calls() const { assert(_num_calls >= 0, "not set"); return _num_calls; } | |
| 399 | |
| 400 // entry functions for printing | |
| 401 #ifndef PRODUCT | |
| 402 static void print_statistics(); | |
| 403 static void print_timers(double total); | |
| 404 #endif | |
| 405 }; | |
| 406 | |
| 407 | |
| 408 // Helper class for ordering moves that are inserted at the same position in the LIR | |
| 409 // When moves between registers are inserted, it is important that the moves are | |
| 410 // ordered such that no register is overwritten. So moves from register to stack | |
| 411 // are processed prior to moves from stack to register. When moves have circular | |
| 412 // dependencies, a temporary stack slot is used to break the circle. | |
| 413 // The same logic is used in the LinearScanWalker and in LinearScan during resolve_data_flow | |
| 414 // and therefore factored out in a separate class | |
| 415 class MoveResolver: public StackObj { | |
| 416 private: | |
| 417 LinearScan* _allocator; | |
| 418 | |
| 419 LIR_List* _insert_list; | |
| 420 int _insert_idx; | |
| 421 LIR_InsertionBuffer _insertion_buffer; // buffer where moves are inserted | |
| 422 | |
| 423 IntervalList _mapping_from; | |
| 424 LIR_OprList _mapping_from_opr; | |
| 425 IntervalList _mapping_to; | |
| 426 bool _multiple_reads_allowed; | |
| 427 int _register_blocked[LinearScan::nof_regs]; | |
| 428 | |
| 429 int register_blocked(int reg) { assert(reg >= 0 && reg < LinearScan::nof_regs, "out of bounds"); return _register_blocked[reg]; } | |
| 430 void set_register_blocked(int reg, int direction) { assert(reg >= 0 && reg < LinearScan::nof_regs, "out of bounds"); assert(direction == 1 || direction == -1, "out of bounds"); _register_blocked[reg] += direction; } | |
| 431 | |
| 432 void block_registers(Interval* it); | |
| 433 void unblock_registers(Interval* it); | |
| 434 bool save_to_process_move(Interval* from, Interval* to); | |
| 435 | |
| 436 void create_insertion_buffer(LIR_List* list); | |
| 437 void append_insertion_buffer(); | |
| 438 void insert_move(Interval* from_interval, Interval* to_interval); | |
| 439 void insert_move(LIR_Opr from_opr, Interval* to_interval); | |
| 440 | |
| 441 DEBUG_ONLY(void verify_before_resolve();) | |
| 442 void resolve_mappings(); | |
| 443 public: | |
| 444 MoveResolver(LinearScan* allocator); | |
| 445 | |
| 446 DEBUG_ONLY(void check_empty();) | |
| 447 void set_multiple_reads_allowed() { _multiple_reads_allowed = true; } | |
| 448 void set_insert_position(LIR_List* insert_list, int insert_idx); | |
| 449 void move_insert_position(LIR_List* insert_list, int insert_idx); | |
| 450 void add_mapping(Interval* from, Interval* to); | |
| 451 void add_mapping(LIR_Opr from, Interval* to); | |
| 452 void resolve_and_append_moves(); | |
| 453 | |
| 454 LinearScan* allocator() { return _allocator; } | |
| 455 bool has_mappings() { return _mapping_from.length() > 0; } | |
| 456 }; | |
| 457 | |
| 458 | |
| 459 class Range : public CompilationResourceObj { | |
| 460 friend class Interval; | |
| 461 | |
| 462 private: | |
| 463 static Range* _end; // sentinel (from == to == max_jint) | |
| 464 | |
| 465 int _from; // from (inclusive) | |
| 466 int _to; // to (exclusive) | |
| 467 Range* _next; // linear list of Ranges | |
| 468 | |
| 469 // used only by class Interval, so hide them | |
| 470 bool intersects(Range* r) const { return intersects_at(r) != -1; } | |
| 471 int intersects_at(Range* r) const; | |
| 472 | |
| 473 public: | |
| 474 Range(int from, int to, Range* next); | |
| 475 | |
| 1584 | 476 static void initialize(Arena* arena); |
| 0 | 477 static Range* end() { return _end; } |
| 478 | |
| 479 int from() const { return _from; } | |
| 480 int to() const { return _to; } | |
| 481 Range* next() const { return _next; } | |
| 482 void set_from(int from) { _from = from; } | |
| 483 void set_to(int to) { _to = to; } | |
| 484 void set_next(Range* next) { _next = next; } | |
| 485 | |
| 486 // for testing | |
| 487 void print(outputStream* out = tty) const PRODUCT_RETURN; | |
| 488 }; | |
| 489 | |
| 490 | |
| 491 // Interval is an ordered list of disjoint ranges. | |
| 492 | |
| 493 // For pre-colored double word LIR_Oprs, one interval is created for | |
| 494 // the low word register and one is created for the hi word register. | |
| 495 // On Intel for FPU double registers only one interval is created. At | |
| 496 // all times assigned_reg contains the reg. number of the physical | |
| 497 // register. | |
| 498 | |
| 499 // For LIR_Opr in virtual registers a single interval can represent | |
| 500 // single and double word values. When a physical register is | |
| 501 // assigned to the interval, assigned_reg contains the | |
| 502 // phys. reg. number and for double word values assigned_regHi the | |
| 503 // phys. reg. number of the hi word if there is any. For spilled | |
| 504 // intervals assigned_reg contains the stack index. assigned_regHi is | |
| 505 // always -1. | |
| 506 | |
| 507 class Interval : public CompilationResourceObj { | |
| 508 private: | |
| 509 static Interval* _end; // sentinel (interval with only range Range::end()) | |
| 510 | |
| 511 int _reg_num; | |
| 512 BasicType _type; // valid only for virtual registers | |
| 513 Range* _first; // sorted list of Ranges | |
| 514 intStack _use_pos_and_kinds; // sorted list of use-positions and their according use-kinds | |
| 515 | |
| 516 Range* _current; // interval iteration: the current Range | |
| 517 Interval* _next; // interval iteration: sorted list of Intervals (ends with sentinel) | |
| 518 IntervalState _state; // interval iteration: to which set belongs this interval | |
| 519 | |
| 520 | |
| 521 int _assigned_reg; | |
| 522 int _assigned_regHi; | |
| 523 | |
| 524 int _cached_to; // cached value: to of last range (-1: not cached) | |
| 525 LIR_Opr _cached_opr; | |
| 526 VMReg _cached_vm_reg; | |
| 527 | |
| 528 Interval* _split_parent; // the original interval where this interval is derived from | |
| 529 IntervalList _split_children; // list of all intervals that are split off from this interval (only available for split parents) | |
| 530 Interval* _current_split_child; // the current split child that has been active or inactive last (always stored in split parents) | |
| 531 | |
| 532 int _canonical_spill_slot; // the stack slot where all split parts of this interval are spilled to (always stored in split parents) | |
| 533 bool _insert_move_when_activated; // true if move is inserted between _current_split_child and this interval when interval gets active the first time | |
| 534 IntervalSpillState _spill_state; // for spill move optimization | |
| 535 int _spill_definition_pos; // position where the interval is defined (if defined only once) | |
| 536 Interval* _register_hint; // this interval should be in the same register as the hint interval | |
| 537 | |
| 538 int calc_to(); | |
| 539 Interval* new_split_child(); | |
| 540 public: | |
| 541 Interval(int reg_num); | |
| 542 | |
| 1584 | 543 static void initialize(Arena* arena); |
| 0 | 544 static Interval* end() { return _end; } |
| 545 | |
| 546 // accessors | |
| 547 int reg_num() const { return _reg_num; } | |
| 548 void set_reg_num(int r) { assert(_reg_num == -1, "cannot change reg_num"); _reg_num = r; } | |
| 549 BasicType type() const { assert(_reg_num == -1 || _reg_num >= LIR_OprDesc::vreg_base, "cannot access type for fixed interval"); return _type; } | |
| 550 void set_type(BasicType type) { assert(_reg_num < LIR_OprDesc::vreg_base || _type == T_ILLEGAL || _type == type, "overwriting existing type"); _type = type; } | |
| 551 | |
| 552 Range* first() const { return _first; } | |
| 553 int from() const { return _first->from(); } | |
| 554 int to() { if (_cached_to == -1) _cached_to = calc_to(); assert(_cached_to == calc_to(), "invalid cached value"); return _cached_to; } | |
| 555 int num_use_positions() const { return _use_pos_and_kinds.length() / 2; } | |
| 556 | |
| 557 Interval* next() const { return _next; } | |
| 558 Interval** next_addr() { return &_next; } | |
| 559 void set_next(Interval* next) { _next = next; } | |
| 560 | |
| 561 int assigned_reg() const { return _assigned_reg; } | |
| 562 int assigned_regHi() const { return _assigned_regHi; } | |
| 563 void assign_reg(int reg) { _assigned_reg = reg; _assigned_regHi = LinearScan::any_reg; } | |
| 564 void assign_reg(int reg,int regHi) { _assigned_reg = reg; _assigned_regHi = regHi; } | |
| 565 | |
| 566 Interval* register_hint(bool search_split_child = true) const; // calculation needed | |
| 567 void set_register_hint(Interval* i) { _register_hint = i; } | |
| 568 | |
| 569 int state() const { return _state; } | |
| 570 void set_state(IntervalState s) { _state = s; } | |
| 571 | |
| 572 // access to split parent and split children | |
| 573 bool is_split_parent() const { return _split_parent == this; } | |
| 574 bool is_split_child() const { return _split_parent != this; } | |
| 575 Interval* split_parent() const { assert(_split_parent->is_split_parent(), "must be"); return _split_parent; } | |
| 576 Interval* split_child_at_op_id(int op_id, LIR_OpVisitState::OprMode mode); | |
| 577 Interval* split_child_before_op_id(int op_id); | |
| 578 bool split_child_covers(int op_id, LIR_OpVisitState::OprMode mode); | |
| 579 DEBUG_ONLY(void check_split_children();) | |
| 580 | |
| 581 // information stored in split parent, but available for all children | |
| 582 int canonical_spill_slot() const { return split_parent()->_canonical_spill_slot; } | |
| 583 void set_canonical_spill_slot(int slot) { assert(split_parent()->_canonical_spill_slot == -1, "overwriting existing value"); split_parent()->_canonical_spill_slot = slot; } | |
| 584 Interval* current_split_child() const { return split_parent()->_current_split_child; } | |
| 585 void make_current_split_child() { split_parent()->_current_split_child = this; } | |
| 586 | |
| 587 bool insert_move_when_activated() const { return _insert_move_when_activated; } | |
| 588 void set_insert_move_when_activated(bool b) { _insert_move_when_activated = b; } | |
| 589 | |
| 590 // for spill optimization | |
| 591 IntervalSpillState spill_state() const { return split_parent()->_spill_state; } | |
| 592 int spill_definition_pos() const { return split_parent()->_spill_definition_pos; } | |
| 593 void set_spill_state(IntervalSpillState state) { assert(state >= spill_state(), "state cannot decrease"); split_parent()->_spill_state = state; } | |
| 594 void set_spill_definition_pos(int pos) { assert(spill_definition_pos() == -1, "cannot set the position twice"); split_parent()->_spill_definition_pos = pos; } | |
| 595 // returns true if this interval has a shadow copy on the stack that is always correct | |
| 596 bool always_in_memory() const { return split_parent()->_spill_state == storeAtDefinition || split_parent()->_spill_state == startInMemory; } | |
| 597 | |
| 598 // caching of values that take time to compute and are used multiple times | |
| 599 LIR_Opr cached_opr() const { return _cached_opr; } | |
| 600 VMReg cached_vm_reg() const { return _cached_vm_reg; } | |
| 601 void set_cached_opr(LIR_Opr opr) { _cached_opr = opr; } | |
| 602 void set_cached_vm_reg(VMReg reg) { _cached_vm_reg = reg; } | |
| 603 | |
| 604 // access to use positions | |
| 605 int first_usage(IntervalUseKind min_use_kind) const; // id of the first operation requiring this interval in a register | |
| 606 int next_usage(IntervalUseKind min_use_kind, int from) const; // id of next usage seen from the given position | |
| 607 int next_usage_exact(IntervalUseKind exact_use_kind, int from) const; | |
| 608 int previous_usage(IntervalUseKind min_use_kind, int from) const; | |
| 609 | |
| 610 // manipulating intervals | |
| 611 void add_use_pos(int pos, IntervalUseKind use_kind); | |
| 612 void add_range(int from, int to); | |
| 613 Interval* split(int split_pos); | |
| 614 Interval* split_from_start(int split_pos); | |
| 615 void remove_first_use_pos() { _use_pos_and_kinds.truncate(_use_pos_and_kinds.length() - 2); } | |
| 616 | |
| 617 // test intersection | |
| 618 bool covers(int op_id, LIR_OpVisitState::OprMode mode) const; | |
| 619 bool has_hole_between(int from, int to); | |
| 620 bool intersects(Interval* i) const { return _first->intersects(i->_first); } | |
| 621 int intersects_at(Interval* i) const { return _first->intersects_at(i->_first); } | |
| 622 | |
| 623 // range iteration | |
| 624 void rewind_range() { _current = _first; } | |
| 625 void next_range() { assert(this != _end, "not allowed on sentinel"); _current = _current->next(); } | |
| 626 int current_from() const { return _current->from(); } | |
| 627 int current_to() const { return _current->to(); } | |
| 628 bool current_at_end() const { return _current == Range::end(); } | |
| 629 bool current_intersects(Interval* it) { return _current->intersects(it->_current); }; | |
| 630 int current_intersects_at(Interval* it) { return _current->intersects_at(it->_current); }; | |
| 631 | |
| 632 // printing | |
| 633 void print(outputStream* out = tty) const PRODUCT_RETURN; | |
| 634 }; | |
| 635 | |
| 636 | |
| 637 class IntervalWalker : public CompilationResourceObj { | |
| 638 protected: | |
| 639 Compilation* _compilation; | |
| 640 LinearScan* _allocator; | |
| 641 | |
| 642 Interval* _unhandled_first[nofKinds]; // sorted list of intervals, not life before the current position | |
| 643 Interval* _active_first [nofKinds]; // sorted list of intervals, life at the current position | |
| 644 Interval* _inactive_first [nofKinds]; // sorted list of intervals, intervals in a life time hole at the current position | |
| 645 | |
| 646 Interval* _current; // the current interval coming from unhandled list | |
| 647 int _current_position; // the current position (intercept point through the intervals) | |
| 648 IntervalKind _current_kind; // and whether it is fixed_kind or any_kind. | |
| 649 | |
| 650 | |
| 651 Compilation* compilation() const { return _compilation; } | |
| 652 LinearScan* allocator() const { return _allocator; } | |
| 653 | |
| 654 // unified bailout support | |
| 655 void bailout(const char* msg) const { compilation()->bailout(msg); } | |
| 656 bool bailed_out() const { return compilation()->bailed_out(); } | |
| 657 | |
| 658 void check_bounds(IntervalKind kind) { assert(kind >= fixedKind && kind <= anyKind, "invalid interval_kind"); } | |
| 659 | |
| 660 Interval** unhandled_first_addr(IntervalKind kind) { check_bounds(kind); return &_unhandled_first[kind]; } | |
| 661 Interval** active_first_addr(IntervalKind kind) { check_bounds(kind); return &_active_first[kind]; } | |
| 662 Interval** inactive_first_addr(IntervalKind kind) { check_bounds(kind); return &_inactive_first[kind]; } | |
| 663 | |
| 664 void append_unsorted(Interval** first, Interval* interval); | |
| 665 void append_sorted(Interval** first, Interval* interval); | |
| 666 void append_to_unhandled(Interval** list, Interval* interval); | |
| 667 | |
| 668 bool remove_from_list(Interval** list, Interval* i); | |
| 669 void remove_from_list(Interval* i); | |
| 670 | |
| 671 void next_interval(); | |
| 672 Interval* current() const { return _current; } | |
| 673 IntervalKind current_kind() const { return _current_kind; } | |
| 674 | |
| 675 void walk_to(IntervalState state, int from); | |
| 676 | |
| 677 // activate_current() is called when an unhandled interval becomes active (in current(), current_kind()). | |
| 678 // Return false if current() should not be moved the the active interval list. | |
| 679 // It is safe to append current to any interval list but the unhandled list. | |
| 680 virtual bool activate_current() { return true; } | |
| 681 | |
| 682 // interval_moved() is called whenever an interval moves from one interval list to another. | |
| 683 // In the implementation of this method it is prohibited to move the interval to any list. | |
| 684 virtual void interval_moved(Interval* interval, IntervalKind kind, IntervalState from, IntervalState to); | |
| 685 | |
| 686 public: | |
| 687 IntervalWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first); | |
| 688 | |
| 689 Interval* unhandled_first(IntervalKind kind) { check_bounds(kind); return _unhandled_first[kind]; } | |
| 690 Interval* active_first(IntervalKind kind) { check_bounds(kind); return _active_first[kind]; } | |
| 691 Interval* inactive_first(IntervalKind kind) { check_bounds(kind); return _inactive_first[kind]; } | |
| 692 | |
| 693 // active contains the intervals that are live after the lir_op | |
| 694 void walk_to(int lir_op_id); | |
| 695 // active contains the intervals that are live before the lir_op | |
| 696 void walk_before(int lir_op_id) { walk_to(lir_op_id-1); } | |
| 697 // walk through all intervals | |
| 698 void walk() { walk_to(max_jint); } | |
| 699 | |
| 700 int current_position() { return _current_position; } | |
| 701 }; | |
| 702 | |
| 703 | |
| 704 // The actual linear scan register allocator | |
| 705 class LinearScanWalker : public IntervalWalker { | |
| 706 enum { | |
| 707 any_reg = LinearScan::any_reg | |
| 708 }; | |
| 709 | |
| 710 private: | |
| 711 int _first_reg; // the reg. number of the first phys. register | |
| 712 int _last_reg; // the reg. nmber of the last phys. register | |
| 713 int _num_phys_regs; // required by current interval | |
| 714 bool _adjacent_regs; // have lo/hi words of phys. regs be adjacent | |
| 715 | |
| 716 int _use_pos[LinearScan::nof_regs]; | |
| 717 int _block_pos[LinearScan::nof_regs]; | |
| 718 IntervalList* _spill_intervals[LinearScan::nof_regs]; | |
| 719 | |
| 720 MoveResolver _move_resolver; // for ordering spill moves | |
| 721 | |
| 722 // accessors mapped to same functions in class LinearScan | |
| 723 int block_count() const { return allocator()->block_count(); } | |
| 724 BlockBegin* block_at(int idx) const { return allocator()->block_at(idx); } | |
| 725 BlockBegin* block_of_op_with_id(int op_id) const { return allocator()->block_of_op_with_id(op_id); } | |
| 726 | |
| 727 void init_use_lists(bool only_process_use_pos); | |
| 728 void exclude_from_use(int reg); | |
| 729 void exclude_from_use(Interval* i); | |
| 730 void set_use_pos(int reg, Interval* i, int use_pos, bool only_process_use_pos); | |
| 731 void set_use_pos(Interval* i, int use_pos, bool only_process_use_pos); | |
| 732 void set_block_pos(int reg, Interval* i, int block_pos); | |
| 733 void set_block_pos(Interval* i, int block_pos); | |
| 734 | |
| 735 void free_exclude_active_fixed(); | |
| 736 void free_exclude_active_any(); | |
| 737 void free_collect_inactive_fixed(Interval* cur); | |
| 738 void free_collect_inactive_any(Interval* cur); | |
| 739 void free_collect_unhandled(IntervalKind kind, Interval* cur); | |
| 740 void spill_exclude_active_fixed(); | |
| 741 void spill_block_unhandled_fixed(Interval* cur); | |
| 742 void spill_block_inactive_fixed(Interval* cur); | |
| 743 void spill_collect_active_any(); | |
| 744 void spill_collect_inactive_any(Interval* cur); | |
| 745 | |
| 746 void insert_move(int op_id, Interval* src_it, Interval* dst_it); | |
| 747 int find_optimal_split_pos(BlockBegin* min_block, BlockBegin* max_block, int max_split_pos); | |
| 748 int find_optimal_split_pos(Interval* it, int min_split_pos, int max_split_pos, bool do_loop_optimization); | |
| 749 void split_before_usage(Interval* it, int min_split_pos, int max_split_pos); | |
| 750 void split_for_spilling(Interval* it); | |
| 751 void split_stack_interval(Interval* it); | |
| 752 void split_when_partial_register_available(Interval* it, int register_available_until); | |
| 753 void split_and_spill_interval(Interval* it); | |
| 754 | |
| 755 int find_free_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split); | |
| 756 int find_free_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split); | |
| 757 bool alloc_free_reg(Interval* cur); | |
| 758 | |
| 759 int find_locked_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split); | |
| 760 int find_locked_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split); | |
| 761 void split_and_spill_intersecting_intervals(int reg, int regHi); | |
| 762 void alloc_locked_reg(Interval* cur); | |
| 763 | |
| 764 bool no_allocation_possible(Interval* cur); | |
| 765 void update_phys_reg_range(bool requires_cpu_register); | |
| 766 void init_vars_for_alloc(Interval* cur); | |
| 767 bool pd_init_regs_for_alloc(Interval* cur); | |
| 768 | |
| 769 void combine_spilled_intervals(Interval* cur); | |
| 770 bool is_move(LIR_Op* op, Interval* from, Interval* to); | |
| 771 | |
| 772 bool activate_current(); | |
| 773 | |
| 774 public: | |
| 775 LinearScanWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first); | |
| 776 | |
| 777 // must be called when all intervals are allocated | |
| 778 void finish_allocation() { _move_resolver.resolve_and_append_moves(); } | |
| 779 }; | |
| 780 | |
| 781 | |
| 782 | |
| 783 /* | |
| 784 When a block has more than one predecessor, and all predecessors end with | |
| 785 the same sequence of move-instructions, than this moves can be placed once | |
| 786 at the beginning of the block instead of multiple times in the predecessors. | |
| 787 | |
| 788 Similarly, when a block has more than one successor, then equal sequences of | |
| 789 moves at the beginning of the successors can be placed once at the end of | |
| 790 the block. But because the moves must be inserted before all branch | |
| 791 instructions, this works only when there is exactly one conditional branch | |
| 792 at the end of the block (because the moves must be inserted before all | |
| 793 branches, but after all compares). | |
| 794 | |
| 795 This optimization affects all kind of moves (reg->reg, reg->stack and | |
| 796 stack->reg). Because this optimization works best when a block contains only | |
| 797 few moves, it has a huge impact on the number of blocks that are totally | |
| 798 empty. | |
| 799 */ | |
| 800 class EdgeMoveOptimizer : public StackObj { | |
| 801 private: | |
| 802 // the class maintains a list with all lir-instruction-list of the | |
| 803 // successors (predecessors) and the current index into the lir-lists | |
| 804 LIR_OpListStack _edge_instructions; | |
| 805 intStack _edge_instructions_idx; | |
| 806 | |
| 807 void init_instructions(); | |
| 808 void append_instructions(LIR_OpList* instructions, int instructions_idx); | |
| 809 LIR_Op* instruction_at(int edge); | |
| 810 void remove_cur_instruction(int edge, bool decrement_index); | |
| 811 | |
| 812 bool operations_different(LIR_Op* op1, LIR_Op* op2); | |
| 813 | |
| 814 void optimize_moves_at_block_end(BlockBegin* cur); | |
| 815 void optimize_moves_at_block_begin(BlockBegin* cur); | |
| 816 | |
| 817 EdgeMoveOptimizer(); | |
| 818 | |
| 819 public: | |
| 820 static void optimize(BlockList* code); | |
| 821 }; | |
| 822 | |
| 823 | |
| 824 | |
| 825 class ControlFlowOptimizer : public StackObj { | |
| 826 private: | |
| 827 BlockList _original_preds; | |
| 828 | |
| 829 enum { | |
| 830 ShortLoopSize = 5 | |
| 831 }; | |
| 832 void reorder_short_loop(BlockList* code, BlockBegin* header_block, int header_idx); | |
| 833 void reorder_short_loops(BlockList* code); | |
| 834 | |
| 835 bool can_delete_block(BlockBegin* cur); | |
| 836 void substitute_branch_target(BlockBegin* cur, BlockBegin* target_from, BlockBegin* target_to); | |
| 837 void delete_empty_blocks(BlockList* code); | |
| 838 | |
| 839 void delete_unnecessary_jumps(BlockList* code); | |
| 840 void delete_jumps_to_return(BlockList* code); | |
| 841 | |
| 842 DEBUG_ONLY(void verify(BlockList* code);) | |
| 843 | |
| 844 ControlFlowOptimizer(); | |
| 845 public: | |
| 846 static void optimize(BlockList* code); | |
| 847 }; | |
| 848 | |
| 849 | |
| 850 #ifndef PRODUCT | |
| 851 | |
| 852 // Helper class for collecting statistics of LinearScan | |
| 853 class LinearScanStatistic : public StackObj { | |
| 854 public: | |
| 855 enum Counter { | |
| 856 // general counters | |
| 857 counter_method, | |
| 858 counter_fpu_method, | |
| 859 counter_loop_method, | |
| 860 counter_exception_method, | |
| 861 counter_loop, | |
| 862 counter_block, | |
| 863 counter_loop_block, | |
| 864 counter_exception_block, | |
| 865 counter_interval, | |
| 866 counter_fixed_interval, | |
| 867 counter_range, | |
| 868 counter_fixed_range, | |
| 869 counter_use_pos, | |
| 870 counter_fixed_use_pos, | |
| 871 counter_spill_slots, | |
| 872 blank_line_1, | |
| 873 | |
| 874 // counter for classes of lir instructions | |
| 875 counter_instruction, | |
| 876 counter_label, | |
| 877 counter_entry, | |
| 878 counter_return, | |
| 879 counter_call, | |
| 880 counter_move, | |
| 881 counter_cmp, | |
| 882 counter_cond_branch, | |
| 883 counter_uncond_branch, | |
| 884 counter_stub_branch, | |
| 885 counter_alu, | |
| 886 counter_alloc, | |
| 887 counter_sync, | |
| 888 counter_throw, | |
| 889 counter_unwind, | |
| 890 counter_typecheck, | |
| 891 counter_fpu_stack, | |
| 892 counter_misc_inst, | |
| 893 counter_other_inst, | |
| 894 blank_line_2, | |
| 895 | |
| 896 // counter for different types of moves | |
| 897 counter_move_total, | |
| 898 counter_move_reg_reg, | |
| 899 counter_move_reg_stack, | |
| 900 counter_move_stack_reg, | |
| 901 counter_move_stack_stack, | |
| 902 counter_move_reg_mem, | |
| 903 counter_move_mem_reg, | |
| 904 counter_move_const_any, | |
| 905 | |
| 906 number_of_counters, | |
| 907 invalid_counter = -1 | |
| 908 }; | |
| 909 | |
| 910 private: | |
| 911 int _counters_sum[number_of_counters]; | |
| 912 int _counters_max[number_of_counters]; | |
| 913 | |
| 914 void inc_counter(Counter idx, int value = 1) { _counters_sum[idx] += value; } | |
| 915 | |
| 916 const char* counter_name(int counter_idx); | |
| 917 Counter base_counter(int counter_idx); | |
| 918 | |
| 919 void sum_up(LinearScanStatistic &method_statistic); | |
| 920 void collect(LinearScan* allocator); | |
| 921 | |
| 922 public: | |
| 923 LinearScanStatistic(); | |
| 924 void print(const char* title); | |
| 925 static void compute(LinearScan* allocator, LinearScanStatistic &global_statistic); | |
| 926 }; | |
| 927 | |
| 928 | |
| 929 // Helper class for collecting compilation time of LinearScan | |
| 930 class LinearScanTimers : public StackObj { | |
| 931 public: | |
| 932 enum Timer { | |
| 933 timer_do_nothing, | |
| 934 timer_number_instructions, | |
| 935 timer_compute_local_live_sets, | |
| 936 timer_compute_global_live_sets, | |
| 937 timer_build_intervals, | |
| 938 timer_sort_intervals_before, | |
| 939 timer_allocate_registers, | |
| 940 timer_resolve_data_flow, | |
| 941 timer_sort_intervals_after, | |
| 942 timer_eliminate_spill_moves, | |
| 943 timer_assign_reg_num, | |
| 944 timer_allocate_fpu_stack, | |
| 945 timer_optimize_lir, | |
| 946 | |
| 947 number_of_timers | |
| 948 }; | |
| 949 | |
| 950 private: | |
| 951 elapsedTimer _timers[number_of_timers]; | |
| 952 const char* timer_name(int idx); | |
| 953 | |
| 954 public: | |
| 955 LinearScanTimers(); | |
| 956 | |
| 957 void begin_method(); // called for each method when register allocation starts | |
| 958 void end_method(LinearScan* allocator); // called for each method when register allocation completed | |
| 959 void print(double total_time); // called before termination of VM to print global summary | |
| 960 | |
| 961 elapsedTimer* timer(int idx) { return &(_timers[idx]); } | |
| 962 }; | |
| 963 | |
| 964 | |
| 965 #endif // ifndef PRODUCT | |
| 966 | |
| 967 | |
| 968 // Pick up platform-dependent implementation details | |
| 1972 | 969 #ifdef TARGET_ARCH_x86 |
| 970 # include "c1_LinearScan_x86.hpp" | |
| 971 #endif | |
| 972 #ifdef TARGET_ARCH_sparc | |
| 973 # include "c1_LinearScan_sparc.hpp" | |
| 974 #endif | |
|
2192
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975 #ifdef TARGET_ARCH_arm |
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976 # include "c1_LinearScan_arm.hpp" |
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977 #endif |
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978 #ifdef TARGET_ARCH_ppc |
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979 # include "c1_LinearScan_ppc.hpp" |
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980 #endif |
| 1972 | 981 |
| 982 | |
| 983 #endif // SHARE_VM_C1_C1_LINEARSCAN_HPP |