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annotate src/cpu/sparc/vm/sparc.ad @ 1552:c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
Summary: Change all the Sun copyrights to Oracle copyright
Reviewed-by: ohair
| author | trims |
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| date | Thu, 27 May 2010 19:08:38 -0700 |
| parents | d7f654633cfe |
| children | e9ff18c4ace7 |
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| 0 | 1 // |
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2 // Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 // | |
| 5 // This code is free software; you can redistribute it and/or modify it | |
| 6 // under the terms of the GNU General Public License version 2 only, as | |
| 7 // published by the Free Software Foundation. | |
| 8 // | |
| 9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 // version 2 for more details (a copy is included in the LICENSE file that | |
| 13 // accompanied this code). | |
| 14 // | |
| 15 // You should have received a copy of the GNU General Public License version | |
| 16 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 // | |
|
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19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 // or visit www.oracle.com if you need additional information or have any |
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21 // questions. |
| 0 | 22 // |
| 23 // | |
| 24 | |
| 25 // SPARC Architecture Description File | |
| 26 | |
| 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
| 28 // This information is used by the matcher and the register allocator to | |
| 29 // describe individual registers and classes of registers within the target | |
| 30 // archtecture. | |
| 31 register %{ | |
| 32 //----------Architecture Description Register Definitions---------------------- | |
| 33 // General Registers | |
| 34 // "reg_def" name ( register save type, C convention save type, | |
| 35 // ideal register type, encoding, vm name ); | |
| 36 // Register Save Types: | |
| 37 // | |
| 38 // NS = No-Save: The register allocator assumes that these registers | |
| 39 // can be used without saving upon entry to the method, & | |
| 40 // that they do not need to be saved at call sites. | |
| 41 // | |
| 42 // SOC = Save-On-Call: The register allocator assumes that these registers | |
| 43 // can be used without saving upon entry to the method, | |
| 44 // but that they must be saved at call sites. | |
| 45 // | |
| 46 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
| 47 // must be saved before using them upon entry to the | |
| 48 // method, but they do not need to be saved at call | |
| 49 // sites. | |
| 50 // | |
| 51 // AS = Always-Save: The register allocator assumes that these registers | |
| 52 // must be saved before using them upon entry to the | |
| 53 // method, & that they must be saved at call sites. | |
| 54 // | |
| 55 // Ideal Register Type is used to determine how to save & restore a | |
| 56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
| 57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
| 58 // | |
| 59 // The encoding number is the actual bit-pattern placed into the opcodes. | |
| 60 | |
| 61 | |
| 62 // ---------------------------- | |
| 63 // Integer/Long Registers | |
| 64 // ---------------------------- | |
| 65 | |
| 66 // Need to expose the hi/lo aspect of 64-bit registers | |
| 67 // This register set is used for both the 64-bit build and | |
| 68 // the 32-bit build with 1-register longs. | |
| 69 | |
| 70 // Global Registers 0-7 | |
| 71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next()); | |
| 72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg()); | |
| 73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next()); | |
| 74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg()); | |
| 75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next()); | |
| 76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg()); | |
| 77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next()); | |
| 78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg()); | |
| 79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next()); | |
| 80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg()); | |
| 81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next()); | |
| 82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg()); | |
| 83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next()); | |
| 84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg()); | |
| 85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next()); | |
| 86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg()); | |
| 87 | |
| 88 // Output Registers 0-7 | |
| 89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next()); | |
| 90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg()); | |
| 91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next()); | |
| 92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg()); | |
| 93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next()); | |
| 94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg()); | |
| 95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next()); | |
| 96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg()); | |
| 97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next()); | |
| 98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg()); | |
| 99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next()); | |
| 100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg()); | |
| 101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next()); | |
| 102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg()); | |
| 103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next()); | |
| 104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg()); | |
| 105 | |
| 106 // Local Registers 0-7 | |
| 107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next()); | |
| 108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg()); | |
| 109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next()); | |
| 110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg()); | |
| 111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next()); | |
| 112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg()); | |
| 113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next()); | |
| 114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg()); | |
| 115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next()); | |
| 116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg()); | |
| 117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next()); | |
| 118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg()); | |
| 119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next()); | |
| 120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg()); | |
| 121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next()); | |
| 122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg()); | |
| 123 | |
| 124 // Input Registers 0-7 | |
| 125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next()); | |
| 126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg()); | |
| 127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next()); | |
| 128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg()); | |
| 129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next()); | |
| 130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg()); | |
| 131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next()); | |
| 132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg()); | |
| 133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next()); | |
| 134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg()); | |
| 135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next()); | |
| 136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg()); | |
| 137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next()); | |
| 138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg()); | |
| 139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next()); | |
| 140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg()); | |
| 141 | |
| 142 // ---------------------------- | |
| 143 // Float/Double Registers | |
| 144 // ---------------------------- | |
| 145 | |
| 146 // Float Registers | |
| 147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()); | |
| 148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()); | |
| 149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()); | |
| 150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()); | |
| 151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()); | |
| 152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()); | |
| 153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()); | |
| 154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()); | |
| 155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()); | |
| 156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()); | |
| 157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg()); | |
| 158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg()); | |
| 159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg()); | |
| 160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg()); | |
| 161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg()); | |
| 162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg()); | |
| 163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg()); | |
| 164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg()); | |
| 165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg()); | |
| 166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg()); | |
| 167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg()); | |
| 168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg()); | |
| 169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg()); | |
| 170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg()); | |
| 171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg()); | |
| 172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg()); | |
| 173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg()); | |
| 174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg()); | |
| 175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg()); | |
| 176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg()); | |
| 177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg()); | |
| 178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg()); | |
| 179 | |
| 180 // Double Registers | |
| 181 // The rules of ADL require that double registers be defined in pairs. | |
| 182 // Each pair must be two 32-bit values, but not necessarily a pair of | |
| 183 // single float registers. In each pair, ADLC-assigned register numbers | |
| 184 // must be adjacent, with the lower number even. Finally, when the | |
| 185 // CPU stores such a register pair to memory, the word associated with | |
| 186 // the lower ADLC-assigned number must be stored to the lower address. | |
| 187 | |
| 188 // These definitions specify the actual bit encodings of the sparc | |
| 189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp | |
| 190 // wants 0-63, so we have to convert every time we want to use fp regs | |
| 191 // with the macroassembler, using reg_to_DoubleFloatRegister_object(). | |
| 605 | 192 // 255 is a flag meaning "don't go here". |
| 0 | 193 // I believe we can't handle callee-save doubles D32 and up until |
| 194 // the place in the sparc stack crawler that asserts on the 255 is | |
| 195 // fixed up. | |
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196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()); |
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197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next()); |
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198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()); |
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199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next()); |
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200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()); |
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201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next()); |
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202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()); |
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203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next()); |
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204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()); |
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205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next()); |
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206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()); |
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207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next()); |
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208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()); |
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209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next()); |
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210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()); |
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211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next()); |
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212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()); |
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213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next()); |
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214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()); |
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215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next()); |
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216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()); |
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217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next()); |
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218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()); |
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219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next()); |
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220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()); |
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221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next()); |
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222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()); |
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223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next()); |
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224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()); |
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225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next()); |
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226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()); |
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227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next()); |
| 0 | 228 |
| 229 | |
| 230 // ---------------------------- | |
| 231 // Special Registers | |
| 232 // Condition Codes Flag Registers | |
| 233 // I tried to break out ICC and XCC but it's not very pretty. | |
| 234 // Every Sparc instruction which defs/kills one also kills the other. | |
| 235 // Hence every compare instruction which defs one kind of flags ends | |
| 236 // up needing a kill of the other. | |
| 237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
| 238 | |
| 239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
| 240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad()); | |
| 241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad()); | |
| 242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad()); | |
| 243 | |
| 244 // ---------------------------- | |
| 245 // Specify the enum values for the registers. These enums are only used by the | |
| 246 // OptoReg "class". We can convert these enum values at will to VMReg when needed | |
| 247 // for visibility to the rest of the vm. The order of this enum influences the | |
| 248 // register allocator so having the freedom to set this order and not be stuck | |
| 249 // with the order that is natural for the rest of the vm is worth it. | |
| 250 alloc_class chunk0( | |
| 251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H, | |
| 252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H, | |
| 253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H, | |
| 254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H); | |
| 255 | |
| 256 // Note that a register is not allocatable unless it is also mentioned | |
| 257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg. | |
| 258 | |
| 259 alloc_class chunk1( | |
| 260 // The first registers listed here are those most likely to be used | |
| 261 // as temporaries. We move F0..F7 away from the front of the list, | |
| 262 // to reduce the likelihood of interferences with parameters and | |
| 263 // return values. Likewise, we avoid using F0/F1 for parameters, | |
| 264 // since they are used for return values. | |
| 265 // This FPU fine-tuning is worth about 1% on the SPEC geomean. | |
| 266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
| 267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23, | |
| 268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31, | |
| 269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values | |
| 270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x, | |
| 271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
| 272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x, | |
| 273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x); | |
| 274 | |
| 275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3); | |
| 276 | |
| 277 //----------Architecture Description Register Classes-------------------------- | |
| 278 // Several register classes are automatically defined based upon information in | |
| 279 // this architecture description. | |
| 280 // 1) reg_class inline_cache_reg ( as defined in frame section ) | |
| 281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) | |
| 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
| 283 // | |
| 284 | |
| 285 // G0 is not included in integer class since it has special meaning. | |
| 286 reg_class g0_reg(R_G0); | |
| 287 | |
| 288 // ---------------------------- | |
| 289 // Integer Register Classes | |
| 290 // ---------------------------- | |
| 291 // Exclusions from i_reg: | |
| 292 // R_G0: hardwired zero | |
| 293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java) | |
| 294 // R_G6: reserved by Solaris ABI to tools | |
| 295 // R_G7: reserved by Solaris ABI to libthread | |
| 296 // R_O7: Used as a temp in many encodings | |
| 297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 298 | |
| 299 // Class for all integer registers, except the G registers. This is used for | |
| 300 // encodings which use G registers as temps. The regular inputs to such | |
| 301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator | |
| 302 // will not put an input into a temp register. | |
| 303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 304 | |
| 305 reg_class g1_regI(R_G1); | |
| 306 reg_class g3_regI(R_G3); | |
| 307 reg_class g4_regI(R_G4); | |
| 308 reg_class o0_regI(R_O0); | |
| 309 reg_class o7_regI(R_O7); | |
| 310 | |
| 311 // ---------------------------- | |
| 312 // Pointer Register Classes | |
| 313 // ---------------------------- | |
| 314 #ifdef _LP64 | |
| 315 // 64-bit build means 64-bit pointers means hi/lo pairs | |
| 316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
| 317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
| 318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
| 319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
| 320 // Lock encodings use G3 and G4 internally | |
| 321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5, | |
| 322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
| 323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
| 324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
| 325 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
| 326 // It is also used for memory addressing, allowing direct TLS addressing. | |
| 327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
| 328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP, | |
| 329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
| 330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP ); | |
| 331 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
| 332 // We use it to save R_G2 across calls out of Java. | |
| 333 reg_class l7_regP(R_L7H,R_L7); | |
| 334 | |
| 335 // Other special pointer regs | |
| 336 reg_class g1_regP(R_G1H,R_G1); | |
| 337 reg_class g2_regP(R_G2H,R_G2); | |
| 338 reg_class g3_regP(R_G3H,R_G3); | |
| 339 reg_class g4_regP(R_G4H,R_G4); | |
| 340 reg_class g5_regP(R_G5H,R_G5); | |
| 341 reg_class i0_regP(R_I0H,R_I0); | |
| 342 reg_class o0_regP(R_O0H,R_O0); | |
| 343 reg_class o1_regP(R_O1H,R_O1); | |
| 344 reg_class o2_regP(R_O2H,R_O2); | |
| 345 reg_class o7_regP(R_O7H,R_O7); | |
| 346 | |
| 347 #else // _LP64 | |
| 348 // 32-bit build means 32-bit pointers means 1 register. | |
| 349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5, | |
| 350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
| 351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
| 352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 353 // Lock encodings use G3 and G4 internally | |
| 354 reg_class lock_ptr_reg(R_G1, R_G5, | |
| 355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
| 356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
| 357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
| 358 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
| 359 // It is also used for memory addressing, allowing direct TLS addressing. | |
| 360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5, | |
| 361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP, | |
| 362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
| 363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP); | |
| 364 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
| 365 // We use it to save R_G2 across calls out of Java. | |
| 366 reg_class l7_regP(R_L7); | |
| 367 | |
| 368 // Other special pointer regs | |
| 369 reg_class g1_regP(R_G1); | |
| 370 reg_class g2_regP(R_G2); | |
| 371 reg_class g3_regP(R_G3); | |
| 372 reg_class g4_regP(R_G4); | |
| 373 reg_class g5_regP(R_G5); | |
| 374 reg_class i0_regP(R_I0); | |
| 375 reg_class o0_regP(R_O0); | |
| 376 reg_class o1_regP(R_O1); | |
| 377 reg_class o2_regP(R_O2); | |
| 378 reg_class o7_regP(R_O7); | |
| 379 #endif // _LP64 | |
| 380 | |
| 381 | |
| 382 // ---------------------------- | |
| 383 // Long Register Classes | |
| 384 // ---------------------------- | |
| 385 // Longs in 1 register. Aligned adjacent hi/lo pairs. | |
| 386 // Note: O7 is never in this class; it is sometimes used as an encoding temp. | |
| 387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5 | |
| 388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5 | |
| 389 #ifdef _LP64 | |
| 390 // 64-bit, longs in 1 register: use all 64-bit integer registers | |
| 391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's. | |
| 392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7 | |
| 393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 | |
| 394 #endif // _LP64 | |
| 395 ); | |
| 396 | |
| 397 reg_class g1_regL(R_G1H,R_G1); | |
|
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398 reg_class g3_regL(R_G3H,R_G3); |
| 0 | 399 reg_class o2_regL(R_O2H,R_O2); |
| 400 reg_class o7_regL(R_O7H,R_O7); | |
| 401 | |
| 402 // ---------------------------- | |
| 403 // Special Class for Condition Code Flags Register | |
| 404 reg_class int_flags(CCR); | |
| 405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3); | |
| 406 reg_class float_flag0(FCC0); | |
| 407 | |
| 408 | |
| 409 // ---------------------------- | |
| 410 // Float Point Register Classes | |
| 411 // ---------------------------- | |
| 412 // Skip F30/F31, they are reserved for mem-mem copies | |
| 413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); | |
| 414 | |
| 415 // Paired floating point registers--they show up in the same order as the floats, | |
| 416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
| 417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
| 418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29, | |
| 419 /* Use extra V9 double registers; this AD file does not support V8 */ | |
| 420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
| 421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x | |
| 422 ); | |
| 423 | |
| 424 // Paired floating point registers--they show up in the same order as the floats, | |
| 425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
| 426 // This class is usable for mis-aligned loads as happen in I2C adapters. | |
| 427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
| 428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31 ); | |
| 429 %} | |
| 430 | |
| 431 //----------DEFINITION BLOCK--------------------------------------------------- | |
| 432 // Define name --> value mappings to inform the ADLC of an integer valued name | |
| 433 // Current support includes integer values in the range [0, 0x7FFFFFFF] | |
| 434 // Format: | |
| 435 // int_def <name> ( <int_value>, <expression>); | |
| 436 // Generated Code in ad_<arch>.hpp | |
| 437 // #define <name> (<expression>) | |
| 438 // // value == <int_value> | |
| 439 // Generated code in ad_<arch>.cpp adlc_verification() | |
| 440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); | |
| 441 // | |
| 442 definitions %{ | |
| 443 // The default cost (of an ALU instruction). | |
| 444 int_def DEFAULT_COST ( 100, 100); | |
| 445 int_def HUGE_COST (1000000, 1000000); | |
| 446 | |
| 447 // Memory refs are twice as expensive as run-of-the-mill. | |
| 448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2); | |
| 449 | |
| 450 // Branches are even more expensive. | |
| 451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3); | |
| 452 int_def CALL_COST ( 300, DEFAULT_COST * 3); | |
| 453 %} | |
| 454 | |
| 455 | |
| 456 //----------SOURCE BLOCK------------------------------------------------------- | |
| 457 // This is a block of C++ code which provides values, functions, and | |
| 458 // definitions necessary in the rest of the architecture description | |
| 459 source_hpp %{ | |
| 460 // Must be visible to the DFA in dfa_sparc.cpp | |
| 461 extern bool can_branch_register( Node *bol, Node *cmp ); | |
| 462 | |
| 463 // Macros to extract hi & lo halves from a long pair. | |
| 464 // G0 is not part of any long pair, so assert on that. | |
| 605 | 465 // Prevents accidentally using G1 instead of G0. |
| 0 | 466 #define LONG_HI_REG(x) (x) |
| 467 #define LONG_LO_REG(x) (x) | |
| 468 | |
| 469 %} | |
| 470 | |
| 471 source %{ | |
| 472 #define __ _masm. | |
| 473 | |
|
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474 // Block initializing store |
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475 #define ASI_BLK_INIT_QUAD_LDD_P 0xE2 |
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476 |
| 0 | 477 // tertiary op of a LoadP or StoreP encoding |
| 478 #define REGP_OP true | |
| 479 | |
| 480 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding); | |
| 481 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding); | |
| 482 static Register reg_to_register_object(int register_encoding); | |
| 483 | |
| 484 // Used by the DFA in dfa_sparc.cpp. | |
| 485 // Check for being able to use a V9 branch-on-register. Requires a | |
| 486 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign- | |
| 487 // extended. Doesn't work following an integer ADD, for example, because of | |
| 488 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On | |
| 489 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and | |
| 490 // replace them with zero, which could become sign-extension in a different OS | |
| 491 // release. There's no obvious reason why an interrupt will ever fill these | |
| 492 // bits with non-zero junk (the registers are reloaded with standard LD | |
| 493 // instructions which either zero-fill or sign-fill). | |
| 494 bool can_branch_register( Node *bol, Node *cmp ) { | |
| 495 if( !BranchOnRegister ) return false; | |
| 496 #ifdef _LP64 | |
| 497 if( cmp->Opcode() == Op_CmpP ) | |
| 498 return true; // No problems with pointer compares | |
| 499 #endif | |
| 500 if( cmp->Opcode() == Op_CmpL ) | |
| 501 return true; // No problems with long compares | |
| 502 | |
| 503 if( !SparcV9RegsHiBitsZero ) return false; | |
| 504 if( bol->as_Bool()->_test._test != BoolTest::ne && | |
| 505 bol->as_Bool()->_test._test != BoolTest::eq ) | |
| 506 return false; | |
| 507 | |
| 508 // Check for comparing against a 'safe' value. Any operation which | |
| 509 // clears out the high word is safe. Thus, loads and certain shifts | |
| 510 // are safe, as are non-negative constants. Any operation which | |
| 511 // preserves zero bits in the high word is safe as long as each of its | |
| 512 // inputs are safe. Thus, phis and bitwise booleans are safe if their | |
| 513 // inputs are safe. At present, the only important case to recognize | |
| 514 // seems to be loads. Constants should fold away, and shifts & | |
| 515 // logicals can use the 'cc' forms. | |
| 516 Node *x = cmp->in(1); | |
| 517 if( x->is_Load() ) return true; | |
| 518 if( x->is_Phi() ) { | |
| 519 for( uint i = 1; i < x->req(); i++ ) | |
| 520 if( !x->in(i)->is_Load() ) | |
| 521 return false; | |
| 522 return true; | |
| 523 } | |
| 524 return false; | |
| 525 } | |
| 526 | |
| 527 // **************************************************************************** | |
| 528 | |
| 529 // REQUIRED FUNCTIONALITY | |
| 530 | |
| 531 // !!!!! Special hack to get all type of calls to specify the byte offset | |
| 532 // from the start of the call to the point where the return address | |
| 533 // will point. | |
| 534 // The "return address" is the address of the call instruction, plus 8. | |
| 535 | |
| 536 int MachCallStaticJavaNode::ret_addr_offset() { | |
| 537 return NativeCall::instruction_size; // call; delay slot | |
| 538 } | |
| 539 | |
| 540 int MachCallDynamicJavaNode::ret_addr_offset() { | |
| 541 int vtable_index = this->_vtable_index; | |
| 542 if (vtable_index < 0) { | |
| 543 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
| 544 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); | |
| 545 return (NativeMovConstReg::instruction_size + | |
| 546 NativeCall::instruction_size); // sethi; setlo; call; delay slot | |
| 547 } else { | |
| 548 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
| 549 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); | |
| 550 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); | |
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551 int klass_load_size; |
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552 if (UseCompressedOops) { |
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553 assert(Universe::heap() != NULL, "java heap should be initialized"); |
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554 if (Universe::narrow_oop_base() == NULL) |
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555 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass() |
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556 else |
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557 klass_load_size = 3*BytesPerInstWord; |
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558 } else { |
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559 klass_load_size = 1*BytesPerInstWord; |
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560 } |
| 0 | 561 if( Assembler::is_simm13(v_off) ) { |
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562 return klass_load_size + |
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563 (2*BytesPerInstWord + // ld_ptr, ld_ptr |
| 0 | 564 NativeCall::instruction_size); // call; delay slot |
| 565 } else { | |
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566 return klass_load_size + |
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567 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr |
| 0 | 568 NativeCall::instruction_size); // call; delay slot |
| 569 } | |
| 570 } | |
| 571 } | |
| 572 | |
| 573 int MachCallRuntimeNode::ret_addr_offset() { | |
| 574 #ifdef _LP64 | |
| 575 return NativeFarCall::instruction_size; // farcall; delay slot | |
| 576 #else | |
| 577 return NativeCall::instruction_size; // call; delay slot | |
| 578 #endif | |
| 579 } | |
| 580 | |
| 581 // Indicate if the safepoint node needs the polling page as an input. | |
| 582 // Since Sparc does not have absolute addressing, it does. | |
| 583 bool SafePointNode::needs_polling_address_input() { | |
| 584 return true; | |
| 585 } | |
| 586 | |
| 587 // emit an interrupt that is caught by the debugger (for debugging compiler) | |
| 588 void emit_break(CodeBuffer &cbuf) { | |
| 589 MacroAssembler _masm(&cbuf); | |
| 590 __ breakpoint_trap(); | |
| 591 } | |
| 592 | |
| 593 #ifndef PRODUCT | |
| 594 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
| 595 st->print("TA"); | |
| 596 } | |
| 597 #endif | |
| 598 | |
| 599 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 600 emit_break(cbuf); | |
| 601 } | |
| 602 | |
| 603 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { | |
| 604 return MachNode::size(ra_); | |
| 605 } | |
| 606 | |
| 607 // Traceable jump | |
| 608 void emit_jmpl(CodeBuffer &cbuf, int jump_target) { | |
| 609 MacroAssembler _masm(&cbuf); | |
| 610 Register rdest = reg_to_register_object(jump_target); | |
| 611 __ JMP(rdest, 0); | |
| 612 __ delayed()->nop(); | |
| 613 } | |
| 614 | |
| 615 // Traceable jump and set exception pc | |
| 616 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) { | |
| 617 MacroAssembler _masm(&cbuf); | |
| 618 Register rdest = reg_to_register_object(jump_target); | |
| 619 __ JMP(rdest, 0); | |
| 620 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc ); | |
| 621 } | |
| 622 | |
| 623 void emit_nop(CodeBuffer &cbuf) { | |
| 624 MacroAssembler _masm(&cbuf); | |
| 625 __ nop(); | |
| 626 } | |
| 627 | |
| 628 void emit_illtrap(CodeBuffer &cbuf) { | |
| 629 MacroAssembler _masm(&cbuf); | |
| 630 __ illtrap(0); | |
| 631 } | |
| 632 | |
| 633 | |
| 634 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) { | |
| 635 assert(n->rule() != loadUB_rule, ""); | |
| 636 | |
| 637 intptr_t offset = 0; | |
| 638 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP | |
| 639 const Node* addr = n->get_base_and_disp(offset, adr_type); | |
| 640 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP"); | |
| 641 assert(addr != NULL && addr != (Node*)-1, "invalid addr"); | |
| 642 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
| 643 atype = atype->add_offset(offset); | |
| 644 assert(disp32 == offset, "wrong disp32"); | |
| 645 return atype->_offset; | |
| 646 } | |
| 647 | |
| 648 | |
| 649 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) { | |
| 650 assert(n->rule() != loadUB_rule, ""); | |
| 651 | |
| 652 intptr_t offset = 0; | |
| 653 Node* addr = n->in(2); | |
| 654 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
| 655 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) { | |
| 656 Node* a = addr->in(2/*AddPNode::Address*/); | |
| 657 Node* o = addr->in(3/*AddPNode::Offset*/); | |
| 658 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot; | |
| 659 atype = a->bottom_type()->is_ptr()->add_offset(offset); | |
| 660 assert(atype->isa_oop_ptr(), "still an oop"); | |
| 661 } | |
| 662 offset = atype->is_ptr()->_offset; | |
| 663 if (offset != Type::OffsetBot) offset += disp32; | |
| 664 return offset; | |
| 665 } | |
| 666 | |
| 667 // Standard Sparc opcode form2 field breakdown | |
| 668 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) { | |
| 669 f0 &= (1<<19)-1; // Mask displacement to 19 bits | |
| 670 int op = (f30 << 30) | | |
| 671 (f29 << 29) | | |
| 672 (f25 << 25) | | |
| 673 (f22 << 22) | | |
| 674 (f20 << 20) | | |
| 675 (f19 << 19) | | |
| 676 (f0 << 0); | |
| 677 *((int*)(cbuf.code_end())) = op; | |
| 678 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 679 } | |
| 680 | |
| 681 // Standard Sparc opcode form2 field breakdown | |
| 682 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) { | |
| 683 f0 >>= 10; // Drop 10 bits | |
| 684 f0 &= (1<<22)-1; // Mask displacement to 22 bits | |
| 685 int op = (f30 << 30) | | |
| 686 (f25 << 25) | | |
| 687 (f22 << 22) | | |
| 688 (f0 << 0); | |
| 689 *((int*)(cbuf.code_end())) = op; | |
| 690 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 691 } | |
| 692 | |
| 693 // Standard Sparc opcode form3 field breakdown | |
| 694 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) { | |
| 695 int op = (f30 << 30) | | |
| 696 (f25 << 25) | | |
| 697 (f19 << 19) | | |
| 698 (f14 << 14) | | |
| 699 (f5 << 5) | | |
| 700 (f0 << 0); | |
| 701 *((int*)(cbuf.code_end())) = op; | |
| 702 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 703 } | |
| 704 | |
| 705 // Standard Sparc opcode form3 field breakdown | |
| 706 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) { | |
| 707 simm13 &= (1<<13)-1; // Mask to 13 bits | |
| 708 int op = (f30 << 30) | | |
| 709 (f25 << 25) | | |
| 710 (f19 << 19) | | |
| 711 (f14 << 14) | | |
| 712 (1 << 13) | // bit to indicate immediate-mode | |
| 713 (simm13<<0); | |
| 714 *((int*)(cbuf.code_end())) = op; | |
| 715 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 716 } | |
| 717 | |
| 718 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) { | |
| 719 simm10 &= (1<<10)-1; // Mask to 10 bits | |
| 720 emit3_simm13(cbuf,f30,f25,f19,f14,simm10); | |
| 721 } | |
| 722 | |
| 723 #ifdef ASSERT | |
| 724 // Helper function for VerifyOops in emit_form3_mem_reg | |
| 725 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) { | |
| 726 warning("VerifyOops encountered unexpected instruction:"); | |
| 727 n->dump(2); | |
| 728 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); | |
| 729 } | |
| 730 #endif | |
| 731 | |
| 732 | |
| 733 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary, | |
| 734 int src1_enc, int disp32, int src2_enc, int dst_enc) { | |
| 735 | |
| 736 #ifdef ASSERT | |
| 737 // The following code implements the +VerifyOops feature. | |
| 738 // It verifies oop values which are loaded into or stored out of | |
| 739 // the current method activation. +VerifyOops complements techniques | |
| 740 // like ScavengeALot, because it eagerly inspects oops in transit, | |
| 741 // as they enter or leave the stack, as opposed to ScavengeALot, | |
| 742 // which inspects oops "at rest", in the stack or heap, at safepoints. | |
| 743 // For this reason, +VerifyOops can sometimes detect bugs very close | |
| 744 // to their point of creation. It can also serve as a cross-check | |
| 745 // on the validity of oop maps, when used toegether with ScavengeALot. | |
| 746 | |
| 747 // It would be good to verify oops at other points, especially | |
| 748 // when an oop is used as a base pointer for a load or store. | |
| 749 // This is presently difficult, because it is hard to know when | |
| 750 // a base address is biased or not. (If we had such information, | |
| 751 // it would be easy and useful to make a two-argument version of | |
| 752 // verify_oop which unbiases the base, and performs verification.) | |
| 753 | |
| 754 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary"); | |
| 755 bool is_verified_oop_base = false; | |
| 756 bool is_verified_oop_load = false; | |
| 757 bool is_verified_oop_store = false; | |
| 758 int tmp_enc = -1; | |
| 759 if (VerifyOops && src1_enc != R_SP_enc) { | |
| 760 // classify the op, mainly for an assert check | |
| 761 int st_op = 0, ld_op = 0; | |
| 762 switch (primary) { | |
| 763 case Assembler::stb_op3: st_op = Op_StoreB; break; | |
| 764 case Assembler::sth_op3: st_op = Op_StoreC; break; | |
| 765 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0 | |
| 766 case Assembler::stw_op3: st_op = Op_StoreI; break; | |
| 767 case Assembler::std_op3: st_op = Op_StoreL; break; | |
| 768 case Assembler::stf_op3: st_op = Op_StoreF; break; | |
| 769 case Assembler::stdf_op3: st_op = Op_StoreD; break; | |
| 770 | |
| 771 case Assembler::ldsb_op3: ld_op = Op_LoadB; break; | |
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772 case Assembler::lduh_op3: ld_op = Op_LoadUS; break; |
| 0 | 773 case Assembler::ldsh_op3: ld_op = Op_LoadS; break; |
| 774 case Assembler::ldx_op3: // may become LoadP or stay LoadI | |
| 775 case Assembler::ldsw_op3: // may become LoadP or stay LoadI | |
| 776 case Assembler::lduw_op3: ld_op = Op_LoadI; break; | |
| 777 case Assembler::ldd_op3: ld_op = Op_LoadL; break; | |
| 778 case Assembler::ldf_op3: ld_op = Op_LoadF; break; | |
| 779 case Assembler::lddf_op3: ld_op = Op_LoadD; break; | |
| 780 case Assembler::ldub_op3: ld_op = Op_LoadB; break; | |
| 781 case Assembler::prefetch_op3: ld_op = Op_LoadI; break; | |
| 782 | |
| 783 default: ShouldNotReachHere(); | |
| 784 } | |
| 785 if (tertiary == REGP_OP) { | |
| 786 if (st_op == Op_StoreI) st_op = Op_StoreP; | |
| 787 else if (ld_op == Op_LoadI) ld_op = Op_LoadP; | |
| 788 else ShouldNotReachHere(); | |
| 789 if (st_op) { | |
| 790 // a store | |
| 791 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
| 792 Node* n2 = n->in(3); | |
| 793 if (n2 != NULL) { | |
| 794 const Type* t = n2->bottom_type(); | |
| 795 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
| 796 } | |
| 797 } else { | |
| 798 // a load | |
| 799 const Type* t = n->bottom_type(); | |
| 800 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
| 801 } | |
| 802 } | |
| 803 | |
| 804 if (ld_op) { | |
| 805 // a Load | |
| 806 // inputs are (0:control, 1:memory, 2:address) | |
| 807 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases | |
| 808 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) && | |
| 809 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) && | |
| 810 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) && | |
| 811 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) && | |
| 812 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) && | |
| 813 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) && | |
| 814 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) && | |
| 815 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) && | |
| 816 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) && | |
| 817 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) && | |
| 818 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) && | |
| 819 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) && | |
| 820 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) && | |
| 821 !(n->rule() == loadUB_rule)) { | |
| 822 verify_oops_warning(n, n->ideal_Opcode(), ld_op); | |
| 823 } | |
| 824 } else if (st_op) { | |
| 825 // a Store | |
| 826 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
| 827 if (!(n->ideal_Opcode()==st_op) && // Following are special cases | |
| 828 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) && | |
| 829 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) && | |
| 830 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) && | |
| 831 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) && | |
| 832 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) { | |
| 833 verify_oops_warning(n, n->ideal_Opcode(), st_op); | |
| 834 } | |
| 835 } | |
| 836 | |
| 837 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) { | |
| 838 Node* addr = n->in(2); | |
| 839 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) { | |
| 840 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr? | |
| 841 if (atype != NULL) { | |
| 842 intptr_t offset = get_offset_from_base(n, atype, disp32); | |
| 843 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32); | |
| 844 if (offset != offset_2) { | |
| 845 get_offset_from_base(n, atype, disp32); | |
| 846 get_offset_from_base_2(n, atype, disp32); | |
| 847 } | |
| 848 assert(offset == offset_2, "different offsets"); | |
| 849 if (offset == disp32) { | |
| 850 // we now know that src1 is a true oop pointer | |
| 851 is_verified_oop_base = true; | |
| 852 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) { | |
| 853 if( primary == Assembler::ldd_op3 ) { | |
| 854 is_verified_oop_base = false; // Cannot 'ldd' into O7 | |
| 855 } else { | |
| 856 tmp_enc = dst_enc; | |
| 857 dst_enc = R_O7_enc; // Load into O7; preserve source oop | |
| 858 assert(src1_enc != dst_enc, ""); | |
| 859 } | |
| 860 } | |
| 861 } | |
| 862 if (st_op && (( offset == oopDesc::klass_offset_in_bytes()) | |
| 863 || offset == oopDesc::mark_offset_in_bytes())) { | |
| 864 // loading the mark should not be allowed either, but | |
| 865 // we don't check this since it conflicts with InlineObjectHash | |
| 866 // usage of LoadINode to get the mark. We could keep the | |
| 867 // check if we create a new LoadMarkNode | |
| 868 // but do not verify the object before its header is initialized | |
| 869 ShouldNotReachHere(); | |
| 870 } | |
| 871 } | |
| 872 } | |
| 873 } | |
| 874 } | |
| 875 #endif | |
| 876 | |
| 877 uint instr; | |
| 878 instr = (Assembler::ldst_op << 30) | |
| 879 | (dst_enc << 25) | |
| 880 | (primary << 19) | |
| 881 | (src1_enc << 14); | |
| 882 | |
| 883 uint index = src2_enc; | |
| 884 int disp = disp32; | |
| 885 | |
| 886 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) | |
| 887 disp += STACK_BIAS; | |
| 888 | |
| 889 // We should have a compiler bailout here rather than a guarantee. | |
| 890 // Better yet would be some mechanism to handle variable-size matches correctly. | |
| 891 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); | |
| 892 | |
| 893 if( disp == 0 ) { | |
| 894 // use reg-reg form | |
| 895 // bit 13 is already zero | |
| 896 instr |= index; | |
| 897 } else { | |
| 898 // use reg-imm form | |
| 899 instr |= 0x00002000; // set bit 13 to one | |
| 900 instr |= disp & 0x1FFF; | |
| 901 } | |
| 902 | |
| 903 uint *code = (uint*)cbuf.code_end(); | |
| 904 *code = instr; | |
| 905 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 906 | |
| 907 #ifdef ASSERT | |
| 908 { | |
| 909 MacroAssembler _masm(&cbuf); | |
| 910 if (is_verified_oop_base) { | |
| 911 __ verify_oop(reg_to_register_object(src1_enc)); | |
| 912 } | |
| 913 if (is_verified_oop_store) { | |
| 914 __ verify_oop(reg_to_register_object(dst_enc)); | |
| 915 } | |
| 916 if (tmp_enc != -1) { | |
| 917 __ mov(O7, reg_to_register_object(tmp_enc)); | |
| 918 } | |
| 919 if (is_verified_oop_load) { | |
| 920 __ verify_oop(reg_to_register_object(dst_enc)); | |
| 921 } | |
| 922 } | |
| 923 #endif | |
| 924 } | |
| 925 | |
| 926 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false, bool force_far_call = false) { | |
| 927 // The method which records debug information at every safepoint | |
| 928 // expects the call to be the first instruction in the snippet as | |
| 929 // it creates a PcDesc structure which tracks the offset of a call | |
| 930 // from the start of the codeBlob. This offset is computed as | |
| 931 // code_end() - code_begin() of the code which has been emitted | |
| 932 // so far. | |
| 933 // In this particular case we have skirted around the problem by | |
| 934 // putting the "mov" instruction in the delay slot but the problem | |
| 935 // may bite us again at some other point and a cleaner/generic | |
| 936 // solution using relocations would be needed. | |
| 937 MacroAssembler _masm(&cbuf); | |
| 938 __ set_inst_mark(); | |
| 939 | |
| 940 // We flush the current window just so that there is a valid stack copy | |
| 941 // the fact that the current window becomes active again instantly is | |
| 942 // not a problem there is nothing live in it. | |
| 943 | |
| 944 #ifdef ASSERT | |
| 945 int startpos = __ offset(); | |
| 946 #endif /* ASSERT */ | |
| 947 | |
| 948 #ifdef _LP64 | |
| 949 // Calls to the runtime or native may not be reachable from compiled code, | |
| 950 // so we generate the far call sequence on 64 bit sparc. | |
| 951 // This code sequence is relocatable to any address, even on LP64. | |
| 952 if ( force_far_call ) { | |
| 953 __ relocate(rtype); | |
| 727 | 954 AddressLiteral dest(entry_point); |
| 955 __ jumpl_to(dest, O7, O7); | |
| 0 | 956 } |
| 957 else | |
| 958 #endif | |
| 959 { | |
| 960 __ call((address)entry_point, rtype); | |
| 961 } | |
| 962 | |
| 963 if (preserve_g2) __ delayed()->mov(G2, L7); | |
| 964 else __ delayed()->nop(); | |
| 965 | |
| 966 if (preserve_g2) __ mov(L7, G2); | |
| 967 | |
| 968 #ifdef ASSERT | |
| 969 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) { | |
| 970 #ifdef _LP64 | |
| 971 // Trash argument dump slots. | |
| 972 __ set(0xb0b8ac0db0b8ac0d, G1); | |
| 973 __ mov(G1, G5); | |
| 974 __ stx(G1, SP, STACK_BIAS + 0x80); | |
| 975 __ stx(G1, SP, STACK_BIAS + 0x88); | |
| 976 __ stx(G1, SP, STACK_BIAS + 0x90); | |
| 977 __ stx(G1, SP, STACK_BIAS + 0x98); | |
| 978 __ stx(G1, SP, STACK_BIAS + 0xA0); | |
| 979 __ stx(G1, SP, STACK_BIAS + 0xA8); | |
| 980 #else // _LP64 | |
| 981 // this is also a native call, so smash the first 7 stack locations, | |
| 982 // and the various registers | |
| 983 | |
| 984 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset], | |
| 985 // while [SP+0x44..0x58] are the argument dump slots. | |
| 986 __ set((intptr_t)0xbaadf00d, G1); | |
| 987 __ mov(G1, G5); | |
| 988 __ sllx(G1, 32, G1); | |
| 989 __ or3(G1, G5, G1); | |
| 990 __ mov(G1, G5); | |
| 991 __ stx(G1, SP, 0x40); | |
| 992 __ stx(G1, SP, 0x48); | |
| 993 __ stx(G1, SP, 0x50); | |
| 994 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot | |
| 995 #endif // _LP64 | |
| 996 } | |
| 997 #endif /*ASSERT*/ | |
| 998 } | |
| 999 | |
| 1000 //============================================================================= | |
| 1001 // REQUIRED FUNCTIONALITY for encoding | |
| 1002 void emit_lo(CodeBuffer &cbuf, int val) { } | |
| 1003 void emit_hi(CodeBuffer &cbuf, int val) { } | |
| 1004 | |
| 1005 | |
| 1006 //============================================================================= | |
| 1007 | |
| 1008 #ifndef PRODUCT | |
| 1009 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1010 Compile* C = ra_->C; | |
| 1011 | |
| 1012 for (int i = 0; i < OptoPrologueNops; i++) { | |
| 1013 st->print_cr("NOP"); st->print("\t"); | |
| 1014 } | |
| 1015 | |
| 1016 if( VerifyThread ) { | |
| 1017 st->print_cr("Verify_Thread"); st->print("\t"); | |
| 1018 } | |
| 1019 | |
| 1020 size_t framesize = C->frame_slots() << LogBytesPerInt; | |
| 1021 | |
| 1022 // Calls to C2R adapters often do not accept exceptional returns. | |
| 1023 // We require that their callers must bang for them. But be careful, because | |
| 1024 // some VM calls (such as call site linkage) can use several kilobytes of | |
| 1025 // stack. But the stack safety zone should account for that. | |
| 1026 // See bugs 4446381, 4468289, 4497237. | |
| 1027 if (C->need_stack_bang(framesize)) { | |
| 1028 st->print_cr("! stack bang"); st->print("\t"); | |
| 1029 } | |
| 1030 | |
| 1031 if (Assembler::is_simm13(-framesize)) { | |
| 1032 st->print ("SAVE R_SP,-%d,R_SP",framesize); | |
| 1033 } else { | |
| 1034 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t"); | |
| 1035 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t"); | |
| 1036 st->print ("SAVE R_SP,R_G3,R_SP"); | |
| 1037 } | |
| 1038 | |
| 1039 } | |
| 1040 #endif | |
| 1041 | |
| 1042 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1043 Compile* C = ra_->C; | |
| 1044 MacroAssembler _masm(&cbuf); | |
| 1045 | |
| 1046 for (int i = 0; i < OptoPrologueNops; i++) { | |
| 1047 __ nop(); | |
| 1048 } | |
| 1049 | |
| 1050 __ verify_thread(); | |
| 1051 | |
| 1052 size_t framesize = C->frame_slots() << LogBytesPerInt; | |
| 1053 assert(framesize >= 16*wordSize, "must have room for reg. save area"); | |
| 1054 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); | |
| 1055 | |
| 1056 // Calls to C2R adapters often do not accept exceptional returns. | |
| 1057 // We require that their callers must bang for them. But be careful, because | |
| 1058 // some VM calls (such as call site linkage) can use several kilobytes of | |
| 1059 // stack. But the stack safety zone should account for that. | |
| 1060 // See bugs 4446381, 4468289, 4497237. | |
| 1061 if (C->need_stack_bang(framesize)) { | |
| 1062 __ generate_stack_overflow_check(framesize); | |
| 1063 } | |
| 1064 | |
| 1065 if (Assembler::is_simm13(-framesize)) { | |
| 1066 __ save(SP, -framesize, SP); | |
| 1067 } else { | |
| 1068 __ sethi(-framesize & ~0x3ff, G3); | |
| 1069 __ add(G3, -framesize & 0x3ff, G3); | |
| 1070 __ save(SP, G3, SP); | |
| 1071 } | |
| 1072 C->set_frame_complete( __ offset() ); | |
| 1073 } | |
| 1074 | |
| 1075 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { | |
| 1076 return MachNode::size(ra_); | |
| 1077 } | |
| 1078 | |
| 1079 int MachPrologNode::reloc() const { | |
| 1080 return 10; // a large enough number | |
| 1081 } | |
| 1082 | |
| 1083 //============================================================================= | |
| 1084 #ifndef PRODUCT | |
| 1085 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1086 Compile* C = ra_->C; | |
| 1087 | |
| 1088 if( do_polling() && ra_->C->is_method_compilation() ) { | |
| 1089 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t"); | |
| 1090 #ifdef _LP64 | |
| 1091 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t"); | |
| 1092 #else | |
| 1093 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t"); | |
| 1094 #endif | |
| 1095 } | |
| 1096 | |
| 1097 if( do_polling() ) | |
| 1098 st->print("RET\n\t"); | |
| 1099 | |
| 1100 st->print("RESTORE"); | |
| 1101 } | |
| 1102 #endif | |
| 1103 | |
| 1104 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1105 MacroAssembler _masm(&cbuf); | |
| 1106 Compile* C = ra_->C; | |
| 1107 | |
| 1108 __ verify_thread(); | |
| 1109 | |
| 1110 // If this does safepoint polling, then do it here | |
| 1111 if( do_polling() && ra_->C->is_method_compilation() ) { | |
| 727 | 1112 AddressLiteral polling_page(os::get_polling_page()); |
| 1113 __ sethi(polling_page, L0); | |
| 0 | 1114 __ relocate(relocInfo::poll_return_type); |
| 1115 __ ld_ptr( L0, 0, G0 ); | |
| 1116 } | |
| 1117 | |
| 1118 // If this is a return, then stuff the restore in the delay slot | |
| 1119 if( do_polling() ) { | |
| 1120 __ ret(); | |
| 1121 __ delayed()->restore(); | |
| 1122 } else { | |
| 1123 __ restore(); | |
| 1124 } | |
| 1125 } | |
| 1126 | |
| 1127 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { | |
| 1128 return MachNode::size(ra_); | |
| 1129 } | |
| 1130 | |
| 1131 int MachEpilogNode::reloc() const { | |
| 1132 return 16; // a large enough number | |
| 1133 } | |
| 1134 | |
| 1135 const Pipeline * MachEpilogNode::pipeline() const { | |
| 1136 return MachNode::pipeline_class(); | |
| 1137 } | |
| 1138 | |
| 1139 int MachEpilogNode::safepoint_offset() const { | |
| 1140 assert( do_polling(), "no return for this epilog node"); | |
| 1141 return MacroAssembler::size_of_sethi(os::get_polling_page()); | |
| 1142 } | |
| 1143 | |
| 1144 //============================================================================= | |
| 1145 | |
| 1146 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack | |
| 1147 enum RC { rc_bad, rc_int, rc_float, rc_stack }; | |
| 1148 static enum RC rc_class( OptoReg::Name reg ) { | |
| 1149 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
| 1150 if (OptoReg::is_stack(reg)) return rc_stack; | |
| 1151 VMReg r = OptoReg::as_VMReg(reg); | |
| 1152 if (r->is_Register()) return rc_int; | |
| 1153 assert(r->is_FloatRegister(), "must be"); | |
| 1154 return rc_float; | |
| 1155 } | |
| 1156 | |
| 1157 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) { | |
| 1158 if( cbuf ) { | |
| 1159 // Better yet would be some mechanism to handle variable-size matches correctly | |
| 1160 if (!Assembler::is_simm13(offset + STACK_BIAS)) { | |
| 1161 ra_->C->record_method_not_compilable("unable to handle large constant offsets"); | |
| 1162 } else { | |
| 1163 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); | |
| 1164 } | |
| 1165 } | |
| 1166 #ifndef PRODUCT | |
| 1167 else if( !do_size ) { | |
| 1168 if( size != 0 ) st->print("\n\t"); | |
| 1169 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg)); | |
| 1170 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset); | |
| 1171 } | |
| 1172 #endif | |
| 1173 return size+4; | |
| 1174 } | |
| 1175 | |
| 1176 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) { | |
| 1177 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] ); | |
| 1178 #ifndef PRODUCT | |
| 1179 else if( !do_size ) { | |
| 1180 if( size != 0 ) st->print("\n\t"); | |
| 1181 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst)); | |
| 1182 } | |
| 1183 #endif | |
| 1184 return size+4; | |
| 1185 } | |
| 1186 | |
| 1187 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, | |
| 1188 PhaseRegAlloc *ra_, | |
| 1189 bool do_size, | |
| 1190 outputStream* st ) const { | |
| 1191 // Get registers to move | |
| 1192 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
| 1193 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
| 1194 OptoReg::Name dst_second = ra_->get_reg_second(this ); | |
| 1195 OptoReg::Name dst_first = ra_->get_reg_first(this ); | |
| 1196 | |
| 1197 enum RC src_second_rc = rc_class(src_second); | |
| 1198 enum RC src_first_rc = rc_class(src_first); | |
| 1199 enum RC dst_second_rc = rc_class(dst_second); | |
| 1200 enum RC dst_first_rc = rc_class(dst_first); | |
| 1201 | |
| 1202 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); | |
| 1203 | |
| 1204 // Generate spill code! | |
| 1205 int size = 0; | |
| 1206 | |
| 1207 if( src_first == dst_first && src_second == dst_second ) | |
| 1208 return size; // Self copy, no move | |
| 1209 | |
| 1210 // -------------------------------------- | |
| 1211 // Check for mem-mem move. Load into unused float registers and fall into | |
| 1212 // the float-store case. | |
| 1213 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { | |
| 1214 int offset = ra_->reg2offset(src_first); | |
| 1215 // Further check for aligned-adjacent pair, so we can use a double load | |
| 1216 if( (src_first&1)==0 && src_first+1 == src_second ) { | |
| 1217 src_second = OptoReg::Name(R_F31_num); | |
| 1218 src_second_rc = rc_float; | |
| 1219 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st); | |
| 1220 } else { | |
| 1221 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st); | |
| 1222 } | |
| 1223 src_first = OptoReg::Name(R_F30_num); | |
| 1224 src_first_rc = rc_float; | |
| 1225 } | |
| 1226 | |
| 1227 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { | |
| 1228 int offset = ra_->reg2offset(src_second); | |
| 1229 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st); | |
| 1230 src_second = OptoReg::Name(R_F31_num); | |
| 1231 src_second_rc = rc_float; | |
| 1232 } | |
| 1233 | |
| 1234 // -------------------------------------- | |
| 1235 // Check for float->int copy; requires a trip through memory | |
| 1236 if( src_first_rc == rc_float && dst_first_rc == rc_int ) { | |
| 1237 int offset = frame::register_save_words*wordSize; | |
| 1238 if( cbuf ) { | |
| 1239 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 ); | |
| 1240 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
| 1241 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
| 1242 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 ); | |
| 1243 } | |
| 1244 #ifndef PRODUCT | |
| 1245 else if( !do_size ) { | |
| 1246 if( size != 0 ) st->print("\n\t"); | |
| 1247 st->print( "SUB R_SP,16,R_SP\n"); | |
| 1248 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
| 1249 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
| 1250 st->print("\tADD R_SP,16,R_SP\n"); | |
| 1251 } | |
| 1252 #endif | |
| 1253 size += 16; | |
| 1254 } | |
| 1255 | |
| 1256 // -------------------------------------- | |
| 1257 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations. | |
| 1258 // In such cases, I have to do the big-endian swap. For aligned targets, the | |
| 1259 // hardware does the flop for me. Doubles are always aligned, so no problem | |
| 1260 // there. Misaligned sources only come from native-long-returns (handled | |
| 1261 // special below). | |
| 1262 #ifndef _LP64 | |
| 1263 if( src_first_rc == rc_int && // source is already big-endian | |
| 1264 src_second_rc != rc_bad && // 64-bit move | |
| 1265 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst | |
| 1266 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" ); | |
| 1267 // Do the big-endian flop. | |
| 1268 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ; | |
| 1269 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc; | |
| 1270 } | |
| 1271 #endif | |
| 1272 | |
| 1273 // -------------------------------------- | |
| 1274 // Check for integer reg-reg copy | |
| 1275 if( src_first_rc == rc_int && dst_first_rc == rc_int ) { | |
| 1276 #ifndef _LP64 | |
| 1277 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case | |
| 1278 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
| 1279 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
| 1280 // operand contains the least significant word of the 64-bit value and vice versa. | |
| 1281 OptoReg::Name tmp = OptoReg::Name(R_O7_num); | |
| 1282 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" ); | |
| 1283 // Shift O0 left in-place, zero-extend O1, then OR them into the dst | |
| 1284 if( cbuf ) { | |
| 1285 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 ); | |
| 1286 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 ); | |
| 1287 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] ); | |
| 1288 #ifndef PRODUCT | |
| 1289 } else if( !do_size ) { | |
| 1290 if( size != 0 ) st->print("\n\t"); | |
| 1291 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp)); | |
| 1292 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second)); | |
| 1293 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first)); | |
| 1294 #endif | |
| 1295 } | |
| 1296 return size+12; | |
| 1297 } | |
| 1298 else if( dst_first == R_I0_num && dst_second == R_I1_num ) { | |
| 1299 // returning a long value in I0/I1 | |
| 1300 // a SpillCopy must be able to target a return instruction's reg_class | |
| 1301 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
| 1302 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
| 1303 // operand contains the least significant word of the 64-bit value and vice versa. | |
| 1304 OptoReg::Name tdest = dst_first; | |
| 1305 | |
| 1306 if (src_first == dst_first) { | |
| 1307 tdest = OptoReg::Name(R_O7_num); | |
| 1308 size += 4; | |
| 1309 } | |
| 1310 | |
| 1311 if( cbuf ) { | |
| 1312 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg"); | |
| 1313 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1 | |
| 1314 // ShrL_reg_imm6 | |
| 1315 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 ); | |
| 1316 // ShrR_reg_imm6 src, 0, dst | |
| 1317 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 ); | |
| 1318 if (tdest != dst_first) { | |
| 1319 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] ); | |
| 1320 } | |
| 1321 } | |
| 1322 #ifndef PRODUCT | |
| 1323 else if( !do_size ) { | |
| 1324 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!! | |
| 1325 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest)); | |
| 1326 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second)); | |
| 1327 if (tdest != dst_first) { | |
| 1328 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first)); | |
| 1329 } | |
| 1330 } | |
| 1331 #endif // PRODUCT | |
| 1332 return size+8; | |
| 1333 } | |
| 1334 #endif // !_LP64 | |
| 1335 // Else normal reg-reg copy | |
| 1336 assert( src_second != dst_first, "smashed second before evacuating it" ); | |
| 1337 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st); | |
| 1338 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" ); | |
| 1339 // This moves an aligned adjacent pair. | |
| 1340 // See if we are done. | |
| 1341 if( src_first+1 == src_second && dst_first+1 == dst_second ) | |
| 1342 return size; | |
| 1343 } | |
| 1344 | |
| 1345 // Check for integer store | |
| 1346 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) { | |
| 1347 int offset = ra_->reg2offset(dst_first); | |
| 1348 // Further check for aligned-adjacent pair, so we can use a double store | |
| 1349 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1350 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st); | |
| 1351 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st); | |
| 1352 } | |
| 1353 | |
| 1354 // Check for integer load | |
| 1355 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) { | |
| 1356 int offset = ra_->reg2offset(src_first); | |
| 1357 // Further check for aligned-adjacent pair, so we can use a double load | |
| 1358 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1359 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st); | |
| 1360 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
| 1361 } | |
| 1362 | |
| 1363 // Check for float reg-reg copy | |
| 1364 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { | |
| 1365 // Further check for aligned-adjacent pair, so we can use a double move | |
| 1366 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1367 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st); | |
| 1368 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st); | |
| 1369 } | |
| 1370 | |
| 1371 // Check for float store | |
| 1372 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { | |
| 1373 int offset = ra_->reg2offset(dst_first); | |
| 1374 // Further check for aligned-adjacent pair, so we can use a double store | |
| 1375 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1376 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st); | |
| 1377 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
| 1378 } | |
| 1379 | |
| 1380 // Check for float load | |
| 1381 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { | |
| 1382 int offset = ra_->reg2offset(src_first); | |
| 1383 // Further check for aligned-adjacent pair, so we can use a double load | |
| 1384 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
| 1385 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st); | |
| 1386 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st); | |
| 1387 } | |
| 1388 | |
| 1389 // -------------------------------------------------------------------- | |
| 1390 // Check for hi bits still needing moving. Only happens for misaligned | |
| 1391 // arguments to native calls. | |
| 1392 if( src_second == dst_second ) | |
| 1393 return size; // Self copy; no move | |
| 1394 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); | |
| 1395 | |
| 1396 #ifndef _LP64 | |
| 1397 // In the LP64 build, all registers can be moved as aligned/adjacent | |
| 605 | 1398 // pairs, so there's never any need to move the high bits separately. |
| 0 | 1399 // The 32-bit builds have to deal with the 32-bit ABI which can force |
| 1400 // all sorts of silly alignment problems. | |
| 1401 | |
| 1402 // Check for integer reg-reg copy. Hi bits are stuck up in the top | |
| 1403 // 32-bits of a 64-bit register, but are needed in low bits of another | |
| 1404 // register (else it's a hi-bits-to-hi-bits copy which should have | |
| 1405 // happened already as part of a 64-bit move) | |
| 1406 if( src_second_rc == rc_int && dst_second_rc == rc_int ) { | |
| 1407 assert( (src_second&1)==1, "its the evil O0/O1 native return case" ); | |
| 1408 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" ); | |
| 1409 // Shift src_second down to dst_second's low bits. | |
| 1410 if( cbuf ) { | |
| 1411 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
| 1412 #ifndef PRODUCT | |
| 1413 } else if( !do_size ) { | |
| 1414 if( size != 0 ) st->print("\n\t"); | |
| 1415 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second)); | |
| 1416 #endif | |
| 1417 } | |
| 1418 return size+4; | |
| 1419 } | |
| 1420 | |
| 1421 // Check for high word integer store. Must down-shift the hi bits | |
| 1422 // into a temp register, then fall into the case of storing int bits. | |
| 1423 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) { | |
| 1424 // Shift src_second down to dst_second's low bits. | |
| 1425 if( cbuf ) { | |
| 1426 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
| 1427 #ifndef PRODUCT | |
| 1428 } else if( !do_size ) { | |
| 1429 if( size != 0 ) st->print("\n\t"); | |
| 1430 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num)); | |
| 1431 #endif | |
| 1432 } | |
| 1433 size+=4; | |
| 1434 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num! | |
| 1435 } | |
| 1436 | |
| 1437 // Check for high word integer load | |
| 1438 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) | |
| 1439 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st); | |
| 1440 | |
| 1441 // Check for high word integer store | |
| 1442 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) | |
| 1443 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st); | |
| 1444 | |
| 1445 // Check for high word float store | |
| 1446 if( src_second_rc == rc_float && dst_second_rc == rc_stack ) | |
| 1447 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st); | |
| 1448 | |
| 1449 #endif // !_LP64 | |
| 1450 | |
| 1451 Unimplemented(); | |
| 1452 } | |
| 1453 | |
| 1454 #ifndef PRODUCT | |
| 1455 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1456 implementation( NULL, ra_, false, st ); | |
| 1457 } | |
| 1458 #endif | |
| 1459 | |
| 1460 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1461 implementation( &cbuf, ra_, false, NULL ); | |
| 1462 } | |
| 1463 | |
| 1464 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { | |
| 1465 return implementation( NULL, ra_, true, NULL ); | |
| 1466 } | |
| 1467 | |
| 1468 //============================================================================= | |
| 1469 #ifndef PRODUCT | |
| 1470 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
| 1471 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count); | |
| 1472 } | |
| 1473 #endif | |
| 1474 | |
| 1475 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { | |
| 1476 MacroAssembler _masm(&cbuf); | |
| 1477 for(int i = 0; i < _count; i += 1) { | |
| 1478 __ nop(); | |
| 1479 } | |
| 1480 } | |
| 1481 | |
| 1482 uint MachNopNode::size(PhaseRegAlloc *ra_) const { | |
| 1483 return 4 * _count; | |
| 1484 } | |
| 1485 | |
| 1486 | |
| 1487 //============================================================================= | |
| 1488 #ifndef PRODUCT | |
| 1489 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1490 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1491 int reg = ra_->get_reg_first(this); | |
| 1492 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]); | |
| 1493 } | |
| 1494 #endif | |
| 1495 | |
| 1496 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1497 MacroAssembler _masm(&cbuf); | |
| 1498 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS; | |
| 1499 int reg = ra_->get_encode(this); | |
| 1500 | |
| 1501 if (Assembler::is_simm13(offset)) { | |
| 1502 __ add(SP, offset, reg_to_register_object(reg)); | |
| 1503 } else { | |
| 1504 __ set(offset, O7); | |
| 1505 __ add(SP, O7, reg_to_register_object(reg)); | |
| 1506 } | |
| 1507 } | |
| 1508 | |
| 1509 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { | |
| 1510 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) | |
| 1511 assert(ra_ == ra_->C->regalloc(), "sanity"); | |
| 1512 return ra_->C->scratch_emit_size(this); | |
| 1513 } | |
| 1514 | |
| 1515 //============================================================================= | |
| 1516 | |
| 1517 // emit call stub, compiled java to interpretor | |
| 1518 void emit_java_to_interp(CodeBuffer &cbuf ) { | |
| 1519 | |
| 1520 // Stub is fixed up when the corresponding call is converted from calling | |
| 1521 // compiled code to calling interpreted code. | |
| 1522 // set (empty), G5 | |
| 1523 // jmp -1 | |
| 1524 | |
| 1525 address mark = cbuf.inst_mark(); // get mark within main instrs section | |
| 1526 | |
| 1527 MacroAssembler _masm(&cbuf); | |
| 1528 | |
| 1529 address base = | |
| 1530 __ start_a_stub(Compile::MAX_stubs_size); | |
| 1531 if (base == NULL) return; // CodeBuffer::expand failed | |
| 1532 | |
| 1533 // static stub relocation stores the instruction address of the call | |
| 1534 __ relocate(static_stub_Relocation::spec(mark)); | |
| 1535 | |
| 1536 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode())); | |
| 1537 | |
| 1538 __ set_inst_mark(); | |
| 727 | 1539 AddressLiteral addrlit(-1); |
| 1540 __ JUMP(addrlit, G3, 0); | |
| 0 | 1541 |
| 1542 __ delayed()->nop(); | |
| 1543 | |
| 1544 // Update current stubs pointer and restore code_end. | |
| 1545 __ end_a_stub(); | |
| 1546 } | |
| 1547 | |
| 1548 // size of call stub, compiled java to interpretor | |
| 1549 uint size_java_to_interp() { | |
| 1550 // This doesn't need to be accurate but it must be larger or equal to | |
| 1551 // the real size of the stub. | |
| 1552 return (NativeMovConstReg::instruction_size + // sethi/setlo; | |
| 1553 NativeJump::instruction_size + // sethi; jmp; nop | |
| 1554 (TraceJumps ? 20 * BytesPerInstWord : 0) ); | |
| 1555 } | |
| 1556 // relocation entries for call stub, compiled java to interpretor | |
| 1557 uint reloc_java_to_interp() { | |
| 1558 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call | |
| 1559 } | |
| 1560 | |
| 1561 | |
| 1562 //============================================================================= | |
| 1563 #ifndef PRODUCT | |
| 1564 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
| 1565 st->print_cr("\nUEP:"); | |
| 1566 #ifdef _LP64 | |
|
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1567 if (UseCompressedOops) { |
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1568 assert(Universe::heap() != NULL, "java heap should be initialized"); |
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1569 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass"); |
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1570 st->print_cr("\tSLL R_G5,3,R_G5"); |
|
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1571 if (Universe::narrow_oop_base() != NULL) |
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1572 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5"); |
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1573 } else { |
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1574 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); |
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1575 } |
| 0 | 1576 st->print_cr("\tCMP R_G5,R_G3" ); |
| 1577 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
| 1578 #else // _LP64 | |
| 1579 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); | |
| 1580 st->print_cr("\tCMP R_G5,R_G3" ); | |
| 1581 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
| 1582 #endif // _LP64 | |
| 1583 } | |
| 1584 #endif | |
| 1585 | |
| 1586 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1587 MacroAssembler _masm(&cbuf); | |
| 1588 Label L; | |
| 1589 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
| 1590 Register temp_reg = G3; | |
| 1591 assert( G5_ic_reg != temp_reg, "conflicting registers" ); | |
| 1592 | |
| 605 | 1593 // Load klass from receiver |
|
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1594 __ load_klass(O0, temp_reg); |
| 0 | 1595 // Compare against expected klass |
| 1596 __ cmp(temp_reg, G5_ic_reg); | |
| 1597 // Branch to miss code, checks xcc or icc depending | |
| 1598 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2); | |
| 1599 } | |
| 1600 | |
| 1601 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { | |
| 1602 return MachNode::size(ra_); | |
| 1603 } | |
| 1604 | |
| 1605 | |
| 1606 //============================================================================= | |
| 1607 | |
| 1608 uint size_exception_handler() { | |
| 1609 if (TraceJumps) { | |
| 1610 return (400); // just a guess | |
| 1611 } | |
| 1612 return ( NativeJump::instruction_size ); // sethi;jmp;nop | |
| 1613 } | |
| 1614 | |
| 1615 uint size_deopt_handler() { | |
| 1616 if (TraceJumps) { | |
| 1617 return (400); // just a guess | |
| 1618 } | |
| 1619 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore | |
| 1620 } | |
| 1621 | |
| 1622 // Emit exception handler code. | |
| 1623 int emit_exception_handler(CodeBuffer& cbuf) { | |
| 1624 Register temp_reg = G3; | |
| 727 | 1625 AddressLiteral exception_blob(OptoRuntime::exception_blob()->instructions_begin()); |
| 0 | 1626 MacroAssembler _masm(&cbuf); |
| 1627 | |
| 1628 address base = | |
| 1629 __ start_a_stub(size_exception_handler()); | |
| 1630 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1631 | |
| 1632 int offset = __ offset(); | |
| 1633 | |
| 727 | 1634 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp |
| 0 | 1635 __ delayed()->nop(); |
| 1636 | |
| 1637 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); | |
| 1638 | |
| 1639 __ end_a_stub(); | |
| 1640 | |
| 1641 return offset; | |
| 1642 } | |
| 1643 | |
| 1644 int emit_deopt_handler(CodeBuffer& cbuf) { | |
| 1645 // Can't use any of the current frame's registers as we may have deopted | |
| 1646 // at a poll and everything (including G3) can be live. | |
| 1647 Register temp_reg = L0; | |
| 727 | 1648 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); |
| 0 | 1649 MacroAssembler _masm(&cbuf); |
| 1650 | |
| 1651 address base = | |
| 1652 __ start_a_stub(size_deopt_handler()); | |
| 1653 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1654 | |
| 1655 int offset = __ offset(); | |
| 1656 __ save_frame(0); | |
| 727 | 1657 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp |
| 0 | 1658 __ delayed()->restore(); |
| 1659 | |
| 1660 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); | |
| 1661 | |
| 1662 __ end_a_stub(); | |
| 1663 return offset; | |
| 1664 | |
| 1665 } | |
| 1666 | |
| 1667 // Given a register encoding, produce a Integer Register object | |
| 1668 static Register reg_to_register_object(int register_encoding) { | |
| 1669 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding"); | |
| 1670 return as_Register(register_encoding); | |
| 1671 } | |
| 1672 | |
| 1673 // Given a register encoding, produce a single-precision Float Register object | |
| 1674 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) { | |
| 1675 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding"); | |
| 1676 return as_SingleFloatRegister(register_encoding); | |
| 1677 } | |
| 1678 | |
| 1679 // Given a register encoding, produce a double-precision Float Register object | |
| 1680 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) { | |
| 1681 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding"); | |
| 1682 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding"); | |
| 1683 return as_DoubleFloatRegister(register_encoding); | |
| 1684 } | |
| 1685 | |
|
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1686 const bool Matcher::match_rule_supported(int opcode) { |
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1687 if (!has_match_rule(opcode)) |
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1688 return false; |
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1689 |
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1690 switch (opcode) { |
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1691 case Op_CountLeadingZerosI: |
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1692 case Op_CountLeadingZerosL: |
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1693 case Op_CountTrailingZerosI: |
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1694 case Op_CountTrailingZerosL: |
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1695 if (!UsePopCountInstruction) |
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1696 return false; |
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1697 break; |
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1698 } |
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1699 |
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1700 return true; // Per default match rules are supported. |
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1701 } |
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1702 |
| 0 | 1703 int Matcher::regnum_to_fpu_offset(int regnum) { |
| 1704 return regnum - 32; // The FP registers are in the second chunk | |
| 1705 } | |
| 1706 | |
| 1707 #ifdef ASSERT | |
| 1708 address last_rethrow = NULL; // debugging aid for Rethrow encoding | |
| 1709 #endif | |
| 1710 | |
| 1711 // Vector width in bytes | |
| 1712 const uint Matcher::vector_width_in_bytes(void) { | |
| 1713 return 8; | |
| 1714 } | |
| 1715 | |
| 1716 // Vector ideal reg | |
| 1717 const uint Matcher::vector_ideal_reg(void) { | |
| 1718 return Op_RegD; | |
| 1719 } | |
| 1720 | |
| 1721 // USII supports fxtof through the whole range of number, USIII doesn't | |
| 1722 const bool Matcher::convL2FSupported(void) { | |
| 1723 return VM_Version::has_fast_fxtof(); | |
| 1724 } | |
| 1725 | |
| 1726 // Is this branch offset short enough that a short branch can be used? | |
| 1727 // | |
| 1728 // NOTE: If the platform does not provide any short branch variants, then | |
| 1729 // this method should return false for offset 0. | |
|
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1730 bool Matcher::is_short_branch_offset(int rule, int offset) { |
| 0 | 1731 return false; |
| 1732 } | |
| 1733 | |
| 1734 const bool Matcher::isSimpleConstant64(jlong value) { | |
| 1735 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
| 1736 // Depends on optimizations in MacroAssembler::setx. | |
| 1737 int hi = (int)(value >> 32); | |
| 1738 int lo = (int)(value & ~0); | |
| 1739 return (hi == 0) || (hi == -1) || (lo == 0); | |
| 1740 } | |
| 1741 | |
| 1742 // No scaling for the parameter the ClearArray node. | |
| 1743 const bool Matcher::init_array_count_is_in_bytes = true; | |
| 1744 | |
| 1745 // Threshold size for cleararray. | |
| 1746 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
| 1747 | |
| 1748 // Should the Matcher clone shifts on addressing modes, expecting them to | |
| 1749 // be subsumed into complex addressing expressions or compute them into | |
| 1750 // registers? True for Intel but false for most RISCs | |
| 1751 const bool Matcher::clone_shift_expressions = false; | |
| 1752 | |
| 1753 // Is it better to copy float constants, or load them directly from memory? | |
| 1754 // Intel can load a float constant from a direct address, requiring no | |
| 1755 // extra registers. Most RISCs will have to materialize an address into a | |
| 1756 // register first, so they would do better to copy the constant from stack. | |
| 1757 const bool Matcher::rematerialize_float_constants = false; | |
| 1758 | |
| 1759 // If CPU can load and store mis-aligned doubles directly then no fixup is | |
| 1760 // needed. Else we split the double into 2 integer pieces and move it | |
| 1761 // piece-by-piece. Only happens when passing doubles into C code as the | |
| 1762 // Java calling convention forces doubles to be aligned. | |
| 1763 #ifdef _LP64 | |
| 1764 const bool Matcher::misaligned_doubles_ok = true; | |
| 1765 #else | |
| 1766 const bool Matcher::misaligned_doubles_ok = false; | |
| 1767 #endif | |
| 1768 | |
| 1769 // No-op on SPARC. | |
| 1770 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { | |
| 1771 } | |
| 1772 | |
| 1773 // Advertise here if the CPU requires explicit rounding operations | |
| 1774 // to implement the UseStrictFP mode. | |
| 1775 const bool Matcher::strict_fp_requires_explicit_rounding = false; | |
| 1776 | |
|
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1777 // Are floats conerted to double when stored to stack during deoptimization? |
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1778 // Sparc does not handle callee-save floats. |
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1779 bool Matcher::float_in_double() { return false; } |
| 0 | 1780 |
| 1781 // Do ints take an entire long register or just half? | |
| 1782 // Note that we if-def off of _LP64. | |
| 1783 // The relevant question is how the int is callee-saved. In _LP64 | |
| 1784 // the whole long is written but de-opt'ing will have to extract | |
| 1785 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written. | |
| 1786 #ifdef _LP64 | |
| 1787 const bool Matcher::int_in_long = true; | |
| 1788 #else | |
| 1789 const bool Matcher::int_in_long = false; | |
| 1790 #endif | |
| 1791 | |
| 1792 // Return whether or not this register is ever used as an argument. This | |
| 1793 // function is used on startup to build the trampoline stubs in generateOptoStub. | |
| 1794 // Registers not mentioned will be killed by the VM call in the trampoline, and | |
| 1795 // arguments in those registers not be available to the callee. | |
| 1796 bool Matcher::can_be_java_arg( int reg ) { | |
| 1797 // Standard sparc 6 args in registers | |
| 1798 if( reg == R_I0_num || | |
| 1799 reg == R_I1_num || | |
| 1800 reg == R_I2_num || | |
| 1801 reg == R_I3_num || | |
| 1802 reg == R_I4_num || | |
| 1803 reg == R_I5_num ) return true; | |
| 1804 #ifdef _LP64 | |
| 1805 // 64-bit builds can pass 64-bit pointers and longs in | |
| 1806 // the high I registers | |
| 1807 if( reg == R_I0H_num || | |
| 1808 reg == R_I1H_num || | |
| 1809 reg == R_I2H_num || | |
| 1810 reg == R_I3H_num || | |
| 1811 reg == R_I4H_num || | |
| 1812 reg == R_I5H_num ) return true; | |
|
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1813 |
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1814 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) { |
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1815 return true; |
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1816 } |
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1817 |
| 0 | 1818 #else |
| 1819 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4. | |
| 1820 // Longs cannot be passed in O regs, because O regs become I regs | |
| 1821 // after a 'save' and I regs get their high bits chopped off on | |
| 1822 // interrupt. | |
| 1823 if( reg == R_G1H_num || reg == R_G1_num ) return true; | |
| 1824 if( reg == R_G4H_num || reg == R_G4_num ) return true; | |
| 1825 #endif | |
| 1826 // A few float args in registers | |
| 1827 if( reg >= R_F0_num && reg <= R_F7_num ) return true; | |
| 1828 | |
| 1829 return false; | |
| 1830 } | |
| 1831 | |
| 1832 bool Matcher::is_spillable_arg( int reg ) { | |
| 1833 return can_be_java_arg(reg); | |
| 1834 } | |
| 1835 | |
| 1836 // Register for DIVI projection of divmodI | |
| 1837 RegMask Matcher::divI_proj_mask() { | |
| 1838 ShouldNotReachHere(); | |
| 1839 return RegMask(); | |
| 1840 } | |
| 1841 | |
| 1842 // Register for MODI projection of divmodI | |
| 1843 RegMask Matcher::modI_proj_mask() { | |
| 1844 ShouldNotReachHere(); | |
| 1845 return RegMask(); | |
| 1846 } | |
| 1847 | |
| 1848 // Register for DIVL projection of divmodL | |
| 1849 RegMask Matcher::divL_proj_mask() { | |
| 1850 ShouldNotReachHere(); | |
| 1851 return RegMask(); | |
| 1852 } | |
| 1853 | |
| 1854 // Register for MODL projection of divmodL | |
| 1855 RegMask Matcher::modL_proj_mask() { | |
| 1856 ShouldNotReachHere(); | |
| 1857 return RegMask(); | |
| 1858 } | |
| 1859 | |
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1860 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
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1861 return RegMask(); |
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1862 } |
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1863 |
| 0 | 1864 %} |
| 1865 | |
| 1866 | |
| 1867 // The intptr_t operand types, defined by textual substitution. | |
| 1868 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.) | |
| 1869 #ifdef _LP64 | |
| 824 | 1870 #define immX immL |
| 1871 #define immX13 immL13 | |
| 1872 #define immX13m7 immL13m7 | |
| 1873 #define iRegX iRegL | |
| 1874 #define g1RegX g1RegL | |
| 0 | 1875 #else |
| 824 | 1876 #define immX immI |
| 1877 #define immX13 immI13 | |
| 1878 #define immX13m7 immI13m7 | |
| 1879 #define iRegX iRegI | |
| 1880 #define g1RegX g1RegI | |
| 0 | 1881 #endif |
| 1882 | |
| 1883 //----------ENCODING BLOCK----------------------------------------------------- | |
| 1884 // This block specifies the encoding classes used by the compiler to output | |
| 1885 // byte streams. Encoding classes are parameterized macros used by | |
| 1886 // Machine Instruction Nodes in order to generate the bit encoding of the | |
| 1887 // instruction. Operands specify their base encoding interface with the | |
| 1888 // interface keyword. There are currently supported four interfaces, | |
| 1889 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an | |
| 1890 // operand to generate a function which returns its register number when | |
| 1891 // queried. CONST_INTER causes an operand to generate a function which | |
| 1892 // returns the value of the constant when queried. MEMORY_INTER causes an | |
| 1893 // operand to generate four functions which return the Base Register, the | |
| 1894 // Index Register, the Scale Value, and the Offset Value of the operand when | |
| 1895 // queried. COND_INTER causes an operand to generate six functions which | |
| 1896 // return the encoding code (ie - encoding bits for the instruction) | |
| 1897 // associated with each basic boolean condition for a conditional instruction. | |
| 1898 // | |
| 1899 // Instructions specify two basic values for encoding. Again, a function | |
| 1900 // is available to check if the constant displacement is an oop. They use the | |
| 1901 // ins_encode keyword to specify their encoding classes (which must be | |
| 1902 // a sequence of enc_class names, and their parameters, specified in | |
| 1903 // the encoding block), and they use the | |
| 1904 // opcode keyword to specify, in order, their primary, secondary, and | |
| 1905 // tertiary opcode. Only the opcode sections which a particular instruction | |
| 1906 // needs for encoding need to be specified. | |
| 1907 encode %{ | |
| 1908 enc_class enc_untested %{ | |
| 1909 #ifdef ASSERT | |
| 1910 MacroAssembler _masm(&cbuf); | |
| 1911 __ untested("encoding"); | |
| 1912 #endif | |
| 1913 %} | |
| 1914 | |
| 1915 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ | |
| 1916 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, | |
| 1917 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); | |
| 1918 %} | |
| 1919 | |
|
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1920 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ |
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1921 emit_form3_mem_reg(cbuf, this, $primary, -1, |
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1922 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); |
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1923 %} |
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1924 |
| 0 | 1925 enc_class form3_mem_prefetch_read( memory mem ) %{ |
|
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1926 emit_form3_mem_reg(cbuf, this, $primary, -1, |
| 0 | 1927 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); |
| 1928 %} | |
| 1929 | |
| 1930 enc_class form3_mem_prefetch_write( memory mem ) %{ | |
|
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1931 emit_form3_mem_reg(cbuf, this, $primary, -1, |
| 0 | 1932 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); |
| 1933 %} | |
| 1934 | |
| 1935 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ | |
| 1936 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); | |
| 1937 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); | |
| 1938 guarantee($mem$$index == R_G0_enc, "double index?"); | |
|
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1939 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); |
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1940 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); |
| 0 | 1941 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); |
| 1942 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); | |
| 1943 %} | |
| 1944 | |
| 1945 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ | |
| 1946 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); | |
| 1947 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); | |
| 1948 guarantee($mem$$index == R_G0_enc, "double index?"); | |
| 1949 // Load long with 2 instructions | |
|
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1950 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); |
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1951 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); |
| 0 | 1952 %} |
| 1953 | |
| 1954 //%%% form3_mem_plus_4_reg is a hack--get rid of it | |
| 1955 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ | |
| 1956 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); | |
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1957 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); |
| 0 | 1958 %} |
| 1959 | |
| 1960 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ | |
| 1961 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 1962 if( $rs2$$reg != $rd$$reg ) | |
| 1963 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg ); | |
| 1964 %} | |
| 1965 | |
| 1966 // Target lo half of long | |
| 1967 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{ | |
| 1968 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 1969 if( $rs2$$reg != LONG_LO_REG($rd$$reg) ) | |
| 1970 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg ); | |
| 1971 %} | |
| 1972 | |
| 1973 // Source lo half of long | |
| 1974 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{ | |
| 1975 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 1976 if( LONG_LO_REG($rs2$$reg) != $rd$$reg ) | |
| 1977 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) ); | |
| 1978 %} | |
| 1979 | |
| 1980 // Target hi half of long | |
| 1981 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{ | |
| 1982 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 ); | |
| 1983 %} | |
| 1984 | |
| 1985 // Source lo half of long, and leave it sign extended. | |
| 1986 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{ | |
| 1987 // Sign extend low half | |
| 1988 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 ); | |
| 1989 %} | |
| 1990 | |
| 1991 // Source hi half of long, and leave it sign extended. | |
| 1992 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{ | |
| 1993 // Shift high half to low half | |
| 1994 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 ); | |
| 1995 %} | |
| 1996 | |
| 1997 // Source hi half of long | |
| 1998 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{ | |
| 1999 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2000 if( LONG_HI_REG($rs2$$reg) != $rd$$reg ) | |
| 2001 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) ); | |
| 2002 %} | |
| 2003 | |
| 2004 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{ | |
| 2005 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg ); | |
| 2006 %} | |
| 2007 | |
| 2008 enc_class enc_to_bool( iRegI src, iRegI dst ) %{ | |
| 2009 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg ); | |
| 2010 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 ); | |
| 2011 %} | |
| 2012 | |
| 2013 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{ | |
| 2014 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg ); | |
| 2015 // clear if nothing else is happening | |
| 2016 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 ); | |
| 2017 // blt,a,pn done | |
| 2018 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 ); | |
| 2019 // mov dst,-1 in delay slot | |
| 2020 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
| 2021 %} | |
| 2022 | |
| 2023 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{ | |
| 2024 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F ); | |
| 2025 %} | |
| 2026 | |
| 2027 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{ | |
| 2028 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 ); | |
| 2029 %} | |
| 2030 | |
| 2031 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{ | |
| 2032 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg ); | |
| 2033 %} | |
| 2034 | |
| 2035 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{ | |
| 2036 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant ); | |
| 2037 %} | |
| 2038 | |
| 2039 enc_class move_return_pc_to_o1() %{ | |
| 2040 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset ); | |
| 2041 %} | |
| 2042 | |
| 2043 #ifdef _LP64 | |
| 2044 /* %%% merge with enc_to_bool */ | |
| 2045 enc_class enc_convP2B( iRegI dst, iRegP src ) %{ | |
| 2046 MacroAssembler _masm(&cbuf); | |
| 2047 | |
| 2048 Register src_reg = reg_to_register_object($src$$reg); | |
| 2049 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 2050 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg); | |
| 2051 %} | |
| 2052 #endif | |
| 2053 | |
| 2054 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{ | |
| 2055 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))) | |
| 2056 MacroAssembler _masm(&cbuf); | |
| 2057 | |
| 2058 Register p_reg = reg_to_register_object($p$$reg); | |
| 2059 Register q_reg = reg_to_register_object($q$$reg); | |
| 2060 Register y_reg = reg_to_register_object($y$$reg); | |
| 2061 Register tmp_reg = reg_to_register_object($tmp$$reg); | |
| 2062 | |
| 2063 __ subcc( p_reg, q_reg, p_reg ); | |
| 2064 __ add ( p_reg, y_reg, tmp_reg ); | |
| 2065 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg ); | |
| 2066 %} | |
| 2067 | |
| 2068 enc_class form_d2i_helper(regD src, regF dst) %{ | |
| 2069 // fcmp %fcc0,$src,$src | |
| 2070 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
| 2071 // branch %fcc0 not-nan, predict taken | |
| 2072 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2073 // fdtoi $src,$dst | |
| 2074 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg ); | |
| 2075 // fitos $dst,$dst (if nan) | |
| 2076 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
| 2077 // clear $dst (if nan) | |
| 2078 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
| 2079 // carry on here... | |
| 2080 %} | |
| 2081 | |
| 2082 enc_class form_d2l_helper(regD src, regD dst) %{ | |
| 2083 // fcmp %fcc0,$src,$src check for NAN | |
| 2084 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
| 2085 // branch %fcc0 not-nan, predict taken | |
| 2086 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2087 // fdtox $src,$dst convert in delay slot | |
| 2088 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg ); | |
| 2089 // fxtod $dst,$dst (if nan) | |
| 2090 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
| 2091 // clear $dst (if nan) | |
| 2092 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
| 2093 // carry on here... | |
| 2094 %} | |
| 2095 | |
| 2096 enc_class form_f2i_helper(regF src, regF dst) %{ | |
| 2097 // fcmps %fcc0,$src,$src | |
| 2098 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
| 2099 // branch %fcc0 not-nan, predict taken | |
| 2100 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2101 // fstoi $src,$dst | |
| 2102 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg ); | |
| 2103 // fitos $dst,$dst (if nan) | |
| 2104 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
| 2105 // clear $dst (if nan) | |
| 2106 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
| 2107 // carry on here... | |
| 2108 %} | |
| 2109 | |
| 2110 enc_class form_f2l_helper(regF src, regD dst) %{ | |
| 2111 // fcmps %fcc0,$src,$src | |
| 2112 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
| 2113 // branch %fcc0 not-nan, predict taken | |
| 2114 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
| 2115 // fstox $src,$dst | |
| 2116 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg ); | |
| 2117 // fxtod $dst,$dst (if nan) | |
| 2118 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
| 2119 // clear $dst (if nan) | |
| 2120 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
| 2121 // carry on here... | |
| 2122 %} | |
| 2123 | |
| 2124 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2125 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2126 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2127 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2128 | |
| 2129 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %} | |
| 2130 | |
| 2131 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
| 2132 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %} | |
| 2133 | |
| 2134 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{ | |
| 2135 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2136 %} | |
| 2137 | |
| 2138 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{ | |
| 2139 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2140 %} | |
| 2141 | |
| 2142 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{ | |
| 2143 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2144 %} | |
| 2145 | |
| 2146 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{ | |
| 2147 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
| 2148 %} | |
| 2149 | |
| 2150 enc_class form3_convI2F(regF rs2, regF rd) %{ | |
| 2151 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg); | |
| 2152 %} | |
| 2153 | |
| 2154 // Encloding class for traceable jumps | |
| 2155 enc_class form_jmpl(g3RegP dest) %{ | |
| 2156 emit_jmpl(cbuf, $dest$$reg); | |
| 2157 %} | |
| 2158 | |
| 2159 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{ | |
| 2160 emit_jmpl_set_exception_pc(cbuf, $dest$$reg); | |
| 2161 %} | |
| 2162 | |
| 2163 enc_class form2_nop() %{ | |
| 2164 emit_nop(cbuf); | |
| 2165 %} | |
| 2166 | |
| 2167 enc_class form2_illtrap() %{ | |
| 2168 emit_illtrap(cbuf); | |
| 2169 %} | |
| 2170 | |
| 2171 | |
| 2172 // Compare longs and convert into -1, 0, 1. | |
| 2173 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{ | |
| 2174 // CMP $src1,$src2 | |
| 2175 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg ); | |
| 2176 // blt,a,pn done | |
| 2177 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 ); | |
| 2178 // mov dst,-1 in delay slot | |
| 2179 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
| 2180 // bgt,a,pn done | |
| 2181 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 ); | |
| 2182 // mov dst,1 in delay slot | |
| 2183 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 ); | |
| 2184 // CLR $dst | |
| 2185 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 ); | |
| 2186 %} | |
| 2187 | |
| 2188 enc_class enc_PartialSubtypeCheck() %{ | |
| 2189 MacroAssembler _masm(&cbuf); | |
| 2190 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type); | |
| 2191 __ delayed()->nop(); | |
| 2192 %} | |
| 2193 | |
| 2194 enc_class enc_bp( Label labl, cmpOp cmp, flagsReg cc ) %{ | |
| 2195 MacroAssembler _masm(&cbuf); | |
| 2196 Label &L = *($labl$$label); | |
| 2197 Assembler::Predict predict_taken = | |
| 2198 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
| 2199 | |
| 2200 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, L); | |
| 2201 __ delayed()->nop(); | |
| 2202 %} | |
| 2203 | |
| 2204 enc_class enc_bpl( Label labl, cmpOp cmp, flagsRegL cc ) %{ | |
| 2205 MacroAssembler _masm(&cbuf); | |
| 2206 Label &L = *($labl$$label); | |
| 2207 Assembler::Predict predict_taken = | |
| 2208 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
| 2209 | |
| 2210 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, L); | |
| 2211 __ delayed()->nop(); | |
| 2212 %} | |
| 2213 | |
| 2214 enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{ | |
| 2215 MacroAssembler _masm(&cbuf); | |
| 2216 Label &L = *($labl$$label); | |
| 2217 Assembler::Predict predict_taken = | |
| 2218 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
| 2219 | |
| 2220 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L); | |
| 2221 __ delayed()->nop(); | |
| 2222 %} | |
| 2223 | |
| 2224 enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{ | |
| 2225 MacroAssembler _masm(&cbuf); | |
| 2226 Label &L = *($labl$$label); | |
| 2227 Assembler::Predict predict_taken = | |
| 2228 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
| 2229 | |
| 2230 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L); | |
| 2231 __ delayed()->nop(); | |
| 2232 %} | |
| 2233 | |
| 2234 enc_class jump_enc( iRegX switch_val, o7RegI table) %{ | |
| 2235 MacroAssembler _masm(&cbuf); | |
| 2236 | |
| 2237 Register switch_reg = as_Register($switch_val$$reg); | |
| 2238 Register table_reg = O7; | |
| 2239 | |
| 2240 address table_base = __ address_table_constant(_index2label); | |
| 2241 RelocationHolder rspec = internal_word_Relocation::spec(table_base); | |
| 2242 | |
| 727 | 2243 // Move table address into a register. |
| 2244 __ set(table_base, table_reg, rspec); | |
| 0 | 2245 |
| 2246 // Jump to base address + switch value | |
| 2247 __ ld_ptr(table_reg, switch_reg, table_reg); | |
| 2248 __ jmp(table_reg, G0); | |
| 2249 __ delayed()->nop(); | |
| 2250 | |
| 2251 %} | |
| 2252 | |
| 2253 enc_class enc_ba( Label labl ) %{ | |
| 2254 MacroAssembler _masm(&cbuf); | |
| 2255 Label &L = *($labl$$label); | |
| 2256 __ ba(false, L); | |
| 2257 __ delayed()->nop(); | |
| 2258 %} | |
| 2259 | |
| 2260 enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{ | |
| 2261 MacroAssembler _masm(&cbuf); | |
| 2262 Label &L = *$labl$$label; | |
| 2263 Assembler::Predict predict_taken = | |
| 2264 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
| 2265 | |
| 2266 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L); | |
| 2267 __ delayed()->nop(); | |
| 2268 %} | |
| 2269 | |
| 2270 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{ | |
| 2271 int op = (Assembler::arith_op << 30) | | |
| 2272 ($dst$$reg << 25) | | |
| 2273 (Assembler::movcc_op3 << 19) | | |
| 2274 (1 << 18) | // cc2 bit for 'icc' | |
| 2275 ($cmp$$cmpcode << 14) | | |
| 2276 (0 << 13) | // select register move | |
| 2277 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc' | |
| 2278 ($src$$reg << 0); | |
| 2279 *((int*)(cbuf.code_end())) = op; | |
| 2280 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 2281 %} | |
| 2282 | |
| 2283 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{ | |
| 2284 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
| 2285 int op = (Assembler::arith_op << 30) | | |
| 2286 ($dst$$reg << 25) | | |
| 2287 (Assembler::movcc_op3 << 19) | | |
| 2288 (1 << 18) | // cc2 bit for 'icc' | |
| 2289 ($cmp$$cmpcode << 14) | | |
| 2290 (1 << 13) | // select immediate move | |
| 2291 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' | |
| 2292 (simm11 << 0); | |
| 2293 *((int*)(cbuf.code_end())) = op; | |
| 2294 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 2295 %} | |
| 2296 | |
| 2297 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{ | |
| 2298 int op = (Assembler::arith_op << 30) | | |
| 2299 ($dst$$reg << 25) | | |
| 2300 (Assembler::movcc_op3 << 19) | | |
| 2301 (0 << 18) | // cc2 bit for 'fccX' | |
| 2302 ($cmp$$cmpcode << 14) | | |
| 2303 (0 << 13) | // select register move | |
| 2304 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
| 2305 ($src$$reg << 0); | |
| 2306 *((int*)(cbuf.code_end())) = op; | |
| 2307 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 2308 %} | |
| 2309 | |
| 2310 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{ | |
| 2311 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
| 2312 int op = (Assembler::arith_op << 30) | | |
| 2313 ($dst$$reg << 25) | | |
| 2314 (Assembler::movcc_op3 << 19) | | |
| 2315 (0 << 18) | // cc2 bit for 'fccX' | |
| 2316 ($cmp$$cmpcode << 14) | | |
| 2317 (1 << 13) | // select immediate move | |
| 2318 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
| 2319 (simm11 << 0); | |
| 2320 *((int*)(cbuf.code_end())) = op; | |
| 2321 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 2322 %} | |
| 2323 | |
| 2324 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{ | |
| 2325 int op = (Assembler::arith_op << 30) | | |
| 2326 ($dst$$reg << 25) | | |
| 2327 (Assembler::fpop2_op3 << 19) | | |
| 2328 (0 << 18) | | |
| 2329 ($cmp$$cmpcode << 14) | | |
| 2330 (1 << 13) | // select register move | |
| 2331 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc' | |
| 2332 ($primary << 5) | // select single, double or quad | |
| 2333 ($src$$reg << 0); | |
| 2334 *((int*)(cbuf.code_end())) = op; | |
| 2335 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 2336 %} | |
| 2337 | |
| 2338 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{ | |
| 2339 int op = (Assembler::arith_op << 30) | | |
| 2340 ($dst$$reg << 25) | | |
| 2341 (Assembler::fpop2_op3 << 19) | | |
| 2342 (0 << 18) | | |
| 2343 ($cmp$$cmpcode << 14) | | |
| 2344 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX' | |
| 2345 ($primary << 5) | // select single, double or quad | |
| 2346 ($src$$reg << 0); | |
| 2347 *((int*)(cbuf.code_end())) = op; | |
| 2348 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 2349 %} | |
| 2350 | |
| 2351 // Used by the MIN/MAX encodings. Same as a CMOV, but | |
| 2352 // the condition comes from opcode-field instead of an argument. | |
| 2353 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{ | |
| 2354 int op = (Assembler::arith_op << 30) | | |
| 2355 ($dst$$reg << 25) | | |
| 2356 (Assembler::movcc_op3 << 19) | | |
| 2357 (1 << 18) | // cc2 bit for 'icc' | |
| 2358 ($primary << 14) | | |
| 2359 (0 << 13) | // select register move | |
| 2360 (0 << 11) | // cc1, cc0 bits for 'icc' | |
| 2361 ($src$$reg << 0); | |
| 2362 *((int*)(cbuf.code_end())) = op; | |
| 2363 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 2364 %} | |
| 2365 | |
| 2366 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{ | |
| 2367 int op = (Assembler::arith_op << 30) | | |
| 2368 ($dst$$reg << 25) | | |
| 2369 (Assembler::movcc_op3 << 19) | | |
| 2370 (6 << 16) | // cc2 bit for 'xcc' | |
| 2371 ($primary << 14) | | |
| 2372 (0 << 13) | // select register move | |
| 2373 (0 << 11) | // cc1, cc0 bits for 'icc' | |
| 2374 ($src$$reg << 0); | |
| 2375 *((int*)(cbuf.code_end())) = op; | |
| 2376 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 2377 %} | |
| 2378 | |
| 2379 // Utility encoding for loading a 64 bit Pointer into a register | |
| 2380 // The 64 bit pointer is stored in the generated code stream | |
| 2381 enc_class SetPtr( immP src, iRegP rd ) %{ | |
| 2382 Register dest = reg_to_register_object($rd$$reg); | |
| 727 | 2383 MacroAssembler _masm(&cbuf); |
| 0 | 2384 // [RGV] This next line should be generated from ADLC |
| 2385 if ( _opnds[1]->constant_is_oop() ) { | |
| 2386 intptr_t val = $src$$constant; | |
| 2387 __ set_oop_constant((jobject)val, dest); | |
| 2388 } else { // non-oop pointers, e.g. card mark base, heap top | |
| 727 | 2389 __ set($src$$constant, dest); |
| 0 | 2390 } |
| 2391 %} | |
| 2392 | |
| 2393 enc_class Set13( immI13 src, iRegI rd ) %{ | |
| 2394 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant ); | |
| 2395 %} | |
| 2396 | |
| 2397 enc_class SetHi22( immI src, iRegI rd ) %{ | |
| 2398 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant ); | |
| 2399 %} | |
| 2400 | |
| 2401 enc_class Set32( immI src, iRegI rd ) %{ | |
| 2402 MacroAssembler _masm(&cbuf); | |
| 2403 __ set($src$$constant, reg_to_register_object($rd$$reg)); | |
| 2404 %} | |
| 2405 | |
| 2406 enc_class SetNull( iRegI rd ) %{ | |
| 2407 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0 ); | |
| 2408 %} | |
| 2409 | |
| 2410 enc_class call_epilog %{ | |
| 2411 if( VerifyStackAtCalls ) { | |
| 2412 MacroAssembler _masm(&cbuf); | |
| 2413 int framesize = ra_->C->frame_slots() << LogBytesPerInt; | |
| 2414 Register temp_reg = G3; | |
| 2415 __ add(SP, framesize, temp_reg); | |
| 2416 __ cmp(temp_reg, FP); | |
| 2417 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc); | |
| 2418 } | |
| 2419 %} | |
| 2420 | |
| 2421 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value | |
| 2422 // to G1 so the register allocator will not have to deal with the misaligned register | |
| 2423 // pair. | |
| 2424 enc_class adjust_long_from_native_call %{ | |
| 2425 #ifndef _LP64 | |
| 2426 if (returns_long()) { | |
| 2427 // sllx O0,32,O0 | |
| 2428 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 ); | |
| 2429 // srl O1,0,O1 | |
| 2430 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 ); | |
| 2431 // or O0,O1,G1 | |
| 2432 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc ); | |
| 2433 } | |
| 2434 #endif | |
| 2435 %} | |
| 2436 | |
| 2437 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime | |
| 2438 // CALL directly to the runtime | |
| 2439 // The user of this is responsible for ensuring that R_L7 is empty (killed). | |
| 2440 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type, | |
| 2441 /*preserve_g2=*/true, /*force far call*/true); | |
| 2442 %} | |
| 2443 | |
| 2444 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL | |
| 2445 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
| 2446 // who we intended to call. | |
| 2447 if ( !_method ) { | |
| 2448 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type); | |
| 2449 } else if (_optimized_virtual) { | |
| 2450 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type); | |
| 2451 } else { | |
| 2452 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type); | |
| 2453 } | |
| 2454 if( _method ) { // Emit stub for static call | |
| 2455 emit_java_to_interp(cbuf); | |
| 2456 } | |
| 2457 %} | |
| 2458 | |
| 2459 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL | |
| 2460 MacroAssembler _masm(&cbuf); | |
| 2461 __ set_inst_mark(); | |
| 2462 int vtable_index = this->_vtable_index; | |
| 2463 // MachCallDynamicJavaNode::ret_addr_offset uses this same test | |
| 2464 if (vtable_index < 0) { | |
| 2465 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
| 2466 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); | |
| 2467 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
| 2468 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()"); | |
| 2469 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub"); | |
| 2470 // !!!!! | |
| 2471 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info | |
| 2472 // emit_call_dynamic_prologue( cbuf ); | |
| 2473 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg); | |
| 2474 | |
| 2475 address virtual_call_oop_addr = __ inst_mark(); | |
| 2476 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
| 2477 // who we intended to call. | |
| 2478 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr)); | |
| 2479 emit_call_reloc(cbuf, $meth$$method, relocInfo::none); | |
| 2480 } else { | |
| 2481 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
| 2482 // Just go thru the vtable | |
| 2483 // get receiver klass (receiver already checked for non-null) | |
| 2484 // If we end up going thru a c2i adapter interpreter expects method in G5 | |
| 2485 int off = __ offset(); | |
|
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2486 __ load_klass(O0, G3_scratch); |
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2487 int klass_load_size; |
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2488 if (UseCompressedOops) { |
|
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2489 assert(Universe::heap() != NULL, "java heap should be initialized"); |
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2490 if (Universe::narrow_oop_base() == NULL) |
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2491 klass_load_size = 2*BytesPerInstWord; |
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2492 else |
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2493 klass_load_size = 3*BytesPerInstWord; |
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2494 } else { |
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2495 klass_load_size = 1*BytesPerInstWord; |
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2496 } |
| 0 | 2497 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); |
| 2498 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); | |
| 2499 if( __ is_simm13(v_off) ) { | |
| 2500 __ ld_ptr(G3, v_off, G5_method); | |
| 2501 } else { | |
| 2502 // Generate 2 instructions | |
| 2503 __ Assembler::sethi(v_off & ~0x3ff, G5_method); | |
| 2504 __ or3(G5_method, v_off & 0x3ff, G5_method); | |
| 2505 // ld_ptr, set_hi, set | |
|
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2506 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord, |
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2507 "Unexpected instruction size(s)"); |
| 0 | 2508 __ ld_ptr(G3, G5_method, G5_method); |
| 2509 } | |
| 2510 // NOTE: for vtable dispatches, the vtable entry will never be null. | |
| 2511 // However it may very well end up in handle_wrong_method if the | |
| 2512 // method is abstract for the particular class. | |
| 2513 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch); | |
| 2514 // jump to target (either compiled code or c2iadapter) | |
| 2515 __ jmpl(G3_scratch, G0, O7); | |
| 2516 __ delayed()->nop(); | |
| 2517 } | |
| 2518 %} | |
| 2519 | |
| 2520 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL | |
| 2521 MacroAssembler _masm(&cbuf); | |
| 2522 | |
| 2523 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
| 2524 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because | |
| 2525 // we might be calling a C2I adapter which needs it. | |
| 2526 | |
| 2527 assert(temp_reg != G5_ic_reg, "conflicting registers"); | |
| 2528 // Load nmethod | |
| 2529 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg); | |
| 2530 | |
| 2531 // CALL to compiled java, indirect the contents of G3 | |
| 2532 __ set_inst_mark(); | |
| 2533 __ callr(temp_reg, G0); | |
| 2534 __ delayed()->nop(); | |
| 2535 %} | |
| 2536 | |
| 2537 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{ | |
| 2538 MacroAssembler _masm(&cbuf); | |
| 2539 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2540 Register Rdivisor = reg_to_register_object($src2$$reg); | |
| 2541 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2542 | |
| 2543 __ sra(Rdivisor, 0, Rdivisor); | |
| 2544 __ sra(Rdividend, 0, Rdividend); | |
| 2545 __ sdivx(Rdividend, Rdivisor, Rresult); | |
| 2546 %} | |
| 2547 | |
| 2548 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{ | |
| 2549 MacroAssembler _masm(&cbuf); | |
| 2550 | |
| 2551 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2552 int divisor = $imm$$constant; | |
| 2553 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2554 | |
| 2555 __ sra(Rdividend, 0, Rdividend); | |
| 2556 __ sdivx(Rdividend, divisor, Rresult); | |
| 2557 %} | |
| 2558 | |
| 2559 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{ | |
| 2560 MacroAssembler _masm(&cbuf); | |
| 2561 Register Rsrc1 = reg_to_register_object($src1$$reg); | |
| 2562 Register Rsrc2 = reg_to_register_object($src2$$reg); | |
| 2563 Register Rdst = reg_to_register_object($dst$$reg); | |
| 2564 | |
| 2565 __ sra( Rsrc1, 0, Rsrc1 ); | |
| 2566 __ sra( Rsrc2, 0, Rsrc2 ); | |
| 2567 __ mulx( Rsrc1, Rsrc2, Rdst ); | |
| 2568 __ srlx( Rdst, 32, Rdst ); | |
| 2569 %} | |
| 2570 | |
| 2571 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{ | |
| 2572 MacroAssembler _masm(&cbuf); | |
| 2573 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2574 Register Rdivisor = reg_to_register_object($src2$$reg); | |
| 2575 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2576 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2577 | |
| 2578 assert(Rdividend != Rscratch, ""); | |
| 2579 assert(Rdivisor != Rscratch, ""); | |
| 2580 | |
| 2581 __ sra(Rdividend, 0, Rdividend); | |
| 2582 __ sra(Rdivisor, 0, Rdivisor); | |
| 2583 __ sdivx(Rdividend, Rdivisor, Rscratch); | |
| 2584 __ mulx(Rscratch, Rdivisor, Rscratch); | |
| 2585 __ sub(Rdividend, Rscratch, Rresult); | |
| 2586 %} | |
| 2587 | |
| 2588 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{ | |
| 2589 MacroAssembler _masm(&cbuf); | |
| 2590 | |
| 2591 Register Rdividend = reg_to_register_object($src1$$reg); | |
| 2592 int divisor = $imm$$constant; | |
| 2593 Register Rresult = reg_to_register_object($dst$$reg); | |
| 2594 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2595 | |
| 2596 assert(Rdividend != Rscratch, ""); | |
| 2597 | |
| 2598 __ sra(Rdividend, 0, Rdividend); | |
| 2599 __ sdivx(Rdividend, divisor, Rscratch); | |
| 2600 __ mulx(Rscratch, divisor, Rscratch); | |
| 2601 __ sub(Rdividend, Rscratch, Rresult); | |
| 2602 %} | |
| 2603 | |
| 2604 enc_class fabss (sflt_reg dst, sflt_reg src) %{ | |
| 2605 MacroAssembler _masm(&cbuf); | |
| 2606 | |
| 2607 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
| 2608 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
| 2609 | |
| 2610 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst); | |
| 2611 %} | |
| 2612 | |
| 2613 enc_class fabsd (dflt_reg dst, dflt_reg src) %{ | |
| 2614 MacroAssembler _masm(&cbuf); | |
| 2615 | |
| 2616 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2617 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2618 | |
| 2619 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2620 %} | |
| 2621 | |
| 2622 enc_class fnegd (dflt_reg dst, dflt_reg src) %{ | |
| 2623 MacroAssembler _masm(&cbuf); | |
| 2624 | |
| 2625 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2626 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2627 | |
| 2628 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2629 %} | |
| 2630 | |
| 2631 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{ | |
| 2632 MacroAssembler _masm(&cbuf); | |
| 2633 | |
| 2634 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
| 2635 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
| 2636 | |
| 2637 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst); | |
| 2638 %} | |
| 2639 | |
| 2640 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{ | |
| 2641 MacroAssembler _masm(&cbuf); | |
| 2642 | |
| 2643 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2644 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2645 | |
| 2646 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2647 %} | |
| 2648 | |
| 2649 enc_class fmovs (dflt_reg dst, dflt_reg src) %{ | |
| 2650 MacroAssembler _masm(&cbuf); | |
| 2651 | |
| 2652 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
| 2653 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
| 2654 | |
| 2655 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst); | |
| 2656 %} | |
| 2657 | |
| 2658 enc_class fmovd (dflt_reg dst, dflt_reg src) %{ | |
| 2659 MacroAssembler _masm(&cbuf); | |
| 2660 | |
| 2661 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
| 2662 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
| 2663 | |
| 2664 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst); | |
| 2665 %} | |
| 2666 | |
| 2667 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
| 2668 MacroAssembler _masm(&cbuf); | |
| 2669 | |
| 2670 Register Roop = reg_to_register_object($oop$$reg); | |
| 2671 Register Rbox = reg_to_register_object($box$$reg); | |
| 2672 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2673 Register Rmark = reg_to_register_object($scratch2$$reg); | |
| 2674 | |
| 2675 assert(Roop != Rscratch, ""); | |
| 2676 assert(Roop != Rmark, ""); | |
| 2677 assert(Rbox != Rscratch, ""); | |
| 2678 assert(Rbox != Rmark, ""); | |
| 2679 | |
|
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|
2680 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining); |
| 0 | 2681 %} |
| 2682 | |
| 2683 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
| 2684 MacroAssembler _masm(&cbuf); | |
| 2685 | |
| 2686 Register Roop = reg_to_register_object($oop$$reg); | |
| 2687 Register Rbox = reg_to_register_object($box$$reg); | |
| 2688 Register Rscratch = reg_to_register_object($scratch$$reg); | |
| 2689 Register Rmark = reg_to_register_object($scratch2$$reg); | |
| 2690 | |
| 2691 assert(Roop != Rscratch, ""); | |
| 2692 assert(Roop != Rmark, ""); | |
| 2693 assert(Rbox != Rscratch, ""); | |
| 2694 assert(Rbox != Rmark, ""); | |
| 2695 | |
|
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diff
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|
2696 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining); |
| 0 | 2697 %} |
| 2698 | |
| 2699 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{ | |
| 2700 MacroAssembler _masm(&cbuf); | |
| 2701 Register Rmem = reg_to_register_object($mem$$reg); | |
| 2702 Register Rold = reg_to_register_object($old$$reg); | |
| 2703 Register Rnew = reg_to_register_object($new$$reg); | |
| 2704 | |
| 2705 // casx_under_lock picks 1 of 3 encodings: | |
| 2706 // For 32-bit pointers you get a 32-bit CAS | |
| 2707 // For 64-bit pointers you get a 64-bit CASX | |
|
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2708 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold |
| 0 | 2709 __ cmp( Rold, Rnew ); |
| 2710 %} | |
| 2711 | |
| 2712 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{ | |
| 2713 Register Rmem = reg_to_register_object($mem$$reg); | |
| 2714 Register Rold = reg_to_register_object($old$$reg); | |
| 2715 Register Rnew = reg_to_register_object($new$$reg); | |
| 2716 | |
| 2717 MacroAssembler _masm(&cbuf); | |
| 2718 __ mov(Rnew, O7); | |
| 2719 __ casx(Rmem, Rold, O7); | |
| 2720 __ cmp( Rold, O7 ); | |
| 2721 %} | |
| 2722 | |
| 2723 // raw int cas, used for compareAndSwap | |
| 2724 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{ | |
| 2725 Register Rmem = reg_to_register_object($mem$$reg); | |
| 2726 Register Rold = reg_to_register_object($old$$reg); | |
| 2727 Register Rnew = reg_to_register_object($new$$reg); | |
| 2728 | |
| 2729 MacroAssembler _masm(&cbuf); | |
| 2730 __ mov(Rnew, O7); | |
| 2731 __ cas(Rmem, Rold, O7); | |
| 2732 __ cmp( Rold, O7 ); | |
| 2733 %} | |
| 2734 | |
| 2735 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{ | |
| 2736 Register Rres = reg_to_register_object($res$$reg); | |
| 2737 | |
| 2738 MacroAssembler _masm(&cbuf); | |
| 2739 __ mov(1, Rres); | |
| 2740 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres ); | |
| 2741 %} | |
| 2742 | |
| 2743 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{ | |
| 2744 Register Rres = reg_to_register_object($res$$reg); | |
| 2745 | |
| 2746 MacroAssembler _masm(&cbuf); | |
| 2747 __ mov(1, Rres); | |
| 2748 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres ); | |
| 2749 %} | |
| 2750 | |
| 2751 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{ | |
| 2752 MacroAssembler _masm(&cbuf); | |
| 2753 Register Rdst = reg_to_register_object($dst$$reg); | |
| 2754 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg) | |
| 2755 : reg_to_DoubleFloatRegister_object($src1$$reg); | |
| 2756 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg) | |
| 2757 : reg_to_DoubleFloatRegister_object($src2$$reg); | |
| 2758 | |
| 2759 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1) | |
| 2760 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst); | |
| 2761 %} | |
| 2762 | |
| 2763 enc_class LdImmL (immL src, iRegL dst, o7RegL tmp) %{ // Load Immediate | |
| 2764 MacroAssembler _masm(&cbuf); | |
| 2765 Register dest = reg_to_register_object($dst$$reg); | |
| 2766 Register temp = reg_to_register_object($tmp$$reg); | |
| 2767 __ set64( $src$$constant, dest, temp ); | |
| 2768 %} | |
| 2769 | |
| 2770 enc_class LdReplImmI(immI src, regD dst, o7RegP tmp, int count, int width) %{ | |
| 2771 // Load a constant replicated "count" times with width "width" | |
| 2772 int bit_width = $width$$constant * 8; | |
| 2773 jlong elt_val = $src$$constant; | |
| 2774 elt_val &= (((jlong)1) << bit_width) - 1; // mask off sign bits | |
| 2775 jlong val = elt_val; | |
| 2776 for (int i = 0; i < $count$$constant - 1; i++) { | |
| 2777 val <<= bit_width; | |
| 2778 val |= elt_val; | |
| 2779 } | |
| 2780 jdouble dval = *(jdouble*)&val; // coerce to double type | |
| 727 | 2781 MacroAssembler _masm(&cbuf); |
| 2782 address double_address = __ double_constant(dval); | |
| 0 | 2783 RelocationHolder rspec = internal_word_Relocation::spec(double_address); |
| 727 | 2784 AddressLiteral addrlit(double_address, rspec); |
| 2785 | |
| 2786 __ sethi(addrlit, $tmp$$Register); | |
|
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|
2787 // XXX This is a quick fix for 6833573. |
|
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|
2788 //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec); |
|
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|
2789 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec); |
| 0 | 2790 %} |
| 2791 | |
| 2792 // Compiler ensures base is doubleword aligned and cnt is count of doublewords | |
| 2793 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{ | |
| 2794 MacroAssembler _masm(&cbuf); | |
| 2795 Register nof_bytes_arg = reg_to_register_object($cnt$$reg); | |
| 2796 Register nof_bytes_tmp = reg_to_register_object($temp$$reg); | |
| 2797 Register base_pointer_arg = reg_to_register_object($base$$reg); | |
| 2798 | |
| 2799 Label loop; | |
| 2800 __ mov(nof_bytes_arg, nof_bytes_tmp); | |
| 2801 | |
| 2802 // Loop and clear, walking backwards through the array. | |
| 2803 // nof_bytes_tmp (if >0) is always the number of bytes to zero | |
| 2804 __ bind(loop); | |
| 2805 __ deccc(nof_bytes_tmp, 8); | |
| 2806 __ br(Assembler::greaterEqual, true, Assembler::pt, loop); | |
| 2807 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp); | |
| 2808 // %%%% this mini-loop must not cross a cache boundary! | |
| 2809 %} | |
| 2810 | |
| 2811 | |
|
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2812 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{ |
| 0 | 2813 Label Ldone, Lloop; |
| 2814 MacroAssembler _masm(&cbuf); | |
| 2815 | |
| 2816 Register str1_reg = reg_to_register_object($str1$$reg); | |
| 2817 Register str2_reg = reg_to_register_object($str2$$reg); | |
|
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2818 Register cnt1_reg = reg_to_register_object($cnt1$$reg); |
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2819 Register cnt2_reg = reg_to_register_object($cnt2$$reg); |
| 0 | 2820 Register result_reg = reg_to_register_object($result$$reg); |
| 2821 | |
|
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2822 assert(result_reg != str1_reg && |
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2823 result_reg != str2_reg && |
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2824 result_reg != cnt1_reg && |
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2825 result_reg != cnt2_reg , |
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2826 "need different registers"); |
| 0 | 2827 |
| 2828 // Compute the minimum of the string lengths(str1_reg) and the | |
| 2829 // difference of the string lengths (stack) | |
| 2830 | |
| 2831 // See if the lengths are different, and calculate min in str1_reg. | |
| 2832 // Stash diff in O7 in case we need it for a tie-breaker. | |
| 2833 Label Lskip; | |
|
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2834 __ subcc(cnt1_reg, cnt2_reg, O7); |
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2835 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit |
| 0 | 2836 __ br(Assembler::greater, true, Assembler::pt, Lskip); |
|
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2837 // cnt2 is shorter, so use its count: |
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2838 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit |
| 0 | 2839 __ bind(Lskip); |
| 2840 | |
|
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2841 // reallocate cnt1_reg, cnt2_reg, result_reg |
| 0 | 2842 // Note: limit_reg holds the string length pre-scaled by 2 |
|
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2843 Register limit_reg = cnt1_reg; |
|
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2844 Register chr2_reg = cnt2_reg; |
| 0 | 2845 Register chr1_reg = result_reg; |
|
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2846 // str{12} are the base pointers |
| 0 | 2847 |
| 2848 // Is the minimum length zero? | |
| 2849 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity | |
| 2850 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
| 2851 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
| 2852 | |
| 2853 // Load first characters | |
|
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2854 __ lduh(str1_reg, 0, chr1_reg); |
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2855 __ lduh(str2_reg, 0, chr2_reg); |
| 0 | 2856 |
| 2857 // Compare first characters | |
| 2858 __ subcc(chr1_reg, chr2_reg, chr1_reg); | |
| 2859 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
| 2860 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
| 2861 __ delayed()->nop(); | |
| 2862 | |
| 2863 { | |
| 2864 // Check after comparing first character to see if strings are equivalent | |
| 2865 Label LSkip2; | |
| 2866 // Check if the strings start at same location | |
|
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2867 __ cmp(str1_reg, str2_reg); |
| 0 | 2868 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2); |
| 2869 __ delayed()->nop(); | |
| 2870 | |
| 2871 // Check if the length difference is zero (in O7) | |
| 2872 __ cmp(G0, O7); | |
| 2873 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
| 2874 __ delayed()->mov(G0, result_reg); // result is zero | |
| 2875 | |
| 2876 // Strings might not be equal | |
| 2877 __ bind(LSkip2); | |
| 2878 } | |
| 2879 | |
| 2880 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg); | |
| 2881 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
| 2882 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
| 2883 | |
|
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2884 // Shift str1_reg and str2_reg to the end of the arrays, negate limit |
|
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2885 __ add(str1_reg, limit_reg, str1_reg); |
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2886 __ add(str2_reg, limit_reg, str2_reg); |
| 0 | 2887 __ neg(chr1_reg, limit_reg); // limit = -(limit-2) |
| 2888 | |
| 2889 // Compare the rest of the characters | |
|
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2890 __ lduh(str1_reg, limit_reg, chr1_reg); |
| 0 | 2891 __ bind(Lloop); |
|
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2892 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
|
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2893 __ lduh(str2_reg, limit_reg, chr2_reg); |
| 0 | 2894 __ subcc(chr1_reg, chr2_reg, chr1_reg); |
| 2895 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
| 2896 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
| 2897 __ delayed()->inccc(limit_reg, sizeof(jchar)); | |
| 2898 // annul LDUH if branch is not taken to prevent access past end of string | |
| 2899 __ br(Assembler::notZero, true, Assembler::pt, Lloop); | |
|
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2900 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
| 0 | 2901 |
| 2902 // If strings are equal up to min length, return the length difference. | |
| 2903 __ mov(O7, result_reg); | |
| 2904 | |
| 2905 // Otherwise, return the difference between the first mismatched chars. | |
| 2906 __ bind(Ldone); | |
| 2907 %} | |
| 2908 | |
|
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2909 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{ |
|
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2910 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone; |
| 681 | 2911 MacroAssembler _masm(&cbuf); |
| 2912 | |
| 2913 Register str1_reg = reg_to_register_object($str1$$reg); | |
| 2914 Register str2_reg = reg_to_register_object($str2$$reg); | |
|
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2915 Register cnt_reg = reg_to_register_object($cnt$$reg); |
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2916 Register tmp1_reg = O7; |
| 681 | 2917 Register result_reg = reg_to_register_object($result$$reg); |
| 2918 | |
|
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2919 assert(result_reg != str1_reg && |
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2920 result_reg != str2_reg && |
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2921 result_reg != cnt_reg && |
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2922 result_reg != tmp1_reg , |
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2923 "need different registers"); |
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2924 |
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|
2925 __ cmp(str1_reg, str2_reg); //same char[] ? |
| 681 | 2926 __ brx(Assembler::equal, true, Assembler::pn, Ldone); |
| 2927 __ delayed()->add(G0, 1, result_reg); | |
| 2928 | |
|
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2929 __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, cnt_reg, Ldone); |
|
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2930 __ delayed()->add(G0, 1, result_reg); // count == 0 |
|
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2931 |
| 681 | 2932 //rename registers |
|
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2933 Register limit_reg = cnt_reg; |
| 681 | 2934 Register chr1_reg = result_reg; |
|
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2935 Register chr2_reg = tmp1_reg; |
| 681 | 2936 |
| 2937 //check for alignment and position the pointers to the ends | |
|
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2938 __ or3(str1_reg, str2_reg, chr1_reg); |
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2939 __ andcc(chr1_reg, 0x3, chr1_reg); |
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2940 // notZero means at least one not 4-byte aligned. |
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2941 // We could optimize the case when both arrays are not aligned |
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2942 // but it is not frequent case and it requires additional checks. |
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2943 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare |
|
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2944 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count |
|
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2945 |
|
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2946 // Compare char[] arrays aligned to 4 bytes. |
|
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2947 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg, |
|
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|
2948 chr1_reg, chr2_reg, Ldone); |
| 681 | 2949 __ ba(false,Ldone); |
| 2950 __ delayed()->add(G0, 1, result_reg); | |
| 2951 | |
|
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2952 // char by char compare |
| 681 | 2953 __ bind(Lchar); |
|
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|
2954 __ add(str1_reg, limit_reg, str1_reg); |
|
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|
2955 __ add(str2_reg, limit_reg, str2_reg); |
| 681 | 2956 __ neg(limit_reg); //negate count |
| 2957 | |
|
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2958 __ lduh(str1_reg, limit_reg, chr1_reg); |
|
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2959 // Lchar_loop |
| 681 | 2960 __ bind(Lchar_loop); |
|
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|
2961 __ lduh(str2_reg, limit_reg, chr2_reg); |
| 681 | 2962 __ cmp(chr1_reg, chr2_reg); |
| 2963 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); | |
| 2964 __ delayed()->mov(G0, result_reg); //not equal | |
| 2965 __ inccc(limit_reg, sizeof(jchar)); | |
| 2966 // annul LDUH if branch is not taken to prevent access past end of string | |
|
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2967 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop); |
|
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|
2968 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
| 681 | 2969 |
| 2970 __ add(G0, 1, result_reg); //equal | |
| 2971 | |
| 2972 __ bind(Ldone); | |
| 2973 %} | |
| 2974 | |
|
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|
2975 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{ |
| 681 | 2976 Label Lvector, Ldone, Lloop; |
| 2977 MacroAssembler _masm(&cbuf); | |
| 2978 | |
| 2979 Register ary1_reg = reg_to_register_object($ary1$$reg); | |
| 2980 Register ary2_reg = reg_to_register_object($ary2$$reg); | |
| 2981 Register tmp1_reg = reg_to_register_object($tmp1$$reg); | |
|
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2982 Register tmp2_reg = O7; |
| 681 | 2983 Register result_reg = reg_to_register_object($result$$reg); |
| 2984 | |
| 2985 int length_offset = arrayOopDesc::length_offset_in_bytes(); | |
| 2986 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); | |
| 2987 | |
| 2988 // return true if the same array | |
| 2989 __ cmp(ary1_reg, ary2_reg); | |
| 1016 | 2990 __ brx(Assembler::equal, true, Assembler::pn, Ldone); |
| 681 | 2991 __ delayed()->add(G0, 1, result_reg); // equal |
| 2992 | |
| 2993 __ br_null(ary1_reg, true, Assembler::pn, Ldone); | |
| 2994 __ delayed()->mov(G0, result_reg); // not equal | |
| 2995 | |
| 2996 __ br_null(ary2_reg, true, Assembler::pn, Ldone); | |
| 2997 __ delayed()->mov(G0, result_reg); // not equal | |
| 2998 | |
| 2999 //load the lengths of arrays | |
| 727 | 3000 __ ld(Address(ary1_reg, length_offset), tmp1_reg); |
| 3001 __ ld(Address(ary2_reg, length_offset), tmp2_reg); | |
| 681 | 3002 |
| 3003 // return false if the two arrays are not equal length | |
| 3004 __ cmp(tmp1_reg, tmp2_reg); | |
| 3005 __ br(Assembler::notEqual, true, Assembler::pn, Ldone); | |
| 3006 __ delayed()->mov(G0, result_reg); // not equal | |
| 3007 | |
|
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3008 __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, tmp1_reg, Ldone); |
| 681 | 3009 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal |
| 3010 | |
| 3011 // load array addresses | |
| 3012 __ add(ary1_reg, base_offset, ary1_reg); | |
| 3013 __ add(ary2_reg, base_offset, ary2_reg); | |
| 3014 | |
| 3015 // renaming registers | |
|
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|
3016 Register chr1_reg = result_reg; // for characters in ary1 |
|
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3017 Register chr2_reg = tmp2_reg; // for characters in ary2 |
| 681 | 3018 Register limit_reg = tmp1_reg; // length |
| 3019 | |
| 3020 // set byte count | |
| 3021 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); | |
|
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|
3022 |
|
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3023 // Compare char[] arrays aligned to 4 bytes. |
|
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3024 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg, |
|
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3025 chr1_reg, chr2_reg, Ldone); |
| 681 | 3026 __ add(G0, 1, result_reg); // equals |
| 3027 | |
| 3028 __ bind(Ldone); | |
| 3029 %} | |
| 3030 | |
| 0 | 3031 enc_class enc_rethrow() %{ |
| 3032 cbuf.set_inst_mark(); | |
| 3033 Register temp_reg = G3; | |
| 727 | 3034 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub()); |
| 0 | 3035 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg"); |
| 3036 MacroAssembler _masm(&cbuf); | |
| 3037 #ifdef ASSERT | |
| 3038 __ save_frame(0); | |
| 727 | 3039 AddressLiteral last_rethrow_addrlit(&last_rethrow); |
| 3040 __ sethi(last_rethrow_addrlit, L1); | |
| 3041 Address addr(L1, last_rethrow_addrlit.low10()); | |
| 0 | 3042 __ get_pc(L2); |
| 3043 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to | |
| 727 | 3044 __ st_ptr(L2, addr); |
| 0 | 3045 __ restore(); |
| 3046 #endif | |
| 727 | 3047 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp |
| 0 | 3048 __ delayed()->nop(); |
| 3049 %} | |
| 3050 | |
| 3051 enc_class emit_mem_nop() %{ | |
| 3052 // Generates the instruction LDUXA [o6,g0],#0x82,g0 | |
| 3053 unsigned int *code = (unsigned int*)cbuf.code_end(); | |
| 3054 *code = (unsigned int)0xc0839040; | |
| 3055 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 3056 %} | |
| 3057 | |
| 3058 enc_class emit_fadd_nop() %{ | |
| 3059 // Generates the instruction FMOVS f31,f31 | |
| 3060 unsigned int *code = (unsigned int*)cbuf.code_end(); | |
| 3061 *code = (unsigned int)0xbfa0003f; | |
| 3062 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 3063 %} | |
| 3064 | |
| 3065 enc_class emit_br_nop() %{ | |
| 3066 // Generates the instruction BPN,PN . | |
| 3067 unsigned int *code = (unsigned int*)cbuf.code_end(); | |
| 3068 *code = (unsigned int)0x00400000; | |
| 3069 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
| 3070 %} | |
| 3071 | |
| 3072 enc_class enc_membar_acquire %{ | |
| 3073 MacroAssembler _masm(&cbuf); | |
| 3074 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) ); | |
| 3075 %} | |
| 3076 | |
| 3077 enc_class enc_membar_release %{ | |
| 3078 MacroAssembler _masm(&cbuf); | |
| 3079 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) ); | |
| 3080 %} | |
| 3081 | |
| 3082 enc_class enc_membar_volatile %{ | |
| 3083 MacroAssembler _masm(&cbuf); | |
| 3084 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); | |
| 3085 %} | |
|
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3086 |
| 0 | 3087 enc_class enc_repl8b( iRegI src, iRegL dst ) %{ |
| 3088 MacroAssembler _masm(&cbuf); | |
| 3089 Register src_reg = reg_to_register_object($src$$reg); | |
| 3090 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 3091 __ sllx(src_reg, 56, dst_reg); | |
| 3092 __ srlx(dst_reg, 8, O7); | |
| 3093 __ or3 (dst_reg, O7, dst_reg); | |
| 3094 __ srlx(dst_reg, 16, O7); | |
| 3095 __ or3 (dst_reg, O7, dst_reg); | |
| 3096 __ srlx(dst_reg, 32, O7); | |
| 3097 __ or3 (dst_reg, O7, dst_reg); | |
| 3098 %} | |
| 3099 | |
| 3100 enc_class enc_repl4b( iRegI src, iRegL dst ) %{ | |
| 3101 MacroAssembler _masm(&cbuf); | |
| 3102 Register src_reg = reg_to_register_object($src$$reg); | |
| 3103 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 3104 __ sll(src_reg, 24, dst_reg); | |
| 3105 __ srl(dst_reg, 8, O7); | |
| 3106 __ or3(dst_reg, O7, dst_reg); | |
| 3107 __ srl(dst_reg, 16, O7); | |
| 3108 __ or3(dst_reg, O7, dst_reg); | |
| 3109 %} | |
| 3110 | |
| 3111 enc_class enc_repl4s( iRegI src, iRegL dst ) %{ | |
| 3112 MacroAssembler _masm(&cbuf); | |
| 3113 Register src_reg = reg_to_register_object($src$$reg); | |
| 3114 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 3115 __ sllx(src_reg, 48, dst_reg); | |
| 3116 __ srlx(dst_reg, 16, O7); | |
| 3117 __ or3 (dst_reg, O7, dst_reg); | |
| 3118 __ srlx(dst_reg, 32, O7); | |
| 3119 __ or3 (dst_reg, O7, dst_reg); | |
| 3120 %} | |
| 3121 | |
| 3122 enc_class enc_repl2i( iRegI src, iRegL dst ) %{ | |
| 3123 MacroAssembler _masm(&cbuf); | |
| 3124 Register src_reg = reg_to_register_object($src$$reg); | |
| 3125 Register dst_reg = reg_to_register_object($dst$$reg); | |
| 3126 __ sllx(src_reg, 32, dst_reg); | |
| 3127 __ srlx(dst_reg, 32, O7); | |
| 3128 __ or3 (dst_reg, O7, dst_reg); | |
| 3129 %} | |
| 3130 | |
| 3131 %} | |
| 3132 | |
| 3133 //----------FRAME-------------------------------------------------------------- | |
| 3134 // Definition of frame structure and management information. | |
| 3135 // | |
| 3136 // S T A C K L A Y O U T Allocators stack-slot number | |
| 3137 // | (to get allocators register number | |
| 3138 // G Owned by | | v add VMRegImpl::stack0) | |
| 3139 // r CALLER | | | |
| 3140 // o | +--------+ pad to even-align allocators stack-slot | |
| 3141 // w V | pad0 | numbers; owned by CALLER | |
| 3142 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
| 3143 // h ^ | in | 5 | |
| 3144 // | | args | 4 Holes in incoming args owned by SELF | |
| 3145 // | | | | 3 | |
| 3146 // | | +--------+ | |
| 3147 // V | | old out| Empty on Intel, window on Sparc | |
| 3148 // | old |preserve| Must be even aligned. | |
| 3149 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned | |
| 3150 // | | in | 3 area for Intel ret address | |
| 3151 // Owned by |preserve| Empty on Sparc. | |
| 3152 // SELF +--------+ | |
| 3153 // | | pad2 | 2 pad to align old SP | |
| 3154 // | +--------+ 1 | |
| 3155 // | | locks | 0 | |
| 3156 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned | |
| 3157 // | | pad1 | 11 pad to align new SP | |
| 3158 // | +--------+ | |
| 3159 // | | | 10 | |
| 3160 // | | spills | 9 spills | |
| 3161 // V | | 8 (pad0 slot for callee) | |
| 3162 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
| 3163 // ^ | out | 7 | |
| 3164 // | | args | 6 Holes in outgoing args owned by CALLEE | |
| 3165 // Owned by +--------+ | |
| 3166 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
| 3167 // | new |preserve| Must be even-aligned. | |
| 3168 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
| 3169 // | | | | |
| 3170 // | |
| 3171 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
| 3172 // known from SELF's arguments and the Java calling convention. | |
| 3173 // Region 6-7 is determined per call site. | |
| 3174 // Note 2: If the calling convention leaves holes in the incoming argument | |
| 3175 // area, those holes are owned by SELF. Holes in the outgoing area | |
| 3176 // are owned by the CALLEE. Holes should not be nessecary in the | |
| 3177 // incoming area, as the Java calling convention is completely under | |
| 3178 // the control of the AD file. Doubles can be sorted and packed to | |
| 3179 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
| 3180 // varargs C calling conventions. | |
| 3181 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
| 3182 // even aligned with pad0 as needed. | |
| 3183 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
| 3184 // region 6-11 is even aligned; it may be padded out more so that | |
| 3185 // the region from SP to FP meets the minimum stack alignment. | |
| 3186 | |
| 3187 frame %{ | |
| 3188 // What direction does stack grow in (assumed to be same for native & Java) | |
| 3189 stack_direction(TOWARDS_LOW); | |
| 3190 | |
| 3191 // These two registers define part of the calling convention | |
| 3192 // between compiled code and the interpreter. | |
| 3193 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C | |
| 3194 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter | |
| 3195 | |
| 3196 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] | |
| 3197 cisc_spilling_operand_name(indOffset); | |
| 3198 | |
| 3199 // Number of stack slots consumed by a Monitor enter | |
| 3200 #ifdef _LP64 | |
| 3201 sync_stack_slots(2); | |
| 3202 #else | |
| 3203 sync_stack_slots(1); | |
| 3204 #endif | |
| 3205 | |
| 3206 // Compiled code's Frame Pointer | |
| 3207 frame_pointer(R_SP); | |
| 3208 | |
| 3209 // Stack alignment requirement | |
| 3210 stack_alignment(StackAlignmentInBytes); | |
| 3211 // LP64: Alignment size in bytes (128-bit -> 16 bytes) | |
| 3212 // !LP64: Alignment size in bytes (64-bit -> 8 bytes) | |
| 3213 | |
| 3214 // Number of stack slots between incoming argument block and the start of | |
| 3215 // a new frame. The PROLOG must add this many slots to the stack. The | |
| 3216 // EPILOG must remove this many slots. | |
| 3217 in_preserve_stack_slots(0); | |
| 3218 | |
| 3219 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
| 3220 // for calls to C. Supports the var-args backing area for register parms. | |
| 3221 // ADLC doesn't support parsing expressions, so I folded the math by hand. | |
| 3222 #ifdef _LP64 | |
| 3223 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word | |
| 3224 varargs_C_out_slots_killed(12); | |
| 3225 #else | |
| 3226 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word | |
| 3227 varargs_C_out_slots_killed( 7); | |
| 3228 #endif | |
| 3229 | |
| 3230 // The after-PROLOG location of the return address. Location of | |
| 3231 // return address specifies a type (REG or STACK) and a number | |
| 3232 // representing the register number (i.e. - use a register name) or | |
| 3233 // stack slot. | |
| 3234 return_addr(REG R_I7); // Ret Addr is in register I7 | |
| 3235 | |
| 3236 // Body of function which returns an OptoRegs array locating | |
| 3237 // arguments either in registers or in stack slots for calling | |
| 3238 // java | |
| 3239 calling_convention %{ | |
| 3240 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing); | |
| 3241 | |
| 3242 %} | |
| 3243 | |
| 3244 // Body of function which returns an OptoRegs array locating | |
| 3245 // arguments either in registers or in stack slots for callin | |
| 3246 // C. | |
| 3247 c_calling_convention %{ | |
| 3248 // This is obviously always outgoing | |
| 3249 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); | |
| 3250 %} | |
| 3251 | |
| 3252 // Location of native (C/C++) and interpreter return values. This is specified to | |
| 3253 // be the same as Java. In the 32-bit VM, long values are actually returned from | |
| 3254 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying | |
| 3255 // to and from the register pairs is done by the appropriate call and epilog | |
| 3256 // opcodes. This simplifies the register allocator. | |
| 3257 c_return_value %{ | |
| 3258 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
| 3259 #ifdef _LP64 | |
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3260 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
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3261 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
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3262 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
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3263 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
| 0 | 3264 #else // !_LP64 |
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3265 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3266 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
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3267 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3268 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
| 0 | 3269 #endif |
| 3270 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
| 3271 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
| 3272 %} | |
| 3273 | |
| 3274 // Location of compiled Java return values. Same as C | |
| 3275 return_value %{ | |
| 3276 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
| 3277 #ifdef _LP64 | |
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3278 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
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3279 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
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3280 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
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3281 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
| 0 | 3282 #else // !_LP64 |
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3283 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3284 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
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3285 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3286 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
| 0 | 3287 #endif |
| 3288 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
| 3289 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
| 3290 %} | |
| 3291 | |
| 3292 %} | |
| 3293 | |
| 3294 | |
| 3295 //----------ATTRIBUTES--------------------------------------------------------- | |
| 3296 //----------Operand Attributes------------------------------------------------- | |
| 3297 op_attrib op_cost(1); // Required cost attribute | |
| 3298 | |
| 3299 //----------Instruction Attributes--------------------------------------------- | |
| 3300 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute | |
| 3301 ins_attrib ins_size(32); // Required size attribute (in bits) | |
| 3302 ins_attrib ins_pc_relative(0); // Required PC Relative flag | |
| 3303 ins_attrib ins_short_branch(0); // Required flag: is this instruction a | |
| 3304 // non-matching short branch variant of some | |
| 3305 // long branch? | |
| 3306 | |
| 3307 //----------OPERANDS----------------------------------------------------------- | |
| 3308 // Operand definitions must precede instruction definitions for correct parsing | |
| 3309 // in the ADLC because operands constitute user defined types which are used in | |
| 3310 // instruction definitions. | |
| 3311 | |
| 3312 //----------Simple Operands---------------------------------------------------- | |
| 3313 // Immediate Operands | |
| 3314 // Integer Immediate: 32-bit | |
| 3315 operand immI() %{ | |
| 3316 match(ConI); | |
| 3317 | |
| 3318 op_cost(0); | |
| 3319 // formats are generated automatically for constants and base registers | |
| 3320 format %{ %} | |
| 3321 interface(CONST_INTER); | |
| 3322 %} | |
| 3323 | |
| 824 | 3324 // Integer Immediate: 8-bit |
| 3325 operand immI8() %{ | |
| 3326 predicate(Assembler::is_simm(n->get_int(), 8)); | |
| 3327 match(ConI); | |
| 3328 op_cost(0); | |
| 3329 format %{ %} | |
| 3330 interface(CONST_INTER); | |
| 3331 %} | |
| 3332 | |
| 0 | 3333 // Integer Immediate: 13-bit |
| 3334 operand immI13() %{ | |
| 3335 predicate(Assembler::is_simm13(n->get_int())); | |
| 3336 match(ConI); | |
| 3337 op_cost(0); | |
| 3338 | |
| 3339 format %{ %} | |
| 3340 interface(CONST_INTER); | |
| 3341 %} | |
| 3342 | |
| 785 | 3343 // Integer Immediate: 13-bit minus 7 |
| 3344 operand immI13m7() %{ | |
| 3345 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095)); | |
| 3346 match(ConI); | |
| 3347 op_cost(0); | |
| 3348 | |
| 3349 format %{ %} | |
| 3350 interface(CONST_INTER); | |
| 3351 %} | |
| 3352 | |
| 824 | 3353 // Integer Immediate: 16-bit |
| 3354 operand immI16() %{ | |
| 3355 predicate(Assembler::is_simm(n->get_int(), 16)); | |
| 3356 match(ConI); | |
| 3357 op_cost(0); | |
| 3358 format %{ %} | |
| 3359 interface(CONST_INTER); | |
| 3360 %} | |
| 3361 | |
| 0 | 3362 // Unsigned (positive) Integer Immediate: 13-bit |
| 3363 operand immU13() %{ | |
| 3364 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); | |
| 3365 match(ConI); | |
| 3366 op_cost(0); | |
| 3367 | |
| 3368 format %{ %} | |
| 3369 interface(CONST_INTER); | |
| 3370 %} | |
| 3371 | |
| 3372 // Integer Immediate: 6-bit | |
| 3373 operand immU6() %{ | |
| 3374 predicate(n->get_int() >= 0 && n->get_int() <= 63); | |
| 3375 match(ConI); | |
| 3376 op_cost(0); | |
| 3377 format %{ %} | |
| 3378 interface(CONST_INTER); | |
| 3379 %} | |
| 3380 | |
| 3381 // Integer Immediate: 11-bit | |
| 3382 operand immI11() %{ | |
| 3383 predicate(Assembler::is_simm(n->get_int(),11)); | |
| 3384 match(ConI); | |
| 3385 op_cost(0); | |
| 3386 format %{ %} | |
| 3387 interface(CONST_INTER); | |
| 3388 %} | |
| 3389 | |
| 3390 // Integer Immediate: 0-bit | |
| 3391 operand immI0() %{ | |
| 3392 predicate(n->get_int() == 0); | |
| 3393 match(ConI); | |
| 3394 op_cost(0); | |
| 3395 | |
| 3396 format %{ %} | |
| 3397 interface(CONST_INTER); | |
| 3398 %} | |
| 3399 | |
| 3400 // Integer Immediate: the value 10 | |
| 3401 operand immI10() %{ | |
| 3402 predicate(n->get_int() == 10); | |
| 3403 match(ConI); | |
| 3404 op_cost(0); | |
| 3405 | |
| 3406 format %{ %} | |
| 3407 interface(CONST_INTER); | |
| 3408 %} | |
| 3409 | |
| 3410 // Integer Immediate: the values 0-31 | |
| 3411 operand immU5() %{ | |
| 3412 predicate(n->get_int() >= 0 && n->get_int() <= 31); | |
| 3413 match(ConI); | |
| 3414 op_cost(0); | |
| 3415 | |
| 3416 format %{ %} | |
| 3417 interface(CONST_INTER); | |
| 3418 %} | |
| 3419 | |
| 3420 // Integer Immediate: the values 1-31 | |
| 3421 operand immI_1_31() %{ | |
| 3422 predicate(n->get_int() >= 1 && n->get_int() <= 31); | |
| 3423 match(ConI); | |
| 3424 op_cost(0); | |
| 3425 | |
| 3426 format %{ %} | |
| 3427 interface(CONST_INTER); | |
| 3428 %} | |
| 3429 | |
| 3430 // Integer Immediate: the values 32-63 | |
| 3431 operand immI_32_63() %{ | |
| 3432 predicate(n->get_int() >= 32 && n->get_int() <= 63); | |
| 3433 match(ConI); | |
| 3434 op_cost(0); | |
| 3435 | |
| 3436 format %{ %} | |
| 3437 interface(CONST_INTER); | |
| 3438 %} | |
| 3439 | |
| 785 | 3440 // Immediates for special shifts (sign extend) |
| 3441 | |
| 3442 // Integer Immediate: the value 16 | |
| 3443 operand immI_16() %{ | |
| 3444 predicate(n->get_int() == 16); | |
| 3445 match(ConI); | |
| 3446 op_cost(0); | |
| 3447 | |
| 3448 format %{ %} | |
| 3449 interface(CONST_INTER); | |
| 3450 %} | |
| 3451 | |
| 3452 // Integer Immediate: the value 24 | |
| 3453 operand immI_24() %{ | |
| 3454 predicate(n->get_int() == 24); | |
| 3455 match(ConI); | |
| 3456 op_cost(0); | |
| 3457 | |
| 3458 format %{ %} | |
| 3459 interface(CONST_INTER); | |
| 3460 %} | |
| 3461 | |
| 0 | 3462 // Integer Immediate: the value 255 |
| 3463 operand immI_255() %{ | |
| 3464 predicate( n->get_int() == 255 ); | |
| 3465 match(ConI); | |
| 3466 op_cost(0); | |
| 3467 | |
| 3468 format %{ %} | |
| 3469 interface(CONST_INTER); | |
| 3470 %} | |
| 3471 | |
| 785 | 3472 // Integer Immediate: the value 65535 |
| 3473 operand immI_65535() %{ | |
| 3474 predicate(n->get_int() == 65535); | |
| 3475 match(ConI); | |
| 3476 op_cost(0); | |
| 3477 | |
| 3478 format %{ %} | |
| 3479 interface(CONST_INTER); | |
| 3480 %} | |
| 3481 | |
| 0 | 3482 // Long Immediate: the value FF |
| 3483 operand immL_FF() %{ | |
| 3484 predicate( n->get_long() == 0xFFL ); | |
| 3485 match(ConL); | |
| 3486 op_cost(0); | |
| 3487 | |
| 3488 format %{ %} | |
| 3489 interface(CONST_INTER); | |
| 3490 %} | |
| 3491 | |
| 3492 // Long Immediate: the value FFFF | |
| 3493 operand immL_FFFF() %{ | |
| 3494 predicate( n->get_long() == 0xFFFFL ); | |
| 3495 match(ConL); | |
| 3496 op_cost(0); | |
| 3497 | |
| 3498 format %{ %} | |
| 3499 interface(CONST_INTER); | |
| 3500 %} | |
| 3501 | |
| 3502 // Pointer Immediate: 32 or 64-bit | |
| 3503 operand immP() %{ | |
| 3504 match(ConP); | |
| 3505 | |
| 3506 op_cost(5); | |
| 3507 // formats are generated automatically for constants and base registers | |
| 3508 format %{ %} | |
| 3509 interface(CONST_INTER); | |
| 3510 %} | |
| 3511 | |
| 3512 operand immP13() %{ | |
| 3513 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095)); | |
| 3514 match(ConP); | |
| 3515 op_cost(0); | |
| 3516 | |
| 3517 format %{ %} | |
| 3518 interface(CONST_INTER); | |
| 3519 %} | |
| 3520 | |
| 3521 operand immP0() %{ | |
| 3522 predicate(n->get_ptr() == 0); | |
| 3523 match(ConP); | |
| 3524 op_cost(0); | |
| 3525 | |
| 3526 format %{ %} | |
| 3527 interface(CONST_INTER); | |
| 3528 %} | |
| 3529 | |
| 3530 operand immP_poll() %{ | |
| 3531 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page()); | |
| 3532 match(ConP); | |
| 3533 | |
| 3534 // formats are generated automatically for constants and base registers | |
| 3535 format %{ %} | |
| 3536 interface(CONST_INTER); | |
| 3537 %} | |
| 3538 | |
|
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3539 // Pointer Immediate |
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3540 operand immN() |
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3541 %{ |
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3542 match(ConN); |
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3543 |
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3544 op_cost(10); |
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3545 format %{ %} |
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3546 interface(CONST_INTER); |
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3547 %} |
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3548 |
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3549 // NULL Pointer Immediate |
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3550 operand immN0() |
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3551 %{ |
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3552 predicate(n->get_narrowcon() == 0); |
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3553 match(ConN); |
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3554 |
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3555 op_cost(0); |
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3556 format %{ %} |
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3557 interface(CONST_INTER); |
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3558 %} |
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3559 |
| 0 | 3560 operand immL() %{ |
| 3561 match(ConL); | |
| 3562 op_cost(40); | |
| 3563 // formats are generated automatically for constants and base registers | |
| 3564 format %{ %} | |
| 3565 interface(CONST_INTER); | |
| 3566 %} | |
| 3567 | |
| 3568 operand immL0() %{ | |
| 3569 predicate(n->get_long() == 0L); | |
| 3570 match(ConL); | |
| 3571 op_cost(0); | |
| 3572 // formats are generated automatically for constants and base registers | |
| 3573 format %{ %} | |
| 3574 interface(CONST_INTER); | |
| 3575 %} | |
| 3576 | |
| 3577 // Long Immediate: 13-bit | |
| 3578 operand immL13() %{ | |
| 3579 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L)); | |
| 3580 match(ConL); | |
| 3581 op_cost(0); | |
| 3582 | |
| 3583 format %{ %} | |
| 3584 interface(CONST_INTER); | |
| 3585 %} | |
| 3586 | |
| 785 | 3587 // Long Immediate: 13-bit minus 7 |
| 3588 operand immL13m7() %{ | |
| 3589 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L)); | |
| 3590 match(ConL); | |
| 3591 op_cost(0); | |
| 3592 | |
| 3593 format %{ %} | |
| 3594 interface(CONST_INTER); | |
| 3595 %} | |
| 3596 | |
| 0 | 3597 // Long Immediate: low 32-bit mask |
| 3598 operand immL_32bits() %{ | |
| 3599 predicate(n->get_long() == 0xFFFFFFFFL); | |
| 3600 match(ConL); | |
| 3601 op_cost(0); | |
| 3602 | |
| 3603 format %{ %} | |
| 3604 interface(CONST_INTER); | |
| 3605 %} | |
| 3606 | |
| 3607 // Double Immediate | |
| 3608 operand immD() %{ | |
| 3609 match(ConD); | |
| 3610 | |
| 3611 op_cost(40); | |
| 3612 format %{ %} | |
| 3613 interface(CONST_INTER); | |
| 3614 %} | |
| 3615 | |
| 3616 operand immD0() %{ | |
| 3617 #ifdef _LP64 | |
| 3618 // on 64-bit architectures this comparision is faster | |
| 3619 predicate(jlong_cast(n->getd()) == 0); | |
| 3620 #else | |
| 3621 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO)); | |
| 3622 #endif | |
| 3623 match(ConD); | |
| 3624 | |
| 3625 op_cost(0); | |
| 3626 format %{ %} | |
| 3627 interface(CONST_INTER); | |
| 3628 %} | |
| 3629 | |
| 3630 // Float Immediate | |
| 3631 operand immF() %{ | |
| 3632 match(ConF); | |
| 3633 | |
| 3634 op_cost(20); | |
| 3635 format %{ %} | |
| 3636 interface(CONST_INTER); | |
| 3637 %} | |
| 3638 | |
| 3639 // Float Immediate: 0 | |
| 3640 operand immF0() %{ | |
| 3641 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO)); | |
| 3642 match(ConF); | |
| 3643 | |
| 3644 op_cost(0); | |
| 3645 format %{ %} | |
| 3646 interface(CONST_INTER); | |
| 3647 %} | |
| 3648 | |
| 3649 // Integer Register Operands | |
| 3650 // Integer Register | |
| 3651 operand iRegI() %{ | |
| 3652 constraint(ALLOC_IN_RC(int_reg)); | |
| 3653 match(RegI); | |
| 3654 | |
| 3655 match(notemp_iRegI); | |
| 3656 match(g1RegI); | |
| 3657 match(o0RegI); | |
| 3658 match(iRegIsafe); | |
| 3659 | |
| 3660 format %{ %} | |
| 3661 interface(REG_INTER); | |
| 3662 %} | |
| 3663 | |
| 3664 operand notemp_iRegI() %{ | |
| 3665 constraint(ALLOC_IN_RC(notemp_int_reg)); | |
| 3666 match(RegI); | |
| 3667 | |
| 3668 match(o0RegI); | |
| 3669 | |
| 3670 format %{ %} | |
| 3671 interface(REG_INTER); | |
| 3672 %} | |
| 3673 | |
| 3674 operand o0RegI() %{ | |
| 3675 constraint(ALLOC_IN_RC(o0_regI)); | |
| 3676 match(iRegI); | |
| 3677 | |
| 3678 format %{ %} | |
| 3679 interface(REG_INTER); | |
| 3680 %} | |
| 3681 | |
| 3682 // Pointer Register | |
| 3683 operand iRegP() %{ | |
| 3684 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 3685 match(RegP); | |
| 3686 | |
| 3687 match(lock_ptr_RegP); | |
| 3688 match(g1RegP); | |
| 3689 match(g2RegP); | |
| 3690 match(g3RegP); | |
| 3691 match(g4RegP); | |
| 3692 match(i0RegP); | |
| 3693 match(o0RegP); | |
| 3694 match(o1RegP); | |
| 3695 match(l7RegP); | |
| 3696 | |
| 3697 format %{ %} | |
| 3698 interface(REG_INTER); | |
| 3699 %} | |
| 3700 | |
| 3701 operand sp_ptr_RegP() %{ | |
| 3702 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 3703 match(RegP); | |
| 3704 match(iRegP); | |
| 3705 | |
| 3706 format %{ %} | |
| 3707 interface(REG_INTER); | |
| 3708 %} | |
| 3709 | |
| 3710 operand lock_ptr_RegP() %{ | |
| 3711 constraint(ALLOC_IN_RC(lock_ptr_reg)); | |
| 3712 match(RegP); | |
| 3713 match(i0RegP); | |
| 3714 match(o0RegP); | |
| 3715 match(o1RegP); | |
| 3716 match(l7RegP); | |
| 3717 | |
| 3718 format %{ %} | |
| 3719 interface(REG_INTER); | |
| 3720 %} | |
| 3721 | |
| 3722 operand g1RegP() %{ | |
| 3723 constraint(ALLOC_IN_RC(g1_regP)); | |
| 3724 match(iRegP); | |
| 3725 | |
| 3726 format %{ %} | |
| 3727 interface(REG_INTER); | |
| 3728 %} | |
| 3729 | |
| 3730 operand g2RegP() %{ | |
| 3731 constraint(ALLOC_IN_RC(g2_regP)); | |
| 3732 match(iRegP); | |
| 3733 | |
| 3734 format %{ %} | |
| 3735 interface(REG_INTER); | |
| 3736 %} | |
| 3737 | |
| 3738 operand g3RegP() %{ | |
| 3739 constraint(ALLOC_IN_RC(g3_regP)); | |
| 3740 match(iRegP); | |
| 3741 | |
| 3742 format %{ %} | |
| 3743 interface(REG_INTER); | |
| 3744 %} | |
| 3745 | |
| 3746 operand g1RegI() %{ | |
| 3747 constraint(ALLOC_IN_RC(g1_regI)); | |
| 3748 match(iRegI); | |
| 3749 | |
| 3750 format %{ %} | |
| 3751 interface(REG_INTER); | |
| 3752 %} | |
| 3753 | |
| 3754 operand g3RegI() %{ | |
| 3755 constraint(ALLOC_IN_RC(g3_regI)); | |
| 3756 match(iRegI); | |
| 3757 | |
| 3758 format %{ %} | |
| 3759 interface(REG_INTER); | |
| 3760 %} | |
| 3761 | |
| 3762 operand g4RegI() %{ | |
| 3763 constraint(ALLOC_IN_RC(g4_regI)); | |
| 3764 match(iRegI); | |
| 3765 | |
| 3766 format %{ %} | |
| 3767 interface(REG_INTER); | |
| 3768 %} | |
| 3769 | |
| 3770 operand g4RegP() %{ | |
| 3771 constraint(ALLOC_IN_RC(g4_regP)); | |
| 3772 match(iRegP); | |
| 3773 | |
| 3774 format %{ %} | |
| 3775 interface(REG_INTER); | |
| 3776 %} | |
| 3777 | |
| 3778 operand i0RegP() %{ | |
| 3779 constraint(ALLOC_IN_RC(i0_regP)); | |
| 3780 match(iRegP); | |
| 3781 | |
| 3782 format %{ %} | |
| 3783 interface(REG_INTER); | |
| 3784 %} | |
| 3785 | |
| 3786 operand o0RegP() %{ | |
| 3787 constraint(ALLOC_IN_RC(o0_regP)); | |
| 3788 match(iRegP); | |
| 3789 | |
| 3790 format %{ %} | |
| 3791 interface(REG_INTER); | |
| 3792 %} | |
| 3793 | |
| 3794 operand o1RegP() %{ | |
| 3795 constraint(ALLOC_IN_RC(o1_regP)); | |
| 3796 match(iRegP); | |
| 3797 | |
| 3798 format %{ %} | |
| 3799 interface(REG_INTER); | |
| 3800 %} | |
| 3801 | |
| 3802 operand o2RegP() %{ | |
| 3803 constraint(ALLOC_IN_RC(o2_regP)); | |
| 3804 match(iRegP); | |
| 3805 | |
| 3806 format %{ %} | |
| 3807 interface(REG_INTER); | |
| 3808 %} | |
| 3809 | |
| 3810 operand o7RegP() %{ | |
| 3811 constraint(ALLOC_IN_RC(o7_regP)); | |
| 3812 match(iRegP); | |
| 3813 | |
| 3814 format %{ %} | |
| 3815 interface(REG_INTER); | |
| 3816 %} | |
| 3817 | |
| 3818 operand l7RegP() %{ | |
| 3819 constraint(ALLOC_IN_RC(l7_regP)); | |
| 3820 match(iRegP); | |
| 3821 | |
| 3822 format %{ %} | |
| 3823 interface(REG_INTER); | |
| 3824 %} | |
| 3825 | |
| 3826 operand o7RegI() %{ | |
| 3827 constraint(ALLOC_IN_RC(o7_regI)); | |
| 3828 match(iRegI); | |
| 3829 | |
| 3830 format %{ %} | |
| 3831 interface(REG_INTER); | |
| 3832 %} | |
| 3833 | |
|
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3834 operand iRegN() %{ |
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3835 constraint(ALLOC_IN_RC(int_reg)); |
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3836 match(RegN); |
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3837 |
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3838 format %{ %} |
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3839 interface(REG_INTER); |
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3840 %} |
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3841 |
| 0 | 3842 // Long Register |
| 3843 operand iRegL() %{ | |
| 3844 constraint(ALLOC_IN_RC(long_reg)); | |
| 3845 match(RegL); | |
| 3846 | |
| 3847 format %{ %} | |
| 3848 interface(REG_INTER); | |
| 3849 %} | |
| 3850 | |
| 3851 operand o2RegL() %{ | |
| 3852 constraint(ALLOC_IN_RC(o2_regL)); | |
| 3853 match(iRegL); | |
| 3854 | |
| 3855 format %{ %} | |
| 3856 interface(REG_INTER); | |
| 3857 %} | |
| 3858 | |
| 3859 operand o7RegL() %{ | |
| 3860 constraint(ALLOC_IN_RC(o7_regL)); | |
| 3861 match(iRegL); | |
| 3862 | |
| 3863 format %{ %} | |
| 3864 interface(REG_INTER); | |
| 3865 %} | |
| 3866 | |
| 3867 operand g1RegL() %{ | |
| 3868 constraint(ALLOC_IN_RC(g1_regL)); | |
| 3869 match(iRegL); | |
| 3870 | |
| 3871 format %{ %} | |
| 3872 interface(REG_INTER); | |
| 3873 %} | |
| 3874 | |
|
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3875 operand g3RegL() %{ |
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3876 constraint(ALLOC_IN_RC(g3_regL)); |
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3877 match(iRegL); |
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|
3878 |
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3879 format %{ %} |
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3880 interface(REG_INTER); |
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3881 %} |
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3882 |
| 0 | 3883 // Int Register safe |
| 3884 // This is 64bit safe | |
| 3885 operand iRegIsafe() %{ | |
| 3886 constraint(ALLOC_IN_RC(long_reg)); | |
| 3887 | |
| 3888 match(iRegI); | |
| 3889 | |
| 3890 format %{ %} | |
| 3891 interface(REG_INTER); | |
| 3892 %} | |
| 3893 | |
| 3894 // Condition Code Flag Register | |
| 3895 operand flagsReg() %{ | |
| 3896 constraint(ALLOC_IN_RC(int_flags)); | |
| 3897 match(RegFlags); | |
| 3898 | |
| 3899 format %{ "ccr" %} // both ICC and XCC | |
| 3900 interface(REG_INTER); | |
| 3901 %} | |
| 3902 | |
| 3903 // Condition Code Register, unsigned comparisons. | |
| 3904 operand flagsRegU() %{ | |
| 3905 constraint(ALLOC_IN_RC(int_flags)); | |
| 3906 match(RegFlags); | |
| 3907 | |
| 3908 format %{ "icc_U" %} | |
| 3909 interface(REG_INTER); | |
| 3910 %} | |
| 3911 | |
| 3912 // Condition Code Register, pointer comparisons. | |
| 3913 operand flagsRegP() %{ | |
| 3914 constraint(ALLOC_IN_RC(int_flags)); | |
| 3915 match(RegFlags); | |
| 3916 | |
| 3917 #ifdef _LP64 | |
| 3918 format %{ "xcc_P" %} | |
| 3919 #else | |
| 3920 format %{ "icc_P" %} | |
| 3921 #endif | |
| 3922 interface(REG_INTER); | |
| 3923 %} | |
| 3924 | |
| 3925 // Condition Code Register, long comparisons. | |
| 3926 operand flagsRegL() %{ | |
| 3927 constraint(ALLOC_IN_RC(int_flags)); | |
| 3928 match(RegFlags); | |
| 3929 | |
| 3930 format %{ "xcc_L" %} | |
| 3931 interface(REG_INTER); | |
| 3932 %} | |
| 3933 | |
| 3934 // Condition Code Register, floating comparisons, unordered same as "less". | |
| 3935 operand flagsRegF() %{ | |
| 3936 constraint(ALLOC_IN_RC(float_flags)); | |
| 3937 match(RegFlags); | |
| 3938 match(flagsRegF0); | |
| 3939 | |
| 3940 format %{ %} | |
| 3941 interface(REG_INTER); | |
| 3942 %} | |
| 3943 | |
| 3944 operand flagsRegF0() %{ | |
| 3945 constraint(ALLOC_IN_RC(float_flag0)); | |
| 3946 match(RegFlags); | |
| 3947 | |
| 3948 format %{ %} | |
| 3949 interface(REG_INTER); | |
| 3950 %} | |
| 3951 | |
| 3952 | |
| 3953 // Condition Code Flag Register used by long compare | |
| 3954 operand flagsReg_long_LTGE() %{ | |
| 3955 constraint(ALLOC_IN_RC(int_flags)); | |
| 3956 match(RegFlags); | |
| 3957 format %{ "icc_LTGE" %} | |
| 3958 interface(REG_INTER); | |
| 3959 %} | |
| 3960 operand flagsReg_long_EQNE() %{ | |
| 3961 constraint(ALLOC_IN_RC(int_flags)); | |
| 3962 match(RegFlags); | |
| 3963 format %{ "icc_EQNE" %} | |
| 3964 interface(REG_INTER); | |
| 3965 %} | |
| 3966 operand flagsReg_long_LEGT() %{ | |
| 3967 constraint(ALLOC_IN_RC(int_flags)); | |
| 3968 match(RegFlags); | |
| 3969 format %{ "icc_LEGT" %} | |
| 3970 interface(REG_INTER); | |
| 3971 %} | |
| 3972 | |
| 3973 | |
| 3974 operand regD() %{ | |
| 3975 constraint(ALLOC_IN_RC(dflt_reg)); | |
| 3976 match(RegD); | |
| 3977 | |
| 551 | 3978 match(regD_low); |
| 3979 | |
| 0 | 3980 format %{ %} |
| 3981 interface(REG_INTER); | |
| 3982 %} | |
| 3983 | |
| 3984 operand regF() %{ | |
| 3985 constraint(ALLOC_IN_RC(sflt_reg)); | |
| 3986 match(RegF); | |
| 3987 | |
| 3988 format %{ %} | |
| 3989 interface(REG_INTER); | |
| 3990 %} | |
| 3991 | |
| 3992 operand regD_low() %{ | |
| 3993 constraint(ALLOC_IN_RC(dflt_low_reg)); | |
| 551 | 3994 match(regD); |
| 0 | 3995 |
| 3996 format %{ %} | |
| 3997 interface(REG_INTER); | |
| 3998 %} | |
| 3999 | |
| 4000 // Special Registers | |
| 4001 | |
| 4002 // Method Register | |
| 4003 operand inline_cache_regP(iRegP reg) %{ | |
| 4004 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1 | |
| 4005 match(reg); | |
| 4006 format %{ %} | |
| 4007 interface(REG_INTER); | |
| 4008 %} | |
| 4009 | |
| 4010 operand interpreter_method_oop_regP(iRegP reg) %{ | |
| 4011 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1 | |
| 4012 match(reg); | |
| 4013 format %{ %} | |
| 4014 interface(REG_INTER); | |
| 4015 %} | |
| 4016 | |
| 4017 | |
| 4018 //----------Complex Operands--------------------------------------------------- | |
| 4019 // Indirect Memory Reference | |
| 4020 operand indirect(sp_ptr_RegP reg) %{ | |
| 4021 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 4022 match(reg); | |
| 4023 | |
| 4024 op_cost(100); | |
| 4025 format %{ "[$reg]" %} | |
| 4026 interface(MEMORY_INTER) %{ | |
| 4027 base($reg); | |
| 4028 index(0x0); | |
| 4029 scale(0x0); | |
| 4030 disp(0x0); | |
| 4031 %} | |
| 4032 %} | |
| 4033 | |
| 785 | 4034 // Indirect with simm13 Offset |
| 0 | 4035 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{ |
| 4036 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 4037 match(AddP reg offset); | |
| 4038 | |
| 4039 op_cost(100); | |
| 4040 format %{ "[$reg + $offset]" %} | |
| 4041 interface(MEMORY_INTER) %{ | |
| 4042 base($reg); | |
| 4043 index(0x0); | |
| 4044 scale(0x0); | |
| 4045 disp($offset); | |
| 4046 %} | |
| 4047 %} | |
| 4048 | |
| 785 | 4049 // Indirect with simm13 Offset minus 7 |
| 4050 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{ | |
| 4051 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
| 4052 match(AddP reg offset); | |
| 4053 | |
| 4054 op_cost(100); | |
| 4055 format %{ "[$reg + $offset]" %} | |
| 4056 interface(MEMORY_INTER) %{ | |
| 4057 base($reg); | |
| 4058 index(0x0); | |
| 4059 scale(0x0); | |
| 4060 disp($offset); | |
| 4061 %} | |
| 4062 %} | |
| 4063 | |
| 0 | 4064 // Note: Intel has a swapped version also, like this: |
| 4065 //operand indOffsetX(iRegI reg, immP offset) %{ | |
| 4066 // constraint(ALLOC_IN_RC(int_reg)); | |
| 4067 // match(AddP offset reg); | |
| 4068 // | |
| 4069 // op_cost(100); | |
| 4070 // format %{ "[$reg + $offset]" %} | |
| 4071 // interface(MEMORY_INTER) %{ | |
| 4072 // base($reg); | |
| 4073 // index(0x0); | |
| 4074 // scale(0x0); | |
| 4075 // disp($offset); | |
| 4076 // %} | |
| 4077 //%} | |
| 4078 //// However, it doesn't make sense for SPARC, since | |
| 4079 // we have no particularly good way to embed oops in | |
| 4080 // single instructions. | |
| 4081 | |
| 4082 // Indirect with Register Index | |
| 4083 operand indIndex(iRegP addr, iRegX index) %{ | |
| 4084 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4085 match(AddP addr index); | |
| 4086 | |
| 4087 op_cost(100); | |
| 4088 format %{ "[$addr + $index]" %} | |
| 4089 interface(MEMORY_INTER) %{ | |
| 4090 base($addr); | |
| 4091 index($index); | |
| 4092 scale(0x0); | |
| 4093 disp(0x0); | |
| 4094 %} | |
| 4095 %} | |
| 4096 | |
| 4097 //----------Special Memory Operands-------------------------------------------- | |
| 4098 // Stack Slot Operand - This operand is used for loading and storing temporary | |
| 4099 // values on the stack where a match requires a value to | |
| 4100 // flow through memory. | |
| 4101 operand stackSlotI(sRegI reg) %{ | |
| 4102 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4103 op_cost(100); | |
| 4104 //match(RegI); | |
| 4105 format %{ "[$reg]" %} | |
| 4106 interface(MEMORY_INTER) %{ | |
| 4107 base(0xE); // R_SP | |
| 4108 index(0x0); | |
| 4109 scale(0x0); | |
| 4110 disp($reg); // Stack Offset | |
| 4111 %} | |
| 4112 %} | |
| 4113 | |
| 4114 operand stackSlotP(sRegP reg) %{ | |
| 4115 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4116 op_cost(100); | |
| 4117 //match(RegP); | |
| 4118 format %{ "[$reg]" %} | |
| 4119 interface(MEMORY_INTER) %{ | |
| 4120 base(0xE); // R_SP | |
| 4121 index(0x0); | |
| 4122 scale(0x0); | |
| 4123 disp($reg); // Stack Offset | |
| 4124 %} | |
| 4125 %} | |
| 4126 | |
| 4127 operand stackSlotF(sRegF reg) %{ | |
| 4128 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4129 op_cost(100); | |
| 4130 //match(RegF); | |
| 4131 format %{ "[$reg]" %} | |
| 4132 interface(MEMORY_INTER) %{ | |
| 4133 base(0xE); // R_SP | |
| 4134 index(0x0); | |
| 4135 scale(0x0); | |
| 4136 disp($reg); // Stack Offset | |
| 4137 %} | |
| 4138 %} | |
| 4139 operand stackSlotD(sRegD reg) %{ | |
| 4140 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4141 op_cost(100); | |
| 4142 //match(RegD); | |
| 4143 format %{ "[$reg]" %} | |
| 4144 interface(MEMORY_INTER) %{ | |
| 4145 base(0xE); // R_SP | |
| 4146 index(0x0); | |
| 4147 scale(0x0); | |
| 4148 disp($reg); // Stack Offset | |
| 4149 %} | |
| 4150 %} | |
| 4151 operand stackSlotL(sRegL reg) %{ | |
| 4152 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4153 op_cost(100); | |
| 4154 //match(RegL); | |
| 4155 format %{ "[$reg]" %} | |
| 4156 interface(MEMORY_INTER) %{ | |
| 4157 base(0xE); // R_SP | |
| 4158 index(0x0); | |
| 4159 scale(0x0); | |
| 4160 disp($reg); // Stack Offset | |
| 4161 %} | |
| 4162 %} | |
| 4163 | |
| 4164 // Operands for expressing Control Flow | |
| 4165 // NOTE: Label is a predefined operand which should not be redefined in | |
| 4166 // the AD file. It is generically handled within the ADLC. | |
| 4167 | |
| 4168 //----------Conditional Branch Operands---------------------------------------- | |
| 4169 // Comparison Op - This is the operation of the comparison, and is limited to | |
| 4170 // the following set of codes: | |
| 4171 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
| 4172 // | |
| 4173 // Other attributes of the comparison, such as unsignedness, are specified | |
| 4174 // by the comparison instruction that sets a condition code flags register. | |
| 4175 // That result is represented by a flags operand whose subtype is appropriate | |
| 4176 // to the unsignedness (etc.) of the comparison. | |
| 4177 // | |
| 4178 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
| 4179 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
| 4180 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
| 4181 | |
| 4182 operand cmpOp() %{ | |
| 4183 match(Bool); | |
| 4184 | |
| 4185 format %{ "" %} | |
| 4186 interface(COND_INTER) %{ | |
| 4187 equal(0x1); | |
| 4188 not_equal(0x9); | |
| 4189 less(0x3); | |
| 4190 greater_equal(0xB); | |
| 4191 less_equal(0x2); | |
| 4192 greater(0xA); | |
| 4193 %} | |
| 4194 %} | |
| 4195 | |
| 4196 // Comparison Op, unsigned | |
| 4197 operand cmpOpU() %{ | |
| 4198 match(Bool); | |
| 4199 | |
| 4200 format %{ "u" %} | |
| 4201 interface(COND_INTER) %{ | |
| 4202 equal(0x1); | |
| 4203 not_equal(0x9); | |
| 4204 less(0x5); | |
| 4205 greater_equal(0xD); | |
| 4206 less_equal(0x4); | |
| 4207 greater(0xC); | |
| 4208 %} | |
| 4209 %} | |
| 4210 | |
| 4211 // Comparison Op, pointer (same as unsigned) | |
| 4212 operand cmpOpP() %{ | |
| 4213 match(Bool); | |
| 4214 | |
| 4215 format %{ "p" %} | |
| 4216 interface(COND_INTER) %{ | |
| 4217 equal(0x1); | |
| 4218 not_equal(0x9); | |
| 4219 less(0x5); | |
| 4220 greater_equal(0xD); | |
| 4221 less_equal(0x4); | |
| 4222 greater(0xC); | |
| 4223 %} | |
| 4224 %} | |
| 4225 | |
| 4226 // Comparison Op, branch-register encoding | |
| 4227 operand cmpOp_reg() %{ | |
| 4228 match(Bool); | |
| 4229 | |
| 4230 format %{ "" %} | |
| 4231 interface(COND_INTER) %{ | |
| 4232 equal (0x1); | |
| 4233 not_equal (0x5); | |
| 4234 less (0x3); | |
| 4235 greater_equal(0x7); | |
| 4236 less_equal (0x2); | |
| 4237 greater (0x6); | |
| 4238 %} | |
| 4239 %} | |
| 4240 | |
| 4241 // Comparison Code, floating, unordered same as less | |
| 4242 operand cmpOpF() %{ | |
| 4243 match(Bool); | |
| 4244 | |
| 4245 format %{ "fl" %} | |
| 4246 interface(COND_INTER) %{ | |
| 4247 equal(0x9); | |
| 4248 not_equal(0x1); | |
| 4249 less(0x3); | |
| 4250 greater_equal(0xB); | |
| 4251 less_equal(0xE); | |
| 4252 greater(0x6); | |
| 4253 %} | |
| 4254 %} | |
| 4255 | |
| 4256 // Used by long compare | |
| 4257 operand cmpOp_commute() %{ | |
| 4258 match(Bool); | |
| 4259 | |
| 4260 format %{ "" %} | |
| 4261 interface(COND_INTER) %{ | |
| 4262 equal(0x1); | |
| 4263 not_equal(0x9); | |
| 4264 less(0xA); | |
| 4265 greater_equal(0x2); | |
| 4266 less_equal(0xB); | |
| 4267 greater(0x3); | |
| 4268 %} | |
| 4269 %} | |
| 4270 | |
| 4271 //----------OPERAND CLASSES---------------------------------------------------- | |
| 4272 // Operand Classes are groups of operands that are used to simplify | |
| 605 | 4273 // instruction definitions by not requiring the AD writer to specify separate |
| 0 | 4274 // instructions for every form of operand when the instruction accepts |
| 4275 // multiple operand types with the same basic encoding and format. The classic | |
| 4276 // case of this is memory operands. | |
| 4277 opclass memory( indirect, indOffset13, indIndex ); | |
|
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|
4278 opclass indIndexMemory( indIndex ); |
| 0 | 4279 |
| 4280 //----------PIPELINE----------------------------------------------------------- | |
| 4281 pipeline %{ | |
| 4282 | |
| 4283 //----------ATTRIBUTES--------------------------------------------------------- | |
| 4284 attributes %{ | |
| 4285 fixed_size_instructions; // Fixed size instructions | |
| 4286 branch_has_delay_slot; // Branch has delay slot following | |
| 4287 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle | |
| 4288 instruction_unit_size = 4; // An instruction is 4 bytes long | |
| 4289 instruction_fetch_unit_size = 16; // The processor fetches one line | |
| 4290 instruction_fetch_units = 1; // of 16 bytes | |
| 4291 | |
| 4292 // List of nop instructions | |
| 4293 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR ); | |
| 4294 %} | |
| 4295 | |
| 4296 //----------RESOURCES---------------------------------------------------------- | |
| 4297 // Resources are the functional units available to the machine | |
| 4298 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1); | |
| 4299 | |
| 4300 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
| 4301 // Pipeline Description specifies the stages in the machine's pipeline | |
| 4302 | |
| 4303 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D); | |
| 4304 | |
| 4305 //----------PIPELINE CLASSES--------------------------------------------------- | |
| 4306 // Pipeline Classes describe the stages in which input and output are | |
| 4307 // referenced by the hardware pipeline. | |
| 4308 | |
| 4309 // Integer ALU reg-reg operation | |
| 4310 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 4311 single_instruction; | |
| 4312 dst : E(write); | |
| 4313 src1 : R(read); | |
| 4314 src2 : R(read); | |
| 4315 IALU : R; | |
| 4316 %} | |
| 4317 | |
| 4318 // Integer ALU reg-reg long operation | |
| 4319 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 4320 instruction_count(2); | |
| 4321 dst : E(write); | |
| 4322 src1 : R(read); | |
| 4323 src2 : R(read); | |
| 4324 IALU : R; | |
| 4325 IALU : R; | |
| 4326 %} | |
| 4327 | |
| 4328 // Integer ALU reg-reg long dependent operation | |
| 4329 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ | |
| 4330 instruction_count(1); multiple_bundles; | |
| 4331 dst : E(write); | |
| 4332 src1 : R(read); | |
| 4333 src2 : R(read); | |
| 4334 cr : E(write); | |
| 4335 IALU : R(2); | |
| 4336 %} | |
| 4337 | |
| 4338 // Integer ALU reg-imm operaion | |
| 4339 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 4340 single_instruction; | |
| 4341 dst : E(write); | |
| 4342 src1 : R(read); | |
| 4343 IALU : R; | |
| 4344 %} | |
| 4345 | |
| 4346 // Integer ALU reg-reg operation with condition code | |
| 4347 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ | |
| 4348 single_instruction; | |
| 4349 dst : E(write); | |
| 4350 cr : E(write); | |
| 4351 src1 : R(read); | |
| 4352 src2 : R(read); | |
| 4353 IALU : R; | |
| 4354 %} | |
| 4355 | |
| 4356 // Integer ALU reg-imm operation with condition code | |
| 4357 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{ | |
| 4358 single_instruction; | |
| 4359 dst : E(write); | |
| 4360 cr : E(write); | |
| 4361 src1 : R(read); | |
| 4362 IALU : R; | |
| 4363 %} | |
| 4364 | |
| 4365 // Integer ALU zero-reg operation | |
| 4366 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
| 4367 single_instruction; | |
| 4368 dst : E(write); | |
| 4369 src2 : R(read); | |
| 4370 IALU : R; | |
| 4371 %} | |
| 4372 | |
| 4373 // Integer ALU zero-reg operation with condition code only | |
| 4374 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{ | |
| 4375 single_instruction; | |
| 4376 cr : E(write); | |
| 4377 src : R(read); | |
| 4378 IALU : R; | |
| 4379 %} | |
| 4380 | |
| 4381 // Integer ALU reg-reg operation with condition code only | |
| 4382 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
| 4383 single_instruction; | |
| 4384 cr : E(write); | |
| 4385 src1 : R(read); | |
| 4386 src2 : R(read); | |
| 4387 IALU : R; | |
| 4388 %} | |
| 4389 | |
| 4390 // Integer ALU reg-imm operation with condition code only | |
| 4391 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
| 4392 single_instruction; | |
| 4393 cr : E(write); | |
| 4394 src1 : R(read); | |
| 4395 IALU : R; | |
| 4396 %} | |
| 4397 | |
| 4398 // Integer ALU reg-reg-zero operation with condition code only | |
| 4399 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{ | |
| 4400 single_instruction; | |
| 4401 cr : E(write); | |
| 4402 src1 : R(read); | |
| 4403 src2 : R(read); | |
| 4404 IALU : R; | |
| 4405 %} | |
| 4406 | |
| 4407 // Integer ALU reg-imm-zero operation with condition code only | |
| 4408 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{ | |
| 4409 single_instruction; | |
| 4410 cr : E(write); | |
| 4411 src1 : R(read); | |
| 4412 IALU : R; | |
| 4413 %} | |
| 4414 | |
| 4415 // Integer ALU reg-reg operation with condition code, src1 modified | |
| 4416 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
| 4417 single_instruction; | |
| 4418 cr : E(write); | |
| 4419 src1 : E(write); | |
| 4420 src1 : R(read); | |
| 4421 src2 : R(read); | |
| 4422 IALU : R; | |
| 4423 %} | |
| 4424 | |
| 4425 // Integer ALU reg-imm operation with condition code, src1 modified | |
| 4426 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
| 4427 single_instruction; | |
| 4428 cr : E(write); | |
| 4429 src1 : E(write); | |
| 4430 src1 : R(read); | |
| 4431 IALU : R; | |
| 4432 %} | |
| 4433 | |
| 4434 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{ | |
| 4435 multiple_bundles; | |
| 4436 dst : E(write)+4; | |
| 4437 cr : E(write); | |
| 4438 src1 : R(read); | |
| 4439 src2 : R(read); | |
| 4440 IALU : R(3); | |
| 4441 BR : R(2); | |
| 4442 %} | |
| 4443 | |
| 4444 // Integer ALU operation | |
| 4445 pipe_class ialu_none(iRegI dst) %{ | |
| 4446 single_instruction; | |
| 4447 dst : E(write); | |
| 4448 IALU : R; | |
| 4449 %} | |
| 4450 | |
| 4451 // Integer ALU reg operation | |
| 4452 pipe_class ialu_reg(iRegI dst, iRegI src) %{ | |
| 4453 single_instruction; may_have_no_code; | |
| 4454 dst : E(write); | |
| 4455 src : R(read); | |
| 4456 IALU : R; | |
| 4457 %} | |
| 4458 | |
| 4459 // Integer ALU reg conditional operation | |
| 4460 // This instruction has a 1 cycle stall, and cannot execute | |
| 4461 // in the same cycle as the instruction setting the condition | |
| 4462 // code. We kludge this by pretending to read the condition code | |
| 4463 // 1 cycle earlier, and by marking the functional units as busy | |
| 4464 // for 2 cycles with the result available 1 cycle later than | |
| 4465 // is really the case. | |
| 4466 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{ | |
| 4467 single_instruction; | |
| 4468 op2_out : C(write); | |
| 4469 op1 : R(read); | |
| 4470 cr : R(read); // This is really E, with a 1 cycle stall | |
| 4471 BR : R(2); | |
| 4472 MS : R(2); | |
| 4473 %} | |
| 4474 | |
| 4475 #ifdef _LP64 | |
| 4476 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{ | |
| 4477 instruction_count(1); multiple_bundles; | |
| 4478 dst : C(write)+1; | |
| 4479 src : R(read)+1; | |
| 4480 IALU : R(1); | |
| 4481 BR : E(2); | |
| 4482 MS : E(2); | |
| 4483 %} | |
| 4484 #endif | |
| 4485 | |
| 4486 // Integer ALU reg operation | |
| 4487 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{ | |
| 4488 single_instruction; may_have_no_code; | |
| 4489 dst : E(write); | |
| 4490 src : R(read); | |
| 4491 IALU : R; | |
| 4492 %} | |
| 4493 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{ | |
| 4494 single_instruction; may_have_no_code; | |
| 4495 dst : E(write); | |
| 4496 src : R(read); | |
| 4497 IALU : R; | |
| 4498 %} | |
| 4499 | |
| 4500 // Two integer ALU reg operations | |
| 4501 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{ | |
| 4502 instruction_count(2); | |
| 4503 dst : E(write); | |
| 4504 src : R(read); | |
| 4505 A0 : R; | |
| 4506 A1 : R; | |
| 4507 %} | |
| 4508 | |
| 4509 // Two integer ALU reg operations | |
| 4510 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{ | |
| 4511 instruction_count(2); may_have_no_code; | |
| 4512 dst : E(write); | |
| 4513 src : R(read); | |
| 4514 A0 : R; | |
| 4515 A1 : R; | |
| 4516 %} | |
| 4517 | |
| 4518 // Integer ALU imm operation | |
| 4519 pipe_class ialu_imm(iRegI dst, immI13 src) %{ | |
| 4520 single_instruction; | |
| 4521 dst : E(write); | |
| 4522 IALU : R; | |
| 4523 %} | |
| 4524 | |
| 4525 // Integer ALU reg-reg with carry operation | |
| 4526 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{ | |
| 4527 single_instruction; | |
| 4528 dst : E(write); | |
| 4529 src1 : R(read); | |
| 4530 src2 : R(read); | |
| 4531 IALU : R; | |
| 4532 %} | |
| 4533 | |
| 4534 // Integer ALU cc operation | |
| 4535 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{ | |
| 4536 single_instruction; | |
| 4537 dst : E(write); | |
| 4538 cc : R(read); | |
| 4539 IALU : R; | |
| 4540 %} | |
| 4541 | |
| 4542 // Integer ALU cc / second IALU operation | |
| 4543 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{ | |
| 4544 instruction_count(1); multiple_bundles; | |
| 4545 dst : E(write)+1; | |
| 4546 src : R(read); | |
| 4547 IALU : R; | |
| 4548 %} | |
| 4549 | |
| 4550 // Integer ALU cc / second IALU operation | |
| 4551 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{ | |
| 4552 instruction_count(1); multiple_bundles; | |
| 4553 dst : E(write)+1; | |
| 4554 p : R(read); | |
| 4555 q : R(read); | |
| 4556 IALU : R; | |
| 4557 %} | |
| 4558 | |
| 4559 // Integer ALU hi-lo-reg operation | |
| 4560 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{ | |
| 4561 instruction_count(1); multiple_bundles; | |
| 4562 dst : E(write)+1; | |
| 4563 IALU : R(2); | |
| 4564 %} | |
| 4565 | |
| 4566 // Float ALU hi-lo-reg operation (with temp) | |
| 4567 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{ | |
| 4568 instruction_count(1); multiple_bundles; | |
| 4569 dst : E(write)+1; | |
| 4570 IALU : R(2); | |
| 4571 %} | |
| 4572 | |
| 4573 // Long Constant | |
| 4574 pipe_class loadConL( iRegL dst, immL src ) %{ | |
| 4575 instruction_count(2); multiple_bundles; | |
| 4576 dst : E(write)+1; | |
| 4577 IALU : R(2); | |
| 4578 IALU : R(2); | |
| 4579 %} | |
| 4580 | |
| 4581 // Pointer Constant | |
| 4582 pipe_class loadConP( iRegP dst, immP src ) %{ | |
| 4583 instruction_count(0); multiple_bundles; | |
| 4584 fixed_latency(6); | |
| 4585 %} | |
| 4586 | |
| 4587 // Polling Address | |
| 4588 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{ | |
| 4589 #ifdef _LP64 | |
| 4590 instruction_count(0); multiple_bundles; | |
| 4591 fixed_latency(6); | |
| 4592 #else | |
| 4593 dst : E(write); | |
| 4594 IALU : R; | |
| 4595 #endif | |
| 4596 %} | |
| 4597 | |
| 4598 // Long Constant small | |
| 4599 pipe_class loadConLlo( iRegL dst, immL src ) %{ | |
| 4600 instruction_count(2); | |
| 4601 dst : E(write); | |
| 4602 IALU : R; | |
| 4603 IALU : R; | |
| 4604 %} | |
| 4605 | |
| 4606 // [PHH] This is wrong for 64-bit. See LdImmF/D. | |
| 4607 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{ | |
| 4608 instruction_count(1); multiple_bundles; | |
| 4609 src : R(read); | |
| 4610 dst : M(write)+1; | |
| 4611 IALU : R; | |
| 4612 MS : E; | |
| 4613 %} | |
| 4614 | |
| 4615 // Integer ALU nop operation | |
| 4616 pipe_class ialu_nop() %{ | |
| 4617 single_instruction; | |
| 4618 IALU : R; | |
| 4619 %} | |
| 4620 | |
| 4621 // Integer ALU nop operation | |
| 4622 pipe_class ialu_nop_A0() %{ | |
| 4623 single_instruction; | |
| 4624 A0 : R; | |
| 4625 %} | |
| 4626 | |
| 4627 // Integer ALU nop operation | |
| 4628 pipe_class ialu_nop_A1() %{ | |
| 4629 single_instruction; | |
| 4630 A1 : R; | |
| 4631 %} | |
| 4632 | |
| 4633 // Integer Multiply reg-reg operation | |
| 4634 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 4635 single_instruction; | |
| 4636 dst : E(write); | |
| 4637 src1 : R(read); | |
| 4638 src2 : R(read); | |
| 4639 MS : R(5); | |
| 4640 %} | |
| 4641 | |
| 4642 // Integer Multiply reg-imm operation | |
| 4643 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 4644 single_instruction; | |
| 4645 dst : E(write); | |
| 4646 src1 : R(read); | |
| 4647 MS : R(5); | |
| 4648 %} | |
| 4649 | |
| 4650 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 4651 single_instruction; | |
| 4652 dst : E(write)+4; | |
| 4653 src1 : R(read); | |
| 4654 src2 : R(read); | |
| 4655 MS : R(6); | |
| 4656 %} | |
| 4657 | |
| 4658 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 4659 single_instruction; | |
| 4660 dst : E(write)+4; | |
| 4661 src1 : R(read); | |
| 4662 MS : R(6); | |
| 4663 %} | |
| 4664 | |
| 4665 // Integer Divide reg-reg | |
| 4666 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{ | |
| 4667 instruction_count(1); multiple_bundles; | |
| 4668 dst : E(write); | |
| 4669 temp : E(write); | |
| 4670 src1 : R(read); | |
| 4671 src2 : R(read); | |
| 4672 temp : R(read); | |
| 4673 MS : R(38); | |
| 4674 %} | |
| 4675 | |
| 4676 // Integer Divide reg-imm | |
| 4677 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{ | |
| 4678 instruction_count(1); multiple_bundles; | |
| 4679 dst : E(write); | |
| 4680 temp : E(write); | |
| 4681 src1 : R(read); | |
| 4682 temp : R(read); | |
| 4683 MS : R(38); | |
| 4684 %} | |
| 4685 | |
| 4686 // Long Divide | |
| 4687 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 4688 dst : E(write)+71; | |
| 4689 src1 : R(read); | |
| 4690 src2 : R(read)+1; | |
| 4691 MS : R(70); | |
| 4692 %} | |
| 4693 | |
| 4694 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 4695 dst : E(write)+71; | |
| 4696 src1 : R(read); | |
| 4697 MS : R(70); | |
| 4698 %} | |
| 4699 | |
| 4700 // Floating Point Add Float | |
| 4701 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 4702 single_instruction; | |
| 4703 dst : X(write); | |
| 4704 src1 : E(read); | |
| 4705 src2 : E(read); | |
| 4706 FA : R; | |
| 4707 %} | |
| 4708 | |
| 4709 // Floating Point Add Double | |
| 4710 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 4711 single_instruction; | |
| 4712 dst : X(write); | |
| 4713 src1 : E(read); | |
| 4714 src2 : E(read); | |
| 4715 FA : R; | |
| 4716 %} | |
| 4717 | |
| 4718 // Floating Point Conditional Move based on integer flags | |
| 4719 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{ | |
| 4720 single_instruction; | |
| 4721 dst : X(write); | |
| 4722 src : E(read); | |
| 4723 cr : R(read); | |
| 4724 FA : R(2); | |
| 4725 BR : R(2); | |
| 4726 %} | |
| 4727 | |
| 4728 // Floating Point Conditional Move based on integer flags | |
| 4729 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{ | |
| 4730 single_instruction; | |
| 4731 dst : X(write); | |
| 4732 src : E(read); | |
| 4733 cr : R(read); | |
| 4734 FA : R(2); | |
| 4735 BR : R(2); | |
| 4736 %} | |
| 4737 | |
| 4738 // Floating Point Multiply Float | |
| 4739 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 4740 single_instruction; | |
| 4741 dst : X(write); | |
| 4742 src1 : E(read); | |
| 4743 src2 : E(read); | |
| 4744 FM : R; | |
| 4745 %} | |
| 4746 | |
| 4747 // Floating Point Multiply Double | |
| 4748 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 4749 single_instruction; | |
| 4750 dst : X(write); | |
| 4751 src1 : E(read); | |
| 4752 src2 : E(read); | |
| 4753 FM : R; | |
| 4754 %} | |
| 4755 | |
| 4756 // Floating Point Divide Float | |
| 4757 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 4758 single_instruction; | |
| 4759 dst : X(write); | |
| 4760 src1 : E(read); | |
| 4761 src2 : E(read); | |
| 4762 FM : R; | |
| 4763 FDIV : C(14); | |
| 4764 %} | |
| 4765 | |
| 4766 // Floating Point Divide Double | |
| 4767 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 4768 single_instruction; | |
| 4769 dst : X(write); | |
| 4770 src1 : E(read); | |
| 4771 src2 : E(read); | |
| 4772 FM : R; | |
| 4773 FDIV : C(17); | |
| 4774 %} | |
| 4775 | |
| 4776 // Floating Point Move/Negate/Abs Float | |
| 4777 pipe_class faddF_reg(regF dst, regF src) %{ | |
| 4778 single_instruction; | |
| 4779 dst : W(write); | |
| 4780 src : E(read); | |
| 4781 FA : R(1); | |
| 4782 %} | |
| 4783 | |
| 4784 // Floating Point Move/Negate/Abs Double | |
| 4785 pipe_class faddD_reg(regD dst, regD src) %{ | |
| 4786 single_instruction; | |
| 4787 dst : W(write); | |
| 4788 src : E(read); | |
| 4789 FA : R; | |
| 4790 %} | |
| 4791 | |
| 4792 // Floating Point Convert F->D | |
| 4793 pipe_class fcvtF2D(regD dst, regF src) %{ | |
| 4794 single_instruction; | |
| 4795 dst : X(write); | |
| 4796 src : E(read); | |
| 4797 FA : R; | |
| 4798 %} | |
| 4799 | |
| 4800 // Floating Point Convert I->D | |
| 4801 pipe_class fcvtI2D(regD dst, regF src) %{ | |
| 4802 single_instruction; | |
| 4803 dst : X(write); | |
| 4804 src : E(read); | |
| 4805 FA : R; | |
| 4806 %} | |
| 4807 | |
| 4808 // Floating Point Convert LHi->D | |
| 4809 pipe_class fcvtLHi2D(regD dst, regD src) %{ | |
| 4810 single_instruction; | |
| 4811 dst : X(write); | |
| 4812 src : E(read); | |
| 4813 FA : R; | |
| 4814 %} | |
| 4815 | |
| 4816 // Floating Point Convert L->D | |
| 4817 pipe_class fcvtL2D(regD dst, regF src) %{ | |
| 4818 single_instruction; | |
| 4819 dst : X(write); | |
| 4820 src : E(read); | |
| 4821 FA : R; | |
| 4822 %} | |
| 4823 | |
| 4824 // Floating Point Convert L->F | |
| 4825 pipe_class fcvtL2F(regD dst, regF src) %{ | |
| 4826 single_instruction; | |
| 4827 dst : X(write); | |
| 4828 src : E(read); | |
| 4829 FA : R; | |
| 4830 %} | |
| 4831 | |
| 4832 // Floating Point Convert D->F | |
| 4833 pipe_class fcvtD2F(regD dst, regF src) %{ | |
| 4834 single_instruction; | |
| 4835 dst : X(write); | |
| 4836 src : E(read); | |
| 4837 FA : R; | |
| 4838 %} | |
| 4839 | |
| 4840 // Floating Point Convert I->L | |
| 4841 pipe_class fcvtI2L(regD dst, regF src) %{ | |
| 4842 single_instruction; | |
| 4843 dst : X(write); | |
| 4844 src : E(read); | |
| 4845 FA : R; | |
| 4846 %} | |
| 4847 | |
| 4848 // Floating Point Convert D->F | |
| 4849 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{ | |
| 4850 instruction_count(1); multiple_bundles; | |
| 4851 dst : X(write)+6; | |
| 4852 src : E(read); | |
| 4853 FA : R; | |
| 4854 %} | |
| 4855 | |
| 4856 // Floating Point Convert D->L | |
| 4857 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{ | |
| 4858 instruction_count(1); multiple_bundles; | |
| 4859 dst : X(write)+6; | |
| 4860 src : E(read); | |
| 4861 FA : R; | |
| 4862 %} | |
| 4863 | |
| 4864 // Floating Point Convert F->I | |
| 4865 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{ | |
| 4866 instruction_count(1); multiple_bundles; | |
| 4867 dst : X(write)+6; | |
| 4868 src : E(read); | |
| 4869 FA : R; | |
| 4870 %} | |
| 4871 | |
| 4872 // Floating Point Convert F->L | |
| 4873 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{ | |
| 4874 instruction_count(1); multiple_bundles; | |
| 4875 dst : X(write)+6; | |
| 4876 src : E(read); | |
| 4877 FA : R; | |
| 4878 %} | |
| 4879 | |
| 4880 // Floating Point Convert I->F | |
| 4881 pipe_class fcvtI2F(regF dst, regF src) %{ | |
| 4882 single_instruction; | |
| 4883 dst : X(write); | |
| 4884 src : E(read); | |
| 4885 FA : R; | |
| 4886 %} | |
| 4887 | |
| 4888 // Floating Point Compare | |
| 4889 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{ | |
| 4890 single_instruction; | |
| 4891 cr : X(write); | |
| 4892 src1 : E(read); | |
| 4893 src2 : E(read); | |
| 4894 FA : R; | |
| 4895 %} | |
| 4896 | |
| 4897 // Floating Point Compare | |
| 4898 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{ | |
| 4899 single_instruction; | |
| 4900 cr : X(write); | |
| 4901 src1 : E(read); | |
| 4902 src2 : E(read); | |
| 4903 FA : R; | |
| 4904 %} | |
| 4905 | |
| 4906 // Floating Add Nop | |
| 4907 pipe_class fadd_nop() %{ | |
| 4908 single_instruction; | |
| 4909 FA : R; | |
| 4910 %} | |
| 4911 | |
| 4912 // Integer Store to Memory | |
| 4913 pipe_class istore_mem_reg(memory mem, iRegI src) %{ | |
| 4914 single_instruction; | |
| 4915 mem : R(read); | |
| 4916 src : C(read); | |
| 4917 MS : R; | |
| 4918 %} | |
| 4919 | |
| 4920 // Integer Store to Memory | |
| 4921 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{ | |
| 4922 single_instruction; | |
| 4923 mem : R(read); | |
| 4924 src : C(read); | |
| 4925 MS : R; | |
| 4926 %} | |
| 4927 | |
| 4928 // Integer Store Zero to Memory | |
| 4929 pipe_class istore_mem_zero(memory mem, immI0 src) %{ | |
| 4930 single_instruction; | |
| 4931 mem : R(read); | |
| 4932 MS : R; | |
| 4933 %} | |
| 4934 | |
| 4935 // Special Stack Slot Store | |
| 4936 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{ | |
| 4937 single_instruction; | |
| 4938 stkSlot : R(read); | |
| 4939 src : C(read); | |
| 4940 MS : R; | |
| 4941 %} | |
| 4942 | |
| 4943 // Special Stack Slot Store | |
| 4944 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{ | |
| 4945 instruction_count(2); multiple_bundles; | |
| 4946 stkSlot : R(read); | |
| 4947 src : C(read); | |
| 4948 MS : R(2); | |
| 4949 %} | |
| 4950 | |
| 4951 // Float Store | |
| 4952 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{ | |
| 4953 single_instruction; | |
| 4954 mem : R(read); | |
| 4955 src : C(read); | |
| 4956 MS : R; | |
| 4957 %} | |
| 4958 | |
| 4959 // Float Store | |
| 4960 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{ | |
| 4961 single_instruction; | |
| 4962 mem : R(read); | |
| 4963 MS : R; | |
| 4964 %} | |
| 4965 | |
| 4966 // Double Store | |
| 4967 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{ | |
| 4968 instruction_count(1); | |
| 4969 mem : R(read); | |
| 4970 src : C(read); | |
| 4971 MS : R; | |
| 4972 %} | |
| 4973 | |
| 4974 // Double Store | |
| 4975 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{ | |
| 4976 single_instruction; | |
| 4977 mem : R(read); | |
| 4978 MS : R; | |
| 4979 %} | |
| 4980 | |
| 4981 // Special Stack Slot Float Store | |
| 4982 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{ | |
| 4983 single_instruction; | |
| 4984 stkSlot : R(read); | |
| 4985 src : C(read); | |
| 4986 MS : R; | |
| 4987 %} | |
| 4988 | |
| 4989 // Special Stack Slot Double Store | |
| 4990 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{ | |
| 4991 single_instruction; | |
| 4992 stkSlot : R(read); | |
| 4993 src : C(read); | |
| 4994 MS : R; | |
| 4995 %} | |
| 4996 | |
| 4997 // Integer Load (when sign bit propagation not needed) | |
| 4998 pipe_class iload_mem(iRegI dst, memory mem) %{ | |
| 4999 single_instruction; | |
| 5000 mem : R(read); | |
| 5001 dst : C(write); | |
| 5002 MS : R; | |
| 5003 %} | |
| 5004 | |
| 5005 // Integer Load from stack operand | |
| 5006 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{ | |
| 5007 single_instruction; | |
| 5008 mem : R(read); | |
| 5009 dst : C(write); | |
| 5010 MS : R; | |
| 5011 %} | |
| 5012 | |
| 5013 // Integer Load (when sign bit propagation or masking is needed) | |
| 5014 pipe_class iload_mask_mem(iRegI dst, memory mem) %{ | |
| 5015 single_instruction; | |
| 5016 mem : R(read); | |
| 5017 dst : M(write); | |
| 5018 MS : R; | |
| 5019 %} | |
| 5020 | |
| 5021 // Float Load | |
| 5022 pipe_class floadF_mem(regF dst, memory mem) %{ | |
| 5023 single_instruction; | |
| 5024 mem : R(read); | |
| 5025 dst : M(write); | |
| 5026 MS : R; | |
| 5027 %} | |
| 5028 | |
| 5029 // Float Load | |
| 5030 pipe_class floadD_mem(regD dst, memory mem) %{ | |
| 5031 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case | |
| 5032 mem : R(read); | |
| 5033 dst : M(write); | |
| 5034 MS : R; | |
| 5035 %} | |
| 5036 | |
| 5037 // Float Load | |
| 5038 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{ | |
| 5039 single_instruction; | |
| 5040 stkSlot : R(read); | |
| 5041 dst : M(write); | |
| 5042 MS : R; | |
| 5043 %} | |
| 5044 | |
| 5045 // Float Load | |
| 5046 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{ | |
| 5047 single_instruction; | |
| 5048 stkSlot : R(read); | |
| 5049 dst : M(write); | |
| 5050 MS : R; | |
| 5051 %} | |
| 5052 | |
| 5053 // Memory Nop | |
| 5054 pipe_class mem_nop() %{ | |
| 5055 single_instruction; | |
| 5056 MS : R; | |
| 5057 %} | |
| 5058 | |
| 5059 pipe_class sethi(iRegP dst, immI src) %{ | |
| 5060 single_instruction; | |
| 5061 dst : E(write); | |
| 5062 IALU : R; | |
| 5063 %} | |
| 5064 | |
| 5065 pipe_class loadPollP(iRegP poll) %{ | |
| 5066 single_instruction; | |
| 5067 poll : R(read); | |
| 5068 MS : R; | |
| 5069 %} | |
| 5070 | |
| 5071 pipe_class br(Universe br, label labl) %{ | |
| 5072 single_instruction_with_delay_slot; | |
| 5073 BR : R; | |
| 5074 %} | |
| 5075 | |
| 5076 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{ | |
| 5077 single_instruction_with_delay_slot; | |
| 5078 cr : E(read); | |
| 5079 BR : R; | |
| 5080 %} | |
| 5081 | |
| 5082 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{ | |
| 5083 single_instruction_with_delay_slot; | |
| 5084 op1 : E(read); | |
| 5085 BR : R; | |
| 5086 MS : R; | |
| 5087 %} | |
| 5088 | |
| 5089 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{ | |
| 5090 single_instruction_with_delay_slot; | |
| 5091 cr : E(read); | |
| 5092 BR : R; | |
| 5093 %} | |
| 5094 | |
| 5095 pipe_class br_nop() %{ | |
| 5096 single_instruction; | |
| 5097 BR : R; | |
| 5098 %} | |
| 5099 | |
| 5100 pipe_class simple_call(method meth) %{ | |
| 5101 instruction_count(2); multiple_bundles; force_serialization; | |
| 5102 fixed_latency(100); | |
| 5103 BR : R(1); | |
| 5104 MS : R(1); | |
| 5105 A0 : R(1); | |
| 5106 %} | |
| 5107 | |
| 5108 pipe_class compiled_call(method meth) %{ | |
| 5109 instruction_count(1); multiple_bundles; force_serialization; | |
| 5110 fixed_latency(100); | |
| 5111 MS : R(1); | |
| 5112 %} | |
| 5113 | |
| 5114 pipe_class call(method meth) %{ | |
| 5115 instruction_count(0); multiple_bundles; force_serialization; | |
| 5116 fixed_latency(100); | |
| 5117 %} | |
| 5118 | |
| 5119 pipe_class tail_call(Universe ignore, label labl) %{ | |
| 5120 single_instruction; has_delay_slot; | |
| 5121 fixed_latency(100); | |
| 5122 BR : R(1); | |
| 5123 MS : R(1); | |
| 5124 %} | |
| 5125 | |
| 5126 pipe_class ret(Universe ignore) %{ | |
| 5127 single_instruction; has_delay_slot; | |
| 5128 BR : R(1); | |
| 5129 MS : R(1); | |
| 5130 %} | |
| 5131 | |
| 5132 pipe_class ret_poll(g3RegP poll) %{ | |
| 5133 instruction_count(3); has_delay_slot; | |
| 5134 poll : E(read); | |
| 5135 MS : R; | |
| 5136 %} | |
| 5137 | |
| 5138 // The real do-nothing guy | |
| 5139 pipe_class empty( ) %{ | |
| 5140 instruction_count(0); | |
| 5141 %} | |
| 5142 | |
| 5143 pipe_class long_memory_op() %{ | |
| 5144 instruction_count(0); multiple_bundles; force_serialization; | |
| 5145 fixed_latency(25); | |
| 5146 MS : R(1); | |
| 5147 %} | |
| 5148 | |
| 5149 // Check-cast | |
| 5150 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{ | |
| 5151 array : R(read); | |
| 5152 match : R(read); | |
| 5153 IALU : R(2); | |
| 5154 BR : R(2); | |
| 5155 MS : R; | |
| 5156 %} | |
| 5157 | |
| 5158 // Convert FPU flags into +1,0,-1 | |
| 5159 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{ | |
| 5160 src1 : E(read); | |
| 5161 src2 : E(read); | |
| 5162 dst : E(write); | |
| 5163 FA : R; | |
| 5164 MS : R(2); | |
| 5165 BR : R(2); | |
| 5166 %} | |
| 5167 | |
| 5168 // Compare for p < q, and conditionally add y | |
| 5169 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{ | |
| 5170 p : E(read); | |
| 5171 q : E(read); | |
| 5172 y : E(read); | |
| 5173 IALU : R(3) | |
| 5174 %} | |
| 5175 | |
| 5176 // Perform a compare, then move conditionally in a branch delay slot. | |
| 5177 pipe_class min_max( iRegI src2, iRegI srcdst ) %{ | |
| 5178 src2 : E(read); | |
| 5179 srcdst : E(read); | |
| 5180 IALU : R; | |
| 5181 BR : R; | |
| 5182 %} | |
| 5183 | |
| 5184 // Define the class for the Nop node | |
| 5185 define %{ | |
| 5186 MachNop = ialu_nop; | |
| 5187 %} | |
| 5188 | |
| 5189 %} | |
| 5190 | |
| 5191 //----------INSTRUCTIONS------------------------------------------------------- | |
| 5192 | |
| 5193 //------------Special Stack Slot instructions - no match rules----------------- | |
| 5194 instruct stkI_to_regF(regF dst, stackSlotI src) %{ | |
| 5195 // No match rule to avoid chain rule match. | |
| 5196 effect(DEF dst, USE src); | |
| 5197 ins_cost(MEMORY_REF_COST); | |
| 5198 size(4); | |
| 5199 format %{ "LDF $src,$dst\t! stkI to regF" %} | |
| 5200 opcode(Assembler::ldf_op3); | |
|
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5201 ins_encode(simple_form3_mem_reg(src, dst)); |
| 0 | 5202 ins_pipe(floadF_stk); |
| 5203 %} | |
| 5204 | |
| 5205 instruct stkL_to_regD(regD dst, stackSlotL src) %{ | |
| 5206 // No match rule to avoid chain rule match. | |
| 5207 effect(DEF dst, USE src); | |
| 5208 ins_cost(MEMORY_REF_COST); | |
| 5209 size(4); | |
| 5210 format %{ "LDDF $src,$dst\t! stkL to regD" %} | |
| 5211 opcode(Assembler::lddf_op3); | |
|
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5212 ins_encode(simple_form3_mem_reg(src, dst)); |
| 0 | 5213 ins_pipe(floadD_stk); |
| 5214 %} | |
| 5215 | |
| 5216 instruct regF_to_stkI(stackSlotI dst, regF src) %{ | |
| 5217 // No match rule to avoid chain rule match. | |
| 5218 effect(DEF dst, USE src); | |
| 5219 ins_cost(MEMORY_REF_COST); | |
| 5220 size(4); | |
| 5221 format %{ "STF $src,$dst\t! regF to stkI" %} | |
| 5222 opcode(Assembler::stf_op3); | |
|
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5223 ins_encode(simple_form3_mem_reg(dst, src)); |
| 0 | 5224 ins_pipe(fstoreF_stk_reg); |
| 5225 %} | |
| 5226 | |
| 5227 instruct regD_to_stkL(stackSlotL dst, regD src) %{ | |
| 5228 // No match rule to avoid chain rule match. | |
| 5229 effect(DEF dst, USE src); | |
| 5230 ins_cost(MEMORY_REF_COST); | |
| 5231 size(4); | |
| 5232 format %{ "STDF $src,$dst\t! regD to stkL" %} | |
| 5233 opcode(Assembler::stdf_op3); | |
|
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5234 ins_encode(simple_form3_mem_reg(dst, src)); |
| 0 | 5235 ins_pipe(fstoreD_stk_reg); |
| 5236 %} | |
| 5237 | |
| 5238 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{ | |
| 5239 effect(DEF dst, USE src); | |
| 5240 ins_cost(MEMORY_REF_COST*2); | |
| 5241 size(8); | |
| 5242 format %{ "STW $src,$dst.hi\t! long\n\t" | |
| 5243 "STW R_G0,$dst.lo" %} | |
| 5244 opcode(Assembler::stw_op3); | |
|
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5245 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0)); |
| 0 | 5246 ins_pipe(lstoreI_stk_reg); |
| 5247 %} | |
| 5248 | |
| 5249 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{ | |
| 5250 // No match rule to avoid chain rule match. | |
| 5251 effect(DEF dst, USE src); | |
| 5252 ins_cost(MEMORY_REF_COST); | |
| 5253 size(4); | |
| 5254 format %{ "STX $src,$dst\t! regL to stkD" %} | |
| 5255 opcode(Assembler::stx_op3); | |
|
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5256 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5257 ins_pipe(istore_stk_reg); |
| 5258 %} | |
| 5259 | |
| 5260 //---------- Chain stack slots between similar types -------- | |
| 5261 | |
| 5262 // Load integer from stack slot | |
| 5263 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{ | |
| 5264 match(Set dst src); | |
| 5265 ins_cost(MEMORY_REF_COST); | |
| 5266 | |
| 5267 size(4); | |
| 5268 format %{ "LDUW $src,$dst\t!stk" %} | |
| 5269 opcode(Assembler::lduw_op3); | |
|
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5270 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 5271 ins_pipe(iload_mem); |
| 5272 %} | |
| 5273 | |
| 5274 // Store integer to stack slot | |
| 5275 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{ | |
| 5276 match(Set dst src); | |
| 5277 ins_cost(MEMORY_REF_COST); | |
| 5278 | |
| 5279 size(4); | |
| 5280 format %{ "STW $src,$dst\t!stk" %} | |
| 5281 opcode(Assembler::stw_op3); | |
|
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5282 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5283 ins_pipe(istore_mem_reg); |
| 5284 %} | |
| 5285 | |
| 5286 // Load long from stack slot | |
| 5287 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{ | |
| 5288 match(Set dst src); | |
| 5289 | |
| 5290 ins_cost(MEMORY_REF_COST); | |
| 5291 size(4); | |
| 5292 format %{ "LDX $src,$dst\t! long" %} | |
| 5293 opcode(Assembler::ldx_op3); | |
|
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5294 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 5295 ins_pipe(iload_mem); |
| 5296 %} | |
| 5297 | |
| 5298 // Store long to stack slot | |
| 5299 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ | |
| 5300 match(Set dst src); | |
| 5301 | |
| 5302 ins_cost(MEMORY_REF_COST); | |
| 5303 size(4); | |
| 5304 format %{ "STX $src,$dst\t! long" %} | |
| 5305 opcode(Assembler::stx_op3); | |
|
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5306 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5307 ins_pipe(istore_mem_reg); |
| 5308 %} | |
| 5309 | |
| 5310 #ifdef _LP64 | |
| 5311 // Load pointer from stack slot, 64-bit encoding | |
| 5312 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
| 5313 match(Set dst src); | |
| 5314 ins_cost(MEMORY_REF_COST); | |
| 5315 size(4); | |
| 5316 format %{ "LDX $src,$dst\t!ptr" %} | |
| 5317 opcode(Assembler::ldx_op3); | |
|
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5318 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 5319 ins_pipe(iload_mem); |
| 5320 %} | |
| 5321 | |
| 5322 // Store pointer to stack slot | |
| 5323 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
| 5324 match(Set dst src); | |
| 5325 ins_cost(MEMORY_REF_COST); | |
| 5326 size(4); | |
| 5327 format %{ "STX $src,$dst\t!ptr" %} | |
| 5328 opcode(Assembler::stx_op3); | |
|
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5329 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5330 ins_pipe(istore_mem_reg); |
| 5331 %} | |
| 5332 #else // _LP64 | |
| 5333 // Load pointer from stack slot, 32-bit encoding | |
| 5334 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
| 5335 match(Set dst src); | |
| 5336 ins_cost(MEMORY_REF_COST); | |
| 5337 format %{ "LDUW $src,$dst\t!ptr" %} | |
| 5338 opcode(Assembler::lduw_op3, Assembler::ldst_op); | |
|
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5339 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 5340 ins_pipe(iload_mem); |
| 5341 %} | |
| 5342 | |
| 5343 // Store pointer to stack slot | |
| 5344 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
| 5345 match(Set dst src); | |
| 5346 ins_cost(MEMORY_REF_COST); | |
| 5347 format %{ "STW $src,$dst\t!ptr" %} | |
| 5348 opcode(Assembler::stw_op3, Assembler::ldst_op); | |
|
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5349 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 5350 ins_pipe(istore_mem_reg); |
| 5351 %} | |
| 5352 #endif // _LP64 | |
| 5353 | |
| 5354 //------------Special Nop instructions for bundling - no match rules----------- | |
| 5355 // Nop using the A0 functional unit | |
| 5356 instruct Nop_A0() %{ | |
| 5357 ins_cost(0); | |
| 5358 | |
| 5359 format %{ "NOP ! Alu Pipeline" %} | |
| 5360 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 5361 ins_encode( form2_nop() ); | |
| 5362 ins_pipe(ialu_nop_A0); | |
| 5363 %} | |
| 5364 | |
| 5365 // Nop using the A1 functional unit | |
| 5366 instruct Nop_A1( ) %{ | |
| 5367 ins_cost(0); | |
| 5368 | |
| 5369 format %{ "NOP ! Alu Pipeline" %} | |
| 5370 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 5371 ins_encode( form2_nop() ); | |
| 5372 ins_pipe(ialu_nop_A1); | |
| 5373 %} | |
| 5374 | |
| 5375 // Nop using the memory functional unit | |
| 5376 instruct Nop_MS( ) %{ | |
| 5377 ins_cost(0); | |
| 5378 | |
| 5379 format %{ "NOP ! Memory Pipeline" %} | |
| 5380 ins_encode( emit_mem_nop ); | |
| 5381 ins_pipe(mem_nop); | |
| 5382 %} | |
| 5383 | |
| 5384 // Nop using the floating add functional unit | |
| 5385 instruct Nop_FA( ) %{ | |
| 5386 ins_cost(0); | |
| 5387 | |
| 5388 format %{ "NOP ! Floating Add Pipeline" %} | |
| 5389 ins_encode( emit_fadd_nop ); | |
| 5390 ins_pipe(fadd_nop); | |
| 5391 %} | |
| 5392 | |
| 5393 // Nop using the branch functional unit | |
| 5394 instruct Nop_BR( ) %{ | |
| 5395 ins_cost(0); | |
| 5396 | |
| 5397 format %{ "NOP ! Branch Pipeline" %} | |
| 5398 ins_encode( emit_br_nop ); | |
| 5399 ins_pipe(br_nop); | |
| 5400 %} | |
| 5401 | |
| 5402 //----------Load/Store/Move Instructions--------------------------------------- | |
| 5403 //----------Load Instructions-------------------------------------------------- | |
| 5404 // Load Byte (8bit signed) | |
| 5405 instruct loadB(iRegI dst, memory mem) %{ | |
| 5406 match(Set dst (LoadB mem)); | |
| 5407 ins_cost(MEMORY_REF_COST); | |
| 5408 | |
| 5409 size(4); | |
| 624 | 5410 format %{ "LDSB $mem,$dst\t! byte" %} |
| 727 | 5411 ins_encode %{ |
| 5412 __ ldsb($mem$$Address, $dst$$Register); | |
| 5413 %} | |
| 624 | 5414 ins_pipe(iload_mask_mem); |
| 5415 %} | |
| 5416 | |
| 5417 // Load Byte (8bit signed) into a Long Register | |
| 5418 instruct loadB2L(iRegL dst, memory mem) %{ | |
| 5419 match(Set dst (ConvI2L (LoadB mem))); | |
| 5420 ins_cost(MEMORY_REF_COST); | |
| 5421 | |
| 5422 size(4); | |
| 5423 format %{ "LDSB $mem,$dst\t! byte -> long" %} | |
| 727 | 5424 ins_encode %{ |
| 5425 __ ldsb($mem$$Address, $dst$$Register); | |
| 5426 %} | |
| 0 | 5427 ins_pipe(iload_mask_mem); |
| 5428 %} | |
| 5429 | |
| 624 | 5430 // Load Unsigned Byte (8bit UNsigned) into an int reg |
| 5431 instruct loadUB(iRegI dst, memory mem) %{ | |
| 5432 match(Set dst (LoadUB mem)); | |
| 0 | 5433 ins_cost(MEMORY_REF_COST); |
| 5434 | |
| 5435 size(4); | |
| 624 | 5436 format %{ "LDUB $mem,$dst\t! ubyte" %} |
| 727 | 5437 ins_encode %{ |
| 5438 __ ldub($mem$$Address, $dst$$Register); | |
| 5439 %} | |
| 824 | 5440 ins_pipe(iload_mem); |
| 624 | 5441 %} |
| 5442 | |
| 5443 // Load Unsigned Byte (8bit UNsigned) into a Long Register | |
| 5444 instruct loadUB2L(iRegL dst, memory mem) %{ | |
| 5445 match(Set dst (ConvI2L (LoadUB mem))); | |
| 5446 ins_cost(MEMORY_REF_COST); | |
| 5447 | |
| 5448 size(4); | |
| 5449 format %{ "LDUB $mem,$dst\t! ubyte -> long" %} | |
| 727 | 5450 ins_encode %{ |
| 5451 __ ldub($mem$$Address, $dst$$Register); | |
| 5452 %} | |
| 824 | 5453 ins_pipe(iload_mem); |
| 5454 %} | |
| 5455 | |
| 5456 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register | |
| 5457 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{ | |
| 5458 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
| 5459 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
| 5460 | |
| 5461 size(2*4); | |
| 5462 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t" | |
| 5463 "AND $dst,$mask,$dst" %} | |
| 5464 ins_encode %{ | |
| 5465 __ ldub($mem$$Address, $dst$$Register); | |
| 5466 __ and3($dst$$Register, $mask$$constant, $dst$$Register); | |
| 5467 %} | |
| 5468 ins_pipe(iload_mem); | |
| 0 | 5469 %} |
| 5470 | |
| 624 | 5471 // Load Short (16bit signed) |
| 5472 instruct loadS(iRegI dst, memory mem) %{ | |
| 5473 match(Set dst (LoadS mem)); | |
| 5474 ins_cost(MEMORY_REF_COST); | |
| 5475 | |
| 5476 size(4); | |
| 5477 format %{ "LDSH $mem,$dst\t! short" %} | |
| 727 | 5478 ins_encode %{ |
| 5479 __ ldsh($mem$$Address, $dst$$Register); | |
| 5480 %} | |
| 624 | 5481 ins_pipe(iload_mask_mem); |
| 5482 %} | |
| 5483 | |
| 785 | 5484 // Load Short (16 bit signed) to Byte (8 bit signed) |
| 5485 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
| 5486 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); | |
| 5487 ins_cost(MEMORY_REF_COST); | |
| 5488 | |
| 5489 size(4); | |
| 5490 | |
| 5491 format %{ "LDSB $mem+1,$dst\t! short -> byte" %} | |
| 5492 ins_encode %{ | |
| 5493 __ ldsb($mem$$Address, $dst$$Register, 1); | |
| 5494 %} | |
| 5495 ins_pipe(iload_mask_mem); | |
| 5496 %} | |
| 5497 | |
| 624 | 5498 // Load Short (16bit signed) into a Long Register |
| 5499 instruct loadS2L(iRegL dst, memory mem) %{ | |
| 5500 match(Set dst (ConvI2L (LoadS mem))); | |
| 0 | 5501 ins_cost(MEMORY_REF_COST); |
| 5502 | |
| 5503 size(4); | |
| 624 | 5504 format %{ "LDSH $mem,$dst\t! short -> long" %} |
| 727 | 5505 ins_encode %{ |
| 5506 __ ldsh($mem$$Address, $dst$$Register); | |
| 5507 %} | |
| 624 | 5508 ins_pipe(iload_mask_mem); |
| 5509 %} | |
| 5510 | |
| 5511 // Load Unsigned Short/Char (16bit UNsigned) | |
| 5512 instruct loadUS(iRegI dst, memory mem) %{ | |
| 5513 match(Set dst (LoadUS mem)); | |
| 5514 ins_cost(MEMORY_REF_COST); | |
| 5515 | |
| 5516 size(4); | |
| 5517 format %{ "LDUH $mem,$dst\t! ushort/char" %} | |
| 727 | 5518 ins_encode %{ |
| 5519 __ lduh($mem$$Address, $dst$$Register); | |
| 5520 %} | |
| 824 | 5521 ins_pipe(iload_mem); |
| 0 | 5522 %} |
| 5523 | |
| 785 | 5524 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
| 5525 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
| 5526 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); | |
| 5527 ins_cost(MEMORY_REF_COST); | |
| 5528 | |
| 5529 size(4); | |
| 5530 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %} | |
| 5531 ins_encode %{ | |
| 5532 __ ldsb($mem$$Address, $dst$$Register, 1); | |
| 5533 %} | |
| 5534 ins_pipe(iload_mask_mem); | |
| 5535 %} | |
| 5536 | |
|
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5537 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register |
| 624 | 5538 instruct loadUS2L(iRegL dst, memory mem) %{ |
| 5539 match(Set dst (ConvI2L (LoadUS mem))); | |
| 0 | 5540 ins_cost(MEMORY_REF_COST); |
| 5541 | |
| 5542 size(4); | |
| 624 | 5543 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %} |
| 727 | 5544 ins_encode %{ |
| 5545 __ lduh($mem$$Address, $dst$$Register); | |
| 5546 %} | |
| 824 | 5547 ins_pipe(iload_mem); |
| 5548 %} | |
| 5549 | |
| 5550 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register | |
| 5551 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ | |
| 5552 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5553 ins_cost(MEMORY_REF_COST); | |
| 5554 | |
| 5555 size(4); | |
| 5556 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %} | |
| 5557 ins_encode %{ | |
| 5558 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE | |
| 5559 %} | |
| 5560 ins_pipe(iload_mem); | |
| 5561 %} | |
| 5562 | |
| 5563 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register | |
| 5564 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{ | |
| 5565 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5566 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
| 5567 | |
| 5568 size(2*4); | |
| 5569 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t" | |
| 5570 "AND $dst,$mask,$dst" %} | |
| 5571 ins_encode %{ | |
| 5572 Register Rdst = $dst$$Register; | |
| 5573 __ lduh($mem$$Address, Rdst); | |
| 5574 __ and3(Rdst, $mask$$constant, Rdst); | |
| 5575 %} | |
| 5576 ins_pipe(iload_mem); | |
| 5577 %} | |
| 5578 | |
| 5579 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register | |
| 5580 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{ | |
| 5581 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5582 effect(TEMP dst, TEMP tmp); | |
| 5583 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | |
| 5584 | |
|
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diff
changeset
|
5585 size((3+1)*4); // set may use two instructions. |
| 824 | 5586 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t" |
| 5587 "SET $mask,$tmp\n\t" | |
| 5588 "AND $dst,$tmp,$dst" %} | |
| 5589 ins_encode %{ | |
| 5590 Register Rdst = $dst$$Register; | |
| 5591 Register Rtmp = $tmp$$Register; | |
| 5592 __ lduh($mem$$Address, Rdst); | |
| 5593 __ set($mask$$constant, Rtmp); | |
| 5594 __ and3(Rdst, Rtmp, Rdst); | |
| 5595 %} | |
| 5596 ins_pipe(iload_mem); | |
| 0 | 5597 %} |
| 5598 | |
| 5599 // Load Integer | |
| 5600 instruct loadI(iRegI dst, memory mem) %{ | |
| 5601 match(Set dst (LoadI mem)); | |
| 5602 ins_cost(MEMORY_REF_COST); | |
| 624 | 5603 |
| 5604 size(4); | |
| 5605 format %{ "LDUW $mem,$dst\t! int" %} | |
| 727 | 5606 ins_encode %{ |
| 5607 __ lduw($mem$$Address, $dst$$Register); | |
| 5608 %} | |
| 624 | 5609 ins_pipe(iload_mem); |
| 5610 %} | |
| 5611 | |
| 785 | 5612 // Load Integer to Byte (8 bit signed) |
| 5613 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
| 5614 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); | |
| 5615 ins_cost(MEMORY_REF_COST); | |
| 5616 | |
| 5617 size(4); | |
| 5618 | |
| 5619 format %{ "LDSB $mem+3,$dst\t! int -> byte" %} | |
| 5620 ins_encode %{ | |
| 5621 __ ldsb($mem$$Address, $dst$$Register, 3); | |
| 5622 %} | |
| 5623 ins_pipe(iload_mask_mem); | |
| 5624 %} | |
| 5625 | |
| 5626 // Load Integer to Unsigned Byte (8 bit UNsigned) | |
| 5627 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{ | |
| 5628 match(Set dst (AndI (LoadI mem) mask)); | |
| 5629 ins_cost(MEMORY_REF_COST); | |
| 5630 | |
| 5631 size(4); | |
| 5632 | |
| 5633 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %} | |
| 5634 ins_encode %{ | |
| 5635 __ ldub($mem$$Address, $dst$$Register, 3); | |
| 5636 %} | |
| 5637 ins_pipe(iload_mask_mem); | |
| 5638 %} | |
| 5639 | |
| 5640 // Load Integer to Short (16 bit signed) | |
| 5641 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{ | |
| 5642 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); | |
| 5643 ins_cost(MEMORY_REF_COST); | |
| 5644 | |
| 5645 size(4); | |
| 5646 | |
| 5647 format %{ "LDSH $mem+2,$dst\t! int -> short" %} | |
| 5648 ins_encode %{ | |
| 5649 __ ldsh($mem$$Address, $dst$$Register, 2); | |
| 5650 %} | |
| 5651 ins_pipe(iload_mask_mem); | |
| 5652 %} | |
| 5653 | |
| 5654 // Load Integer to Unsigned Short (16 bit UNsigned) | |
| 5655 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{ | |
| 5656 match(Set dst (AndI (LoadI mem) mask)); | |
| 5657 ins_cost(MEMORY_REF_COST); | |
| 5658 | |
| 5659 size(4); | |
| 5660 | |
| 5661 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %} | |
| 5662 ins_encode %{ | |
| 5663 __ lduh($mem$$Address, $dst$$Register, 2); | |
| 5664 %} | |
| 5665 ins_pipe(iload_mask_mem); | |
| 5666 %} | |
| 5667 | |
| 624 | 5668 // Load Integer into a Long Register |
| 5669 instruct loadI2L(iRegL dst, memory mem) %{ | |
| 5670 match(Set dst (ConvI2L (LoadI mem))); | |
| 5671 ins_cost(MEMORY_REF_COST); | |
| 5672 | |
| 5673 size(4); | |
| 5674 format %{ "LDSW $mem,$dst\t! int -> long" %} | |
| 727 | 5675 ins_encode %{ |
| 5676 __ ldsw($mem$$Address, $dst$$Register); | |
| 5677 %} | |
| 824 | 5678 ins_pipe(iload_mask_mem); |
| 5679 %} | |
| 5680 | |
| 5681 // Load Integer with mask 0xFF into a Long Register | |
| 5682 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ | |
| 5683 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5684 ins_cost(MEMORY_REF_COST); | |
| 5685 | |
| 5686 size(4); | |
| 5687 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %} | |
| 5688 ins_encode %{ | |
| 5689 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE | |
| 5690 %} | |
| 5691 ins_pipe(iload_mem); | |
| 5692 %} | |
| 5693 | |
| 5694 // Load Integer with mask 0xFFFF into a Long Register | |
| 5695 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{ | |
| 5696 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5697 ins_cost(MEMORY_REF_COST); | |
| 5698 | |
| 5699 size(4); | |
| 5700 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %} | |
| 5701 ins_encode %{ | |
| 5702 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE | |
| 5703 %} | |
| 5704 ins_pipe(iload_mem); | |
| 5705 %} | |
| 5706 | |
| 5707 // Load Integer with a 13-bit mask into a Long Register | |
| 5708 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{ | |
| 5709 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5710 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
| 5711 | |
| 5712 size(2*4); | |
| 5713 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t" | |
| 5714 "AND $dst,$mask,$dst" %} | |
| 5715 ins_encode %{ | |
| 5716 Register Rdst = $dst$$Register; | |
| 5717 __ lduw($mem$$Address, Rdst); | |
| 5718 __ and3(Rdst, $mask$$constant, Rdst); | |
| 5719 %} | |
| 5720 ins_pipe(iload_mem); | |
| 5721 %} | |
| 5722 | |
| 5723 // Load Integer with a 32-bit mask into a Long Register | |
| 5724 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{ | |
| 5725 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 5726 effect(TEMP dst, TEMP tmp); | |
| 5727 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | |
| 5728 | |
|
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|
5729 size((3+1)*4); // set may use two instructions. |
| 824 | 5730 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t" |
| 5731 "SET $mask,$tmp\n\t" | |
| 5732 "AND $dst,$tmp,$dst" %} | |
| 5733 ins_encode %{ | |
| 5734 Register Rdst = $dst$$Register; | |
| 5735 Register Rtmp = $tmp$$Register; | |
| 5736 __ lduw($mem$$Address, Rdst); | |
| 5737 __ set($mask$$constant, Rtmp); | |
| 5738 __ and3(Rdst, Rtmp, Rdst); | |
| 5739 %} | |
| 624 | 5740 ins_pipe(iload_mem); |
| 5741 %} | |
| 5742 | |
| 5743 // Load Unsigned Integer into a Long Register | |
| 5744 instruct loadUI2L(iRegL dst, memory mem) %{ | |
| 5745 match(Set dst (LoadUI2L mem)); | |
| 5746 ins_cost(MEMORY_REF_COST); | |
| 5747 | |
| 5748 size(4); | |
| 5749 format %{ "LDUW $mem,$dst\t! uint -> long" %} | |
| 727 | 5750 ins_encode %{ |
| 5751 __ lduw($mem$$Address, $dst$$Register); | |
| 5752 %} | |
| 0 | 5753 ins_pipe(iload_mem); |
| 5754 %} | |
| 5755 | |
| 5756 // Load Long - aligned | |
| 5757 instruct loadL(iRegL dst, memory mem ) %{ | |
| 5758 match(Set dst (LoadL mem)); | |
| 5759 ins_cost(MEMORY_REF_COST); | |
| 624 | 5760 |
| 0 | 5761 size(4); |
| 5762 format %{ "LDX $mem,$dst\t! long" %} | |
| 727 | 5763 ins_encode %{ |
| 5764 __ ldx($mem$$Address, $dst$$Register); | |
| 5765 %} | |
| 0 | 5766 ins_pipe(iload_mem); |
| 5767 %} | |
| 5768 | |
| 5769 // Load Long - UNaligned | |
| 5770 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{ | |
| 5771 match(Set dst (LoadL_unaligned mem)); | |
| 5772 effect(KILL tmp); | |
| 5773 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
| 5774 size(16); | |
| 5775 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n" | |
| 5776 "\tLDUW $mem ,$dst\n" | |
| 5777 "\tSLLX #32, $dst, $dst\n" | |
| 5778 "\tOR $dst, R_O7, $dst" %} | |
| 5779 opcode(Assembler::lduw_op3); | |
|
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|
5780 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst )); |
| 0 | 5781 ins_pipe(iload_mem); |
| 5782 %} | |
| 5783 | |
| 5784 // Load Aligned Packed Byte into a Double Register | |
| 5785 instruct loadA8B(regD dst, memory mem) %{ | |
| 5786 match(Set dst (Load8B mem)); | |
| 5787 ins_cost(MEMORY_REF_COST); | |
| 5788 size(4); | |
| 5789 format %{ "LDDF $mem,$dst\t! packed8B" %} | |
| 5790 opcode(Assembler::lddf_op3); | |
|
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|
5791 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5792 ins_pipe(floadD_mem); |
| 5793 %} | |
| 5794 | |
| 5795 // Load Aligned Packed Char into a Double Register | |
| 5796 instruct loadA4C(regD dst, memory mem) %{ | |
| 5797 match(Set dst (Load4C mem)); | |
| 5798 ins_cost(MEMORY_REF_COST); | |
| 5799 size(4); | |
| 5800 format %{ "LDDF $mem,$dst\t! packed4C" %} | |
| 5801 opcode(Assembler::lddf_op3); | |
|
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|
5802 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5803 ins_pipe(floadD_mem); |
| 5804 %} | |
| 5805 | |
| 5806 // Load Aligned Packed Short into a Double Register | |
| 5807 instruct loadA4S(regD dst, memory mem) %{ | |
| 5808 match(Set dst (Load4S mem)); | |
| 5809 ins_cost(MEMORY_REF_COST); | |
| 5810 size(4); | |
| 5811 format %{ "LDDF $mem,$dst\t! packed4S" %} | |
| 5812 opcode(Assembler::lddf_op3); | |
|
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|
5813 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5814 ins_pipe(floadD_mem); |
| 5815 %} | |
| 5816 | |
| 5817 // Load Aligned Packed Int into a Double Register | |
| 5818 instruct loadA2I(regD dst, memory mem) %{ | |
| 5819 match(Set dst (Load2I mem)); | |
| 5820 ins_cost(MEMORY_REF_COST); | |
| 5821 size(4); | |
| 5822 format %{ "LDDF $mem,$dst\t! packed2I" %} | |
| 5823 opcode(Assembler::lddf_op3); | |
|
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|
5824 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5825 ins_pipe(floadD_mem); |
| 5826 %} | |
| 5827 | |
| 5828 // Load Range | |
| 5829 instruct loadRange(iRegI dst, memory mem) %{ | |
| 5830 match(Set dst (LoadRange mem)); | |
| 5831 ins_cost(MEMORY_REF_COST); | |
| 5832 | |
| 5833 size(4); | |
| 5834 format %{ "LDUW $mem,$dst\t! range" %} | |
| 5835 opcode(Assembler::lduw_op3); | |
|
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|
5836 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5837 ins_pipe(iload_mem); |
| 5838 %} | |
| 5839 | |
| 5840 // Load Integer into %f register (for fitos/fitod) | |
| 5841 instruct loadI_freg(regF dst, memory mem) %{ | |
| 5842 match(Set dst (LoadI mem)); | |
| 5843 ins_cost(MEMORY_REF_COST); | |
| 5844 size(4); | |
| 5845 | |
| 5846 format %{ "LDF $mem,$dst\t! for fitos/fitod" %} | |
| 5847 opcode(Assembler::ldf_op3); | |
|
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|
5848 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5849 ins_pipe(floadF_mem); |
| 5850 %} | |
| 5851 | |
| 5852 // Load Pointer | |
| 5853 instruct loadP(iRegP dst, memory mem) %{ | |
| 5854 match(Set dst (LoadP mem)); | |
| 5855 ins_cost(MEMORY_REF_COST); | |
| 5856 size(4); | |
| 5857 | |
| 5858 #ifndef _LP64 | |
| 5859 format %{ "LDUW $mem,$dst\t! ptr" %} | |
| 727 | 5860 ins_encode %{ |
| 5861 __ lduw($mem$$Address, $dst$$Register); | |
| 5862 %} | |
| 0 | 5863 #else |
| 5864 format %{ "LDX $mem,$dst\t! ptr" %} | |
| 727 | 5865 ins_encode %{ |
| 5866 __ ldx($mem$$Address, $dst$$Register); | |
| 5867 %} | |
| 0 | 5868 #endif |
| 5869 ins_pipe(iload_mem); | |
| 5870 %} | |
| 5871 | |
|
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diff
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|
5872 // Load Compressed Pointer |
|
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|
5873 instruct loadN(iRegN dst, memory mem) %{ |
| 727 | 5874 match(Set dst (LoadN mem)); |
| 5875 ins_cost(MEMORY_REF_COST); | |
| 5876 size(4); | |
| 5877 | |
| 5878 format %{ "LDUW $mem,$dst\t! compressed ptr" %} | |
| 5879 ins_encode %{ | |
| 5880 __ lduw($mem$$Address, $dst$$Register); | |
| 5881 %} | |
| 5882 ins_pipe(iload_mem); | |
|
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|
5883 %} |
|
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|
5884 |
| 0 | 5885 // Load Klass Pointer |
| 5886 instruct loadKlass(iRegP dst, memory mem) %{ | |
| 5887 match(Set dst (LoadKlass mem)); | |
| 5888 ins_cost(MEMORY_REF_COST); | |
| 5889 size(4); | |
| 5890 | |
| 5891 #ifndef _LP64 | |
| 5892 format %{ "LDUW $mem,$dst\t! klass ptr" %} | |
| 727 | 5893 ins_encode %{ |
| 5894 __ lduw($mem$$Address, $dst$$Register); | |
| 5895 %} | |
| 0 | 5896 #else |
| 5897 format %{ "LDX $mem,$dst\t! klass ptr" %} | |
| 727 | 5898 ins_encode %{ |
| 5899 __ ldx($mem$$Address, $dst$$Register); | |
| 5900 %} | |
| 0 | 5901 #endif |
| 5902 ins_pipe(iload_mem); | |
| 5903 %} | |
| 5904 | |
|
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|
5905 // Load narrow Klass Pointer |
|
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|
5906 instruct loadNKlass(iRegN dst, memory mem) %{ |
|
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|
5907 match(Set dst (LoadNKlass mem)); |
|
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|
5908 ins_cost(MEMORY_REF_COST); |
|
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|
5909 size(4); |
|
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|
5910 |
|
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|
5911 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} |
|
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|
5912 ins_encode %{ |
| 727 | 5913 __ lduw($mem$$Address, $dst$$Register); |
|
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5914 %} |
|
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|
5915 ins_pipe(iload_mem); |
|
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|
5916 %} |
|
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|
5917 |
| 0 | 5918 // Load Double |
| 5919 instruct loadD(regD dst, memory mem) %{ | |
| 5920 match(Set dst (LoadD mem)); | |
| 5921 ins_cost(MEMORY_REF_COST); | |
| 5922 | |
| 5923 size(4); | |
| 5924 format %{ "LDDF $mem,$dst" %} | |
| 5925 opcode(Assembler::lddf_op3); | |
|
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|
5926 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5927 ins_pipe(floadD_mem); |
| 5928 %} | |
| 5929 | |
| 5930 // Load Double - UNaligned | |
| 5931 instruct loadD_unaligned(regD_low dst, memory mem ) %{ | |
| 5932 match(Set dst (LoadD_unaligned mem)); | |
| 5933 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
| 5934 size(8); | |
| 5935 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n" | |
| 5936 "\tLDF $mem+4,$dst.lo\t!" %} | |
| 5937 opcode(Assembler::ldf_op3); | |
| 5938 ins_encode( form3_mem_reg_double_unaligned( mem, dst )); | |
| 5939 ins_pipe(iload_mem); | |
| 5940 %} | |
| 5941 | |
| 5942 // Load Float | |
| 5943 instruct loadF(regF dst, memory mem) %{ | |
| 5944 match(Set dst (LoadF mem)); | |
| 5945 ins_cost(MEMORY_REF_COST); | |
| 5946 | |
| 5947 size(4); | |
| 5948 format %{ "LDF $mem,$dst" %} | |
| 5949 opcode(Assembler::ldf_op3); | |
|
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|
5950 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 5951 ins_pipe(floadF_mem); |
| 5952 %} | |
| 5953 | |
| 5954 // Load Constant | |
| 5955 instruct loadConI( iRegI dst, immI src ) %{ | |
| 5956 match(Set dst src); | |
| 5957 ins_cost(DEFAULT_COST * 3/2); | |
| 5958 format %{ "SET $src,$dst" %} | |
| 5959 ins_encode( Set32(src, dst) ); | |
| 5960 ins_pipe(ialu_hi_lo_reg); | |
| 5961 %} | |
| 5962 | |
| 5963 instruct loadConI13( iRegI dst, immI13 src ) %{ | |
| 5964 match(Set dst src); | |
| 5965 | |
| 5966 size(4); | |
| 5967 format %{ "MOV $src,$dst" %} | |
| 5968 ins_encode( Set13( src, dst ) ); | |
| 5969 ins_pipe(ialu_imm); | |
| 5970 %} | |
| 5971 | |
| 5972 instruct loadConP(iRegP dst, immP src) %{ | |
| 5973 match(Set dst src); | |
| 5974 ins_cost(DEFAULT_COST * 3/2); | |
| 5975 format %{ "SET $src,$dst\t!ptr" %} | |
| 5976 // This rule does not use "expand" unlike loadConI because then | |
| 5977 // the result type is not known to be an Oop. An ADLC | |
| 5978 // enhancement will be needed to make that work - not worth it! | |
| 5979 | |
| 5980 ins_encode( SetPtr( src, dst ) ); | |
| 5981 ins_pipe(loadConP); | |
| 5982 | |
| 5983 %} | |
| 5984 | |
| 5985 instruct loadConP0(iRegP dst, immP0 src) %{ | |
| 5986 match(Set dst src); | |
| 5987 | |
| 5988 size(4); | |
| 5989 format %{ "CLR $dst\t!ptr" %} | |
| 5990 ins_encode( SetNull( dst ) ); | |
| 5991 ins_pipe(ialu_imm); | |
| 5992 %} | |
| 5993 | |
| 5994 instruct loadConP_poll(iRegP dst, immP_poll src) %{ | |
| 5995 match(Set dst src); | |
| 5996 ins_cost(DEFAULT_COST); | |
| 5997 format %{ "SET $src,$dst\t!ptr" %} | |
| 5998 ins_encode %{ | |
| 727 | 5999 AddressLiteral polling_page(os::get_polling_page()); |
| 6000 __ sethi(polling_page, reg_to_register_object($dst$$reg)); | |
| 0 | 6001 %} |
| 6002 ins_pipe(loadConP_poll); | |
| 6003 %} | |
| 6004 | |
|
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6005 instruct loadConN0(iRegN dst, immN0 src) %{ |
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6006 match(Set dst src); |
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6007 |
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6008 size(4); |
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6009 format %{ "CLR $dst\t! compressed NULL ptr" %} |
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6010 ins_encode( SetNull( dst ) ); |
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6011 ins_pipe(ialu_imm); |
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6012 %} |
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6013 |
|
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6014 instruct loadConN(iRegN dst, immN src) %{ |
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6015 match(Set dst src); |
|
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6016 ins_cost(DEFAULT_COST * 3/2); |
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6017 format %{ "SET $src,$dst\t! compressed ptr" %} |
|
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6018 ins_encode %{ |
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6019 Register dst = $dst$$Register; |
|
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6020 __ set_narrow_oop((jobject)$src$$constant, dst); |
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6021 %} |
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|
6022 ins_pipe(ialu_hi_lo_reg); |
|
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6023 %} |
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6024 |
| 0 | 6025 instruct loadConL(iRegL dst, immL src, o7RegL tmp) %{ |
| 6026 // %%% maybe this should work like loadConD | |
| 6027 match(Set dst src); | |
| 6028 effect(KILL tmp); | |
| 6029 ins_cost(DEFAULT_COST * 4); | |
| 6030 format %{ "SET64 $src,$dst KILL $tmp\t! long" %} | |
| 6031 ins_encode( LdImmL(src, dst, tmp) ); | |
| 6032 ins_pipe(loadConL); | |
| 6033 %} | |
| 6034 | |
| 6035 instruct loadConL0( iRegL dst, immL0 src ) %{ | |
| 6036 match(Set dst src); | |
| 6037 ins_cost(DEFAULT_COST); | |
| 6038 size(4); | |
| 6039 format %{ "CLR $dst\t! long" %} | |
| 6040 ins_encode( Set13( src, dst ) ); | |
| 6041 ins_pipe(ialu_imm); | |
| 6042 %} | |
| 6043 | |
| 6044 instruct loadConL13( iRegL dst, immL13 src ) %{ | |
| 6045 match(Set dst src); | |
| 6046 ins_cost(DEFAULT_COST * 2); | |
| 6047 | |
| 6048 size(4); | |
| 6049 format %{ "MOV $src,$dst\t! long" %} | |
| 6050 ins_encode( Set13( src, dst ) ); | |
| 6051 ins_pipe(ialu_imm); | |
| 6052 %} | |
| 6053 | |
| 6054 instruct loadConF(regF dst, immF src, o7RegP tmp) %{ | |
| 6055 match(Set dst src); | |
| 6056 effect(KILL tmp); | |
| 6057 | |
| 6058 #ifdef _LP64 | |
| 727 | 6059 size(8*4); |
| 0 | 6060 #else |
| 727 | 6061 size(2*4); |
| 0 | 6062 #endif |
| 6063 | |
| 6064 format %{ "SETHI hi(&$src),$tmp\t!get float $src from table\n\t" | |
| 6065 "LDF [$tmp+lo(&$src)],$dst" %} | |
| 727 | 6066 ins_encode %{ |
| 6067 address float_address = __ float_constant($src$$constant); | |
| 6068 RelocationHolder rspec = internal_word_Relocation::spec(float_address); | |
| 6069 AddressLiteral addrlit(float_address, rspec); | |
| 6070 | |
| 6071 __ sethi(addrlit, $tmp$$Register); | |
| 6072 __ ldf(FloatRegisterImpl::S, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec); | |
| 6073 %} | |
| 0 | 6074 ins_pipe(loadConFD); |
| 6075 %} | |
| 6076 | |
| 6077 instruct loadConD(regD dst, immD src, o7RegP tmp) %{ | |
| 6078 match(Set dst src); | |
| 6079 effect(KILL tmp); | |
| 6080 | |
| 6081 #ifdef _LP64 | |
| 727 | 6082 size(8*4); |
| 0 | 6083 #else |
| 727 | 6084 size(2*4); |
| 0 | 6085 #endif |
| 6086 | |
| 6087 format %{ "SETHI hi(&$src),$tmp\t!get double $src from table\n\t" | |
| 6088 "LDDF [$tmp+lo(&$src)],$dst" %} | |
| 727 | 6089 ins_encode %{ |
| 6090 address double_address = __ double_constant($src$$constant); | |
| 6091 RelocationHolder rspec = internal_word_Relocation::spec(double_address); | |
| 6092 AddressLiteral addrlit(double_address, rspec); | |
| 6093 | |
| 6094 __ sethi(addrlit, $tmp$$Register); | |
|
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|
6095 // XXX This is a quick fix for 6833573. |
|
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|
6096 //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec); |
|
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|
6097 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec); |
| 727 | 6098 %} |
| 0 | 6099 ins_pipe(loadConFD); |
| 6100 %} | |
| 6101 | |
| 6102 // Prefetch instructions. | |
| 6103 // Must be safe to execute with invalid address (cannot fault). | |
| 6104 | |
| 6105 instruct prefetchr( memory mem ) %{ | |
| 6106 match( PrefetchRead mem ); | |
| 6107 ins_cost(MEMORY_REF_COST); | |
| 6108 | |
| 6109 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %} | |
| 6110 opcode(Assembler::prefetch_op3); | |
| 6111 ins_encode( form3_mem_prefetch_read( mem ) ); | |
| 6112 ins_pipe(iload_mem); | |
| 6113 %} | |
| 6114 | |
| 6115 instruct prefetchw( memory mem ) %{ | |
|
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6116 predicate(AllocatePrefetchStyle != 3 ); |
| 0 | 6117 match( PrefetchWrite mem ); |
| 6118 ins_cost(MEMORY_REF_COST); | |
| 6119 | |
| 6120 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %} | |
| 6121 opcode(Assembler::prefetch_op3); | |
| 6122 ins_encode( form3_mem_prefetch_write( mem ) ); | |
| 6123 ins_pipe(iload_mem); | |
| 6124 %} | |
| 6125 | |
|
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6126 // Use BIS instruction to prefetch. |
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6127 instruct prefetchw_bis( memory mem ) %{ |
|
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|
6128 predicate(AllocatePrefetchStyle == 3); |
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6129 match( PrefetchWrite mem ); |
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|
6130 ins_cost(MEMORY_REF_COST); |
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|
6131 |
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6132 format %{ "STXA G0,$mem\t! // Block initializing store" %} |
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6133 ins_encode %{ |
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6134 Register base = as_Register($mem$$base); |
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|
6135 int disp = $mem$$disp; |
|
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|
6136 if (disp != 0) { |
|
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|
6137 __ add(base, AllocatePrefetchStepSize, base); |
|
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|
6138 } |
|
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6139 __ stxa(G0, base, G0, ASI_BLK_INIT_QUAD_LDD_P); |
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|
6140 %} |
|
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|
6141 ins_pipe(istore_mem_reg); |
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6142 %} |
| 0 | 6143 |
| 6144 //----------Store Instructions------------------------------------------------- | |
| 6145 // Store Byte | |
| 6146 instruct storeB(memory mem, iRegI src) %{ | |
| 6147 match(Set mem (StoreB mem src)); | |
| 6148 ins_cost(MEMORY_REF_COST); | |
| 6149 | |
| 6150 size(4); | |
| 6151 format %{ "STB $src,$mem\t! byte" %} | |
| 6152 opcode(Assembler::stb_op3); | |
|
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|
6153 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6154 ins_pipe(istore_mem_reg); |
| 6155 %} | |
| 6156 | |
| 6157 instruct storeB0(memory mem, immI0 src) %{ | |
| 6158 match(Set mem (StoreB mem src)); | |
| 6159 ins_cost(MEMORY_REF_COST); | |
| 6160 | |
| 6161 size(4); | |
| 6162 format %{ "STB $src,$mem\t! byte" %} | |
| 6163 opcode(Assembler::stb_op3); | |
|
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|
6164 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6165 ins_pipe(istore_mem_zero); |
| 6166 %} | |
| 6167 | |
| 6168 instruct storeCM0(memory mem, immI0 src) %{ | |
| 6169 match(Set mem (StoreCM mem src)); | |
| 6170 ins_cost(MEMORY_REF_COST); | |
| 6171 | |
| 6172 size(4); | |
| 6173 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %} | |
| 6174 opcode(Assembler::stb_op3); | |
|
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|
6175 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6176 ins_pipe(istore_mem_zero); |
| 6177 %} | |
| 6178 | |
| 6179 // Store Char/Short | |
| 6180 instruct storeC(memory mem, iRegI src) %{ | |
| 6181 match(Set mem (StoreC mem src)); | |
| 6182 ins_cost(MEMORY_REF_COST); | |
| 6183 | |
| 6184 size(4); | |
| 6185 format %{ "STH $src,$mem\t! short" %} | |
| 6186 opcode(Assembler::sth_op3); | |
|
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|
6187 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6188 ins_pipe(istore_mem_reg); |
| 6189 %} | |
| 6190 | |
| 6191 instruct storeC0(memory mem, immI0 src) %{ | |
| 6192 match(Set mem (StoreC mem src)); | |
| 6193 ins_cost(MEMORY_REF_COST); | |
| 6194 | |
| 6195 size(4); | |
| 6196 format %{ "STH $src,$mem\t! short" %} | |
| 6197 opcode(Assembler::sth_op3); | |
|
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|
6198 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6199 ins_pipe(istore_mem_zero); |
| 6200 %} | |
| 6201 | |
| 6202 // Store Integer | |
| 6203 instruct storeI(memory mem, iRegI src) %{ | |
| 6204 match(Set mem (StoreI mem src)); | |
| 6205 ins_cost(MEMORY_REF_COST); | |
| 6206 | |
| 6207 size(4); | |
| 6208 format %{ "STW $src,$mem" %} | |
| 6209 opcode(Assembler::stw_op3); | |
|
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|
6210 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6211 ins_pipe(istore_mem_reg); |
| 6212 %} | |
| 6213 | |
| 6214 // Store Long | |
| 6215 instruct storeL(memory mem, iRegL src) %{ | |
| 6216 match(Set mem (StoreL mem src)); | |
| 6217 ins_cost(MEMORY_REF_COST); | |
| 6218 size(4); | |
| 6219 format %{ "STX $src,$mem\t! long" %} | |
| 6220 opcode(Assembler::stx_op3); | |
|
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|
6221 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6222 ins_pipe(istore_mem_reg); |
| 6223 %} | |
| 6224 | |
| 6225 instruct storeI0(memory mem, immI0 src) %{ | |
| 6226 match(Set mem (StoreI mem src)); | |
| 6227 ins_cost(MEMORY_REF_COST); | |
| 6228 | |
| 6229 size(4); | |
| 6230 format %{ "STW $src,$mem" %} | |
| 6231 opcode(Assembler::stw_op3); | |
|
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|
6232 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6233 ins_pipe(istore_mem_zero); |
| 6234 %} | |
| 6235 | |
| 6236 instruct storeL0(memory mem, immL0 src) %{ | |
| 6237 match(Set mem (StoreL mem src)); | |
| 6238 ins_cost(MEMORY_REF_COST); | |
| 6239 | |
| 6240 size(4); | |
| 6241 format %{ "STX $src,$mem" %} | |
| 6242 opcode(Assembler::stx_op3); | |
|
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6243 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6244 ins_pipe(istore_mem_zero); |
| 6245 %} | |
| 6246 | |
| 6247 // Store Integer from float register (used after fstoi) | |
| 6248 instruct storeI_Freg(memory mem, regF src) %{ | |
| 6249 match(Set mem (StoreI mem src)); | |
| 6250 ins_cost(MEMORY_REF_COST); | |
| 6251 | |
| 6252 size(4); | |
| 6253 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %} | |
| 6254 opcode(Assembler::stf_op3); | |
|
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6255 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6256 ins_pipe(fstoreF_mem_reg); |
| 6257 %} | |
| 6258 | |
| 6259 // Store Pointer | |
| 6260 instruct storeP(memory dst, sp_ptr_RegP src) %{ | |
| 6261 match(Set dst (StoreP dst src)); | |
| 6262 ins_cost(MEMORY_REF_COST); | |
| 6263 size(4); | |
| 6264 | |
| 6265 #ifndef _LP64 | |
| 6266 format %{ "STW $src,$dst\t! ptr" %} | |
| 6267 opcode(Assembler::stw_op3, 0, REGP_OP); | |
| 6268 #else | |
| 6269 format %{ "STX $src,$dst\t! ptr" %} | |
| 6270 opcode(Assembler::stx_op3, 0, REGP_OP); | |
| 6271 #endif | |
| 6272 ins_encode( form3_mem_reg( dst, src ) ); | |
| 6273 ins_pipe(istore_mem_spORreg); | |
| 6274 %} | |
| 6275 | |
| 6276 instruct storeP0(memory dst, immP0 src) %{ | |
| 6277 match(Set dst (StoreP dst src)); | |
| 6278 ins_cost(MEMORY_REF_COST); | |
| 6279 size(4); | |
| 6280 | |
| 6281 #ifndef _LP64 | |
| 6282 format %{ "STW $src,$dst\t! ptr" %} | |
| 6283 opcode(Assembler::stw_op3, 0, REGP_OP); | |
| 6284 #else | |
| 6285 format %{ "STX $src,$dst\t! ptr" %} | |
| 6286 opcode(Assembler::stx_op3, 0, REGP_OP); | |
| 6287 #endif | |
| 6288 ins_encode( form3_mem_reg( dst, R_G0 ) ); | |
| 6289 ins_pipe(istore_mem_zero); | |
| 6290 %} | |
| 6291 | |
|
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6292 // Store Compressed Pointer |
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6293 instruct storeN(memory dst, iRegN src) %{ |
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6294 match(Set dst (StoreN dst src)); |
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6295 ins_cost(MEMORY_REF_COST); |
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|
6296 size(4); |
|
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|
6297 |
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|
6298 format %{ "STW $src,$dst\t! compressed ptr" %} |
|
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6299 ins_encode %{ |
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6300 Register base = as_Register($dst$$base); |
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6301 Register index = as_Register($dst$$index); |
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6302 Register src = $src$$Register; |
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6303 if (index != G0) { |
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6304 __ stw(src, base, index); |
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6305 } else { |
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6306 __ stw(src, base, $dst$$disp); |
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6307 } |
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6308 %} |
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6309 ins_pipe(istore_mem_spORreg); |
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6310 %} |
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6311 |
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6312 instruct storeN0(memory dst, immN0 src) %{ |
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6313 match(Set dst (StoreN dst src)); |
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6314 ins_cost(MEMORY_REF_COST); |
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6315 size(4); |
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6316 |
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6317 format %{ "STW $src,$dst\t! compressed ptr" %} |
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6318 ins_encode %{ |
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6319 Register base = as_Register($dst$$base); |
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6320 Register index = as_Register($dst$$index); |
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6321 if (index != G0) { |
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6322 __ stw(0, base, index); |
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6323 } else { |
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6324 __ stw(0, base, $dst$$disp); |
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6325 } |
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6326 %} |
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6327 ins_pipe(istore_mem_zero); |
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6328 %} |
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6329 |
| 0 | 6330 // Store Double |
| 6331 instruct storeD( memory mem, regD src) %{ | |
| 6332 match(Set mem (StoreD mem src)); | |
| 6333 ins_cost(MEMORY_REF_COST); | |
| 6334 | |
| 6335 size(4); | |
| 6336 format %{ "STDF $src,$mem" %} | |
| 6337 opcode(Assembler::stdf_op3); | |
|
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6338 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6339 ins_pipe(fstoreD_mem_reg); |
| 6340 %} | |
| 6341 | |
| 6342 instruct storeD0( memory mem, immD0 src) %{ | |
| 6343 match(Set mem (StoreD mem src)); | |
| 6344 ins_cost(MEMORY_REF_COST); | |
| 6345 | |
| 6346 size(4); | |
| 6347 format %{ "STX $src,$mem" %} | |
| 6348 opcode(Assembler::stx_op3); | |
|
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6349 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6350 ins_pipe(fstoreD_mem_zero); |
| 6351 %} | |
| 6352 | |
| 6353 // Store Float | |
| 6354 instruct storeF( memory mem, regF src) %{ | |
| 6355 match(Set mem (StoreF mem src)); | |
| 6356 ins_cost(MEMORY_REF_COST); | |
| 6357 | |
| 6358 size(4); | |
| 6359 format %{ "STF $src,$mem" %} | |
| 6360 opcode(Assembler::stf_op3); | |
|
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6361 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6362 ins_pipe(fstoreF_mem_reg); |
| 6363 %} | |
| 6364 | |
| 6365 instruct storeF0( memory mem, immF0 src) %{ | |
| 6366 match(Set mem (StoreF mem src)); | |
| 6367 ins_cost(MEMORY_REF_COST); | |
| 6368 | |
| 6369 size(4); | |
| 6370 format %{ "STW $src,$mem\t! storeF0" %} | |
| 6371 opcode(Assembler::stw_op3); | |
|
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|
6372 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6373 ins_pipe(fstoreF_mem_zero); |
| 6374 %} | |
| 6375 | |
| 6376 // Store Aligned Packed Bytes in Double register to memory | |
| 6377 instruct storeA8B(memory mem, regD src) %{ | |
| 6378 match(Set mem (Store8B mem src)); | |
| 6379 ins_cost(MEMORY_REF_COST); | |
| 6380 size(4); | |
| 6381 format %{ "STDF $src,$mem\t! packed8B" %} | |
| 6382 opcode(Assembler::stdf_op3); | |
|
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6383 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6384 ins_pipe(fstoreD_mem_reg); |
| 6385 %} | |
| 6386 | |
|
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6387 // Convert oop pointer into compressed form |
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6388 instruct encodeHeapOop(iRegN dst, iRegP src) %{ |
|
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6389 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); |
|
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6390 match(Set dst (EncodeP src)); |
|
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6391 format %{ "encode_heap_oop $src, $dst" %} |
|
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6392 ins_encode %{ |
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6393 __ encode_heap_oop($src$$Register, $dst$$Register); |
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6394 %} |
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6395 ins_pipe(ialu_reg); |
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6396 %} |
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6397 |
|
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6398 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{ |
|
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6399 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); |
|
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6400 match(Set dst (EncodeP src)); |
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6401 format %{ "encode_heap_oop_not_null $src, $dst" %} |
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6402 ins_encode %{ |
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6403 __ encode_heap_oop_not_null($src$$Register, $dst$$Register); |
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6404 %} |
|
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|
6405 ins_pipe(ialu_reg); |
|
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|
6406 %} |
|
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|
6407 |
|
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6408 instruct decodeHeapOop(iRegP dst, iRegN src) %{ |
|
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6409 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && |
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6410 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); |
|
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6411 match(Set dst (DecodeN src)); |
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6412 format %{ "decode_heap_oop $src, $dst" %} |
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6413 ins_encode %{ |
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6414 __ decode_heap_oop($src$$Register, $dst$$Register); |
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6415 %} |
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6416 ins_pipe(ialu_reg); |
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6417 %} |
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|
6418 |
|
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6419 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{ |
|
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6420 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || |
|
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|
6421 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); |
|
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6422 match(Set dst (DecodeN src)); |
|
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6423 format %{ "decode_heap_oop_not_null $src, $dst" %} |
|
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|
6424 ins_encode %{ |
|
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|
6425 __ decode_heap_oop_not_null($src$$Register, $dst$$Register); |
|
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6426 %} |
|
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|
6427 ins_pipe(ialu_reg); |
|
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|
6428 %} |
|
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|
6429 |
|
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6430 |
| 0 | 6431 // Store Zero into Aligned Packed Bytes |
| 6432 instruct storeA8B0(memory mem, immI0 zero) %{ | |
| 6433 match(Set mem (Store8B mem zero)); | |
| 6434 ins_cost(MEMORY_REF_COST); | |
| 6435 size(4); | |
| 6436 format %{ "STX $zero,$mem\t! packed8B" %} | |
| 6437 opcode(Assembler::stx_op3); | |
|
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6438 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6439 ins_pipe(fstoreD_mem_zero); |
| 6440 %} | |
| 6441 | |
| 6442 // Store Aligned Packed Chars/Shorts in Double register to memory | |
| 6443 instruct storeA4C(memory mem, regD src) %{ | |
| 6444 match(Set mem (Store4C mem src)); | |
| 6445 ins_cost(MEMORY_REF_COST); | |
| 6446 size(4); | |
| 6447 format %{ "STDF $src,$mem\t! packed4C" %} | |
| 6448 opcode(Assembler::stdf_op3); | |
|
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6449 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6450 ins_pipe(fstoreD_mem_reg); |
| 6451 %} | |
| 6452 | |
| 6453 // Store Zero into Aligned Packed Chars/Shorts | |
| 6454 instruct storeA4C0(memory mem, immI0 zero) %{ | |
| 6455 match(Set mem (Store4C mem (Replicate4C zero))); | |
| 6456 ins_cost(MEMORY_REF_COST); | |
| 6457 size(4); | |
| 6458 format %{ "STX $zero,$mem\t! packed4C" %} | |
| 6459 opcode(Assembler::stx_op3); | |
|
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6460 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6461 ins_pipe(fstoreD_mem_zero); |
| 6462 %} | |
| 6463 | |
| 6464 // Store Aligned Packed Ints in Double register to memory | |
| 6465 instruct storeA2I(memory mem, regD src) %{ | |
| 6466 match(Set mem (Store2I mem src)); | |
| 6467 ins_cost(MEMORY_REF_COST); | |
| 6468 size(4); | |
| 6469 format %{ "STDF $src,$mem\t! packed2I" %} | |
| 6470 opcode(Assembler::stdf_op3); | |
|
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6471 ins_encode(simple_form3_mem_reg( mem, src ) ); |
| 0 | 6472 ins_pipe(fstoreD_mem_reg); |
| 6473 %} | |
| 6474 | |
| 6475 // Store Zero into Aligned Packed Ints | |
| 6476 instruct storeA2I0(memory mem, immI0 zero) %{ | |
| 6477 match(Set mem (Store2I mem zero)); | |
| 6478 ins_cost(MEMORY_REF_COST); | |
| 6479 size(4); | |
| 6480 format %{ "STX $zero,$mem\t! packed2I" %} | |
| 6481 opcode(Assembler::stx_op3); | |
|
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|
6482 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
| 0 | 6483 ins_pipe(fstoreD_mem_zero); |
| 6484 %} | |
| 6485 | |
| 6486 | |
| 6487 //----------MemBar Instructions----------------------------------------------- | |
| 6488 // Memory barrier flavors | |
| 6489 | |
| 6490 instruct membar_acquire() %{ | |
| 6491 match(MemBarAcquire); | |
| 6492 ins_cost(4*MEMORY_REF_COST); | |
| 6493 | |
| 6494 size(0); | |
| 6495 format %{ "MEMBAR-acquire" %} | |
| 6496 ins_encode( enc_membar_acquire ); | |
| 6497 ins_pipe(long_memory_op); | |
| 6498 %} | |
| 6499 | |
| 6500 instruct membar_acquire_lock() %{ | |
| 6501 match(MemBarAcquire); | |
| 6502 predicate(Matcher::prior_fast_lock(n)); | |
| 6503 ins_cost(0); | |
| 6504 | |
| 6505 size(0); | |
| 6506 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} | |
| 6507 ins_encode( ); | |
| 6508 ins_pipe(empty); | |
| 6509 %} | |
| 6510 | |
| 6511 instruct membar_release() %{ | |
| 6512 match(MemBarRelease); | |
| 6513 ins_cost(4*MEMORY_REF_COST); | |
| 6514 | |
| 6515 size(0); | |
| 6516 format %{ "MEMBAR-release" %} | |
| 6517 ins_encode( enc_membar_release ); | |
| 6518 ins_pipe(long_memory_op); | |
| 6519 %} | |
| 6520 | |
| 6521 instruct membar_release_lock() %{ | |
| 6522 match(MemBarRelease); | |
| 6523 predicate(Matcher::post_fast_unlock(n)); | |
| 6524 ins_cost(0); | |
| 6525 | |
| 6526 size(0); | |
| 6527 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} | |
| 6528 ins_encode( ); | |
| 6529 ins_pipe(empty); | |
| 6530 %} | |
| 6531 | |
| 6532 instruct membar_volatile() %{ | |
| 6533 match(MemBarVolatile); | |
| 6534 ins_cost(4*MEMORY_REF_COST); | |
| 6535 | |
| 6536 size(4); | |
| 6537 format %{ "MEMBAR-volatile" %} | |
| 6538 ins_encode( enc_membar_volatile ); | |
| 6539 ins_pipe(long_memory_op); | |
| 6540 %} | |
| 6541 | |
| 6542 instruct unnecessary_membar_volatile() %{ | |
| 6543 match(MemBarVolatile); | |
| 6544 predicate(Matcher::post_store_load_barrier(n)); | |
| 6545 ins_cost(0); | |
| 6546 | |
| 6547 size(0); | |
| 6548 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %} | |
| 6549 ins_encode( ); | |
| 6550 ins_pipe(empty); | |
| 6551 %} | |
| 6552 | |
| 6553 //----------Register Move Instructions----------------------------------------- | |
| 6554 instruct roundDouble_nop(regD dst) %{ | |
| 6555 match(Set dst (RoundDouble dst)); | |
| 6556 ins_cost(0); | |
| 6557 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
| 6558 ins_encode( ); | |
| 6559 ins_pipe(empty); | |
| 6560 %} | |
| 6561 | |
| 6562 | |
| 6563 instruct roundFloat_nop(regF dst) %{ | |
| 6564 match(Set dst (RoundFloat dst)); | |
| 6565 ins_cost(0); | |
| 6566 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
| 6567 ins_encode( ); | |
| 6568 ins_pipe(empty); | |
| 6569 %} | |
| 6570 | |
| 6571 | |
| 6572 // Cast Index to Pointer for unsafe natives | |
| 6573 instruct castX2P(iRegX src, iRegP dst) %{ | |
| 6574 match(Set dst (CastX2P src)); | |
| 6575 | |
| 6576 format %{ "MOV $src,$dst\t! IntX->Ptr" %} | |
| 6577 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
| 6578 ins_pipe(ialu_reg); | |
| 6579 %} | |
| 6580 | |
| 6581 // Cast Pointer to Index for unsafe natives | |
| 6582 instruct castP2X(iRegP src, iRegX dst) %{ | |
| 6583 match(Set dst (CastP2X src)); | |
| 6584 | |
| 6585 format %{ "MOV $src,$dst\t! Ptr->IntX" %} | |
| 6586 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
| 6587 ins_pipe(ialu_reg); | |
| 6588 %} | |
| 6589 | |
| 6590 instruct stfSSD(stackSlotD stkSlot, regD src) %{ | |
| 6591 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
| 6592 match(Set stkSlot src); // chain rule | |
| 6593 ins_cost(MEMORY_REF_COST); | |
| 6594 format %{ "STDF $src,$stkSlot\t!stk" %} | |
| 6595 opcode(Assembler::stdf_op3); | |
|
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6596 ins_encode(simple_form3_mem_reg(stkSlot, src)); |
| 0 | 6597 ins_pipe(fstoreD_stk_reg); |
| 6598 %} | |
| 6599 | |
| 6600 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{ | |
| 6601 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
| 6602 match(Set dst stkSlot); // chain rule | |
| 6603 ins_cost(MEMORY_REF_COST); | |
| 6604 format %{ "LDDF $stkSlot,$dst\t!stk" %} | |
| 6605 opcode(Assembler::lddf_op3); | |
|
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|
6606 ins_encode(simple_form3_mem_reg(stkSlot, dst)); |
| 0 | 6607 ins_pipe(floadD_stk); |
| 6608 %} | |
| 6609 | |
| 6610 instruct stfSSF(stackSlotF stkSlot, regF src) %{ | |
| 6611 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
| 6612 match(Set stkSlot src); // chain rule | |
| 6613 ins_cost(MEMORY_REF_COST); | |
| 6614 format %{ "STF $src,$stkSlot\t!stk" %} | |
| 6615 opcode(Assembler::stf_op3); | |
|
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|
6616 ins_encode(simple_form3_mem_reg(stkSlot, src)); |
| 0 | 6617 ins_pipe(fstoreF_stk_reg); |
| 6618 %} | |
| 6619 | |
| 6620 //----------Conditional Move--------------------------------------------------- | |
| 6621 // Conditional move | |
| 6622 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{ | |
| 6623 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
| 6624 ins_cost(150); | |
| 6625 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
| 6626 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6627 ins_pipe(ialu_reg); | |
| 6628 %} | |
| 6629 | |
| 6630 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{ | |
| 6631 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
| 6632 ins_cost(140); | |
| 6633 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
| 6634 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6635 ins_pipe(ialu_imm); | |
| 6636 %} | |
| 6637 | |
| 6638 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{ | |
| 6639 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
| 6640 ins_cost(150); | |
| 6641 size(4); | |
| 6642 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6643 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6644 ins_pipe(ialu_reg); | |
| 6645 %} | |
| 6646 | |
| 6647 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{ | |
| 6648 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
| 6649 ins_cost(140); | |
| 6650 size(4); | |
| 6651 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6652 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
| 6653 ins_pipe(ialu_imm); | |
| 6654 %} | |
| 6655 | |
|
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|
6656 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{ |
| 0 | 6657 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
| 6658 ins_cost(150); | |
| 6659 size(4); | |
| 6660 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6661 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6662 ins_pipe(ialu_reg); | |
| 6663 %} | |
| 6664 | |
|
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|
6665 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{ |
| 0 | 6666 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
| 6667 ins_cost(140); | |
| 6668 size(4); | |
| 6669 format %{ "MOV$cmp $icc,$src,$dst" %} | |
| 6670 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
| 6671 ins_pipe(ialu_imm); | |
| 6672 %} | |
| 6673 | |
| 6674 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{ | |
| 6675 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
| 6676 ins_cost(150); | |
| 6677 size(4); | |
| 6678 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 6679 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
| 6680 ins_pipe(ialu_reg); | |
| 6681 %} | |
| 6682 | |
| 6683 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{ | |
| 6684 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
| 6685 ins_cost(140); | |
| 6686 size(4); | |
| 6687 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 6688 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
| 6689 ins_pipe(ialu_imm); | |
| 6690 %} | |
| 6691 | |
|
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|
6692 // Conditional move for RegN. Only cmov(reg,reg). |
|
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|
6693 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{ |
|
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|
6694 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src))); |
|
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|
6695 ins_cost(150); |
|
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|
6696 format %{ "MOV$cmp $pcc,$src,$dst" %} |
|
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|
6697 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); |
|
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|
6698 ins_pipe(ialu_reg); |
|
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|
6699 %} |
|
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|
6700 |
|
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|
6701 // This instruction also works with CmpN so we don't need cmovNN_reg. |
|
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|
6702 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{ |
|
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|
6703 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
|
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|
6704 ins_cost(150); |
|
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|
6705 size(4); |
|
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|
6706 format %{ "MOV$cmp $icc,$src,$dst" %} |
|
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|
6707 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
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|
6708 ins_pipe(ialu_reg); |
|
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|
6709 %} |
|
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|
6710 |
|
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|
6711 // This instruction also works with CmpN so we don't need cmovNN_reg. |
|
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|
6712 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{ |
|
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|
6713 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
|
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|
6714 ins_cost(150); |
|
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|
6715 size(4); |
|
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|
6716 format %{ "MOV$cmp $icc,$src,$dst" %} |
|
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|
6717 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
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|
6718 ins_pipe(ialu_reg); |
|
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|
6719 %} |
|
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|
6720 |
|
164
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|
6721 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{ |
|
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|
6722 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src))); |
|
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|
6723 ins_cost(150); |
|
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|
6724 size(4); |
|
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|
6725 format %{ "MOV$cmp $fcc,$src,$dst" %} |
|
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|
6726 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); |
|
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|
6727 ins_pipe(ialu_reg); |
|
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|
6728 %} |
|
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|
6729 |
| 0 | 6730 // Conditional move |
| 6731 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{ | |
| 6732 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
| 6733 ins_cost(150); | |
| 6734 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
| 6735 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6736 ins_pipe(ialu_reg); | |
| 6737 %} | |
| 6738 | |
| 6739 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{ | |
| 6740 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
| 6741 ins_cost(140); | |
| 6742 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
| 6743 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6744 ins_pipe(ialu_imm); | |
| 6745 %} | |
| 6746 | |
|
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|
6747 // This instruction also works with CmpN so we don't need cmovPN_reg. |
| 0 | 6748 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{ |
| 6749 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
| 6750 ins_cost(150); | |
| 6751 | |
| 6752 size(4); | |
| 6753 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
| 6754 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6755 ins_pipe(ialu_reg); | |
| 6756 %} | |
| 6757 | |
|
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|
6758 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{ |
|
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|
6759 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
|
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|
6760 ins_cost(150); |
|
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|
6761 |
|
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|
6762 size(4); |
|
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|
6763 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} |
|
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|
6764 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
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|
6765 ins_pipe(ialu_reg); |
|
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|
6766 %} |
|
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|
6767 |
| 0 | 6768 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{ |
| 6769 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
| 6770 ins_cost(140); | |
| 6771 | |
| 6772 size(4); | |
| 6773 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
| 6774 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
| 6775 ins_pipe(ialu_imm); | |
| 6776 %} | |
| 6777 | |
|
1160
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|
6778 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{ |
|
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|
6779 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
|
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|
6780 ins_cost(140); |
|
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|
6781 |
|
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|
6782 size(4); |
|
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|
6783 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} |
|
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|
6784 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); |
|
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|
6785 ins_pipe(ialu_imm); |
|
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|
6786 %} |
|
f24201449cac
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diff
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|
6787 |
| 0 | 6788 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{ |
| 6789 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
| 6790 ins_cost(150); | |
| 6791 size(4); | |
| 6792 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 6793 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
| 6794 ins_pipe(ialu_imm); | |
| 6795 %} | |
| 6796 | |
| 6797 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{ | |
| 6798 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
| 6799 ins_cost(140); | |
| 6800 size(4); | |
| 6801 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
| 6802 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
| 6803 ins_pipe(ialu_imm); | |
| 6804 %} | |
| 6805 | |
| 6806 // Conditional move | |
| 6807 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{ | |
| 6808 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src))); | |
| 6809 ins_cost(150); | |
| 6810 opcode(0x101); | |
| 6811 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
| 6812 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6813 ins_pipe(int_conditional_float_move); | |
| 6814 %} | |
| 6815 | |
| 6816 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{ | |
| 6817 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); | |
| 6818 ins_cost(150); | |
| 6819 | |
| 6820 size(4); | |
| 6821 format %{ "FMOVS$cmp $icc,$src,$dst" %} | |
| 6822 opcode(0x101); | |
| 6823 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6824 ins_pipe(int_conditional_float_move); | |
| 6825 %} | |
| 6826 | |
|
1160
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changeset
|
6827 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{ |
|
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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|
6828 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); |
|
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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diff
changeset
|
6829 ins_cost(150); |
|
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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diff
changeset
|
6830 |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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diff
changeset
|
6831 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6832 format %{ "FMOVS$cmp $icc,$src,$dst" %} |
|
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|
6833 opcode(0x101); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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|
6834 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); |
|
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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|
6835 ins_pipe(int_conditional_float_move); |
|
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changeset
|
6836 %} |
|
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6837 |
| 0 | 6838 // Conditional move, |
| 6839 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{ | |
| 6840 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src))); | |
| 6841 ins_cost(150); | |
| 6842 size(4); | |
| 6843 format %{ "FMOVF$cmp $fcc,$src,$dst" %} | |
| 6844 opcode(0x1); | |
| 6845 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
| 6846 ins_pipe(int_conditional_double_move); | |
| 6847 %} | |
| 6848 | |
| 6849 // Conditional move | |
| 6850 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{ | |
| 6851 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src))); | |
| 6852 ins_cost(150); | |
| 6853 size(4); | |
| 6854 opcode(0x102); | |
| 6855 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
| 6856 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6857 ins_pipe(int_conditional_double_move); | |
| 6858 %} | |
| 6859 | |
| 6860 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{ | |
| 6861 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); | |
| 6862 ins_cost(150); | |
| 6863 | |
| 6864 size(4); | |
| 6865 format %{ "FMOVD$cmp $icc,$src,$dst" %} | |
| 6866 opcode(0x102); | |
| 6867 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6868 ins_pipe(int_conditional_double_move); | |
| 6869 %} | |
| 6870 | |
|
1160
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|
6871 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{ |
|
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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|
6872 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); |
|
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|
6873 ins_cost(150); |
|
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changeset
|
6874 |
|
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6875 size(4); |
|
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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|
6876 format %{ "FMOVD$cmp $icc,$src,$dst" %} |
|
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changeset
|
6877 opcode(0x102); |
|
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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|
6878 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); |
|
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changeset
|
6879 ins_pipe(int_conditional_double_move); |
|
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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|
6880 %} |
|
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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|
6881 |
| 0 | 6882 // Conditional move, |
| 6883 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{ | |
| 6884 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src))); | |
| 6885 ins_cost(150); | |
| 6886 size(4); | |
| 6887 format %{ "FMOVD$cmp $fcc,$src,$dst" %} | |
| 6888 opcode(0x2); | |
| 6889 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
| 6890 ins_pipe(int_conditional_double_move); | |
| 6891 %} | |
| 6892 | |
| 6893 // Conditional move | |
| 6894 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{ | |
| 6895 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
| 6896 ins_cost(150); | |
| 6897 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
| 6898 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6899 ins_pipe(ialu_reg); | |
| 6900 %} | |
| 6901 | |
| 6902 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{ | |
| 6903 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
| 6904 ins_cost(140); | |
| 6905 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
| 6906 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
| 6907 ins_pipe(ialu_imm); | |
| 6908 %} | |
| 6909 | |
| 6910 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{ | |
| 6911 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); | |
| 6912 ins_cost(150); | |
| 6913 | |
| 6914 size(4); | |
| 6915 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} | |
| 6916 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
| 6917 ins_pipe(ialu_reg); | |
| 6918 %} | |
| 6919 | |
| 6920 | |
|
1160
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|
6921 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{ |
|
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|
6922 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); |
|
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|
6923 ins_cost(150); |
|
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changeset
|
6924 |
|
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changeset
|
6925 size(4); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6926 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6927 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
|
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changeset
|
6928 ins_pipe(ialu_reg); |
|
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6929 %} |
|
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6930 |
|
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6931 |
| 0 | 6932 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{ |
| 6933 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src))); | |
| 6934 ins_cost(150); | |
| 6935 | |
| 6936 size(4); | |
| 6937 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %} | |
| 6938 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
| 6939 ins_pipe(ialu_reg); | |
| 6940 %} | |
| 6941 | |
| 6942 | |
| 6943 | |
| 6944 //----------OS and Locking Instructions---------------------------------------- | |
| 6945 | |
| 6946 // This name is KNOWN by the ADLC and cannot be changed. | |
| 6947 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type | |
| 6948 // for this guy. | |
| 6949 instruct tlsLoadP(g2RegP dst) %{ | |
| 6950 match(Set dst (ThreadLocal)); | |
| 6951 | |
| 6952 size(0); | |
| 6953 ins_cost(0); | |
| 6954 format %{ "# TLS is in G2" %} | |
| 6955 ins_encode( /*empty encoding*/ ); | |
| 6956 ins_pipe(ialu_none); | |
| 6957 %} | |
| 6958 | |
| 6959 instruct checkCastPP( iRegP dst ) %{ | |
| 6960 match(Set dst (CheckCastPP dst)); | |
| 6961 | |
| 6962 size(0); | |
| 6963 format %{ "# checkcastPP of $dst" %} | |
| 6964 ins_encode( /*empty encoding*/ ); | |
| 6965 ins_pipe(empty); | |
| 6966 %} | |
| 6967 | |
| 6968 | |
| 6969 instruct castPP( iRegP dst ) %{ | |
| 6970 match(Set dst (CastPP dst)); | |
| 6971 format %{ "# castPP of $dst" %} | |
| 6972 ins_encode( /*empty encoding*/ ); | |
| 6973 ins_pipe(empty); | |
| 6974 %} | |
| 6975 | |
| 6976 instruct castII( iRegI dst ) %{ | |
| 6977 match(Set dst (CastII dst)); | |
| 6978 format %{ "# castII of $dst" %} | |
| 6979 ins_encode( /*empty encoding*/ ); | |
| 6980 ins_cost(0); | |
| 6981 ins_pipe(empty); | |
| 6982 %} | |
| 6983 | |
| 6984 //----------Arithmetic Instructions-------------------------------------------- | |
| 6985 // Addition Instructions | |
| 6986 // Register Addition | |
| 6987 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 6988 match(Set dst (AddI src1 src2)); | |
| 6989 | |
| 6990 size(4); | |
| 6991 format %{ "ADD $src1,$src2,$dst" %} | |
| 6992 ins_encode %{ | |
| 6993 __ add($src1$$Register, $src2$$Register, $dst$$Register); | |
| 6994 %} | |
| 6995 ins_pipe(ialu_reg_reg); | |
| 6996 %} | |
| 6997 | |
| 6998 // Immediate Addition | |
| 6999 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7000 match(Set dst (AddI src1 src2)); | |
| 7001 | |
| 7002 size(4); | |
| 7003 format %{ "ADD $src1,$src2,$dst" %} | |
| 7004 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7005 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7006 ins_pipe(ialu_reg_imm); | |
| 7007 %} | |
| 7008 | |
| 7009 // Pointer Register Addition | |
| 7010 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{ | |
| 7011 match(Set dst (AddP src1 src2)); | |
| 7012 | |
| 7013 size(4); | |
| 7014 format %{ "ADD $src1,$src2,$dst" %} | |
| 7015 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7016 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7017 ins_pipe(ialu_reg_reg); | |
| 7018 %} | |
| 7019 | |
| 7020 // Pointer Immediate Addition | |
| 7021 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{ | |
| 7022 match(Set dst (AddP src1 src2)); | |
| 7023 | |
| 7024 size(4); | |
| 7025 format %{ "ADD $src1,$src2,$dst" %} | |
| 7026 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7027 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7028 ins_pipe(ialu_reg_imm); | |
| 7029 %} | |
| 7030 | |
| 7031 // Long Addition | |
| 7032 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7033 match(Set dst (AddL src1 src2)); | |
| 7034 | |
| 7035 size(4); | |
| 7036 format %{ "ADD $src1,$src2,$dst\t! long" %} | |
| 7037 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7038 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7039 ins_pipe(ialu_reg_reg); | |
| 7040 %} | |
| 7041 | |
| 7042 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 7043 match(Set dst (AddL src1 con)); | |
| 7044 | |
| 7045 size(4); | |
| 7046 format %{ "ADD $src1,$con,$dst" %} | |
| 7047 opcode(Assembler::add_op3, Assembler::arith_op); | |
| 7048 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 7049 ins_pipe(ialu_reg_imm); | |
| 7050 %} | |
| 7051 | |
| 7052 //----------Conditional_store-------------------------------------------------- | |
| 7053 // Conditional-store of the updated heap-top. | |
| 7054 // Used during allocation of the shared heap. | |
| 7055 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. | |
| 7056 | |
| 7057 // LoadP-locked. Same as a regular pointer load when used with a compare-swap | |
| 7058 instruct loadPLocked(iRegP dst, memory mem) %{ | |
| 7059 match(Set dst (LoadPLocked mem)); | |
| 7060 ins_cost(MEMORY_REF_COST); | |
| 7061 | |
| 7062 #ifndef _LP64 | |
| 7063 size(4); | |
| 7064 format %{ "LDUW $mem,$dst\t! ptr" %} | |
| 7065 opcode(Assembler::lduw_op3, 0, REGP_OP); | |
| 7066 #else | |
| 7067 format %{ "LDX $mem,$dst\t! ptr" %} | |
| 7068 opcode(Assembler::ldx_op3, 0, REGP_OP); | |
| 7069 #endif | |
| 7070 ins_encode( form3_mem_reg( mem, dst ) ); | |
| 7071 ins_pipe(iload_mem); | |
| 7072 %} | |
| 7073 | |
| 7074 // LoadL-locked. Same as a regular long load when used with a compare-swap | |
| 7075 instruct loadLLocked(iRegL dst, memory mem) %{ | |
| 7076 match(Set dst (LoadLLocked mem)); | |
| 7077 ins_cost(MEMORY_REF_COST); | |
| 7078 size(4); | |
| 7079 format %{ "LDX $mem,$dst\t! long" %} | |
| 7080 opcode(Assembler::ldx_op3); | |
|
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|
7081 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
| 0 | 7082 ins_pipe(iload_mem); |
| 7083 %} | |
| 7084 | |
| 7085 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{ | |
| 7086 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval))); | |
| 7087 effect( KILL newval ); | |
| 7088 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t" | |
| 7089 "CMP R_G3,$oldval\t\t! See if we made progress" %} | |
| 7090 ins_encode( enc_cas(heap_top_ptr,oldval,newval) ); | |
| 7091 ins_pipe( long_memory_op ); | |
| 7092 %} | |
| 7093 | |
|
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|
7094 // Conditional-store of an int value. |
|
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|
7095 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{ |
|
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|
7096 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval))); |
|
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diff
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|
7097 effect( KILL newval ); |
|
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|
7098 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
|
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|
7099 "CMP $oldval,$newval\t\t! See if we made progress" %} |
|
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|
7100 ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
| 0 | 7101 ins_pipe( long_memory_op ); |
| 7102 %} | |
| 7103 | |
|
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|
7104 // Conditional-store of a long value. |
|
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|
7105 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{ |
|
a1980da045cc
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|
7106 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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diff
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|
7107 effect( KILL newval ); |
|
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changeset
|
7108 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
|
a1980da045cc
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|
7109 "CMP $oldval,$newval\t\t! See if we made progress" %} |
|
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changeset
|
7110 ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
| 0 | 7111 ins_pipe( long_memory_op ); |
| 7112 %} | |
| 7113 | |
| 7114 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them | |
| 7115 | |
| 7116 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
| 7117 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); | |
| 7118 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
| 7119 format %{ | |
| 7120 "MOV $newval,O7\n\t" | |
| 7121 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
| 7122 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
| 7123 "MOV 1,$res\n\t" | |
| 7124 "MOVne xcc,R_G0,$res" | |
| 7125 %} | |
| 7126 ins_encode( enc_casx(mem_ptr, oldval, newval), | |
| 7127 enc_lflags_ne_to_boolean(res) ); | |
| 7128 ins_pipe( long_memory_op ); | |
| 7129 %} | |
| 7130 | |
| 7131 | |
| 7132 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
| 7133 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); | |
| 7134 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
| 7135 format %{ | |
| 7136 "MOV $newval,O7\n\t" | |
| 7137 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
| 7138 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
| 7139 "MOV 1,$res\n\t" | |
| 7140 "MOVne icc,R_G0,$res" | |
| 7141 %} | |
| 7142 ins_encode( enc_casi(mem_ptr, oldval, newval), | |
| 7143 enc_iflags_ne_to_boolean(res) ); | |
| 7144 ins_pipe( long_memory_op ); | |
| 7145 %} | |
| 7146 | |
| 7147 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
| 7148 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); | |
| 7149 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
| 7150 format %{ | |
| 7151 "MOV $newval,O7\n\t" | |
|
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7152 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" |
| 0 | 7153 "CMP $oldval,O7\t\t! See if we made progress\n\t" |
| 7154 "MOV 1,$res\n\t" | |
| 7155 "MOVne xcc,R_G0,$res" | |
| 7156 %} | |
|
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7157 #ifdef _LP64 |
| 0 | 7158 ins_encode( enc_casx(mem_ptr, oldval, newval), |
| 7159 enc_lflags_ne_to_boolean(res) ); | |
| 7160 #else | |
|
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7161 ins_encode( enc_casi(mem_ptr, oldval, newval), |
|
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7162 enc_iflags_ne_to_boolean(res) ); |
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7163 #endif |
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7164 ins_pipe( long_memory_op ); |
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7165 %} |
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7166 |
|
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7167 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ |
|
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7168 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); |
|
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7169 effect( USE mem_ptr, KILL ccr, KILL tmp1); |
| 0 | 7170 format %{ |
| 7171 "MOV $newval,O7\n\t" | |
| 7172 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
| 7173 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
| 7174 "MOV 1,$res\n\t" | |
| 7175 "MOVne icc,R_G0,$res" | |
| 7176 %} | |
|
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7177 ins_encode( enc_casi(mem_ptr, oldval, newval), |
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|
7178 enc_iflags_ne_to_boolean(res) ); |
| 0 | 7179 ins_pipe( long_memory_op ); |
| 7180 %} | |
| 7181 | |
| 7182 //--------------------- | |
| 7183 // Subtraction Instructions | |
| 7184 // Register Subtraction | |
| 7185 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7186 match(Set dst (SubI src1 src2)); | |
| 7187 | |
| 7188 size(4); | |
| 7189 format %{ "SUB $src1,$src2,$dst" %} | |
| 7190 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7191 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7192 ins_pipe(ialu_reg_reg); | |
| 7193 %} | |
| 7194 | |
| 7195 // Immediate Subtraction | |
| 7196 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7197 match(Set dst (SubI src1 src2)); | |
| 7198 | |
| 7199 size(4); | |
| 7200 format %{ "SUB $src1,$src2,$dst" %} | |
| 7201 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7202 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7203 ins_pipe(ialu_reg_imm); | |
| 7204 %} | |
| 7205 | |
| 7206 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
| 7207 match(Set dst (SubI zero src2)); | |
| 7208 | |
| 7209 size(4); | |
| 7210 format %{ "NEG $src2,$dst" %} | |
| 7211 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7212 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
| 7213 ins_pipe(ialu_zero_reg); | |
| 7214 %} | |
| 7215 | |
| 7216 // Long subtraction | |
| 7217 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7218 match(Set dst (SubL src1 src2)); | |
| 7219 | |
| 7220 size(4); | |
| 7221 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
| 7222 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7223 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7224 ins_pipe(ialu_reg_reg); | |
| 7225 %} | |
| 7226 | |
| 7227 // Immediate Subtraction | |
| 7228 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 7229 match(Set dst (SubL src1 con)); | |
| 7230 | |
| 7231 size(4); | |
| 7232 format %{ "SUB $src1,$con,$dst\t! long" %} | |
| 7233 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7234 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 7235 ins_pipe(ialu_reg_imm); | |
| 7236 %} | |
| 7237 | |
| 7238 // Long negation | |
| 7239 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{ | |
| 7240 match(Set dst (SubL zero src2)); | |
| 7241 | |
| 7242 size(4); | |
| 7243 format %{ "NEG $src2,$dst\t! long" %} | |
| 7244 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7245 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
| 7246 ins_pipe(ialu_zero_reg); | |
| 7247 %} | |
| 7248 | |
| 7249 // Multiplication Instructions | |
| 7250 // Integer Multiplication | |
| 7251 // Register Multiplication | |
| 7252 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7253 match(Set dst (MulI src1 src2)); | |
| 7254 | |
| 7255 size(4); | |
| 7256 format %{ "MULX $src1,$src2,$dst" %} | |
| 7257 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7258 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7259 ins_pipe(imul_reg_reg); | |
| 7260 %} | |
| 7261 | |
| 7262 // Immediate Multiplication | |
| 7263 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7264 match(Set dst (MulI src1 src2)); | |
| 7265 | |
| 7266 size(4); | |
| 7267 format %{ "MULX $src1,$src2,$dst" %} | |
| 7268 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7269 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7270 ins_pipe(imul_reg_imm); | |
| 7271 %} | |
| 7272 | |
| 7273 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7274 match(Set dst (MulL src1 src2)); | |
| 7275 ins_cost(DEFAULT_COST * 5); | |
| 7276 size(4); | |
| 7277 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
| 7278 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7279 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7280 ins_pipe(mulL_reg_reg); | |
| 7281 %} | |
| 7282 | |
| 7283 // Immediate Multiplication | |
| 7284 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7285 match(Set dst (MulL src1 src2)); | |
| 7286 ins_cost(DEFAULT_COST * 5); | |
| 7287 size(4); | |
| 7288 format %{ "MULX $src1,$src2,$dst" %} | |
| 7289 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7290 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7291 ins_pipe(mulL_reg_imm); | |
| 7292 %} | |
| 7293 | |
| 7294 // Integer Division | |
| 7295 // Register Division | |
| 7296 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{ | |
| 7297 match(Set dst (DivI src1 src2)); | |
| 7298 ins_cost((2+71)*DEFAULT_COST); | |
| 7299 | |
| 7300 format %{ "SRA $src2,0,$src2\n\t" | |
| 7301 "SRA $src1,0,$src1\n\t" | |
| 7302 "SDIVX $src1,$src2,$dst" %} | |
| 7303 ins_encode( idiv_reg( src1, src2, dst ) ); | |
| 7304 ins_pipe(sdiv_reg_reg); | |
| 7305 %} | |
| 7306 | |
| 7307 // Immediate Division | |
| 7308 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{ | |
| 7309 match(Set dst (DivI src1 src2)); | |
| 7310 ins_cost((2+71)*DEFAULT_COST); | |
| 7311 | |
| 7312 format %{ "SRA $src1,0,$src1\n\t" | |
| 7313 "SDIVX $src1,$src2,$dst" %} | |
| 7314 ins_encode( idiv_imm( src1, src2, dst ) ); | |
| 7315 ins_pipe(sdiv_reg_imm); | |
| 7316 %} | |
| 7317 | |
| 7318 //----------Div-By-10-Expansion------------------------------------------------ | |
| 7319 // Extract hi bits of a 32x32->64 bit multiply. | |
| 7320 // Expand rule only, not matched | |
| 7321 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{ | |
| 7322 effect( DEF dst, USE src1, USE src2 ); | |
| 7323 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t" | |
| 7324 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %} | |
| 7325 ins_encode( enc_mul_hi(dst,src1,src2)); | |
| 7326 ins_pipe(sdiv_reg_reg); | |
| 7327 %} | |
| 7328 | |
| 605 | 7329 // Magic constant, reciprocal of 10 |
| 0 | 7330 instruct loadConI_x66666667(iRegIsafe dst) %{ |
| 7331 effect( DEF dst ); | |
| 7332 | |
| 7333 size(8); | |
| 7334 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %} | |
| 7335 ins_encode( Set32(0x66666667, dst) ); | |
| 7336 ins_pipe(ialu_hi_lo_reg); | |
| 7337 %} | |
| 7338 | |
| 605 | 7339 // Register Shift Right Arithmetic Long by 32-63 |
| 0 | 7340 instruct sra_31( iRegI dst, iRegI src ) %{ |
| 7341 effect( DEF dst, USE src ); | |
| 7342 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %} | |
| 7343 ins_encode( form3_rs1_rd_copysign_hi(src,dst) ); | |
| 7344 ins_pipe(ialu_reg_reg); | |
| 7345 %} | |
| 7346 | |
| 7347 // Arithmetic Shift Right by 8-bit immediate | |
| 7348 instruct sra_reg_2( iRegI dst, iRegI src ) %{ | |
| 7349 effect( DEF dst, USE src ); | |
| 7350 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %} | |
| 7351 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 7352 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) ); | |
| 7353 ins_pipe(ialu_reg_imm); | |
| 7354 %} | |
| 7355 | |
| 7356 // Integer DIV with 10 | |
| 7357 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{ | |
| 7358 match(Set dst (DivI src div)); | |
| 7359 ins_cost((6+6)*DEFAULT_COST); | |
| 7360 expand %{ | |
| 7361 iRegIsafe tmp1; // Killed temps; | |
| 7362 iRegIsafe tmp2; // Killed temps; | |
| 7363 iRegI tmp3; // Killed temps; | |
| 7364 iRegI tmp4; // Killed temps; | |
| 7365 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1 | |
| 7366 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2 | |
| 7367 sra_31( tmp3, src ); // SRA src,31 -> tmp3 | |
| 7368 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4 | |
| 7369 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst | |
| 7370 %} | |
| 7371 %} | |
| 7372 | |
| 7373 // Register Long Division | |
| 7374 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7375 match(Set dst (DivL src1 src2)); | |
| 7376 ins_cost(DEFAULT_COST*71); | |
| 7377 size(4); | |
| 7378 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 7379 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 7380 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7381 ins_pipe(divL_reg_reg); | |
| 7382 %} | |
| 7383 | |
| 7384 // Register Long Division | |
| 7385 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7386 match(Set dst (DivL src1 src2)); | |
| 7387 ins_cost(DEFAULT_COST*71); | |
| 7388 size(4); | |
| 7389 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 7390 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 7391 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7392 ins_pipe(divL_reg_imm); | |
| 7393 %} | |
| 7394 | |
| 7395 // Integer Remainder | |
| 7396 // Register Remainder | |
| 7397 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{ | |
| 7398 match(Set dst (ModI src1 src2)); | |
| 7399 effect( KILL ccr, KILL temp); | |
| 7400 | |
| 7401 format %{ "SREM $src1,$src2,$dst" %} | |
| 7402 ins_encode( irem_reg(src1, src2, dst, temp) ); | |
| 7403 ins_pipe(sdiv_reg_reg); | |
| 7404 %} | |
| 7405 | |
| 7406 // Immediate Remainder | |
| 7407 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{ | |
| 7408 match(Set dst (ModI src1 src2)); | |
| 7409 effect( KILL ccr, KILL temp); | |
| 7410 | |
| 7411 format %{ "SREM $src1,$src2,$dst" %} | |
| 7412 ins_encode( irem_imm(src1, src2, dst, temp) ); | |
| 7413 ins_pipe(sdiv_reg_imm); | |
| 7414 %} | |
| 7415 | |
| 7416 // Register Long Remainder | |
| 7417 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7418 effect(DEF dst, USE src1, USE src2); | |
| 7419 size(4); | |
| 7420 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 7421 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 7422 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7423 ins_pipe(divL_reg_reg); | |
| 7424 %} | |
| 7425 | |
| 7426 // Register Long Division | |
| 7427 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7428 effect(DEF dst, USE src1, USE src2); | |
| 7429 size(4); | |
| 7430 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
| 7431 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
| 7432 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7433 ins_pipe(divL_reg_imm); | |
| 7434 %} | |
| 7435 | |
| 7436 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7437 effect(DEF dst, USE src1, USE src2); | |
| 7438 size(4); | |
| 7439 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
| 7440 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7441 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7442 ins_pipe(mulL_reg_reg); | |
| 7443 %} | |
| 7444 | |
| 7445 // Immediate Multiplication | |
| 7446 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7447 effect(DEF dst, USE src1, USE src2); | |
| 7448 size(4); | |
| 7449 format %{ "MULX $src1,$src2,$dst" %} | |
| 7450 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
| 7451 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7452 ins_pipe(mulL_reg_imm); | |
| 7453 %} | |
| 7454 | |
| 7455 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7456 effect(DEF dst, USE src1, USE src2); | |
| 7457 size(4); | |
| 7458 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
| 7459 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7460 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7461 ins_pipe(ialu_reg_reg); | |
| 7462 %} | |
| 7463 | |
| 7464 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7465 effect(DEF dst, USE src1, USE src2); | |
| 7466 size(4); | |
| 7467 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
| 7468 opcode(Assembler::sub_op3, Assembler::arith_op); | |
| 7469 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7470 ins_pipe(ialu_reg_reg); | |
| 7471 %} | |
| 7472 | |
| 7473 // Register Long Remainder | |
| 7474 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7475 match(Set dst (ModL src1 src2)); | |
| 7476 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
| 7477 expand %{ | |
| 7478 iRegL tmp1; | |
| 7479 iRegL tmp2; | |
| 7480 divL_reg_reg_1(tmp1, src1, src2); | |
| 7481 mulL_reg_reg_1(tmp2, tmp1, src2); | |
| 7482 subL_reg_reg_1(dst, src1, tmp2); | |
| 7483 %} | |
| 7484 %} | |
| 7485 | |
| 7486 // Register Long Remainder | |
| 7487 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
| 7488 match(Set dst (ModL src1 src2)); | |
| 7489 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
| 7490 expand %{ | |
| 7491 iRegL tmp1; | |
| 7492 iRegL tmp2; | |
| 7493 divL_reg_imm13_1(tmp1, src1, src2); | |
| 7494 mulL_reg_imm13_1(tmp2, tmp1, src2); | |
| 7495 subL_reg_reg_2 (dst, src1, tmp2); | |
| 7496 %} | |
| 7497 %} | |
| 7498 | |
| 7499 // Integer Shift Instructions | |
| 7500 // Register Shift Left | |
| 7501 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7502 match(Set dst (LShiftI src1 src2)); | |
| 7503 | |
| 7504 size(4); | |
| 7505 format %{ "SLL $src1,$src2,$dst" %} | |
| 7506 opcode(Assembler::sll_op3, Assembler::arith_op); | |
| 7507 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7508 ins_pipe(ialu_reg_reg); | |
| 7509 %} | |
| 7510 | |
| 7511 // Register Shift Left Immediate | |
| 7512 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
| 7513 match(Set dst (LShiftI src1 src2)); | |
| 7514 | |
| 7515 size(4); | |
| 7516 format %{ "SLL $src1,$src2,$dst" %} | |
| 7517 opcode(Assembler::sll_op3, Assembler::arith_op); | |
| 7518 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7519 ins_pipe(ialu_reg_imm); | |
| 7520 %} | |
| 7521 | |
| 7522 // Register Shift Left | |
| 7523 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
| 7524 match(Set dst (LShiftL src1 src2)); | |
| 7525 | |
| 7526 size(4); | |
| 7527 format %{ "SLLX $src1,$src2,$dst" %} | |
| 7528 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
| 7529 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7530 ins_pipe(ialu_reg_reg); | |
| 7531 %} | |
| 7532 | |
| 7533 // Register Shift Left Immediate | |
| 7534 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
| 7535 match(Set dst (LShiftL src1 src2)); | |
| 7536 | |
| 7537 size(4); | |
| 7538 format %{ "SLLX $src1,$src2,$dst" %} | |
| 7539 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
| 7540 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7541 ins_pipe(ialu_reg_imm); | |
| 7542 %} | |
| 7543 | |
| 7544 // Register Arithmetic Shift Right | |
| 7545 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7546 match(Set dst (RShiftI src1 src2)); | |
| 7547 size(4); | |
| 7548 format %{ "SRA $src1,$src2,$dst" %} | |
| 7549 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 7550 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7551 ins_pipe(ialu_reg_reg); | |
| 7552 %} | |
| 7553 | |
| 7554 // Register Arithmetic Shift Right Immediate | |
| 7555 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
| 7556 match(Set dst (RShiftI src1 src2)); | |
| 7557 | |
| 7558 size(4); | |
| 7559 format %{ "SRA $src1,$src2,$dst" %} | |
| 7560 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 7561 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7562 ins_pipe(ialu_reg_imm); | |
| 7563 %} | |
| 7564 | |
| 7565 // Register Shift Right Arithmatic Long | |
| 7566 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
| 7567 match(Set dst (RShiftL src1 src2)); | |
| 7568 | |
| 7569 size(4); | |
| 7570 format %{ "SRAX $src1,$src2,$dst" %} | |
| 7571 opcode(Assembler::srax_op3, Assembler::arith_op); | |
| 7572 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7573 ins_pipe(ialu_reg_reg); | |
| 7574 %} | |
| 7575 | |
| 7576 // Register Shift Left Immediate | |
| 7577 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
| 7578 match(Set dst (RShiftL src1 src2)); | |
| 7579 | |
| 7580 size(4); | |
| 7581 format %{ "SRAX $src1,$src2,$dst" %} | |
| 7582 opcode(Assembler::srax_op3, Assembler::arith_op); | |
| 7583 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7584 ins_pipe(ialu_reg_imm); | |
| 7585 %} | |
| 7586 | |
| 7587 // Register Shift Right | |
| 7588 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7589 match(Set dst (URShiftI src1 src2)); | |
| 7590 | |
| 7591 size(4); | |
| 7592 format %{ "SRL $src1,$src2,$dst" %} | |
| 7593 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 7594 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7595 ins_pipe(ialu_reg_reg); | |
| 7596 %} | |
| 7597 | |
| 7598 // Register Shift Right Immediate | |
| 7599 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
| 7600 match(Set dst (URShiftI src1 src2)); | |
| 7601 | |
| 7602 size(4); | |
| 7603 format %{ "SRL $src1,$src2,$dst" %} | |
| 7604 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 7605 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7606 ins_pipe(ialu_reg_imm); | |
| 7607 %} | |
| 7608 | |
| 7609 // Register Shift Right | |
| 7610 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
| 7611 match(Set dst (URShiftL src1 src2)); | |
| 7612 | |
| 7613 size(4); | |
| 7614 format %{ "SRLX $src1,$src2,$dst" %} | |
| 7615 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
| 7616 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7617 ins_pipe(ialu_reg_reg); | |
| 7618 %} | |
| 7619 | |
| 7620 // Register Shift Right Immediate | |
| 7621 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
| 7622 match(Set dst (URShiftL src1 src2)); | |
| 7623 | |
| 7624 size(4); | |
| 7625 format %{ "SRLX $src1,$src2,$dst" %} | |
| 7626 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
| 7627 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7628 ins_pipe(ialu_reg_imm); | |
| 7629 %} | |
| 7630 | |
| 7631 // Register Shift Right Immediate with a CastP2X | |
| 7632 #ifdef _LP64 | |
| 7633 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{ | |
| 7634 match(Set dst (URShiftL (CastP2X src1) src2)); | |
| 7635 size(4); | |
| 7636 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %} | |
| 7637 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
| 7638 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
| 7639 ins_pipe(ialu_reg_imm); | |
| 7640 %} | |
| 7641 #else | |
| 7642 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{ | |
| 7643 match(Set dst (URShiftI (CastP2X src1) src2)); | |
| 7644 size(4); | |
| 7645 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %} | |
| 7646 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 7647 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
| 7648 ins_pipe(ialu_reg_imm); | |
| 7649 %} | |
| 7650 #endif | |
| 7651 | |
| 7652 | |
| 7653 //----------Floating Point Arithmetic Instructions----------------------------- | |
| 7654 | |
| 7655 // Add float single precision | |
| 7656 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7657 match(Set dst (AddF src1 src2)); | |
| 7658 | |
| 7659 size(4); | |
| 7660 format %{ "FADDS $src1,$src2,$dst" %} | |
| 7661 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf); | |
| 7662 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7663 ins_pipe(faddF_reg_reg); | |
| 7664 %} | |
| 7665 | |
| 7666 // Add float double precision | |
| 7667 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7668 match(Set dst (AddD src1 src2)); | |
| 7669 | |
| 7670 size(4); | |
| 7671 format %{ "FADDD $src1,$src2,$dst" %} | |
| 7672 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
| 7673 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7674 ins_pipe(faddD_reg_reg); | |
| 7675 %} | |
| 7676 | |
| 7677 // Sub float single precision | |
| 7678 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7679 match(Set dst (SubF src1 src2)); | |
| 7680 | |
| 7681 size(4); | |
| 7682 format %{ "FSUBS $src1,$src2,$dst" %} | |
| 7683 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf); | |
| 7684 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7685 ins_pipe(faddF_reg_reg); | |
| 7686 %} | |
| 7687 | |
| 7688 // Sub float double precision | |
| 7689 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7690 match(Set dst (SubD src1 src2)); | |
| 7691 | |
| 7692 size(4); | |
| 7693 format %{ "FSUBD $src1,$src2,$dst" %} | |
| 7694 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
| 7695 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7696 ins_pipe(faddD_reg_reg); | |
| 7697 %} | |
| 7698 | |
| 7699 // Mul float single precision | |
| 7700 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7701 match(Set dst (MulF src1 src2)); | |
| 7702 | |
| 7703 size(4); | |
| 7704 format %{ "FMULS $src1,$src2,$dst" %} | |
| 7705 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf); | |
| 7706 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7707 ins_pipe(fmulF_reg_reg); | |
| 7708 %} | |
| 7709 | |
| 7710 // Mul float double precision | |
| 7711 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7712 match(Set dst (MulD src1 src2)); | |
| 7713 | |
| 7714 size(4); | |
| 7715 format %{ "FMULD $src1,$src2,$dst" %} | |
| 7716 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
| 7717 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7718 ins_pipe(fmulD_reg_reg); | |
| 7719 %} | |
| 7720 | |
| 7721 // Div float single precision | |
| 7722 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ | |
| 7723 match(Set dst (DivF src1 src2)); | |
| 7724 | |
| 7725 size(4); | |
| 7726 format %{ "FDIVS $src1,$src2,$dst" %} | |
| 7727 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf); | |
| 7728 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
| 7729 ins_pipe(fdivF_reg_reg); | |
| 7730 %} | |
| 7731 | |
| 7732 // Div float double precision | |
| 7733 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ | |
| 7734 match(Set dst (DivD src1 src2)); | |
| 7735 | |
| 7736 size(4); | |
| 7737 format %{ "FDIVD $src1,$src2,$dst" %} | |
| 7738 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf); | |
| 7739 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 7740 ins_pipe(fdivD_reg_reg); | |
| 7741 %} | |
| 7742 | |
| 7743 // Absolute float double precision | |
| 7744 instruct absD_reg(regD dst, regD src) %{ | |
| 7745 match(Set dst (AbsD src)); | |
| 7746 | |
| 7747 format %{ "FABSd $src,$dst" %} | |
| 7748 ins_encode(fabsd(dst, src)); | |
| 7749 ins_pipe(faddD_reg); | |
| 7750 %} | |
| 7751 | |
| 7752 // Absolute float single precision | |
| 7753 instruct absF_reg(regF dst, regF src) %{ | |
| 7754 match(Set dst (AbsF src)); | |
| 7755 | |
| 7756 format %{ "FABSs $src,$dst" %} | |
| 7757 ins_encode(fabss(dst, src)); | |
| 7758 ins_pipe(faddF_reg); | |
| 7759 %} | |
| 7760 | |
| 7761 instruct negF_reg(regF dst, regF src) %{ | |
| 7762 match(Set dst (NegF src)); | |
| 7763 | |
| 7764 size(4); | |
| 7765 format %{ "FNEGs $src,$dst" %} | |
| 7766 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf); | |
| 7767 ins_encode(form3_opf_rs2F_rdF(src, dst)); | |
| 7768 ins_pipe(faddF_reg); | |
| 7769 %} | |
| 7770 | |
| 7771 instruct negD_reg(regD dst, regD src) %{ | |
| 7772 match(Set dst (NegD src)); | |
| 7773 | |
| 7774 format %{ "FNEGd $src,$dst" %} | |
| 7775 ins_encode(fnegd(dst, src)); | |
| 7776 ins_pipe(faddD_reg); | |
| 7777 %} | |
| 7778 | |
| 7779 // Sqrt float double precision | |
| 7780 instruct sqrtF_reg_reg(regF dst, regF src) %{ | |
| 7781 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); | |
| 7782 | |
| 7783 size(4); | |
| 7784 format %{ "FSQRTS $src,$dst" %} | |
| 7785 ins_encode(fsqrts(dst, src)); | |
| 7786 ins_pipe(fdivF_reg_reg); | |
| 7787 %} | |
| 7788 | |
| 7789 // Sqrt float double precision | |
| 7790 instruct sqrtD_reg_reg(regD dst, regD src) %{ | |
| 7791 match(Set dst (SqrtD src)); | |
| 7792 | |
| 7793 size(4); | |
| 7794 format %{ "FSQRTD $src,$dst" %} | |
| 7795 ins_encode(fsqrtd(dst, src)); | |
| 7796 ins_pipe(fdivD_reg_reg); | |
| 7797 %} | |
| 7798 | |
| 7799 //----------Logical Instructions----------------------------------------------- | |
| 7800 // And Instructions | |
| 7801 // Register And | |
| 7802 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7803 match(Set dst (AndI src1 src2)); | |
| 7804 | |
| 7805 size(4); | |
| 7806 format %{ "AND $src1,$src2,$dst" %} | |
| 7807 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 7808 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7809 ins_pipe(ialu_reg_reg); | |
| 7810 %} | |
| 7811 | |
| 7812 // Immediate And | |
| 7813 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7814 match(Set dst (AndI src1 src2)); | |
| 7815 | |
| 7816 size(4); | |
| 7817 format %{ "AND $src1,$src2,$dst" %} | |
| 7818 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 7819 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7820 ins_pipe(ialu_reg_imm); | |
| 7821 %} | |
| 7822 | |
| 7823 // Register And Long | |
| 7824 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7825 match(Set dst (AndL src1 src2)); | |
| 7826 | |
| 7827 ins_cost(DEFAULT_COST); | |
| 7828 size(4); | |
| 7829 format %{ "AND $src1,$src2,$dst\t! long" %} | |
| 7830 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 7831 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7832 ins_pipe(ialu_reg_reg); | |
| 7833 %} | |
| 7834 | |
| 7835 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 7836 match(Set dst (AndL src1 con)); | |
| 7837 | |
| 7838 ins_cost(DEFAULT_COST); | |
| 7839 size(4); | |
| 7840 format %{ "AND $src1,$con,$dst\t! long" %} | |
| 7841 opcode(Assembler::and_op3, Assembler::arith_op); | |
| 7842 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 7843 ins_pipe(ialu_reg_imm); | |
| 7844 %} | |
| 7845 | |
| 7846 // Or Instructions | |
| 7847 // Register Or | |
| 7848 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7849 match(Set dst (OrI src1 src2)); | |
| 7850 | |
| 7851 size(4); | |
| 7852 format %{ "OR $src1,$src2,$dst" %} | |
| 7853 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 7854 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7855 ins_pipe(ialu_reg_reg); | |
| 7856 %} | |
| 7857 | |
| 7858 // Immediate Or | |
| 7859 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7860 match(Set dst (OrI src1 src2)); | |
| 7861 | |
| 7862 size(4); | |
| 7863 format %{ "OR $src1,$src2,$dst" %} | |
| 7864 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 7865 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7866 ins_pipe(ialu_reg_imm); | |
| 7867 %} | |
| 7868 | |
| 7869 // Register Or Long | |
| 7870 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7871 match(Set dst (OrL src1 src2)); | |
| 7872 | |
| 7873 ins_cost(DEFAULT_COST); | |
| 7874 size(4); | |
| 7875 format %{ "OR $src1,$src2,$dst\t! long" %} | |
| 7876 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 7877 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7878 ins_pipe(ialu_reg_reg); | |
| 7879 %} | |
| 7880 | |
| 7881 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 7882 match(Set dst (OrL src1 con)); | |
| 7883 ins_cost(DEFAULT_COST*2); | |
| 7884 | |
| 7885 ins_cost(DEFAULT_COST); | |
| 7886 size(4); | |
| 7887 format %{ "OR $src1,$con,$dst\t! long" %} | |
| 7888 opcode(Assembler::or_op3, Assembler::arith_op); | |
| 7889 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 7890 ins_pipe(ialu_reg_imm); | |
| 7891 %} | |
| 7892 | |
|
420
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7893 #ifndef _LP64 |
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7894 |
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7895 // Use sp_ptr_RegP to match G2 (TLS register) without spilling. |
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7896 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{ |
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7897 match(Set dst (OrI src1 (CastP2X src2))); |
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7898 |
|
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7899 size(4); |
|
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7900 format %{ "OR $src1,$src2,$dst" %} |
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7901 opcode(Assembler::or_op3, Assembler::arith_op); |
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7902 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
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7903 ins_pipe(ialu_reg_reg); |
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7904 %} |
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7905 |
|
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7906 #else |
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7907 |
|
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7908 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{ |
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7909 match(Set dst (OrL src1 (CastP2X src2))); |
|
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7910 |
|
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7911 ins_cost(DEFAULT_COST); |
|
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7912 size(4); |
|
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7913 format %{ "OR $src1,$src2,$dst\t! long" %} |
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7914 opcode(Assembler::or_op3, Assembler::arith_op); |
|
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7915 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
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7916 ins_pipe(ialu_reg_reg); |
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7917 %} |
|
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7918 |
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7919 #endif |
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7920 |
| 0 | 7921 // Xor Instructions |
| 7922 // Register Xor | |
| 7923 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
| 7924 match(Set dst (XorI src1 src2)); | |
| 7925 | |
| 7926 size(4); | |
| 7927 format %{ "XOR $src1,$src2,$dst" %} | |
| 7928 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 7929 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7930 ins_pipe(ialu_reg_reg); | |
| 7931 %} | |
| 7932 | |
| 7933 // Immediate Xor | |
| 7934 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
| 7935 match(Set dst (XorI src1 src2)); | |
| 7936 | |
| 7937 size(4); | |
| 7938 format %{ "XOR $src1,$src2,$dst" %} | |
| 7939 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 7940 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
| 7941 ins_pipe(ialu_reg_imm); | |
| 7942 %} | |
| 7943 | |
| 7944 // Register Xor Long | |
| 7945 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
| 7946 match(Set dst (XorL src1 src2)); | |
| 7947 | |
| 7948 ins_cost(DEFAULT_COST); | |
| 7949 size(4); | |
| 7950 format %{ "XOR $src1,$src2,$dst\t! long" %} | |
| 7951 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 7952 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
| 7953 ins_pipe(ialu_reg_reg); | |
| 7954 %} | |
| 7955 | |
| 7956 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
| 7957 match(Set dst (XorL src1 con)); | |
| 7958 | |
| 7959 ins_cost(DEFAULT_COST); | |
| 7960 size(4); | |
| 7961 format %{ "XOR $src1,$con,$dst\t! long" %} | |
| 7962 opcode(Assembler::xor_op3, Assembler::arith_op); | |
| 7963 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
| 7964 ins_pipe(ialu_reg_imm); | |
| 7965 %} | |
| 7966 | |
| 7967 //----------Convert to Boolean------------------------------------------------- | |
| 7968 // Nice hack for 32-bit tests but doesn't work for | |
| 7969 // 64-bit pointers. | |
| 7970 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{ | |
| 7971 match(Set dst (Conv2B src)); | |
| 7972 effect( KILL ccr ); | |
| 7973 ins_cost(DEFAULT_COST*2); | |
| 7974 format %{ "CMP R_G0,$src\n\t" | |
| 7975 "ADDX R_G0,0,$dst" %} | |
| 7976 ins_encode( enc_to_bool( src, dst ) ); | |
| 7977 ins_pipe(ialu_reg_ialu); | |
| 7978 %} | |
| 7979 | |
| 7980 #ifndef _LP64 | |
| 7981 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{ | |
| 7982 match(Set dst (Conv2B src)); | |
| 7983 effect( KILL ccr ); | |
| 7984 ins_cost(DEFAULT_COST*2); | |
| 7985 format %{ "CMP R_G0,$src\n\t" | |
| 7986 "ADDX R_G0,0,$dst" %} | |
| 7987 ins_encode( enc_to_bool( src, dst ) ); | |
| 7988 ins_pipe(ialu_reg_ialu); | |
| 7989 %} | |
| 7990 #else | |
| 7991 instruct convP2B( iRegI dst, iRegP src ) %{ | |
| 7992 match(Set dst (Conv2B src)); | |
| 7993 ins_cost(DEFAULT_COST*2); | |
| 7994 format %{ "MOV $src,$dst\n\t" | |
| 7995 "MOVRNZ $src,1,$dst" %} | |
| 7996 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) ); | |
| 7997 ins_pipe(ialu_clr_and_mover); | |
| 7998 %} | |
| 7999 #endif | |
| 8000 | |
| 8001 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{ | |
| 8002 match(Set dst (CmpLTMask p q)); | |
| 8003 effect( KILL ccr ); | |
| 8004 ins_cost(DEFAULT_COST*4); | |
| 8005 format %{ "CMP $p,$q\n\t" | |
| 8006 "MOV #0,$dst\n\t" | |
| 8007 "BLT,a .+8\n\t" | |
| 8008 "MOV #-1,$dst" %} | |
| 8009 ins_encode( enc_ltmask(p,q,dst) ); | |
| 8010 ins_pipe(ialu_reg_reg_ialu); | |
| 8011 %} | |
| 8012 | |
| 8013 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ | |
| 8014 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
| 8015 effect(KILL ccr, TEMP tmp); | |
| 8016 ins_cost(DEFAULT_COST*3); | |
| 8017 | |
| 8018 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" | |
| 8019 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" | |
| 8020 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %} | |
| 8021 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); | |
| 8022 ins_pipe( cadd_cmpltmask ); | |
| 8023 %} | |
| 8024 | |
| 8025 instruct cadd_cmpLTMask2( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ | |
| 8026 match(Set p (AddI (SubI p q) (AndI (CmpLTMask p q) y))); | |
| 8027 effect( KILL ccr, TEMP tmp); | |
| 8028 ins_cost(DEFAULT_COST*3); | |
| 8029 | |
| 8030 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" | |
| 8031 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" | |
| 8032 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %} | |
| 8033 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); | |
| 8034 ins_pipe( cadd_cmpltmask ); | |
| 8035 %} | |
| 8036 | |
| 8037 //----------Arithmetic Conversion Instructions--------------------------------- | |
| 8038 // The conversions operations are all Alpha sorted. Please keep it that way! | |
| 8039 | |
| 8040 instruct convD2F_reg(regF dst, regD src) %{ | |
| 8041 match(Set dst (ConvD2F src)); | |
| 8042 size(4); | |
| 8043 format %{ "FDTOS $src,$dst" %} | |
| 8044 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf); | |
| 8045 ins_encode(form3_opf_rs2D_rdF(src, dst)); | |
| 8046 ins_pipe(fcvtD2F); | |
| 8047 %} | |
| 8048 | |
| 8049 | |
| 8050 // Convert a double to an int in a float register. | |
| 8051 // If the double is a NAN, stuff a zero in instead. | |
| 8052 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{ | |
| 8053 effect(DEF dst, USE src, KILL fcc0); | |
| 8054 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
| 8055 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 8056 "FDTOI $src,$dst\t! convert in delay slot\n\t" | |
| 8057 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
| 8058 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
| 8059 "skip:" %} | |
| 8060 ins_encode(form_d2i_helper(src,dst)); | |
| 8061 ins_pipe(fcvtD2I); | |
| 8062 %} | |
| 8063 | |
| 8064 instruct convD2I_reg(stackSlotI dst, regD src) %{ | |
| 8065 match(Set dst (ConvD2I src)); | |
| 8066 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 8067 expand %{ | |
| 8068 regF tmp; | |
| 8069 convD2I_helper(tmp, src); | |
| 8070 regF_to_stkI(dst, tmp); | |
| 8071 %} | |
| 8072 %} | |
| 8073 | |
| 8074 // Convert a double to a long in a double register. | |
| 8075 // If the double is a NAN, stuff a zero in instead. | |
| 8076 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{ | |
| 8077 effect(DEF dst, USE src, KILL fcc0); | |
| 8078 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
| 8079 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 8080 "FDTOX $src,$dst\t! convert in delay slot\n\t" | |
| 8081 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
| 8082 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
| 8083 "skip:" %} | |
| 8084 ins_encode(form_d2l_helper(src,dst)); | |
| 8085 ins_pipe(fcvtD2L); | |
| 8086 %} | |
| 8087 | |
| 8088 | |
| 8089 // Double to Long conversion | |
| 8090 instruct convD2L_reg(stackSlotL dst, regD src) %{ | |
| 8091 match(Set dst (ConvD2L src)); | |
| 8092 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 8093 expand %{ | |
| 8094 regD tmp; | |
| 8095 convD2L_helper(tmp, src); | |
| 8096 regD_to_stkL(dst, tmp); | |
| 8097 %} | |
| 8098 %} | |
| 8099 | |
| 8100 | |
| 8101 instruct convF2D_reg(regD dst, regF src) %{ | |
| 8102 match(Set dst (ConvF2D src)); | |
| 8103 format %{ "FSTOD $src,$dst" %} | |
| 8104 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf); | |
| 8105 ins_encode(form3_opf_rs2F_rdD(src, dst)); | |
| 8106 ins_pipe(fcvtF2D); | |
| 8107 %} | |
| 8108 | |
| 8109 | |
| 8110 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{ | |
| 8111 effect(DEF dst, USE src, KILL fcc0); | |
| 8112 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
| 8113 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 8114 "FSTOI $src,$dst\t! convert in delay slot\n\t" | |
| 8115 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
| 8116 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
| 8117 "skip:" %} | |
| 8118 ins_encode(form_f2i_helper(src,dst)); | |
| 8119 ins_pipe(fcvtF2I); | |
| 8120 %} | |
| 8121 | |
| 8122 instruct convF2I_reg(stackSlotI dst, regF src) %{ | |
| 8123 match(Set dst (ConvF2I src)); | |
| 8124 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 8125 expand %{ | |
| 8126 regF tmp; | |
| 8127 convF2I_helper(tmp, src); | |
| 8128 regF_to_stkI(dst, tmp); | |
| 8129 %} | |
| 8130 %} | |
| 8131 | |
| 8132 | |
| 8133 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{ | |
| 8134 effect(DEF dst, USE src, KILL fcc0); | |
| 8135 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
| 8136 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
| 8137 "FSTOX $src,$dst\t! convert in delay slot\n\t" | |
| 8138 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
| 8139 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
| 8140 "skip:" %} | |
| 8141 ins_encode(form_f2l_helper(src,dst)); | |
| 8142 ins_pipe(fcvtF2L); | |
| 8143 %} | |
| 8144 | |
| 8145 // Float to Long conversion | |
| 8146 instruct convF2L_reg(stackSlotL dst, regF src) %{ | |
| 8147 match(Set dst (ConvF2L src)); | |
| 8148 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
| 8149 expand %{ | |
| 8150 regD tmp; | |
| 8151 convF2L_helper(tmp, src); | |
| 8152 regD_to_stkL(dst, tmp); | |
| 8153 %} | |
| 8154 %} | |
| 8155 | |
| 8156 | |
| 8157 instruct convI2D_helper(regD dst, regF tmp) %{ | |
| 8158 effect(USE tmp, DEF dst); | |
| 8159 format %{ "FITOD $tmp,$dst" %} | |
| 8160 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
| 8161 ins_encode(form3_opf_rs2F_rdD(tmp, dst)); | |
| 8162 ins_pipe(fcvtI2D); | |
| 8163 %} | |
| 8164 | |
| 8165 instruct convI2D_reg(stackSlotI src, regD dst) %{ | |
| 8166 match(Set dst (ConvI2D src)); | |
| 8167 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8168 expand %{ | |
| 8169 regF tmp; | |
| 8170 stkI_to_regF( tmp, src); | |
| 8171 convI2D_helper( dst, tmp); | |
| 8172 %} | |
| 8173 %} | |
| 8174 | |
| 8175 instruct convI2D_mem( regD_low dst, memory mem ) %{ | |
| 8176 match(Set dst (ConvI2D (LoadI mem))); | |
| 8177 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8178 size(8); | |
| 8179 format %{ "LDF $mem,$dst\n\t" | |
| 8180 "FITOD $dst,$dst" %} | |
| 8181 opcode(Assembler::ldf_op3, Assembler::fitod_opf); | |
|
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8182 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); |
| 0 | 8183 ins_pipe(floadF_mem); |
| 8184 %} | |
| 8185 | |
| 8186 | |
| 8187 instruct convI2F_helper(regF dst, regF tmp) %{ | |
| 8188 effect(DEF dst, USE tmp); | |
| 8189 format %{ "FITOS $tmp,$dst" %} | |
| 8190 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf); | |
| 8191 ins_encode(form3_opf_rs2F_rdF(tmp, dst)); | |
| 8192 ins_pipe(fcvtI2F); | |
| 8193 %} | |
| 8194 | |
| 8195 instruct convI2F_reg( regF dst, stackSlotI src ) %{ | |
| 8196 match(Set dst (ConvI2F src)); | |
| 8197 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8198 expand %{ | |
| 8199 regF tmp; | |
| 8200 stkI_to_regF(tmp,src); | |
| 8201 convI2F_helper(dst, tmp); | |
| 8202 %} | |
| 8203 %} | |
| 8204 | |
| 8205 instruct convI2F_mem( regF dst, memory mem ) %{ | |
| 8206 match(Set dst (ConvI2F (LoadI mem))); | |
| 8207 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8208 size(8); | |
| 8209 format %{ "LDF $mem,$dst\n\t" | |
| 8210 "FITOS $dst,$dst" %} | |
| 8211 opcode(Assembler::ldf_op3, Assembler::fitos_opf); | |
|
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8212 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); |
| 0 | 8213 ins_pipe(floadF_mem); |
| 8214 %} | |
| 8215 | |
| 8216 | |
| 8217 instruct convI2L_reg(iRegL dst, iRegI src) %{ | |
| 8218 match(Set dst (ConvI2L src)); | |
| 8219 size(4); | |
| 8220 format %{ "SRA $src,0,$dst\t! int->long" %} | |
| 8221 opcode(Assembler::sra_op3, Assembler::arith_op); | |
| 8222 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
| 8223 ins_pipe(ialu_reg_reg); | |
| 8224 %} | |
| 8225 | |
| 8226 // Zero-extend convert int to long | |
| 8227 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{ | |
| 8228 match(Set dst (AndL (ConvI2L src) mask) ); | |
| 8229 size(4); | |
| 8230 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %} | |
| 8231 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 8232 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
| 8233 ins_pipe(ialu_reg_reg); | |
| 8234 %} | |
| 8235 | |
| 8236 // Zero-extend long | |
| 8237 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{ | |
| 8238 match(Set dst (AndL src mask) ); | |
| 8239 size(4); | |
| 8240 format %{ "SRL $src,0,$dst\t! zero-extend long" %} | |
| 8241 opcode(Assembler::srl_op3, Assembler::arith_op); | |
| 8242 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
| 8243 ins_pipe(ialu_reg_reg); | |
| 8244 %} | |
| 8245 | |
| 8246 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ | |
| 8247 match(Set dst (MoveF2I src)); | |
| 8248 effect(DEF dst, USE src); | |
| 8249 ins_cost(MEMORY_REF_COST); | |
| 8250 | |
| 8251 size(4); | |
| 8252 format %{ "LDUW $src,$dst\t! MoveF2I" %} | |
| 8253 opcode(Assembler::lduw_op3); | |
|
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8254 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 8255 ins_pipe(iload_mem); |
| 8256 %} | |
| 8257 | |
| 8258 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ | |
| 8259 match(Set dst (MoveI2F src)); | |
| 8260 effect(DEF dst, USE src); | |
| 8261 ins_cost(MEMORY_REF_COST); | |
| 8262 | |
| 8263 size(4); | |
| 8264 format %{ "LDF $src,$dst\t! MoveI2F" %} | |
| 8265 opcode(Assembler::ldf_op3); | |
|
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8266 ins_encode(simple_form3_mem_reg(src, dst)); |
| 0 | 8267 ins_pipe(floadF_stk); |
| 8268 %} | |
| 8269 | |
| 8270 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ | |
| 8271 match(Set dst (MoveD2L src)); | |
| 8272 effect(DEF dst, USE src); | |
| 8273 ins_cost(MEMORY_REF_COST); | |
| 8274 | |
| 8275 size(4); | |
| 8276 format %{ "LDX $src,$dst\t! MoveD2L" %} | |
| 8277 opcode(Assembler::ldx_op3); | |
|
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8278 ins_encode(simple_form3_mem_reg( src, dst ) ); |
| 0 | 8279 ins_pipe(iload_mem); |
| 8280 %} | |
| 8281 | |
| 8282 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ | |
| 8283 match(Set dst (MoveL2D src)); | |
| 8284 effect(DEF dst, USE src); | |
| 8285 ins_cost(MEMORY_REF_COST); | |
| 8286 | |
| 8287 size(4); | |
| 8288 format %{ "LDDF $src,$dst\t! MoveL2D" %} | |
| 8289 opcode(Assembler::lddf_op3); | |
|
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8290 ins_encode(simple_form3_mem_reg(src, dst)); |
| 0 | 8291 ins_pipe(floadD_stk); |
| 8292 %} | |
| 8293 | |
| 8294 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ | |
| 8295 match(Set dst (MoveF2I src)); | |
| 8296 effect(DEF dst, USE src); | |
| 8297 ins_cost(MEMORY_REF_COST); | |
| 8298 | |
| 8299 size(4); | |
| 8300 format %{ "STF $src,$dst\t!MoveF2I" %} | |
| 8301 opcode(Assembler::stf_op3); | |
|
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|
8302 ins_encode(simple_form3_mem_reg(dst, src)); |
| 0 | 8303 ins_pipe(fstoreF_stk_reg); |
| 8304 %} | |
| 8305 | |
| 8306 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ | |
| 8307 match(Set dst (MoveI2F src)); | |
| 8308 effect(DEF dst, USE src); | |
| 8309 ins_cost(MEMORY_REF_COST); | |
| 8310 | |
| 8311 size(4); | |
| 8312 format %{ "STW $src,$dst\t!MoveI2F" %} | |
| 8313 opcode(Assembler::stw_op3); | |
|
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|
8314 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 8315 ins_pipe(istore_mem_reg); |
| 8316 %} | |
| 8317 | |
| 8318 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ | |
| 8319 match(Set dst (MoveD2L src)); | |
| 8320 effect(DEF dst, USE src); | |
| 8321 ins_cost(MEMORY_REF_COST); | |
| 8322 | |
| 8323 size(4); | |
| 8324 format %{ "STDF $src,$dst\t!MoveD2L" %} | |
| 8325 opcode(Assembler::stdf_op3); | |
|
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|
8326 ins_encode(simple_form3_mem_reg(dst, src)); |
| 0 | 8327 ins_pipe(fstoreD_stk_reg); |
| 8328 %} | |
| 8329 | |
| 8330 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ | |
| 8331 match(Set dst (MoveL2D src)); | |
| 8332 effect(DEF dst, USE src); | |
| 8333 ins_cost(MEMORY_REF_COST); | |
| 8334 | |
| 8335 size(4); | |
| 8336 format %{ "STX $src,$dst\t!MoveL2D" %} | |
| 8337 opcode(Assembler::stx_op3); | |
|
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|
8338 ins_encode(simple_form3_mem_reg( dst, src ) ); |
| 0 | 8339 ins_pipe(istore_mem_reg); |
| 8340 %} | |
| 8341 | |
| 8342 | |
| 8343 //----------- | |
| 8344 // Long to Double conversion using V8 opcodes. | |
| 8345 // Still useful because cheetah traps and becomes | |
| 8346 // amazingly slow for some common numbers. | |
| 8347 | |
| 8348 // Magic constant, 0x43300000 | |
| 8349 instruct loadConI_x43300000(iRegI dst) %{ | |
| 8350 effect(DEF dst); | |
| 8351 size(4); | |
| 8352 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %} | |
| 8353 ins_encode(SetHi22(0x43300000, dst)); | |
| 8354 ins_pipe(ialu_none); | |
| 8355 %} | |
| 8356 | |
| 8357 // Magic constant, 0x41f00000 | |
| 8358 instruct loadConI_x41f00000(iRegI dst) %{ | |
| 8359 effect(DEF dst); | |
| 8360 size(4); | |
| 8361 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %} | |
| 8362 ins_encode(SetHi22(0x41f00000, dst)); | |
| 8363 ins_pipe(ialu_none); | |
| 8364 %} | |
| 8365 | |
| 8366 // Construct a double from two float halves | |
| 8367 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{ | |
| 8368 effect(DEF dst, USE src1, USE src2); | |
| 8369 size(8); | |
| 8370 format %{ "FMOVS $src1.hi,$dst.hi\n\t" | |
| 8371 "FMOVS $src2.lo,$dst.lo" %} | |
| 8372 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf); | |
| 8373 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst)); | |
| 8374 ins_pipe(faddD_reg_reg); | |
| 8375 %} | |
| 8376 | |
| 8377 // Convert integer in high half of a double register (in the lower half of | |
| 8378 // the double register file) to double | |
| 8379 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{ | |
| 8380 effect(DEF dst, USE src); | |
| 8381 size(4); | |
| 8382 format %{ "FITOD $src,$dst" %} | |
| 8383 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
| 8384 ins_encode(form3_opf_rs2D_rdD(src, dst)); | |
| 8385 ins_pipe(fcvtLHi2D); | |
| 8386 %} | |
| 8387 | |
| 8388 // Add float double precision | |
| 8389 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{ | |
| 8390 effect(DEF dst, USE src1, USE src2); | |
| 8391 size(4); | |
| 8392 format %{ "FADDD $src1,$src2,$dst" %} | |
| 8393 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
| 8394 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 8395 ins_pipe(faddD_reg_reg); | |
| 8396 %} | |
| 8397 | |
| 8398 // Sub float double precision | |
| 8399 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{ | |
| 8400 effect(DEF dst, USE src1, USE src2); | |
| 8401 size(4); | |
| 8402 format %{ "FSUBD $src1,$src2,$dst" %} | |
| 8403 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
| 8404 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 8405 ins_pipe(faddD_reg_reg); | |
| 8406 %} | |
| 8407 | |
| 8408 // Mul float double precision | |
| 8409 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{ | |
| 8410 effect(DEF dst, USE src1, USE src2); | |
| 8411 size(4); | |
| 8412 format %{ "FMULD $src1,$src2,$dst" %} | |
| 8413 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
| 8414 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
| 8415 ins_pipe(fmulD_reg_reg); | |
| 8416 %} | |
| 8417 | |
| 8418 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{ | |
| 8419 match(Set dst (ConvL2D src)); | |
| 8420 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6); | |
| 8421 | |
| 8422 expand %{ | |
| 8423 regD_low tmpsrc; | |
| 8424 iRegI ix43300000; | |
| 8425 iRegI ix41f00000; | |
| 8426 stackSlotL lx43300000; | |
| 8427 stackSlotL lx41f00000; | |
| 8428 regD_low dx43300000; | |
| 8429 regD dx41f00000; | |
| 8430 regD tmp1; | |
| 8431 regD_low tmp2; | |
| 8432 regD tmp3; | |
| 8433 regD tmp4; | |
| 8434 | |
| 8435 stkL_to_regD(tmpsrc, src); | |
| 8436 | |
| 8437 loadConI_x43300000(ix43300000); | |
| 8438 loadConI_x41f00000(ix41f00000); | |
| 8439 regI_to_stkLHi(lx43300000, ix43300000); | |
| 8440 regI_to_stkLHi(lx41f00000, ix41f00000); | |
| 8441 stkL_to_regD(dx43300000, lx43300000); | |
| 8442 stkL_to_regD(dx41f00000, lx41f00000); | |
| 8443 | |
| 8444 convI2D_regDHi_regD(tmp1, tmpsrc); | |
| 8445 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc); | |
| 8446 subD_regD_regD(tmp3, tmp2, dx43300000); | |
| 8447 mulD_regD_regD(tmp4, tmp1, dx41f00000); | |
| 8448 addD_regD_regD(dst, tmp3, tmp4); | |
| 8449 %} | |
| 8450 %} | |
| 8451 | |
| 8452 // Long to Double conversion using fast fxtof | |
| 8453 instruct convL2D_helper(regD dst, regD tmp) %{ | |
| 8454 effect(DEF dst, USE tmp); | |
| 8455 size(4); | |
| 8456 format %{ "FXTOD $tmp,$dst" %} | |
| 8457 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf); | |
| 8458 ins_encode(form3_opf_rs2D_rdD(tmp, dst)); | |
| 8459 ins_pipe(fcvtL2D); | |
| 8460 %} | |
| 8461 | |
| 8462 instruct convL2D_reg_fast_fxtof(regD dst, stackSlotL src) %{ | |
| 8463 predicate(VM_Version::has_fast_fxtof()); | |
| 8464 match(Set dst (ConvL2D src)); | |
| 8465 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST); | |
| 8466 expand %{ | |
| 8467 regD tmp; | |
| 8468 stkL_to_regD(tmp, src); | |
| 8469 convL2D_helper(dst, tmp); | |
| 8470 %} | |
| 8471 %} | |
| 8472 | |
| 8473 //----------- | |
| 8474 // Long to Float conversion using V8 opcodes. | |
| 8475 // Still useful because cheetah traps and becomes | |
| 8476 // amazingly slow for some common numbers. | |
| 8477 | |
| 8478 // Long to Float conversion using fast fxtof | |
| 8479 instruct convL2F_helper(regF dst, regD tmp) %{ | |
| 8480 effect(DEF dst, USE tmp); | |
| 8481 size(4); | |
| 8482 format %{ "FXTOS $tmp,$dst" %} | |
| 8483 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf); | |
| 8484 ins_encode(form3_opf_rs2D_rdF(tmp, dst)); | |
| 8485 ins_pipe(fcvtL2F); | |
| 8486 %} | |
| 8487 | |
| 8488 instruct convL2F_reg_fast_fxtof(regF dst, stackSlotL src) %{ | |
| 8489 match(Set dst (ConvL2F src)); | |
| 8490 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
| 8491 expand %{ | |
| 8492 regD tmp; | |
| 8493 stkL_to_regD(tmp, src); | |
| 8494 convL2F_helper(dst, tmp); | |
| 8495 %} | |
| 8496 %} | |
| 8497 //----------- | |
| 8498 | |
| 8499 instruct convL2I_reg(iRegI dst, iRegL src) %{ | |
| 8500 match(Set dst (ConvL2I src)); | |
| 8501 #ifndef _LP64 | |
| 8502 format %{ "MOV $src.lo,$dst\t! long->int" %} | |
| 8503 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) ); | |
| 8504 ins_pipe(ialu_move_reg_I_to_L); | |
| 8505 #else | |
| 8506 size(4); | |
| 8507 format %{ "SRA $src,R_G0,$dst\t! long->int" %} | |
| 8508 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) ); | |
| 8509 ins_pipe(ialu_reg); | |
| 8510 #endif | |
| 8511 %} | |
| 8512 | |
| 8513 // Register Shift Right Immediate | |
| 8514 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{ | |
| 8515 match(Set dst (ConvL2I (RShiftL src cnt))); | |
| 8516 | |
| 8517 size(4); | |
| 8518 format %{ "SRAX $src,$cnt,$dst" %} | |
| 8519 opcode(Assembler::srax_op3, Assembler::arith_op); | |
| 8520 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) ); | |
| 8521 ins_pipe(ialu_reg_imm); | |
| 8522 %} | |
| 8523 | |
| 8524 // Replicate scalar to packed byte values in Double register | |
| 8525 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{ | |
| 8526 effect(DEF dst, USE src); | |
| 8527 format %{ "SLLX $src,56,$dst\n\t" | |
| 8528 "SRLX $dst, 8,O7\n\t" | |
| 8529 "OR $dst,O7,$dst\n\t" | |
| 8530 "SRLX $dst,16,O7\n\t" | |
| 8531 "OR $dst,O7,$dst\n\t" | |
| 8532 "SRLX $dst,32,O7\n\t" | |
| 8533 "OR $dst,O7,$dst\t! replicate8B" %} | |
| 8534 ins_encode( enc_repl8b(src, dst)); | |
| 8535 ins_pipe(ialu_reg); | |
| 8536 %} | |
| 8537 | |
| 8538 // Replicate scalar to packed byte values in Double register | |
| 8539 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{ | |
| 8540 match(Set dst (Replicate8B src)); | |
| 8541 expand %{ | |
| 8542 iRegL tmp; | |
| 8543 Repl8B_reg_helper(tmp, src); | |
| 8544 regL_to_stkD(dst, tmp); | |
| 8545 %} | |
| 8546 %} | |
| 8547 | |
| 8548 // Replicate scalar constant to packed byte values in Double register | |
| 8549 instruct Repl8B_immI(regD dst, immI13 src, o7RegP tmp) %{ | |
| 8550 match(Set dst (Replicate8B src)); | |
| 8551 #ifdef _LP64 | |
| 8552 size(36); | |
| 8553 #else | |
| 8554 size(8); | |
| 8555 #endif | |
| 8556 format %{ "SETHI hi(&Repl8($src)),$tmp\t!get Repl8B($src) from table\n\t" | |
| 8557 "LDDF [$tmp+lo(&Repl8($src))],$dst" %} | |
| 8558 ins_encode( LdReplImmI(src, dst, tmp, (8), (1)) ); | |
| 8559 ins_pipe(loadConFD); | |
| 8560 %} | |
| 8561 | |
| 8562 // Replicate scalar to packed char values into stack slot | |
| 8563 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{ | |
| 8564 effect(DEF dst, USE src); | |
| 8565 format %{ "SLLX $src,48,$dst\n\t" | |
| 8566 "SRLX $dst,16,O7\n\t" | |
| 8567 "OR $dst,O7,$dst\n\t" | |
| 8568 "SRLX $dst,32,O7\n\t" | |
| 8569 "OR $dst,O7,$dst\t! replicate4C" %} | |
| 8570 ins_encode( enc_repl4s(src, dst) ); | |
| 8571 ins_pipe(ialu_reg); | |
| 8572 %} | |
| 8573 | |
| 8574 // Replicate scalar to packed char values into stack slot | |
| 8575 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{ | |
| 8576 match(Set dst (Replicate4C src)); | |
| 8577 expand %{ | |
| 8578 iRegL tmp; | |
| 8579 Repl4C_reg_helper(tmp, src); | |
| 8580 regL_to_stkD(dst, tmp); | |
| 8581 %} | |
| 8582 %} | |
| 8583 | |
| 8584 // Replicate scalar constant to packed char values in Double register | |
| 8585 instruct Repl4C_immI(regD dst, immI src, o7RegP tmp) %{ | |
| 8586 match(Set dst (Replicate4C src)); | |
| 8587 #ifdef _LP64 | |
| 8588 size(36); | |
| 8589 #else | |
| 8590 size(8); | |
| 8591 #endif | |
| 8592 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4C($src) from table\n\t" | |
| 8593 "LDDF [$tmp+lo(&Repl4($src))],$dst" %} | |
| 8594 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) ); | |
| 8595 ins_pipe(loadConFD); | |
| 8596 %} | |
| 8597 | |
| 8598 // Replicate scalar to packed short values into stack slot | |
| 8599 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{ | |
| 8600 effect(DEF dst, USE src); | |
| 8601 format %{ "SLLX $src,48,$dst\n\t" | |
| 8602 "SRLX $dst,16,O7\n\t" | |
| 8603 "OR $dst,O7,$dst\n\t" | |
| 8604 "SRLX $dst,32,O7\n\t" | |
| 8605 "OR $dst,O7,$dst\t! replicate4S" %} | |
| 8606 ins_encode( enc_repl4s(src, dst) ); | |
| 8607 ins_pipe(ialu_reg); | |
| 8608 %} | |
| 8609 | |
| 8610 // Replicate scalar to packed short values into stack slot | |
| 8611 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{ | |
| 8612 match(Set dst (Replicate4S src)); | |
| 8613 expand %{ | |
| 8614 iRegL tmp; | |
| 8615 Repl4S_reg_helper(tmp, src); | |
| 8616 regL_to_stkD(dst, tmp); | |
| 8617 %} | |
| 8618 %} | |
| 8619 | |
| 8620 // Replicate scalar constant to packed short values in Double register | |
| 8621 instruct Repl4S_immI(regD dst, immI src, o7RegP tmp) %{ | |
| 8622 match(Set dst (Replicate4S src)); | |
| 8623 #ifdef _LP64 | |
| 8624 size(36); | |
| 8625 #else | |
| 8626 size(8); | |
| 8627 #endif | |
| 8628 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4S($src) from table\n\t" | |
| 8629 "LDDF [$tmp+lo(&Repl4($src))],$dst" %} | |
| 8630 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) ); | |
| 8631 ins_pipe(loadConFD); | |
| 8632 %} | |
| 8633 | |
| 8634 // Replicate scalar to packed int values in Double register | |
| 8635 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{ | |
| 8636 effect(DEF dst, USE src); | |
| 8637 format %{ "SLLX $src,32,$dst\n\t" | |
| 8638 "SRLX $dst,32,O7\n\t" | |
| 8639 "OR $dst,O7,$dst\t! replicate2I" %} | |
| 8640 ins_encode( enc_repl2i(src, dst)); | |
| 8641 ins_pipe(ialu_reg); | |
| 8642 %} | |
| 8643 | |
| 8644 // Replicate scalar to packed int values in Double register | |
| 8645 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{ | |
| 8646 match(Set dst (Replicate2I src)); | |
| 8647 expand %{ | |
| 8648 iRegL tmp; | |
| 8649 Repl2I_reg_helper(tmp, src); | |
| 8650 regL_to_stkD(dst, tmp); | |
| 8651 %} | |
| 8652 %} | |
| 8653 | |
| 8654 // Replicate scalar zero constant to packed int values in Double register | |
| 8655 instruct Repl2I_immI(regD dst, immI src, o7RegP tmp) %{ | |
| 8656 match(Set dst (Replicate2I src)); | |
| 8657 #ifdef _LP64 | |
| 8658 size(36); | |
| 8659 #else | |
| 8660 size(8); | |
| 8661 #endif | |
| 8662 format %{ "SETHI hi(&Repl2($src)),$tmp\t!get Repl2I($src) from table\n\t" | |
| 8663 "LDDF [$tmp+lo(&Repl2($src))],$dst" %} | |
| 8664 ins_encode( LdReplImmI(src, dst, tmp, (2), (4)) ); | |
| 8665 ins_pipe(loadConFD); | |
| 8666 %} | |
| 8667 | |
| 8668 //----------Control Flow Instructions------------------------------------------ | |
| 8669 // Compare Instructions | |
| 8670 // Compare Integers | |
| 8671 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{ | |
| 8672 match(Set icc (CmpI op1 op2)); | |
| 8673 effect( DEF icc, USE op1, USE op2 ); | |
| 8674 | |
| 8675 size(4); | |
| 8676 format %{ "CMP $op1,$op2" %} | |
| 8677 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8678 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8679 ins_pipe(ialu_cconly_reg_reg); | |
| 8680 %} | |
| 8681 | |
| 8682 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{ | |
| 8683 match(Set icc (CmpU op1 op2)); | |
| 8684 | |
| 8685 size(4); | |
| 8686 format %{ "CMP $op1,$op2\t! unsigned" %} | |
| 8687 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8688 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8689 ins_pipe(ialu_cconly_reg_reg); | |
| 8690 %} | |
| 8691 | |
| 8692 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{ | |
| 8693 match(Set icc (CmpI op1 op2)); | |
| 8694 effect( DEF icc, USE op1 ); | |
| 8695 | |
| 8696 size(4); | |
| 8697 format %{ "CMP $op1,$op2" %} | |
| 8698 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8699 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 8700 ins_pipe(ialu_cconly_reg_imm); | |
| 8701 %} | |
| 8702 | |
| 8703 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{ | |
| 8704 match(Set icc (CmpI (AndI op1 op2) zero)); | |
| 8705 | |
| 8706 size(4); | |
| 8707 format %{ "BTST $op2,$op1" %} | |
| 8708 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 8709 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8710 ins_pipe(ialu_cconly_reg_reg_zero); | |
| 8711 %} | |
| 8712 | |
| 8713 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{ | |
| 8714 match(Set icc (CmpI (AndI op1 op2) zero)); | |
| 8715 | |
| 8716 size(4); | |
| 8717 format %{ "BTST $op2,$op1" %} | |
| 8718 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 8719 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 8720 ins_pipe(ialu_cconly_reg_imm_zero); | |
| 8721 %} | |
| 8722 | |
| 8723 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{ | |
| 8724 match(Set xcc (CmpL op1 op2)); | |
| 8725 effect( DEF xcc, USE op1, USE op2 ); | |
| 8726 | |
| 8727 size(4); | |
| 8728 format %{ "CMP $op1,$op2\t\t! long" %} | |
| 8729 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8730 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8731 ins_pipe(ialu_cconly_reg_reg); | |
| 8732 %} | |
| 8733 | |
| 8734 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{ | |
| 8735 match(Set xcc (CmpL op1 con)); | |
| 8736 effect( DEF xcc, USE op1, USE con ); | |
| 8737 | |
| 8738 size(4); | |
| 8739 format %{ "CMP $op1,$con\t\t! long" %} | |
| 8740 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8741 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
| 8742 ins_pipe(ialu_cconly_reg_reg); | |
| 8743 %} | |
| 8744 | |
| 8745 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{ | |
| 8746 match(Set xcc (CmpL (AndL op1 op2) zero)); | |
| 8747 effect( DEF xcc, USE op1, USE op2 ); | |
| 8748 | |
| 8749 size(4); | |
| 8750 format %{ "BTST $op1,$op2\t\t! long" %} | |
| 8751 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 8752 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8753 ins_pipe(ialu_cconly_reg_reg); | |
| 8754 %} | |
| 8755 | |
| 8756 // useful for checking the alignment of a pointer: | |
| 8757 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{ | |
| 8758 match(Set xcc (CmpL (AndL op1 con) zero)); | |
| 8759 effect( DEF xcc, USE op1, USE con ); | |
| 8760 | |
| 8761 size(4); | |
| 8762 format %{ "BTST $op1,$con\t\t! long" %} | |
| 8763 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
| 8764 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
| 8765 ins_pipe(ialu_cconly_reg_reg); | |
| 8766 %} | |
| 8767 | |
| 8768 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{ | |
| 8769 match(Set icc (CmpU op1 op2)); | |
| 8770 | |
| 8771 size(4); | |
| 8772 format %{ "CMP $op1,$op2\t! unsigned" %} | |
| 8773 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8774 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 8775 ins_pipe(ialu_cconly_reg_imm); | |
| 8776 %} | |
| 8777 | |
| 8778 // Compare Pointers | |
| 8779 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{ | |
| 8780 match(Set pcc (CmpP op1 op2)); | |
| 8781 | |
| 8782 size(4); | |
| 8783 format %{ "CMP $op1,$op2\t! ptr" %} | |
| 8784 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8785 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
| 8786 ins_pipe(ialu_cconly_reg_reg); | |
| 8787 %} | |
| 8788 | |
| 8789 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{ | |
| 8790 match(Set pcc (CmpP op1 op2)); | |
| 8791 | |
| 8792 size(4); | |
| 8793 format %{ "CMP $op1,$op2\t! ptr" %} | |
| 8794 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
| 8795 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
| 8796 ins_pipe(ialu_cconly_reg_imm); | |
| 8797 %} | |
| 8798 | |
|
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8799 // Compare Narrow oops |
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8800 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{ |
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8801 match(Set icc (CmpN op1 op2)); |
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8802 |
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8803 size(4); |
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8804 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
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8805 opcode(Assembler::subcc_op3, Assembler::arith_op); |
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8806 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); |
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8807 ins_pipe(ialu_cconly_reg_reg); |
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8808 %} |
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8809 |
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8810 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{ |
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8811 match(Set icc (CmpN op1 op2)); |
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8812 |
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8813 size(4); |
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8814 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
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8815 opcode(Assembler::subcc_op3, Assembler::arith_op); |
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8816 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); |
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8817 ins_pipe(ialu_cconly_reg_imm); |
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8818 %} |
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8819 |
| 0 | 8820 //----------Max and Min-------------------------------------------------------- |
| 8821 // Min Instructions | |
| 8822 // Conditional move for min | |
| 8823 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
| 8824 effect( USE_DEF op2, USE op1, USE icc ); | |
| 8825 | |
| 8826 size(4); | |
| 8827 format %{ "MOVlt icc,$op1,$op2\t! min" %} | |
| 8828 opcode(Assembler::less); | |
| 8829 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
| 8830 ins_pipe(ialu_reg_flags); | |
| 8831 %} | |
| 8832 | |
| 8833 // Min Register with Register. | |
| 8834 instruct minI_eReg(iRegI op1, iRegI op2) %{ | |
| 8835 match(Set op2 (MinI op1 op2)); | |
| 8836 ins_cost(DEFAULT_COST*2); | |
| 8837 expand %{ | |
| 8838 flagsReg icc; | |
| 8839 compI_iReg(icc,op1,op2); | |
| 8840 cmovI_reg_lt(op2,op1,icc); | |
| 8841 %} | |
| 8842 %} | |
| 8843 | |
| 8844 // Max Instructions | |
| 8845 // Conditional move for max | |
| 8846 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
| 8847 effect( USE_DEF op2, USE op1, USE icc ); | |
| 8848 format %{ "MOVgt icc,$op1,$op2\t! max" %} | |
| 8849 opcode(Assembler::greater); | |
| 8850 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
| 8851 ins_pipe(ialu_reg_flags); | |
| 8852 %} | |
| 8853 | |
| 8854 // Max Register with Register | |
| 8855 instruct maxI_eReg(iRegI op1, iRegI op2) %{ | |
| 8856 match(Set op2 (MaxI op1 op2)); | |
| 8857 ins_cost(DEFAULT_COST*2); | |
| 8858 expand %{ | |
| 8859 flagsReg icc; | |
| 8860 compI_iReg(icc,op1,op2); | |
| 8861 cmovI_reg_gt(op2,op1,icc); | |
| 8862 %} | |
| 8863 %} | |
| 8864 | |
| 8865 | |
| 8866 //----------Float Compares---------------------------------------------------- | |
| 8867 // Compare floating, generate condition code | |
| 8868 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{ | |
| 8869 match(Set fcc (CmpF src1 src2)); | |
| 8870 | |
| 8871 size(4); | |
| 8872 format %{ "FCMPs $fcc,$src1,$src2" %} | |
| 8873 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf); | |
| 8874 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) ); | |
| 8875 ins_pipe(faddF_fcc_reg_reg_zero); | |
| 8876 %} | |
| 8877 | |
| 8878 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{ | |
| 8879 match(Set fcc (CmpD src1 src2)); | |
| 8880 | |
| 8881 size(4); | |
| 8882 format %{ "FCMPd $fcc,$src1,$src2" %} | |
| 8883 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf); | |
| 8884 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) ); | |
| 8885 ins_pipe(faddD_fcc_reg_reg_zero); | |
| 8886 %} | |
| 8887 | |
| 8888 | |
| 8889 // Compare floating, generate -1,0,1 | |
| 8890 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{ | |
| 8891 match(Set dst (CmpF3 src1 src2)); | |
| 8892 effect(KILL fcc0); | |
| 8893 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
| 8894 format %{ "fcmpl $dst,$src1,$src2" %} | |
| 8895 // Primary = float | |
| 8896 opcode( true ); | |
| 8897 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
| 8898 ins_pipe( floating_cmp ); | |
| 8899 %} | |
| 8900 | |
| 8901 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{ | |
| 8902 match(Set dst (CmpD3 src1 src2)); | |
| 8903 effect(KILL fcc0); | |
| 8904 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
| 8905 format %{ "dcmpl $dst,$src1,$src2" %} | |
| 8906 // Primary = double (not float) | |
| 8907 opcode( false ); | |
| 8908 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
| 8909 ins_pipe( floating_cmp ); | |
| 8910 %} | |
| 8911 | |
| 8912 //----------Branches--------------------------------------------------------- | |
| 8913 // Jump | |
| 8914 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above) | |
| 8915 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{ | |
| 8916 match(Jump switch_val); | |
| 8917 | |
| 8918 ins_cost(350); | |
| 8919 | |
| 8920 format %{ "SETHI [hi(table_base)],O7\n\t" | |
| 8921 "ADD O7, lo(table_base), O7\n\t" | |
| 8922 "LD [O7+$switch_val], O7\n\t" | |
| 8923 "JUMP O7" | |
| 8924 %} | |
| 8925 ins_encode( jump_enc( switch_val, table) ); | |
| 8926 ins_pc_relative(1); | |
| 8927 ins_pipe(ialu_reg_reg); | |
| 8928 %} | |
| 8929 | |
| 8930 // Direct Branch. Use V8 version with longer range. | |
| 8931 instruct branch(label labl) %{ | |
| 8932 match(Goto); | |
| 8933 effect(USE labl); | |
| 8934 | |
| 8935 size(8); | |
| 8936 ins_cost(BRANCH_COST); | |
| 8937 format %{ "BA $labl" %} | |
| 8938 // Prim = bits 24-22, Secnd = bits 31-30, Tert = cond | |
| 8939 opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always); | |
| 8940 ins_encode( enc_ba( labl ) ); | |
| 8941 ins_pc_relative(1); | |
| 8942 ins_pipe(br); | |
| 8943 %} | |
| 8944 | |
| 8945 // Conditional Direct Branch | |
| 8946 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{ | |
| 8947 match(If cmp icc); | |
| 8948 effect(USE labl); | |
| 8949 | |
| 8950 size(8); | |
| 8951 ins_cost(BRANCH_COST); | |
| 8952 format %{ "BP$cmp $icc,$labl" %} | |
| 8953 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 8954 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 8955 ins_pc_relative(1); | |
| 8956 ins_pipe(br_cc); | |
| 8957 %} | |
| 8958 | |
| 8959 // Branch-on-register tests all 64 bits. We assume that values | |
| 8960 // in 64-bit registers always remains zero or sign extended | |
| 8961 // unless our code munges the high bits. Interrupts can chop | |
| 8962 // the high order bits to zero or sign at any time. | |
| 8963 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{ | |
| 8964 match(If cmp (CmpI op1 zero)); | |
| 8965 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
| 8966 effect(USE labl); | |
| 8967 | |
| 8968 size(8); | |
| 8969 ins_cost(BRANCH_COST); | |
| 8970 format %{ "BR$cmp $op1,$labl" %} | |
| 8971 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
| 8972 ins_pc_relative(1); | |
| 8973 ins_pipe(br_reg); | |
| 8974 %} | |
| 8975 | |
| 8976 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{ | |
| 8977 match(If cmp (CmpP op1 null)); | |
| 8978 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
| 8979 effect(USE labl); | |
| 8980 | |
| 8981 size(8); | |
| 8982 ins_cost(BRANCH_COST); | |
| 8983 format %{ "BR$cmp $op1,$labl" %} | |
| 8984 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
| 8985 ins_pc_relative(1); | |
| 8986 ins_pipe(br_reg); | |
| 8987 %} | |
| 8988 | |
| 8989 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{ | |
| 8990 match(If cmp (CmpL op1 zero)); | |
| 8991 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
| 8992 effect(USE labl); | |
| 8993 | |
| 8994 size(8); | |
| 8995 ins_cost(BRANCH_COST); | |
| 8996 format %{ "BR$cmp $op1,$labl" %} | |
| 8997 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
| 8998 ins_pc_relative(1); | |
| 8999 ins_pipe(br_reg); | |
| 9000 %} | |
| 9001 | |
| 9002 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
| 9003 match(If cmp icc); | |
| 9004 effect(USE labl); | |
| 9005 | |
| 9006 format %{ "BP$cmp $icc,$labl" %} | |
| 9007 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9008 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 9009 ins_pc_relative(1); | |
| 9010 ins_pipe(br_cc); | |
| 9011 %} | |
| 9012 | |
| 9013 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{ | |
| 9014 match(If cmp pcc); | |
| 9015 effect(USE labl); | |
| 9016 | |
| 9017 size(8); | |
| 9018 ins_cost(BRANCH_COST); | |
| 9019 format %{ "BP$cmp $pcc,$labl" %} | |
| 9020 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9021 ins_encode( enc_bpx( labl, cmp, pcc ) ); | |
| 9022 ins_pc_relative(1); | |
| 9023 ins_pipe(br_cc); | |
| 9024 %} | |
| 9025 | |
| 9026 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{ | |
| 9027 match(If cmp fcc); | |
| 9028 effect(USE labl); | |
| 9029 | |
| 9030 size(8); | |
| 9031 ins_cost(BRANCH_COST); | |
| 9032 format %{ "FBP$cmp $fcc,$labl" %} | |
| 9033 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9034 ins_encode( enc_fbp( labl, cmp, fcc ) ); | |
| 9035 ins_pc_relative(1); | |
| 9036 ins_pipe(br_fcc); | |
| 9037 %} | |
| 9038 | |
| 9039 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{ | |
| 9040 match(CountedLoopEnd cmp icc); | |
| 9041 effect(USE labl); | |
| 9042 | |
| 9043 size(8); | |
| 9044 ins_cost(BRANCH_COST); | |
| 9045 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
| 9046 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9047 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 9048 ins_pc_relative(1); | |
| 9049 ins_pipe(br_cc); | |
| 9050 %} | |
| 9051 | |
| 9052 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
| 9053 match(CountedLoopEnd cmp icc); | |
| 9054 effect(USE labl); | |
| 9055 | |
| 9056 size(8); | |
| 9057 ins_cost(BRANCH_COST); | |
| 9058 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
| 9059 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9060 ins_encode( enc_bp( labl, cmp, icc ) ); | |
| 9061 ins_pc_relative(1); | |
| 9062 ins_pipe(br_cc); | |
| 9063 %} | |
| 9064 | |
| 9065 // ============================================================================ | |
| 9066 // Long Compare | |
| 9067 // | |
| 9068 // Currently we hold longs in 2 registers. Comparing such values efficiently | |
| 9069 // is tricky. The flavor of compare used depends on whether we are testing | |
| 9070 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. | |
| 9071 // The GE test is the negated LT test. The LE test can be had by commuting | |
| 9072 // the operands (yielding a GE test) and then negating; negate again for the | |
| 9073 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the | |
| 9074 // NE test is negated from that. | |
| 9075 | |
| 9076 // Due to a shortcoming in the ADLC, it mixes up expressions like: | |
| 9077 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the | |
| 9078 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections | |
| 9079 // are collapsed internally in the ADLC's dfa-gen code. The match for | |
| 9080 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the | |
| 9081 // foo match ends up with the wrong leaf. One fix is to not match both | |
| 9082 // reg-reg and reg-zero forms of long-compare. This is unfortunate because | |
| 9083 // both forms beat the trinary form of long-compare and both are very useful | |
| 9084 // on Intel which has so few registers. | |
| 9085 | |
| 9086 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{ | |
| 9087 match(If cmp xcc); | |
| 9088 effect(USE labl); | |
| 9089 | |
| 9090 size(8); | |
| 9091 ins_cost(BRANCH_COST); | |
| 9092 format %{ "BP$cmp $xcc,$labl" %} | |
| 9093 // Prim = bits 24-22, Secnd = bits 31-30 | |
| 9094 ins_encode( enc_bpl( labl, cmp, xcc ) ); | |
| 9095 ins_pc_relative(1); | |
| 9096 ins_pipe(br_cc); | |
| 9097 %} | |
| 9098 | |
| 9099 // Manifest a CmpL3 result in an integer register. Very painful. | |
| 9100 // This is the test to avoid. | |
| 9101 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{ | |
| 9102 match(Set dst (CmpL3 src1 src2) ); | |
| 9103 effect( KILL ccr ); | |
| 9104 ins_cost(6*DEFAULT_COST); | |
| 9105 size(24); | |
| 9106 format %{ "CMP $src1,$src2\t\t! long\n" | |
| 9107 "\tBLT,a,pn done\n" | |
| 9108 "\tMOV -1,$dst\t! delay slot\n" | |
| 9109 "\tBGT,a,pn done\n" | |
| 9110 "\tMOV 1,$dst\t! delay slot\n" | |
| 9111 "\tCLR $dst\n" | |
| 9112 "done:" %} | |
| 9113 ins_encode( cmpl_flag(src1,src2,dst) ); | |
| 9114 ins_pipe(cmpL_reg); | |
| 9115 %} | |
| 9116 | |
| 9117 // Conditional move | |
| 9118 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{ | |
| 9119 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
| 9120 ins_cost(150); | |
| 9121 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
| 9122 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9123 ins_pipe(ialu_reg); | |
| 9124 %} | |
| 9125 | |
| 9126 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{ | |
| 9127 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
| 9128 ins_cost(140); | |
| 9129 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
| 9130 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
| 9131 ins_pipe(ialu_imm); | |
| 9132 %} | |
| 9133 | |
| 9134 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{ | |
| 9135 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
| 9136 ins_cost(150); | |
| 9137 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 9138 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9139 ins_pipe(ialu_reg); | |
| 9140 %} | |
| 9141 | |
| 9142 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{ | |
| 9143 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
| 9144 ins_cost(140); | |
| 9145 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 9146 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
| 9147 ins_pipe(ialu_imm); | |
| 9148 %} | |
| 9149 | |
|
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9150 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{ |
|
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9151 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src))); |
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9152 ins_cost(150); |
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9153 format %{ "MOV$cmp $xcc,$src,$dst" %} |
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9154 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); |
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9155 ins_pipe(ialu_reg); |
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9156 %} |
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9157 |
| 0 | 9158 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{ |
| 9159 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
| 9160 ins_cost(150); | |
| 9161 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 9162 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9163 ins_pipe(ialu_reg); | |
| 9164 %} | |
| 9165 | |
| 9166 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{ | |
| 9167 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
| 9168 ins_cost(140); | |
| 9169 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
| 9170 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
| 9171 ins_pipe(ialu_imm); | |
| 9172 %} | |
| 9173 | |
| 9174 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{ | |
| 9175 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src))); | |
| 9176 ins_cost(150); | |
| 9177 opcode(0x101); | |
| 9178 format %{ "FMOVS$cmp $xcc,$src,$dst" %} | |
| 9179 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9180 ins_pipe(int_conditional_float_move); | |
| 9181 %} | |
| 9182 | |
| 9183 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{ | |
| 9184 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src))); | |
| 9185 ins_cost(150); | |
| 9186 opcode(0x102); | |
| 9187 format %{ "FMOVD$cmp $xcc,$src,$dst" %} | |
| 9188 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
| 9189 ins_pipe(int_conditional_float_move); | |
| 9190 %} | |
| 9191 | |
| 9192 // ============================================================================ | |
| 9193 // Safepoint Instruction | |
| 9194 instruct safePoint_poll(iRegP poll) %{ | |
| 9195 match(SafePoint poll); | |
| 9196 effect(USE poll); | |
| 9197 | |
| 9198 size(4); | |
| 9199 #ifdef _LP64 | |
| 9200 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %} | |
| 9201 #else | |
| 9202 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %} | |
| 9203 #endif | |
| 9204 ins_encode %{ | |
| 9205 __ relocate(relocInfo::poll_type); | |
| 9206 __ ld_ptr($poll$$Register, 0, G0); | |
| 9207 %} | |
| 9208 ins_pipe(loadPollP); | |
| 9209 %} | |
| 9210 | |
| 9211 // ============================================================================ | |
| 9212 // Call Instructions | |
| 9213 // Call Java Static Instruction | |
| 9214 instruct CallStaticJavaDirect( method meth ) %{ | |
| 9215 match(CallStaticJava); | |
| 9216 effect(USE meth); | |
| 9217 | |
| 9218 size(8); | |
| 9219 ins_cost(CALL_COST); | |
| 9220 format %{ "CALL,static ; NOP ==> " %} | |
| 9221 ins_encode( Java_Static_Call( meth ), call_epilog ); | |
| 9222 ins_pc_relative(1); | |
| 9223 ins_pipe(simple_call); | |
| 9224 %} | |
| 9225 | |
| 9226 // Call Java Dynamic Instruction | |
| 9227 instruct CallDynamicJavaDirect( method meth ) %{ | |
| 9228 match(CallDynamicJava); | |
| 9229 effect(USE meth); | |
| 9230 | |
| 9231 ins_cost(CALL_COST); | |
| 9232 format %{ "SET (empty),R_G5\n\t" | |
| 9233 "CALL,dynamic ; NOP ==> " %} | |
| 9234 ins_encode( Java_Dynamic_Call( meth ), call_epilog ); | |
| 9235 ins_pc_relative(1); | |
| 9236 ins_pipe(call); | |
| 9237 %} | |
| 9238 | |
| 9239 // Call Runtime Instruction | |
| 9240 instruct CallRuntimeDirect(method meth, l7RegP l7) %{ | |
| 9241 match(CallRuntime); | |
| 9242 effect(USE meth, KILL l7); | |
| 9243 ins_cost(CALL_COST); | |
| 9244 format %{ "CALL,runtime" %} | |
| 9245 ins_encode( Java_To_Runtime( meth ), | |
| 9246 call_epilog, adjust_long_from_native_call ); | |
| 9247 ins_pc_relative(1); | |
| 9248 ins_pipe(simple_call); | |
| 9249 %} | |
| 9250 | |
| 9251 // Call runtime without safepoint - same as CallRuntime | |
| 9252 instruct CallLeafDirect(method meth, l7RegP l7) %{ | |
| 9253 match(CallLeaf); | |
| 9254 effect(USE meth, KILL l7); | |
| 9255 ins_cost(CALL_COST); | |
| 9256 format %{ "CALL,runtime leaf" %} | |
| 9257 ins_encode( Java_To_Runtime( meth ), | |
| 9258 call_epilog, | |
| 9259 adjust_long_from_native_call ); | |
| 9260 ins_pc_relative(1); | |
| 9261 ins_pipe(simple_call); | |
| 9262 %} | |
| 9263 | |
| 9264 // Call runtime without safepoint - same as CallLeaf | |
| 9265 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{ | |
| 9266 match(CallLeafNoFP); | |
| 9267 effect(USE meth, KILL l7); | |
| 9268 ins_cost(CALL_COST); | |
| 9269 format %{ "CALL,runtime leaf nofp" %} | |
| 9270 ins_encode( Java_To_Runtime( meth ), | |
| 9271 call_epilog, | |
| 9272 adjust_long_from_native_call ); | |
| 9273 ins_pc_relative(1); | |
| 9274 ins_pipe(simple_call); | |
| 9275 %} | |
| 9276 | |
| 9277 // Tail Call; Jump from runtime stub to Java code. | |
| 9278 // Also known as an 'interprocedural jump'. | |
| 9279 // Target of jump will eventually return to caller. | |
| 9280 // TailJump below removes the return address. | |
| 9281 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{ | |
| 9282 match(TailCall jump_target method_oop ); | |
| 9283 | |
| 9284 ins_cost(CALL_COST); | |
| 9285 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %} | |
| 9286 ins_encode(form_jmpl(jump_target)); | |
| 9287 ins_pipe(tail_call); | |
| 9288 %} | |
| 9289 | |
| 9290 | |
| 9291 // Return Instruction | |
| 9292 instruct Ret() %{ | |
| 9293 match(Return); | |
| 9294 | |
| 9295 // The epilogue node did the ret already. | |
| 9296 size(0); | |
| 9297 format %{ "! return" %} | |
| 9298 ins_encode(); | |
| 9299 ins_pipe(empty); | |
| 9300 %} | |
| 9301 | |
| 9302 | |
| 9303 // Tail Jump; remove the return address; jump to target. | |
| 9304 // TailCall above leaves the return address around. | |
| 9305 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). | |
| 9306 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a | |
| 9307 // "restore" before this instruction (in Epilogue), we need to materialize it | |
| 9308 // in %i0. | |
| 9309 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{ | |
| 9310 match( TailJump jump_target ex_oop ); | |
| 9311 ins_cost(CALL_COST); | |
| 9312 format %{ "! discard R_O7\n\t" | |
| 9313 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %} | |
| 9314 ins_encode(form_jmpl_set_exception_pc(jump_target)); | |
| 9315 // opcode(Assembler::jmpl_op3, Assembler::arith_op); | |
| 9316 // The hack duplicates the exception oop into G3, so that CreateEx can use it there. | |
| 9317 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() ); | |
| 9318 ins_pipe(tail_call); | |
| 9319 %} | |
| 9320 | |
| 9321 // Create exception oop: created by stack-crawling runtime code. | |
| 9322 // Created exception is now available to this handler, and is setup | |
| 9323 // just prior to jumping to this handler. No code emitted. | |
| 9324 instruct CreateException( o0RegP ex_oop ) | |
| 9325 %{ | |
| 9326 match(Set ex_oop (CreateEx)); | |
| 9327 ins_cost(0); | |
| 9328 | |
| 9329 size(0); | |
| 9330 // use the following format syntax | |
| 9331 format %{ "! exception oop is in R_O0; no code emitted" %} | |
| 9332 ins_encode(); | |
| 9333 ins_pipe(empty); | |
| 9334 %} | |
| 9335 | |
| 9336 | |
| 9337 // Rethrow exception: | |
| 9338 // The exception oop will come in the first argument position. | |
| 9339 // Then JUMP (not call) to the rethrow stub code. | |
| 9340 instruct RethrowException() | |
| 9341 %{ | |
| 9342 match(Rethrow); | |
| 9343 ins_cost(CALL_COST); | |
| 9344 | |
| 9345 // use the following format syntax | |
| 9346 format %{ "Jmp rethrow_stub" %} | |
| 9347 ins_encode(enc_rethrow); | |
| 9348 ins_pipe(tail_call); | |
| 9349 %} | |
| 9350 | |
| 9351 | |
| 9352 // Die now | |
| 9353 instruct ShouldNotReachHere( ) | |
| 9354 %{ | |
| 9355 match(Halt); | |
| 9356 ins_cost(CALL_COST); | |
| 9357 | |
| 9358 size(4); | |
| 9359 // Use the following format syntax | |
| 9360 format %{ "ILLTRAP ; ShouldNotReachHere" %} | |
| 9361 ins_encode( form2_illtrap() ); | |
| 9362 ins_pipe(tail_call); | |
| 9363 %} | |
| 9364 | |
| 9365 // ============================================================================ | |
| 9366 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass | |
| 9367 // array for an instance of the superklass. Set a hidden internal cache on a | |
| 9368 // hit (cache is checked with exposed code in gen_subtype_check()). Return | |
| 9369 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. | |
| 9370 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{ | |
| 9371 match(Set index (PartialSubtypeCheck sub super)); | |
| 9372 effect( KILL pcc, KILL o7 ); | |
| 9373 ins_cost(DEFAULT_COST*10); | |
| 9374 format %{ "CALL PartialSubtypeCheck\n\tNOP" %} | |
| 9375 ins_encode( enc_PartialSubtypeCheck() ); | |
| 9376 ins_pipe(partial_subtype_check_pipe); | |
| 9377 %} | |
| 9378 | |
| 9379 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{ | |
| 9380 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero)); | |
| 9381 effect( KILL idx, KILL o7 ); | |
| 9382 ins_cost(DEFAULT_COST*10); | |
| 9383 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %} | |
| 9384 ins_encode( enc_PartialSubtypeCheck() ); | |
| 9385 ins_pipe(partial_subtype_check_pipe); | |
| 9386 %} | |
| 9387 | |
|
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9388 |
| 0 | 9389 // ============================================================================ |
| 9390 // inlined locking and unlocking | |
| 9391 | |
| 9392 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ | |
| 9393 match(Set pcc (FastLock object box)); | |
| 9394 | |
| 9395 effect(KILL scratch, TEMP scratch2); | |
| 9396 ins_cost(100); | |
| 9397 | |
| 9398 size(4*112); // conservative overestimation ... | |
| 9399 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %} | |
| 9400 ins_encode( Fast_Lock(object, box, scratch, scratch2) ); | |
| 9401 ins_pipe(long_memory_op); | |
| 9402 %} | |
| 9403 | |
| 9404 | |
| 9405 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ | |
| 9406 match(Set pcc (FastUnlock object box)); | |
| 9407 effect(KILL scratch, TEMP scratch2); | |
| 9408 ins_cost(100); | |
| 9409 | |
| 9410 size(4*120); // conservative overestimation ... | |
| 9411 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %} | |
| 9412 ins_encode( Fast_Unlock(object, box, scratch, scratch2) ); | |
| 9413 ins_pipe(long_memory_op); | |
| 9414 %} | |
| 9415 | |
| 9416 // Count and Base registers are fixed because the allocator cannot | |
| 9417 // kill unknown registers. The encodings are generic. | |
| 9418 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{ | |
| 9419 match(Set dummy (ClearArray cnt base)); | |
| 9420 effect(TEMP temp, KILL ccr); | |
| 9421 ins_cost(300); | |
| 9422 format %{ "MOV $cnt,$temp\n" | |
| 9423 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n" | |
| 9424 " BRge loop\t\t! Clearing loop\n" | |
| 9425 " STX G0,[$base+$temp]\t! delay slot" %} | |
| 9426 ins_encode( enc_Clear_Array(cnt, base, temp) ); | |
| 9427 ins_pipe(long_memory_op); | |
| 9428 %} | |
| 9429 | |
|
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9430 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, |
|
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|
9431 o7RegI tmp, flagsReg ccr) %{ |
|
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|
9432 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
|
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|
9433 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp); |
| 0 | 9434 ins_cost(300); |
|
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9435 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %} |
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|
9436 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) ); |
| 0 | 9437 ins_pipe(long_memory_op); |
| 9438 %} | |
| 9439 | |
|
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9440 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result, |
|
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9441 o7RegI tmp, flagsReg ccr) %{ |
|
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|
9442 match(Set result (StrEquals (Binary str1 str2) cnt)); |
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9443 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr); |
| 681 | 9444 ins_cost(300); |
|
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9445 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %} |
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|
9446 ins_encode( enc_String_Equals(str1, str2, cnt, result) ); |
| 681 | 9447 ins_pipe(long_memory_op); |
| 9448 %} | |
| 9449 | |
|
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9450 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result, |
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|
9451 o7RegI tmp2, flagsReg ccr) %{ |
| 681 | 9452 match(Set result (AryEq ary1 ary2)); |
| 9453 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); | |
| 9454 ins_cost(300); | |
|
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9455 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %} |
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9456 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result)); |
| 681 | 9457 ins_pipe(long_memory_op); |
| 9458 %} | |
|
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9459 |
|
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|
9460 |
|
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9461 //---------- Zeros Count Instructions ------------------------------------------ |
|
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|
9462 |
|
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|
9463 instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{ |
|
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|
9464 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
|
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|
9465 match(Set dst (CountLeadingZerosI src)); |
|
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9466 effect(TEMP dst, TEMP tmp, KILL cr); |
|
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|
9467 |
|
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|
9468 // x |= (x >> 1); |
|
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|
9469 // x |= (x >> 2); |
|
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|
9470 // x |= (x >> 4); |
|
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|
9471 // x |= (x >> 8); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9472 // x |= (x >> 16); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9473 // return (WORDBITS - popc(x)); |
|
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9474 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t" |
|
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9475 "SRL $src,0,$dst\t! 32-bit zero extend\n\t" |
|
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9476 "OR $dst,$tmp,$dst\n\t" |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9477 "SRL $dst,2,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9478 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9479 "SRL $dst,4,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9480 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9481 "SRL $dst,8,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9482 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9483 "SRL $dst,16,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9484 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9485 "POPC $dst,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9486 "MOV 32,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9487 "SUB $tmp,$dst,$dst" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9488 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9489 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9490 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9491 Register Rtmp = $tmp$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9492 __ srl(Rsrc, 1, Rtmp); |
|
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9493 __ srl(Rsrc, 0, Rdst); |
|
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9494 __ or3(Rdst, Rtmp, Rdst); |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9495 __ srl(Rdst, 2, Rtmp); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9496 __ or3(Rdst, Rtmp, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9497 __ srl(Rdst, 4, Rtmp); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9498 __ or3(Rdst, Rtmp, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9499 __ srl(Rdst, 8, Rtmp); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9500 __ or3(Rdst, Rtmp, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9501 __ srl(Rdst, 16, Rtmp); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9502 __ or3(Rdst, Rtmp, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9503 __ popc(Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9504 __ mov(BitsPerInt, Rtmp); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9505 __ sub(Rtmp, Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9506 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9507 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9508 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9509 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9510 instruct countLeadingZerosL(iRegI dst, iRegL src, iRegL tmp, flagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9511 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9512 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9513 effect(TEMP dst, TEMP tmp, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9514 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9515 // x |= (x >> 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9516 // x |= (x >> 2); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9517 // x |= (x >> 4); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9518 // x |= (x >> 8); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9519 // x |= (x >> 16); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9520 // x |= (x >> 32); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9521 // return (WORDBITS - popc(x)); |
|
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9522 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t" |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9523 "OR $src,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9524 "SRLX $dst,2,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9525 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9526 "SRLX $dst,4,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9527 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9528 "SRLX $dst,8,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9529 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9530 "SRLX $dst,16,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9531 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9532 "SRLX $dst,32,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9533 "OR $dst,$tmp,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9534 "POPC $dst,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9535 "MOV 64,$tmp\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9536 "SUB $tmp,$dst,$dst" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9537 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9538 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9539 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9540 Register Rtmp = $tmp$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9541 __ srlx(Rsrc, 1, Rtmp); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9542 __ or3(Rsrc, Rtmp, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9543 __ srlx(Rdst, 2, Rtmp); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9544 __ or3(Rdst, Rtmp, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9545 __ srlx(Rdst, 4, Rtmp); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9546 __ or3(Rdst, Rtmp, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9547 __ srlx(Rdst, 8, Rtmp); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9548 __ or3(Rdst, Rtmp, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9549 __ srlx(Rdst, 16, Rtmp); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9550 __ or3(Rdst, Rtmp, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9551 __ srlx(Rdst, 32, Rtmp); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9552 __ or3(Rdst, Rtmp, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9553 __ popc(Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9554 __ mov(BitsPerLong, Rtmp); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9555 __ sub(Rtmp, Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9556 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9557 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9558 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9559 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9560 instruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9561 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9562 match(Set dst (CountTrailingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9563 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9564 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9565 // return popc(~x & (x - 1)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9566 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9567 "ANDN $dst,$src,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9568 "SRL $dst,R_G0,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9569 "POPC $dst,$dst" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9570 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9571 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9572 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9573 __ sub(Rsrc, 1, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9574 __ andn(Rdst, Rsrc, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9575 __ srl(Rdst, G0, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9576 __ popc(Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9577 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9578 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9579 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9580 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9581 instruct countTrailingZerosL(iRegI dst, iRegL src, flagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9582 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9583 match(Set dst (CountTrailingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9584 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9585 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9586 // return popc(~x & (x - 1)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9587 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9588 "ANDN $dst,$src,$dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9589 "POPC $dst,$dst" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9590 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9591 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9592 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9593 __ sub(Rsrc, 1, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9594 __ andn(Rdst, Rsrc, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9595 __ popc(Rdst, Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9596 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9597 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9598 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9599 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9600 |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9601 //---------- Population Count Instructions ------------------------------------- |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9602 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9603 instruct popCountI(iRegI dst, iRegI src) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9604 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9605 match(Set dst (PopCountI src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9606 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9607 format %{ "POPC $src, $dst" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9608 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9609 __ popc($src$$Register, $dst$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9610 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9611 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9612 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9613 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9614 // Note: Long.bitCount(long) returns an int. |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9615 instruct popCountL(iRegI dst, iRegL src) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9616 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9617 match(Set dst (PopCountL src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9618 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9619 format %{ "POPC $src, $dst" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9620 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9621 __ popc($src$$Register, $dst$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9622 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9623 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9624 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9625 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9626 |
| 0 | 9627 // ============================================================================ |
| 9628 //------------Bytes reverse-------------------------------------------------- | |
| 9629 | |
| 9630 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{ | |
| 9631 match(Set dst (ReverseBytesI src)); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9632 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9633 // Op cost is artificially doubled to make sure that load or store |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9634 // instructions are preferred over this one which requires a spill |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9635 // onto a stack slot. |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9636 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9637 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9638 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9639 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9640 __ set($src$$disp + STACK_BIAS, O7); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9641 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9642 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9643 ins_pipe( iload_mem ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9644 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9645 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9646 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9647 match(Set dst (ReverseBytesL src)); |
| 0 | 9648 |
| 9649 // Op cost is artificially doubled to make sure that load or store | |
| 9650 // instructions are preferred over this one which requires a spill | |
| 9651 // onto a stack slot. | |
| 9652 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9653 format %{ "LDXA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9654 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9655 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9656 __ set($src$$disp + STACK_BIAS, O7); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9657 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9658 %} |
| 0 | 9659 ins_pipe( iload_mem ); |
| 9660 %} | |
| 9661 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9662 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9663 match(Set dst (ReverseBytesUS src)); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9664 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9665 // Op cost is artificially doubled to make sure that load or store |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9666 // instructions are preferred over this one which requires a spill |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9667 // onto a stack slot. |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9668 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9669 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9670 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9671 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9672 // the value was spilled as an int so bias the load |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9673 __ set($src$$disp + STACK_BIAS + 2, O7); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9674 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9675 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9676 ins_pipe( iload_mem ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9677 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9678 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9679 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9680 match(Set dst (ReverseBytesS src)); |
| 0 | 9681 |
| 9682 // Op cost is artificially doubled to make sure that load or store | |
| 9683 // instructions are preferred over this one which requires a spill | |
| 9684 // onto a stack slot. | |
| 9685 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9686 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9687 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9688 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9689 // the value was spilled as an int so bias the load |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9690 __ set($src$$disp + STACK_BIAS + 2, O7); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9691 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9692 %} |
| 0 | 9693 ins_pipe( iload_mem ); |
| 9694 %} | |
| 9695 | |
| 9696 // Load Integer reversed byte order | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9697 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{ |
| 0 | 9698 match(Set dst (ReverseBytesI (LoadI src))); |
| 9699 | |
| 9700 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9701 size(4); |
| 0 | 9702 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} |
| 9703 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9704 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9705 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9706 %} |
| 0 | 9707 ins_pipe(iload_mem); |
| 9708 %} | |
| 9709 | |
| 9710 // Load Long - aligned and reversed | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9711 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{ |
| 0 | 9712 match(Set dst (ReverseBytesL (LoadL src))); |
| 9713 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9714 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9715 size(4); |
| 0 | 9716 format %{ "LDXA $src, $dst\t!asi=primary_little" %} |
| 9717 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9718 ins_encode %{ |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9719 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9720 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9721 ins_pipe(iload_mem); |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9722 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9723 |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9724 // Load unsigned short / char reversed byte order |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9725 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{ |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9726 match(Set dst (ReverseBytesUS (LoadUS src))); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9727 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9728 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9729 size(4); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9730 format %{ "LDUHA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9731 |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9732 ins_encode %{ |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9733 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9734 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9735 ins_pipe(iload_mem); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9736 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9737 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9738 // Load short reversed byte order |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9739 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{ |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9740 match(Set dst (ReverseBytesS (LoadS src))); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9741 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9742 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9743 size(4); |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9744 format %{ "LDSHA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9745 |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9746 ins_encode %{ |
|
d7f654633cfe
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never
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1367
diff
changeset
|
9747 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); |
|
d7f654633cfe
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never
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diff
changeset
|
9748 %} |
| 0 | 9749 ins_pipe(iload_mem); |
| 9750 %} | |
| 9751 | |
| 9752 // Store Integer reversed byte order | |
|
1396
d7f654633cfe
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1367
diff
changeset
|
9753 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{ |
| 0 | 9754 match(Set dst (StoreI dst (ReverseBytesI src))); |
| 9755 | |
| 9756 ins_cost(MEMORY_REF_COST); | |
|
1396
d7f654633cfe
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never
parents:
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diff
changeset
|
9757 size(4); |
| 0 | 9758 format %{ "STWA $src, $dst\t!asi=primary_little" %} |
| 9759 | |
|
1396
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9760 ins_encode %{ |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9761 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
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diff
changeset
|
9762 %} |
| 0 | 9763 ins_pipe(istore_mem_reg); |
| 9764 %} | |
| 9765 | |
| 9766 // Store Long reversed byte order | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9767 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{ |
| 0 | 9768 match(Set dst (StoreL dst (ReverseBytesL src))); |
| 9769 | |
| 9770 ins_cost(MEMORY_REF_COST); | |
|
1396
d7f654633cfe
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never
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diff
changeset
|
9771 size(4); |
| 0 | 9772 format %{ "STXA $src, $dst\t!asi=primary_little" %} |
| 9773 | |
|
1396
d7f654633cfe
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never
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1367
diff
changeset
|
9774 ins_encode %{ |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9775 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9776 %} |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9777 ins_pipe(istore_mem_reg); |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9778 %} |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9779 |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9780 // Store unsighed short/char reversed byte order |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9781 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{ |
|
d7f654633cfe
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never
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1367
diff
changeset
|
9782 match(Set dst (StoreC dst (ReverseBytesUS src))); |
|
d7f654633cfe
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never
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diff
changeset
|
9783 |
|
d7f654633cfe
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never
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1367
diff
changeset
|
9784 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9785 size(4); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9786 format %{ "STHA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9787 |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9788 ins_encode %{ |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9789 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9790 %} |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9791 ins_pipe(istore_mem_reg); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9792 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9793 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9794 // Store short reversed byte order |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9795 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{ |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9796 match(Set dst (StoreC dst (ReverseBytesS src))); |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9797 |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9798 ins_cost(MEMORY_REF_COST); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9799 size(4); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1367
diff
changeset
|
9800 format %{ "STHA $src, $dst\t!asi=primary_little" %} |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9801 |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9802 ins_encode %{ |
|
d7f654633cfe
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never
parents:
1367
diff
changeset
|
9803 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); |
|
d7f654633cfe
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never
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diff
changeset
|
9804 %} |
| 0 | 9805 ins_pipe(istore_mem_reg); |
| 9806 %} | |
| 9807 | |
| 9808 //----------PEEPHOLE RULES----------------------------------------------------- | |
| 9809 // These must follow all instruction definitions as they use the names | |
| 9810 // defined in the instructions definitions. | |
| 9811 // | |
| 605 | 9812 // peepmatch ( root_instr_name [preceding_instruction]* ); |
| 0 | 9813 // |
| 9814 // peepconstraint %{ | |
| 9815 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
| 9816 // [, ...] ); | |
| 9817 // // instruction numbers are zero-based using left to right order in peepmatch | |
| 9818 // | |
| 9819 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
| 9820 // // provide an instruction_number.operand_name for each operand that appears | |
| 9821 // // in the replacement instruction's match rule | |
| 9822 // | |
| 9823 // ---------VM FLAGS--------------------------------------------------------- | |
| 9824 // | |
| 9825 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
| 9826 // | |
| 9827 // Each peephole rule is given an identifying number starting with zero and | |
| 9828 // increasing by one in the order seen by the parser. An individual peephole | |
| 9829 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
| 9830 // on the command-line. | |
| 9831 // | |
| 9832 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
| 9833 // | |
| 9834 // Only match adjacent instructions in same basic block | |
| 9835 // Only equality constraints | |
| 9836 // Only constraints between operands, not (0.dest_reg == EAX_enc) | |
| 9837 // Only one replacement instruction | |
| 9838 // | |
| 9839 // ---------EXAMPLE---------------------------------------------------------- | |
| 9840 // | |
| 9841 // // pertinent parts of existing instructions in architecture description | |
| 9842 // instruct movI(eRegI dst, eRegI src) %{ | |
| 9843 // match(Set dst (CopyI src)); | |
| 9844 // %} | |
| 9845 // | |
| 9846 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ | |
| 9847 // match(Set dst (AddI dst src)); | |
| 9848 // effect(KILL cr); | |
| 9849 // %} | |
| 9850 // | |
| 9851 // // Change (inc mov) to lea | |
| 9852 // peephole %{ | |
| 9853 // // increment preceeded by register-register move | |
| 9854 // peepmatch ( incI_eReg movI ); | |
| 9855 // // require that the destination register of the increment | |
| 9856 // // match the destination register of the move | |
| 9857 // peepconstraint ( 0.dst == 1.dst ); | |
| 9858 // // construct a replacement instruction that sets | |
| 9859 // // the destination to ( move's source register + one ) | |
| 9860 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) ); | |
| 9861 // %} | |
| 9862 // | |
| 9863 | |
| 9864 // // Change load of spilled value to only a spill | |
| 9865 // instruct storeI(memory mem, eRegI src) %{ | |
| 9866 // match(Set mem (StoreI mem src)); | |
| 9867 // %} | |
| 9868 // | |
| 9869 // instruct loadI(eRegI dst, memory mem) %{ | |
| 9870 // match(Set dst (LoadI mem)); | |
| 9871 // %} | |
| 9872 // | |
| 9873 // peephole %{ | |
| 9874 // peepmatch ( loadI storeI ); | |
| 9875 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); | |
| 9876 // peepreplace ( storeI( 1.mem 1.mem 1.src ) ); | |
| 9877 // %} | |
| 9878 | |
| 9879 //----------SMARTSPILL RULES--------------------------------------------------- | |
| 9880 // These must follow all instruction definitions as they use the names | |
| 9881 // defined in the instructions definitions. | |
| 9882 // | |
| 9883 // SPARC will probably not have any of these rules due to RISC instruction set. | |
| 9884 | |
| 9885 //----------PIPELINE----------------------------------------------------------- | |
| 9886 // Rules which define the behavior of the target architectures pipeline. |