Mercurial > hg > graal-compiler
annotate src/cpu/x86/vm/x86_32.ad @ 6138:ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
Reviewed-by: kvn
| author | twisti |
|---|---|
| date | Mon, 11 Jun 2012 16:47:41 -0700 |
| parents | 6759698e3140 |
| children | 8b0a4867acf0 |
| rev | line source |
|---|---|
| 0 | 1 // |
| 4950 | 2 // Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 // | |
| 5 // This code is free software; you can redistribute it and/or modify it | |
| 6 // under the terms of the GNU General Public License version 2 only, as | |
| 7 // published by the Free Software Foundation. | |
| 8 // | |
| 9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 // version 2 for more details (a copy is included in the LICENSE file that | |
| 13 // accompanied this code). | |
| 14 // | |
| 15 // You should have received a copy of the GNU General Public License version | |
| 16 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 // | |
|
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19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 // or visit www.oracle.com if you need additional information or have any |
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21 // questions. |
| 0 | 22 // |
| 23 // | |
| 24 | |
| 25 // X86 Architecture Description File | |
| 26 | |
| 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
| 28 // This information is used by the matcher and the register allocator to | |
| 29 // describe individual registers and classes of registers within the target | |
| 30 // archtecture. | |
| 31 | |
| 32 register %{ | |
| 33 //----------Architecture Description Register Definitions---------------------- | |
| 34 // General Registers | |
| 35 // "reg_def" name ( register save type, C convention save type, | |
| 36 // ideal register type, encoding ); | |
| 37 // Register Save Types: | |
| 38 // | |
| 39 // NS = No-Save: The register allocator assumes that these registers | |
| 40 // can be used without saving upon entry to the method, & | |
| 41 // that they do not need to be saved at call sites. | |
| 42 // | |
| 43 // SOC = Save-On-Call: The register allocator assumes that these registers | |
| 44 // can be used without saving upon entry to the method, | |
| 45 // but that they must be saved at call sites. | |
| 46 // | |
| 47 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
| 48 // must be saved before using them upon entry to the | |
| 49 // method, but they do not need to be saved at call | |
| 50 // sites. | |
| 51 // | |
| 52 // AS = Always-Save: The register allocator assumes that these registers | |
| 53 // must be saved before using them upon entry to the | |
| 54 // method, & that they must be saved at call sites. | |
| 55 // | |
| 56 // Ideal Register Type is used to determine how to save & restore a | |
| 57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
| 58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
| 59 // | |
| 60 // The encoding number is the actual bit-pattern placed into the opcodes. | |
| 61 | |
| 62 // General Registers | |
| 63 // Previously set EBX, ESI, and EDI as save-on-entry for java code | |
| 64 // Turn off SOE in java-code due to frequent use of uncommon-traps. | |
| 65 // Now that allocator is better, turn on ESI and EDI as SOE registers. | |
| 66 | |
| 67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()); | |
| 68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()); | |
| 69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()); | |
| 70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()); | |
| 71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code | |
| 72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg()); | |
| 73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()); | |
| 74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg()); | |
| 75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg()); | |
| 76 | |
| 77 // Special Registers | |
| 78 reg_def EFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad()); | |
| 79 | |
| 80 // Float registers. We treat TOS/FPR0 special. It is invisible to the | |
| 81 // allocator, and only shows up in the encodings. | |
| 82 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); | |
| 83 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); | |
| 84 // Ok so here's the trick FPR1 is really st(0) except in the midst | |
| 85 // of emission of assembly for a machnode. During the emission the fpu stack | |
| 86 // is pushed making FPR1 == st(1) temporarily. However at any safepoint | |
| 87 // the stack will not have this element so FPR1 == st(0) from the | |
| 88 // oopMap viewpoint. This same weirdness with numbering causes | |
| 89 // instruction encoding to have to play games with the register | |
| 90 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation | |
| 91 // where it does flt->flt moves to see an example | |
| 92 // | |
| 93 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()); | |
| 94 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next()); | |
| 95 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()); | |
| 96 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next()); | |
| 97 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()); | |
| 98 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next()); | |
| 99 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()); | |
| 100 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next()); | |
| 101 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()); | |
| 102 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next()); | |
| 103 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()); | |
| 104 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next()); | |
| 105 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()); | |
| 106 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next()); | |
| 107 | |
| 108 // XMM registers. 128-bit registers or 4 words each, labeled a-d. | |
| 109 // Word a in each register holds a Float, words ab hold a Double. | |
| 110 // We currently do not use the SIMD capabilities, so registers cd | |
| 111 // are unused at the moment. | |
| 112 reg_def XMM0a( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()); | |
| 113 reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next()); | |
| 114 reg_def XMM1a( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()); | |
| 115 reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next()); | |
| 116 reg_def XMM2a( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()); | |
| 117 reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next()); | |
| 118 reg_def XMM3a( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()); | |
| 119 reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next()); | |
| 120 reg_def XMM4a( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()); | |
| 121 reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next()); | |
| 122 reg_def XMM5a( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()); | |
| 123 reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next()); | |
| 124 reg_def XMM6a( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()); | |
| 125 reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next()); | |
| 126 reg_def XMM7a( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()); | |
| 127 reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next()); | |
| 128 | |
| 129 // Specify priority of register selection within phases of register | |
| 130 // allocation. Highest priority is first. A useful heuristic is to | |
| 131 // give registers a low priority when they are required by machine | |
| 132 // instructions, like EAX and EDX. Registers which are used as | |
| 605 | 133 // pairs must fall on an even boundary (witness the FPR#L's in this list). |
| 0 | 134 // For the Intel integer registers, the equivalent Long pairs are |
| 135 // EDX:EAX, EBX:ECX, and EDI:EBP. | |
| 136 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP, | |
| 137 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H, | |
| 138 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H, | |
| 139 FPR6L, FPR6H, FPR7L, FPR7H ); | |
| 140 | |
| 141 alloc_class chunk1( XMM0a, XMM0b, | |
| 142 XMM1a, XMM1b, | |
| 143 XMM2a, XMM2b, | |
| 144 XMM3a, XMM3b, | |
| 145 XMM4a, XMM4b, | |
| 146 XMM5a, XMM5b, | |
| 147 XMM6a, XMM6b, | |
| 148 XMM7a, XMM7b, EFLAGS); | |
| 149 | |
| 150 | |
| 151 //----------Architecture Description Register Classes-------------------------- | |
| 152 // Several register classes are automatically defined based upon information in | |
| 153 // this architecture description. | |
| 154 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ ) | |
| 155 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ ) | |
| 156 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ ) | |
| 157 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
| 158 // | |
| 159 // Class for all registers | |
| 160 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP); | |
| 161 // Class for general registers | |
| 162 reg_class e_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX); | |
| 163 // Class for general registers which may be used for implicit null checks on win95 | |
| 164 // Also safe for use by tailjump. We don't want to allocate in rbp, | |
| 165 reg_class e_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX); | |
| 166 // Class of "X" registers | |
| 167 reg_class x_reg(EBX, ECX, EDX, EAX); | |
| 168 // Class of registers that can appear in an address with no offset. | |
| 169 // EBP and ESP require an extra instruction byte for zero offset. | |
| 170 // Used in fast-unlock | |
| 171 reg_class p_reg(EDX, EDI, ESI, EBX); | |
| 172 // Class for general registers not including ECX | |
| 173 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX); | |
| 174 // Class for general registers not including EAX | |
| 175 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX); | |
| 176 // Class for general registers not including EAX or EBX. | |
| 177 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP); | |
| 178 // Class of EAX (for multiply and divide operations) | |
| 179 reg_class eax_reg(EAX); | |
| 180 // Class of EBX (for atomic add) | |
| 181 reg_class ebx_reg(EBX); | |
| 182 // Class of ECX (for shift and JCXZ operations and cmpLTMask) | |
| 183 reg_class ecx_reg(ECX); | |
| 184 // Class of EDX (for multiply and divide operations) | |
| 185 reg_class edx_reg(EDX); | |
| 186 // Class of EDI (for synchronization) | |
| 187 reg_class edi_reg(EDI); | |
| 188 // Class of ESI (for synchronization) | |
| 189 reg_class esi_reg(ESI); | |
| 190 // Singleton class for interpreter's stack pointer | |
| 191 reg_class ebp_reg(EBP); | |
| 192 // Singleton class for stack pointer | |
| 193 reg_class sp_reg(ESP); | |
| 194 // Singleton class for instruction pointer | |
| 195 // reg_class ip_reg(EIP); | |
| 196 // Singleton class for condition codes | |
| 197 reg_class int_flags(EFLAGS); | |
| 198 // Class of integer register pairs | |
| 199 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI ); | |
| 200 // Class of integer register pairs that aligns with calling convention | |
| 201 reg_class eadx_reg( EAX,EDX ); | |
| 202 reg_class ebcx_reg( ECX,EBX ); | |
| 203 // Not AX or DX, used in divides | |
| 204 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP ); | |
| 205 | |
| 206 // Floating point registers. Notice FPR0 is not a choice. | |
| 207 // FPR0 is not ever allocated; we use clever encodings to fake | |
| 208 // a 2-address instructions out of Intels FP stack. | |
| 209 reg_class flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L ); | |
| 210 | |
| 211 // make a register class for SSE registers | |
| 212 reg_class xmm_reg(XMM0a, XMM1a, XMM2a, XMM3a, XMM4a, XMM5a, XMM6a, XMM7a); | |
| 213 | |
| 214 // make a double register class for SSE2 registers | |
| 215 reg_class xdb_reg(XMM0a,XMM0b, XMM1a,XMM1b, XMM2a,XMM2b, XMM3a,XMM3b, | |
| 216 XMM4a,XMM4b, XMM5a,XMM5b, XMM6a,XMM6b, XMM7a,XMM7b ); | |
| 217 | |
| 218 reg_class dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H, | |
| 219 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H, | |
| 220 FPR7L,FPR7H ); | |
| 221 | |
| 222 reg_class flt_reg0( FPR1L ); | |
| 223 reg_class dbl_reg0( FPR1L,FPR1H ); | |
| 224 reg_class dbl_reg1( FPR2L,FPR2H ); | |
| 225 reg_class dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H, | |
| 226 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H ); | |
| 227 | |
| 228 // XMM6 and XMM7 could be used as temporary registers for long, float and | |
| 229 // double values for SSE2. | |
| 230 reg_class xdb_reg6( XMM6a,XMM6b ); | |
| 231 reg_class xdb_reg7( XMM7a,XMM7b ); | |
| 232 %} | |
| 233 | |
| 234 | |
| 235 //----------SOURCE BLOCK------------------------------------------------------- | |
| 236 // This is a block of C++ code which provides values, functions, and | |
| 237 // definitions necessary in the rest of the architecture description | |
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238 source_hpp %{ |
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239 // Must be visible to the DFA in dfa_x86_32.cpp |
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240 extern bool is_operand_hi32_zero(Node* n); |
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241 %} |
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242 |
| 0 | 243 source %{ |
| 304 | 244 #define RELOC_IMM32 Assembler::imm_operand |
| 0 | 245 #define RELOC_DISP32 Assembler::disp32_operand |
| 246 | |
| 247 #define __ _masm. | |
| 248 | |
| 249 // How to find the high register of a Long pair, given the low register | |
| 250 #define HIGH_FROM_LOW(x) ((x)+2) | |
| 251 | |
| 252 // These masks are used to provide 128-bit aligned bitmasks to the XMM | |
| 253 // instructions, to allow sign-masking or sign-bit flipping. They allow | |
| 254 // fast versions of NegF/NegD and AbsF/AbsD. | |
| 255 | |
| 256 // Note: 'double' and 'long long' have 32-bits alignment on x86. | |
| 257 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { | |
| 258 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address | |
| 259 // of 128-bits operands for SSE instructions. | |
| 260 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF))); | |
| 261 // Store the value to a 128-bits operand. | |
| 262 operand[0] = lo; | |
| 263 operand[1] = hi; | |
| 264 return operand; | |
| 265 } | |
| 266 | |
| 267 // Buffer for 128-bits masks used by SSE instructions. | |
| 268 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) | |
| 269 | |
| 270 // Static initialization during VM startup. | |
| 271 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); | |
| 272 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); | |
| 273 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); | |
| 274 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); | |
| 275 | |
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276 // Offset hacking within calls. |
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277 static int pre_call_FPU_size() { |
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278 if (Compile::current()->in_24_bit_fp_mode()) |
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279 return 6; // fldcw |
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280 return 0; |
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281 } |
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282 |
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283 static int preserve_SP_size() { |
| 4759 | 284 return 2; // op, rm(reg/reg) |
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285 } |
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286 |
| 0 | 287 // !!!!! Special hack to get all type of calls to specify the byte offset |
| 288 // from the start of the call to the point where the return address | |
| 289 // will point. | |
| 290 int MachCallStaticJavaNode::ret_addr_offset() { | |
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291 int offset = 5 + pre_call_FPU_size(); // 5 bytes from start of call to where return address points |
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292 if (_method_handle_invoke) |
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293 offset += preserve_SP_size(); |
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294 return offset; |
| 0 | 295 } |
| 296 | |
| 297 int MachCallDynamicJavaNode::ret_addr_offset() { | |
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298 return 10 + pre_call_FPU_size(); // 10 bytes from start of call to where return address points |
| 0 | 299 } |
| 300 | |
| 301 static int sizeof_FFree_Float_Stack_All = -1; | |
| 302 | |
| 303 int MachCallRuntimeNode::ret_addr_offset() { | |
| 304 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already"); | |
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305 return sizeof_FFree_Float_Stack_All + 5 + pre_call_FPU_size(); |
| 0 | 306 } |
| 307 | |
| 308 // Indicate if the safepoint node needs the polling page as an input. | |
| 309 // Since x86 does have absolute addressing, it doesn't. | |
| 310 bool SafePointNode::needs_polling_address_input() { | |
| 311 return false; | |
| 312 } | |
| 313 | |
| 314 // | |
| 315 // Compute padding required for nodes which need alignment | |
| 316 // | |
| 317 | |
| 318 // The address of the call instruction needs to be 4-byte aligned to | |
| 319 // ensure that it does not span a cache line so that it can be patched. | |
| 320 int CallStaticJavaDirectNode::compute_padding(int current_offset) const { | |
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321 current_offset += pre_call_FPU_size(); // skip fldcw, if any |
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322 current_offset += 1; // skip call opcode byte |
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323 return round_to(current_offset, alignment_required()) - current_offset; |
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324 } |
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325 |
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326 // The address of the call instruction needs to be 4-byte aligned to |
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327 // ensure that it does not span a cache line so that it can be patched. |
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328 int CallStaticJavaHandleNode::compute_padding(int current_offset) const { |
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329 current_offset += pre_call_FPU_size(); // skip fldcw, if any |
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330 current_offset += preserve_SP_size(); // skip mov rbp, rsp |
| 0 | 331 current_offset += 1; // skip call opcode byte |
| 332 return round_to(current_offset, alignment_required()) - current_offset; | |
| 333 } | |
| 334 | |
| 335 // The address of the call instruction needs to be 4-byte aligned to | |
| 336 // ensure that it does not span a cache line so that it can be patched. | |
| 337 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const { | |
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338 current_offset += pre_call_FPU_size(); // skip fldcw, if any |
| 0 | 339 current_offset += 5; // skip MOV instruction |
| 340 current_offset += 1; // skip call opcode byte | |
| 341 return round_to(current_offset, alignment_required()) - current_offset; | |
| 342 } | |
| 343 | |
| 344 // EMIT_RM() | |
| 345 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) { | |
| 346 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3); | |
| 1748 | 347 cbuf.insts()->emit_int8(c); |
| 0 | 348 } |
| 349 | |
| 350 // EMIT_CC() | |
| 351 void emit_cc(CodeBuffer &cbuf, int f1, int f2) { | |
| 352 unsigned char c = (unsigned char)( f1 | f2 ); | |
| 1748 | 353 cbuf.insts()->emit_int8(c); |
| 0 | 354 } |
| 355 | |
| 356 // EMIT_OPCODE() | |
| 357 void emit_opcode(CodeBuffer &cbuf, int code) { | |
| 1748 | 358 cbuf.insts()->emit_int8((unsigned char) code); |
| 0 | 359 } |
| 360 | |
| 361 // EMIT_OPCODE() w/ relocation information | |
| 362 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) { | |
| 1748 | 363 cbuf.relocate(cbuf.insts_mark() + offset, reloc); |
| 0 | 364 emit_opcode(cbuf, code); |
| 365 } | |
| 366 | |
| 367 // EMIT_D8() | |
| 368 void emit_d8(CodeBuffer &cbuf, int d8) { | |
| 1748 | 369 cbuf.insts()->emit_int8((unsigned char) d8); |
| 0 | 370 } |
| 371 | |
| 372 // EMIT_D16() | |
| 373 void emit_d16(CodeBuffer &cbuf, int d16) { | |
| 1748 | 374 cbuf.insts()->emit_int16(d16); |
| 0 | 375 } |
| 376 | |
| 377 // EMIT_D32() | |
| 378 void emit_d32(CodeBuffer &cbuf, int d32) { | |
| 1748 | 379 cbuf.insts()->emit_int32(d32); |
| 0 | 380 } |
| 381 | |
| 382 // emit 32 bit value and construct relocation entry from relocInfo::relocType | |
| 383 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc, | |
| 384 int format) { | |
| 1748 | 385 cbuf.relocate(cbuf.insts_mark(), reloc, format); |
| 386 cbuf.insts()->emit_int32(d32); | |
| 0 | 387 } |
| 388 | |
| 389 // emit 32 bit value and construct relocation entry from RelocationHolder | |
| 390 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec, | |
| 391 int format) { | |
| 392 #ifdef ASSERT | |
| 393 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) { | |
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394 assert(oop(d32)->is_oop() && (ScavengeRootsInCode || !oop(d32)->is_scavengable()), "cannot embed scavengable oops in code"); |
| 0 | 395 } |
| 396 #endif | |
| 1748 | 397 cbuf.relocate(cbuf.insts_mark(), rspec, format); |
| 398 cbuf.insts()->emit_int32(d32); | |
| 0 | 399 } |
| 400 | |
| 401 // Access stack slot for load or store | |
| 402 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) { | |
| 403 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src]) | |
| 404 if( -128 <= disp && disp <= 127 ) { | |
| 405 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte | |
| 406 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 407 emit_d8 (cbuf, disp); // Displacement // R/M byte | |
| 408 } else { | |
| 409 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte | |
| 410 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 411 emit_d32(cbuf, disp); // Displacement // R/M byte | |
| 412 } | |
| 413 } | |
| 414 | |
| 415 // eRegI ereg, memory mem) %{ // emit_reg_mem | |
| 416 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) { | |
| 417 // There is no index & no scale, use form without SIB byte | |
| 418 if ((index == 0x4) && | |
| 419 (scale == 0) && (base != ESP_enc)) { | |
| 420 // If no displacement, mode is 0x0; unless base is [EBP] | |
| 421 if ( (displace == 0) && (base != EBP_enc) ) { | |
| 422 emit_rm(cbuf, 0x0, reg_encoding, base); | |
| 423 } | |
| 424 else { // If 8-bit displacement, mode 0x1 | |
| 425 if ((displace >= -128) && (displace <= 127) | |
| 426 && !(displace_is_oop) ) { | |
| 427 emit_rm(cbuf, 0x1, reg_encoding, base); | |
| 428 emit_d8(cbuf, displace); | |
| 429 } | |
| 430 else { // If 32-bit displacement | |
| 431 if (base == -1) { // Special flag for absolute address | |
| 432 emit_rm(cbuf, 0x0, reg_encoding, 0x5); | |
| 433 // (manual lies; no SIB needed here) | |
| 434 if ( displace_is_oop ) { | |
| 435 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1); | |
| 436 } else { | |
| 437 emit_d32 (cbuf, displace); | |
| 438 } | |
| 439 } | |
| 440 else { // Normal base + offset | |
| 441 emit_rm(cbuf, 0x2, reg_encoding, base); | |
| 442 if ( displace_is_oop ) { | |
| 443 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1); | |
| 444 } else { | |
| 445 emit_d32 (cbuf, displace); | |
| 446 } | |
| 447 } | |
| 448 } | |
| 449 } | |
| 450 } | |
| 451 else { // Else, encode with the SIB byte | |
| 452 // If no displacement, mode is 0x0; unless base is [EBP] | |
| 453 if (displace == 0 && (base != EBP_enc)) { // If no displacement | |
| 454 emit_rm(cbuf, 0x0, reg_encoding, 0x4); | |
| 455 emit_rm(cbuf, scale, index, base); | |
| 456 } | |
| 457 else { // If 8-bit displacement, mode 0x1 | |
| 458 if ((displace >= -128) && (displace <= 127) | |
| 459 && !(displace_is_oop) ) { | |
| 460 emit_rm(cbuf, 0x1, reg_encoding, 0x4); | |
| 461 emit_rm(cbuf, scale, index, base); | |
| 462 emit_d8(cbuf, displace); | |
| 463 } | |
| 464 else { // If 32-bit displacement | |
| 465 if (base == 0x04 ) { | |
| 466 emit_rm(cbuf, 0x2, reg_encoding, 0x4); | |
| 467 emit_rm(cbuf, scale, index, 0x04); | |
| 468 } else { | |
| 469 emit_rm(cbuf, 0x2, reg_encoding, 0x4); | |
| 470 emit_rm(cbuf, scale, index, base); | |
| 471 } | |
| 472 if ( displace_is_oop ) { | |
| 473 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1); | |
| 474 } else { | |
| 475 emit_d32 (cbuf, displace); | |
| 476 } | |
| 477 } | |
| 478 } | |
| 479 } | |
| 480 } | |
| 481 | |
| 482 | |
| 483 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) { | |
| 484 if( dst_encoding == src_encoding ) { | |
| 485 // reg-reg copy, use an empty encoding | |
| 486 } else { | |
| 487 emit_opcode( cbuf, 0x8B ); | |
| 488 emit_rm(cbuf, 0x3, dst_encoding, src_encoding ); | |
| 489 } | |
| 490 } | |
| 491 | |
| 4759 | 492 void emit_cmpfp_fixup(MacroAssembler& _masm) { |
| 493 Label exit; | |
| 494 __ jccb(Assembler::noParity, exit); | |
| 495 __ pushf(); | |
| 496 // | |
| 497 // comiss/ucomiss instructions set ZF,PF,CF flags and | |
| 498 // zero OF,AF,SF for NaN values. | |
| 499 // Fixup flags by zeroing ZF,PF so that compare of NaN | |
| 500 // values returns 'less than' result (CF is set). | |
| 501 // Leave the rest of flags unchanged. | |
| 502 // | |
| 503 // 7 6 5 4 3 2 1 0 | |
| 504 // |S|Z|r|A|r|P|r|C| (r - reserved bit) | |
| 505 // 0 0 1 0 1 0 1 1 (0x2B) | |
| 506 // | |
| 507 __ andl(Address(rsp, 0), 0xffffff2b); | |
| 508 __ popf(); | |
| 509 __ bind(exit); | |
| 510 } | |
| 511 | |
| 512 void emit_cmpfp3(MacroAssembler& _masm, Register dst) { | |
| 513 Label done; | |
| 514 __ movl(dst, -1); | |
| 515 __ jcc(Assembler::parity, done); | |
| 516 __ jcc(Assembler::below, done); | |
| 517 __ setb(Assembler::notEqual, dst); | |
| 518 __ movzbl(dst, dst); | |
| 519 __ bind(done); | |
| 0 | 520 } |
| 521 | |
| 522 | |
| 523 //============================================================================= | |
| 2008 | 524 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty; |
| 525 | |
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526 int Compile::ConstantTable::calculate_table_base_offset() const { |
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527 return 0; // absolute addressing, no offset |
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528 } |
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529 |
| 2008 | 530 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { |
| 531 // Empty encoding | |
| 532 } | |
| 533 | |
| 534 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { | |
| 535 return 0; | |
| 536 } | |
| 537 | |
| 538 #ifndef PRODUCT | |
| 539 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { | |
| 540 st->print("# MachConstantBaseNode (empty encoding)"); | |
| 541 } | |
| 542 #endif | |
| 543 | |
| 544 | |
| 545 //============================================================================= | |
| 0 | 546 #ifndef PRODUCT |
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547 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const { |
| 0 | 548 Compile* C = ra_->C; |
| 549 | |
| 550 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 551 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
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552 // Remove wordSize for return addr which is already pushed. |
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553 framesize -= wordSize; |
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554 |
| 0 | 555 if (C->need_stack_bang(framesize)) { |
| 556 framesize -= wordSize; | |
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557 st->print("# stack bang"); |
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558 st->print("\n\t"); |
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559 st->print("PUSH EBP\t# Save EBP"); |
| 0 | 560 if (framesize) { |
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561 st->print("\n\t"); |
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562 st->print("SUB ESP, #%d\t# Create frame",framesize); |
| 0 | 563 } |
| 564 } else { | |
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565 st->print("SUB ESP, #%d\t# Create frame",framesize); |
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566 st->print("\n\t"); |
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567 framesize -= wordSize; |
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568 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize); |
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569 } |
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570 |
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571 if (VerifyStackAtCalls) { |
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572 st->print("\n\t"); |
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573 framesize -= wordSize; |
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574 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize); |
| 0 | 575 } |
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576 |
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577 if( C->in_24_bit_fp_mode() ) { |
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578 st->print("\n\t"); |
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579 st->print("FLDCW \t# load 24 bit fpu control word"); |
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580 } |
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581 if (UseSSE >= 2 && VerifyFPU) { |
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582 st->print("\n\t"); |
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583 st->print("# verify FPU stack (must be clean on entry)"); |
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584 } |
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585 |
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586 #ifdef ASSERT |
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587 if (VerifyStackAtCalls) { |
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588 st->print("\n\t"); |
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589 st->print("# stack alignment check"); |
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590 } |
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591 #endif |
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592 st->cr(); |
| 0 | 593 } |
| 594 #endif | |
| 595 | |
| 596 | |
| 597 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 598 Compile* C = ra_->C; | |
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599 MacroAssembler _masm(&cbuf); |
| 0 | 600 |
| 601 int framesize = C->frame_slots() << LogBytesPerInt; | |
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602 |
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603 __ verified_entry(framesize, C->need_stack_bang(framesize), C->in_24_bit_fp_mode()); |
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604 |
| 1748 | 605 C->set_frame_complete(cbuf.insts_size()); |
| 0 | 606 |
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607 if (C->has_mach_constant_base_node()) { |
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608 // NOTE: We set the table base offset here because users might be |
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609 // emitted before MachConstantBaseNode. |
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610 Compile::ConstantTable& constant_table = C->constant_table(); |
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611 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); |
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612 } |
| 0 | 613 } |
| 614 | |
| 615 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { | |
| 616 return MachNode::size(ra_); // too many variables; just compute it the hard way | |
| 617 } | |
| 618 | |
| 619 int MachPrologNode::reloc() const { | |
| 620 return 0; // a large enough number | |
| 621 } | |
| 622 | |
| 623 //============================================================================= | |
| 624 #ifndef PRODUCT | |
| 625 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 626 Compile *C = ra_->C; | |
| 627 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 628 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 629 // Remove two words for return addr and rbp, | |
| 630 framesize -= 2*wordSize; | |
| 631 | |
| 632 if( C->in_24_bit_fp_mode() ) { | |
| 633 st->print("FLDCW standard control word"); | |
| 634 st->cr(); st->print("\t"); | |
| 635 } | |
| 636 if( framesize ) { | |
| 637 st->print("ADD ESP,%d\t# Destroy frame",framesize); | |
| 638 st->cr(); st->print("\t"); | |
| 639 } | |
| 640 st->print_cr("POPL EBP"); st->print("\t"); | |
| 641 if( do_polling() && C->is_method_compilation() ) { | |
| 642 st->print("TEST PollPage,EAX\t! Poll Safepoint"); | |
| 643 st->cr(); st->print("\t"); | |
| 644 } | |
| 645 } | |
| 646 #endif | |
| 647 | |
| 648 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 649 Compile *C = ra_->C; | |
| 650 | |
| 651 // If method set FPU control word, restore to standard control word | |
| 652 if( C->in_24_bit_fp_mode() ) { | |
| 653 MacroAssembler masm(&cbuf); | |
| 654 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 655 } | |
| 656 | |
| 657 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 658 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 659 // Remove two words for return addr and rbp, | |
| 660 framesize -= 2*wordSize; | |
| 661 | |
| 662 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here | |
| 663 | |
| 664 if( framesize >= 128 ) { | |
| 665 emit_opcode(cbuf, 0x81); // add SP, #framesize | |
| 666 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 667 emit_d32(cbuf, framesize); | |
| 668 } | |
| 669 else if( framesize ) { | |
| 670 emit_opcode(cbuf, 0x83); // add SP, #framesize | |
| 671 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 672 emit_d8(cbuf, framesize); | |
| 673 } | |
| 674 | |
| 675 emit_opcode(cbuf, 0x58 | EBP_enc); | |
| 676 | |
| 677 if( do_polling() && C->is_method_compilation() ) { | |
| 1748 | 678 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0); |
| 0 | 679 emit_opcode(cbuf,0x85); |
| 680 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX | |
| 681 emit_d32(cbuf, (intptr_t)os::get_polling_page()); | |
| 682 } | |
| 683 } | |
| 684 | |
| 685 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { | |
| 686 Compile *C = ra_->C; | |
| 687 // If method set FPU control word, restore to standard control word | |
| 688 int size = C->in_24_bit_fp_mode() ? 6 : 0; | |
| 689 if( do_polling() && C->is_method_compilation() ) size += 6; | |
| 690 | |
| 691 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 692 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 693 // Remove two words for return addr and rbp, | |
| 694 framesize -= 2*wordSize; | |
| 695 | |
| 696 size++; // popl rbp, | |
| 697 | |
| 698 if( framesize >= 128 ) { | |
| 699 size += 6; | |
| 700 } else { | |
| 701 size += framesize ? 3 : 0; | |
| 702 } | |
| 703 return size; | |
| 704 } | |
| 705 | |
| 706 int MachEpilogNode::reloc() const { | |
| 707 return 0; // a large enough number | |
| 708 } | |
| 709 | |
| 710 const Pipeline * MachEpilogNode::pipeline() const { | |
| 711 return MachNode::pipeline_class(); | |
| 712 } | |
| 713 | |
| 714 int MachEpilogNode::safepoint_offset() const { return 0; } | |
| 715 | |
| 716 //============================================================================= | |
| 717 | |
| 718 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack }; | |
| 719 static enum RC rc_class( OptoReg::Name reg ) { | |
| 720 | |
| 721 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
| 722 if (OptoReg::is_stack(reg)) return rc_stack; | |
| 723 | |
| 724 VMReg r = OptoReg::as_VMReg(reg); | |
| 725 if (r->is_Register()) return rc_int; | |
| 726 if (r->is_FloatRegister()) { | |
| 727 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode"); | |
| 728 return rc_float; | |
| 729 } | |
| 730 assert(r->is_XMMRegister(), "must be"); | |
| 731 return rc_xmm; | |
| 732 } | |
| 733 | |
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734 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg, |
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735 int opcode, const char *op_str, int size, outputStream* st ) { |
| 0 | 736 if( cbuf ) { |
| 737 emit_opcode (*cbuf, opcode ); | |
| 738 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, false); | |
| 739 #ifndef PRODUCT | |
| 740 } else if( !do_size ) { | |
|
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741 if( size != 0 ) st->print("\n\t"); |
| 0 | 742 if( opcode == 0x8B || opcode == 0x89 ) { // MOV |
|
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743 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset); |
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744 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]); |
| 0 | 745 } else { // FLD, FST, PUSH, POP |
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746 st->print("%s [ESP + #%d]",op_str,offset); |
| 0 | 747 } |
| 748 #endif | |
| 749 } | |
| 750 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
| 751 return size+3+offset_size; | |
| 752 } | |
| 753 | |
| 754 // Helper for XMM registers. Extra opcode bits, limited syntax. | |
| 755 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load, | |
|
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756 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) { |
| 4759 | 757 if (cbuf) { |
| 758 MacroAssembler _masm(cbuf); | |
| 759 if (reg_lo+1 == reg_hi) { // double move? | |
| 760 if (is_load) { | |
| 761 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset)); | |
| 762 } else { | |
| 763 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo])); | |
| 764 } | |
| 0 | 765 } else { |
| 4759 | 766 if (is_load) { |
| 767 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset)); | |
| 768 } else { | |
| 769 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo])); | |
| 770 } | |
| 0 | 771 } |
| 772 #ifndef PRODUCT | |
| 4759 | 773 } else if (!do_size) { |
| 774 if (size != 0) st->print("\n\t"); | |
| 775 if (reg_lo+1 == reg_hi) { // double move? | |
| 776 if (is_load) st->print("%s %s,[ESP + #%d]", | |
| 777 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD", | |
| 778 Matcher::regName[reg_lo], offset); | |
| 779 else st->print("MOVSD [ESP + #%d],%s", | |
| 780 offset, Matcher::regName[reg_lo]); | |
| 0 | 781 } else { |
| 4759 | 782 if (is_load) st->print("MOVSS %s,[ESP + #%d]", |
| 783 Matcher::regName[reg_lo], offset); | |
| 784 else st->print("MOVSS [ESP + #%d],%s", | |
| 785 offset, Matcher::regName[reg_lo]); | |
| 0 | 786 } |
| 787 #endif | |
| 788 } | |
| 789 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
| 4759 | 790 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes. |
| 0 | 791 return size+5+offset_size; |
| 792 } | |
| 793 | |
| 794 | |
| 795 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, | |
|
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796 int src_hi, int dst_hi, int size, outputStream* st ) { |
| 4759 | 797 if (cbuf) { |
| 798 MacroAssembler _masm(cbuf); | |
| 799 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move? | |
| 800 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]), | |
| 801 as_XMMRegister(Matcher::_regEncode[src_lo])); | |
| 802 } else { | |
| 803 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]), | |
| 804 as_XMMRegister(Matcher::_regEncode[src_lo])); | |
| 805 } | |
| 0 | 806 #ifndef PRODUCT |
| 4759 | 807 } else if (!do_size) { |
| 808 if (size != 0) st->print("\n\t"); | |
| 809 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers | |
| 810 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move? | |
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811 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 812 } else { |
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813 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 814 } |
| 4759 | 815 } else { |
| 0 | 816 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move? |
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817 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 818 } else { |
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819 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); |
| 0 | 820 } |
| 4759 | 821 } |
| 0 | 822 #endif |
| 823 } | |
| 4759 | 824 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes. |
| 825 // Only MOVAPS SSE prefix uses 1 byte. | |
| 826 int sz = 4; | |
| 827 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) && | |
| 828 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3; | |
| 829 return size + sz; | |
| 0 | 830 } |
| 831 | |
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832 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
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833 int src_hi, int dst_hi, int size, outputStream* st ) { |
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834 // 32-bit |
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835 if (cbuf) { |
| 4759 | 836 MacroAssembler _masm(cbuf); |
| 837 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]), | |
| 838 as_Register(Matcher::_regEncode[src_lo])); | |
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839 #ifndef PRODUCT |
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840 } else if (!do_size) { |
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841 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]); |
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842 #endif |
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843 } |
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844 return 4; |
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845 } |
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846 |
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847 |
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848 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, |
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849 int src_hi, int dst_hi, int size, outputStream* st ) { |
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850 // 32-bit |
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851 if (cbuf) { |
| 4759 | 852 MacroAssembler _masm(cbuf); |
| 853 __ movdl(as_Register(Matcher::_regEncode[dst_lo]), | |
| 854 as_XMMRegister(Matcher::_regEncode[src_lo])); | |
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855 #ifndef PRODUCT |
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856 } else if (!do_size) { |
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857 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]); |
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858 #endif |
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859 } |
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860 return 4; |
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861 } |
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862 |
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863 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) { |
| 0 | 864 if( cbuf ) { |
| 865 emit_opcode(*cbuf, 0x8B ); | |
| 866 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] ); | |
| 867 #ifndef PRODUCT | |
| 868 } else if( !do_size ) { | |
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869 if( size != 0 ) st->print("\n\t"); |
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870 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]); |
| 0 | 871 #endif |
| 872 } | |
| 873 return size+2; | |
| 874 } | |
| 875 | |
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876 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi, |
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877 int offset, int size, outputStream* st ) { |
| 0 | 878 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there |
| 879 if( cbuf ) { | |
| 880 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it) | |
| 881 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] ); | |
| 882 #ifndef PRODUCT | |
| 883 } else if( !do_size ) { | |
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884 if( size != 0 ) st->print("\n\t"); |
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885 st->print("FLD %s",Matcher::regName[src_lo]); |
| 0 | 886 #endif |
| 887 } | |
| 888 size += 2; | |
| 889 } | |
| 890 | |
| 891 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/; | |
| 892 const char *op_str; | |
| 893 int op; | |
| 894 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store? | |
| 895 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D "; | |
| 896 op = 0xDD; | |
| 897 } else { // 32-bit store | |
| 898 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S "; | |
| 899 op = 0xD9; | |
| 900 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" ); | |
| 901 } | |
| 902 | |
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903 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st); |
| 0 | 904 } |
| 905 | |
| 906 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const { | |
| 907 // Get registers to move | |
| 908 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
| 909 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
| 910 OptoReg::Name dst_second = ra_->get_reg_second(this ); | |
| 911 OptoReg::Name dst_first = ra_->get_reg_first(this ); | |
| 912 | |
| 913 enum RC src_second_rc = rc_class(src_second); | |
| 914 enum RC src_first_rc = rc_class(src_first); | |
| 915 enum RC dst_second_rc = rc_class(dst_second); | |
| 916 enum RC dst_first_rc = rc_class(dst_first); | |
| 917 | |
| 918 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); | |
| 919 | |
| 920 // Generate spill code! | |
| 921 int size = 0; | |
| 922 | |
| 923 if( src_first == dst_first && src_second == dst_second ) | |
| 924 return size; // Self copy, no move | |
| 925 | |
| 926 // -------------------------------------- | |
| 927 // Check for mem-mem move. push/pop to move. | |
| 928 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { | |
| 929 if( src_second == dst_first ) { // overlapping stack copy ranges | |
| 930 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" ); | |
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931 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st); |
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932 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st); |
| 0 | 933 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits |
| 934 } | |
| 935 // move low bits | |
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936 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st); |
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937 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st); |
| 0 | 938 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits |
|
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939 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st); |
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940 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st); |
| 0 | 941 } |
| 942 return size; | |
| 943 } | |
| 944 | |
| 945 // -------------------------------------- | |
| 946 // Check for integer reg-reg copy | |
| 947 if( src_first_rc == rc_int && dst_first_rc == rc_int ) | |
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948 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st); |
| 0 | 949 |
| 950 // Check for integer store | |
| 951 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) | |
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952 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st); |
| 0 | 953 |
| 954 // Check for integer load | |
| 955 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) | |
|
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956 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st); |
| 0 | 957 |
|
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958 // Check for integer reg-xmm reg copy |
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959 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) { |
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960 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad), |
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961 "no 64 bit integer-float reg moves" ); |
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962 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); |
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963 } |
| 0 | 964 // -------------------------------------- |
| 965 // Check for float reg-reg copy | |
| 966 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { | |
| 967 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) || | |
| 968 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" ); | |
| 969 if( cbuf ) { | |
| 970 | |
| 971 // Note the mucking with the register encode to compensate for the 0/1 | |
| 972 // indexing issue mentioned in a comment in the reg_def sections | |
| 973 // for FPR registers many lines above here. | |
| 974 | |
| 975 if( src_first != FPR1L_num ) { | |
| 976 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i) | |
| 977 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 ); | |
| 978 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i) | |
| 979 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] ); | |
| 980 } else { | |
| 981 emit_opcode (*cbuf, 0xDD ); // FST ST(i) | |
| 982 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 ); | |
| 983 } | |
| 984 #ifndef PRODUCT | |
| 985 } else if( !do_size ) { | |
| 986 if( size != 0 ) st->print("\n\t"); | |
| 987 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]); | |
| 988 else st->print( "FST %s", Matcher::regName[dst_first]); | |
| 989 #endif | |
| 990 } | |
| 991 return size + ((src_first != FPR1L_num) ? 2+2 : 2); | |
| 992 } | |
| 993 | |
| 994 // Check for float store | |
| 995 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { | |
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996 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st); |
| 0 | 997 } |
| 998 | |
| 999 // Check for float load | |
| 1000 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { | |
| 1001 int offset = ra_->reg2offset(src_first); | |
| 1002 const char *op_str; | |
| 1003 int op; | |
| 1004 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load? | |
| 1005 op_str = "FLD_D"; | |
| 1006 op = 0xDD; | |
| 1007 } else { // 32-bit load | |
| 1008 op_str = "FLD_S"; | |
| 1009 op = 0xD9; | |
| 1010 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" ); | |
| 1011 } | |
| 1012 if( cbuf ) { | |
| 1013 emit_opcode (*cbuf, op ); | |
| 1014 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, false); | |
| 1015 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i) | |
| 1016 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] ); | |
| 1017 #ifndef PRODUCT | |
| 1018 } else if( !do_size ) { | |
| 1019 if( size != 0 ) st->print("\n\t"); | |
| 1020 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]); | |
| 1021 #endif | |
| 1022 } | |
| 1023 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); | |
| 1024 return size + 3+offset_size+2; | |
| 1025 } | |
| 1026 | |
| 1027 // Check for xmm reg-reg copy | |
| 1028 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) { | |
| 1029 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) || | |
| 1030 (src_first+1 == src_second && dst_first+1 == dst_second), | |
| 1031 "no non-adjacent float-moves" ); | |
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1032 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); |
| 0 | 1033 } |
| 1034 | |
|
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1035 // Check for xmm reg-integer reg copy |
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1036 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) { |
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1037 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad), |
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1038 "no 64 bit float-integer reg moves" ); |
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1039 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); |
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1040 } |
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1041 |
| 0 | 1042 // Check for xmm store |
| 1043 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) { | |
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1044 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st); |
| 0 | 1045 } |
| 1046 | |
| 1047 // Check for float xmm load | |
| 1048 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) { | |
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1049 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st); |
| 0 | 1050 } |
| 1051 | |
| 1052 // Copy from float reg to xmm reg | |
| 1053 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) { | |
| 1054 // copy to the top of stack from floating point reg | |
| 1055 // and use LEA to preserve flags | |
| 1056 if( cbuf ) { | |
| 1057 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8] | |
| 1058 emit_rm(*cbuf, 0x1, ESP_enc, 0x04); | |
| 1059 emit_rm(*cbuf, 0x0, 0x04, ESP_enc); | |
| 1060 emit_d8(*cbuf,0xF8); | |
| 1061 #ifndef PRODUCT | |
| 1062 } else if( !do_size ) { | |
| 1063 if( size != 0 ) st->print("\n\t"); | |
| 1064 st->print("LEA ESP,[ESP-8]"); | |
| 1065 #endif | |
| 1066 } | |
| 1067 size += 4; | |
| 1068 | |
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1069 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st); |
| 0 | 1070 |
| 1071 // Copy from the temp memory to the xmm reg. | |
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1072 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st); |
| 0 | 1073 |
| 1074 if( cbuf ) { | |
| 1075 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8] | |
| 1076 emit_rm(*cbuf, 0x1, ESP_enc, 0x04); | |
| 1077 emit_rm(*cbuf, 0x0, 0x04, ESP_enc); | |
| 1078 emit_d8(*cbuf,0x08); | |
| 1079 #ifndef PRODUCT | |
| 1080 } else if( !do_size ) { | |
| 1081 if( size != 0 ) st->print("\n\t"); | |
| 1082 st->print("LEA ESP,[ESP+8]"); | |
| 1083 #endif | |
| 1084 } | |
| 1085 size += 4; | |
| 1086 return size; | |
| 1087 } | |
| 1088 | |
| 1089 assert( size > 0, "missed a case" ); | |
| 1090 | |
| 1091 // -------------------------------------------------------------------- | |
| 1092 // Check for second bits still needing moving. | |
| 1093 if( src_second == dst_second ) | |
| 1094 return size; // Self copy; no move | |
| 1095 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); | |
| 1096 | |
| 1097 // Check for second word int-int move | |
| 1098 if( src_second_rc == rc_int && dst_second_rc == rc_int ) | |
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1099 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st); |
| 0 | 1100 |
| 1101 // Check for second word integer store | |
| 1102 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) | |
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1103 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st); |
| 0 | 1104 |
| 1105 // Check for second word integer load | |
| 1106 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) | |
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1107 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st); |
| 0 | 1108 |
| 1109 | |
| 1110 Unimplemented(); | |
| 1111 } | |
| 1112 | |
| 1113 #ifndef PRODUCT | |
| 4950 | 1114 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const { |
| 0 | 1115 implementation( NULL, ra_, false, st ); |
| 1116 } | |
| 1117 #endif | |
| 1118 | |
| 1119 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1120 implementation( &cbuf, ra_, false, NULL ); | |
| 1121 } | |
| 1122 | |
| 1123 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { | |
| 1124 return implementation( NULL, ra_, true, NULL ); | |
| 1125 } | |
| 1126 | |
| 1127 | |
| 1128 //============================================================================= | |
| 1129 #ifndef PRODUCT | |
| 1130 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 1131 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1132 int reg = ra_->get_reg_first(this); | |
| 1133 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset); | |
| 1134 } | |
| 1135 #endif | |
| 1136 | |
| 1137 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1138 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1139 int reg = ra_->get_encode(this); | |
| 1140 if( offset >= 128 ) { | |
| 1141 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1142 emit_rm(cbuf, 0x2, reg, 0x04); | |
| 1143 emit_rm(cbuf, 0x0, 0x04, ESP_enc); | |
| 1144 emit_d32(cbuf, offset); | |
| 1145 } | |
| 1146 else { | |
| 1147 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1148 emit_rm(cbuf, 0x1, reg, 0x04); | |
| 1149 emit_rm(cbuf, 0x0, 0x04, ESP_enc); | |
| 1150 emit_d8(cbuf, offset); | |
| 1151 } | |
| 1152 } | |
| 1153 | |
| 1154 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { | |
| 1155 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1156 if( offset >= 128 ) { | |
| 1157 return 7; | |
| 1158 } | |
| 1159 else { | |
| 1160 return 4; | |
| 1161 } | |
| 1162 } | |
| 1163 | |
| 1164 //============================================================================= | |
| 1165 | |
| 1166 // emit call stub, compiled java to interpreter | |
| 1167 void emit_java_to_interp(CodeBuffer &cbuf ) { | |
| 1168 // Stub is fixed up when the corresponding call is converted from calling | |
| 1169 // compiled code to calling interpreted code. | |
| 1170 // mov rbx,0 | |
| 1171 // jmp -1 | |
| 1172 | |
| 1748 | 1173 address mark = cbuf.insts_mark(); // get mark within main instrs section |
| 1174 | |
| 1175 // Note that the code buffer's insts_mark is always relative to insts. | |
| 0 | 1176 // That's why we must use the macroassembler to generate a stub. |
| 1177 MacroAssembler _masm(&cbuf); | |
| 1178 | |
| 1179 address base = | |
| 1180 __ start_a_stub(Compile::MAX_stubs_size); | |
| 1181 if (base == NULL) return; // CodeBuffer::expand failed | |
| 1182 // static stub relocation stores the instruction address of the call | |
| 1183 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32); | |
| 1184 // static stub relocation also tags the methodOop in the code-stream. | |
| 1185 __ movoop(rbx, (jobject)NULL); // method is zapped till fixup time | |
| 304 | 1186 // This is recognized as unresolved by relocs/nativeInst/ic code |
| 1187 __ jump(RuntimeAddress(__ pc())); | |
| 0 | 1188 |
| 1189 __ end_a_stub(); | |
| 1748 | 1190 // Update current stubs pointer and restore insts_end. |
| 0 | 1191 } |
| 1192 // size of call stub, compiled java to interpretor | |
| 1193 uint size_java_to_interp() { | |
| 1194 return 10; // movl; jmp | |
| 1195 } | |
| 1196 // relocation entries for call stub, compiled java to interpretor | |
| 1197 uint reloc_java_to_interp() { | |
| 1198 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call | |
| 1199 } | |
| 1200 | |
| 1201 //============================================================================= | |
| 1202 #ifndef PRODUCT | |
| 1203 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { | |
| 1204 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check"); | |
| 1205 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub"); | |
| 1206 st->print_cr("\tNOP"); | |
| 1207 st->print_cr("\tNOP"); | |
| 1208 if( !OptoBreakpoint ) | |
| 1209 st->print_cr("\tNOP"); | |
| 1210 } | |
| 1211 #endif | |
| 1212 | |
| 1213 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
| 1214 MacroAssembler masm(&cbuf); | |
| 1215 #ifdef ASSERT | |
| 1748 | 1216 uint insts_size = cbuf.insts_size(); |
| 0 | 1217 #endif |
| 304 | 1218 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes())); |
| 0 | 1219 masm.jump_cc(Assembler::notEqual, |
| 1220 RuntimeAddress(SharedRuntime::get_ic_miss_stub())); | |
| 1221 /* WARNING these NOPs are critical so that verified entry point is properly | |
| 1222 aligned for patching by NativeJump::patch_verified_entry() */ | |
| 1223 int nops_cnt = 2; | |
| 1224 if( !OptoBreakpoint ) // Leave space for int3 | |
| 1225 nops_cnt += 1; | |
| 1226 masm.nop(nops_cnt); | |
| 1227 | |
| 1748 | 1228 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node"); |
| 0 | 1229 } |
| 1230 | |
| 1231 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { | |
| 1232 return OptoBreakpoint ? 11 : 12; | |
| 1233 } | |
| 1234 | |
| 1235 | |
| 1236 //============================================================================= | |
| 1237 uint size_exception_handler() { | |
| 1238 // NativeCall instruction size is the same as NativeJump. | |
| 1239 // exception handler starts out as jump and can be patched to | |
| 1240 // a call be deoptimization. (4932387) | |
| 1241 // Note that this value is also credited (in output.cpp) to | |
| 1242 // the size of the code section. | |
| 1243 return NativeJump::instruction_size; | |
| 1244 } | |
| 1245 | |
| 1246 // Emit exception handler code. Stuff framesize into a register | |
| 1247 // and call a VM stub routine. | |
| 1248 int emit_exception_handler(CodeBuffer& cbuf) { | |
| 1249 | |
| 1748 | 1250 // Note that the code buffer's insts_mark is always relative to insts. |
| 0 | 1251 // That's why we must use the macroassembler to generate a handler. |
| 1252 MacroAssembler _masm(&cbuf); | |
| 1253 address base = | |
| 1254 __ start_a_stub(size_exception_handler()); | |
| 1255 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1256 int offset = __ offset(); | |
| 1748 | 1257 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point())); |
| 0 | 1258 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); |
| 1259 __ end_a_stub(); | |
| 1260 return offset; | |
| 1261 } | |
| 1262 | |
| 1263 uint size_deopt_handler() { | |
| 1264 // NativeCall instruction size is the same as NativeJump. | |
| 1265 // exception handler starts out as jump and can be patched to | |
| 1266 // a call be deoptimization. (4932387) | |
| 1267 // Note that this value is also credited (in output.cpp) to | |
| 1268 // the size of the code section. | |
| 1269 return 5 + NativeJump::instruction_size; // pushl(); jmp; | |
| 1270 } | |
| 1271 | |
| 1272 // Emit deopt handler code. | |
| 1273 int emit_deopt_handler(CodeBuffer& cbuf) { | |
| 1274 | |
| 1748 | 1275 // Note that the code buffer's insts_mark is always relative to insts. |
| 0 | 1276 // That's why we must use the macroassembler to generate a handler. |
| 1277 MacroAssembler _masm(&cbuf); | |
| 1278 address base = | |
| 1279 __ start_a_stub(size_exception_handler()); | |
| 1280 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1281 int offset = __ offset(); | |
| 1282 InternalAddress here(__ pc()); | |
| 1283 __ pushptr(here.addr()); | |
| 1284 | |
| 1285 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); | |
| 1286 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); | |
| 1287 __ end_a_stub(); | |
| 1288 return offset; | |
| 1289 } | |
| 1290 | |
| 1291 | |
|
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1292 const bool Matcher::match_rule_supported(int opcode) { |
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1293 if (!has_match_rule(opcode)) |
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1294 return false; |
|
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6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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|
1295 |
|
5934
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7152957: VM crashes with assert(false) failed: bad AD file
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|
1296 switch (opcode) { |
|
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7152957: VM crashes with assert(false) failed: bad AD file
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|
1297 case Op_PopCountI: |
|
61b82be3b1ff
7152957: VM crashes with assert(false) failed: bad AD file
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changeset
|
1298 case Op_PopCountL: |
|
61b82be3b1ff
7152957: VM crashes with assert(false) failed: bad AD file
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|
1299 if (!UsePopCountInstruction) |
|
61b82be3b1ff
7152957: VM crashes with assert(false) failed: bad AD file
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diff
changeset
|
1300 return false; |
|
61b82be3b1ff
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diff
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|
1301 break; |
|
61b82be3b1ff
7152957: VM crashes with assert(false) failed: bad AD file
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diff
changeset
|
1302 } |
|
61b82be3b1ff
7152957: VM crashes with assert(false) failed: bad AD file
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diff
changeset
|
1303 |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
1304 return true; // Per default match rules are supported. |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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|
1305 } |
|
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6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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|
1306 |
| 0 | 1307 int Matcher::regnum_to_fpu_offset(int regnum) { |
| 1308 return regnum - 32; // The FP registers are in the second chunk | |
| 1309 } | |
| 1310 | |
| 1311 // This is UltraSparc specific, true just means we have fast l2f conversion | |
| 1312 const bool Matcher::convL2FSupported(void) { | |
| 1313 return true; | |
| 1314 } | |
| 1315 | |
| 1316 // Vector width in bytes | |
| 1317 const uint Matcher::vector_width_in_bytes(void) { | |
| 1318 return UseSSE >= 2 ? 8 : 0; | |
| 1319 } | |
| 1320 | |
| 1321 // Vector ideal reg | |
| 1322 const uint Matcher::vector_ideal_reg(void) { | |
| 1323 return Op_RegD; | |
| 1324 } | |
| 1325 | |
| 1326 // Is this branch offset short enough that a short branch can be used? | |
| 1327 // | |
| 1328 // NOTE: If the platform does not provide any short branch variants, then | |
| 1329 // this method should return false for offset 0. | |
| 3851 | 1330 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { |
| 1331 // The passed offset is relative to address of the branch. | |
| 1332 // On 86 a branch displacement is calculated relative to address | |
| 1333 // of a next instruction. | |
| 1334 offset -= br_size; | |
| 1335 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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changeset
|
1336 // the short version of jmpConUCF2 contains multiple branches, |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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|
1337 // making the reach slightly less |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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|
1338 if (rule == jmpConUCF2_rule) |
|
4d9884b01ba6
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|
1339 return (-126 <= offset && offset <= 125); |
| 0 | 1340 return (-128 <= offset && offset <= 127); |
| 1341 } | |
| 1342 | |
| 1343 const bool Matcher::isSimpleConstant64(jlong value) { | |
| 1344 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
| 1345 return false; | |
| 1346 } | |
| 1347 | |
| 1348 // The ecx parameter to rep stos for the ClearArray node is in dwords. | |
| 1349 const bool Matcher::init_array_count_is_in_bytes = false; | |
| 1350 | |
| 1351 // Threshold size for cleararray. | |
| 1352 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
| 1353 | |
| 4047 | 1354 // Needs 2 CMOV's for longs. |
| 1355 const int Matcher::long_cmove_cost() { return 1; } | |
| 1356 | |
| 1357 // No CMOVF/CMOVD with SSE/SSE2 | |
| 1358 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; } | |
| 1359 | |
| 0 | 1360 // Should the Matcher clone shifts on addressing modes, expecting them to |
| 1361 // be subsumed into complex addressing expressions or compute them into | |
| 1362 // registers? True for Intel but false for most RISCs | |
| 1363 const bool Matcher::clone_shift_expressions = true; | |
| 1364 | |
|
2401
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7029017: Additional architecture support for c2 compiler
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|
1365 // Do we need to mask the count passed to shift instructions or does |
|
7e88bdae86ec
7029017: Additional architecture support for c2 compiler
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diff
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|
1366 // the cpu only look at the lower 5/6 bits anyway? |
|
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|
1367 const bool Matcher::need_masked_shift_count = false; |
|
7e88bdae86ec
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|
1368 |
|
1575
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diff
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|
1369 bool Matcher::narrow_oop_use_complex_address() { |
|
3657cb01ffc5
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|
1370 ShouldNotCallThis(); |
|
3657cb01ffc5
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diff
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|
1371 return true; |
|
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diff
changeset
|
1372 } |
|
3657cb01ffc5
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diff
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|
1373 |
|
3657cb01ffc5
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kvn
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1567
diff
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|
1374 |
| 0 | 1375 // Is it better to copy float constants, or load them directly from memory? |
| 1376 // Intel can load a float constant from a direct address, requiring no | |
| 1377 // extra registers. Most RISCs will have to materialize an address into a | |
| 1378 // register first, so they would do better to copy the constant from stack. | |
| 1379 const bool Matcher::rematerialize_float_constants = true; | |
| 1380 | |
| 1381 // If CPU can load and store mis-aligned doubles directly then no fixup is | |
| 1382 // needed. Else we split the double into 2 integer pieces and move it | |
| 1383 // piece-by-piece. Only happens when passing doubles into C code as the | |
| 1384 // Java calling convention forces doubles to be aligned. | |
| 1385 const bool Matcher::misaligned_doubles_ok = true; | |
| 1386 | |
| 1387 | |
| 1388 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { | |
| 1389 // Get the memory operand from the node | |
| 1390 uint numopnds = node->num_opnds(); // Virtual call for number of operands | |
| 1391 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far | |
| 1392 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" ); | |
| 1393 uint opcnt = 1; // First operand | |
| 1394 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand | |
| 1395 while( idx >= skipped+num_edges ) { | |
| 1396 skipped += num_edges; | |
| 1397 opcnt++; // Bump operand count | |
| 1398 assert( opcnt < numopnds, "Accessing non-existent operand" ); | |
| 1399 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand | |
| 1400 } | |
| 1401 | |
| 1402 MachOper *memory = node->_opnds[opcnt]; | |
| 1403 MachOper *new_memory = NULL; | |
| 1404 switch (memory->opcode()) { | |
| 1405 case DIRECT: | |
| 1406 case INDOFFSET32X: | |
| 1407 // No transformation necessary. | |
| 1408 return; | |
| 1409 case INDIRECT: | |
| 1410 new_memory = new (C) indirect_win95_safeOper( ); | |
| 1411 break; | |
| 1412 case INDOFFSET8: | |
| 1413 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1414 break; | |
| 1415 case INDOFFSET32: | |
| 1416 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1417 break; | |
| 1418 case INDINDEXOFFSET: | |
| 1419 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0)); | |
| 1420 break; | |
| 1421 case INDINDEXSCALE: | |
| 1422 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale()); | |
| 1423 break; | |
| 1424 case INDINDEXSCALEOFFSET: | |
| 1425 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0)); | |
| 1426 break; | |
| 1427 case LOAD_LONG_INDIRECT: | |
| 1428 case LOAD_LONG_INDOFFSET32: | |
| 1429 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI} | |
| 1430 return; | |
| 1431 default: | |
| 1432 assert(false, "unexpected memory operand in pd_implicit_null_fixup()"); | |
| 1433 return; | |
| 1434 } | |
| 1435 node->_opnds[opcnt] = new_memory; | |
| 1436 } | |
| 1437 | |
| 1438 // Advertise here if the CPU requires explicit rounding operations | |
| 1439 // to implement the UseStrictFP mode. | |
| 1440 const bool Matcher::strict_fp_requires_explicit_rounding = true; | |
| 1441 | |
|
1274
2883969d09e7
6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
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1209
diff
changeset
|
1442 // Are floats conerted to double when stored to stack during deoptimization? |
|
2883969d09e7
6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
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1209
diff
changeset
|
1443 // On x32 it is stored with convertion only when FPU is used for floats. |
|
2883969d09e7
6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents:
1209
diff
changeset
|
1444 bool Matcher::float_in_double() { return (UseSSE == 0); } |
|
2883969d09e7
6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
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1209
diff
changeset
|
1445 |
| 0 | 1446 // Do ints take an entire long register or just half? |
| 1447 const bool Matcher::int_in_long = false; | |
| 1448 | |
| 1449 // Return whether or not this register is ever used as an argument. This | |
| 1450 // function is used on startup to build the trampoline stubs in generateOptoStub. | |
| 1451 // Registers not mentioned will be killed by the VM call in the trampoline, and | |
| 1452 // arguments in those registers not be available to the callee. | |
| 1453 bool Matcher::can_be_java_arg( int reg ) { | |
| 1454 if( reg == ECX_num || reg == EDX_num ) return true; | |
| 1455 if( (reg == XMM0a_num || reg == XMM1a_num) && UseSSE>=1 ) return true; | |
| 1456 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true; | |
| 1457 return false; | |
| 1458 } | |
| 1459 | |
| 1460 bool Matcher::is_spillable_arg( int reg ) { | |
| 1461 return can_be_java_arg(reg); | |
| 1462 } | |
| 1463 | |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1464 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1465 // Use hardware integer DIV instruction when |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1466 // it is faster than a code which use multiply. |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1467 // Only when constant divisor fits into 32 bit |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1468 // (min_jint is excluded to get only correct |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1469 // positive 32 bit values from negative). |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1470 return VM_Version::has_fast_idiv() && |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1471 (divisor == (int)divisor && divisor != min_jint); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1472 } |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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diff
changeset
|
1473 |
| 0 | 1474 // Register for DIVI projection of divmodI |
| 1475 RegMask Matcher::divI_proj_mask() { | |
|
4121
db2e64ca2d5a
7090968: Allow adlc register class to depend on runtime conditions
roland
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4114
diff
changeset
|
1476 return EAX_REG_mask(); |
| 0 | 1477 } |
| 1478 | |
| 1479 // Register for MODI projection of divmodI | |
| 1480 RegMask Matcher::modI_proj_mask() { | |
|
4121
db2e64ca2d5a
7090968: Allow adlc register class to depend on runtime conditions
roland
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4114
diff
changeset
|
1481 return EDX_REG_mask(); |
| 0 | 1482 } |
| 1483 | |
| 1484 // Register for DIVL projection of divmodL | |
| 1485 RegMask Matcher::divL_proj_mask() { | |
| 1486 ShouldNotReachHere(); | |
| 1487 return RegMask(); | |
| 1488 } | |
| 1489 | |
| 1490 // Register for MODL projection of divmodL | |
| 1491 RegMask Matcher::modL_proj_mask() { | |
| 1492 ShouldNotReachHere(); | |
| 1493 return RegMask(); | |
| 1494 } | |
| 1495 | |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
1496 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
|
4121
db2e64ca2d5a
7090968: Allow adlc register class to depend on runtime conditions
roland
parents:
4114
diff
changeset
|
1497 return EBP_REG_mask(); |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
1498 } |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
1499 |
|
1209
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
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parents:
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diff
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|
1500 // Returns true if the high 32 bits of the value is known to be zero. |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
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parents:
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diff
changeset
|
1501 bool is_operand_hi32_zero(Node* n) { |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
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parents:
1137
diff
changeset
|
1502 int opc = n->Opcode(); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
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parents:
1137
diff
changeset
|
1503 if (opc == Op_LoadUI2L) { |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
1504 return true; |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
1505 } |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
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parents:
1137
diff
changeset
|
1506 if (opc == Op_AndL) { |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
1507 Node* o2 = n->in(2); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
1137
diff
changeset
|
1508 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) { |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
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parents:
1137
diff
changeset
|
1509 return true; |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
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parents:
1137
diff
changeset
|
1510 } |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
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diff
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|
1511 } |
|
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
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|
1512 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) { |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
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|
1513 return true; |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents:
1748
diff
changeset
|
1514 } |
|
1209
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
parents:
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diff
changeset
|
1515 return false; |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
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parents:
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diff
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|
1516 } |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
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parents:
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|
1517 |
| 0 | 1518 %} |
| 1519 | |
| 1520 //----------ENCODING BLOCK----------------------------------------------------- | |
| 1521 // This block specifies the encoding classes used by the compiler to output | |
| 1522 // byte streams. Encoding classes generate functions which are called by | |
| 1523 // Machine Instruction Nodes in order to generate the bit encoding of the | |
| 1524 // instruction. Operands specify their base encoding interface with the | |
| 1525 // interface keyword. There are currently supported four interfaces, | |
| 1526 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an | |
| 1527 // operand to generate a function which returns its register number when | |
| 1528 // queried. CONST_INTER causes an operand to generate a function which | |
| 1529 // returns the value of the constant when queried. MEMORY_INTER causes an | |
| 1530 // operand to generate four functions which return the Base Register, the | |
| 1531 // Index Register, the Scale Value, and the Offset Value of the operand when | |
| 1532 // queried. COND_INTER causes an operand to generate six functions which | |
| 1533 // return the encoding code (ie - encoding bits for the instruction) | |
| 1534 // associated with each basic boolean condition for a conditional instruction. | |
| 1535 // Instructions specify two basic values for encoding. They use the | |
| 1536 // ins_encode keyword to specify their encoding class (which must be one of | |
| 1537 // the class names specified in the encoding block), and they use the | |
| 1538 // opcode keyword to specify, in order, their primary, secondary, and | |
| 1539 // tertiary opcode. Only the opcode sections which a particular instruction | |
| 1540 // needs for encoding need to be specified. | |
| 1541 encode %{ | |
| 1542 // Build emit functions for each basic byte or larger field in the intel | |
| 1543 // encoding scheme (opcode, rm, sib, immediate), and call them from C++ | |
| 1544 // code in the enc_class source block. Emit functions will live in the | |
| 1545 // main source block for now. In future, we can generalize this by | |
| 1546 // adding a syntax that specifies the sizes of fields in an order, | |
| 1547 // so that the adlc can build the emit functions automagically | |
|
643
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1548 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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parents:
624
diff
changeset
|
1549 // Emit primary opcode |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1550 enc_class OpcP %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
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diff
changeset
|
1551 emit_opcode(cbuf, $primary); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1552 %} |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1553 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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parents:
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diff
changeset
|
1554 // Emit secondary opcode |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
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diff
changeset
|
1555 enc_class OpcS %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
1556 emit_opcode(cbuf, $secondary); |
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1557 %} |
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1558 |
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1559 // Emit opcode directly |
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1560 enc_class Opcode(immI d8) %{ |
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1561 emit_opcode(cbuf, $d8$$constant); |
| 0 | 1562 %} |
| 1563 | |
| 1564 enc_class SizePrefix %{ | |
| 1565 emit_opcode(cbuf,0x66); | |
| 1566 %} | |
| 1567 | |
| 1568 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many) | |
| 1569 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 1570 %} | |
| 1571 | |
| 1572 enc_class OpcRegReg (immI opcode, eRegI dst, eRegI src) %{ // OpcRegReg(Many) | |
| 1573 emit_opcode(cbuf,$opcode$$constant); | |
| 1574 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 1575 %} | |
| 1576 | |
| 1577 enc_class mov_r32_imm0( eRegI dst ) %{ | |
| 1578 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32 | |
| 1579 emit_d32 ( cbuf, 0x0 ); // imm32==0x0 | |
| 1580 %} | |
| 1581 | |
| 1582 enc_class cdq_enc %{ | |
| 1583 // Full implementation of Java idiv and irem; checks for | |
| 1584 // special case as described in JVM spec., p.243 & p.271. | |
| 1585 // | |
| 1586 // normal case special case | |
| 1587 // | |
| 1588 // input : rax,: dividend min_int | |
| 1589 // reg: divisor -1 | |
| 1590 // | |
| 1591 // output: rax,: quotient (= rax, idiv reg) min_int | |
| 1592 // rdx: remainder (= rax, irem reg) 0 | |
| 1593 // | |
| 1594 // Code sequnce: | |
| 1595 // | |
| 1596 // 81 F8 00 00 00 80 cmp rax,80000000h | |
| 1597 // 0F 85 0B 00 00 00 jne normal_case | |
| 1598 // 33 D2 xor rdx,edx | |
| 1599 // 83 F9 FF cmp rcx,0FFh | |
| 1600 // 0F 84 03 00 00 00 je done | |
| 1601 // normal_case: | |
| 1602 // 99 cdq | |
| 1603 // F7 F9 idiv rax,ecx | |
| 1604 // done: | |
| 1605 // | |
| 1606 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8); | |
| 1607 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); | |
| 1608 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h | |
| 1609 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85); | |
| 1610 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00); | |
| 1611 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case | |
| 1612 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx | |
| 1613 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh | |
| 1614 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84); | |
| 1615 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00); | |
| 1616 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done | |
| 1617 // normal_case: | |
| 1618 emit_opcode(cbuf,0x99); // cdq | |
| 1619 // idiv (note: must be emitted by the user of this rule) | |
| 1620 // normal: | |
| 1621 %} | |
| 1622 | |
| 1623 // Dense encoding for older common ops | |
| 1624 enc_class Opc_plus(immI opcode, eRegI reg) %{ | |
| 1625 emit_opcode(cbuf, $opcode$$constant + $reg$$reg); | |
| 1626 %} | |
| 1627 | |
| 1628 | |
| 1629 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension | |
| 1630 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit | |
| 1631 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1632 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1633 emit_opcode(cbuf, $primary | 0x02); | |
| 1634 } | |
| 1635 else { // If 32-bit immediate | |
| 1636 emit_opcode(cbuf, $primary); | |
| 1637 } | |
| 1638 %} | |
| 1639 | |
| 1640 enc_class OpcSErm (eRegI dst, immI imm) %{ // OpcSEr/m | |
| 1641 // Emit primary opcode and set sign-extend bit | |
| 1642 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1643 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1644 emit_opcode(cbuf, $primary | 0x02); } | |
| 1645 else { // If 32-bit immediate | |
| 1646 emit_opcode(cbuf, $primary); | |
| 1647 } | |
| 1648 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 1649 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1650 %} | |
| 1651 | |
| 1652 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits | |
| 1653 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1654 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { | |
| 1655 $$$emit8$imm$$constant; | |
| 1656 } | |
| 1657 else { // If 32-bit immediate | |
| 1658 // Output immediate | |
| 1659 $$$emit32$imm$$constant; | |
| 1660 } | |
| 1661 %} | |
| 1662 | |
| 1663 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{ | |
| 1664 // Emit primary opcode and set sign-extend bit | |
| 1665 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1666 int con = (int)$imm$$constant; // Throw away top bits | |
| 1667 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary); | |
| 1668 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 1669 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1670 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con); | |
| 1671 else emit_d32(cbuf,con); | |
| 1672 %} | |
| 1673 | |
| 1674 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{ | |
| 1675 // Emit primary opcode and set sign-extend bit | |
| 1676 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 1677 int con = (int)($imm$$constant >> 32); // Throw away bottom bits | |
| 1678 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary); | |
| 1679 // Emit r/m byte with tertiary opcode, after primary opcode. | |
| 1680 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg)); | |
| 1681 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con); | |
| 1682 else emit_d32(cbuf,con); | |
| 1683 %} | |
| 1684 | |
| 1685 enc_class OpcSReg (eRegI dst) %{ // BSWAP | |
| 1686 emit_cc(cbuf, $secondary, $dst$$reg ); | |
| 1687 %} | |
| 1688 | |
| 1689 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP | |
| 1690 int destlo = $dst$$reg; | |
| 1691 int desthi = HIGH_FROM_LOW(destlo); | |
| 1692 // bswap lo | |
| 1693 emit_opcode(cbuf, 0x0F); | |
| 1694 emit_cc(cbuf, 0xC8, destlo); | |
| 1695 // bswap hi | |
| 1696 emit_opcode(cbuf, 0x0F); | |
| 1697 emit_cc(cbuf, 0xC8, desthi); | |
| 1698 // xchg lo and hi | |
| 1699 emit_opcode(cbuf, 0x87); | |
| 1700 emit_rm(cbuf, 0x3, destlo, desthi); | |
| 1701 %} | |
| 1702 | |
| 1703 enc_class RegOpc (eRegI div) %{ // IDIV, IMOD, JMP indirect, ... | |
| 1704 emit_rm(cbuf, 0x3, $secondary, $div$$reg ); | |
| 1705 %} | |
| 1706 | |
| 1707 enc_class enc_cmov(cmpOp cop ) %{ // CMOV | |
| 1708 $$$emit8$primary; | |
| 1709 emit_cc(cbuf, $secondary, $cop$$cmpcode); | |
| 1710 %} | |
| 1711 | |
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1712 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV |
| 0 | 1713 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1); |
| 1714 emit_d8(cbuf, op >> 8 ); | |
| 1715 emit_d8(cbuf, op & 255); | |
| 1716 %} | |
| 1717 | |
| 1718 // emulate a CMOV with a conditional branch around a MOV | |
| 1719 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV | |
| 1720 // Invert sense of branch from sense of CMOV | |
| 1721 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) ); | |
| 1722 emit_d8( cbuf, $brOffs$$constant ); | |
| 1723 %} | |
| 1724 | |
| 1725 enc_class enc_PartialSubtypeCheck( ) %{ | |
| 1726 Register Redi = as_Register(EDI_enc); // result register | |
| 1727 Register Reax = as_Register(EAX_enc); // super class | |
| 1728 Register Recx = as_Register(ECX_enc); // killed | |
| 1729 Register Resi = as_Register(ESI_enc); // sub class | |
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1730 Label miss; |
| 0 | 1731 |
| 1732 MacroAssembler _masm(&cbuf); | |
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1733 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi, |
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1734 NULL, &miss, |
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1735 /*set_cond_codes:*/ true); |
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1736 if ($primary) { |
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1737 __ xorptr(Redi, Redi); |
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1738 } |
| 0 | 1739 __ bind(miss); |
| 1740 %} | |
| 1741 | |
| 1742 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All | |
| 1743 MacroAssembler masm(&cbuf); | |
| 1744 int start = masm.offset(); | |
| 1745 if (UseSSE >= 2) { | |
| 1746 if (VerifyFPU) { | |
| 1747 masm.verify_FPU(0, "must be empty in SSE2+ mode"); | |
| 1748 } | |
| 1749 } else { | |
| 1750 // External c_calling_convention expects the FPU stack to be 'clean'. | |
| 1751 // Compiled code leaves it dirty. Do cleanup now. | |
| 1752 masm.empty_FPU_stack(); | |
| 1753 } | |
| 1754 if (sizeof_FFree_Float_Stack_All == -1) { | |
| 1755 sizeof_FFree_Float_Stack_All = masm.offset() - start; | |
| 1756 } else { | |
| 1757 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size"); | |
| 1758 } | |
| 1759 %} | |
| 1760 | |
| 1761 enc_class Verify_FPU_For_Leaf %{ | |
| 1762 if( VerifyFPU ) { | |
| 1763 MacroAssembler masm(&cbuf); | |
| 1764 masm.verify_FPU( -3, "Returning from Runtime Leaf call"); | |
| 1765 } | |
| 1766 %} | |
| 1767 | |
| 1768 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf | |
| 1769 // This is the instruction starting address for relocation info. | |
| 1748 | 1770 cbuf.set_insts_mark(); |
| 0 | 1771 $$$emit8$primary; |
| 1772 // CALL directly to the runtime | |
| 1748 | 1773 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1774 runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 1775 | |
| 1776 if (UseSSE >= 2) { | |
| 1777 MacroAssembler _masm(&cbuf); | |
| 1778 BasicType rt = tf()->return_type(); | |
| 1779 | |
| 1780 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) { | |
| 1781 // A C runtime call where the return value is unused. In SSE2+ | |
| 1782 // mode the result needs to be removed from the FPU stack. It's | |
| 1783 // likely that this function call could be removed by the | |
| 1784 // optimizer if the C function is a pure function. | |
| 1785 __ ffree(0); | |
| 1786 } else if (rt == T_FLOAT) { | |
| 304 | 1787 __ lea(rsp, Address(rsp, -4)); |
| 0 | 1788 __ fstp_s(Address(rsp, 0)); |
| 1789 __ movflt(xmm0, Address(rsp, 0)); | |
| 304 | 1790 __ lea(rsp, Address(rsp, 4)); |
| 0 | 1791 } else if (rt == T_DOUBLE) { |
| 304 | 1792 __ lea(rsp, Address(rsp, -8)); |
| 0 | 1793 __ fstp_d(Address(rsp, 0)); |
| 1794 __ movdbl(xmm0, Address(rsp, 0)); | |
| 304 | 1795 __ lea(rsp, Address(rsp, 8)); |
| 0 | 1796 } |
| 1797 } | |
| 1798 %} | |
| 1799 | |
| 1800 | |
| 1801 enc_class pre_call_FPU %{ | |
| 1802 // If method sets FPU control word restore it here | |
| 1748 | 1803 debug_only(int off0 = cbuf.insts_size()); |
| 0 | 1804 if( Compile::current()->in_24_bit_fp_mode() ) { |
| 1805 MacroAssembler masm(&cbuf); | |
| 1806 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 1807 } | |
| 1748 | 1808 debug_only(int off1 = cbuf.insts_size()); |
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1809 assert(off1 - off0 == pre_call_FPU_size(), "correct size prediction"); |
| 0 | 1810 %} |
| 1811 | |
| 1812 enc_class post_call_FPU %{ | |
| 1813 // If method sets FPU control word do it here also | |
| 1814 if( Compile::current()->in_24_bit_fp_mode() ) { | |
| 1815 MacroAssembler masm(&cbuf); | |
| 1816 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 1817 } | |
| 1818 %} | |
| 1819 | |
| 1820 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL | |
| 1821 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
| 1822 // who we intended to call. | |
| 1748 | 1823 cbuf.set_insts_mark(); |
| 0 | 1824 $$$emit8$primary; |
| 1825 if ( !_method ) { | |
| 1748 | 1826 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1827 runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 1828 } else if(_optimized_virtual) { | |
| 1748 | 1829 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1830 opt_virtual_call_Relocation::spec(), RELOC_IMM32 ); |
| 1831 } else { | |
| 1748 | 1832 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1833 static_call_Relocation::spec(), RELOC_IMM32 ); |
| 1834 } | |
| 1835 if( _method ) { // Emit stub for static call | |
| 1836 emit_java_to_interp(cbuf); | |
| 1837 } | |
| 1838 %} | |
| 1839 | |
| 1840 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL | |
| 1841 // !!!!! | |
| 1842 // Generate "Mov EAX,0x00", placeholder instruction to load oop-info | |
| 1843 // emit_call_dynamic_prologue( cbuf ); | |
| 1748 | 1844 cbuf.set_insts_mark(); |
| 0 | 1845 emit_opcode(cbuf, 0xB8 + EAX_enc); // mov EAX,-1 |
| 1846 emit_d32_reloc(cbuf, (int)Universe::non_oop_word(), oop_Relocation::spec_for_immediate(), RELOC_IMM32); | |
| 1748 | 1847 address virtual_call_oop_addr = cbuf.insts_mark(); |
| 0 | 1848 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine |
| 1849 // who we intended to call. | |
| 1748 | 1850 cbuf.set_insts_mark(); |
| 0 | 1851 $$$emit8$primary; |
| 1748 | 1852 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), |
| 0 | 1853 virtual_call_Relocation::spec(virtual_call_oop_addr), RELOC_IMM32 ); |
| 1854 %} | |
| 1855 | |
| 1856 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL | |
| 1857 int disp = in_bytes(methodOopDesc::from_compiled_offset()); | |
| 1858 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small"); | |
| 1859 | |
| 1860 // CALL *[EAX+in_bytes(methodOopDesc::from_compiled_code_entry_point_offset())] | |
| 1748 | 1861 cbuf.set_insts_mark(); |
| 0 | 1862 $$$emit8$primary; |
| 1863 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte | |
| 1864 emit_d8(cbuf, disp); // Displacement | |
| 1865 | |
| 1866 %} | |
| 1867 | |
| 1868 // Following encoding is no longer used, but may be restored if calling | |
| 1869 // convention changes significantly. | |
| 1870 // Became: Xor_Reg(EBP), Java_To_Runtime( labl ) | |
| 1871 // | |
| 1872 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL | |
| 1873 // // int ic_reg = Matcher::inline_cache_reg(); | |
| 1874 // // int ic_encode = Matcher::_regEncode[ic_reg]; | |
| 1875 // // int imo_reg = Matcher::interpreter_method_oop_reg(); | |
| 1876 // // int imo_encode = Matcher::_regEncode[imo_reg]; | |
| 1877 // | |
| 1878 // // // Interpreter expects method_oop in EBX, currently a callee-saved register, | |
| 1879 // // // so we load it immediately before the call | |
| 1880 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop | |
| 1881 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte | |
| 1882 // | |
| 1883 // // xor rbp,ebp | |
| 1884 // emit_opcode(cbuf, 0x33); | |
| 1885 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc); | |
| 1886 // | |
| 1887 // // CALL to interpreter. | |
| 1748 | 1888 // cbuf.set_insts_mark(); |
| 0 | 1889 // $$$emit8$primary; |
| 1748 | 1890 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4), |
| 0 | 1891 // runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 1892 // %} | |
| 1893 | |
| 1894 enc_class RegOpcImm (eRegI dst, immI8 shift) %{ // SHL, SAR, SHR | |
| 1895 $$$emit8$primary; | |
| 1896 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); | |
| 1897 $$$emit8$shift$$constant; | |
| 1898 %} | |
| 1899 | |
| 1900 enc_class LdImmI (eRegI dst, immI src) %{ // Load Immediate | |
| 1901 // Load immediate does not have a zero or sign extended version | |
| 1902 // for 8-bit immediates | |
| 1903 emit_opcode(cbuf, 0xB8 + $dst$$reg); | |
| 1904 $$$emit32$src$$constant; | |
| 1905 %} | |
| 1906 | |
| 1907 enc_class LdImmP (eRegI dst, immI src) %{ // Load Immediate | |
| 1908 // Load immediate does not have a zero or sign extended version | |
| 1909 // for 8-bit immediates | |
| 1910 emit_opcode(cbuf, $primary + $dst$$reg); | |
| 1911 $$$emit32$src$$constant; | |
| 1912 %} | |
| 1913 | |
| 1914 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate | |
| 1915 // Load immediate does not have a zero or sign extended version | |
| 1916 // for 8-bit immediates | |
| 1917 int dst_enc = $dst$$reg; | |
| 1918 int src_con = $src$$constant & 0x0FFFFFFFFL; | |
| 1919 if (src_con == 0) { | |
| 1920 // xor dst, dst | |
| 1921 emit_opcode(cbuf, 0x33); | |
| 1922 emit_rm(cbuf, 0x3, dst_enc, dst_enc); | |
| 1923 } else { | |
| 1924 emit_opcode(cbuf, $primary + dst_enc); | |
| 1925 emit_d32(cbuf, src_con); | |
| 1926 } | |
| 1927 %} | |
| 1928 | |
| 1929 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate | |
| 1930 // Load immediate does not have a zero or sign extended version | |
| 1931 // for 8-bit immediates | |
| 1932 int dst_enc = $dst$$reg + 2; | |
| 1933 int src_con = ((julong)($src$$constant)) >> 32; | |
| 1934 if (src_con == 0) { | |
| 1935 // xor dst, dst | |
| 1936 emit_opcode(cbuf, 0x33); | |
| 1937 emit_rm(cbuf, 0x3, dst_enc, dst_enc); | |
| 1938 } else { | |
| 1939 emit_opcode(cbuf, $primary + dst_enc); | |
| 1940 emit_d32(cbuf, src_con); | |
| 1941 } | |
| 1942 %} | |
| 1943 | |
| 1944 | |
| 1945 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 1946 enc_class enc_Copy( eRegI dst, eRegI src ) %{ | |
| 1947 encode_Copy( cbuf, $dst$$reg, $src$$reg ); | |
| 1948 %} | |
| 1949 | |
| 1950 enc_class enc_CopyL_Lo( eRegI dst, eRegL src ) %{ | |
| 1951 encode_Copy( cbuf, $dst$$reg, $src$$reg ); | |
| 1952 %} | |
| 1953 | |
| 1954 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many) | |
| 1955 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 1956 %} | |
| 1957 | |
| 1958 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 1959 $$$emit8$primary; | |
| 1960 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 1961 %} | |
| 1962 | |
| 1963 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 1964 $$$emit8$secondary; | |
| 1965 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); | |
| 1966 %} | |
| 1967 | |
| 1968 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 1969 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 1970 %} | |
| 1971 | |
| 1972 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many) | |
| 1973 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); | |
| 1974 %} | |
| 1975 | |
| 1976 enc_class RegReg_HiLo( eRegL src, eRegI dst ) %{ | |
| 1977 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg)); | |
| 1978 %} | |
| 1979 | |
| 1980 enc_class Con32 (immI src) %{ // Con32(storeImmI) | |
| 1981 // Output immediate | |
| 1982 $$$emit32$src$$constant; | |
| 1983 %} | |
| 1984 | |
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1985 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm |
| 0 | 1986 // Output Float immediate bits |
| 1987 jfloat jf = $src$$constant; | |
| 1988 int jf_as_bits = jint_cast( jf ); | |
| 1989 emit_d32(cbuf, jf_as_bits); | |
| 1990 %} | |
| 1991 | |
|
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1992 enc_class Con32F_as_bits(immF src) %{ // storeX_imm |
| 0 | 1993 // Output Float immediate bits |
| 1994 jfloat jf = $src$$constant; | |
| 1995 int jf_as_bits = jint_cast( jf ); | |
| 1996 emit_d32(cbuf, jf_as_bits); | |
| 1997 %} | |
| 1998 | |
| 1999 enc_class Con16 (immI src) %{ // Con16(storeImmI) | |
| 2000 // Output immediate | |
| 2001 $$$emit16$src$$constant; | |
| 2002 %} | |
| 2003 | |
| 2004 enc_class Con_d32(immI src) %{ | |
| 2005 emit_d32(cbuf,$src$$constant); | |
| 2006 %} | |
| 2007 | |
| 2008 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI) | |
| 2009 // Output immediate memory reference | |
| 2010 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 ); | |
| 2011 emit_d32(cbuf, 0x00); | |
| 2012 %} | |
| 2013 | |
| 2014 enc_class lock_prefix( ) %{ | |
| 2015 if( os::is_MP() ) | |
| 2016 emit_opcode(cbuf,0xF0); // [Lock] | |
| 2017 %} | |
| 2018 | |
| 2019 // Cmp-xchg long value. | |
| 2020 // Note: we need to swap rbx, and rcx before and after the | |
| 2021 // cmpxchg8 instruction because the instruction uses | |
| 2022 // rcx as the high order word of the new value to store but | |
| 2023 // our register encoding uses rbx,. | |
| 2024 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{ | |
| 2025 | |
| 2026 // XCHG rbx,ecx | |
| 2027 emit_opcode(cbuf,0x87); | |
| 2028 emit_opcode(cbuf,0xD9); | |
| 2029 // [Lock] | |
| 2030 if( os::is_MP() ) | |
| 2031 emit_opcode(cbuf,0xF0); | |
| 2032 // CMPXCHG8 [Eptr] | |
| 2033 emit_opcode(cbuf,0x0F); | |
| 2034 emit_opcode(cbuf,0xC7); | |
| 2035 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg ); | |
| 2036 // XCHG rbx,ecx | |
| 2037 emit_opcode(cbuf,0x87); | |
| 2038 emit_opcode(cbuf,0xD9); | |
| 2039 %} | |
| 2040 | |
| 2041 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{ | |
| 2042 // [Lock] | |
| 2043 if( os::is_MP() ) | |
| 2044 emit_opcode(cbuf,0xF0); | |
| 2045 | |
| 2046 // CMPXCHG [Eptr] | |
| 2047 emit_opcode(cbuf,0x0F); | |
| 2048 emit_opcode(cbuf,0xB1); | |
| 2049 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg ); | |
| 2050 %} | |
| 2051 | |
| 2052 enc_class enc_flags_ne_to_boolean( iRegI res ) %{ | |
| 2053 int res_encoding = $res$$reg; | |
| 2054 | |
| 2055 // MOV res,0 | |
| 2056 emit_opcode( cbuf, 0xB8 + res_encoding); | |
| 2057 emit_d32( cbuf, 0 ); | |
| 2058 // JNE,s fail | |
| 2059 emit_opcode(cbuf,0x75); | |
| 2060 emit_d8(cbuf, 5 ); | |
| 2061 // MOV res,1 | |
| 2062 emit_opcode( cbuf, 0xB8 + res_encoding); | |
| 2063 emit_d32( cbuf, 1 ); | |
| 2064 // fail: | |
| 2065 %} | |
| 2066 | |
| 2067 enc_class set_instruction_start( ) %{ | |
| 1748 | 2068 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand |
| 0 | 2069 %} |
| 2070 | |
| 2071 enc_class RegMem (eRegI ereg, memory mem) %{ // emit_reg_mem | |
| 2072 int reg_encoding = $ereg$$reg; | |
| 2073 int base = $mem$$base; | |
| 2074 int index = $mem$$index; | |
| 2075 int scale = $mem$$scale; | |
| 2076 int displace = $mem$$disp; | |
| 2077 bool disp_is_oop = $mem->disp_is_oop(); | |
| 2078 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); | |
| 2079 %} | |
| 2080 | |
| 2081 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem | |
| 2082 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo | |
| 2083 int base = $mem$$base; | |
| 2084 int index = $mem$$index; | |
| 2085 int scale = $mem$$scale; | |
| 2086 int displace = $mem$$disp + 4; // Offset is 4 further in memory | |
| 2087 assert( !$mem->disp_is_oop(), "Cannot add 4 to oop" ); | |
| 2088 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, false/*disp_is_oop*/); | |
| 2089 %} | |
| 2090 | |
| 2091 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{ | |
| 2092 int r1, r2; | |
| 2093 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); } | |
| 2094 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); } | |
| 2095 emit_opcode(cbuf,0x0F); | |
| 2096 emit_opcode(cbuf,$tertiary); | |
| 2097 emit_rm(cbuf, 0x3, r1, r2); | |
| 2098 emit_d8(cbuf,$cnt$$constant); | |
| 2099 emit_d8(cbuf,$primary); | |
| 2100 emit_rm(cbuf, 0x3, $secondary, r1); | |
| 2101 emit_d8(cbuf,$cnt$$constant); | |
| 2102 %} | |
| 2103 | |
| 2104 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{ | |
| 2105 emit_opcode( cbuf, 0x8B ); // Move | |
| 2106 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg)); | |
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2107 if( $cnt$$constant > 32 ) { // Shift, if not by zero |
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2108 emit_d8(cbuf,$primary); |
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2109 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); |
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2110 emit_d8(cbuf,$cnt$$constant-32); |
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2111 } |
| 0 | 2112 emit_d8(cbuf,$primary); |
| 2113 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg)); | |
| 2114 emit_d8(cbuf,31); | |
| 2115 %} | |
| 2116 | |
| 2117 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{ | |
| 2118 int r1, r2; | |
| 2119 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); } | |
| 2120 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); } | |
| 2121 | |
| 2122 emit_opcode( cbuf, 0x8B ); // Move r1,r2 | |
| 2123 emit_rm(cbuf, 0x3, r1, r2); | |
| 2124 if( $cnt$$constant > 32 ) { // Shift, if not by zero | |
| 2125 emit_opcode(cbuf,$primary); | |
| 2126 emit_rm(cbuf, 0x3, $secondary, r1); | |
| 2127 emit_d8(cbuf,$cnt$$constant-32); | |
| 2128 } | |
| 2129 emit_opcode(cbuf,0x33); // XOR r2,r2 | |
| 2130 emit_rm(cbuf, 0x3, r2, r2); | |
| 2131 %} | |
| 2132 | |
| 2133 // Clone of RegMem but accepts an extra parameter to access each | |
| 2134 // half of a double in memory; it never needs relocation info. | |
| 2135 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, eRegI rm_reg) %{ | |
| 2136 emit_opcode(cbuf,$opcode$$constant); | |
| 2137 int reg_encoding = $rm_reg$$reg; | |
| 2138 int base = $mem$$base; | |
| 2139 int index = $mem$$index; | |
| 2140 int scale = $mem$$scale; | |
| 2141 int displace = $mem$$disp + $disp_for_half$$constant; | |
| 2142 bool disp_is_oop = false; | |
| 2143 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); | |
| 2144 %} | |
| 2145 | |
| 2146 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!! | |
| 2147 // | |
| 2148 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant | |
| 2149 // and it never needs relocation information. | |
| 2150 // Frequently used to move data between FPU's Stack Top and memory. | |
| 2151 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{ | |
| 2152 int rm_byte_opcode = $rm_opcode$$constant; | |
| 2153 int base = $mem$$base; | |
| 2154 int index = $mem$$index; | |
| 2155 int scale = $mem$$scale; | |
| 2156 int displace = $mem$$disp; | |
| 2157 assert( !$mem->disp_is_oop(), "No oops here because no relo info allowed" ); | |
| 2158 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, false); | |
| 2159 %} | |
| 2160 | |
| 2161 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{ | |
| 2162 int rm_byte_opcode = $rm_opcode$$constant; | |
| 2163 int base = $mem$$base; | |
| 2164 int index = $mem$$index; | |
| 2165 int scale = $mem$$scale; | |
| 2166 int displace = $mem$$disp; | |
| 2167 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals | |
| 2168 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop); | |
| 2169 %} | |
| 2170 | |
| 2171 enc_class RegLea (eRegI dst, eRegI src0, immI src1 ) %{ // emit_reg_lea | |
| 2172 int reg_encoding = $dst$$reg; | |
| 2173 int base = $src0$$reg; // 0xFFFFFFFF indicates no base | |
| 2174 int index = 0x04; // 0x04 indicates no index | |
| 2175 int scale = 0x00; // 0x00 indicates no scale | |
| 2176 int displace = $src1$$constant; // 0x00 indicates no displacement | |
| 2177 bool disp_is_oop = false; | |
| 2178 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); | |
| 2179 %} | |
| 2180 | |
| 2181 enc_class min_enc (eRegI dst, eRegI src) %{ // MIN | |
| 2182 // Compare dst,src | |
| 2183 emit_opcode(cbuf,0x3B); | |
| 2184 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2185 // jmp dst < src around move | |
| 2186 emit_opcode(cbuf,0x7C); | |
| 2187 emit_d8(cbuf,2); | |
| 2188 // move dst,src | |
| 2189 emit_opcode(cbuf,0x8B); | |
| 2190 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2191 %} | |
| 2192 | |
| 2193 enc_class max_enc (eRegI dst, eRegI src) %{ // MAX | |
| 2194 // Compare dst,src | |
| 2195 emit_opcode(cbuf,0x3B); | |
| 2196 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2197 // jmp dst > src around move | |
| 2198 emit_opcode(cbuf,0x7F); | |
| 2199 emit_d8(cbuf,2); | |
| 2200 // move dst,src | |
| 2201 emit_opcode(cbuf,0x8B); | |
| 2202 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); | |
| 2203 %} | |
| 2204 | |
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2205 enc_class enc_FPR_store(memory mem, regDPR src) %{ |
| 0 | 2206 // If src is FPR1, we can just FST to store it. |
| 2207 // Else we need to FLD it to FPR1, then FSTP to store/pop it. | |
| 2208 int reg_encoding = 0x2; // Just store | |
| 2209 int base = $mem$$base; | |
| 2210 int index = $mem$$index; | |
| 2211 int scale = $mem$$scale; | |
| 2212 int displace = $mem$$disp; | |
| 2213 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals | |
| 2214 if( $src$$reg != FPR1L_enc ) { | |
| 2215 reg_encoding = 0x3; // Store & pop | |
| 2216 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it) | |
| 2217 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2218 } | |
| 1748 | 2219 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand |
| 0 | 2220 emit_opcode(cbuf,$primary); |
| 2221 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); | |
| 2222 %} | |
| 2223 | |
| 2224 enc_class neg_reg(eRegI dst) %{ | |
| 2225 // NEG $dst | |
| 2226 emit_opcode(cbuf,0xF7); | |
| 2227 emit_rm(cbuf, 0x3, 0x03, $dst$$reg ); | |
| 2228 %} | |
| 2229 | |
| 2230 enc_class setLT_reg(eCXRegI dst) %{ | |
| 2231 // SETLT $dst | |
| 2232 emit_opcode(cbuf,0x0F); | |
| 2233 emit_opcode(cbuf,0x9C); | |
| 2234 emit_rm( cbuf, 0x3, 0x4, $dst$$reg ); | |
| 2235 %} | |
| 2236 | |
| 2237 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT | |
| 2238 int tmpReg = $tmp$$reg; | |
| 2239 | |
| 2240 // SUB $p,$q | |
| 2241 emit_opcode(cbuf,0x2B); | |
| 2242 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg); | |
| 2243 // SBB $tmp,$tmp | |
| 2244 emit_opcode(cbuf,0x1B); | |
| 2245 emit_rm(cbuf, 0x3, tmpReg, tmpReg); | |
| 2246 // AND $tmp,$y | |
| 2247 emit_opcode(cbuf,0x23); | |
| 2248 emit_rm(cbuf, 0x3, tmpReg, $y$$reg); | |
| 2249 // ADD $p,$tmp | |
| 2250 emit_opcode(cbuf,0x03); | |
| 2251 emit_rm(cbuf, 0x3, $p$$reg, tmpReg); | |
| 2252 %} | |
| 2253 | |
| 2254 enc_class enc_cmpLTP_mem(eRegI p, eRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT | |
| 2255 int tmpReg = $tmp$$reg; | |
| 2256 | |
| 2257 // SUB $p,$q | |
| 2258 emit_opcode(cbuf,0x2B); | |
| 2259 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg); | |
| 2260 // SBB $tmp,$tmp | |
| 2261 emit_opcode(cbuf,0x1B); | |
| 2262 emit_rm(cbuf, 0x3, tmpReg, tmpReg); | |
| 2263 // AND $tmp,$y | |
| 1748 | 2264 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand |
| 0 | 2265 emit_opcode(cbuf,0x23); |
| 2266 int reg_encoding = tmpReg; | |
| 2267 int base = $mem$$base; | |
| 2268 int index = $mem$$index; | |
| 2269 int scale = $mem$$scale; | |
| 2270 int displace = $mem$$disp; | |
| 2271 bool disp_is_oop = $mem->disp_is_oop(); | |
| 2272 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); | |
| 2273 // ADD $p,$tmp | |
| 2274 emit_opcode(cbuf,0x03); | |
| 2275 emit_rm(cbuf, 0x3, $p$$reg, tmpReg); | |
| 2276 %} | |
| 2277 | |
| 2278 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{ | |
| 2279 // TEST shift,32 | |
| 2280 emit_opcode(cbuf,0xF7); | |
| 2281 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2282 emit_d32(cbuf,0x20); | |
| 2283 // JEQ,s small | |
| 2284 emit_opcode(cbuf, 0x74); | |
| 2285 emit_d8(cbuf, 0x04); | |
| 2286 // MOV $dst.hi,$dst.lo | |
| 2287 emit_opcode( cbuf, 0x8B ); | |
| 2288 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg ); | |
| 2289 // CLR $dst.lo | |
| 2290 emit_opcode(cbuf, 0x33); | |
| 2291 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg); | |
| 2292 // small: | |
| 2293 // SHLD $dst.hi,$dst.lo,$shift | |
| 2294 emit_opcode(cbuf,0x0F); | |
| 2295 emit_opcode(cbuf,0xA5); | |
| 2296 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg)); | |
| 2297 // SHL $dst.lo,$shift" | |
| 2298 emit_opcode(cbuf,0xD3); | |
| 2299 emit_rm(cbuf, 0x3, 0x4, $dst$$reg ); | |
| 2300 %} | |
| 2301 | |
| 2302 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{ | |
| 2303 // TEST shift,32 | |
| 2304 emit_opcode(cbuf,0xF7); | |
| 2305 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2306 emit_d32(cbuf,0x20); | |
| 2307 // JEQ,s small | |
| 2308 emit_opcode(cbuf, 0x74); | |
| 2309 emit_d8(cbuf, 0x04); | |
| 2310 // MOV $dst.lo,$dst.hi | |
| 2311 emit_opcode( cbuf, 0x8B ); | |
| 2312 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2313 // CLR $dst.hi | |
| 2314 emit_opcode(cbuf, 0x33); | |
| 2315 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg)); | |
| 2316 // small: | |
| 2317 // SHRD $dst.lo,$dst.hi,$shift | |
| 2318 emit_opcode(cbuf,0x0F); | |
| 2319 emit_opcode(cbuf,0xAD); | |
| 2320 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg); | |
| 2321 // SHR $dst.hi,$shift" | |
| 2322 emit_opcode(cbuf,0xD3); | |
| 2323 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) ); | |
| 2324 %} | |
| 2325 | |
| 2326 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{ | |
| 2327 // TEST shift,32 | |
| 2328 emit_opcode(cbuf,0xF7); | |
| 2329 emit_rm(cbuf, 0x3, 0, ECX_enc); | |
| 2330 emit_d32(cbuf,0x20); | |
| 2331 // JEQ,s small | |
| 2332 emit_opcode(cbuf, 0x74); | |
| 2333 emit_d8(cbuf, 0x05); | |
| 2334 // MOV $dst.lo,$dst.hi | |
| 2335 emit_opcode( cbuf, 0x8B ); | |
| 2336 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2337 // SAR $dst.hi,31 | |
| 2338 emit_opcode(cbuf, 0xC1); | |
| 2339 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) ); | |
| 2340 emit_d8(cbuf, 0x1F ); | |
| 2341 // small: | |
| 2342 // SHRD $dst.lo,$dst.hi,$shift | |
| 2343 emit_opcode(cbuf,0x0F); | |
| 2344 emit_opcode(cbuf,0xAD); | |
| 2345 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg); | |
| 2346 // SAR $dst.hi,$shift" | |
| 2347 emit_opcode(cbuf,0xD3); | |
| 2348 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) ); | |
| 2349 %} | |
| 2350 | |
| 2351 | |
| 2352 // ----------------- Encodings for floating point unit ----------------- | |
| 2353 // May leave result in FPU-TOS or FPU reg depending on opcodes | |
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2354 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV |
| 0 | 2355 $$$emit8$primary; |
| 2356 emit_rm(cbuf, 0x3, $secondary, $src$$reg ); | |
| 2357 %} | |
| 2358 | |
| 2359 // Pop argument in FPR0 with FSTP ST(0) | |
| 2360 enc_class PopFPU() %{ | |
| 2361 emit_opcode( cbuf, 0xDD ); | |
| 2362 emit_d8( cbuf, 0xD8 ); | |
| 2363 %} | |
| 2364 | |
| 2365 // !!!!! equivalent to Pop_Reg_F | |
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2366 enc_class Pop_Reg_DPR( regDPR dst ) %{ |
| 0 | 2367 emit_opcode( cbuf, 0xDD ); // FSTP ST(i) |
| 2368 emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2369 %} | |
| 2370 | |
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2371 enc_class Push_Reg_DPR( regDPR dst ) %{ |
| 0 | 2372 emit_opcode( cbuf, 0xD9 ); |
| 2373 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1) | |
| 2374 %} | |
| 2375 | |
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2376 enc_class strictfp_bias1( regDPR dst ) %{ |
| 0 | 2377 emit_opcode( cbuf, 0xDB ); // FLD m80real |
| 2378 emit_opcode( cbuf, 0x2D ); | |
| 2379 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() ); | |
| 2380 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0 | |
| 2381 emit_opcode( cbuf, 0xC8+$dst$$reg ); | |
| 2382 %} | |
| 2383 | |
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2384 enc_class strictfp_bias2( regDPR dst ) %{ |
| 0 | 2385 emit_opcode( cbuf, 0xDB ); // FLD m80real |
| 2386 emit_opcode( cbuf, 0x2D ); | |
| 2387 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() ); | |
| 2388 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0 | |
| 2389 emit_opcode( cbuf, 0xC8+$dst$$reg ); | |
| 2390 %} | |
| 2391 | |
| 2392 // Special case for moving an integer register to a stack slot. | |
| 2393 enc_class OpcPRegSS( stackSlotI dst, eRegI src ) %{ // RegSS | |
| 2394 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp ); | |
| 2395 %} | |
| 2396 | |
| 2397 // Special case for moving a register to a stack slot. | |
| 2398 enc_class RegSS( stackSlotI dst, eRegI src ) %{ // RegSS | |
| 2399 // Opcode already emitted | |
| 2400 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte | |
| 2401 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte | |
| 2402 emit_d32(cbuf, $dst$$disp); // Displacement | |
| 2403 %} | |
| 2404 | |
| 2405 // Push the integer in stackSlot 'src' onto FP-stack | |
| 2406 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src] | |
| 2407 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp ); | |
| 2408 %} | |
| 2409 | |
| 2410 // Push FPU's TOS float to a stack-slot, and pop FPU-stack | |
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2411 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst] |
| 0 | 2412 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp ); |
| 2413 %} | |
| 2414 | |
| 2415 // Same as Pop_Mem_F except for opcode | |
| 2416 // Push FPU's TOS double to a stack-slot, and pop FPU-stack | |
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2417 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst] |
| 0 | 2418 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp ); |
| 2419 %} | |
| 2420 | |
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2421 enc_class Pop_Reg_FPR( regFPR dst ) %{ |
| 0 | 2422 emit_opcode( cbuf, 0xDD ); // FSTP ST(i) |
| 2423 emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2424 %} | |
| 2425 | |
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2426 enc_class Push_Reg_FPR( regFPR dst ) %{ |
| 0 | 2427 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) |
| 2428 emit_d8( cbuf, 0xC0-1+$dst$$reg ); | |
| 2429 %} | |
| 2430 | |
| 2431 // Push FPU's float to a stack-slot, and pop FPU-stack | |
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2432 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{ |
| 0 | 2433 int pop = 0x02; |
| 2434 if ($src$$reg != FPR1L_enc) { | |
| 2435 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) | |
| 2436 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2437 pop = 0x03; | |
| 2438 } | |
| 2439 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst] | |
| 2440 %} | |
| 2441 | |
| 2442 // Push FPU's double to a stack-slot, and pop FPU-stack | |
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2443 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{ |
| 0 | 2444 int pop = 0x02; |
| 2445 if ($src$$reg != FPR1L_enc) { | |
| 2446 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) | |
| 2447 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2448 pop = 0x03; | |
| 2449 } | |
| 2450 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst] | |
| 2451 %} | |
| 2452 | |
| 2453 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack | |
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2454 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{ |
| 0 | 2455 int pop = 0xD0 - 1; // -1 since we skip FLD |
| 2456 if ($src$$reg != FPR1L_enc) { | |
| 2457 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1) | |
| 2458 emit_d8( cbuf, 0xC0-1+$src$$reg ); | |
| 2459 pop = 0xD8; | |
| 2460 } | |
| 2461 emit_opcode( cbuf, 0xDD ); | |
| 2462 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i) | |
| 2463 %} | |
| 2464 | |
| 2465 | |
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2466 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{ |
| 0 | 2467 // load dst in FPR0 |
| 2468 emit_opcode( cbuf, 0xD9 ); | |
| 2469 emit_d8( cbuf, 0xC0-1+$dst$$reg ); | |
| 2470 if ($src$$reg != FPR1L_enc) { | |
| 2471 // fincstp | |
| 2472 emit_opcode (cbuf, 0xD9); | |
| 2473 emit_opcode (cbuf, 0xF7); | |
| 2474 // swap src with FPR1: | |
| 2475 // FXCH FPR1 with src | |
| 2476 emit_opcode(cbuf, 0xD9); | |
| 2477 emit_d8(cbuf, 0xC8-1+$src$$reg ); | |
| 2478 // fdecstp | |
| 2479 emit_opcode (cbuf, 0xD9); | |
| 2480 emit_opcode (cbuf, 0xF6); | |
| 2481 } | |
| 2482 %} | |
| 2483 | |
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2484 enc_class Push_ModD_encoding(regD src0, regD src1) %{ |
| 4759 | 2485 MacroAssembler _masm(&cbuf); |
| 2486 __ subptr(rsp, 8); | |
| 2487 __ movdbl(Address(rsp, 0), $src1$$XMMRegister); | |
| 2488 __ fld_d(Address(rsp, 0)); | |
| 2489 __ movdbl(Address(rsp, 0), $src0$$XMMRegister); | |
| 2490 __ fld_d(Address(rsp, 0)); | |
| 2491 %} | |
| 2492 | |
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2493 enc_class Push_ModF_encoding(regF src0, regF src1) %{ |
| 4759 | 2494 MacroAssembler _masm(&cbuf); |
| 2495 __ subptr(rsp, 4); | |
| 2496 __ movflt(Address(rsp, 0), $src1$$XMMRegister); | |
| 2497 __ fld_s(Address(rsp, 0)); | |
| 2498 __ movflt(Address(rsp, 0), $src0$$XMMRegister); | |
| 2499 __ fld_s(Address(rsp, 0)); | |
| 0 | 2500 %} |
| 2501 | |
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2502 enc_class Push_ResultD(regD dst) %{ |
| 4759 | 2503 MacroAssembler _masm(&cbuf); |
| 2504 __ fstp_d(Address(rsp, 0)); | |
| 2505 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); | |
| 2506 __ addptr(rsp, 8); | |
| 0 | 2507 %} |
| 2508 | |
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2509 enc_class Push_ResultF(regF dst, immI d8) %{ |
| 4759 | 2510 MacroAssembler _masm(&cbuf); |
| 2511 __ fstp_s(Address(rsp, 0)); | |
| 2512 __ movflt($dst$$XMMRegister, Address(rsp, 0)); | |
| 2513 __ addptr(rsp, $d8$$constant); | |
| 0 | 2514 %} |
| 2515 | |
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2516 enc_class Push_SrcD(regD src) %{ |
| 4759 | 2517 MacroAssembler _masm(&cbuf); |
| 2518 __ subptr(rsp, 8); | |
| 2519 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 2520 __ fld_d(Address(rsp, 0)); | |
| 0 | 2521 %} |
| 2522 | |
| 2523 enc_class push_stack_temp_qword() %{ | |
| 4759 | 2524 MacroAssembler _masm(&cbuf); |
| 2525 __ subptr(rsp, 8); | |
| 0 | 2526 %} |
| 2527 | |
| 2528 enc_class pop_stack_temp_qword() %{ | |
| 4759 | 2529 MacroAssembler _masm(&cbuf); |
| 2530 __ addptr(rsp, 8); | |
| 2531 %} | |
| 2532 | |
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2533 enc_class push_xmm_to_fpr1(regD src) %{ |
| 4759 | 2534 MacroAssembler _masm(&cbuf); |
| 2535 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 2536 __ fld_d(Address(rsp, 0)); | |
| 0 | 2537 %} |
| 2538 | |
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2539 enc_class Push_Result_Mod_DPR( regDPR src) %{ |
| 0 | 2540 if ($src$$reg != FPR1L_enc) { |
| 2541 // fincstp | |
| 2542 emit_opcode (cbuf, 0xD9); | |
| 2543 emit_opcode (cbuf, 0xF7); | |
| 2544 // FXCH FPR1 with src | |
| 2545 emit_opcode(cbuf, 0xD9); | |
| 2546 emit_d8(cbuf, 0xC8-1+$src$$reg ); | |
| 2547 // fdecstp | |
| 2548 emit_opcode (cbuf, 0xD9); | |
| 2549 emit_opcode (cbuf, 0xF6); | |
| 2550 } | |
| 2551 // // following asm replaced with Pop_Reg_F or Pop_Mem_F | |
| 2552 // // FSTP FPR$dst$$reg | |
| 2553 // emit_opcode( cbuf, 0xDD ); | |
| 2554 // emit_d8( cbuf, 0xD8+$dst$$reg ); | |
| 2555 %} | |
| 2556 | |
| 2557 enc_class fnstsw_sahf_skip_parity() %{ | |
| 2558 // fnstsw ax | |
| 2559 emit_opcode( cbuf, 0xDF ); | |
| 2560 emit_opcode( cbuf, 0xE0 ); | |
| 2561 // sahf | |
| 2562 emit_opcode( cbuf, 0x9E ); | |
| 2563 // jnp ::skip | |
| 2564 emit_opcode( cbuf, 0x7B ); | |
| 2565 emit_opcode( cbuf, 0x05 ); | |
| 2566 %} | |
| 2567 | |
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2568 enc_class emitModDPR() %{ |
| 0 | 2569 // fprem must be iterative |
| 2570 // :: loop | |
| 2571 // fprem | |
| 2572 emit_opcode( cbuf, 0xD9 ); | |
| 2573 emit_opcode( cbuf, 0xF8 ); | |
| 2574 // wait | |
| 2575 emit_opcode( cbuf, 0x9b ); | |
| 2576 // fnstsw ax | |
| 2577 emit_opcode( cbuf, 0xDF ); | |
| 2578 emit_opcode( cbuf, 0xE0 ); | |
| 2579 // sahf | |
| 2580 emit_opcode( cbuf, 0x9E ); | |
| 2581 // jp ::loop | |
| 2582 emit_opcode( cbuf, 0x0F ); | |
| 2583 emit_opcode( cbuf, 0x8A ); | |
| 2584 emit_opcode( cbuf, 0xF4 ); | |
| 2585 emit_opcode( cbuf, 0xFF ); | |
| 2586 emit_opcode( cbuf, 0xFF ); | |
| 2587 emit_opcode( cbuf, 0xFF ); | |
| 2588 %} | |
| 2589 | |
| 2590 enc_class fpu_flags() %{ | |
| 2591 // fnstsw_ax | |
| 2592 emit_opcode( cbuf, 0xDF); | |
| 2593 emit_opcode( cbuf, 0xE0); | |
| 2594 // test ax,0x0400 | |
| 2595 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate | |
| 2596 emit_opcode( cbuf, 0xA9 ); | |
| 2597 emit_d16 ( cbuf, 0x0400 ); | |
| 2598 // // // This sequence works, but stalls for 12-16 cycles on PPro | |
| 2599 // // test rax,0x0400 | |
| 2600 // emit_opcode( cbuf, 0xA9 ); | |
| 2601 // emit_d32 ( cbuf, 0x00000400 ); | |
| 2602 // | |
| 2603 // jz exit (no unordered comparison) | |
| 2604 emit_opcode( cbuf, 0x74 ); | |
| 2605 emit_d8 ( cbuf, 0x02 ); | |
| 2606 // mov ah,1 - treat as LT case (set carry flag) | |
| 2607 emit_opcode( cbuf, 0xB4 ); | |
| 2608 emit_d8 ( cbuf, 0x01 ); | |
| 2609 // sahf | |
| 2610 emit_opcode( cbuf, 0x9E); | |
| 2611 %} | |
| 2612 | |
| 2613 enc_class cmpF_P6_fixup() %{ | |
| 2614 // Fixup the integer flags in case comparison involved a NaN | |
| 2615 // | |
| 2616 // JNP exit (no unordered comparison, P-flag is set by NaN) | |
| 2617 emit_opcode( cbuf, 0x7B ); | |
| 2618 emit_d8 ( cbuf, 0x03 ); | |
| 2619 // MOV AH,1 - treat as LT case (set carry flag) | |
| 2620 emit_opcode( cbuf, 0xB4 ); | |
| 2621 emit_d8 ( cbuf, 0x01 ); | |
| 2622 // SAHF | |
| 2623 emit_opcode( cbuf, 0x9E); | |
| 2624 // NOP // target for branch to avoid branch to branch | |
| 2625 emit_opcode( cbuf, 0x90); | |
| 2626 %} | |
| 2627 | |
| 2628 // fnstsw_ax(); | |
| 2629 // sahf(); | |
| 2630 // movl(dst, nan_result); | |
| 2631 // jcc(Assembler::parity, exit); | |
| 2632 // movl(dst, less_result); | |
| 2633 // jcc(Assembler::below, exit); | |
| 2634 // movl(dst, equal_result); | |
| 2635 // jcc(Assembler::equal, exit); | |
| 2636 // movl(dst, greater_result); | |
| 2637 | |
| 2638 // less_result = 1; | |
| 2639 // greater_result = -1; | |
| 2640 // equal_result = 0; | |
| 2641 // nan_result = -1; | |
| 2642 | |
| 2643 enc_class CmpF_Result(eRegI dst) %{ | |
| 2644 // fnstsw_ax(); | |
| 2645 emit_opcode( cbuf, 0xDF); | |
| 2646 emit_opcode( cbuf, 0xE0); | |
| 2647 // sahf | |
| 2648 emit_opcode( cbuf, 0x9E); | |
| 2649 // movl(dst, nan_result); | |
| 2650 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2651 emit_d32( cbuf, -1 ); | |
| 2652 // jcc(Assembler::parity, exit); | |
| 2653 emit_opcode( cbuf, 0x7A ); | |
| 2654 emit_d8 ( cbuf, 0x13 ); | |
| 2655 // movl(dst, less_result); | |
| 2656 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2657 emit_d32( cbuf, -1 ); | |
| 2658 // jcc(Assembler::below, exit); | |
| 2659 emit_opcode( cbuf, 0x72 ); | |
| 2660 emit_d8 ( cbuf, 0x0C ); | |
| 2661 // movl(dst, equal_result); | |
| 2662 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2663 emit_d32( cbuf, 0 ); | |
| 2664 // jcc(Assembler::equal, exit); | |
| 2665 emit_opcode( cbuf, 0x74 ); | |
| 2666 emit_d8 ( cbuf, 0x05 ); | |
| 2667 // movl(dst, greater_result); | |
| 2668 emit_opcode( cbuf, 0xB8 + $dst$$reg); | |
| 2669 emit_d32( cbuf, 1 ); | |
| 2670 %} | |
| 2671 | |
| 2672 | |
| 2673 // Compare the longs and set flags | |
| 2674 // BROKEN! Do Not use as-is | |
| 2675 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{ | |
| 2676 // CMP $src1.hi,$src2.hi | |
| 2677 emit_opcode( cbuf, 0x3B ); | |
| 2678 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); | |
| 2679 // JNE,s done | |
| 2680 emit_opcode(cbuf,0x75); | |
| 2681 emit_d8(cbuf, 2 ); | |
| 2682 // CMP $src1.lo,$src2.lo | |
| 2683 emit_opcode( cbuf, 0x3B ); | |
| 2684 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 2685 // done: | |
| 2686 %} | |
| 2687 | |
| 2688 enc_class convert_int_long( regL dst, eRegI src ) %{ | |
| 2689 // mov $dst.lo,$src | |
| 2690 int dst_encoding = $dst$$reg; | |
| 2691 int src_encoding = $src$$reg; | |
| 2692 encode_Copy( cbuf, dst_encoding , src_encoding ); | |
| 2693 // mov $dst.hi,$src | |
| 2694 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding ); | |
| 2695 // sar $dst.hi,31 | |
| 2696 emit_opcode( cbuf, 0xC1 ); | |
| 2697 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) ); | |
| 2698 emit_d8(cbuf, 0x1F ); | |
| 2699 %} | |
| 2700 | |
| 2701 enc_class convert_long_double( eRegL src ) %{ | |
| 2702 // push $src.hi | |
| 2703 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg)); | |
| 2704 // push $src.lo | |
| 2705 emit_opcode(cbuf, 0x50+$src$$reg ); | |
| 2706 // fild 64-bits at [SP] | |
| 2707 emit_opcode(cbuf,0xdf); | |
| 2708 emit_d8(cbuf, 0x6C); | |
| 2709 emit_d8(cbuf, 0x24); | |
| 2710 emit_d8(cbuf, 0x00); | |
| 2711 // pop stack | |
| 2712 emit_opcode(cbuf, 0x83); // add SP, #8 | |
| 2713 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 2714 emit_d8(cbuf, 0x8); | |
| 2715 %} | |
| 2716 | |
| 2717 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{ | |
| 2718 // IMUL EDX:EAX,$src1 | |
| 2719 emit_opcode( cbuf, 0xF7 ); | |
| 2720 emit_rm( cbuf, 0x3, 0x5, $src1$$reg ); | |
| 2721 // SAR EDX,$cnt-32 | |
| 2722 int shift_count = ((int)$cnt$$constant) - 32; | |
| 2723 if (shift_count > 0) { | |
| 2724 emit_opcode(cbuf, 0xC1); | |
| 2725 emit_rm(cbuf, 0x3, 7, $dst$$reg ); | |
| 2726 emit_d8(cbuf, shift_count); | |
| 2727 } | |
| 2728 %} | |
| 2729 | |
| 2730 // this version doesn't have add sp, 8 | |
| 2731 enc_class convert_long_double2( eRegL src ) %{ | |
| 2732 // push $src.hi | |
| 2733 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg)); | |
| 2734 // push $src.lo | |
| 2735 emit_opcode(cbuf, 0x50+$src$$reg ); | |
| 2736 // fild 64-bits at [SP] | |
| 2737 emit_opcode(cbuf,0xdf); | |
| 2738 emit_d8(cbuf, 0x6C); | |
| 2739 emit_d8(cbuf, 0x24); | |
| 2740 emit_d8(cbuf, 0x00); | |
| 2741 %} | |
| 2742 | |
| 2743 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{ | |
| 2744 // Basic idea: long = (long)int * (long)int | |
| 2745 // IMUL EDX:EAX, src | |
| 2746 emit_opcode( cbuf, 0xF7 ); | |
| 2747 emit_rm( cbuf, 0x3, 0x5, $src$$reg); | |
| 2748 %} | |
| 2749 | |
| 2750 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{ | |
| 2751 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL) | |
| 2752 // MUL EDX:EAX, src | |
| 2753 emit_opcode( cbuf, 0xF7 ); | |
| 2754 emit_rm( cbuf, 0x3, 0x4, $src$$reg); | |
| 2755 %} | |
| 2756 | |
| 2757 enc_class long_multiply( eADXRegL dst, eRegL src, eRegI tmp ) %{ | |
| 2758 // Basic idea: lo(result) = lo(x_lo * y_lo) | |
| 2759 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) | |
| 2760 // MOV $tmp,$src.lo | |
| 2761 encode_Copy( cbuf, $tmp$$reg, $src$$reg ); | |
| 2762 // IMUL $tmp,EDX | |
| 2763 emit_opcode( cbuf, 0x0F ); | |
| 2764 emit_opcode( cbuf, 0xAF ); | |
| 2765 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2766 // MOV EDX,$src.hi | |
| 2767 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) ); | |
| 2768 // IMUL EDX,EAX | |
| 2769 emit_opcode( cbuf, 0x0F ); | |
| 2770 emit_opcode( cbuf, 0xAF ); | |
| 2771 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg ); | |
| 2772 // ADD $tmp,EDX | |
| 2773 emit_opcode( cbuf, 0x03 ); | |
| 2774 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2775 // MUL EDX:EAX,$src.lo | |
| 2776 emit_opcode( cbuf, 0xF7 ); | |
| 2777 emit_rm( cbuf, 0x3, 0x4, $src$$reg ); | |
| 2778 // ADD EDX,ESI | |
| 2779 emit_opcode( cbuf, 0x03 ); | |
| 2780 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg ); | |
| 2781 %} | |
| 2782 | |
| 2783 enc_class long_multiply_con( eADXRegL dst, immL_127 src, eRegI tmp ) %{ | |
| 2784 // Basic idea: lo(result) = lo(src * y_lo) | |
| 2785 // hi(result) = hi(src * y_lo) + lo(src * y_hi) | |
| 2786 // IMUL $tmp,EDX,$src | |
| 2787 emit_opcode( cbuf, 0x6B ); | |
| 2788 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); | |
| 2789 emit_d8( cbuf, (int)$src$$constant ); | |
| 2790 // MOV EDX,$src | |
| 2791 emit_opcode(cbuf, 0xB8 + EDX_enc); | |
| 2792 emit_d32( cbuf, (int)$src$$constant ); | |
| 2793 // MUL EDX:EAX,EDX | |
| 2794 emit_opcode( cbuf, 0xF7 ); | |
| 2795 emit_rm( cbuf, 0x3, 0x4, EDX_enc ); | |
| 2796 // ADD EDX,ESI | |
| 2797 emit_opcode( cbuf, 0x03 ); | |
| 2798 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg ); | |
| 2799 %} | |
| 2800 | |
| 2801 enc_class long_div( eRegL src1, eRegL src2 ) %{ | |
| 2802 // PUSH src1.hi | |
| 2803 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) ); | |
| 2804 // PUSH src1.lo | |
| 2805 emit_opcode(cbuf, 0x50+$src1$$reg ); | |
| 2806 // PUSH src2.hi | |
| 2807 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) ); | |
| 2808 // PUSH src2.lo | |
| 2809 emit_opcode(cbuf, 0x50+$src2$$reg ); | |
| 2810 // CALL directly to the runtime | |
| 1748 | 2811 cbuf.set_insts_mark(); |
| 0 | 2812 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 2813 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 2814 // Restore stack |
| 2815 emit_opcode(cbuf, 0x83); // add SP, #framesize | |
| 2816 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 2817 emit_d8(cbuf, 4*4); | |
| 2818 %} | |
| 2819 | |
| 2820 enc_class long_mod( eRegL src1, eRegL src2 ) %{ | |
| 2821 // PUSH src1.hi | |
| 2822 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) ); | |
| 2823 // PUSH src1.lo | |
| 2824 emit_opcode(cbuf, 0x50+$src1$$reg ); | |
| 2825 // PUSH src2.hi | |
| 2826 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) ); | |
| 2827 // PUSH src2.lo | |
| 2828 emit_opcode(cbuf, 0x50+$src2$$reg ); | |
| 2829 // CALL directly to the runtime | |
| 1748 | 2830 cbuf.set_insts_mark(); |
| 0 | 2831 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 2832 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 2833 // Restore stack |
| 2834 emit_opcode(cbuf, 0x83); // add SP, #framesize | |
| 2835 emit_rm(cbuf, 0x3, 0x00, ESP_enc); | |
| 2836 emit_d8(cbuf, 4*4); | |
| 2837 %} | |
| 2838 | |
| 2839 enc_class long_cmp_flags0( eRegL src, eRegI tmp ) %{ | |
| 2840 // MOV $tmp,$src.lo | |
| 2841 emit_opcode(cbuf, 0x8B); | |
| 2842 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg); | |
| 2843 // OR $tmp,$src.hi | |
| 2844 emit_opcode(cbuf, 0x0B); | |
| 2845 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg)); | |
| 2846 %} | |
| 2847 | |
| 2848 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{ | |
| 2849 // CMP $src1.lo,$src2.lo | |
| 2850 emit_opcode( cbuf, 0x3B ); | |
| 2851 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 2852 // JNE,s skip | |
| 2853 emit_cc(cbuf, 0x70, 0x5); | |
| 2854 emit_d8(cbuf,2); | |
| 2855 // CMP $src1.hi,$src2.hi | |
| 2856 emit_opcode( cbuf, 0x3B ); | |
| 2857 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); | |
| 2858 %} | |
| 2859 | |
| 2860 enc_class long_cmp_flags2( eRegL src1, eRegL src2, eRegI tmp ) %{ | |
| 2861 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits | |
| 2862 emit_opcode( cbuf, 0x3B ); | |
| 2863 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); | |
| 2864 // MOV $tmp,$src1.hi | |
| 2865 emit_opcode( cbuf, 0x8B ); | |
| 2866 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) ); | |
| 2867 // SBB $tmp,$src2.hi\t! Compute flags for long compare | |
| 2868 emit_opcode( cbuf, 0x1B ); | |
| 2869 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) ); | |
| 2870 %} | |
| 2871 | |
| 2872 enc_class long_cmp_flags3( eRegL src, eRegI tmp ) %{ | |
| 2873 // XOR $tmp,$tmp | |
| 2874 emit_opcode(cbuf,0x33); // XOR | |
| 2875 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg); | |
| 2876 // CMP $tmp,$src.lo | |
| 2877 emit_opcode( cbuf, 0x3B ); | |
| 2878 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg ); | |
| 2879 // SBB $tmp,$src.hi | |
| 2880 emit_opcode( cbuf, 0x1B ); | |
| 2881 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) ); | |
| 2882 %} | |
| 2883 | |
| 2884 // Sniff, sniff... smells like Gnu Superoptimizer | |
| 2885 enc_class neg_long( eRegL dst ) %{ | |
| 2886 emit_opcode(cbuf,0xF7); // NEG hi | |
| 2887 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg)); | |
| 2888 emit_opcode(cbuf,0xF7); // NEG lo | |
| 2889 emit_rm (cbuf,0x3, 0x3, $dst$$reg ); | |
| 2890 emit_opcode(cbuf,0x83); // SBB hi,0 | |
| 2891 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg)); | |
| 2892 emit_d8 (cbuf,0 ); | |
| 2893 %} | |
| 2894 | |
| 2895 | |
| 2896 // Because the transitions from emitted code to the runtime | |
| 2897 // monitorenter/exit helper stubs are so slow it's critical that | |
| 2898 // we inline both the stack-locking fast-path and the inflated fast path. | |
| 2899 // | |
| 2900 // See also: cmpFastLock and cmpFastUnlock. | |
| 2901 // | |
| 2902 // What follows is a specialized inline transliteration of the code | |
| 2903 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat | |
| 2904 // another option would be to emit TrySlowEnter and TrySlowExit methods | |
| 2905 // at startup-time. These methods would accept arguments as | |
| 2906 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure | |
| 2907 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply | |
| 2908 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit. | |
| 2909 // In practice, however, the # of lock sites is bounded and is usually small. | |
| 2910 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer | |
| 2911 // if the processor uses simple bimodal branch predictors keyed by EIP | |
| 2912 // Since the helper routines would be called from multiple synchronization | |
| 2913 // sites. | |
| 2914 // | |
| 2915 // An even better approach would be write "MonitorEnter()" and "MonitorExit()" | |
| 2916 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites | |
| 2917 // to those specialized methods. That'd give us a mostly platform-independent | |
| 2918 // implementation that the JITs could optimize and inline at their pleasure. | |
| 2919 // Done correctly, the only time we'd need to cross to native could would be | |
| 2920 // to park() or unpark() threads. We'd also need a few more unsafe operators | |
| 2921 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and | |
| 2922 // (b) explicit barriers or fence operations. | |
| 2923 // | |
| 2924 // TODO: | |
| 2925 // | |
| 2926 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr). | |
| 2927 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals. | |
| 2928 // Given TLAB allocation, Self is usually manifested in a register, so passing it into | |
| 2929 // the lock operators would typically be faster than reifying Self. | |
| 2930 // | |
| 2931 // * Ideally I'd define the primitives as: | |
| 2932 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED. | |
| 2933 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED | |
| 2934 // Unfortunately ADLC bugs prevent us from expressing the ideal form. | |
| 2935 // Instead, we're stuck with a rather awkward and brittle register assignments below. | |
| 2936 // Furthermore the register assignments are overconstrained, possibly resulting in | |
| 2937 // sub-optimal code near the synchronization site. | |
| 2938 // | |
| 2939 // * Eliminate the sp-proximity tests and just use "== Self" tests instead. | |
| 2940 // Alternately, use a better sp-proximity test. | |
| 2941 // | |
| 2942 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value. | |
| 2943 // Either one is sufficient to uniquely identify a thread. | |
| 2944 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead. | |
| 2945 // | |
| 2946 // * Intrinsify notify() and notifyAll() for the common cases where the | |
| 2947 // object is locked by the calling thread but the waitlist is empty. | |
| 2948 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll(). | |
| 2949 // | |
| 2950 // * use jccb and jmpb instead of jcc and jmp to improve code density. | |
| 2951 // But beware of excessive branch density on AMD Opterons. | |
| 2952 // | |
| 2953 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success | |
| 2954 // or failure of the fast-path. If the fast-path fails then we pass | |
| 2955 // control to the slow-path, typically in C. In Fast_Lock and | |
| 2956 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2 | |
| 2957 // will emit a conditional branch immediately after the node. | |
| 2958 // So we have branches to branches and lots of ICC.ZF games. | |
| 2959 // Instead, it might be better to have C2 pass a "FailureLabel" | |
| 2960 // into Fast_Lock and Fast_Unlock. In the case of success, control | |
| 2961 // will drop through the node. ICC.ZF is undefined at exit. | |
| 2962 // In the case of failure, the node will branch directly to the | |
| 2963 // FailureLabel | |
| 2964 | |
| 2965 | |
| 2966 // obj: object to lock | |
| 2967 // box: on-stack box address (displaced header location) - KILLED | |
| 2968 // rax,: tmp -- KILLED | |
| 2969 // scr: tmp -- KILLED | |
| 2970 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{ | |
| 2971 | |
| 2972 Register objReg = as_Register($obj$$reg); | |
| 2973 Register boxReg = as_Register($box$$reg); | |
| 2974 Register tmpReg = as_Register($tmp$$reg); | |
| 2975 Register scrReg = as_Register($scr$$reg); | |
| 2976 | |
| 2977 // Ensure the register assignents are disjoint | |
| 2978 guarantee (objReg != boxReg, "") ; | |
| 2979 guarantee (objReg != tmpReg, "") ; | |
| 2980 guarantee (objReg != scrReg, "") ; | |
| 2981 guarantee (boxReg != tmpReg, "") ; | |
| 2982 guarantee (boxReg != scrReg, "") ; | |
| 2983 guarantee (tmpReg == as_Register(EAX_enc), "") ; | |
| 2984 | |
| 2985 MacroAssembler masm(&cbuf); | |
| 2986 | |
| 2987 if (_counters != NULL) { | |
| 2988 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr())); | |
| 2989 } | |
| 2990 if (EmitSync & 1) { | |
| 2991 // set box->dhw = unused_mark (3) | |
| 304 | 2992 // Force all sync thru slow-path: slow_enter() and slow_exit() |
| 2993 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ; | |
| 2994 masm.cmpptr (rsp, (int32_t)0) ; | |
| 2995 } else | |
| 2996 if (EmitSync & 2) { | |
| 2997 Label DONE_LABEL ; | |
| 0 | 2998 if (UseBiasedLocking) { |
| 2999 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument. | |
| 3000 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters); | |
| 3001 } | |
| 3002 | |
| 304 | 3003 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword |
| 3004 masm.orptr (tmpReg, 0x1); | |
| 3005 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS | |
| 0 | 3006 if (os::is_MP()) { masm.lock(); } |
| 304 | 3007 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg |
| 0 | 3008 masm.jcc(Assembler::equal, DONE_LABEL); |
| 3009 // Recursive locking | |
| 304 | 3010 masm.subptr(tmpReg, rsp); |
| 3011 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 ); | |
| 3012 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 3013 masm.bind(DONE_LABEL) ; | |
| 3014 } else { | |
| 3015 // Possible cases that we'll encounter in fast_lock | |
| 0 | 3016 // ------------------------------------------------ |
| 3017 // * Inflated | |
| 3018 // -- unlocked | |
| 3019 // -- Locked | |
| 3020 // = by self | |
| 3021 // = by other | |
| 3022 // * biased | |
| 3023 // -- by Self | |
| 3024 // -- by other | |
| 3025 // * neutral | |
| 3026 // * stack-locked | |
| 3027 // -- by self | |
| 3028 // = sp-proximity test hits | |
| 3029 // = sp-proximity test generates false-negative | |
| 3030 // -- by other | |
| 3031 // | |
| 3032 | |
| 3033 Label IsInflated, DONE_LABEL, PopDone ; | |
| 3034 | |
| 3035 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage | |
| 3036 // order to reduce the number of conditional branches in the most common cases. | |
| 3037 // Beware -- there's a subtle invariant that fetch of the markword | |
| 3038 // at [FETCH], below, will never observe a biased encoding (*101b). | |
| 3039 // If this invariant is not held we risk exclusion (safety) failure. | |
|
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|
3040 if (UseBiasedLocking && !UseOptoBiasInlining) { |
| 0 | 3041 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters); |
| 3042 } | |
| 3043 | |
| 304 | 3044 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH] |
| 3045 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral) | |
| 0 | 3046 masm.jccb (Assembler::notZero, IsInflated) ; |
| 3047 | |
| 3048 // Attempt stack-locking ... | |
| 304 | 3049 masm.orptr (tmpReg, 0x1); |
| 3050 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS | |
| 0 | 3051 if (os::is_MP()) { masm.lock(); } |
| 304 | 3052 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg |
| 0 | 3053 if (_counters != NULL) { |
| 3054 masm.cond_inc32(Assembler::equal, | |
| 3055 ExternalAddress((address)_counters->fast_path_entry_count_addr())); | |
| 3056 } | |
| 3057 masm.jccb (Assembler::equal, DONE_LABEL); | |
| 3058 | |
| 3059 // Recursive locking | |
| 304 | 3060 masm.subptr(tmpReg, rsp); |
| 3061 masm.andptr(tmpReg, 0xFFFFF003 ); | |
| 3062 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 0 | 3063 if (_counters != NULL) { |
| 3064 masm.cond_inc32(Assembler::equal, | |
| 3065 ExternalAddress((address)_counters->fast_path_entry_count_addr())); | |
| 3066 } | |
| 3067 masm.jmp (DONE_LABEL) ; | |
| 3068 | |
| 3069 masm.bind (IsInflated) ; | |
| 3070 | |
| 3071 // The object is inflated. | |
| 3072 // | |
| 3073 // TODO-FIXME: eliminate the ugly use of manifest constants: | |
| 3074 // Use markOopDesc::monitor_value instead of "2". | |
| 3075 // use markOop::unused_mark() instead of "3". | |
| 3076 // The tmpReg value is an objectMonitor reference ORed with | |
| 3077 // markOopDesc::monitor_value (2). We can either convert tmpReg to an | |
| 3078 // objectmonitor pointer by masking off the "2" bit or we can just | |
| 3079 // use tmpReg as an objectmonitor pointer but bias the objectmonitor | |
| 3080 // field offsets with "-2" to compensate for and annul the low-order tag bit. | |
| 3081 // | |
| 3082 // I use the latter as it avoids AGI stalls. | |
| 3083 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]" | |
| 3084 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]". | |
| 3085 // | |
| 3086 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2) | |
| 3087 | |
| 3088 // boxReg refers to the on-stack BasicLock in the current frame. | |
| 3089 // We'd like to write: | |
| 3090 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices. | |
| 3091 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers | |
| 3092 // additional latency as we have another ST in the store buffer that must drain. | |
| 3093 | |
| 304 | 3094 if (EmitSync & 8192) { |
| 3095 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty | |
| 3096 masm.get_thread (scrReg) ; | |
| 3097 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] | |
|
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changeset
|
3098 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov |
| 304 | 3099 if (os::is_MP()) { masm.lock(); } |
| 3100 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; | |
| 3101 } else | |
| 0 | 3102 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS |
| 304 | 3103 masm.movptr(scrReg, boxReg) ; |
| 3104 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] | |
| 0 | 3105 |
| 3106 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes | |
| 2479 | 3107 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { |
| 0 | 3108 // prefetchw [eax + Offset(_owner)-2] |
| 304 | 3109 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2)); |
| 0 | 3110 } |
| 3111 | |
| 3112 if ((EmitSync & 64) == 0) { | |
| 3113 // Optimistic form: consider XORL tmpReg,tmpReg | |
|
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changeset
|
3114 masm.movptr(tmpReg, NULL_WORD) ; |
| 304 | 3115 } else { |
| 0 | 3116 // Can suffer RTS->RTO upgrades on shared or cold $ lines |
| 3117 // Test-And-CAS instead of CAS | |
| 304 | 3118 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner |
| 3119 masm.testptr(tmpReg, tmpReg) ; // Locked ? | |
| 3120 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
| 0 | 3121 } |
| 3122 | |
| 3123 // Appears unlocked - try to swing _owner from null to non-null. | |
| 3124 // Ideally, I'd manifest "Self" with get_thread and then attempt | |
| 3125 // to CAS the register containing Self into m->Owner. | |
| 3126 // But we don't have enough registers, so instead we can either try to CAS | |
| 3127 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds | |
| 3128 // we later store "Self" into m->Owner. Transiently storing a stack address | |
| 3129 // (rsp or the address of the box) into m->owner is harmless. | |
| 3130 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. | |
| 3131 if (os::is_MP()) { masm.lock(); } | |
| 304 | 3132 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
| 3133 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3 | |
| 3134 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
| 0 | 3135 masm.get_thread (scrReg) ; // beware: clobbers ICCs |
| 304 | 3136 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ; |
| 3137 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success | |
| 3138 | |
| 3139 // If the CAS fails we can either retry or pass control to the slow-path. | |
| 3140 // We use the latter tactic. | |
| 0 | 3141 // Pass the CAS result in the icc.ZFlag into DONE_LABEL |
| 3142 // If the CAS was successful ... | |
| 3143 // Self has acquired the lock | |
| 3144 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. | |
| 3145 // Intentional fall-through into DONE_LABEL ... | |
| 3146 } else { | |
| 304 | 3147 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty |
| 3148 masm.movptr(boxReg, tmpReg) ; | |
| 0 | 3149 |
| 3150 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes | |
| 2479 | 3151 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { |
| 0 | 3152 // prefetchw [eax + Offset(_owner)-2] |
| 304 | 3153 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2)); |
| 0 | 3154 } |
| 3155 | |
| 3156 if ((EmitSync & 64) == 0) { | |
| 3157 // Optimistic form | |
| 304 | 3158 masm.xorptr (tmpReg, tmpReg) ; |
| 3159 } else { | |
| 0 | 3160 // Can suffer RTS->RTO upgrades on shared or cold $ lines |
| 304 | 3161 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner |
| 3162 masm.testptr(tmpReg, tmpReg) ; // Locked ? | |
| 3163 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
| 0 | 3164 } |
| 3165 | |
| 3166 // Appears unlocked - try to swing _owner from null to non-null. | |
| 3167 // Use either "Self" (in scr) or rsp as thread identity in _owner. | |
| 3168 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. | |
| 3169 masm.get_thread (scrReg) ; | |
| 3170 if (os::is_MP()) { masm.lock(); } | |
| 304 | 3171 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
| 0 | 3172 |
| 3173 // If the CAS fails we can either retry or pass control to the slow-path. | |
| 3174 // We use the latter tactic. | |
| 3175 // Pass the CAS result in the icc.ZFlag into DONE_LABEL | |
| 3176 // If the CAS was successful ... | |
| 3177 // Self has acquired the lock | |
| 3178 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. | |
| 3179 // Intentional fall-through into DONE_LABEL ... | |
| 3180 } | |
| 3181 | |
| 3182 // DONE_LABEL is a hot target - we'd really like to place it at the | |
| 3183 // start of cache line by padding with NOPs. | |
| 3184 // See the AMD and Intel software optimization manuals for the | |
| 3185 // most efficient "long" NOP encodings. | |
| 3186 // Unfortunately none of our alignment mechanisms suffice. | |
| 3187 masm.bind(DONE_LABEL); | |
| 3188 | |
| 3189 // Avoid branch-to-branch on AMD processors | |
| 3190 // This appears to be superstition. | |
| 3191 if (EmitSync & 32) masm.nop() ; | |
| 3192 | |
| 3193 | |
| 3194 // At DONE_LABEL the icc ZFlag is set as follows ... | |
| 3195 // Fast_Unlock uses the same protocol. | |
| 3196 // ZFlag == 1 -> Success | |
| 3197 // ZFlag == 0 -> Failure - force control through the slow-path | |
| 3198 } | |
| 3199 %} | |
| 3200 | |
| 3201 // obj: object to unlock | |
| 3202 // box: box address (displaced header location), killed. Must be EAX. | |
| 3203 // rbx,: killed tmp; cannot be obj nor box. | |
| 3204 // | |
| 3205 // Some commentary on balanced locking: | |
| 3206 // | |
| 3207 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites. | |
| 3208 // Methods that don't have provably balanced locking are forced to run in the | |
| 3209 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock. | |
| 3210 // The interpreter provides two properties: | |
| 3211 // I1: At return-time the interpreter automatically and quietly unlocks any | |
| 3212 // objects acquired the current activation (frame). Recall that the | |
| 3213 // interpreter maintains an on-stack list of locks currently held by | |
| 3214 // a frame. | |
| 3215 // I2: If a method attempts to unlock an object that is not held by the | |
| 3216 // the frame the interpreter throws IMSX. | |
| 3217 // | |
| 3218 // Lets say A(), which has provably balanced locking, acquires O and then calls B(). | |
| 3219 // B() doesn't have provably balanced locking so it runs in the interpreter. | |
| 3220 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O | |
| 3221 // is still locked by A(). | |
| 3222 // | |
| 3223 // The only other source of unbalanced locking would be JNI. The "Java Native Interface: | |
| 3224 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter | |
| 3225 // should not be unlocked by "normal" java-level locking and vice-versa. The specification | |
| 3226 // doesn't specify what will occur if a program engages in such mixed-mode locking, however. | |
| 3227 | |
| 3228 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{ | |
| 3229 | |
| 3230 Register objReg = as_Register($obj$$reg); | |
| 3231 Register boxReg = as_Register($box$$reg); | |
| 3232 Register tmpReg = as_Register($tmp$$reg); | |
| 3233 | |
| 3234 guarantee (objReg != boxReg, "") ; | |
| 3235 guarantee (objReg != tmpReg, "") ; | |
| 3236 guarantee (boxReg != tmpReg, "") ; | |
| 3237 guarantee (boxReg == as_Register(EAX_enc), "") ; | |
| 3238 MacroAssembler masm(&cbuf); | |
| 3239 | |
| 3240 if (EmitSync & 4) { | |
| 3241 // Disable - inhibit all inlining. Force control through the slow-path | |
| 304 | 3242 masm.cmpptr (rsp, 0) ; |
| 3243 } else | |
| 0 | 3244 if (EmitSync & 8) { |
| 3245 Label DONE_LABEL ; | |
| 3246 if (UseBiasedLocking) { | |
| 3247 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); | |
| 3248 } | |
| 3249 // classic stack-locking code ... | |
| 304 | 3250 masm.movptr(tmpReg, Address(boxReg, 0)) ; |
| 3251 masm.testptr(tmpReg, tmpReg) ; | |
| 0 | 3252 masm.jcc (Assembler::zero, DONE_LABEL) ; |
| 3253 if (os::is_MP()) { masm.lock(); } | |
| 304 | 3254 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box |
| 0 | 3255 masm.bind(DONE_LABEL); |
| 3256 } else { | |
| 3257 Label DONE_LABEL, Stacked, CheckSucc, Inflated ; | |
| 3258 | |
| 3259 // Critically, the biased locking test must have precedence over | |
| 3260 // and appear before the (box->dhw == 0) recursive stack-lock test. | |
|
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3261 if (UseBiasedLocking && !UseOptoBiasInlining) { |
| 0 | 3262 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); |
| 3263 } | |
| 304 | 3264 |
| 3265 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header | |
| 3266 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword | |
| 0 | 3267 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock |
| 3268 | |
| 304 | 3269 masm.testptr(tmpReg, 0x02) ; // Inflated? |
| 0 | 3270 masm.jccb (Assembler::zero, Stacked) ; |
| 3271 | |
| 3272 masm.bind (Inflated) ; | |
| 3273 // It's inflated. | |
| 3274 // Despite our balanced locking property we still check that m->_owner == Self | |
| 3275 // as java routines or native JNI code called by this thread might | |
| 3276 // have released the lock. | |
| 3277 // Refer to the comments in synchronizer.cpp for how we might encode extra | |
| 3278 // state in _succ so we can avoid fetching EntryList|cxq. | |
| 3279 // | |
| 3280 // I'd like to add more cases in fast_lock() and fast_unlock() -- | |
| 3281 // such as recursive enter and exit -- but we have to be wary of | |
| 3282 // I$ bloat, T$ effects and BP$ effects. | |
| 3283 // | |
| 3284 // If there's no contention try a 1-0 exit. That is, exit without | |
| 3285 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how | |
| 3286 // we detect and recover from the race that the 1-0 exit admits. | |
| 3287 // | |
| 3288 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier | |
| 3289 // before it STs null into _owner, releasing the lock. Updates | |
| 3290 // to data protected by the critical section must be visible before | |
| 3291 // we drop the lock (and thus before any other thread could acquire | |
| 3292 // the lock and observe the fields protected by the lock). | |
| 3293 // IA32's memory-model is SPO, so STs are ordered with respect to | |
| 3294 // each other and there's no need for an explicit barrier (fence). | |
| 3295 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html. | |
| 3296 | |
| 3297 masm.get_thread (boxReg) ; | |
| 2479 | 3298 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { |
| 304 | 3299 // prefetchw [ebx + Offset(_owner)-2] |
| 3300 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2)); | |
| 0 | 3301 } |
| 3302 | |
| 3303 // Note that we could employ various encoding schemes to reduce | |
| 3304 // the number of loads below (currently 4) to just 2 or 3. | |
| 3305 // Refer to the comments in synchronizer.cpp. | |
| 3306 // In practice the chain of fetches doesn't seem to impact performance, however. | |
| 3307 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) { | |
| 3308 // Attempt to reduce branch density - AMD's branch predictor. | |
| 304 | 3309 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
| 3310 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; | |
| 3311 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; | |
| 3312 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; | |
| 3313 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
|
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3314 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; |
| 304 | 3315 masm.jmpb (DONE_LABEL) ; |
| 3316 } else { | |
| 3317 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; | |
| 3318 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; | |
| 3319 masm.jccb (Assembler::notZero, DONE_LABEL) ; | |
| 3320 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; | |
| 3321 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; | |
| 3322 masm.jccb (Assembler::notZero, CheckSucc) ; | |
|
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|
3323 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; |
| 304 | 3324 masm.jmpb (DONE_LABEL) ; |
| 0 | 3325 } |
| 3326 | |
| 3327 // The Following code fragment (EmitSync & 65536) improves the performance of | |
| 3328 // contended applications and contended synchronization microbenchmarks. | |
| 3329 // Unfortunately the emission of the code - even though not executed - causes regressions | |
| 3330 // in scimark and jetstream, evidently because of $ effects. Replacing the code | |
| 3331 // with an equal number of never-executed NOPs results in the same regression. | |
| 3332 // We leave it off by default. | |
| 3333 | |
| 3334 if ((EmitSync & 65536) != 0) { | |
| 3335 Label LSuccess, LGoSlowPath ; | |
| 3336 | |
| 3337 masm.bind (CheckSucc) ; | |
| 3338 | |
| 3339 // Optional pre-test ... it's safe to elide this | |
| 304 | 3340 if ((EmitSync & 16) == 0) { |
| 3341 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ; | |
| 3342 masm.jccb (Assembler::zero, LGoSlowPath) ; | |
| 0 | 3343 } |
| 3344 | |
| 3345 // We have a classic Dekker-style idiom: | |
| 3346 // ST m->_owner = 0 ; MEMBAR; LD m->_succ | |
| 3347 // There are a number of ways to implement the barrier: | |
| 3348 // (1) lock:andl &m->_owner, 0 | |
| 3349 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form. | |
| 3350 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0 | |
| 3351 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8 | |
| 3352 // (2) If supported, an explicit MFENCE is appealing. | |
| 3353 // In older IA32 processors MFENCE is slower than lock:add or xchg | |
| 3354 // particularly if the write-buffer is full as might be the case if | |
| 3355 // if stores closely precede the fence or fence-equivalent instruction. | |
| 3356 // In more modern implementations MFENCE appears faster, however. | |
| 3357 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack | |
| 3358 // The $lines underlying the top-of-stack should be in M-state. | |
| 3359 // The locked add instruction is serializing, of course. | |
| 3360 // (4) Use xchg, which is serializing | |
| 3361 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works | |
| 3362 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0. | |
| 3363 // The integer condition codes will tell us if succ was 0. | |
| 3364 // Since _succ and _owner should reside in the same $line and | |
| 3365 // we just stored into _owner, it's likely that the $line | |
| 3366 // remains in M-state for the lock:orl. | |
| 3367 // | |
| 3368 // We currently use (3), although it's likely that switching to (2) | |
| 3369 // is correct for the future. | |
| 304 | 3370 |
|
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|
3371 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; |
| 304 | 3372 if (os::is_MP()) { |
| 3373 if (VM_Version::supports_sse2() && 1 == FenceInstruction) { | |
| 3374 masm.mfence(); | |
| 3375 } else { | |
| 3376 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ; | |
| 0 | 3377 } |
| 3378 } | |
| 3379 // Ratify _succ remains non-null | |
| 304 | 3380 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ; |
| 3381 masm.jccb (Assembler::notZero, LSuccess) ; | |
| 3382 | |
| 3383 masm.xorptr(boxReg, boxReg) ; // box is really EAX | |
| 0 | 3384 if (os::is_MP()) { masm.lock(); } |
| 304 | 3385 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); |
| 0 | 3386 masm.jccb (Assembler::notEqual, LSuccess) ; |
| 3387 // Since we're low on registers we installed rsp as a placeholding in _owner. | |
| 3388 // Now install Self over rsp. This is safe as we're transitioning from | |
| 3389 // non-null to non=null | |
| 3390 masm.get_thread (boxReg) ; | |
| 304 | 3391 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ; |
| 0 | 3392 // Intentional fall-through into LGoSlowPath ... |
| 3393 | |
| 304 | 3394 masm.bind (LGoSlowPath) ; |
| 3395 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure | |
| 3396 masm.jmpb (DONE_LABEL) ; | |
| 3397 | |
| 3398 masm.bind (LSuccess) ; | |
| 3399 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success | |
| 3400 masm.jmpb (DONE_LABEL) ; | |
| 0 | 3401 } |
| 3402 | |
| 3403 masm.bind (Stacked) ; | |
| 3404 // It's not inflated and it's not recursively stack-locked and it's not biased. | |
| 3405 // It must be stack-locked. | |
| 3406 // Try to reset the header to displaced header. | |
| 3407 // The "box" value on the stack is stable, so we can reload | |
| 3408 // and be assured we observe the same value as above. | |
| 304 | 3409 masm.movptr(tmpReg, Address(boxReg, 0)) ; |
| 0 | 3410 if (os::is_MP()) { masm.lock(); } |
| 304 | 3411 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box |
| 0 | 3412 // Intention fall-thru into DONE_LABEL |
| 3413 | |
| 3414 | |
| 3415 // DONE_LABEL is a hot target - we'd really like to place it at the | |
| 3416 // start of cache line by padding with NOPs. | |
| 3417 // See the AMD and Intel software optimization manuals for the | |
| 3418 // most efficient "long" NOP encodings. | |
| 3419 // Unfortunately none of our alignment mechanisms suffice. | |
| 3420 if ((EmitSync & 65536) == 0) { | |
| 3421 masm.bind (CheckSucc) ; | |
| 3422 } | |
| 3423 masm.bind(DONE_LABEL); | |
| 3424 | |
| 3425 // Avoid branch to branch on AMD processors | |
| 3426 if (EmitSync & 32768) { masm.nop() ; } | |
| 3427 } | |
| 3428 %} | |
| 3429 | |
|
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3430 |
| 0 | 3431 enc_class enc_pop_rdx() %{ |
| 3432 emit_opcode(cbuf,0x5A); | |
| 3433 %} | |
| 3434 | |
| 3435 enc_class enc_rethrow() %{ | |
| 1748 | 3436 cbuf.set_insts_mark(); |
| 0 | 3437 emit_opcode(cbuf, 0xE9); // jmp entry |
| 1748 | 3438 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4, |
| 0 | 3439 runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 3440 %} | |
| 3441 | |
| 3442 | |
| 3443 // Convert a double to an int. Java semantics require we do complex | |
| 3444 // manglelations in the corner cases. So we set the rounding mode to | |
| 3445 // 'zero', store the darned double down as an int, and reset the | |
| 3446 // rounding mode to 'nearest'. The hardware throws an exception which | |
| 3447 // patches up the correct value directly to the stack. | |
|
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3448 enc_class DPR2I_encoding( regDPR src ) %{ |
| 0 | 3449 // Flip to round-to-zero mode. We attempted to allow invalid-op |
| 3450 // exceptions here, so that a NAN or other corner-case value will | |
| 3451 // thrown an exception (but normal values get converted at full speed). | |
| 3452 // However, I2C adapters and other float-stack manglers leave pending | |
| 3453 // invalid-op exceptions hanging. We would have to clear them before | |
| 3454 // enabling them and that is more expensive than just testing for the | |
| 3455 // invalid value Intel stores down in the corner cases. | |
| 3456 emit_opcode(cbuf,0xD9); // FLDCW trunc | |
| 3457 emit_opcode(cbuf,0x2D); | |
| 3458 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); | |
| 3459 // Allocate a word | |
| 3460 emit_opcode(cbuf,0x83); // SUB ESP,4 | |
| 3461 emit_opcode(cbuf,0xEC); | |
| 3462 emit_d8(cbuf,0x04); | |
| 3463 // Encoding assumes a double has been pushed into FPR0. | |
| 3464 // Store down the double as an int, popping the FPU stack | |
| 3465 emit_opcode(cbuf,0xDB); // FISTP [ESP] | |
| 3466 emit_opcode(cbuf,0x1C); | |
| 3467 emit_d8(cbuf,0x24); | |
| 3468 // Restore the rounding mode; mask the exception | |
| 3469 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode | |
| 3470 emit_opcode(cbuf,0x2D); | |
| 3471 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() | |
| 3472 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() | |
| 3473 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); | |
| 3474 | |
| 3475 // Load the converted int; adjust CPU stack | |
| 3476 emit_opcode(cbuf,0x58); // POP EAX | |
| 3477 emit_opcode(cbuf,0x3D); // CMP EAX,imm | |
| 3478 emit_d32 (cbuf,0x80000000); // 0x80000000 | |
| 3479 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 3480 emit_d8 (cbuf,0x07); // Size of slow_call | |
| 3481 // Push src onto stack slow-path | |
| 3482 emit_opcode(cbuf,0xD9 ); // FLD ST(i) | |
| 3483 emit_d8 (cbuf,0xC0-1+$src$$reg ); | |
| 3484 // CALL directly to the runtime | |
| 1748 | 3485 cbuf.set_insts_mark(); |
| 0 | 3486 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 3487 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 3488 // Carry on here... |
| 3489 %} | |
| 3490 | |
|
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3491 enc_class DPR2L_encoding( regDPR src ) %{ |
| 0 | 3492 emit_opcode(cbuf,0xD9); // FLDCW trunc |
| 3493 emit_opcode(cbuf,0x2D); | |
| 3494 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); | |
| 3495 // Allocate a word | |
| 3496 emit_opcode(cbuf,0x83); // SUB ESP,8 | |
| 3497 emit_opcode(cbuf,0xEC); | |
| 3498 emit_d8(cbuf,0x08); | |
| 3499 // Encoding assumes a double has been pushed into FPR0. | |
| 3500 // Store down the double as a long, popping the FPU stack | |
| 3501 emit_opcode(cbuf,0xDF); // FISTP [ESP] | |
| 3502 emit_opcode(cbuf,0x3C); | |
| 3503 emit_d8(cbuf,0x24); | |
| 3504 // Restore the rounding mode; mask the exception | |
| 3505 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode | |
| 3506 emit_opcode(cbuf,0x2D); | |
| 3507 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() | |
| 3508 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() | |
| 3509 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); | |
| 3510 | |
| 3511 // Load the converted int; adjust CPU stack | |
| 3512 emit_opcode(cbuf,0x58); // POP EAX | |
| 3513 emit_opcode(cbuf,0x5A); // POP EDX | |
| 3514 emit_opcode(cbuf,0x81); // CMP EDX,imm | |
| 3515 emit_d8 (cbuf,0xFA); // rdx | |
| 3516 emit_d32 (cbuf,0x80000000); // 0x80000000 | |
| 3517 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 3518 emit_d8 (cbuf,0x07+4); // Size of slow_call | |
| 3519 emit_opcode(cbuf,0x85); // TEST EAX,EAX | |
| 3520 emit_opcode(cbuf,0xC0); // 2/rax,/rax, | |
| 3521 emit_opcode(cbuf,0x75); // JNE around_slow_call | |
| 3522 emit_d8 (cbuf,0x07); // Size of slow_call | |
| 3523 // Push src onto stack slow-path | |
| 3524 emit_opcode(cbuf,0xD9 ); // FLD ST(i) | |
| 3525 emit_d8 (cbuf,0xC0-1+$src$$reg ); | |
| 3526 // CALL directly to the runtime | |
| 1748 | 3527 cbuf.set_insts_mark(); |
| 0 | 3528 emit_opcode(cbuf,0xE8); // Call into runtime |
| 1748 | 3529 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); |
| 0 | 3530 // Carry on here... |
| 3531 %} | |
| 3532 | |
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3533 enc_class FMul_ST_reg( eRegFPR src1 ) %{ |
| 0 | 3534 // Operand was loaded from memory into fp ST (stack top) |
| 3535 // FMUL ST,$src /* D8 C8+i */ | |
| 3536 emit_opcode(cbuf, 0xD8); | |
| 3537 emit_opcode(cbuf, 0xC8 + $src1$$reg); | |
| 3538 %} | |
| 3539 | |
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3540 enc_class FAdd_ST_reg( eRegFPR src2 ) %{ |
| 0 | 3541 // FADDP ST,src2 /* D8 C0+i */ |
| 3542 emit_opcode(cbuf, 0xD8); | |
| 3543 emit_opcode(cbuf, 0xC0 + $src2$$reg); | |
| 3544 //could use FADDP src2,fpST /* DE C0+i */ | |
| 3545 %} | |
| 3546 | |
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3547 enc_class FAddP_reg_ST( eRegFPR src2 ) %{ |
| 0 | 3548 // FADDP src2,ST /* DE C0+i */ |
| 3549 emit_opcode(cbuf, 0xDE); | |
| 3550 emit_opcode(cbuf, 0xC0 + $src2$$reg); | |
| 3551 %} | |
| 3552 | |
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3553 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{ |
| 0 | 3554 // Operand has been loaded into fp ST (stack top) |
| 3555 // FSUB ST,$src1 | |
| 3556 emit_opcode(cbuf, 0xD8); | |
| 3557 emit_opcode(cbuf, 0xE0 + $src1$$reg); | |
| 3558 | |
| 3559 // FDIV | |
| 3560 emit_opcode(cbuf, 0xD8); | |
| 3561 emit_opcode(cbuf, 0xF0 + $src2$$reg); | |
| 3562 %} | |
| 3563 | |
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3564 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{ |
| 0 | 3565 // Operand was loaded from memory into fp ST (stack top) |
| 3566 // FADD ST,$src /* D8 C0+i */ | |
| 3567 emit_opcode(cbuf, 0xD8); | |
| 3568 emit_opcode(cbuf, 0xC0 + $src1$$reg); | |
| 3569 | |
| 3570 // FMUL ST,src2 /* D8 C*+i */ | |
| 3571 emit_opcode(cbuf, 0xD8); | |
| 3572 emit_opcode(cbuf, 0xC8 + $src2$$reg); | |
| 3573 %} | |
| 3574 | |
| 3575 | |
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3576 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{ |
| 0 | 3577 // Operand was loaded from memory into fp ST (stack top) |
| 3578 // FADD ST,$src /* D8 C0+i */ | |
| 3579 emit_opcode(cbuf, 0xD8); | |
| 3580 emit_opcode(cbuf, 0xC0 + $src1$$reg); | |
| 3581 | |
| 3582 // FMULP src2,ST /* DE C8+i */ | |
| 3583 emit_opcode(cbuf, 0xDE); | |
| 3584 emit_opcode(cbuf, 0xC8 + $src2$$reg); | |
| 3585 %} | |
| 3586 | |
| 3587 // Atomically load the volatile long | |
| 3588 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{ | |
| 3589 emit_opcode(cbuf,0xDF); | |
| 3590 int rm_byte_opcode = 0x05; | |
| 3591 int base = $mem$$base; | |
| 3592 int index = $mem$$index; | |
| 3593 int scale = $mem$$scale; | |
| 3594 int displace = $mem$$disp; | |
| 3595 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals | |
| 3596 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop); | |
| 3597 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp ); | |
| 3598 %} | |
| 3599 | |
| 3600 // Volatile Store Long. Must be atomic, so move it into | |
| 3601 // the FP TOS and then do a 64-bit FIST. Has to probe the | |
| 3602 // target address before the store (for null-ptr checks) | |
| 3603 // so the memory operand is used twice in the encoding. | |
| 3604 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{ | |
| 3605 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp ); | |
| 1748 | 3606 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop |
| 0 | 3607 emit_opcode(cbuf,0xDF); |
| 3608 int rm_byte_opcode = 0x07; | |
| 3609 int base = $mem$$base; | |
| 3610 int index = $mem$$index; | |
| 3611 int scale = $mem$$scale; | |
| 3612 int displace = $mem$$disp; | |
| 3613 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals | |
| 3614 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop); | |
| 3615 %} | |
| 3616 | |
| 3617 // Safepoint Poll. This polls the safepoint page, and causes an | |
| 3618 // exception if it is not readable. Unfortunately, it kills the condition code | |
| 3619 // in the process | |
| 3620 // We current use TESTL [spp],EDI | |
| 3621 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0 | |
| 3622 | |
| 3623 enc_class Safepoint_Poll() %{ | |
| 1748 | 3624 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0); |
| 0 | 3625 emit_opcode(cbuf,0x85); |
| 3626 emit_rm (cbuf, 0x0, 0x7, 0x5); | |
| 3627 emit_d32(cbuf, (intptr_t)os::get_polling_page()); | |
| 3628 %} | |
| 3629 %} | |
| 3630 | |
| 3631 | |
| 3632 //----------FRAME-------------------------------------------------------------- | |
| 3633 // Definition of frame structure and management information. | |
| 3634 // | |
| 3635 // S T A C K L A Y O U T Allocators stack-slot number | |
| 3636 // | (to get allocators register number | |
| 3637 // G Owned by | | v add OptoReg::stack0()) | |
| 3638 // r CALLER | | | |
| 3639 // o | +--------+ pad to even-align allocators stack-slot | |
| 3640 // w V | pad0 | numbers; owned by CALLER | |
| 3641 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
| 3642 // h ^ | in | 5 | |
| 3643 // | | args | 4 Holes in incoming args owned by SELF | |
| 3644 // | | | | 3 | |
| 3645 // | | +--------+ | |
| 3646 // V | | old out| Empty on Intel, window on Sparc | |
| 3647 // | old |preserve| Must be even aligned. | |
| 3648 // | SP-+--------+----> Matcher::_old_SP, even aligned | |
| 3649 // | | in | 3 area for Intel ret address | |
| 3650 // Owned by |preserve| Empty on Sparc. | |
| 3651 // SELF +--------+ | |
| 3652 // | | pad2 | 2 pad to align old SP | |
| 3653 // | +--------+ 1 | |
| 3654 // | | locks | 0 | |
| 3655 // | +--------+----> OptoReg::stack0(), even aligned | |
| 3656 // | | pad1 | 11 pad to align new SP | |
| 3657 // | +--------+ | |
| 3658 // | | | 10 | |
| 3659 // | | spills | 9 spills | |
| 3660 // V | | 8 (pad0 slot for callee) | |
| 3661 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
| 3662 // ^ | out | 7 | |
| 3663 // | | args | 6 Holes in outgoing args owned by CALLEE | |
| 3664 // Owned by +--------+ | |
| 3665 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
| 3666 // | new |preserve| Must be even-aligned. | |
| 3667 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
| 3668 // | | | | |
| 3669 // | |
| 3670 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
| 3671 // known from SELF's arguments and the Java calling convention. | |
| 3672 // Region 6-7 is determined per call site. | |
| 3673 // Note 2: If the calling convention leaves holes in the incoming argument | |
| 3674 // area, those holes are owned by SELF. Holes in the outgoing area | |
| 3675 // are owned by the CALLEE. Holes should not be nessecary in the | |
| 3676 // incoming area, as the Java calling convention is completely under | |
| 3677 // the control of the AD file. Doubles can be sorted and packed to | |
| 3678 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
| 3679 // varargs C calling conventions. | |
| 3680 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
| 3681 // even aligned with pad0 as needed. | |
| 3682 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
| 3683 // region 6-11 is even aligned; it may be padded out more so that | |
| 3684 // the region from SP to FP meets the minimum stack alignment. | |
| 3685 | |
| 3686 frame %{ | |
| 3687 // What direction does stack grow in (assumed to be same for C & Java) | |
| 3688 stack_direction(TOWARDS_LOW); | |
| 3689 | |
| 3690 // These three registers define part of the calling convention | |
| 3691 // between compiled code and the interpreter. | |
| 3692 inline_cache_reg(EAX); // Inline Cache Register | |
| 3693 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter | |
| 3694 | |
| 3695 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] | |
| 3696 cisc_spilling_operand_name(indOffset32); | |
| 3697 | |
| 3698 // Number of stack slots consumed by locking an object | |
| 3699 sync_stack_slots(1); | |
| 3700 | |
| 3701 // Compiled code's Frame Pointer | |
| 3702 frame_pointer(ESP); | |
| 3703 // Interpreter stores its frame pointer in a register which is | |
| 3704 // stored to the stack by I2CAdaptors. | |
| 3705 // I2CAdaptors convert from interpreted java to compiled java. | |
| 3706 interpreter_frame_pointer(EBP); | |
| 3707 | |
| 3708 // Stack alignment requirement | |
| 3709 // Alignment size in bytes (128-bit -> 16 bytes) | |
| 3710 stack_alignment(StackAlignmentInBytes); | |
| 3711 | |
| 3712 // Number of stack slots between incoming argument block and the start of | |
| 3713 // a new frame. The PROLOG must add this many slots to the stack. The | |
| 3714 // EPILOG must remove this many slots. Intel needs one slot for | |
| 3715 // return address and one for rbp, (must save rbp) | |
| 3716 in_preserve_stack_slots(2+VerifyStackAtCalls); | |
| 3717 | |
| 3718 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
| 3719 // for calls to C. Supports the var-args backing area for register parms. | |
| 3720 varargs_C_out_slots_killed(0); | |
| 3721 | |
| 3722 // The after-PROLOG location of the return address. Location of | |
| 3723 // return address specifies a type (REG or STACK) and a number | |
| 3724 // representing the register number (i.e. - use a register name) or | |
| 3725 // stack slot. | |
| 3726 // Ret Addr is on stack in slot 0 if no locks or verification or alignment. | |
| 3727 // Otherwise, it is above the locks and verification slot and alignment word | |
| 3728 return_addr(STACK - 1 + | |
| 4950 | 3729 round_to((Compile::current()->in_preserve_stack_slots() + |
| 3730 Compile::current()->fixed_slots()), | |
| 3731 stack_alignment_in_slots())); | |
| 0 | 3732 |
| 3733 // Body of function which returns an integer array locating | |
| 3734 // arguments either in registers or in stack slots. Passed an array | |
| 3735 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 3736 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 3737 // arguments for a CALLEE. Incoming stack arguments are | |
| 3738 // automatically biased by the preserve_stack_slots field above. | |
| 3739 calling_convention %{ | |
| 3740 // No difference between ingoing/outgoing just pass false | |
| 3741 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); | |
| 3742 %} | |
| 3743 | |
| 3744 | |
| 3745 // Body of function which returns an integer array locating | |
| 3746 // arguments either in registers or in stack slots. Passed an array | |
| 3747 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 3748 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 3749 // arguments for a CALLEE. Incoming stack arguments are | |
| 3750 // automatically biased by the preserve_stack_slots field above. | |
| 3751 c_calling_convention %{ | |
| 3752 // This is obviously always outgoing | |
| 3753 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); | |
| 3754 %} | |
| 3755 | |
| 3756 // Location of C & interpreter return values | |
| 3757 c_return_value %{ | |
| 3758 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
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3759 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; |
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3760 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; |
| 0 | 3761 |
| 3762 // in SSE2+ mode we want to keep the FPU stack clean so pretend | |
| 3763 // that C functions return float and double results in XMM0. | |
| 3764 if( ideal_reg == Op_RegD && UseSSE>=2 ) | |
| 3765 return OptoRegPair(XMM0b_num,XMM0a_num); | |
| 3766 if( ideal_reg == Op_RegF && UseSSE>=2 ) | |
| 3767 return OptoRegPair(OptoReg::Bad,XMM0a_num); | |
| 3768 | |
| 3769 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); | |
| 3770 %} | |
| 3771 | |
| 3772 // Location of return values | |
| 3773 return_value %{ | |
| 3774 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
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3775 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; |
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3776 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; |
| 0 | 3777 if( ideal_reg == Op_RegD && UseSSE>=2 ) |
| 3778 return OptoRegPair(XMM0b_num,XMM0a_num); | |
| 3779 if( ideal_reg == Op_RegF && UseSSE>=1 ) | |
| 3780 return OptoRegPair(OptoReg::Bad,XMM0a_num); | |
| 3781 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); | |
| 3782 %} | |
| 3783 | |
| 3784 %} | |
| 3785 | |
| 3786 //----------ATTRIBUTES--------------------------------------------------------- | |
| 3787 //----------Operand Attributes------------------------------------------------- | |
| 3788 op_attrib op_cost(0); // Required cost attribute | |
| 3789 | |
| 3790 //----------Instruction Attributes--------------------------------------------- | |
| 3791 ins_attrib ins_cost(100); // Required cost attribute | |
| 3792 ins_attrib ins_size(8); // Required size attribute (in bits) | |
| 3793 ins_attrib ins_short_branch(0); // Required flag: is this instruction a | |
| 3794 // non-matching short branch variant of some | |
| 3795 // long branch? | |
| 3796 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2) | |
| 3797 // specifies the alignment that some part of the instruction (not | |
| 3798 // necessarily the start) requires. If > 1, a compute_padding() | |
| 3799 // function must be provided for the instruction | |
| 3800 | |
| 3801 //----------OPERANDS----------------------------------------------------------- | |
| 3802 // Operand definitions must precede instruction definitions for correct parsing | |
| 3803 // in the ADLC because operands constitute user defined types which are used in | |
| 3804 // instruction definitions. | |
| 3805 | |
| 3806 //----------Simple Operands---------------------------------------------------- | |
| 3807 // Immediate Operands | |
| 3808 // Integer Immediate | |
| 3809 operand immI() %{ | |
| 3810 match(ConI); | |
| 3811 | |
| 3812 op_cost(10); | |
| 3813 format %{ %} | |
| 3814 interface(CONST_INTER); | |
| 3815 %} | |
| 3816 | |
| 3817 // Constant for test vs zero | |
| 3818 operand immI0() %{ | |
| 3819 predicate(n->get_int() == 0); | |
| 3820 match(ConI); | |
| 3821 | |
| 3822 op_cost(0); | |
| 3823 format %{ %} | |
| 3824 interface(CONST_INTER); | |
| 3825 %} | |
| 3826 | |
| 3827 // Constant for increment | |
| 3828 operand immI1() %{ | |
| 3829 predicate(n->get_int() == 1); | |
| 3830 match(ConI); | |
| 3831 | |
| 3832 op_cost(0); | |
| 3833 format %{ %} | |
| 3834 interface(CONST_INTER); | |
| 3835 %} | |
| 3836 | |
| 3837 // Constant for decrement | |
| 3838 operand immI_M1() %{ | |
| 3839 predicate(n->get_int() == -1); | |
| 3840 match(ConI); | |
| 3841 | |
| 3842 op_cost(0); | |
| 3843 format %{ %} | |
| 3844 interface(CONST_INTER); | |
| 3845 %} | |
| 3846 | |
| 3847 // Valid scale values for addressing modes | |
| 3848 operand immI2() %{ | |
| 3849 predicate(0 <= n->get_int() && (n->get_int() <= 3)); | |
| 3850 match(ConI); | |
| 3851 | |
| 3852 format %{ %} | |
| 3853 interface(CONST_INTER); | |
| 3854 %} | |
| 3855 | |
| 3856 operand immI8() %{ | |
| 3857 predicate((-128 <= n->get_int()) && (n->get_int() <= 127)); | |
| 3858 match(ConI); | |
| 3859 | |
| 3860 op_cost(5); | |
| 3861 format %{ %} | |
| 3862 interface(CONST_INTER); | |
| 3863 %} | |
| 3864 | |
| 3865 operand immI16() %{ | |
| 3866 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767)); | |
| 3867 match(ConI); | |
| 3868 | |
| 3869 op_cost(10); | |
| 3870 format %{ %} | |
| 3871 interface(CONST_INTER); | |
| 3872 %} | |
| 3873 | |
| 3874 // Constant for long shifts | |
| 3875 operand immI_32() %{ | |
| 3876 predicate( n->get_int() == 32 ); | |
| 3877 match(ConI); | |
| 3878 | |
| 3879 op_cost(0); | |
| 3880 format %{ %} | |
| 3881 interface(CONST_INTER); | |
| 3882 %} | |
| 3883 | |
| 3884 operand immI_1_31() %{ | |
| 3885 predicate( n->get_int() >= 1 && n->get_int() <= 31 ); | |
| 3886 match(ConI); | |
| 3887 | |
| 3888 op_cost(0); | |
| 3889 format %{ %} | |
| 3890 interface(CONST_INTER); | |
| 3891 %} | |
| 3892 | |
| 3893 operand immI_32_63() %{ | |
| 3894 predicate( n->get_int() >= 32 && n->get_int() <= 63 ); | |
| 3895 match(ConI); | |
| 3896 op_cost(0); | |
| 3897 | |
| 3898 format %{ %} | |
| 3899 interface(CONST_INTER); | |
| 3900 %} | |
| 3901 | |
| 219 | 3902 operand immI_1() %{ |
| 3903 predicate( n->get_int() == 1 ); | |
| 3904 match(ConI); | |
| 3905 | |
| 3906 op_cost(0); | |
| 3907 format %{ %} | |
| 3908 interface(CONST_INTER); | |
| 3909 %} | |
| 3910 | |
| 3911 operand immI_2() %{ | |
| 3912 predicate( n->get_int() == 2 ); | |
| 3913 match(ConI); | |
| 3914 | |
| 3915 op_cost(0); | |
| 3916 format %{ %} | |
| 3917 interface(CONST_INTER); | |
| 3918 %} | |
| 3919 | |
| 3920 operand immI_3() %{ | |
| 3921 predicate( n->get_int() == 3 ); | |
| 3922 match(ConI); | |
| 3923 | |
| 3924 op_cost(0); | |
| 3925 format %{ %} | |
| 3926 interface(CONST_INTER); | |
| 3927 %} | |
| 3928 | |
| 0 | 3929 // Pointer Immediate |
| 3930 operand immP() %{ | |
| 3931 match(ConP); | |
| 3932 | |
| 3933 op_cost(10); | |
| 3934 format %{ %} | |
| 3935 interface(CONST_INTER); | |
| 3936 %} | |
| 3937 | |
| 3938 // NULL Pointer Immediate | |
| 3939 operand immP0() %{ | |
| 3940 predicate( n->get_ptr() == 0 ); | |
| 3941 match(ConP); | |
| 3942 op_cost(0); | |
| 3943 | |
| 3944 format %{ %} | |
| 3945 interface(CONST_INTER); | |
| 3946 %} | |
| 3947 | |
| 3948 // Long Immediate | |
| 3949 operand immL() %{ | |
| 3950 match(ConL); | |
| 3951 | |
| 3952 op_cost(20); | |
| 3953 format %{ %} | |
| 3954 interface(CONST_INTER); | |
| 3955 %} | |
| 3956 | |
| 3957 // Long Immediate zero | |
| 3958 operand immL0() %{ | |
| 3959 predicate( n->get_long() == 0L ); | |
| 3960 match(ConL); | |
| 3961 op_cost(0); | |
| 3962 | |
| 3963 format %{ %} | |
| 3964 interface(CONST_INTER); | |
| 3965 %} | |
| 3966 | |
| 403 | 3967 // Long Immediate zero |
| 3968 operand immL_M1() %{ | |
| 3969 predicate( n->get_long() == -1L ); | |
| 3970 match(ConL); | |
| 3971 op_cost(0); | |
| 3972 | |
| 3973 format %{ %} | |
| 3974 interface(CONST_INTER); | |
| 3975 %} | |
| 3976 | |
| 0 | 3977 // Long immediate from 0 to 127. |
| 3978 // Used for a shorter form of long mul by 10. | |
| 3979 operand immL_127() %{ | |
| 3980 predicate((0 <= n->get_long()) && (n->get_long() <= 127)); | |
| 3981 match(ConL); | |
| 3982 op_cost(0); | |
| 3983 | |
| 3984 format %{ %} | |
| 3985 interface(CONST_INTER); | |
| 3986 %} | |
| 3987 | |
| 3988 // Long Immediate: low 32-bit mask | |
| 3989 operand immL_32bits() %{ | |
| 3990 predicate(n->get_long() == 0xFFFFFFFFL); | |
| 3991 match(ConL); | |
| 3992 op_cost(0); | |
| 3993 | |
| 3994 format %{ %} | |
| 3995 interface(CONST_INTER); | |
| 3996 %} | |
| 3997 | |
| 3998 // Long Immediate: low 32-bit mask | |
| 3999 operand immL32() %{ | |
| 4000 predicate(n->get_long() == (int)(n->get_long())); | |
| 4001 match(ConL); | |
| 4002 op_cost(20); | |
| 4003 | |
| 4004 format %{ %} | |
| 4005 interface(CONST_INTER); | |
| 4006 %} | |
| 4007 | |
| 4008 //Double Immediate zero | |
|
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4009 operand immDPR0() %{ |
| 0 | 4010 // Do additional (and counter-intuitive) test against NaN to work around VC++ |
| 4011 // bug that generates code such that NaNs compare equal to 0.0 | |
| 4012 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) ); | |
| 4013 match(ConD); | |
| 4014 | |
| 4015 op_cost(5); | |
| 4016 format %{ %} | |
| 4017 interface(CONST_INTER); | |
| 4018 %} | |
| 4019 | |
| 2008 | 4020 // Double Immediate one |
|
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4021 operand immDPR1() %{ |
| 0 | 4022 predicate( UseSSE<=1 && n->getd() == 1.0 ); |
| 4023 match(ConD); | |
| 4024 | |
| 4025 op_cost(5); | |
| 4026 format %{ %} | |
| 4027 interface(CONST_INTER); | |
| 4028 %} | |
| 4029 | |
| 4030 // Double Immediate | |
|
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4031 operand immDPR() %{ |
| 0 | 4032 predicate(UseSSE<=1); |
| 4033 match(ConD); | |
| 4034 | |
| 4035 op_cost(5); | |
| 4036 format %{ %} | |
| 4037 interface(CONST_INTER); | |
| 4038 %} | |
| 4039 | |
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4040 operand immD() %{ |
| 0 | 4041 predicate(UseSSE>=2); |
| 4042 match(ConD); | |
| 4043 | |
| 4044 op_cost(5); | |
| 4045 format %{ %} | |
| 4046 interface(CONST_INTER); | |
| 4047 %} | |
| 4048 | |
| 4049 // Double Immediate zero | |
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4050 operand immD0() %{ |
| 0 | 4051 // Do additional (and counter-intuitive) test against NaN to work around VC++ |
| 4052 // bug that generates code such that NaNs compare equal to 0.0 AND do not | |
| 4053 // compare equal to -0.0. | |
| 4054 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 ); | |
| 4055 match(ConD); | |
| 4056 | |
| 4057 format %{ %} | |
| 4058 interface(CONST_INTER); | |
| 4059 %} | |
| 4060 | |
| 4061 // Float Immediate zero | |
|
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4062 operand immFPR0() %{ |
| 2008 | 4063 predicate(UseSSE == 0 && n->getf() == 0.0F); |
| 4064 match(ConF); | |
| 4065 | |
| 4066 op_cost(5); | |
| 4067 format %{ %} | |
| 4068 interface(CONST_INTER); | |
| 4069 %} | |
| 4070 | |
| 4071 // Float Immediate one | |
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4072 operand immFPR1() %{ |
| 2008 | 4073 predicate(UseSSE == 0 && n->getf() == 1.0F); |
| 0 | 4074 match(ConF); |
| 4075 | |
| 4076 op_cost(5); | |
| 4077 format %{ %} | |
| 4078 interface(CONST_INTER); | |
| 4079 %} | |
| 4080 | |
| 4081 // Float Immediate | |
|
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4082 operand immFPR() %{ |
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4083 predicate( UseSSE == 0 ); |
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4084 match(ConF); |
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4085 |
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4086 op_cost(5); |
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4087 format %{ %} |
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4088 interface(CONST_INTER); |
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4089 %} |
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4090 |
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4091 // Float Immediate |
| 0 | 4092 operand immF() %{ |
| 4093 predicate(UseSSE >= 1); | |
| 4094 match(ConF); | |
| 4095 | |
| 4096 op_cost(5); | |
| 4097 format %{ %} | |
| 4098 interface(CONST_INTER); | |
| 4099 %} | |
| 4100 | |
| 4101 // Float Immediate zero. Zero and not -0.0 | |
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4102 operand immF0() %{ |
| 0 | 4103 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 ); |
| 4104 match(ConF); | |
| 4105 | |
| 4106 op_cost(5); | |
| 4107 format %{ %} | |
| 4108 interface(CONST_INTER); | |
| 4109 %} | |
| 4110 | |
| 4111 // Immediates for special shifts (sign extend) | |
| 4112 | |
| 4113 // Constants for increment | |
| 4114 operand immI_16() %{ | |
| 4115 predicate( n->get_int() == 16 ); | |
| 4116 match(ConI); | |
| 4117 | |
| 4118 format %{ %} | |
| 4119 interface(CONST_INTER); | |
| 4120 %} | |
| 4121 | |
| 4122 operand immI_24() %{ | |
| 4123 predicate( n->get_int() == 24 ); | |
| 4124 match(ConI); | |
| 4125 | |
| 4126 format %{ %} | |
| 4127 interface(CONST_INTER); | |
| 4128 %} | |
| 4129 | |
| 4130 // Constant for byte-wide masking | |
| 4131 operand immI_255() %{ | |
| 4132 predicate( n->get_int() == 255 ); | |
| 4133 match(ConI); | |
| 4134 | |
| 4135 format %{ %} | |
| 4136 interface(CONST_INTER); | |
| 4137 %} | |
| 4138 | |
| 785 | 4139 // Constant for short-wide masking |
| 4140 operand immI_65535() %{ | |
| 4141 predicate(n->get_int() == 65535); | |
| 4142 match(ConI); | |
| 4143 | |
| 4144 format %{ %} | |
| 4145 interface(CONST_INTER); | |
| 4146 %} | |
| 4147 | |
| 0 | 4148 // Register Operands |
| 4149 // Integer Register | |
| 4150 operand eRegI() %{ | |
| 4151 constraint(ALLOC_IN_RC(e_reg)); | |
| 4152 match(RegI); | |
| 4153 match(xRegI); | |
| 4154 match(eAXRegI); | |
| 4155 match(eBXRegI); | |
| 4156 match(eCXRegI); | |
| 4157 match(eDXRegI); | |
| 4158 match(eDIRegI); | |
| 4159 match(eSIRegI); | |
| 4160 | |
| 4161 format %{ %} | |
| 4162 interface(REG_INTER); | |
| 4163 %} | |
| 4164 | |
| 4165 // Subset of Integer Register | |
| 4166 operand xRegI(eRegI reg) %{ | |
| 4167 constraint(ALLOC_IN_RC(x_reg)); | |
| 4168 match(reg); | |
| 4169 match(eAXRegI); | |
| 4170 match(eBXRegI); | |
| 4171 match(eCXRegI); | |
| 4172 match(eDXRegI); | |
| 4173 | |
| 4174 format %{ %} | |
| 4175 interface(REG_INTER); | |
| 4176 %} | |
| 4177 | |
| 4178 // Special Registers | |
| 4179 operand eAXRegI(xRegI reg) %{ | |
| 4180 constraint(ALLOC_IN_RC(eax_reg)); | |
| 4181 match(reg); | |
| 4182 match(eRegI); | |
| 4183 | |
| 4184 format %{ "EAX" %} | |
| 4185 interface(REG_INTER); | |
| 4186 %} | |
| 4187 | |
| 4188 // Special Registers | |
| 4189 operand eBXRegI(xRegI reg) %{ | |
| 4190 constraint(ALLOC_IN_RC(ebx_reg)); | |
| 4191 match(reg); | |
| 4192 match(eRegI); | |
| 4193 | |
| 4194 format %{ "EBX" %} | |
| 4195 interface(REG_INTER); | |
| 4196 %} | |
| 4197 | |
| 4198 operand eCXRegI(xRegI reg) %{ | |
| 4199 constraint(ALLOC_IN_RC(ecx_reg)); | |
| 4200 match(reg); | |
| 4201 match(eRegI); | |
| 4202 | |
| 4203 format %{ "ECX" %} | |
| 4204 interface(REG_INTER); | |
| 4205 %} | |
| 4206 | |
| 4207 operand eDXRegI(xRegI reg) %{ | |
| 4208 constraint(ALLOC_IN_RC(edx_reg)); | |
| 4209 match(reg); | |
| 4210 match(eRegI); | |
| 4211 | |
| 4212 format %{ "EDX" %} | |
| 4213 interface(REG_INTER); | |
| 4214 %} | |
| 4215 | |
| 4216 operand eDIRegI(xRegI reg) %{ | |
| 4217 constraint(ALLOC_IN_RC(edi_reg)); | |
| 4218 match(reg); | |
| 4219 match(eRegI); | |
| 4220 | |
| 4221 format %{ "EDI" %} | |
| 4222 interface(REG_INTER); | |
| 4223 %} | |
| 4224 | |
| 4225 operand naxRegI() %{ | |
| 4226 constraint(ALLOC_IN_RC(nax_reg)); | |
| 4227 match(RegI); | |
| 4228 match(eCXRegI); | |
| 4229 match(eDXRegI); | |
| 4230 match(eSIRegI); | |
| 4231 match(eDIRegI); | |
| 4232 | |
| 4233 format %{ %} | |
| 4234 interface(REG_INTER); | |
| 4235 %} | |
| 4236 | |
| 4237 operand nadxRegI() %{ | |
| 4238 constraint(ALLOC_IN_RC(nadx_reg)); | |
| 4239 match(RegI); | |
| 4240 match(eBXRegI); | |
| 4241 match(eCXRegI); | |
| 4242 match(eSIRegI); | |
| 4243 match(eDIRegI); | |
| 4244 | |
| 4245 format %{ %} | |
| 4246 interface(REG_INTER); | |
| 4247 %} | |
| 4248 | |
| 4249 operand ncxRegI() %{ | |
| 4250 constraint(ALLOC_IN_RC(ncx_reg)); | |
| 4251 match(RegI); | |
| 4252 match(eAXRegI); | |
| 4253 match(eDXRegI); | |
| 4254 match(eSIRegI); | |
| 4255 match(eDIRegI); | |
| 4256 | |
| 4257 format %{ %} | |
| 4258 interface(REG_INTER); | |
| 4259 %} | |
| 4260 | |
| 4261 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg | |
| 4262 // // | |
| 4263 operand eSIRegI(xRegI reg) %{ | |
| 4264 constraint(ALLOC_IN_RC(esi_reg)); | |
| 4265 match(reg); | |
| 4266 match(eRegI); | |
| 4267 | |
| 4268 format %{ "ESI" %} | |
| 4269 interface(REG_INTER); | |
| 4270 %} | |
| 4271 | |
| 4272 // Pointer Register | |
| 4273 operand anyRegP() %{ | |
| 4274 constraint(ALLOC_IN_RC(any_reg)); | |
| 4275 match(RegP); | |
| 4276 match(eAXRegP); | |
| 4277 match(eBXRegP); | |
| 4278 match(eCXRegP); | |
| 4279 match(eDIRegP); | |
| 4280 match(eRegP); | |
| 4281 | |
| 4282 format %{ %} | |
| 4283 interface(REG_INTER); | |
| 4284 %} | |
| 4285 | |
| 4286 operand eRegP() %{ | |
| 4287 constraint(ALLOC_IN_RC(e_reg)); | |
| 4288 match(RegP); | |
| 4289 match(eAXRegP); | |
| 4290 match(eBXRegP); | |
| 4291 match(eCXRegP); | |
| 4292 match(eDIRegP); | |
| 4293 | |
| 4294 format %{ %} | |
| 4295 interface(REG_INTER); | |
| 4296 %} | |
| 4297 | |
| 4298 // On windows95, EBP is not safe to use for implicit null tests. | |
| 4299 operand eRegP_no_EBP() %{ | |
| 4300 constraint(ALLOC_IN_RC(e_reg_no_rbp)); | |
| 4301 match(RegP); | |
| 4302 match(eAXRegP); | |
| 4303 match(eBXRegP); | |
| 4304 match(eCXRegP); | |
| 4305 match(eDIRegP); | |
| 4306 | |
| 4307 op_cost(100); | |
| 4308 format %{ %} | |
| 4309 interface(REG_INTER); | |
| 4310 %} | |
| 4311 | |
| 4312 operand naxRegP() %{ | |
| 4313 constraint(ALLOC_IN_RC(nax_reg)); | |
| 4314 match(RegP); | |
| 4315 match(eBXRegP); | |
| 4316 match(eDXRegP); | |
| 4317 match(eCXRegP); | |
| 4318 match(eSIRegP); | |
| 4319 match(eDIRegP); | |
| 4320 | |
| 4321 format %{ %} | |
| 4322 interface(REG_INTER); | |
| 4323 %} | |
| 4324 | |
| 4325 operand nabxRegP() %{ | |
| 4326 constraint(ALLOC_IN_RC(nabx_reg)); | |
| 4327 match(RegP); | |
| 4328 match(eCXRegP); | |
| 4329 match(eDXRegP); | |
| 4330 match(eSIRegP); | |
| 4331 match(eDIRegP); | |
| 4332 | |
| 4333 format %{ %} | |
| 4334 interface(REG_INTER); | |
| 4335 %} | |
| 4336 | |
| 4337 operand pRegP() %{ | |
| 4338 constraint(ALLOC_IN_RC(p_reg)); | |
| 4339 match(RegP); | |
| 4340 match(eBXRegP); | |
| 4341 match(eDXRegP); | |
| 4342 match(eSIRegP); | |
| 4343 match(eDIRegP); | |
| 4344 | |
| 4345 format %{ %} | |
| 4346 interface(REG_INTER); | |
| 4347 %} | |
| 4348 | |
| 4349 // Special Registers | |
| 4350 // Return a pointer value | |
| 4351 operand eAXRegP(eRegP reg) %{ | |
| 4352 constraint(ALLOC_IN_RC(eax_reg)); | |
| 4353 match(reg); | |
| 4354 format %{ "EAX" %} | |
| 4355 interface(REG_INTER); | |
| 4356 %} | |
| 4357 | |
| 4358 // Used in AtomicAdd | |
| 4359 operand eBXRegP(eRegP reg) %{ | |
| 4360 constraint(ALLOC_IN_RC(ebx_reg)); | |
| 4361 match(reg); | |
| 4362 format %{ "EBX" %} | |
| 4363 interface(REG_INTER); | |
| 4364 %} | |
| 4365 | |
| 4366 // Tail-call (interprocedural jump) to interpreter | |
| 4367 operand eCXRegP(eRegP reg) %{ | |
| 4368 constraint(ALLOC_IN_RC(ecx_reg)); | |
| 4369 match(reg); | |
| 4370 format %{ "ECX" %} | |
| 4371 interface(REG_INTER); | |
| 4372 %} | |
| 4373 | |
| 4374 operand eSIRegP(eRegP reg) %{ | |
| 4375 constraint(ALLOC_IN_RC(esi_reg)); | |
| 4376 match(reg); | |
| 4377 format %{ "ESI" %} | |
| 4378 interface(REG_INTER); | |
| 4379 %} | |
| 4380 | |
| 4381 // Used in rep stosw | |
| 4382 operand eDIRegP(eRegP reg) %{ | |
| 4383 constraint(ALLOC_IN_RC(edi_reg)); | |
| 4384 match(reg); | |
| 4385 format %{ "EDI" %} | |
| 4386 interface(REG_INTER); | |
| 4387 %} | |
| 4388 | |
| 4389 operand eBPRegP() %{ | |
| 4390 constraint(ALLOC_IN_RC(ebp_reg)); | |
| 4391 match(RegP); | |
| 4392 format %{ "EBP" %} | |
| 4393 interface(REG_INTER); | |
| 4394 %} | |
| 4395 | |
| 4396 operand eRegL() %{ | |
| 4397 constraint(ALLOC_IN_RC(long_reg)); | |
| 4398 match(RegL); | |
| 4399 match(eADXRegL); | |
| 4400 | |
| 4401 format %{ %} | |
| 4402 interface(REG_INTER); | |
| 4403 %} | |
| 4404 | |
| 4405 operand eADXRegL( eRegL reg ) %{ | |
| 4406 constraint(ALLOC_IN_RC(eadx_reg)); | |
| 4407 match(reg); | |
| 4408 | |
| 4409 format %{ "EDX:EAX" %} | |
| 4410 interface(REG_INTER); | |
| 4411 %} | |
| 4412 | |
| 4413 operand eBCXRegL( eRegL reg ) %{ | |
| 4414 constraint(ALLOC_IN_RC(ebcx_reg)); | |
| 4415 match(reg); | |
| 4416 | |
| 4417 format %{ "EBX:ECX" %} | |
| 4418 interface(REG_INTER); | |
| 4419 %} | |
| 4420 | |
| 4421 // Special case for integer high multiply | |
| 4422 operand eADXRegL_low_only() %{ | |
| 4423 constraint(ALLOC_IN_RC(eadx_reg)); | |
| 4424 match(RegL); | |
| 4425 | |
| 4426 format %{ "EAX" %} | |
| 4427 interface(REG_INTER); | |
| 4428 %} | |
| 4429 | |
| 4430 // Flags register, used as output of compare instructions | |
| 4431 operand eFlagsReg() %{ | |
| 4432 constraint(ALLOC_IN_RC(int_flags)); | |
| 4433 match(RegFlags); | |
| 4434 | |
| 4435 format %{ "EFLAGS" %} | |
| 4436 interface(REG_INTER); | |
| 4437 %} | |
| 4438 | |
| 4439 // Flags register, used as output of FLOATING POINT compare instructions | |
| 4440 operand eFlagsRegU() %{ | |
| 4441 constraint(ALLOC_IN_RC(int_flags)); | |
| 4442 match(RegFlags); | |
| 4443 | |
| 4444 format %{ "EFLAGS_U" %} | |
| 4445 interface(REG_INTER); | |
| 4446 %} | |
| 4447 | |
|
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4448 operand eFlagsRegUCF() %{ |
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4449 constraint(ALLOC_IN_RC(int_flags)); |
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4450 match(RegFlags); |
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4451 predicate(false); |
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4452 |
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4453 format %{ "EFLAGS_U_CF" %} |
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4454 interface(REG_INTER); |
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4455 %} |
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4456 |
| 0 | 4457 // Condition Code Register used by long compare |
| 4458 operand flagsReg_long_LTGE() %{ | |
| 4459 constraint(ALLOC_IN_RC(int_flags)); | |
| 4460 match(RegFlags); | |
| 4461 format %{ "FLAGS_LTGE" %} | |
| 4462 interface(REG_INTER); | |
| 4463 %} | |
| 4464 operand flagsReg_long_EQNE() %{ | |
| 4465 constraint(ALLOC_IN_RC(int_flags)); | |
| 4466 match(RegFlags); | |
| 4467 format %{ "FLAGS_EQNE" %} | |
| 4468 interface(REG_INTER); | |
| 4469 %} | |
| 4470 operand flagsReg_long_LEGT() %{ | |
| 4471 constraint(ALLOC_IN_RC(int_flags)); | |
| 4472 match(RegFlags); | |
| 4473 format %{ "FLAGS_LEGT" %} | |
| 4474 interface(REG_INTER); | |
| 4475 %} | |
| 4476 | |
| 4477 // Float register operands | |
|
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4478 operand regDPR() %{ |
| 0 | 4479 predicate( UseSSE < 2 ); |
| 4480 constraint(ALLOC_IN_RC(dbl_reg)); | |
| 4481 match(RegD); | |
| 4482 match(regDPR1); | |
| 4483 match(regDPR2); | |
| 4484 format %{ %} | |
| 4485 interface(REG_INTER); | |
| 4486 %} | |
| 4487 | |
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4488 operand regDPR1(regDPR reg) %{ |
| 0 | 4489 predicate( UseSSE < 2 ); |
| 4490 constraint(ALLOC_IN_RC(dbl_reg0)); | |
| 4491 match(reg); | |
| 4492 format %{ "FPR1" %} | |
| 4493 interface(REG_INTER); | |
| 4494 %} | |
| 4495 | |
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4496 operand regDPR2(regDPR reg) %{ |
| 0 | 4497 predicate( UseSSE < 2 ); |
| 4498 constraint(ALLOC_IN_RC(dbl_reg1)); | |
| 4499 match(reg); | |
| 4500 format %{ "FPR2" %} | |
| 4501 interface(REG_INTER); | |
| 4502 %} | |
| 4503 | |
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4504 operand regnotDPR1(regDPR reg) %{ |
| 0 | 4505 predicate( UseSSE < 2 ); |
| 4506 constraint(ALLOC_IN_RC(dbl_notreg0)); | |
| 4507 match(reg); | |
| 4508 format %{ %} | |
| 4509 interface(REG_INTER); | |
| 4510 %} | |
| 4511 | |
| 4512 // XMM Double register operands | |
|
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4513 operand regD() %{ |
| 0 | 4514 predicate( UseSSE>=2 ); |
| 4515 constraint(ALLOC_IN_RC(xdb_reg)); | |
| 4516 match(RegD); | |
|
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4517 match(regD6); |
|
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|
4518 match(regD7); |
| 0 | 4519 format %{ %} |
| 4520 interface(REG_INTER); | |
| 4521 %} | |
| 4522 | |
| 4523 // XMM6 double register operands | |
|
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|
4524 operand regD6(regD reg) %{ |
| 0 | 4525 predicate( UseSSE>=2 ); |
| 4526 constraint(ALLOC_IN_RC(xdb_reg6)); | |
| 4527 match(reg); | |
| 4528 format %{ "XMM6" %} | |
| 4529 interface(REG_INTER); | |
| 4530 %} | |
| 4531 | |
| 4532 // XMM7 double register operands | |
|
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4533 operand regD7(regD reg) %{ |
| 0 | 4534 predicate( UseSSE>=2 ); |
| 4535 constraint(ALLOC_IN_RC(xdb_reg7)); | |
| 4536 match(reg); | |
| 4537 format %{ "XMM7" %} | |
| 4538 interface(REG_INTER); | |
| 4539 %} | |
| 4540 | |
| 4541 // Float register operands | |
|
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|
4542 operand regFPR() %{ |
| 0 | 4543 predicate( UseSSE < 2 ); |
| 4544 constraint(ALLOC_IN_RC(flt_reg)); | |
| 4545 match(RegF); | |
| 4546 match(regFPR1); | |
| 4547 format %{ %} | |
| 4548 interface(REG_INTER); | |
| 4549 %} | |
| 4550 | |
| 4551 // Float register operands | |
|
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|
4552 operand regFPR1(regFPR reg) %{ |
| 0 | 4553 predicate( UseSSE < 2 ); |
| 4554 constraint(ALLOC_IN_RC(flt_reg0)); | |
| 4555 match(reg); | |
| 4556 format %{ "FPR1" %} | |
| 4557 interface(REG_INTER); | |
| 4558 %} | |
| 4559 | |
| 4560 // XMM register operands | |
|
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|
4561 operand regF() %{ |
| 0 | 4562 predicate( UseSSE>=1 ); |
| 4563 constraint(ALLOC_IN_RC(xmm_reg)); | |
| 4564 match(RegF); | |
| 4565 format %{ %} | |
| 4566 interface(REG_INTER); | |
| 4567 %} | |
| 4568 | |
| 4569 | |
| 4570 //----------Memory Operands---------------------------------------------------- | |
| 4571 // Direct Memory Operand | |
| 4572 operand direct(immP addr) %{ | |
| 4573 match(addr); | |
| 4574 | |
| 4575 format %{ "[$addr]" %} | |
| 4576 interface(MEMORY_INTER) %{ | |
| 4577 base(0xFFFFFFFF); | |
| 4578 index(0x4); | |
| 4579 scale(0x0); | |
| 4580 disp($addr); | |
| 4581 %} | |
| 4582 %} | |
| 4583 | |
| 4584 // Indirect Memory Operand | |
| 4585 operand indirect(eRegP reg) %{ | |
| 4586 constraint(ALLOC_IN_RC(e_reg)); | |
| 4587 match(reg); | |
| 4588 | |
| 4589 format %{ "[$reg]" %} | |
| 4590 interface(MEMORY_INTER) %{ | |
| 4591 base($reg); | |
| 4592 index(0x4); | |
| 4593 scale(0x0); | |
| 4594 disp(0x0); | |
| 4595 %} | |
| 4596 %} | |
| 4597 | |
| 4598 // Indirect Memory Plus Short Offset Operand | |
| 4599 operand indOffset8(eRegP reg, immI8 off) %{ | |
| 4600 match(AddP reg off); | |
| 4601 | |
| 4602 format %{ "[$reg + $off]" %} | |
| 4603 interface(MEMORY_INTER) %{ | |
| 4604 base($reg); | |
| 4605 index(0x4); | |
| 4606 scale(0x0); | |
| 4607 disp($off); | |
| 4608 %} | |
| 4609 %} | |
| 4610 | |
| 4611 // Indirect Memory Plus Long Offset Operand | |
| 4612 operand indOffset32(eRegP reg, immI off) %{ | |
| 4613 match(AddP reg off); | |
| 4614 | |
| 4615 format %{ "[$reg + $off]" %} | |
| 4616 interface(MEMORY_INTER) %{ | |
| 4617 base($reg); | |
| 4618 index(0x4); | |
| 4619 scale(0x0); | |
| 4620 disp($off); | |
| 4621 %} | |
| 4622 %} | |
| 4623 | |
| 4624 // Indirect Memory Plus Long Offset Operand | |
| 4625 operand indOffset32X(eRegI reg, immP off) %{ | |
| 4626 match(AddP off reg); | |
| 4627 | |
| 4628 format %{ "[$reg + $off]" %} | |
| 4629 interface(MEMORY_INTER) %{ | |
| 4630 base($reg); | |
| 4631 index(0x4); | |
| 4632 scale(0x0); | |
| 4633 disp($off); | |
| 4634 %} | |
| 4635 %} | |
| 4636 | |
| 4637 // Indirect Memory Plus Index Register Plus Offset Operand | |
| 4638 operand indIndexOffset(eRegP reg, eRegI ireg, immI off) %{ | |
| 4639 match(AddP (AddP reg ireg) off); | |
| 4640 | |
| 4641 op_cost(10); | |
| 4642 format %{"[$reg + $off + $ireg]" %} | |
| 4643 interface(MEMORY_INTER) %{ | |
| 4644 base($reg); | |
| 4645 index($ireg); | |
| 4646 scale(0x0); | |
| 4647 disp($off); | |
| 4648 %} | |
| 4649 %} | |
| 4650 | |
| 4651 // Indirect Memory Plus Index Register Plus Offset Operand | |
| 4652 operand indIndex(eRegP reg, eRegI ireg) %{ | |
| 4653 match(AddP reg ireg); | |
| 4654 | |
| 4655 op_cost(10); | |
| 4656 format %{"[$reg + $ireg]" %} | |
| 4657 interface(MEMORY_INTER) %{ | |
| 4658 base($reg); | |
| 4659 index($ireg); | |
| 4660 scale(0x0); | |
| 4661 disp(0x0); | |
| 4662 %} | |
| 4663 %} | |
| 4664 | |
| 4665 // // ------------------------------------------------------------------------- | |
| 4666 // // 486 architecture doesn't support "scale * index + offset" with out a base | |
| 4667 // // ------------------------------------------------------------------------- | |
| 4668 // // Scaled Memory Operands | |
| 4669 // // Indirect Memory Times Scale Plus Offset Operand | |
| 4670 // operand indScaleOffset(immP off, eRegI ireg, immI2 scale) %{ | |
| 4671 // match(AddP off (LShiftI ireg scale)); | |
| 4672 // | |
| 4673 // op_cost(10); | |
| 4674 // format %{"[$off + $ireg << $scale]" %} | |
| 4675 // interface(MEMORY_INTER) %{ | |
| 4676 // base(0x4); | |
| 4677 // index($ireg); | |
| 4678 // scale($scale); | |
| 4679 // disp($off); | |
| 4680 // %} | |
| 4681 // %} | |
| 4682 | |
| 4683 // Indirect Memory Times Scale Plus Index Register | |
| 4684 operand indIndexScale(eRegP reg, eRegI ireg, immI2 scale) %{ | |
| 4685 match(AddP reg (LShiftI ireg scale)); | |
| 4686 | |
| 4687 op_cost(10); | |
| 4688 format %{"[$reg + $ireg << $scale]" %} | |
| 4689 interface(MEMORY_INTER) %{ | |
| 4690 base($reg); | |
| 4691 index($ireg); | |
| 4692 scale($scale); | |
| 4693 disp(0x0); | |
| 4694 %} | |
| 4695 %} | |
| 4696 | |
| 4697 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
| 4698 operand indIndexScaleOffset(eRegP reg, immI off, eRegI ireg, immI2 scale) %{ | |
| 4699 match(AddP (AddP reg (LShiftI ireg scale)) off); | |
| 4700 | |
| 4701 op_cost(10); | |
| 4702 format %{"[$reg + $off + $ireg << $scale]" %} | |
| 4703 interface(MEMORY_INTER) %{ | |
| 4704 base($reg); | |
| 4705 index($ireg); | |
| 4706 scale($scale); | |
| 4707 disp($off); | |
| 4708 %} | |
| 4709 %} | |
| 4710 | |
| 4711 //----------Load Long Memory Operands------------------------------------------ | |
| 4712 // The load-long idiom will use it's address expression again after loading | |
| 4713 // the first word of the long. If the load-long destination overlaps with | |
| 4714 // registers used in the addressing expression, the 2nd half will be loaded | |
| 4715 // from a clobbered address. Fix this by requiring that load-long use | |
| 4716 // address registers that do not overlap with the load-long target. | |
| 4717 | |
| 4718 // load-long support | |
| 4719 operand load_long_RegP() %{ | |
| 4720 constraint(ALLOC_IN_RC(esi_reg)); | |
| 4721 match(RegP); | |
| 4722 match(eSIRegP); | |
| 4723 op_cost(100); | |
| 4724 format %{ %} | |
| 4725 interface(REG_INTER); | |
| 4726 %} | |
| 4727 | |
| 4728 // Indirect Memory Operand Long | |
| 4729 operand load_long_indirect(load_long_RegP reg) %{ | |
| 4730 constraint(ALLOC_IN_RC(esi_reg)); | |
| 4731 match(reg); | |
| 4732 | |
| 4733 format %{ "[$reg]" %} | |
| 4734 interface(MEMORY_INTER) %{ | |
| 4735 base($reg); | |
| 4736 index(0x4); | |
| 4737 scale(0x0); | |
| 4738 disp(0x0); | |
| 4739 %} | |
| 4740 %} | |
| 4741 | |
| 4742 // Indirect Memory Plus Long Offset Operand | |
| 4743 operand load_long_indOffset32(load_long_RegP reg, immI off) %{ | |
| 4744 match(AddP reg off); | |
| 4745 | |
| 4746 format %{ "[$reg + $off]" %} | |
| 4747 interface(MEMORY_INTER) %{ | |
| 4748 base($reg); | |
| 4749 index(0x4); | |
| 4750 scale(0x0); | |
| 4751 disp($off); | |
| 4752 %} | |
| 4753 %} | |
| 4754 | |
| 4755 opclass load_long_memory(load_long_indirect, load_long_indOffset32); | |
| 4756 | |
| 4757 | |
| 4758 //----------Special Memory Operands-------------------------------------------- | |
| 4759 // Stack Slot Operand - This operand is used for loading and storing temporary | |
| 4760 // values on the stack where a match requires a value to | |
| 4761 // flow through memory. | |
| 4762 operand stackSlotP(sRegP reg) %{ | |
| 4763 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4764 // No match rule because this operand is only generated in matching | |
| 4765 format %{ "[$reg]" %} | |
| 4766 interface(MEMORY_INTER) %{ | |
| 4767 base(0x4); // ESP | |
| 4768 index(0x4); // No Index | |
| 4769 scale(0x0); // No Scale | |
| 4770 disp($reg); // Stack Offset | |
| 4771 %} | |
| 4772 %} | |
| 4773 | |
| 4774 operand stackSlotI(sRegI reg) %{ | |
| 4775 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4776 // No match rule because this operand is only generated in matching | |
| 4777 format %{ "[$reg]" %} | |
| 4778 interface(MEMORY_INTER) %{ | |
| 4779 base(0x4); // ESP | |
| 4780 index(0x4); // No Index | |
| 4781 scale(0x0); // No Scale | |
| 4782 disp($reg); // Stack Offset | |
| 4783 %} | |
| 4784 %} | |
| 4785 | |
| 4786 operand stackSlotF(sRegF reg) %{ | |
| 4787 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4788 // No match rule because this operand is only generated in matching | |
| 4789 format %{ "[$reg]" %} | |
| 4790 interface(MEMORY_INTER) %{ | |
| 4791 base(0x4); // ESP | |
| 4792 index(0x4); // No Index | |
| 4793 scale(0x0); // No Scale | |
| 4794 disp($reg); // Stack Offset | |
| 4795 %} | |
| 4796 %} | |
| 4797 | |
| 4798 operand stackSlotD(sRegD reg) %{ | |
| 4799 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4800 // No match rule because this operand is only generated in matching | |
| 4801 format %{ "[$reg]" %} | |
| 4802 interface(MEMORY_INTER) %{ | |
| 4803 base(0x4); // ESP | |
| 4804 index(0x4); // No Index | |
| 4805 scale(0x0); // No Scale | |
| 4806 disp($reg); // Stack Offset | |
| 4807 %} | |
| 4808 %} | |
| 4809 | |
| 4810 operand stackSlotL(sRegL reg) %{ | |
| 4811 constraint(ALLOC_IN_RC(stack_slots)); | |
| 4812 // No match rule because this operand is only generated in matching | |
| 4813 format %{ "[$reg]" %} | |
| 4814 interface(MEMORY_INTER) %{ | |
| 4815 base(0x4); // ESP | |
| 4816 index(0x4); // No Index | |
| 4817 scale(0x0); // No Scale | |
| 4818 disp($reg); // Stack Offset | |
| 4819 %} | |
| 4820 %} | |
| 4821 | |
| 4822 //----------Memory Operands - Win95 Implicit Null Variants---------------- | |
| 4823 // Indirect Memory Operand | |
| 4824 operand indirect_win95_safe(eRegP_no_EBP reg) | |
| 4825 %{ | |
| 4826 constraint(ALLOC_IN_RC(e_reg)); | |
| 4827 match(reg); | |
| 4828 | |
| 4829 op_cost(100); | |
| 4830 format %{ "[$reg]" %} | |
| 4831 interface(MEMORY_INTER) %{ | |
| 4832 base($reg); | |
| 4833 index(0x4); | |
| 4834 scale(0x0); | |
| 4835 disp(0x0); | |
| 4836 %} | |
| 4837 %} | |
| 4838 | |
| 4839 // Indirect Memory Plus Short Offset Operand | |
| 4840 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off) | |
| 4841 %{ | |
| 4842 match(AddP reg off); | |
| 4843 | |
| 4844 op_cost(100); | |
| 4845 format %{ "[$reg + $off]" %} | |
| 4846 interface(MEMORY_INTER) %{ | |
| 4847 base($reg); | |
| 4848 index(0x4); | |
| 4849 scale(0x0); | |
| 4850 disp($off); | |
| 4851 %} | |
| 4852 %} | |
| 4853 | |
| 4854 // Indirect Memory Plus Long Offset Operand | |
| 4855 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off) | |
| 4856 %{ | |
| 4857 match(AddP reg off); | |
| 4858 | |
| 4859 op_cost(100); | |
| 4860 format %{ "[$reg + $off]" %} | |
| 4861 interface(MEMORY_INTER) %{ | |
| 4862 base($reg); | |
| 4863 index(0x4); | |
| 4864 scale(0x0); | |
| 4865 disp($off); | |
| 4866 %} | |
| 4867 %} | |
| 4868 | |
| 4869 // Indirect Memory Plus Index Register Plus Offset Operand | |
| 4870 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI off) | |
| 4871 %{ | |
| 4872 match(AddP (AddP reg ireg) off); | |
| 4873 | |
| 4874 op_cost(100); | |
| 4875 format %{"[$reg + $off + $ireg]" %} | |
| 4876 interface(MEMORY_INTER) %{ | |
| 4877 base($reg); | |
| 4878 index($ireg); | |
| 4879 scale(0x0); | |
| 4880 disp($off); | |
| 4881 %} | |
| 4882 %} | |
| 4883 | |
| 4884 // Indirect Memory Times Scale Plus Index Register | |
| 4885 operand indIndexScale_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI2 scale) | |
| 4886 %{ | |
| 4887 match(AddP reg (LShiftI ireg scale)); | |
| 4888 | |
| 4889 op_cost(100); | |
| 4890 format %{"[$reg + $ireg << $scale]" %} | |
| 4891 interface(MEMORY_INTER) %{ | |
| 4892 base($reg); | |
| 4893 index($ireg); | |
| 4894 scale($scale); | |
| 4895 disp(0x0); | |
| 4896 %} | |
| 4897 %} | |
| 4898 | |
| 4899 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
| 4900 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, eRegI ireg, immI2 scale) | |
| 4901 %{ | |
| 4902 match(AddP (AddP reg (LShiftI ireg scale)) off); | |
| 4903 | |
| 4904 op_cost(100); | |
| 4905 format %{"[$reg + $off + $ireg << $scale]" %} | |
| 4906 interface(MEMORY_INTER) %{ | |
| 4907 base($reg); | |
| 4908 index($ireg); | |
| 4909 scale($scale); | |
| 4910 disp($off); | |
| 4911 %} | |
| 4912 %} | |
| 4913 | |
| 4914 //----------Conditional Branch Operands---------------------------------------- | |
| 4915 // Comparison Op - This is the operation of the comparison, and is limited to | |
| 4916 // the following set of codes: | |
| 4917 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
| 4918 // | |
| 4919 // Other attributes of the comparison, such as unsignedness, are specified | |
| 4920 // by the comparison instruction that sets a condition code flags register. | |
| 4921 // That result is represented by a flags operand whose subtype is appropriate | |
| 4922 // to the unsignedness (etc.) of the comparison. | |
| 4923 // | |
| 4924 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
| 4925 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
| 4926 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
| 4927 | |
| 4928 // Comparision Code | |
| 4929 operand cmpOp() %{ | |
| 4930 match(Bool); | |
| 4931 | |
| 4932 format %{ "" %} | |
| 4933 interface(COND_INTER) %{ | |
|
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|
4934 equal(0x4, "e"); |
|
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|
4935 not_equal(0x5, "ne"); |
|
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diff
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|
4936 less(0xC, "l"); |
|
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diff
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|
4937 greater_equal(0xD, "ge"); |
|
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|
4938 less_equal(0xE, "le"); |
|
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|
4939 greater(0xF, "g"); |
| 0 | 4940 %} |
| 4941 %} | |
| 4942 | |
| 4943 // Comparison Code, unsigned compare. Used by FP also, with | |
| 4944 // C2 (unordered) turned into GT or LT already. The other bits | |
| 4945 // C0 and C3 are turned into Carry & Zero flags. | |
| 4946 operand cmpOpU() %{ | |
| 4947 match(Bool); | |
| 4948 | |
| 4949 format %{ "" %} | |
| 4950 interface(COND_INTER) %{ | |
|
415
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|
4951 equal(0x4, "e"); |
|
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|
4952 not_equal(0x5, "ne"); |
|
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|
4953 less(0x2, "b"); |
|
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|
4954 greater_equal(0x3, "nb"); |
|
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|
4955 less_equal(0x6, "be"); |
|
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diff
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|
4956 greater(0x7, "nbe"); |
|
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diff
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|
4957 %} |
|
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|
4958 %} |
|
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|
4959 |
|
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|
4960 // Floating comparisons that don't require any fixup for the unordered case |
|
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|
4961 operand cmpOpUCF() %{ |
|
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diff
changeset
|
4962 match(Bool); |
|
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changeset
|
4963 predicate(n->as_Bool()->_test._test == BoolTest::lt || |
|
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|
4964 n->as_Bool()->_test._test == BoolTest::ge || |
|
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|
4965 n->as_Bool()->_test._test == BoolTest::le || |
|
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|
4966 n->as_Bool()->_test._test == BoolTest::gt); |
|
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diff
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|
4967 format %{ "" %} |
|
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diff
changeset
|
4968 interface(COND_INTER) %{ |
|
4d9884b01ba6
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diff
changeset
|
4969 equal(0x4, "e"); |
|
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diff
changeset
|
4970 not_equal(0x5, "ne"); |
|
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diff
changeset
|
4971 less(0x2, "b"); |
|
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|
4972 greater_equal(0x3, "nb"); |
|
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4973 less_equal(0x6, "be"); |
|
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|
4974 greater(0x7, "nbe"); |
|
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|
4975 %} |
|
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|
4976 %} |
|
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|
4977 |
|
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|
4978 |
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|
4979 // Floating comparisons that can be fixed up with extra conditional jumps |
|
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|
4980 operand cmpOpUCF2() %{ |
|
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|
4981 match(Bool); |
|
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|
4982 predicate(n->as_Bool()->_test._test == BoolTest::ne || |
|
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|
4983 n->as_Bool()->_test._test == BoolTest::eq); |
|
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|
4984 format %{ "" %} |
|
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|
4985 interface(COND_INTER) %{ |
|
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|
4986 equal(0x4, "e"); |
|
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|
4987 not_equal(0x5, "ne"); |
|
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|
4988 less(0x2, "b"); |
|
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|
4989 greater_equal(0x3, "nb"); |
|
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|
4990 less_equal(0x6, "be"); |
|
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|
4991 greater(0x7, "nbe"); |
| 0 | 4992 %} |
| 4993 %} | |
| 4994 | |
| 4995 // Comparison Code for FP conditional move | |
| 4996 operand cmpOp_fcmov() %{ | |
| 4997 match(Bool); | |
| 4998 | |
| 4999 format %{ "" %} | |
| 5000 interface(COND_INTER) %{ | |
| 5001 equal (0x0C8); | |
| 5002 not_equal (0x1C8); | |
| 5003 less (0x0C0); | |
| 5004 greater_equal(0x1C0); | |
| 5005 less_equal (0x0D0); | |
| 5006 greater (0x1D0); | |
| 5007 %} | |
| 5008 %} | |
| 5009 | |
| 5010 // Comparision Code used in long compares | |
| 5011 operand cmpOp_commute() %{ | |
| 5012 match(Bool); | |
| 5013 | |
| 5014 format %{ "" %} | |
| 5015 interface(COND_INTER) %{ | |
|
415
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|
5016 equal(0x4, "e"); |
|
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|
5017 not_equal(0x5, "ne"); |
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|
5018 less(0xF, "g"); |
|
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|
5019 greater_equal(0xE, "le"); |
|
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|
5020 less_equal(0xD, "ge"); |
|
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|
5021 greater(0xC, "l"); |
| 0 | 5022 %} |
| 5023 %} | |
| 5024 | |
| 5025 //----------OPERAND CLASSES---------------------------------------------------- | |
| 5026 // Operand Classes are groups of operands that are used as to simplify | |
| 605 | 5027 // instruction definitions by not requiring the AD writer to specify separate |
| 0 | 5028 // instructions for every form of operand when the instruction accepts |
| 5029 // multiple operand types with the same basic encoding and format. The classic | |
| 5030 // case of this is memory operands. | |
| 5031 | |
| 5032 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset, | |
| 5033 indIndex, indIndexScale, indIndexScaleOffset); | |
| 5034 | |
| 5035 // Long memory operations are encoded in 2 instructions and a +4 offset. | |
| 5036 // This means some kind of offset is always required and you cannot use | |
| 5037 // an oop as the offset (done when working on static globals). | |
| 5038 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset, | |
| 5039 indIndex, indIndexScale, indIndexScaleOffset); | |
| 5040 | |
| 5041 | |
| 5042 //----------PIPELINE----------------------------------------------------------- | |
| 5043 // Rules which define the behavior of the target architectures pipeline. | |
| 5044 pipeline %{ | |
| 5045 | |
| 5046 //----------ATTRIBUTES--------------------------------------------------------- | |
| 5047 attributes %{ | |
| 5048 variable_size_instructions; // Fixed size instructions | |
| 5049 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle | |
| 5050 instruction_unit_size = 1; // An instruction is 1 bytes long | |
| 5051 instruction_fetch_unit_size = 16; // The processor fetches one line | |
| 5052 instruction_fetch_units = 1; // of 16 bytes | |
| 5053 | |
| 5054 // List of nop instructions | |
| 5055 nops( MachNop ); | |
| 5056 %} | |
| 5057 | |
| 5058 //----------RESOURCES---------------------------------------------------------- | |
| 5059 // Resources are the functional units available to the machine | |
| 5060 | |
| 5061 // Generic P2/P3 pipeline | |
| 5062 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of | |
| 5063 // 3 instructions decoded per cycle. | |
| 5064 // 2 load/store ops per cycle, 1 branch, 1 FPU, | |
| 5065 // 2 ALU op, only ALU0 handles mul/div instructions. | |
| 5066 resources( D0, D1, D2, DECODE = D0 | D1 | D2, | |
| 5067 MS0, MS1, MEM = MS0 | MS1, | |
| 5068 BR, FPU, | |
| 5069 ALU0, ALU1, ALU = ALU0 | ALU1 ); | |
| 5070 | |
| 5071 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
| 5072 // Pipeline Description specifies the stages in the machine's pipeline | |
| 5073 | |
| 5074 // Generic P2/P3 pipeline | |
| 5075 pipe_desc(S0, S1, S2, S3, S4, S5); | |
| 5076 | |
| 5077 //----------PIPELINE CLASSES--------------------------------------------------- | |
| 5078 // Pipeline Classes describe the stages in which input and output are | |
| 5079 // referenced by the hardware pipeline. | |
| 5080 | |
| 5081 // Naming convention: ialu or fpu | |
| 5082 // Then: _reg | |
| 5083 // Then: _reg if there is a 2nd register | |
| 5084 // Then: _long if it's a pair of instructions implementing a long | |
| 5085 // Then: _fat if it requires the big decoder | |
| 5086 // Or: _mem if it requires the big decoder and a memory unit. | |
| 5087 | |
| 5088 // Integer ALU reg operation | |
| 5089 pipe_class ialu_reg(eRegI dst) %{ | |
| 5090 single_instruction; | |
| 5091 dst : S4(write); | |
| 5092 dst : S3(read); | |
| 5093 DECODE : S0; // any decoder | |
| 5094 ALU : S3; // any alu | |
| 5095 %} | |
| 5096 | |
| 5097 // Long ALU reg operation | |
| 5098 pipe_class ialu_reg_long(eRegL dst) %{ | |
| 5099 instruction_count(2); | |
| 5100 dst : S4(write); | |
| 5101 dst : S3(read); | |
| 5102 DECODE : S0(2); // any 2 decoders | |
| 5103 ALU : S3(2); // both alus | |
| 5104 %} | |
| 5105 | |
| 5106 // Integer ALU reg operation using big decoder | |
| 5107 pipe_class ialu_reg_fat(eRegI dst) %{ | |
| 5108 single_instruction; | |
| 5109 dst : S4(write); | |
| 5110 dst : S3(read); | |
| 5111 D0 : S0; // big decoder only | |
| 5112 ALU : S3; // any alu | |
| 5113 %} | |
| 5114 | |
| 5115 // Long ALU reg operation using big decoder | |
| 5116 pipe_class ialu_reg_long_fat(eRegL dst) %{ | |
| 5117 instruction_count(2); | |
| 5118 dst : S4(write); | |
| 5119 dst : S3(read); | |
| 5120 D0 : S0(2); // big decoder only; twice | |
| 5121 ALU : S3(2); // any 2 alus | |
| 5122 %} | |
| 5123 | |
| 5124 // Integer ALU reg-reg operation | |
| 5125 pipe_class ialu_reg_reg(eRegI dst, eRegI src) %{ | |
| 5126 single_instruction; | |
| 5127 dst : S4(write); | |
| 5128 src : S3(read); | |
| 5129 DECODE : S0; // any decoder | |
| 5130 ALU : S3; // any alu | |
| 5131 %} | |
| 5132 | |
| 5133 // Long ALU reg-reg operation | |
| 5134 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{ | |
| 5135 instruction_count(2); | |
| 5136 dst : S4(write); | |
| 5137 src : S3(read); | |
| 5138 DECODE : S0(2); // any 2 decoders | |
| 5139 ALU : S3(2); // both alus | |
| 5140 %} | |
| 5141 | |
| 5142 // Integer ALU reg-reg operation | |
| 5143 pipe_class ialu_reg_reg_fat(eRegI dst, memory src) %{ | |
| 5144 single_instruction; | |
| 5145 dst : S4(write); | |
| 5146 src : S3(read); | |
| 5147 D0 : S0; // big decoder only | |
| 5148 ALU : S3; // any alu | |
| 5149 %} | |
| 5150 | |
| 5151 // Long ALU reg-reg operation | |
| 5152 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{ | |
| 5153 instruction_count(2); | |
| 5154 dst : S4(write); | |
| 5155 src : S3(read); | |
| 5156 D0 : S0(2); // big decoder only; twice | |
| 5157 ALU : S3(2); // both alus | |
| 5158 %} | |
| 5159 | |
| 5160 // Integer ALU reg-mem operation | |
| 5161 pipe_class ialu_reg_mem(eRegI dst, memory mem) %{ | |
| 5162 single_instruction; | |
| 5163 dst : S5(write); | |
| 5164 mem : S3(read); | |
| 5165 D0 : S0; // big decoder only | |
| 5166 ALU : S4; // any alu | |
| 5167 MEM : S3; // any mem | |
| 5168 %} | |
| 5169 | |
| 5170 // Long ALU reg-mem operation | |
| 5171 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{ | |
| 5172 instruction_count(2); | |
| 5173 dst : S5(write); | |
| 5174 mem : S3(read); | |
| 5175 D0 : S0(2); // big decoder only; twice | |
| 5176 ALU : S4(2); // any 2 alus | |
| 5177 MEM : S3(2); // both mems | |
| 5178 %} | |
| 5179 | |
| 5180 // Integer mem operation (prefetch) | |
| 5181 pipe_class ialu_mem(memory mem) | |
| 5182 %{ | |
| 5183 single_instruction; | |
| 5184 mem : S3(read); | |
| 5185 D0 : S0; // big decoder only | |
| 5186 MEM : S3; // any mem | |
| 5187 %} | |
| 5188 | |
| 5189 // Integer Store to Memory | |
| 5190 pipe_class ialu_mem_reg(memory mem, eRegI src) %{ | |
| 5191 single_instruction; | |
| 5192 mem : S3(read); | |
| 5193 src : S5(read); | |
| 5194 D0 : S0; // big decoder only | |
| 5195 ALU : S4; // any alu | |
| 5196 MEM : S3; | |
| 5197 %} | |
| 5198 | |
| 5199 // Long Store to Memory | |
| 5200 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{ | |
| 5201 instruction_count(2); | |
| 5202 mem : S3(read); | |
| 5203 src : S5(read); | |
| 5204 D0 : S0(2); // big decoder only; twice | |
| 5205 ALU : S4(2); // any 2 alus | |
| 5206 MEM : S3(2); // Both mems | |
| 5207 %} | |
| 5208 | |
| 5209 // Integer Store to Memory | |
| 5210 pipe_class ialu_mem_imm(memory mem) %{ | |
| 5211 single_instruction; | |
| 5212 mem : S3(read); | |
| 5213 D0 : S0; // big decoder only | |
| 5214 ALU : S4; // any alu | |
| 5215 MEM : S3; | |
| 5216 %} | |
| 5217 | |
| 5218 // Integer ALU0 reg-reg operation | |
| 5219 pipe_class ialu_reg_reg_alu0(eRegI dst, eRegI src) %{ | |
| 5220 single_instruction; | |
| 5221 dst : S4(write); | |
| 5222 src : S3(read); | |
| 5223 D0 : S0; // Big decoder only | |
| 5224 ALU0 : S3; // only alu0 | |
| 5225 %} | |
| 5226 | |
| 5227 // Integer ALU0 reg-mem operation | |
| 5228 pipe_class ialu_reg_mem_alu0(eRegI dst, memory mem) %{ | |
| 5229 single_instruction; | |
| 5230 dst : S5(write); | |
| 5231 mem : S3(read); | |
| 5232 D0 : S0; // big decoder only | |
| 5233 ALU0 : S4; // ALU0 only | |
| 5234 MEM : S3; // any mem | |
| 5235 %} | |
| 5236 | |
| 5237 // Integer ALU reg-reg operation | |
| 5238 pipe_class ialu_cr_reg_reg(eFlagsReg cr, eRegI src1, eRegI src2) %{ | |
| 5239 single_instruction; | |
| 5240 cr : S4(write); | |
| 5241 src1 : S3(read); | |
| 5242 src2 : S3(read); | |
| 5243 DECODE : S0; // any decoder | |
| 5244 ALU : S3; // any alu | |
| 5245 %} | |
| 5246 | |
| 5247 // Integer ALU reg-imm operation | |
| 5248 pipe_class ialu_cr_reg_imm(eFlagsReg cr, eRegI src1) %{ | |
| 5249 single_instruction; | |
| 5250 cr : S4(write); | |
| 5251 src1 : S3(read); | |
| 5252 DECODE : S0; // any decoder | |
| 5253 ALU : S3; // any alu | |
| 5254 %} | |
| 5255 | |
| 5256 // Integer ALU reg-mem operation | |
| 5257 pipe_class ialu_cr_reg_mem(eFlagsReg cr, eRegI src1, memory src2) %{ | |
| 5258 single_instruction; | |
| 5259 cr : S4(write); | |
| 5260 src1 : S3(read); | |
| 5261 src2 : S3(read); | |
| 5262 D0 : S0; // big decoder only | |
| 5263 ALU : S4; // any alu | |
| 5264 MEM : S3; | |
| 5265 %} | |
| 5266 | |
| 5267 // Conditional move reg-reg | |
| 5268 pipe_class pipe_cmplt( eRegI p, eRegI q, eRegI y ) %{ | |
| 5269 instruction_count(4); | |
| 5270 y : S4(read); | |
| 5271 q : S3(read); | |
| 5272 p : S3(read); | |
| 5273 DECODE : S0(4); // any decoder | |
| 5274 %} | |
| 5275 | |
| 5276 // Conditional move reg-reg | |
| 5277 pipe_class pipe_cmov_reg( eRegI dst, eRegI src, eFlagsReg cr ) %{ | |
| 5278 single_instruction; | |
| 5279 dst : S4(write); | |
| 5280 src : S3(read); | |
| 5281 cr : S3(read); | |
| 5282 DECODE : S0; // any decoder | |
| 5283 %} | |
| 5284 | |
| 5285 // Conditional move reg-mem | |
| 5286 pipe_class pipe_cmov_mem( eFlagsReg cr, eRegI dst, memory src) %{ | |
| 5287 single_instruction; | |
| 5288 dst : S4(write); | |
| 5289 src : S3(read); | |
| 5290 cr : S3(read); | |
| 5291 DECODE : S0; // any decoder | |
| 5292 MEM : S3; | |
| 5293 %} | |
| 5294 | |
| 5295 // Conditional move reg-reg long | |
| 5296 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{ | |
| 5297 single_instruction; | |
| 5298 dst : S4(write); | |
| 5299 src : S3(read); | |
| 5300 cr : S3(read); | |
| 5301 DECODE : S0(2); // any 2 decoders | |
| 5302 %} | |
| 5303 | |
| 5304 // Conditional move double reg-reg | |
|
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5305 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{ |
| 0 | 5306 single_instruction; |
| 5307 dst : S4(write); | |
| 5308 src : S3(read); | |
| 5309 cr : S3(read); | |
| 5310 DECODE : S0; // any decoder | |
| 5311 %} | |
| 5312 | |
| 5313 // Float reg-reg operation | |
|
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5314 pipe_class fpu_reg(regDPR dst) %{ |
| 0 | 5315 instruction_count(2); |
| 5316 dst : S3(read); | |
| 5317 DECODE : S0(2); // any 2 decoders | |
| 5318 FPU : S3; | |
| 5319 %} | |
| 5320 | |
| 5321 // Float reg-reg operation | |
|
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5322 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{ |
| 0 | 5323 instruction_count(2); |
| 5324 dst : S4(write); | |
| 5325 src : S3(read); | |
| 5326 DECODE : S0(2); // any 2 decoders | |
| 5327 FPU : S3; | |
| 5328 %} | |
| 5329 | |
| 5330 // Float reg-reg operation | |
|
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5331 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{ |
| 0 | 5332 instruction_count(3); |
| 5333 dst : S4(write); | |
| 5334 src1 : S3(read); | |
| 5335 src2 : S3(read); | |
| 5336 DECODE : S0(3); // any 3 decoders | |
| 5337 FPU : S3(2); | |
| 5338 %} | |
| 5339 | |
| 5340 // Float reg-reg operation | |
|
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5341 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{ |
| 0 | 5342 instruction_count(4); |
| 5343 dst : S4(write); | |
| 5344 src1 : S3(read); | |
| 5345 src2 : S3(read); | |
| 5346 src3 : S3(read); | |
| 5347 DECODE : S0(4); // any 3 decoders | |
| 5348 FPU : S3(2); | |
| 5349 %} | |
| 5350 | |
| 5351 // Float reg-reg operation | |
|
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5352 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{ |
| 0 | 5353 instruction_count(4); |
| 5354 dst : S4(write); | |
| 5355 src1 : S3(read); | |
| 5356 src2 : S3(read); | |
| 5357 src3 : S3(read); | |
| 5358 DECODE : S1(3); // any 3 decoders | |
| 5359 D0 : S0; // Big decoder only | |
| 5360 FPU : S3(2); | |
| 5361 MEM : S3; | |
| 5362 %} | |
| 5363 | |
| 5364 // Float reg-mem operation | |
|
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5365 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{ |
| 0 | 5366 instruction_count(2); |
| 5367 dst : S5(write); | |
| 5368 mem : S3(read); | |
| 5369 D0 : S0; // big decoder only | |
| 5370 DECODE : S1; // any decoder for FPU POP | |
| 5371 FPU : S4; | |
| 5372 MEM : S3; // any mem | |
| 5373 %} | |
| 5374 | |
| 5375 // Float reg-mem operation | |
|
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5376 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{ |
| 0 | 5377 instruction_count(3); |
| 5378 dst : S5(write); | |
| 5379 src1 : S3(read); | |
| 5380 mem : S3(read); | |
| 5381 D0 : S0; // big decoder only | |
| 5382 DECODE : S1(2); // any decoder for FPU POP | |
| 5383 FPU : S4; | |
| 5384 MEM : S3; // any mem | |
| 5385 %} | |
| 5386 | |
| 5387 // Float mem-reg operation | |
|
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|
5388 pipe_class fpu_mem_reg(memory mem, regDPR src) %{ |
| 0 | 5389 instruction_count(2); |
| 5390 src : S5(read); | |
| 5391 mem : S3(read); | |
| 5392 DECODE : S0; // any decoder for FPU PUSH | |
| 5393 D0 : S1; // big decoder only | |
| 5394 FPU : S4; | |
| 5395 MEM : S3; // any mem | |
| 5396 %} | |
| 5397 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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4759
diff
changeset
|
5398 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{ |
| 0 | 5399 instruction_count(3); |
| 5400 src1 : S3(read); | |
| 5401 src2 : S3(read); | |
| 5402 mem : S3(read); | |
| 5403 DECODE : S0(2); // any decoder for FPU PUSH | |
| 5404 D0 : S1; // big decoder only | |
| 5405 FPU : S4; | |
| 5406 MEM : S3; // any mem | |
| 5407 %} | |
| 5408 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
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4759
diff
changeset
|
5409 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{ |
| 0 | 5410 instruction_count(3); |
| 5411 src1 : S3(read); | |
| 5412 src2 : S3(read); | |
| 5413 mem : S4(read); | |
| 5414 DECODE : S0; // any decoder for FPU PUSH | |
| 5415 D0 : S0(2); // big decoder only | |
| 5416 FPU : S4; | |
| 5417 MEM : S3(2); // any mem | |
| 5418 %} | |
| 5419 | |
| 5420 pipe_class fpu_mem_mem(memory dst, memory src1) %{ | |
| 5421 instruction_count(2); | |
| 5422 src1 : S3(read); | |
| 5423 dst : S4(read); | |
| 5424 D0 : S0(2); // big decoder only | |
| 5425 MEM : S3(2); // any mem | |
| 5426 %} | |
| 5427 | |
| 5428 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{ | |
| 5429 instruction_count(3); | |
| 5430 src1 : S3(read); | |
| 5431 src2 : S3(read); | |
| 5432 dst : S4(read); | |
| 5433 D0 : S0(3); // big decoder only | |
| 5434 FPU : S4; | |
| 5435 MEM : S3(3); // any mem | |
| 5436 %} | |
| 5437 | |
|
4761
65149e74c706
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4759
diff
changeset
|
5438 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{ |
| 0 | 5439 instruction_count(3); |
| 5440 src1 : S4(read); | |
| 5441 mem : S4(read); | |
| 5442 DECODE : S0; // any decoder for FPU PUSH | |
| 5443 D0 : S0(2); // big decoder only | |
| 5444 FPU : S4; | |
| 5445 MEM : S3(2); // any mem | |
| 5446 %} | |
| 5447 | |
| 5448 // Float load constant | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
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4759
diff
changeset
|
5449 pipe_class fpu_reg_con(regDPR dst) %{ |
| 0 | 5450 instruction_count(2); |
| 5451 dst : S5(write); | |
| 5452 D0 : S0; // big decoder only for the load | |
| 5453 DECODE : S1; // any decoder for FPU POP | |
| 5454 FPU : S4; | |
| 5455 MEM : S3; // any mem | |
| 5456 %} | |
| 5457 | |
| 5458 // Float load constant | |
|
4761
65149e74c706
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4759
diff
changeset
|
5459 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{ |
| 0 | 5460 instruction_count(3); |
| 5461 dst : S5(write); | |
| 5462 src : S3(read); | |
| 5463 D0 : S0; // big decoder only for the load | |
| 5464 DECODE : S1(2); // any decoder for FPU POP | |
| 5465 FPU : S4; | |
| 5466 MEM : S3; // any mem | |
| 5467 %} | |
| 5468 | |
| 5469 // UnConditional branch | |
| 5470 pipe_class pipe_jmp( label labl ) %{ | |
| 5471 single_instruction; | |
| 5472 BR : S3; | |
| 5473 %} | |
| 5474 | |
| 5475 // Conditional branch | |
| 5476 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{ | |
| 5477 single_instruction; | |
| 5478 cr : S1(read); | |
| 5479 BR : S3; | |
| 5480 %} | |
| 5481 | |
| 5482 // Allocation idiom | |
| 5483 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{ | |
| 5484 instruction_count(1); force_serialization; | |
| 5485 fixed_latency(6); | |
| 5486 heap_ptr : S3(read); | |
| 5487 DECODE : S0(3); | |
| 5488 D0 : S2; | |
| 5489 MEM : S3; | |
| 5490 ALU : S3(2); | |
| 5491 dst : S5(write); | |
| 5492 BR : S5; | |
| 5493 %} | |
| 5494 | |
| 5495 // Generic big/slow expanded idiom | |
| 5496 pipe_class pipe_slow( ) %{ | |
| 5497 instruction_count(10); multiple_bundles; force_serialization; | |
| 5498 fixed_latency(100); | |
| 5499 D0 : S0(2); | |
| 5500 MEM : S3(2); | |
| 5501 %} | |
| 5502 | |
| 5503 // The real do-nothing guy | |
| 5504 pipe_class empty( ) %{ | |
| 5505 instruction_count(0); | |
| 5506 %} | |
| 5507 | |
| 5508 // Define the class for the Nop node | |
| 5509 define %{ | |
| 5510 MachNop = empty; | |
| 5511 %} | |
| 5512 | |
| 5513 %} | |
| 5514 | |
| 5515 //----------INSTRUCTIONS------------------------------------------------------- | |
| 5516 // | |
| 5517 // match -- States which machine-independent subtree may be replaced | |
| 5518 // by this instruction. | |
| 5519 // ins_cost -- The estimated cost of this instruction is used by instruction | |
| 5520 // selection to identify a minimum cost tree of machine | |
| 5521 // instructions that matches a tree of machine-independent | |
| 5522 // instructions. | |
| 5523 // format -- A string providing the disassembly for this instruction. | |
| 5524 // The value of an instruction's operand may be inserted | |
| 5525 // by referring to it with a '$' prefix. | |
| 5526 // opcode -- Three instruction opcodes may be provided. These are referred | |
| 5527 // to within an encode class as $primary, $secondary, and $tertiary | |
| 5528 // respectively. The primary opcode is commonly used to | |
| 5529 // indicate the type of machine instruction, while secondary | |
| 5530 // and tertiary are often used for prefix options or addressing | |
| 5531 // modes. | |
| 5532 // ins_encode -- A list of encode classes with parameters. The encode class | |
| 5533 // name must have been defined in an 'enc_class' specification | |
| 5534 // in the encode section of the architecture description. | |
| 5535 | |
| 5536 //----------BSWAP-Instruction-------------------------------------------------- | |
| 5537 instruct bytes_reverse_int(eRegI dst) %{ | |
| 5538 match(Set dst (ReverseBytesI dst)); | |
| 5539 | |
| 5540 format %{ "BSWAP $dst" %} | |
| 5541 opcode(0x0F, 0xC8); | |
| 5542 ins_encode( OpcP, OpcSReg(dst) ); | |
| 5543 ins_pipe( ialu_reg ); | |
| 5544 %} | |
| 5545 | |
| 5546 instruct bytes_reverse_long(eRegL dst) %{ | |
| 5547 match(Set dst (ReverseBytesL dst)); | |
| 5548 | |
| 5549 format %{ "BSWAP $dst.lo\n\t" | |
| 5550 "BSWAP $dst.hi\n\t" | |
| 5551 "XCHG $dst.lo $dst.hi" %} | |
| 5552 | |
| 5553 ins_cost(125); | |
| 5554 ins_encode( bswap_long_bytes(dst) ); | |
| 5555 ins_pipe( ialu_reg_reg); | |
| 5556 %} | |
| 5557 | |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
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6084
diff
changeset
|
5558 instruct bytes_reverse_unsigned_short(eRegI dst, eFlagsReg cr) %{ |
|
1396
d7f654633cfe
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1274
diff
changeset
|
5559 match(Set dst (ReverseBytesUS dst)); |
|
6138
ccaa67adfe5b
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parents:
6084
diff
changeset
|
5560 effect(KILL cr); |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5561 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5562 format %{ "BSWAP $dst\n\t" |
|
d7f654633cfe
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parents:
1274
diff
changeset
|
5563 "SHR $dst,16\n\t" %} |
|
d7f654633cfe
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never
parents:
1274
diff
changeset
|
5564 ins_encode %{ |
|
d7f654633cfe
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never
parents:
1274
diff
changeset
|
5565 __ bswapl($dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5566 __ shrl($dst$$Register, 16); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5567 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5568 ins_pipe( ialu_reg ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5569 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5570 |
|
6138
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parents:
6084
diff
changeset
|
5571 instruct bytes_reverse_short(eRegI dst, eFlagsReg cr) %{ |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5572 match(Set dst (ReverseBytesS dst)); |
|
6138
ccaa67adfe5b
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parents:
6084
diff
changeset
|
5573 effect(KILL cr); |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5574 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5575 format %{ "BSWAP $dst\n\t" |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5576 "SAR $dst,16\n\t" %} |
|
d7f654633cfe
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never
parents:
1274
diff
changeset
|
5577 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5578 __ bswapl($dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5579 __ sarl($dst$$Register, 16); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5580 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5581 ins_pipe( ialu_reg ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5582 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
5583 |
| 0 | 5584 |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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parents:
681
diff
changeset
|
5585 //---------- Zeros Count Instructions ------------------------------------------ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5586 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5587 instruct countLeadingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5588 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5589 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5590 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5591 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5592 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5593 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5594 __ lzcntl($dst$$Register, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5595 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5596 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5597 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5598 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5599 instruct countLeadingZerosI_bsr(eRegI dst, eRegI src, eFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5600 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5601 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5602 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5603 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5604 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5605 "JNZ skip\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5606 "MOV $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5607 "skip:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5608 "NEG $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5609 "ADD $dst, 31" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5610 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5611 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5612 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5613 Label skip; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5614 __ bsrl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5615 __ jccb(Assembler::notZero, skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5616 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5617 __ bind(skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5618 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5619 __ addl(Rdst, BitsPerInt - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5620 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5621 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5622 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5623 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5624 instruct countLeadingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5625 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5626 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5627 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5628 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5629 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5630 "JNC done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5631 "LZCNT $dst, $src.lo\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5632 "ADD $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5633 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5634 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5635 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5636 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5637 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5638 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5639 __ jccb(Assembler::carryClear, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5640 __ lzcntl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5641 __ addl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5642 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5643 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5644 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5645 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5646 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5647 instruct countLeadingZerosL_bsr(eRegI dst, eRegL src, eFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5648 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5649 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5650 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5651 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5652 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5653 "JZ msw_is_zero\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5654 "ADD $dst, 32\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5655 "JMP not_zero\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5656 "msw_is_zero:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5657 "BSR $dst, $src.lo\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5658 "JNZ not_zero\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5659 "MOV $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5660 "not_zero:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5661 "NEG $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5662 "ADD $dst, 63\n" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5663 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5664 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5665 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5666 Label msw_is_zero; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5667 Label not_zero; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5668 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5669 __ jccb(Assembler::zero, msw_is_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5670 __ addl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5671 __ jmpb(not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5672 __ bind(msw_is_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5673 __ bsrl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5674 __ jccb(Assembler::notZero, not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5675 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5676 __ bind(not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5677 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5678 __ addl(Rdst, BitsPerLong - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5679 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5680 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5681 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5682 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5683 instruct countTrailingZerosI(eRegI dst, eRegI src, eFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5684 match(Set dst (CountTrailingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5685 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5686 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5687 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5688 "JNZ done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5689 "MOV $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5690 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5691 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5692 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5693 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5694 __ bsfl(Rdst, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5695 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5696 __ movl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5697 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5698 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5699 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5700 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5701 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5702 instruct countTrailingZerosL(eRegI dst, eRegL src, eFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5703 match(Set dst (CountTrailingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5704 effect(TEMP dst, KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5705 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5706 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5707 "JNZ done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5708 "BSF $dst, $src.hi\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5709 "JNZ msw_not_zero\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5710 "MOV $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5711 "msw_not_zero:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5712 "ADD $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5713 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5714 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5715 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5716 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5717 Label msw_not_zero; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5718 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5719 __ bsfl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5720 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5721 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5722 __ jccb(Assembler::notZero, msw_not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5723 __ movl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5724 __ bind(msw_not_zero); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5725 __ addl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5726 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5727 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5728 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5729 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5730 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
5731 |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5732 //---------- Population Count Instructions ------------------------------------- |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5733 |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents:
6084
diff
changeset
|
5734 instruct popCountI(eRegI dst, eRegI src, eFlagsReg cr) %{ |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5735 predicate(UsePopCountInstruction); |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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624
diff
changeset
|
5736 match(Set dst (PopCountI src)); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
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parents:
6084
diff
changeset
|
5737 effect(KILL cr); |
|
643
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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624
diff
changeset
|
5738 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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parents:
624
diff
changeset
|
5739 format %{ "POPCNT $dst, $src" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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parents:
624
diff
changeset
|
5740 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5741 __ popcntl($dst$$Register, $src$$Register); |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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parents:
624
diff
changeset
|
5742 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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parents:
624
diff
changeset
|
5743 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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624
diff
changeset
|
5744 %} |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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parents:
624
diff
changeset
|
5745 |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
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parents:
6084
diff
changeset
|
5746 instruct popCountI_mem(eRegI dst, memory mem, eFlagsReg cr) %{ |
|
643
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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624
diff
changeset
|
5747 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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624
diff
changeset
|
5748 match(Set dst (PopCountI (LoadI mem))); |
|
6138
ccaa67adfe5b
7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
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parents:
6084
diff
changeset
|
5749 effect(KILL cr); |
|
643
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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parents:
624
diff
changeset
|
5750 |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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parents:
624
diff
changeset
|
5751 format %{ "POPCNT $dst, $mem" %} |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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parents:
624
diff
changeset
|
5752 ins_encode %{ |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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parents:
624
diff
changeset
|
5753 __ popcntl($dst$$Register, $mem$$Address); |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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parents:
624
diff
changeset
|
5754 %} |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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parents:
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diff
changeset
|
5755 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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parents:
624
diff
changeset
|
5756 %} |
|
c771b7f43bbf
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parents:
624
diff
changeset
|
5757 |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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parents:
624
diff
changeset
|
5758 // Note: Long.bitCount(long) returns an int. |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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diff
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|
5759 instruct popCountL(eRegI dst, eRegL src, eRegI tmp, eFlagsReg cr) %{ |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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624
diff
changeset
|
5760 predicate(UsePopCountInstruction); |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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parents:
624
diff
changeset
|
5761 match(Set dst (PopCountL src)); |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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parents:
624
diff
changeset
|
5762 effect(KILL cr, TEMP tmp, TEMP dst); |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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624
diff
changeset
|
5763 |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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parents:
624
diff
changeset
|
5764 format %{ "POPCNT $dst, $src.lo\n\t" |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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parents:
624
diff
changeset
|
5765 "POPCNT $tmp, $src.hi\n\t" |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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parents:
624
diff
changeset
|
5766 "ADD $dst, $tmp" %} |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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parents:
624
diff
changeset
|
5767 ins_encode %{ |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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624
diff
changeset
|
5768 __ popcntl($dst$$Register, $src$$Register); |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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parents:
624
diff
changeset
|
5769 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register)); |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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diff
changeset
|
5770 __ addl($dst$$Register, $tmp$$Register); |
|
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parents:
624
diff
changeset
|
5771 %} |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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parents:
624
diff
changeset
|
5772 ins_pipe(ialu_reg); |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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624
diff
changeset
|
5773 %} |
|
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parents:
624
diff
changeset
|
5774 |
|
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parents:
624
diff
changeset
|
5775 // Note: Long.bitCount(long) returns an int. |
|
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624
diff
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|
5776 instruct popCountL_mem(eRegI dst, memory mem, eRegI tmp, eFlagsReg cr) %{ |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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624
diff
changeset
|
5777 predicate(UsePopCountInstruction); |
|
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624
diff
changeset
|
5778 match(Set dst (PopCountL (LoadL mem))); |
|
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parents:
624
diff
changeset
|
5779 effect(KILL cr, TEMP tmp, TEMP dst); |
|
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parents:
624
diff
changeset
|
5780 |
|
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parents:
624
diff
changeset
|
5781 format %{ "POPCNT $dst, $mem\n\t" |
|
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parents:
624
diff
changeset
|
5782 "POPCNT $tmp, $mem+4\n\t" |
|
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parents:
624
diff
changeset
|
5783 "ADD $dst, $tmp" %} |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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parents:
624
diff
changeset
|
5784 ins_encode %{ |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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624
diff
changeset
|
5785 //__ popcntl($dst$$Register, $mem$$Address$$first); |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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parents:
624
diff
changeset
|
5786 //__ popcntl($tmp$$Register, $mem$$Address$$second); |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5787 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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624
diff
changeset
|
5788 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false)); |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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parents:
624
diff
changeset
|
5789 __ addl($dst$$Register, $tmp$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5790 %} |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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parents:
624
diff
changeset
|
5791 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5792 %} |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
624
diff
changeset
|
5793 |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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parents:
624
diff
changeset
|
5794 |
| 0 | 5795 //----------Load/Store/Move Instructions--------------------------------------- |
| 5796 //----------Load Instructions-------------------------------------------------- | |
| 5797 // Load Byte (8bit signed) | |
| 5798 instruct loadB(xRegI dst, memory mem) %{ | |
| 5799 match(Set dst (LoadB mem)); | |
| 5800 | |
| 5801 ins_cost(125); | |
| 624 | 5802 format %{ "MOVSX8 $dst,$mem\t# byte" %} |
| 5803 | |
| 5804 ins_encode %{ | |
| 5805 __ movsbl($dst$$Register, $mem$$Address); | |
| 5806 %} | |
| 5807 | |
| 5808 ins_pipe(ialu_reg_mem); | |
| 5809 %} | |
| 5810 | |
| 5811 // Load Byte (8bit signed) into Long Register | |
| 824 | 5812 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5813 match(Set dst (ConvI2L (LoadB mem))); |
| 824 | 5814 effect(KILL cr); |
| 624 | 5815 |
| 5816 ins_cost(375); | |
| 5817 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t" | |
| 5818 "MOV $dst.hi,$dst.lo\n\t" | |
| 5819 "SAR $dst.hi,7" %} | |
| 5820 | |
| 5821 ins_encode %{ | |
| 5822 __ movsbl($dst$$Register, $mem$$Address); | |
| 5823 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 5824 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended. | |
| 5825 %} | |
| 5826 | |
| 5827 ins_pipe(ialu_reg_mem); | |
| 5828 %} | |
| 5829 | |
| 5830 // Load Unsigned Byte (8bit UNsigned) | |
| 5831 instruct loadUB(xRegI dst, memory mem) %{ | |
| 5832 match(Set dst (LoadUB mem)); | |
| 0 | 5833 |
| 5834 ins_cost(125); | |
| 624 | 5835 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %} |
| 5836 | |
| 5837 ins_encode %{ | |
| 5838 __ movzbl($dst$$Register, $mem$$Address); | |
| 5839 %} | |
| 5840 | |
| 5841 ins_pipe(ialu_reg_mem); | |
| 5842 %} | |
| 5843 | |
| 5844 // Load Unsigned Byte (8 bit UNsigned) into Long Register | |
| 824 | 5845 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5846 match(Set dst (ConvI2L (LoadUB mem))); |
| 824 | 5847 effect(KILL cr); |
| 624 | 5848 |
| 5849 ins_cost(250); | |
| 5850 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t" | |
| 5851 "XOR $dst.hi,$dst.hi" %} | |
| 5852 | |
| 5853 ins_encode %{ | |
| 824 | 5854 Register Rdst = $dst$$Register; |
| 5855 __ movzbl(Rdst, $mem$$Address); | |
| 5856 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5857 %} | |
| 5858 | |
| 5859 ins_pipe(ialu_reg_mem); | |
| 5860 %} | |
| 5861 | |
| 5862 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register | |
| 5863 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{ | |
| 5864 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
| 5865 effect(KILL cr); | |
| 5866 | |
| 5867 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t" | |
| 5868 "XOR $dst.hi,$dst.hi\n\t" | |
| 5869 "AND $dst.lo,$mask" %} | |
| 5870 ins_encode %{ | |
| 5871 Register Rdst = $dst$$Register; | |
| 5872 __ movzbl(Rdst, $mem$$Address); | |
| 5873 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5874 __ andl(Rdst, $mask$$constant); | |
| 5875 %} | |
| 624 | 5876 ins_pipe(ialu_reg_mem); |
| 5877 %} | |
| 5878 | |
| 5879 // Load Short (16bit signed) | |
| 5880 instruct loadS(eRegI dst, memory mem) %{ | |
| 5881 match(Set dst (LoadS mem)); | |
| 5882 | |
| 5883 ins_cost(125); | |
| 5884 format %{ "MOVSX $dst,$mem\t# short" %} | |
| 5885 | |
| 5886 ins_encode %{ | |
| 5887 __ movswl($dst$$Register, $mem$$Address); | |
| 5888 %} | |
| 5889 | |
| 5890 ins_pipe(ialu_reg_mem); | |
| 5891 %} | |
| 5892 | |
| 785 | 5893 // Load Short (16 bit signed) to Byte (8 bit signed) |
| 5894 instruct loadS2B(eRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 5895 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); | |
| 5896 | |
| 5897 ins_cost(125); | |
| 5898 format %{ "MOVSX $dst, $mem\t# short -> byte" %} | |
| 5899 ins_encode %{ | |
| 5900 __ movsbl($dst$$Register, $mem$$Address); | |
| 5901 %} | |
| 5902 ins_pipe(ialu_reg_mem); | |
| 5903 %} | |
| 5904 | |
| 624 | 5905 // Load Short (16bit signed) into Long Register |
| 824 | 5906 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5907 match(Set dst (ConvI2L (LoadS mem))); |
| 824 | 5908 effect(KILL cr); |
| 624 | 5909 |
| 5910 ins_cost(375); | |
| 5911 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t" | |
| 5912 "MOV $dst.hi,$dst.lo\n\t" | |
| 5913 "SAR $dst.hi,15" %} | |
| 5914 | |
| 5915 ins_encode %{ | |
| 5916 __ movswl($dst$$Register, $mem$$Address); | |
| 5917 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 5918 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended. | |
| 5919 %} | |
| 5920 | |
| 5921 ins_pipe(ialu_reg_mem); | |
| 0 | 5922 %} |
| 5923 | |
|
558
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
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parents:
420
diff
changeset
|
5924 // Load Unsigned Short/Char (16bit unsigned) |
|
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
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parents:
420
diff
changeset
|
5925 instruct loadUS(eRegI dst, memory mem) %{ |
|
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
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parents:
420
diff
changeset
|
5926 match(Set dst (LoadUS mem)); |
| 0 | 5927 |
| 5928 ins_cost(125); | |
| 624 | 5929 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %} |
| 5930 | |
| 5931 ins_encode %{ | |
| 5932 __ movzwl($dst$$Register, $mem$$Address); | |
| 5933 %} | |
| 5934 | |
| 5935 ins_pipe(ialu_reg_mem); | |
| 5936 %} | |
| 5937 | |
| 785 | 5938 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
| 5939 instruct loadUS2B(eRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 5940 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); | |
| 5941 | |
| 5942 ins_cost(125); | |
| 5943 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %} | |
| 5944 ins_encode %{ | |
| 5945 __ movsbl($dst$$Register, $mem$$Address); | |
| 5946 %} | |
| 5947 ins_pipe(ialu_reg_mem); | |
| 5948 %} | |
| 5949 | |
| 624 | 5950 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register |
| 824 | 5951 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 5952 match(Set dst (ConvI2L (LoadUS mem))); |
| 824 | 5953 effect(KILL cr); |
| 624 | 5954 |
| 5955 ins_cost(250); | |
| 5956 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t" | |
| 5957 "XOR $dst.hi,$dst.hi" %} | |
| 5958 | |
| 5959 ins_encode %{ | |
| 5960 __ movzwl($dst$$Register, $mem$$Address); | |
| 5961 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register)); | |
| 5962 %} | |
| 5963 | |
| 5964 ins_pipe(ialu_reg_mem); | |
| 0 | 5965 %} |
| 5966 | |
| 824 | 5967 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register |
| 5968 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{ | |
| 5969 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5970 effect(KILL cr); | |
| 5971 | |
| 5972 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t" | |
| 5973 "XOR $dst.hi,$dst.hi" %} | |
| 5974 ins_encode %{ | |
| 5975 Register Rdst = $dst$$Register; | |
| 5976 __ movzbl(Rdst, $mem$$Address); | |
| 5977 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5978 %} | |
| 5979 ins_pipe(ialu_reg_mem); | |
| 5980 %} | |
| 5981 | |
| 5982 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register | |
| 5983 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{ | |
| 5984 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 5985 effect(KILL cr); | |
| 5986 | |
| 5987 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t" | |
| 5988 "XOR $dst.hi,$dst.hi\n\t" | |
| 5989 "AND $dst.lo,$mask" %} | |
| 5990 ins_encode %{ | |
| 5991 Register Rdst = $dst$$Register; | |
| 5992 __ movzwl(Rdst, $mem$$Address); | |
| 5993 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 5994 __ andl(Rdst, $mask$$constant); | |
| 5995 %} | |
| 5996 ins_pipe(ialu_reg_mem); | |
| 5997 %} | |
| 5998 | |
| 0 | 5999 // Load Integer |
| 6000 instruct loadI(eRegI dst, memory mem) %{ | |
| 6001 match(Set dst (LoadI mem)); | |
| 6002 | |
| 6003 ins_cost(125); | |
| 624 | 6004 format %{ "MOV $dst,$mem\t# int" %} |
| 6005 | |
| 6006 ins_encode %{ | |
| 6007 __ movl($dst$$Register, $mem$$Address); | |
| 6008 %} | |
| 6009 | |
| 6010 ins_pipe(ialu_reg_mem); | |
| 6011 %} | |
| 6012 | |
| 785 | 6013 // Load Integer (32 bit signed) to Byte (8 bit signed) |
| 6014 instruct loadI2B(eRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 6015 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); | |
| 6016 | |
| 6017 ins_cost(125); | |
| 6018 format %{ "MOVSX $dst, $mem\t# int -> byte" %} | |
| 6019 ins_encode %{ | |
| 6020 __ movsbl($dst$$Register, $mem$$Address); | |
| 6021 %} | |
| 6022 ins_pipe(ialu_reg_mem); | |
| 6023 %} | |
| 6024 | |
| 6025 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned) | |
| 6026 instruct loadI2UB(eRegI dst, memory mem, immI_255 mask) %{ | |
| 6027 match(Set dst (AndI (LoadI mem) mask)); | |
| 6028 | |
| 6029 ins_cost(125); | |
| 6030 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %} | |
| 6031 ins_encode %{ | |
| 6032 __ movzbl($dst$$Register, $mem$$Address); | |
| 6033 %} | |
| 6034 ins_pipe(ialu_reg_mem); | |
| 6035 %} | |
| 6036 | |
| 6037 // Load Integer (32 bit signed) to Short (16 bit signed) | |
| 6038 instruct loadI2S(eRegI dst, memory mem, immI_16 sixteen) %{ | |
| 6039 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); | |
| 6040 | |
| 6041 ins_cost(125); | |
| 6042 format %{ "MOVSX $dst, $mem\t# int -> short" %} | |
| 6043 ins_encode %{ | |
| 6044 __ movswl($dst$$Register, $mem$$Address); | |
| 6045 %} | |
| 6046 ins_pipe(ialu_reg_mem); | |
| 6047 %} | |
| 6048 | |
| 6049 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned) | |
| 6050 instruct loadI2US(eRegI dst, memory mem, immI_65535 mask) %{ | |
| 6051 match(Set dst (AndI (LoadI mem) mask)); | |
| 6052 | |
| 6053 ins_cost(125); | |
| 6054 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %} | |
| 6055 ins_encode %{ | |
| 6056 __ movzwl($dst$$Register, $mem$$Address); | |
| 6057 %} | |
| 6058 ins_pipe(ialu_reg_mem); | |
| 6059 %} | |
| 6060 | |
| 624 | 6061 // Load Integer into Long Register |
| 824 | 6062 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 6063 match(Set dst (ConvI2L (LoadI mem))); |
| 824 | 6064 effect(KILL cr); |
| 624 | 6065 |
| 6066 ins_cost(375); | |
| 6067 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t" | |
| 6068 "MOV $dst.hi,$dst.lo\n\t" | |
| 6069 "SAR $dst.hi,31" %} | |
| 6070 | |
| 6071 ins_encode %{ | |
| 6072 __ movl($dst$$Register, $mem$$Address); | |
| 6073 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. | |
| 6074 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); | |
| 6075 %} | |
| 6076 | |
| 6077 ins_pipe(ialu_reg_mem); | |
| 6078 %} | |
| 6079 | |
| 824 | 6080 // Load Integer with mask 0xFF into Long Register |
| 6081 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{ | |
| 6082 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 6083 effect(KILL cr); | |
| 6084 | |
| 6085 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t" | |
| 6086 "XOR $dst.hi,$dst.hi" %} | |
| 6087 ins_encode %{ | |
| 6088 Register Rdst = $dst$$Register; | |
| 6089 __ movzbl(Rdst, $mem$$Address); | |
| 6090 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 6091 %} | |
| 6092 ins_pipe(ialu_reg_mem); | |
| 6093 %} | |
| 6094 | |
| 6095 // Load Integer with mask 0xFFFF into Long Register | |
| 6096 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{ | |
| 6097 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 6098 effect(KILL cr); | |
| 6099 | |
| 6100 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t" | |
| 6101 "XOR $dst.hi,$dst.hi" %} | |
| 6102 ins_encode %{ | |
| 6103 Register Rdst = $dst$$Register; | |
| 6104 __ movzwl(Rdst, $mem$$Address); | |
| 6105 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 6106 %} | |
| 6107 ins_pipe(ialu_reg_mem); | |
| 6108 %} | |
| 6109 | |
| 6110 // Load Integer with 32-bit mask into Long Register | |
| 6111 instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{ | |
| 6112 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 6113 effect(KILL cr); | |
| 6114 | |
| 6115 format %{ "MOV $dst.lo,$mem\t# int & 32-bit mask -> long\n\t" | |
| 6116 "XOR $dst.hi,$dst.hi\n\t" | |
| 6117 "AND $dst.lo,$mask" %} | |
| 6118 ins_encode %{ | |
| 6119 Register Rdst = $dst$$Register; | |
| 6120 __ movl(Rdst, $mem$$Address); | |
| 6121 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); | |
| 6122 __ andl(Rdst, $mask$$constant); | |
| 6123 %} | |
| 6124 ins_pipe(ialu_reg_mem); | |
| 6125 %} | |
| 6126 | |
| 624 | 6127 // Load Unsigned Integer into Long Register |
| 824 | 6128 instruct loadUI2L(eRegL dst, memory mem, eFlagsReg cr) %{ |
| 624 | 6129 match(Set dst (LoadUI2L mem)); |
| 824 | 6130 effect(KILL cr); |
| 624 | 6131 |
| 6132 ins_cost(250); | |
| 6133 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t" | |
| 6134 "XOR $dst.hi,$dst.hi" %} | |
| 6135 | |
| 6136 ins_encode %{ | |
| 6137 __ movl($dst$$Register, $mem$$Address); | |
| 6138 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register)); | |
| 6139 %} | |
| 6140 | |
| 6141 ins_pipe(ialu_reg_mem); | |
| 0 | 6142 %} |
| 6143 | |
| 6144 // Load Long. Cannot clobber address while loading, so restrict address | |
| 6145 // register to ESI | |
| 6146 instruct loadL(eRegL dst, load_long_memory mem) %{ | |
| 6147 predicate(!((LoadLNode*)n)->require_atomic_access()); | |
| 6148 match(Set dst (LoadL mem)); | |
| 6149 | |
| 6150 ins_cost(250); | |
| 624 | 6151 format %{ "MOV $dst.lo,$mem\t# long\n\t" |
| 0 | 6152 "MOV $dst.hi,$mem+4" %} |
| 624 | 6153 |
| 6154 ins_encode %{ | |
| 6155 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false); | |
| 6156 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false); | |
| 6157 __ movl($dst$$Register, Amemlo); | |
| 6158 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi); | |
| 6159 %} | |
| 6160 | |
| 6161 ins_pipe(ialu_reg_long_mem); | |
| 0 | 6162 %} |
| 6163 | |
| 6164 // Volatile Load Long. Must be atomic, so do 64-bit FILD | |
| 6165 // then store it down to the stack and reload on the int | |
| 6166 // side. | |
| 6167 instruct loadL_volatile(stackSlotL dst, memory mem) %{ | |
| 6168 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access()); | |
| 6169 match(Set dst (LoadL mem)); | |
| 6170 | |
| 6171 ins_cost(200); | |
| 6172 format %{ "FILD $mem\t# Atomic volatile long load\n\t" | |
| 6173 "FISTp $dst" %} | |
| 6174 ins_encode(enc_loadL_volatile(mem,dst)); | |
| 6175 ins_pipe( fpu_reg_mem ); | |
| 6176 %} | |
| 6177 | |
|
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6178 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{ |
| 0 | 6179 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access()); |
| 6180 match(Set dst (LoadL mem)); | |
| 6181 effect(TEMP tmp); | |
| 6182 ins_cost(180); | |
| 6183 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" | |
| 6184 "MOVSD $dst,$tmp" %} | |
| 4759 | 6185 ins_encode %{ |
| 6186 __ movdbl($tmp$$XMMRegister, $mem$$Address); | |
| 6187 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister); | |
| 6188 %} | |
| 0 | 6189 ins_pipe( pipe_slow ); |
| 6190 %} | |
| 6191 | |
|
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6192 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{ |
| 0 | 6193 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access()); |
| 6194 match(Set dst (LoadL mem)); | |
| 6195 effect(TEMP tmp); | |
| 6196 ins_cost(160); | |
| 6197 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" | |
| 6198 "MOVD $dst.lo,$tmp\n\t" | |
| 6199 "PSRLQ $tmp,32\n\t" | |
| 6200 "MOVD $dst.hi,$tmp" %} | |
| 4759 | 6201 ins_encode %{ |
| 6202 __ movdbl($tmp$$XMMRegister, $mem$$Address); | |
| 6203 __ movdl($dst$$Register, $tmp$$XMMRegister); | |
| 6204 __ psrlq($tmp$$XMMRegister, 32); | |
| 6205 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister); | |
| 6206 %} | |
| 0 | 6207 ins_pipe( pipe_slow ); |
| 6208 %} | |
| 6209 | |
| 6210 // Load Range | |
| 6211 instruct loadRange(eRegI dst, memory mem) %{ | |
| 6212 match(Set dst (LoadRange mem)); | |
| 6213 | |
| 6214 ins_cost(125); | |
| 6215 format %{ "MOV $dst,$mem" %} | |
| 6216 opcode(0x8B); | |
| 6217 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6218 ins_pipe( ialu_reg_mem ); | |
| 6219 %} | |
| 6220 | |
| 6221 | |
| 6222 // Load Pointer | |
| 6223 instruct loadP(eRegP dst, memory mem) %{ | |
| 6224 match(Set dst (LoadP mem)); | |
| 6225 | |
| 6226 ins_cost(125); | |
| 6227 format %{ "MOV $dst,$mem" %} | |
| 6228 opcode(0x8B); | |
| 6229 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6230 ins_pipe( ialu_reg_mem ); | |
| 6231 %} | |
| 6232 | |
| 6233 // Load Klass Pointer | |
| 6234 instruct loadKlass(eRegP dst, memory mem) %{ | |
| 6235 match(Set dst (LoadKlass mem)); | |
| 6236 | |
| 6237 ins_cost(125); | |
| 6238 format %{ "MOV $dst,$mem" %} | |
| 6239 opcode(0x8B); | |
| 6240 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6241 ins_pipe( ialu_reg_mem ); | |
| 6242 %} | |
| 6243 | |
| 6244 // Load Double | |
|
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6245 instruct loadDPR(regDPR dst, memory mem) %{ |
| 0 | 6246 predicate(UseSSE<=1); |
| 6247 match(Set dst (LoadD mem)); | |
| 6248 | |
| 6249 ins_cost(150); | |
| 6250 format %{ "FLD_D ST,$mem\n\t" | |
| 6251 "FSTP $dst" %} | |
| 6252 opcode(0xDD); /* DD /0 */ | |
| 6253 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
|
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6254 Pop_Reg_DPR(dst) ); |
| 0 | 6255 ins_pipe( fpu_reg_mem ); |
| 6256 %} | |
| 6257 | |
| 6258 // Load Double to XMM | |
|
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6259 instruct loadD(regD dst, memory mem) %{ |
| 0 | 6260 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper); |
| 6261 match(Set dst (LoadD mem)); | |
| 6262 ins_cost(145); | |
| 6263 format %{ "MOVSD $dst,$mem" %} | |
| 4759 | 6264 ins_encode %{ |
| 6265 __ movdbl ($dst$$XMMRegister, $mem$$Address); | |
| 6266 %} | |
| 0 | 6267 ins_pipe( pipe_slow ); |
| 6268 %} | |
| 6269 | |
|
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6270 instruct loadD_partial(regD dst, memory mem) %{ |
| 0 | 6271 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper); |
| 6272 match(Set dst (LoadD mem)); | |
| 6273 ins_cost(145); | |
| 6274 format %{ "MOVLPD $dst,$mem" %} | |
| 4759 | 6275 ins_encode %{ |
| 6276 __ movdbl ($dst$$XMMRegister, $mem$$Address); | |
| 6277 %} | |
| 0 | 6278 ins_pipe( pipe_slow ); |
| 6279 %} | |
| 6280 | |
| 6281 // Load to XMM register (single-precision floating point) | |
| 6282 // MOVSS instruction | |
|
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6283 instruct loadF(regF dst, memory mem) %{ |
| 0 | 6284 predicate(UseSSE>=1); |
| 6285 match(Set dst (LoadF mem)); | |
| 6286 ins_cost(145); | |
| 6287 format %{ "MOVSS $dst,$mem" %} | |
| 4759 | 6288 ins_encode %{ |
| 6289 __ movflt ($dst$$XMMRegister, $mem$$Address); | |
| 6290 %} | |
| 0 | 6291 ins_pipe( pipe_slow ); |
| 6292 %} | |
| 6293 | |
| 6294 // Load Float | |
|
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6295 instruct loadFPR(regFPR dst, memory mem) %{ |
| 0 | 6296 predicate(UseSSE==0); |
| 6297 match(Set dst (LoadF mem)); | |
| 6298 | |
| 6299 ins_cost(150); | |
| 6300 format %{ "FLD_S ST,$mem\n\t" | |
| 6301 "FSTP $dst" %} | |
| 6302 opcode(0xD9); /* D9 /0 */ | |
| 6303 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
|
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6304 Pop_Reg_FPR(dst) ); |
| 0 | 6305 ins_pipe( fpu_reg_mem ); |
| 6306 %} | |
| 6307 | |
| 6308 // Load Aligned Packed Byte to XMM register | |
|
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6309 instruct loadA8B(regD dst, memory mem) %{ |
| 0 | 6310 predicate(UseSSE>=1); |
| 6311 match(Set dst (Load8B mem)); | |
| 6312 ins_cost(125); | |
| 6313 format %{ "MOVQ $dst,$mem\t! packed8B" %} | |
| 4759 | 6314 ins_encode %{ |
| 6315 __ movq($dst$$XMMRegister, $mem$$Address); | |
| 6316 %} | |
| 0 | 6317 ins_pipe( pipe_slow ); |
| 6318 %} | |
| 6319 | |
| 6320 // Load Aligned Packed Short to XMM register | |
|
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6321 instruct loadA4S(regD dst, memory mem) %{ |
| 0 | 6322 predicate(UseSSE>=1); |
| 6323 match(Set dst (Load4S mem)); | |
| 6324 ins_cost(125); | |
| 6325 format %{ "MOVQ $dst,$mem\t! packed4S" %} | |
| 4759 | 6326 ins_encode %{ |
| 6327 __ movq($dst$$XMMRegister, $mem$$Address); | |
| 6328 %} | |
| 0 | 6329 ins_pipe( pipe_slow ); |
| 6330 %} | |
| 6331 | |
| 6332 // Load Aligned Packed Char to XMM register | |
|
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6333 instruct loadA4C(regD dst, memory mem) %{ |
| 0 | 6334 predicate(UseSSE>=1); |
| 6335 match(Set dst (Load4C mem)); | |
| 6336 ins_cost(125); | |
| 6337 format %{ "MOVQ $dst,$mem\t! packed4C" %} | |
| 4759 | 6338 ins_encode %{ |
| 6339 __ movq($dst$$XMMRegister, $mem$$Address); | |
| 6340 %} | |
| 0 | 6341 ins_pipe( pipe_slow ); |
| 6342 %} | |
| 6343 | |
| 6344 // Load Aligned Packed Integer to XMM register | |
|
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6345 instruct load2IU(regD dst, memory mem) %{ |
| 0 | 6346 predicate(UseSSE>=1); |
| 6347 match(Set dst (Load2I mem)); | |
| 6348 ins_cost(125); | |
| 6349 format %{ "MOVQ $dst,$mem\t! packed2I" %} | |
| 4759 | 6350 ins_encode %{ |
| 6351 __ movq($dst$$XMMRegister, $mem$$Address); | |
| 6352 %} | |
| 0 | 6353 ins_pipe( pipe_slow ); |
| 6354 %} | |
| 6355 | |
| 6356 // Load Aligned Packed Single to XMM | |
|
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6357 instruct loadA2F(regD dst, memory mem) %{ |
| 0 | 6358 predicate(UseSSE>=1); |
| 6359 match(Set dst (Load2F mem)); | |
| 6360 ins_cost(145); | |
| 6361 format %{ "MOVQ $dst,$mem\t! packed2F" %} | |
| 4759 | 6362 ins_encode %{ |
| 6363 __ movq($dst$$XMMRegister, $mem$$Address); | |
| 6364 %} | |
| 0 | 6365 ins_pipe( pipe_slow ); |
| 6366 %} | |
| 6367 | |
| 6368 // Load Effective Address | |
| 6369 instruct leaP8(eRegP dst, indOffset8 mem) %{ | |
| 6370 match(Set dst mem); | |
| 6371 | |
| 6372 ins_cost(110); | |
| 6373 format %{ "LEA $dst,$mem" %} | |
| 6374 opcode(0x8D); | |
| 6375 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6376 ins_pipe( ialu_reg_reg_fat ); | |
| 6377 %} | |
| 6378 | |
| 6379 instruct leaP32(eRegP dst, indOffset32 mem) %{ | |
| 6380 match(Set dst mem); | |
| 6381 | |
| 6382 ins_cost(110); | |
| 6383 format %{ "LEA $dst,$mem" %} | |
| 6384 opcode(0x8D); | |
| 6385 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6386 ins_pipe( ialu_reg_reg_fat ); | |
| 6387 %} | |
| 6388 | |
| 6389 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{ | |
| 6390 match(Set dst mem); | |
| 6391 | |
| 6392 ins_cost(110); | |
| 6393 format %{ "LEA $dst,$mem" %} | |
| 6394 opcode(0x8D); | |
| 6395 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6396 ins_pipe( ialu_reg_reg_fat ); | |
| 6397 %} | |
| 6398 | |
| 6399 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{ | |
| 6400 match(Set dst mem); | |
| 6401 | |
| 6402 ins_cost(110); | |
| 6403 format %{ "LEA $dst,$mem" %} | |
| 6404 opcode(0x8D); | |
| 6405 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6406 ins_pipe( ialu_reg_reg_fat ); | |
| 6407 %} | |
| 6408 | |
| 6409 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{ | |
| 6410 match(Set dst mem); | |
| 6411 | |
| 6412 ins_cost(110); | |
| 6413 format %{ "LEA $dst,$mem" %} | |
| 6414 opcode(0x8D); | |
| 6415 ins_encode( OpcP, RegMem(dst,mem)); | |
| 6416 ins_pipe( ialu_reg_reg_fat ); | |
| 6417 %} | |
| 6418 | |
| 6419 // Load Constant | |
| 6420 instruct loadConI(eRegI dst, immI src) %{ | |
| 6421 match(Set dst src); | |
| 6422 | |
| 6423 format %{ "MOV $dst,$src" %} | |
| 6424 ins_encode( LdImmI(dst, src) ); | |
| 6425 ins_pipe( ialu_reg_fat ); | |
| 6426 %} | |
| 6427 | |
| 6428 // Load Constant zero | |
| 6429 instruct loadConI0(eRegI dst, immI0 src, eFlagsReg cr) %{ | |
| 6430 match(Set dst src); | |
| 6431 effect(KILL cr); | |
| 6432 | |
| 6433 ins_cost(50); | |
| 6434 format %{ "XOR $dst,$dst" %} | |
| 6435 opcode(0x33); /* + rd */ | |
| 6436 ins_encode( OpcP, RegReg( dst, dst ) ); | |
| 6437 ins_pipe( ialu_reg ); | |
| 6438 %} | |
| 6439 | |
| 6440 instruct loadConP(eRegP dst, immP src) %{ | |
| 6441 match(Set dst src); | |
| 6442 | |
| 6443 format %{ "MOV $dst,$src" %} | |
| 6444 opcode(0xB8); /* + rd */ | |
| 6445 ins_encode( LdImmP(dst, src) ); | |
| 6446 ins_pipe( ialu_reg_fat ); | |
| 6447 %} | |
| 6448 | |
| 6449 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 6450 match(Set dst src); | |
| 6451 effect(KILL cr); | |
| 6452 ins_cost(200); | |
| 6453 format %{ "MOV $dst.lo,$src.lo\n\t" | |
| 6454 "MOV $dst.hi,$src.hi" %} | |
| 6455 opcode(0xB8); | |
| 6456 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) ); | |
| 6457 ins_pipe( ialu_reg_long_fat ); | |
| 6458 %} | |
| 6459 | |
| 6460 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{ | |
| 6461 match(Set dst src); | |
| 6462 effect(KILL cr); | |
| 6463 ins_cost(150); | |
| 6464 format %{ "XOR $dst.lo,$dst.lo\n\t" | |
| 6465 "XOR $dst.hi,$dst.hi" %} | |
| 6466 opcode(0x33,0x33); | |
| 6467 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) ); | |
| 6468 ins_pipe( ialu_reg_long ); | |
| 6469 %} | |
| 6470 | |
|
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6471 // The instruction usage is guarded by predicate in operand immFPR(). |
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6472 instruct loadConFPR(regFPR dst, immFPR con) %{ |
| 2008 | 6473 match(Set dst con); |
| 6474 ins_cost(125); | |
| 6475 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 6476 "FSTP $dst" %} | |
| 6477 ins_encode %{ | |
| 6478 __ fld_s($constantaddress($con)); | |
| 6479 __ fstp_d($dst$$reg); | |
| 6480 %} | |
| 6481 ins_pipe(fpu_reg_con); | |
| 6482 %} | |
| 6483 | |
|
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6484 // The instruction usage is guarded by predicate in operand immFPR0(). |
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6485 instruct loadConFPR0(regFPR dst, immFPR0 con) %{ |
| 2008 | 6486 match(Set dst con); |
| 0 | 6487 ins_cost(125); |
| 2008 | 6488 format %{ "FLDZ ST\n\t" |
| 0 | 6489 "FSTP $dst" %} |
| 2008 | 6490 ins_encode %{ |
| 6491 __ fldz(); | |
| 6492 __ fstp_d($dst$$reg); | |
| 6493 %} | |
| 6494 ins_pipe(fpu_reg_con); | |
| 6495 %} | |
| 6496 | |
|
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6497 // The instruction usage is guarded by predicate in operand immFPR1(). |
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6498 instruct loadConFPR1(regFPR dst, immFPR1 con) %{ |
| 2008 | 6499 match(Set dst con); |
| 6500 ins_cost(125); | |
| 6501 format %{ "FLD1 ST\n\t" | |
| 6502 "FSTP $dst" %} | |
| 6503 ins_encode %{ | |
| 6504 __ fld1(); | |
| 6505 __ fstp_d($dst$$reg); | |
| 6506 %} | |
| 6507 ins_pipe(fpu_reg_con); | |
| 0 | 6508 %} |
| 6509 | |
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6510 // The instruction usage is guarded by predicate in operand immF(). |
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6511 instruct loadConF(regF dst, immF con) %{ |
| 0 | 6512 match(Set dst con); |
| 6513 ins_cost(125); | |
| 2008 | 6514 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %} |
| 6515 ins_encode %{ | |
| 6516 __ movflt($dst$$XMMRegister, $constantaddress($con)); | |
| 6517 %} | |
| 6518 ins_pipe(pipe_slow); | |
| 0 | 6519 %} |
| 6520 | |
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6521 // The instruction usage is guarded by predicate in operand immF0(). |
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6522 instruct loadConF0(regF dst, immF0 src) %{ |
| 0 | 6523 match(Set dst src); |
| 6524 ins_cost(100); | |
| 6525 format %{ "XORPS $dst,$dst\t# float 0.0" %} | |
| 2008 | 6526 ins_encode %{ |
| 6527 __ xorps($dst$$XMMRegister, $dst$$XMMRegister); | |
| 6528 %} | |
| 6529 ins_pipe(pipe_slow); | |
| 0 | 6530 %} |
| 6531 | |
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6532 // The instruction usage is guarded by predicate in operand immDPR(). |
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6533 instruct loadConDPR(regDPR dst, immDPR con) %{ |
| 2008 | 6534 match(Set dst con); |
| 6535 ins_cost(125); | |
| 6536 | |
| 6537 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t" | |
| 6538 "FSTP $dst" %} | |
| 6539 ins_encode %{ | |
| 6540 __ fld_d($constantaddress($con)); | |
| 6541 __ fstp_d($dst$$reg); | |
| 6542 %} | |
| 6543 ins_pipe(fpu_reg_con); | |
| 6544 %} | |
| 6545 | |
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6546 // The instruction usage is guarded by predicate in operand immDPR0(). |
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6547 instruct loadConDPR0(regDPR dst, immDPR0 con) %{ |
| 2008 | 6548 match(Set dst con); |
| 0 | 6549 ins_cost(125); |
| 6550 | |
| 2008 | 6551 format %{ "FLDZ ST\n\t" |
| 0 | 6552 "FSTP $dst" %} |
| 2008 | 6553 ins_encode %{ |
| 6554 __ fldz(); | |
| 6555 __ fstp_d($dst$$reg); | |
| 6556 %} | |
| 6557 ins_pipe(fpu_reg_con); | |
| 6558 %} | |
| 6559 | |
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6560 // The instruction usage is guarded by predicate in operand immDPR1(). |
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6561 instruct loadConDPR1(regDPR dst, immDPR1 con) %{ |
| 2008 | 6562 match(Set dst con); |
| 6563 ins_cost(125); | |
| 6564 | |
| 6565 format %{ "FLD1 ST\n\t" | |
| 6566 "FSTP $dst" %} | |
| 6567 ins_encode %{ | |
| 6568 __ fld1(); | |
| 6569 __ fstp_d($dst$$reg); | |
| 6570 %} | |
| 6571 ins_pipe(fpu_reg_con); | |
| 0 | 6572 %} |
| 6573 | |
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6574 // The instruction usage is guarded by predicate in operand immD(). |
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6575 instruct loadConD(regD dst, immD con) %{ |
| 0 | 6576 match(Set dst con); |
| 6577 ins_cost(125); | |
| 2008 | 6578 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %} |
| 6579 ins_encode %{ | |
| 6580 __ movdbl($dst$$XMMRegister, $constantaddress($con)); | |
| 6581 %} | |
| 6582 ins_pipe(pipe_slow); | |
| 0 | 6583 %} |
| 6584 | |
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6585 // The instruction usage is guarded by predicate in operand immD0(). |
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6586 instruct loadConD0(regD dst, immD0 src) %{ |
| 0 | 6587 match(Set dst src); |
| 6588 ins_cost(100); | |
| 6589 format %{ "XORPD $dst,$dst\t# double 0.0" %} | |
| 4759 | 6590 ins_encode %{ |
| 6591 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister); | |
| 6592 %} | |
| 0 | 6593 ins_pipe( pipe_slow ); |
| 6594 %} | |
| 6595 | |
| 6596 // Load Stack Slot | |
| 6597 instruct loadSSI(eRegI dst, stackSlotI src) %{ | |
| 6598 match(Set dst src); | |
| 6599 ins_cost(125); | |
| 6600 | |
| 6601 format %{ "MOV $dst,$src" %} | |
| 6602 opcode(0x8B); | |
| 6603 ins_encode( OpcP, RegMem(dst,src)); | |
| 6604 ins_pipe( ialu_reg_mem ); | |
| 6605 %} | |
| 6606 | |
| 6607 instruct loadSSL(eRegL dst, stackSlotL src) %{ | |
| 6608 match(Set dst src); | |
| 6609 | |
| 6610 ins_cost(200); | |
| 6611 format %{ "MOV $dst,$src.lo\n\t" | |
| 6612 "MOV $dst+4,$src.hi" %} | |
| 6613 opcode(0x8B, 0x8B); | |
| 6614 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) ); | |
| 6615 ins_pipe( ialu_mem_long_reg ); | |
| 6616 %} | |
| 6617 | |
| 6618 // Load Stack Slot | |
| 6619 instruct loadSSP(eRegP dst, stackSlotP src) %{ | |
| 6620 match(Set dst src); | |
| 6621 ins_cost(125); | |
| 6622 | |
| 6623 format %{ "MOV $dst,$src" %} | |
| 6624 opcode(0x8B); | |
| 6625 ins_encode( OpcP, RegMem(dst,src)); | |
| 6626 ins_pipe( ialu_reg_mem ); | |
| 6627 %} | |
| 6628 | |
| 6629 // Load Stack Slot | |
|
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6630 instruct loadSSF(regFPR dst, stackSlotF src) %{ |
| 0 | 6631 match(Set dst src); |
| 6632 ins_cost(125); | |
| 6633 | |
| 6634 format %{ "FLD_S $src\n\t" | |
| 6635 "FSTP $dst" %} | |
| 6636 opcode(0xD9); /* D9 /0, FLD m32real */ | |
| 6637 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
|
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6638 Pop_Reg_FPR(dst) ); |
| 0 | 6639 ins_pipe( fpu_reg_mem ); |
| 6640 %} | |
| 6641 | |
| 6642 // Load Stack Slot | |
|
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6643 instruct loadSSD(regDPR dst, stackSlotD src) %{ |
| 0 | 6644 match(Set dst src); |
| 6645 ins_cost(125); | |
| 6646 | |
| 6647 format %{ "FLD_D $src\n\t" | |
| 6648 "FSTP $dst" %} | |
| 6649 opcode(0xDD); /* DD /0, FLD m64real */ | |
| 6650 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
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6651 Pop_Reg_DPR(dst) ); |
| 0 | 6652 ins_pipe( fpu_reg_mem ); |
| 6653 %} | |
| 6654 | |
| 6655 // Prefetch instructions. | |
| 6656 // Must be safe to execute with invalid address (cannot fault). | |
| 6657 | |
| 6658 instruct prefetchr0( memory mem ) %{ | |
| 2479 | 6659 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch()); |
| 0 | 6660 match(PrefetchRead mem); |
| 6661 ins_cost(0); | |
| 6662 size(0); | |
| 6663 format %{ "PREFETCHR (non-SSE is empty encoding)" %} | |
| 6664 ins_encode(); | |
| 6665 ins_pipe(empty); | |
| 6666 %} | |
| 6667 | |
| 6668 instruct prefetchr( memory mem ) %{ | |
| 2479 | 6669 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3); |
| 0 | 6670 match(PrefetchRead mem); |
| 6671 ins_cost(100); | |
| 6672 | |
| 6673 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %} | |
| 3854 | 6674 ins_encode %{ |
| 6675 __ prefetchr($mem$$Address); | |
| 6676 %} | |
| 0 | 6677 ins_pipe(ialu_mem); |
| 6678 %} | |
| 6679 | |
| 6680 instruct prefetchrNTA( memory mem ) %{ | |
| 6681 predicate(UseSSE>=1 && ReadPrefetchInstr==0); | |
| 6682 match(PrefetchRead mem); | |
| 6683 ins_cost(100); | |
| 6684 | |
| 6685 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %} | |
| 3854 | 6686 ins_encode %{ |
| 6687 __ prefetchnta($mem$$Address); | |
| 6688 %} | |
| 0 | 6689 ins_pipe(ialu_mem); |
| 6690 %} | |
| 6691 | |
| 6692 instruct prefetchrT0( memory mem ) %{ | |
| 6693 predicate(UseSSE>=1 && ReadPrefetchInstr==1); | |
| 6694 match(PrefetchRead mem); | |
| 6695 ins_cost(100); | |
| 6696 | |
| 6697 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %} | |
| 3854 | 6698 ins_encode %{ |
| 6699 __ prefetcht0($mem$$Address); | |
| 6700 %} | |
| 0 | 6701 ins_pipe(ialu_mem); |
| 6702 %} | |
| 6703 | |
| 6704 instruct prefetchrT2( memory mem ) %{ | |
| 6705 predicate(UseSSE>=1 && ReadPrefetchInstr==2); | |
| 6706 match(PrefetchRead mem); | |
| 6707 ins_cost(100); | |
| 6708 | |
| 6709 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %} | |
| 3854 | 6710 ins_encode %{ |
| 6711 __ prefetcht2($mem$$Address); | |
| 6712 %} | |
| 0 | 6713 ins_pipe(ialu_mem); |
| 6714 %} | |
| 6715 | |
| 6716 instruct prefetchw0( memory mem ) %{ | |
| 2479 | 6717 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch()); |
| 0 | 6718 match(PrefetchWrite mem); |
| 6719 ins_cost(0); | |
| 6720 size(0); | |
| 6721 format %{ "Prefetch (non-SSE is empty encoding)" %} | |
| 6722 ins_encode(); | |
| 6723 ins_pipe(empty); | |
| 6724 %} | |
| 6725 | |
| 6726 instruct prefetchw( memory mem ) %{ | |
| 3854 | 6727 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch()); |
| 0 | 6728 match( PrefetchWrite mem ); |
| 6729 ins_cost(100); | |
| 6730 | |
| 6731 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %} | |
| 3854 | 6732 ins_encode %{ |
| 6733 __ prefetchw($mem$$Address); | |
| 6734 %} | |
| 0 | 6735 ins_pipe(ialu_mem); |
| 6736 %} | |
| 6737 | |
| 6738 instruct prefetchwNTA( memory mem ) %{ | |
| 3854 | 6739 predicate(UseSSE>=1); |
| 0 | 6740 match(PrefetchWrite mem); |
| 6741 ins_cost(100); | |
| 6742 | |
| 6743 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %} | |
| 3854 | 6744 ins_encode %{ |
| 6745 __ prefetchnta($mem$$Address); | |
| 6746 %} | |
| 0 | 6747 ins_pipe(ialu_mem); |
| 6748 %} | |
| 6749 | |
| 3854 | 6750 // Prefetch instructions for allocation. |
| 6751 | |
| 6752 instruct prefetchAlloc0( memory mem ) %{ | |
| 6753 predicate(UseSSE==0 && AllocatePrefetchInstr!=3); | |
| 6754 match(PrefetchAllocation mem); | |
| 6755 ins_cost(0); | |
| 6756 size(0); | |
| 6757 format %{ "Prefetch allocation (non-SSE is empty encoding)" %} | |
| 6758 ins_encode(); | |
| 6759 ins_pipe(empty); | |
| 6760 %} | |
| 6761 | |
| 6762 instruct prefetchAlloc( memory mem ) %{ | |
| 6763 predicate(AllocatePrefetchInstr==3); | |
| 6764 match( PrefetchAllocation mem ); | |
| 0 | 6765 ins_cost(100); |
| 6766 | |
| 3854 | 6767 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %} |
| 6768 ins_encode %{ | |
| 6769 __ prefetchw($mem$$Address); | |
| 6770 %} | |
| 6771 ins_pipe(ialu_mem); | |
| 6772 %} | |
| 6773 | |
| 6774 instruct prefetchAllocNTA( memory mem ) %{ | |
| 6775 predicate(UseSSE>=1 && AllocatePrefetchInstr==0); | |
| 6776 match(PrefetchAllocation mem); | |
| 6777 ins_cost(100); | |
| 6778 | |
| 6779 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %} | |
| 6780 ins_encode %{ | |
| 6781 __ prefetchnta($mem$$Address); | |
| 6782 %} | |
| 0 | 6783 ins_pipe(ialu_mem); |
| 6784 %} | |
| 6785 | |
| 3854 | 6786 instruct prefetchAllocT0( memory mem ) %{ |
| 6787 predicate(UseSSE>=1 && AllocatePrefetchInstr==1); | |
| 6788 match(PrefetchAllocation mem); | |
| 0 | 6789 ins_cost(100); |
| 6790 | |
| 3854 | 6791 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %} |
| 6792 ins_encode %{ | |
| 6793 __ prefetcht0($mem$$Address); | |
| 6794 %} | |
| 6795 ins_pipe(ialu_mem); | |
| 6796 %} | |
| 6797 | |
| 6798 instruct prefetchAllocT2( memory mem ) %{ | |
| 6799 predicate(UseSSE>=1 && AllocatePrefetchInstr==2); | |
| 6800 match(PrefetchAllocation mem); | |
| 6801 ins_cost(100); | |
| 6802 | |
| 6803 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %} | |
| 6804 ins_encode %{ | |
| 6805 __ prefetcht2($mem$$Address); | |
| 6806 %} | |
| 0 | 6807 ins_pipe(ialu_mem); |
| 6808 %} | |
| 6809 | |
| 6810 //----------Store Instructions------------------------------------------------- | |
| 6811 | |
| 6812 // Store Byte | |
| 6813 instruct storeB(memory mem, xRegI src) %{ | |
| 6814 match(Set mem (StoreB mem src)); | |
| 6815 | |
| 6816 ins_cost(125); | |
| 6817 format %{ "MOV8 $mem,$src" %} | |
| 6818 opcode(0x88); | |
| 6819 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 6820 ins_pipe( ialu_mem_reg ); | |
| 6821 %} | |
| 6822 | |
| 6823 // Store Char/Short | |
| 6824 instruct storeC(memory mem, eRegI src) %{ | |
| 6825 match(Set mem (StoreC mem src)); | |
| 6826 | |
| 6827 ins_cost(125); | |
| 6828 format %{ "MOV16 $mem,$src" %} | |
| 6829 opcode(0x89, 0x66); | |
| 6830 ins_encode( OpcS, OpcP, RegMem( src, mem ) ); | |
| 6831 ins_pipe( ialu_mem_reg ); | |
| 6832 %} | |
| 6833 | |
| 6834 // Store Integer | |
| 6835 instruct storeI(memory mem, eRegI src) %{ | |
| 6836 match(Set mem (StoreI mem src)); | |
| 6837 | |
| 6838 ins_cost(125); | |
| 6839 format %{ "MOV $mem,$src" %} | |
| 6840 opcode(0x89); | |
| 6841 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 6842 ins_pipe( ialu_mem_reg ); | |
| 6843 %} | |
| 6844 | |
| 6845 // Store Long | |
| 6846 instruct storeL(long_memory mem, eRegL src) %{ | |
| 6847 predicate(!((StoreLNode*)n)->require_atomic_access()); | |
| 6848 match(Set mem (StoreL mem src)); | |
| 6849 | |
| 6850 ins_cost(200); | |
| 6851 format %{ "MOV $mem,$src.lo\n\t" | |
| 6852 "MOV $mem+4,$src.hi" %} | |
| 6853 opcode(0x89, 0x89); | |
| 6854 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) ); | |
| 6855 ins_pipe( ialu_mem_long_reg ); | |
| 6856 %} | |
| 6857 | |
| 824 | 6858 // Store Long to Integer |
| 6859 instruct storeL2I(memory mem, eRegL src) %{ | |
| 6860 match(Set mem (StoreI mem (ConvL2I src))); | |
| 6861 | |
| 6862 format %{ "MOV $mem,$src.lo\t# long -> int" %} | |
| 6863 ins_encode %{ | |
| 6864 __ movl($mem$$Address, $src$$Register); | |
| 6865 %} | |
| 6866 ins_pipe(ialu_mem_reg); | |
| 6867 %} | |
| 6868 | |
| 0 | 6869 // Volatile Store Long. Must be atomic, so move it into |
| 6870 // the FP TOS and then do a 64-bit FIST. Has to probe the | |
| 6871 // target address before the store (for null-ptr checks) | |
| 6872 // so the memory operand is used twice in the encoding. | |
| 6873 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{ | |
| 6874 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access()); | |
| 6875 match(Set mem (StoreL mem src)); | |
| 6876 effect( KILL cr ); | |
| 6877 ins_cost(400); | |
| 6878 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 6879 "FILD $src\n\t" | |
| 6880 "FISTp $mem\t # 64-bit atomic volatile long store" %} | |
| 6881 opcode(0x3B); | |
| 6882 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src)); | |
| 6883 ins_pipe( fpu_reg_mem ); | |
| 6884 %} | |
| 6885 | |
|
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6886 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{ |
| 0 | 6887 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access()); |
| 6888 match(Set mem (StoreL mem src)); | |
| 6889 effect( TEMP tmp, KILL cr ); | |
| 6890 ins_cost(380); | |
| 6891 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 6892 "MOVSD $tmp,$src\n\t" | |
| 6893 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %} | |
| 4759 | 6894 ins_encode %{ |
| 6895 __ cmpl(rax, $mem$$Address); | |
| 6896 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp)); | |
| 6897 __ movdbl($mem$$Address, $tmp$$XMMRegister); | |
| 6898 %} | |
| 0 | 6899 ins_pipe( pipe_slow ); |
| 6900 %} | |
| 6901 | |
|
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6902 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{ |
| 0 | 6903 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access()); |
| 6904 match(Set mem (StoreL mem src)); | |
| 6905 effect( TEMP tmp2 , TEMP tmp, KILL cr ); | |
| 6906 ins_cost(360); | |
| 6907 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" | |
| 6908 "MOVD $tmp,$src.lo\n\t" | |
| 6909 "MOVD $tmp2,$src.hi\n\t" | |
| 6910 "PUNPCKLDQ $tmp,$tmp2\n\t" | |
| 6911 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %} | |
| 4759 | 6912 ins_encode %{ |
| 6913 __ cmpl(rax, $mem$$Address); | |
| 6914 __ movdl($tmp$$XMMRegister, $src$$Register); | |
| 6915 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register)); | |
| 6916 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister); | |
| 6917 __ movdbl($mem$$Address, $tmp$$XMMRegister); | |
| 6918 %} | |
| 0 | 6919 ins_pipe( pipe_slow ); |
| 6920 %} | |
| 6921 | |
| 6922 // Store Pointer; for storing unknown oops and raw pointers | |
| 6923 instruct storeP(memory mem, anyRegP src) %{ | |
| 6924 match(Set mem (StoreP mem src)); | |
| 6925 | |
| 6926 ins_cost(125); | |
| 6927 format %{ "MOV $mem,$src" %} | |
| 6928 opcode(0x89); | |
| 6929 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 6930 ins_pipe( ialu_mem_reg ); | |
| 6931 %} | |
| 6932 | |
| 6933 // Store Integer Immediate | |
| 6934 instruct storeImmI(memory mem, immI src) %{ | |
| 6935 match(Set mem (StoreI mem src)); | |
| 6936 | |
| 6937 ins_cost(150); | |
| 6938 format %{ "MOV $mem,$src" %} | |
| 6939 opcode(0xC7); /* C7 /0 */ | |
| 6940 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src )); | |
| 6941 ins_pipe( ialu_mem_imm ); | |
| 6942 %} | |
| 6943 | |
| 6944 // Store Short/Char Immediate | |
| 6945 instruct storeImmI16(memory mem, immI16 src) %{ | |
| 6946 predicate(UseStoreImmI16); | |
| 6947 match(Set mem (StoreC mem src)); | |
| 6948 | |
| 6949 ins_cost(150); | |
| 6950 format %{ "MOV16 $mem,$src" %} | |
| 6951 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */ | |
| 6952 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src )); | |
| 6953 ins_pipe( ialu_mem_imm ); | |
| 6954 %} | |
| 6955 | |
| 6956 // Store Pointer Immediate; null pointers or constant oops that do not | |
| 6957 // need card-mark barriers. | |
| 6958 instruct storeImmP(memory mem, immP src) %{ | |
| 6959 match(Set mem (StoreP mem src)); | |
| 6960 | |
| 6961 ins_cost(150); | |
| 6962 format %{ "MOV $mem,$src" %} | |
| 6963 opcode(0xC7); /* C7 /0 */ | |
| 6964 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src )); | |
| 6965 ins_pipe( ialu_mem_imm ); | |
| 6966 %} | |
| 6967 | |
| 6968 // Store Byte Immediate | |
| 6969 instruct storeImmB(memory mem, immI8 src) %{ | |
| 6970 match(Set mem (StoreB mem src)); | |
| 6971 | |
| 6972 ins_cost(150); | |
| 6973 format %{ "MOV8 $mem,$src" %} | |
| 6974 opcode(0xC6); /* C6 /0 */ | |
| 6975 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src )); | |
| 6976 ins_pipe( ialu_mem_imm ); | |
| 6977 %} | |
| 6978 | |
| 6979 // Store Aligned Packed Byte XMM register to memory | |
|
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6980 instruct storeA8B(memory mem, regD src) %{ |
| 0 | 6981 predicate(UseSSE>=1); |
| 6982 match(Set mem (Store8B mem src)); | |
| 6983 ins_cost(145); | |
| 6984 format %{ "MOVQ $mem,$src\t! packed8B" %} | |
| 4759 | 6985 ins_encode %{ |
| 6986 __ movq($mem$$Address, $src$$XMMRegister); | |
| 6987 %} | |
| 0 | 6988 ins_pipe( pipe_slow ); |
| 6989 %} | |
| 6990 | |
| 6991 // Store Aligned Packed Char/Short XMM register to memory | |
|
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|
6992 instruct storeA4C(memory mem, regD src) %{ |
| 0 | 6993 predicate(UseSSE>=1); |
| 6994 match(Set mem (Store4C mem src)); | |
| 6995 ins_cost(145); | |
| 6996 format %{ "MOVQ $mem,$src\t! packed4C" %} | |
| 4759 | 6997 ins_encode %{ |
| 6998 __ movq($mem$$Address, $src$$XMMRegister); | |
| 6999 %} | |
| 0 | 7000 ins_pipe( pipe_slow ); |
| 7001 %} | |
| 7002 | |
| 7003 // Store Aligned Packed Integer XMM register to memory | |
|
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|
7004 instruct storeA2I(memory mem, regD src) %{ |
| 0 | 7005 predicate(UseSSE>=1); |
| 7006 match(Set mem (Store2I mem src)); | |
| 7007 ins_cost(145); | |
| 7008 format %{ "MOVQ $mem,$src\t! packed2I" %} | |
| 4759 | 7009 ins_encode %{ |
| 7010 __ movq($mem$$Address, $src$$XMMRegister); | |
| 7011 %} | |
| 0 | 7012 ins_pipe( pipe_slow ); |
| 7013 %} | |
| 7014 | |
| 7015 // Store CMS card-mark Immediate | |
| 7016 instruct storeImmCM(memory mem, immI8 src) %{ | |
| 7017 match(Set mem (StoreCM mem src)); | |
| 7018 | |
| 7019 ins_cost(150); | |
| 7020 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %} | |
| 7021 opcode(0xC6); /* C6 /0 */ | |
| 7022 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src )); | |
| 7023 ins_pipe( ialu_mem_imm ); | |
| 7024 %} | |
| 7025 | |
| 7026 // Store Double | |
|
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7027 instruct storeDPR( memory mem, regDPR1 src) %{ |
| 0 | 7028 predicate(UseSSE<=1); |
| 7029 match(Set mem (StoreD mem src)); | |
| 7030 | |
| 7031 ins_cost(100); | |
| 7032 format %{ "FST_D $mem,$src" %} | |
| 7033 opcode(0xDD); /* DD /2 */ | |
|
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7034 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 7035 ins_pipe( fpu_mem_reg ); |
| 7036 %} | |
| 7037 | |
| 7038 // Store double does rounding on x86 | |
|
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7039 instruct storeDPR_rounded( memory mem, regDPR1 src) %{ |
| 0 | 7040 predicate(UseSSE<=1); |
| 7041 match(Set mem (StoreD mem (RoundDouble src))); | |
| 7042 | |
| 7043 ins_cost(100); | |
| 7044 format %{ "FST_D $mem,$src\t# round" %} | |
| 7045 opcode(0xDD); /* DD /2 */ | |
|
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7046 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 7047 ins_pipe( fpu_mem_reg ); |
| 7048 %} | |
| 7049 | |
| 7050 // Store XMM register to memory (double-precision floating points) | |
| 7051 // MOVSD instruction | |
|
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|
7052 instruct storeD(memory mem, regD src) %{ |
| 0 | 7053 predicate(UseSSE>=2); |
| 7054 match(Set mem (StoreD mem src)); | |
| 7055 ins_cost(95); | |
| 7056 format %{ "MOVSD $mem,$src" %} | |
| 4759 | 7057 ins_encode %{ |
| 7058 __ movdbl($mem$$Address, $src$$XMMRegister); | |
| 7059 %} | |
| 0 | 7060 ins_pipe( pipe_slow ); |
| 7061 %} | |
| 7062 | |
| 7063 // Store XMM register to memory (single-precision floating point) | |
| 7064 // MOVSS instruction | |
|
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7065 instruct storeF(memory mem, regF src) %{ |
| 0 | 7066 predicate(UseSSE>=1); |
| 7067 match(Set mem (StoreF mem src)); | |
| 7068 ins_cost(95); | |
| 7069 format %{ "MOVSS $mem,$src" %} | |
| 4759 | 7070 ins_encode %{ |
| 7071 __ movflt($mem$$Address, $src$$XMMRegister); | |
| 7072 %} | |
| 0 | 7073 ins_pipe( pipe_slow ); |
| 7074 %} | |
| 7075 | |
| 7076 // Store Aligned Packed Single Float XMM register to memory | |
|
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7077 instruct storeA2F(memory mem, regD src) %{ |
| 0 | 7078 predicate(UseSSE>=1); |
| 7079 match(Set mem (Store2F mem src)); | |
| 7080 ins_cost(145); | |
| 7081 format %{ "MOVQ $mem,$src\t! packed2F" %} | |
| 4759 | 7082 ins_encode %{ |
| 7083 __ movq($mem$$Address, $src$$XMMRegister); | |
| 7084 %} | |
| 0 | 7085 ins_pipe( pipe_slow ); |
| 7086 %} | |
| 7087 | |
| 7088 // Store Float | |
|
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|
7089 instruct storeFPR( memory mem, regFPR1 src) %{ |
| 0 | 7090 predicate(UseSSE==0); |
| 7091 match(Set mem (StoreF mem src)); | |
| 7092 | |
| 7093 ins_cost(100); | |
| 7094 format %{ "FST_S $mem,$src" %} | |
| 7095 opcode(0xD9); /* D9 /2 */ | |
|
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|
7096 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 7097 ins_pipe( fpu_mem_reg ); |
| 7098 %} | |
| 7099 | |
| 7100 // Store Float does rounding on x86 | |
|
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7101 instruct storeFPR_rounded( memory mem, regFPR1 src) %{ |
| 0 | 7102 predicate(UseSSE==0); |
| 7103 match(Set mem (StoreF mem (RoundFloat src))); | |
| 7104 | |
| 7105 ins_cost(100); | |
| 7106 format %{ "FST_S $mem,$src\t# round" %} | |
| 7107 opcode(0xD9); /* D9 /2 */ | |
|
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|
7108 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 7109 ins_pipe( fpu_mem_reg ); |
| 7110 %} | |
| 7111 | |
| 7112 // Store Float does rounding on x86 | |
|
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7113 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{ |
| 0 | 7114 predicate(UseSSE<=1); |
| 7115 match(Set mem (StoreF mem (ConvD2F src))); | |
| 7116 | |
| 7117 ins_cost(100); | |
| 7118 format %{ "FST_S $mem,$src\t# D-round" %} | |
| 7119 opcode(0xD9); /* D9 /2 */ | |
|
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|
7120 ins_encode( enc_FPR_store(mem,src) ); |
| 0 | 7121 ins_pipe( fpu_mem_reg ); |
| 7122 %} | |
| 7123 | |
| 7124 // Store immediate Float value (it is faster than store from FPU register) | |
|
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7125 // The instruction usage is guarded by predicate in operand immFPR(). |
|
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7126 instruct storeFPR_imm( memory mem, immFPR src) %{ |
|
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|
7127 match(Set mem (StoreF mem src)); |
|
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|
7128 |
|
65149e74c706
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|
7129 ins_cost(50); |
|
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|
7130 format %{ "MOV $mem,$src\t# store float" %} |
|
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|
7131 opcode(0xC7); /* C7 /0 */ |
|
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|
7132 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src )); |
|
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|
7133 ins_pipe( ialu_mem_imm ); |
|
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|
7134 %} |
|
65149e74c706
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|
7135 |
|
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|
7136 // Store immediate Float value (it is faster than store from XMM register) |
| 0 | 7137 // The instruction usage is guarded by predicate in operand immF(). |
| 7138 instruct storeF_imm( memory mem, immF src) %{ | |
| 7139 match(Set mem (StoreF mem src)); | |
| 7140 | |
| 7141 ins_cost(50); | |
| 7142 format %{ "MOV $mem,$src\t# store float" %} | |
| 7143 opcode(0xC7); /* C7 /0 */ | |
| 7144 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src )); | |
| 7145 ins_pipe( ialu_mem_imm ); | |
| 7146 %} | |
| 7147 | |
| 7148 // Store Integer to stack slot | |
| 7149 instruct storeSSI(stackSlotI dst, eRegI src) %{ | |
| 7150 match(Set dst src); | |
| 7151 | |
| 7152 ins_cost(100); | |
| 7153 format %{ "MOV $dst,$src" %} | |
| 7154 opcode(0x89); | |
| 7155 ins_encode( OpcPRegSS( dst, src ) ); | |
| 7156 ins_pipe( ialu_mem_reg ); | |
| 7157 %} | |
| 7158 | |
| 7159 // Store Integer to stack slot | |
| 7160 instruct storeSSP(stackSlotP dst, eRegP src) %{ | |
| 7161 match(Set dst src); | |
| 7162 | |
| 7163 ins_cost(100); | |
| 7164 format %{ "MOV $dst,$src" %} | |
| 7165 opcode(0x89); | |
| 7166 ins_encode( OpcPRegSS( dst, src ) ); | |
| 7167 ins_pipe( ialu_mem_reg ); | |
| 7168 %} | |
| 7169 | |
| 7170 // Store Long to stack slot | |
| 7171 instruct storeSSL(stackSlotL dst, eRegL src) %{ | |
| 7172 match(Set dst src); | |
| 7173 | |
| 7174 ins_cost(200); | |
| 7175 format %{ "MOV $dst,$src.lo\n\t" | |
| 7176 "MOV $dst+4,$src.hi" %} | |
| 7177 opcode(0x89, 0x89); | |
| 7178 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) ); | |
| 7179 ins_pipe( ialu_mem_long_reg ); | |
| 7180 %} | |
| 7181 | |
| 7182 //----------MemBar Instructions----------------------------------------------- | |
| 7183 // Memory barrier flavors | |
| 7184 | |
| 7185 instruct membar_acquire() %{ | |
| 7186 match(MemBarAcquire); | |
| 7187 ins_cost(400); | |
| 7188 | |
| 7189 size(0); | |
|
671
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diff
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|
7190 format %{ "MEMBAR-acquire ! (empty encoding)" %} |
|
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6822204: volatile fences should prefer lock:addl to actual mfence instructions
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diff
changeset
|
7191 ins_encode(); |
|
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changeset
|
7192 ins_pipe(empty); |
| 0 | 7193 %} |
| 7194 | |
| 7195 instruct membar_acquire_lock() %{ | |
|
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|
7196 match(MemBarAcquireLock); |
| 0 | 7197 ins_cost(0); |
| 7198 | |
| 7199 size(0); | |
| 7200 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %} | |
| 7201 ins_encode( ); | |
| 7202 ins_pipe(empty); | |
| 7203 %} | |
| 7204 | |
| 7205 instruct membar_release() %{ | |
| 7206 match(MemBarRelease); | |
| 7207 ins_cost(400); | |
| 7208 | |
| 7209 size(0); | |
|
671
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|
7210 format %{ "MEMBAR-release ! (empty encoding)" %} |
|
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diff
changeset
|
7211 ins_encode( ); |
|
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|
7212 ins_pipe(empty); |
| 0 | 7213 %} |
| 7214 | |
| 7215 instruct membar_release_lock() %{ | |
|
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|
7216 match(MemBarReleaseLock); |
| 0 | 7217 ins_cost(0); |
| 7218 | |
| 7219 size(0); | |
| 7220 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %} | |
| 7221 ins_encode( ); | |
| 7222 ins_pipe(empty); | |
| 7223 %} | |
| 7224 | |
|
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|
7225 instruct membar_volatile(eFlagsReg cr) %{ |
| 0 | 7226 match(MemBarVolatile); |
|
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|
7227 effect(KILL cr); |
| 0 | 7228 ins_cost(400); |
| 7229 | |
|
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|
7230 format %{ |
|
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|
7231 $$template |
|
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|
7232 if (os::is_MP()) { |
|
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|
7233 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile" |
|
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|
7234 } else { |
|
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|
7235 $$emit$$"MEMBAR-volatile ! (empty encoding)" |
|
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diff
changeset
|
7236 } |
|
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diff
changeset
|
7237 %} |
|
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diff
changeset
|
7238 ins_encode %{ |
|
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changeset
|
7239 __ membar(Assembler::StoreLoad); |
|
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diff
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|
7240 %} |
| 0 | 7241 ins_pipe(pipe_slow); |
| 7242 %} | |
| 7243 | |
| 7244 instruct unnecessary_membar_volatile() %{ | |
| 7245 match(MemBarVolatile); | |
| 7246 predicate(Matcher::post_store_load_barrier(n)); | |
| 7247 ins_cost(0); | |
| 7248 | |
| 7249 size(0); | |
| 7250 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %} | |
| 7251 ins_encode( ); | |
| 7252 ins_pipe(empty); | |
| 7253 %} | |
| 7254 | |
|
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|
7255 instruct membar_storestore() %{ |
|
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|
7256 match(MemBarStoreStore); |
|
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|
7257 ins_cost(0); |
|
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|
7258 |
|
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|
7259 size(0); |
|
1dc233a8c7fe
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|
7260 format %{ "MEMBAR-storestore (empty encoding)" %} |
|
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changeset
|
7261 ins_encode( ); |
|
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|
7262 ins_pipe(empty); |
|
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diff
changeset
|
7263 %} |
|
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changeset
|
7264 |
| 0 | 7265 //----------Move Instructions-------------------------------------------------- |
| 7266 instruct castX2P(eAXRegP dst, eAXRegI src) %{ | |
| 7267 match(Set dst (CastX2P src)); | |
| 7268 format %{ "# X2P $dst, $src" %} | |
| 7269 ins_encode( /*empty encoding*/ ); | |
| 7270 ins_cost(0); | |
| 7271 ins_pipe(empty); | |
| 7272 %} | |
| 7273 | |
| 7274 instruct castP2X(eRegI dst, eRegP src ) %{ | |
| 7275 match(Set dst (CastP2X src)); | |
| 7276 ins_cost(50); | |
| 7277 format %{ "MOV $dst, $src\t# CastP2X" %} | |
| 7278 ins_encode( enc_Copy( dst, src) ); | |
| 7279 ins_pipe( ialu_reg_reg ); | |
| 7280 %} | |
| 7281 | |
| 7282 //----------Conditional Move--------------------------------------------------- | |
| 7283 // Conditional move | |
| 4047 | 7284 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, eRegI dst, eRegI src) %{ |
| 7285 predicate(!VM_Version::supports_cmov() ); | |
| 7286 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 7287 ins_cost(200); | |
| 7288 format %{ "J$cop,us skip\t# signed cmove\n\t" | |
| 7289 "MOV $dst,$src\n" | |
| 7290 "skip:" %} | |
| 7291 ins_encode %{ | |
| 7292 Label Lskip; | |
| 7293 // Invert sense of branch from sense of CMOV | |
| 7294 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 7295 __ movl($dst$$Register, $src$$Register); | |
| 7296 __ bind(Lskip); | |
| 7297 %} | |
| 7298 ins_pipe( pipe_cmov_reg ); | |
| 7299 %} | |
| 7300 | |
| 7301 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src) %{ | |
| 7302 predicate(!VM_Version::supports_cmov() ); | |
| 7303 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 7304 ins_cost(200); | |
| 7305 format %{ "J$cop,us skip\t# unsigned cmove\n\t" | |
| 7306 "MOV $dst,$src\n" | |
| 7307 "skip:" %} | |
| 7308 ins_encode %{ | |
| 7309 Label Lskip; | |
| 7310 // Invert sense of branch from sense of CMOV | |
| 7311 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); | |
| 7312 __ movl($dst$$Register, $src$$Register); | |
| 7313 __ bind(Lskip); | |
| 7314 %} | |
| 7315 ins_pipe( pipe_cmov_reg ); | |
| 7316 %} | |
| 7317 | |
| 0 | 7318 instruct cmovI_reg(eRegI dst, eRegI src, eFlagsReg cr, cmpOp cop ) %{ |
| 7319 predicate(VM_Version::supports_cmov() ); | |
| 7320 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 7321 ins_cost(200); | |
| 7322 format %{ "CMOV$cop $dst,$src" %} | |
| 7323 opcode(0x0F,0x40); | |
| 7324 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 7325 ins_pipe( pipe_cmov_reg ); | |
| 7326 %} | |
| 7327 | |
|
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|
7328 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src ) %{ |
| 0 | 7329 predicate(VM_Version::supports_cmov() ); |
| 7330 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 7331 ins_cost(200); | |
| 7332 format %{ "CMOV$cop $dst,$src" %} | |
| 7333 opcode(0x0F,0x40); | |
| 7334 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 7335 ins_pipe( pipe_cmov_reg ); | |
| 7336 %} | |
| 7337 | |
|
415
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|
7338 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, eRegI src ) %{ |
|
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|
7339 predicate(VM_Version::supports_cmov() ); |
|
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|
7340 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
|
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|
7341 ins_cost(200); |
|
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diff
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|
7342 expand %{ |
|
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diff
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|
7343 cmovI_regU(cop, cr, dst, src); |
|
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diff
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|
7344 %} |
|
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diff
changeset
|
7345 %} |
|
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diff
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|
7346 |
| 0 | 7347 // Conditional move |
| 7348 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, eRegI dst, memory src) %{ | |
| 7349 predicate(VM_Version::supports_cmov() ); | |
| 7350 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
| 7351 ins_cost(250); | |
| 7352 format %{ "CMOV$cop $dst,$src" %} | |
| 7353 opcode(0x0F,0x40); | |
| 7354 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 7355 ins_pipe( pipe_cmov_mem ); | |
| 7356 %} | |
| 7357 | |
| 7358 // Conditional move | |
|
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|
7359 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, eRegI dst, memory src) %{ |
| 0 | 7360 predicate(VM_Version::supports_cmov() ); |
| 7361 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
| 7362 ins_cost(250); | |
| 7363 format %{ "CMOV$cop $dst,$src" %} | |
| 7364 opcode(0x0F,0x40); | |
| 7365 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 7366 ins_pipe( pipe_cmov_mem ); | |
| 7367 %} | |
| 7368 | |
|
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|
7369 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, memory src) %{ |
|
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changeset
|
7370 predicate(VM_Version::supports_cmov() ); |
|
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|
7371 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
|
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|
7372 ins_cost(250); |
|
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diff
changeset
|
7373 expand %{ |
|
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diff
changeset
|
7374 cmovI_memU(cop, cr, dst, src); |
|
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|
7375 %} |
|
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|
7376 %} |
|
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|
7377 |
| 0 | 7378 // Conditional move |
| 7379 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{ | |
| 7380 predicate(VM_Version::supports_cmov() ); | |
| 7381 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 7382 ins_cost(200); | |
| 7383 format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7384 opcode(0x0F,0x40); | |
| 7385 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 7386 ins_pipe( pipe_cmov_reg ); | |
| 7387 %} | |
| 7388 | |
| 7389 // Conditional move (non-P6 version) | |
| 7390 // Note: a CMoveP is generated for stubs and native wrappers | |
| 7391 // regardless of whether we are on a P6, so we | |
| 7392 // emulate a cmov here | |
| 7393 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{ | |
| 7394 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 7395 ins_cost(300); | |
| 7396 format %{ "Jn$cop skip\n\t" | |
| 7397 "MOV $dst,$src\t# pointer\n" | |
| 7398 "skip:" %} | |
| 7399 opcode(0x8b); | |
| 7400 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src)); | |
| 7401 ins_pipe( pipe_cmov_reg ); | |
| 7402 %} | |
| 7403 | |
| 7404 // Conditional move | |
|
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|
7405 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{ |
| 0 | 7406 predicate(VM_Version::supports_cmov() ); |
| 7407 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 7408 ins_cost(200); | |
| 7409 format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7410 opcode(0x0F,0x40); | |
| 7411 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); | |
| 7412 ins_pipe( pipe_cmov_reg ); | |
| 7413 %} | |
| 7414 | |
|
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|
7415 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{ |
|
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changeset
|
7416 predicate(VM_Version::supports_cmov() ); |
|
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diff
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|
7417 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); |
|
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diff
changeset
|
7418 ins_cost(200); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7419 expand %{ |
|
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403
diff
changeset
|
7420 cmovP_regU(cop, cr, dst, src); |
|
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diff
changeset
|
7421 %} |
|
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diff
changeset
|
7422 %} |
|
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diff
changeset
|
7423 |
| 0 | 7424 // DISABLED: Requires the ADLC to emit a bottom_type call that |
| 7425 // correctly meets the two pointer arguments; one is an incoming | |
| 7426 // register but the other is a memory operand. ALSO appears to | |
| 7427 // be buggy with implicit null checks. | |
| 7428 // | |
| 7429 //// Conditional move | |
| 7430 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{ | |
| 7431 // predicate(VM_Version::supports_cmov() ); | |
| 7432 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 7433 // ins_cost(250); | |
| 7434 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7435 // opcode(0x0F,0x40); | |
| 7436 // ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 7437 // ins_pipe( pipe_cmov_mem ); | |
| 7438 //%} | |
| 7439 // | |
| 7440 //// Conditional move | |
| 7441 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{ | |
| 7442 // predicate(VM_Version::supports_cmov() ); | |
| 7443 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 7444 // ins_cost(250); | |
| 7445 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7446 // opcode(0x0F,0x40); | |
| 7447 // ins_encode( enc_cmov(cop), RegMem( dst, src ) ); | |
| 7448 // ins_pipe( pipe_cmov_mem ); | |
| 7449 //%} | |
| 7450 | |
| 7451 // Conditional move | |
|
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|
7452 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{ |
| 0 | 7453 predicate(UseSSE<=1); |
| 7454 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 7455 ins_cost(200); | |
| 7456 format %{ "FCMOV$cop $dst,$src\t# double" %} | |
| 7457 opcode(0xDA); | |
|
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diff
changeset
|
7458 ins_encode( enc_cmov_dpr(cop,src) ); |
|
65149e74c706
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diff
changeset
|
7459 ins_pipe( pipe_cmovDPR_reg ); |
| 0 | 7460 %} |
| 7461 | |
| 7462 // Conditional move | |
|
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|
7463 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{ |
| 0 | 7464 predicate(UseSSE==0); |
| 7465 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 7466 ins_cost(200); | |
| 7467 format %{ "FCMOV$cop $dst,$src\t# float" %} | |
| 7468 opcode(0xDA); | |
|
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diff
changeset
|
7469 ins_encode( enc_cmov_dpr(cop,src) ); |
|
65149e74c706
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diff
changeset
|
7470 ins_pipe( pipe_cmovDPR_reg ); |
| 0 | 7471 %} |
| 7472 | |
| 7473 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned. | |
|
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|
7474 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{ |
| 0 | 7475 predicate(UseSSE<=1); |
| 7476 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 7477 ins_cost(200); | |
| 7478 format %{ "Jn$cop skip\n\t" | |
| 7479 "MOV $dst,$src\t# double\n" | |
| 7480 "skip:" %} | |
| 7481 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */ | |
|
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|
7482 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) ); |
|
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diff
changeset
|
7483 ins_pipe( pipe_cmovDPR_reg ); |
| 0 | 7484 %} |
| 7485 | |
| 7486 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned. | |
|
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|
7487 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{ |
| 0 | 7488 predicate(UseSSE==0); |
| 7489 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 7490 ins_cost(200); | |
| 7491 format %{ "Jn$cop skip\n\t" | |
| 7492 "MOV $dst,$src\t# float\n" | |
| 7493 "skip:" %} | |
| 7494 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */ | |
|
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|
7495 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) ); |
|
65149e74c706
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diff
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|
7496 ins_pipe( pipe_cmovDPR_reg ); |
| 0 | 7497 %} |
| 7498 | |
| 7499 // No CMOVE with SSE/SSE2 | |
|
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|
7500 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{ |
| 0 | 7501 predicate (UseSSE>=1); |
| 7502 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 7503 ins_cost(200); | |
| 7504 format %{ "Jn$cop skip\n\t" | |
| 7505 "MOVSS $dst,$src\t# float\n" | |
| 7506 "skip:" %} | |
| 7507 ins_encode %{ | |
| 7508 Label skip; | |
| 7509 // Invert sense of branch from sense of CMOV | |
| 7510 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 7511 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 7512 __ bind(skip); | |
| 7513 %} | |
| 7514 ins_pipe( pipe_slow ); | |
| 7515 %} | |
| 7516 | |
| 7517 // No CMOVE with SSE/SSE2 | |
|
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|
7518 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{ |
| 0 | 7519 predicate (UseSSE>=2); |
| 7520 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 7521 ins_cost(200); | |
| 7522 format %{ "Jn$cop skip\n\t" | |
| 7523 "MOVSD $dst,$src\t# float\n" | |
| 7524 "skip:" %} | |
| 7525 ins_encode %{ | |
| 7526 Label skip; | |
| 7527 // Invert sense of branch from sense of CMOV | |
| 7528 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 7529 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 7530 __ bind(skip); | |
| 7531 %} | |
| 7532 ins_pipe( pipe_slow ); | |
| 7533 %} | |
| 7534 | |
| 7535 // unsigned version | |
|
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diff
changeset
|
7536 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{ |
| 0 | 7537 predicate (UseSSE>=1); |
| 7538 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 7539 ins_cost(200); | |
| 7540 format %{ "Jn$cop skip\n\t" | |
| 7541 "MOVSS $dst,$src\t# float\n" | |
| 7542 "skip:" %} | |
| 7543 ins_encode %{ | |
| 7544 Label skip; | |
| 7545 // Invert sense of branch from sense of CMOV | |
| 7546 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 7547 __ movflt($dst$$XMMRegister, $src$$XMMRegister); | |
| 7548 __ bind(skip); | |
| 7549 %} | |
| 7550 ins_pipe( pipe_slow ); | |
| 7551 %} | |
| 7552 | |
|
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changeset
|
7553 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{ |
|
415
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diff
changeset
|
7554 predicate (UseSSE>=1); |
|
4d9884b01ba6
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diff
changeset
|
7555 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
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diff
changeset
|
7556 ins_cost(200); |
|
4d9884b01ba6
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403
diff
changeset
|
7557 expand %{ |
|
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diff
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|
7558 fcmovF_regU(cop, cr, dst, src); |
|
415
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diff
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|
7559 %} |
|
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diff
changeset
|
7560 %} |
|
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diff
changeset
|
7561 |
| 0 | 7562 // unsigned version |
|
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|
7563 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{ |
| 0 | 7564 predicate (UseSSE>=2); |
| 7565 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 7566 ins_cost(200); | |
| 7567 format %{ "Jn$cop skip\n\t" | |
| 7568 "MOVSD $dst,$src\t# float\n" | |
| 7569 "skip:" %} | |
| 7570 ins_encode %{ | |
| 7571 Label skip; | |
| 7572 // Invert sense of branch from sense of CMOV | |
| 7573 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); | |
| 7574 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); | |
| 7575 __ bind(skip); | |
| 7576 %} | |
| 7577 ins_pipe( pipe_slow ); | |
| 7578 %} | |
| 7579 | |
|
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|
7580 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{ |
|
415
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|
7581 predicate (UseSSE>=2); |
|
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diff
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|
7582 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); |
|
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|
7583 ins_cost(200); |
|
4d9884b01ba6
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diff
changeset
|
7584 expand %{ |
|
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diff
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|
7585 fcmovD_regU(cop, cr, dst, src); |
|
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diff
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|
7586 %} |
|
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parents:
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diff
changeset
|
7587 %} |
|
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parents:
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diff
changeset
|
7588 |
| 0 | 7589 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{ |
| 7590 predicate(VM_Version::supports_cmov() ); | |
| 7591 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 7592 ins_cost(200); | |
| 7593 format %{ "CMOV$cop $dst.lo,$src.lo\n\t" | |
| 7594 "CMOV$cop $dst.hi,$src.hi" %} | |
| 7595 opcode(0x0F,0x40); | |
| 7596 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) ); | |
| 7597 ins_pipe( pipe_cmov_reg_long ); | |
| 7598 %} | |
| 7599 | |
| 7600 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{ | |
| 7601 predicate(VM_Version::supports_cmov() ); | |
| 7602 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 7603 ins_cost(200); | |
| 7604 format %{ "CMOV$cop $dst.lo,$src.lo\n\t" | |
| 7605 "CMOV$cop $dst.hi,$src.hi" %} | |
| 7606 opcode(0x0F,0x40); | |
| 7607 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) ); | |
| 7608 ins_pipe( pipe_cmov_reg_long ); | |
| 7609 %} | |
| 7610 | |
|
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|
7611 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{ |
|
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diff
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|
7612 predicate(VM_Version::supports_cmov() ); |
|
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diff
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|
7613 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); |
|
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|
7614 ins_cost(200); |
|
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diff
changeset
|
7615 expand %{ |
|
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diff
changeset
|
7616 cmovL_regU(cop, cr, dst, src); |
|
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diff
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|
7617 %} |
|
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diff
changeset
|
7618 %} |
|
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diff
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|
7619 |
| 0 | 7620 //----------Arithmetic Instructions-------------------------------------------- |
| 7621 //----------Addition Instructions---------------------------------------------- | |
| 7622 // Integer Addition Instructions | |
| 7623 instruct addI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ | |
| 7624 match(Set dst (AddI dst src)); | |
| 7625 effect(KILL cr); | |
| 7626 | |
| 7627 size(2); | |
| 7628 format %{ "ADD $dst,$src" %} | |
| 7629 opcode(0x03); | |
| 7630 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7631 ins_pipe( ialu_reg_reg ); | |
| 7632 %} | |
| 7633 | |
| 7634 instruct addI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ | |
| 7635 match(Set dst (AddI dst src)); | |
| 7636 effect(KILL cr); | |
| 7637 | |
| 7638 format %{ "ADD $dst,$src" %} | |
| 7639 opcode(0x81, 0x00); /* /0 id */ | |
| 7640 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 7641 ins_pipe( ialu_reg ); | |
| 7642 %} | |
| 7643 | |
| 7644 instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ | |
| 7645 predicate(UseIncDec); | |
| 7646 match(Set dst (AddI dst src)); | |
| 7647 effect(KILL cr); | |
| 7648 | |
| 7649 size(1); | |
| 7650 format %{ "INC $dst" %} | |
| 7651 opcode(0x40); /* */ | |
| 7652 ins_encode( Opc_plus( primary, dst ) ); | |
| 7653 ins_pipe( ialu_reg ); | |
| 7654 %} | |
| 7655 | |
| 7656 instruct leaI_eReg_immI(eRegI dst, eRegI src0, immI src1) %{ | |
| 7657 match(Set dst (AddI src0 src1)); | |
| 7658 ins_cost(110); | |
| 7659 | |
| 7660 format %{ "LEA $dst,[$src0 + $src1]" %} | |
| 7661 opcode(0x8D); /* 0x8D /r */ | |
| 7662 ins_encode( OpcP, RegLea( dst, src0, src1 ) ); | |
| 7663 ins_pipe( ialu_reg_reg ); | |
| 7664 %} | |
| 7665 | |
| 7666 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{ | |
| 7667 match(Set dst (AddP src0 src1)); | |
| 7668 ins_cost(110); | |
| 7669 | |
| 7670 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %} | |
| 7671 opcode(0x8D); /* 0x8D /r */ | |
| 7672 ins_encode( OpcP, RegLea( dst, src0, src1 ) ); | |
| 7673 ins_pipe( ialu_reg_reg ); | |
| 7674 %} | |
| 7675 | |
| 7676 instruct decI_eReg(eRegI dst, immI_M1 src, eFlagsReg cr) %{ | |
| 7677 predicate(UseIncDec); | |
| 7678 match(Set dst (AddI dst src)); | |
| 7679 effect(KILL cr); | |
| 7680 | |
| 7681 size(1); | |
| 7682 format %{ "DEC $dst" %} | |
| 7683 opcode(0x48); /* */ | |
| 7684 ins_encode( Opc_plus( primary, dst ) ); | |
| 7685 ins_pipe( ialu_reg ); | |
| 7686 %} | |
| 7687 | |
| 7688 instruct addP_eReg(eRegP dst, eRegI src, eFlagsReg cr) %{ | |
| 7689 match(Set dst (AddP dst src)); | |
| 7690 effect(KILL cr); | |
| 7691 | |
| 7692 size(2); | |
| 7693 format %{ "ADD $dst,$src" %} | |
| 7694 opcode(0x03); | |
| 7695 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7696 ins_pipe( ialu_reg_reg ); | |
| 7697 %} | |
| 7698 | |
| 7699 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{ | |
| 7700 match(Set dst (AddP dst src)); | |
| 7701 effect(KILL cr); | |
| 7702 | |
| 7703 format %{ "ADD $dst,$src" %} | |
| 7704 opcode(0x81,0x00); /* Opcode 81 /0 id */ | |
| 7705 // ins_encode( RegImm( dst, src) ); | |
| 7706 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 7707 ins_pipe( ialu_reg ); | |
| 7708 %} | |
| 7709 | |
| 7710 instruct addI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ | |
| 7711 match(Set dst (AddI dst (LoadI src))); | |
| 7712 effect(KILL cr); | |
| 7713 | |
| 7714 ins_cost(125); | |
| 7715 format %{ "ADD $dst,$src" %} | |
| 7716 opcode(0x03); | |
| 7717 ins_encode( OpcP, RegMem( dst, src) ); | |
| 7718 ins_pipe( ialu_reg_mem ); | |
| 7719 %} | |
| 7720 | |
| 7721 instruct addI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ | |
| 7722 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7723 effect(KILL cr); | |
| 7724 | |
| 7725 ins_cost(150); | |
| 7726 format %{ "ADD $dst,$src" %} | |
| 7727 opcode(0x01); /* Opcode 01 /r */ | |
| 7728 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 7729 ins_pipe( ialu_mem_reg ); | |
| 7730 %} | |
| 7731 | |
| 7732 // Add Memory with Immediate | |
| 7733 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 7734 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7735 effect(KILL cr); | |
| 7736 | |
| 7737 ins_cost(125); | |
| 7738 format %{ "ADD $dst,$src" %} | |
| 7739 opcode(0x81); /* Opcode 81 /0 id */ | |
| 7740 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) ); | |
| 7741 ins_pipe( ialu_mem_imm ); | |
| 7742 %} | |
| 7743 | |
| 7744 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{ | |
| 7745 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7746 effect(KILL cr); | |
| 7747 | |
| 7748 ins_cost(125); | |
| 7749 format %{ "INC $dst" %} | |
| 7750 opcode(0xFF); /* Opcode FF /0 */ | |
| 7751 ins_encode( OpcP, RMopc_Mem(0x00,dst)); | |
| 7752 ins_pipe( ialu_mem_imm ); | |
| 7753 %} | |
| 7754 | |
| 7755 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{ | |
| 7756 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 7757 effect(KILL cr); | |
| 7758 | |
| 7759 ins_cost(125); | |
| 7760 format %{ "DEC $dst" %} | |
| 7761 opcode(0xFF); /* Opcode FF /1 */ | |
| 7762 ins_encode( OpcP, RMopc_Mem(0x01,dst)); | |
| 7763 ins_pipe( ialu_mem_imm ); | |
| 7764 %} | |
| 7765 | |
| 7766 | |
| 7767 instruct checkCastPP( eRegP dst ) %{ | |
| 7768 match(Set dst (CheckCastPP dst)); | |
| 7769 | |
| 7770 size(0); | |
| 7771 format %{ "#checkcastPP of $dst" %} | |
| 7772 ins_encode( /*empty encoding*/ ); | |
| 7773 ins_pipe( empty ); | |
| 7774 %} | |
| 7775 | |
| 7776 instruct castPP( eRegP dst ) %{ | |
| 7777 match(Set dst (CastPP dst)); | |
| 7778 format %{ "#castPP of $dst" %} | |
| 7779 ins_encode( /*empty encoding*/ ); | |
| 7780 ins_pipe( empty ); | |
| 7781 %} | |
| 7782 | |
| 7783 instruct castII( eRegI dst ) %{ | |
| 7784 match(Set dst (CastII dst)); | |
| 7785 format %{ "#castII of $dst" %} | |
| 7786 ins_encode( /*empty encoding*/ ); | |
| 7787 ins_cost(0); | |
| 7788 ins_pipe( empty ); | |
| 7789 %} | |
| 7790 | |
| 7791 | |
| 7792 // Load-locked - same as a regular pointer load when used with compare-swap | |
| 7793 instruct loadPLocked(eRegP dst, memory mem) %{ | |
| 7794 match(Set dst (LoadPLocked mem)); | |
| 7795 | |
| 7796 ins_cost(125); | |
| 7797 format %{ "MOV $dst,$mem\t# Load ptr. locked" %} | |
| 7798 opcode(0x8B); | |
| 7799 ins_encode( OpcP, RegMem(dst,mem)); | |
| 7800 ins_pipe( ialu_reg_mem ); | |
| 7801 %} | |
| 7802 | |
| 7803 // LoadLong-locked - same as a volatile long load when used with compare-swap | |
| 4759 | 7804 instruct loadLLocked(stackSlotL dst, memory mem) %{ |
| 0 | 7805 predicate(UseSSE<=1); |
| 7806 match(Set dst (LoadLLocked mem)); | |
| 7807 | |
| 7808 ins_cost(200); | |
| 7809 format %{ "FILD $mem\t# Atomic volatile long load\n\t" | |
| 7810 "FISTp $dst" %} | |
| 7811 ins_encode(enc_loadL_volatile(mem,dst)); | |
| 7812 ins_pipe( fpu_reg_mem ); | |
| 7813 %} | |
| 7814 | |
|
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|
7815 instruct loadLX_Locked(stackSlotL dst, memory mem, regD tmp) %{ |
| 0 | 7816 predicate(UseSSE>=2); |
| 7817 match(Set dst (LoadLLocked mem)); | |
| 7818 effect(TEMP tmp); | |
| 7819 ins_cost(180); | |
| 7820 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" | |
| 7821 "MOVSD $dst,$tmp" %} | |
| 4759 | 7822 ins_encode %{ |
| 7823 __ movdbl($tmp$$XMMRegister, $mem$$Address); | |
| 7824 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister); | |
| 7825 %} | |
| 7826 ins_pipe( pipe_slow ); | |
| 7827 %} | |
| 7828 | |
|
4761
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diff
changeset
|
7829 instruct loadLX_reg_Locked(eRegL dst, memory mem, regD tmp) %{ |
| 0 | 7830 predicate(UseSSE>=2); |
| 7831 match(Set dst (LoadLLocked mem)); | |
| 7832 effect(TEMP tmp); | |
| 7833 ins_cost(160); | |
| 7834 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" | |
| 7835 "MOVD $dst.lo,$tmp\n\t" | |
| 7836 "PSRLQ $tmp,32\n\t" | |
| 7837 "MOVD $dst.hi,$tmp" %} | |
| 4759 | 7838 ins_encode %{ |
| 7839 __ movdbl($tmp$$XMMRegister, $mem$$Address); | |
| 7840 __ movdl($dst$$Register, $tmp$$XMMRegister); | |
| 7841 __ psrlq($tmp$$XMMRegister, 32); | |
| 7842 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister); | |
| 7843 %} | |
| 0 | 7844 ins_pipe( pipe_slow ); |
| 7845 %} | |
| 7846 | |
| 7847 // Conditional-store of the updated heap-top. | |
| 7848 // Used during allocation of the shared heap. | |
| 7849 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel. | |
| 7850 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{ | |
| 7851 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval))); | |
| 7852 // EAX is killed if there is contention, but then it's also unused. | |
| 7853 // In the common case of no contention, EAX holds the new oop address. | |
| 7854 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %} | |
| 7855 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) ); | |
| 7856 ins_pipe( pipe_cmpxchg ); | |
| 7857 %} | |
| 7858 | |
|
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|
7859 // Conditional-store of an int value. |
|
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|
7860 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel. |
|
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7861 instruct storeIConditional( memory mem, eAXRegI oldval, eRegI newval, eFlagsReg cr ) %{ |
|
a1980da045cc
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|
7862 match(Set cr (StoreIConditional mem (Binary oldval newval))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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|
7863 effect(KILL oldval); |
|
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6462850: generate biased locking code in C2 ideal graph
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diff
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|
7864 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %} |
|
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|
7865 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) ); |
| 0 | 7866 ins_pipe( pipe_cmpxchg ); |
| 7867 %} | |
| 7868 | |
|
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|
7869 // Conditional-store of a long value. |
|
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|
7870 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel. |
|
a1980da045cc
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|
7871 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ |
|
a1980da045cc
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|
7872 match(Set cr (StoreLConditional mem (Binary oldval newval))); |
|
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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|
7873 effect(KILL oldval); |
|
a1980da045cc
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diff
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|
7874 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t" |
|
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|
7875 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t" |
|
a1980da045cc
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changeset
|
7876 "XCHG EBX,ECX" |
|
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diff
changeset
|
7877 %} |
|
a1980da045cc
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diff
changeset
|
7878 ins_encode %{ |
|
a1980da045cc
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diff
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|
7879 // Note: we need to swap rbx, and rcx before and after the |
|
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|
7880 // cmpxchg8 instruction because the instruction uses |
|
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diff
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|
7881 // rcx as the high order word of the new value to store but |
|
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|
7882 // our register encoding uses rbx. |
|
a1980da045cc
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|
7883 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc)); |
|
a1980da045cc
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changeset
|
7884 if( os::is_MP() ) |
|
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|
7885 __ lock(); |
| 624 | 7886 __ cmpxchg8($mem$$Address); |
|
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|
7887 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc)); |
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a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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|
7888 %} |
| 0 | 7889 ins_pipe( pipe_cmpxchg ); |
| 7890 %} | |
| 7891 | |
| 7892 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them | |
| 7893 | |
| 7894 instruct compareAndSwapL( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ | |
| 7895 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); | |
| 7896 effect(KILL cr, KILL oldval); | |
| 7897 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 7898 "MOV $res,0\n\t" | |
| 7899 "JNE,s fail\n\t" | |
| 7900 "MOV $res,1\n" | |
| 7901 "fail:" %} | |
| 7902 ins_encode( enc_cmpxchg8(mem_ptr), | |
| 7903 enc_flags_ne_to_boolean(res) ); | |
| 7904 ins_pipe( pipe_cmpxchg ); | |
| 7905 %} | |
| 7906 | |
| 7907 instruct compareAndSwapP( eRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{ | |
| 7908 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); | |
| 7909 effect(KILL cr, KILL oldval); | |
| 7910 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 7911 "MOV $res,0\n\t" | |
| 7912 "JNE,s fail\n\t" | |
| 7913 "MOV $res,1\n" | |
| 7914 "fail:" %} | |
| 7915 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) ); | |
| 7916 ins_pipe( pipe_cmpxchg ); | |
| 7917 %} | |
| 7918 | |
| 7919 instruct compareAndSwapI( eRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{ | |
| 7920 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); | |
| 7921 effect(KILL cr, KILL oldval); | |
| 7922 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" | |
| 7923 "MOV $res,0\n\t" | |
| 7924 "JNE,s fail\n\t" | |
| 7925 "MOV $res,1\n" | |
| 7926 "fail:" %} | |
| 7927 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) ); | |
| 7928 ins_pipe( pipe_cmpxchg ); | |
| 7929 %} | |
| 7930 | |
| 7931 //----------Subtraction Instructions------------------------------------------- | |
| 7932 // Integer Subtraction Instructions | |
| 7933 instruct subI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ | |
| 7934 match(Set dst (SubI dst src)); | |
| 7935 effect(KILL cr); | |
| 7936 | |
| 7937 size(2); | |
| 7938 format %{ "SUB $dst,$src" %} | |
| 7939 opcode(0x2B); | |
| 7940 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7941 ins_pipe( ialu_reg_reg ); | |
| 7942 %} | |
| 7943 | |
| 7944 instruct subI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ | |
| 7945 match(Set dst (SubI dst src)); | |
| 7946 effect(KILL cr); | |
| 7947 | |
| 7948 format %{ "SUB $dst,$src" %} | |
| 7949 opcode(0x81,0x05); /* Opcode 81 /5 */ | |
| 7950 // ins_encode( RegImm( dst, src) ); | |
| 7951 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 7952 ins_pipe( ialu_reg ); | |
| 7953 %} | |
| 7954 | |
| 7955 instruct subI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ | |
| 7956 match(Set dst (SubI dst (LoadI src))); | |
| 7957 effect(KILL cr); | |
| 7958 | |
| 7959 ins_cost(125); | |
| 7960 format %{ "SUB $dst,$src" %} | |
| 7961 opcode(0x2B); | |
| 7962 ins_encode( OpcP, RegMem( dst, src) ); | |
| 7963 ins_pipe( ialu_reg_mem ); | |
| 7964 %} | |
| 7965 | |
| 7966 instruct subI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ | |
| 7967 match(Set dst (StoreI dst (SubI (LoadI dst) src))); | |
| 7968 effect(KILL cr); | |
| 7969 | |
| 7970 ins_cost(150); | |
| 7971 format %{ "SUB $dst,$src" %} | |
| 7972 opcode(0x29); /* Opcode 29 /r */ | |
| 7973 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 7974 ins_pipe( ialu_mem_reg ); | |
| 7975 %} | |
| 7976 | |
| 7977 // Subtract from a pointer | |
| 7978 instruct subP_eReg(eRegP dst, eRegI src, immI0 zero, eFlagsReg cr) %{ | |
| 7979 match(Set dst (AddP dst (SubI zero src))); | |
| 7980 effect(KILL cr); | |
| 7981 | |
| 7982 size(2); | |
| 7983 format %{ "SUB $dst,$src" %} | |
| 7984 opcode(0x2B); | |
| 7985 ins_encode( OpcP, RegReg( dst, src) ); | |
| 7986 ins_pipe( ialu_reg_reg ); | |
| 7987 %} | |
| 7988 | |
| 7989 instruct negI_eReg(eRegI dst, immI0 zero, eFlagsReg cr) %{ | |
| 7990 match(Set dst (SubI zero dst)); | |
| 7991 effect(KILL cr); | |
| 7992 | |
| 7993 size(2); | |
| 7994 format %{ "NEG $dst" %} | |
| 7995 opcode(0xF7,0x03); // Opcode F7 /3 | |
| 7996 ins_encode( OpcP, RegOpc( dst ) ); | |
| 7997 ins_pipe( ialu_reg ); | |
| 7998 %} | |
| 7999 | |
| 8000 | |
| 8001 //----------Multiplication/Division Instructions------------------------------- | |
| 8002 // Integer Multiplication Instructions | |
| 8003 // Multiply Register | |
| 8004 instruct mulI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ | |
| 8005 match(Set dst (MulI dst src)); | |
| 8006 effect(KILL cr); | |
| 8007 | |
| 8008 size(3); | |
| 8009 ins_cost(300); | |
| 8010 format %{ "IMUL $dst,$src" %} | |
| 8011 opcode(0xAF, 0x0F); | |
| 8012 ins_encode( OpcS, OpcP, RegReg( dst, src) ); | |
| 8013 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8014 %} | |
| 8015 | |
| 8016 // Multiply 32-bit Immediate | |
| 8017 instruct mulI_eReg_imm(eRegI dst, eRegI src, immI imm, eFlagsReg cr) %{ | |
| 8018 match(Set dst (MulI src imm)); | |
| 8019 effect(KILL cr); | |
| 8020 | |
| 8021 ins_cost(300); | |
| 8022 format %{ "IMUL $dst,$src,$imm" %} | |
| 8023 opcode(0x69); /* 69 /r id */ | |
| 8024 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) ); | |
| 8025 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8026 %} | |
| 8027 | |
| 8028 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{ | |
| 8029 match(Set dst src); | |
| 8030 effect(KILL cr); | |
| 8031 | |
| 8032 // Note that this is artificially increased to make it more expensive than loadConL | |
| 8033 ins_cost(250); | |
| 8034 format %{ "MOV EAX,$src\t// low word only" %} | |
| 8035 opcode(0xB8); | |
| 8036 ins_encode( LdImmL_Lo(dst, src) ); | |
| 8037 ins_pipe( ialu_reg_fat ); | |
| 8038 %} | |
| 8039 | |
| 8040 // Multiply by 32-bit Immediate, taking the shifted high order results | |
| 8041 // (special case for shift by 32) | |
| 8042 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{ | |
| 8043 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt))); | |
| 8044 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL && | |
| 8045 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint && | |
| 8046 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint ); | |
| 8047 effect(USE src1, KILL cr); | |
| 8048 | |
| 8049 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only | |
| 8050 ins_cost(0*100 + 1*400 - 150); | |
| 8051 format %{ "IMUL EDX:EAX,$src1" %} | |
| 8052 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) ); | |
| 8053 ins_pipe( pipe_slow ); | |
| 8054 %} | |
| 8055 | |
| 8056 // Multiply by 32-bit Immediate, taking the shifted high order results | |
| 8057 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 8058 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt))); | |
| 8059 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL && | |
| 8060 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint && | |
| 8061 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint ); | |
| 8062 effect(USE src1, KILL cr); | |
| 8063 | |
| 8064 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only | |
| 8065 ins_cost(1*100 + 1*400 - 150); | |
| 8066 format %{ "IMUL EDX:EAX,$src1\n\t" | |
| 8067 "SAR EDX,$cnt-32" %} | |
| 8068 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) ); | |
| 8069 ins_pipe( pipe_slow ); | |
| 8070 %} | |
| 8071 | |
| 8072 // Multiply Memory 32-bit Immediate | |
| 8073 instruct mulI_mem_imm(eRegI dst, memory src, immI imm, eFlagsReg cr) %{ | |
| 8074 match(Set dst (MulI (LoadI src) imm)); | |
| 8075 effect(KILL cr); | |
| 8076 | |
| 8077 ins_cost(300); | |
| 8078 format %{ "IMUL $dst,$src,$imm" %} | |
| 8079 opcode(0x69); /* 69 /r id */ | |
| 8080 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) ); | |
| 8081 ins_pipe( ialu_reg_mem_alu0 ); | |
| 8082 %} | |
| 8083 | |
| 8084 // Multiply Memory | |
| 8085 instruct mulI(eRegI dst, memory src, eFlagsReg cr) %{ | |
| 8086 match(Set dst (MulI dst (LoadI src))); | |
| 8087 effect(KILL cr); | |
| 8088 | |
| 8089 ins_cost(350); | |
| 8090 format %{ "IMUL $dst,$src" %} | |
| 8091 opcode(0xAF, 0x0F); | |
| 8092 ins_encode( OpcS, OpcP, RegMem( dst, src) ); | |
| 8093 ins_pipe( ialu_reg_mem_alu0 ); | |
| 8094 %} | |
| 8095 | |
| 8096 // Multiply Register Int to Long | |
| 8097 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{ | |
| 8098 // Basic Idea: long = (long)int * (long)int | |
| 8099 match(Set dst (MulL (ConvI2L src) (ConvI2L src1))); | |
| 8100 effect(DEF dst, USE src, USE src1, KILL flags); | |
| 8101 | |
| 8102 ins_cost(300); | |
| 8103 format %{ "IMUL $dst,$src1" %} | |
| 8104 | |
| 8105 ins_encode( long_int_multiply( dst, src1 ) ); | |
| 8106 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8107 %} | |
| 8108 | |
| 8109 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{ | |
| 8110 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL) | |
| 8111 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask))); | |
| 8112 effect(KILL flags); | |
| 8113 | |
| 8114 ins_cost(300); | |
| 8115 format %{ "MUL $dst,$src1" %} | |
| 8116 | |
| 8117 ins_encode( long_uint_multiply(dst, src1) ); | |
| 8118 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8119 %} | |
| 8120 | |
| 8121 // Multiply Register Long | |
| 8122 instruct mulL_eReg(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{ | |
| 8123 match(Set dst (MulL dst src)); | |
| 8124 effect(KILL cr, TEMP tmp); | |
| 8125 ins_cost(4*100+3*400); | |
| 8126 // Basic idea: lo(result) = lo(x_lo * y_lo) | |
| 8127 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) | |
| 8128 format %{ "MOV $tmp,$src.lo\n\t" | |
| 8129 "IMUL $tmp,EDX\n\t" | |
| 8130 "MOV EDX,$src.hi\n\t" | |
| 8131 "IMUL EDX,EAX\n\t" | |
| 8132 "ADD $tmp,EDX\n\t" | |
| 8133 "MUL EDX:EAX,$src.lo\n\t" | |
| 8134 "ADD EDX,$tmp" %} | |
| 8135 ins_encode( long_multiply( dst, src, tmp ) ); | |
| 8136 ins_pipe( pipe_slow ); | |
| 8137 %} | |
| 8138 | |
|
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8139 // Multiply Register Long where the left operand's high 32 bits are zero |
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8140 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{ |
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8141 predicate(is_operand_hi32_zero(n->in(1))); |
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8142 match(Set dst (MulL dst src)); |
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8143 effect(KILL cr, TEMP tmp); |
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8144 ins_cost(2*100+2*400); |
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8145 // Basic idea: lo(result) = lo(x_lo * y_lo) |
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8146 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0 |
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8147 format %{ "MOV $tmp,$src.hi\n\t" |
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8148 "IMUL $tmp,EAX\n\t" |
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8149 "MUL EDX:EAX,$src.lo\n\t" |
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8150 "ADD EDX,$tmp" %} |
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8151 ins_encode %{ |
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8152 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register)); |
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8153 __ imull($tmp$$Register, rax); |
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8154 __ mull($src$$Register); |
|
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8155 __ addl(rdx, $tmp$$Register); |
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8156 %} |
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8157 ins_pipe( pipe_slow ); |
|
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8158 %} |
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8159 |
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8160 // Multiply Register Long where the right operand's high 32 bits are zero |
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8161 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{ |
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8162 predicate(is_operand_hi32_zero(n->in(2))); |
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8163 match(Set dst (MulL dst src)); |
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8164 effect(KILL cr, TEMP tmp); |
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8165 ins_cost(2*100+2*400); |
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8166 // Basic idea: lo(result) = lo(x_lo * y_lo) |
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8167 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0 |
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8168 format %{ "MOV $tmp,$src.lo\n\t" |
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8169 "IMUL $tmp,EDX\n\t" |
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8170 "MUL EDX:EAX,$src.lo\n\t" |
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8171 "ADD EDX,$tmp" %} |
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8172 ins_encode %{ |
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8173 __ movl($tmp$$Register, $src$$Register); |
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8174 __ imull($tmp$$Register, rdx); |
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8175 __ mull($src$$Register); |
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8176 __ addl(rdx, $tmp$$Register); |
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8177 %} |
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8178 ins_pipe( pipe_slow ); |
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8179 %} |
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8180 |
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8181 // Multiply Register Long where the left and the right operands' high 32 bits are zero |
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8182 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{ |
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8183 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2))); |
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8184 match(Set dst (MulL dst src)); |
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8185 effect(KILL cr); |
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8186 ins_cost(1*400); |
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|
8187 // Basic idea: lo(result) = lo(x_lo * y_lo) |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
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|
8188 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0 |
|
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|
8189 format %{ "MUL EDX:EAX,$src.lo\n\t" %} |
|
e8443c7be117
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1137
diff
changeset
|
8190 ins_encode %{ |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
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diff
changeset
|
8191 __ mull($src$$Register); |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
never
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1137
diff
changeset
|
8192 %} |
|
e8443c7be117
6921969: optimize 64 long multiply for case with high bits zero
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1137
diff
changeset
|
8193 ins_pipe( pipe_slow ); |
|
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6921969: optimize 64 long multiply for case with high bits zero
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1137
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changeset
|
8194 %} |
|
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changeset
|
8195 |
| 0 | 8196 // Multiply Register Long by small constant |
| 8197 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, eRegI tmp, eFlagsReg cr) %{ | |
| 8198 match(Set dst (MulL dst src)); | |
| 8199 effect(KILL cr, TEMP tmp); | |
| 8200 ins_cost(2*100+2*400); | |
| 8201 size(12); | |
| 8202 // Basic idea: lo(result) = lo(src * EAX) | |
| 8203 // hi(result) = hi(src * EAX) + lo(src * EDX) | |
| 8204 format %{ "IMUL $tmp,EDX,$src\n\t" | |
| 8205 "MOV EDX,$src\n\t" | |
| 8206 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t" | |
| 8207 "ADD EDX,$tmp" %} | |
| 8208 ins_encode( long_multiply_con( dst, src, tmp ) ); | |
| 8209 ins_pipe( pipe_slow ); | |
| 8210 %} | |
| 8211 | |
| 8212 // Integer DIV with Register | |
| 8213 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ | |
| 8214 match(Set rax (DivI rax div)); | |
| 8215 effect(KILL rdx, KILL cr); | |
| 8216 size(26); | |
| 8217 ins_cost(30*100+10*100); | |
| 8218 format %{ "CMP EAX,0x80000000\n\t" | |
| 8219 "JNE,s normal\n\t" | |
| 8220 "XOR EDX,EDX\n\t" | |
| 8221 "CMP ECX,-1\n\t" | |
| 8222 "JE,s done\n" | |
| 8223 "normal: CDQ\n\t" | |
| 8224 "IDIV $div\n\t" | |
| 8225 "done:" %} | |
| 8226 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8227 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 8228 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8229 %} | |
| 8230 | |
| 8231 // Divide Register Long | |
| 8232 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ | |
| 8233 match(Set dst (DivL src1 src2)); | |
| 8234 effect( KILL cr, KILL cx, KILL bx ); | |
| 8235 ins_cost(10000); | |
| 8236 format %{ "PUSH $src1.hi\n\t" | |
| 8237 "PUSH $src1.lo\n\t" | |
| 8238 "PUSH $src2.hi\n\t" | |
| 8239 "PUSH $src2.lo\n\t" | |
| 8240 "CALL SharedRuntime::ldiv\n\t" | |
| 8241 "ADD ESP,16" %} | |
| 8242 ins_encode( long_div(src1,src2) ); | |
| 8243 ins_pipe( pipe_slow ); | |
| 8244 %} | |
| 8245 | |
| 8246 // Integer DIVMOD with Register, both quotient and mod results | |
| 8247 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ | |
| 8248 match(DivModI rax div); | |
| 8249 effect(KILL cr); | |
| 8250 size(26); | |
| 8251 ins_cost(30*100+10*100); | |
| 8252 format %{ "CMP EAX,0x80000000\n\t" | |
| 8253 "JNE,s normal\n\t" | |
| 8254 "XOR EDX,EDX\n\t" | |
| 8255 "CMP ECX,-1\n\t" | |
| 8256 "JE,s done\n" | |
| 8257 "normal: CDQ\n\t" | |
| 8258 "IDIV $div\n\t" | |
| 8259 "done:" %} | |
| 8260 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8261 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 8262 ins_pipe( pipe_slow ); | |
| 8263 %} | |
| 8264 | |
| 8265 // Integer MOD with Register | |
| 8266 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{ | |
| 8267 match(Set rdx (ModI rax div)); | |
| 8268 effect(KILL rax, KILL cr); | |
| 8269 | |
| 8270 size(26); | |
| 8271 ins_cost(300); | |
| 8272 format %{ "CDQ\n\t" | |
| 8273 "IDIV $div" %} | |
| 8274 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8275 ins_encode( cdq_enc, OpcP, RegOpc(div) ); | |
| 8276 ins_pipe( ialu_reg_reg_alu0 ); | |
| 8277 %} | |
| 8278 | |
| 8279 // Remainder Register Long | |
| 8280 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ | |
| 8281 match(Set dst (ModL src1 src2)); | |
| 8282 effect( KILL cr, KILL cx, KILL bx ); | |
| 8283 ins_cost(10000); | |
| 8284 format %{ "PUSH $src1.hi\n\t" | |
| 8285 "PUSH $src1.lo\n\t" | |
| 8286 "PUSH $src2.hi\n\t" | |
| 8287 "PUSH $src2.lo\n\t" | |
| 8288 "CALL SharedRuntime::lrem\n\t" | |
| 8289 "ADD ESP,16" %} | |
| 8290 ins_encode( long_mod(src1,src2) ); | |
| 8291 ins_pipe( pipe_slow ); | |
| 8292 %} | |
| 8293 | |
|
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|
8294 // Divide Register Long (no special case since divisor != -1) |
|
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
8295 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, eRegI tmp, eRegI tmp2, eFlagsReg cr ) %{ |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8296 match(Set dst (DivL dst imm)); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8297 effect( TEMP tmp, TEMP tmp2, KILL cr ); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8298 ins_cost(1000); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8299 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t" |
| 1920 | 8300 "XOR $tmp2,$tmp2\n\t" |
|
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8301 "CMP $tmp,EDX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8302 "JA,s fast\n\t" |
|
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8303 "MOV $tmp2,EAX\n\t" |
|
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8304 "MOV EAX,EDX\n\t" |
| 1920 | 8305 "MOV EDX,0\n\t" |
| 8306 "JLE,s pos\n\t" | |
| 8307 "LNEG EAX : $tmp2\n\t" | |
| 8308 "DIV $tmp # unsigned division\n\t" | |
| 8309 "XCHG EAX,$tmp2\n\t" | |
| 8310 "DIV $tmp\n\t" | |
| 8311 "LNEG $tmp2 : EAX\n\t" | |
|
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|
8312 "JMP,s done\n" |
| 1920 | 8313 "pos:\n\t" |
| 8314 "DIV $tmp\n\t" | |
| 8315 "XCHG EAX,$tmp2\n" | |
|
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|
8316 "fast:\n\t" |
| 1920 | 8317 "DIV $tmp\n" |
|
1914
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|
8318 "done:\n\t" |
| 1920 | 8319 "MOV EDX,$tmp2\n\t" |
|
1914
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8320 "NEG EDX:EAX # if $imm < 0" %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
8321 ins_encode %{ |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8322 int con = (int)$imm$$constant; |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8323 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor"); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8324 int pcon = (con > 0) ? con : -con; |
| 1920 | 8325 Label Lfast, Lpos, Ldone; |
|
1914
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
8326 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8327 __ movl($tmp$$Register, pcon); |
| 1920 | 8328 __ xorl($tmp2$$Register,$tmp2$$Register); |
|
1914
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8329 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register)); |
| 1920 | 8330 __ jccb(Assembler::above, Lfast); // result fits into 32 bit |
|
1914
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8331 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
8332 __ movl($tmp2$$Register, $dst$$Register); // save |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
8333 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); |
| 1920 | 8334 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags |
| 8335 __ jccb(Assembler::lessEqual, Lpos); // result is positive | |
| 8336 | |
| 8337 // Negative dividend. | |
| 8338 // convert value to positive to use unsigned division | |
| 8339 __ lneg($dst$$Register, $tmp2$$Register); | |
| 8340 __ divl($tmp$$Register); | |
|
1914
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
8341 __ xchgl($dst$$Register, $tmp2$$Register); |
| 1920 | 8342 __ divl($tmp$$Register); |
| 8343 // revert result back to negative | |
| 8344 __ lneg($tmp2$$Register, $dst$$Register); | |
|
1914
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
8345 __ jmpb(Ldone); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
8346 |
| 1920 | 8347 __ bind(Lpos); |
| 8348 __ divl($tmp$$Register); // Use unsigned division | |
| 8349 __ xchgl($dst$$Register, $tmp2$$Register); | |
| 8350 // Fallthrow for final divide, tmp2 has 32 bit hi result | |
| 8351 | |
|
1914
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kvn
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|
8352 __ bind(Lfast); |
| 1920 | 8353 // fast path: src is positive |
| 8354 __ divl($tmp$$Register); // Use unsigned division | |
|
1914
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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changeset
|
8355 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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changeset
|
8356 __ bind(Ldone); |
| 1920 | 8357 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register); |
|
1914
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6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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changeset
|
8358 if (con < 0) { |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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1748
diff
changeset
|
8359 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
8360 } |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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diff
changeset
|
8361 %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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diff
changeset
|
8362 ins_pipe( pipe_slow ); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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changeset
|
8363 %} |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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diff
changeset
|
8364 |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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changeset
|
8365 // Remainder Register Long (remainder fit into 32 bits) |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
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|
8366 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, eRegI tmp, eRegI tmp2, eFlagsReg cr ) %{ |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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changeset
|
8367 match(Set dst (ModL dst imm)); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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changeset
|
8368 effect( TEMP tmp, TEMP tmp2, KILL cr ); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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changeset
|
8369 ins_cost(1000); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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changeset
|
8370 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t" |
|
ae065c367d93
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|
8371 "CMP $tmp,EDX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8372 "JA,s fast\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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changeset
|
8373 "MOV $tmp2,EAX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8374 "MOV EAX,EDX\n\t" |
| 1920 | 8375 "MOV EDX,0\n\t" |
| 8376 "JLE,s pos\n\t" | |
| 8377 "LNEG EAX : $tmp2\n\t" | |
| 8378 "DIV $tmp # unsigned division\n\t" | |
| 8379 "MOV EAX,$tmp2\n\t" | |
| 8380 "DIV $tmp\n\t" | |
| 8381 "NEG EDX\n\t" | |
| 8382 "JMP,s done\n" | |
| 8383 "pos:\n\t" | |
| 8384 "DIV $tmp\n\t" | |
|
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|
8385 "MOV EAX,$tmp2\n" |
|
ae065c367d93
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|
8386 "fast:\n\t" |
| 1920 | 8387 "DIV $tmp\n" |
| 8388 "done:\n\t" | |
|
1914
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|
8389 "MOV EAX,EDX\n\t" |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8390 "SAR EDX,31\n\t" %} |
|
ae065c367d93
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|
8391 ins_encode %{ |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8392 int con = (int)$imm$$constant; |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8393 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor"); |
|
ae065c367d93
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|
8394 int pcon = (con > 0) ? con : -con; |
| 1920 | 8395 Label Lfast, Lpos, Ldone; |
|
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|
8396 |
|
ae065c367d93
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changeset
|
8397 __ movl($tmp$$Register, pcon); |
|
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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|
8398 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register)); |
|
ae065c367d93
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|
8399 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit |
|
ae065c367d93
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|
8400 |
|
ae065c367d93
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|
8401 __ movl($tmp2$$Register, $dst$$Register); // save |
|
ae065c367d93
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|
8402 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); |
| 1920 | 8403 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags |
| 8404 __ jccb(Assembler::lessEqual, Lpos); // result is positive | |
| 8405 | |
| 8406 // Negative dividend. | |
| 8407 // convert value to positive to use unsigned division | |
| 8408 __ lneg($dst$$Register, $tmp2$$Register); | |
| 8409 __ divl($tmp$$Register); | |
| 8410 __ movl($dst$$Register, $tmp2$$Register); | |
| 8411 __ divl($tmp$$Register); | |
| 8412 // revert remainder back to negative | |
| 8413 __ negl(HIGH_FROM_LOW($dst$$Register)); | |
| 8414 __ jmpb(Ldone); | |
| 8415 | |
| 8416 __ bind(Lpos); | |
| 8417 __ divl($tmp$$Register); | |
|
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|
8418 __ movl($dst$$Register, $tmp2$$Register); |
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8419 |
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|
8420 __ bind(Lfast); |
| 1920 | 8421 // fast path: src is positive |
| 8422 __ divl($tmp$$Register); | |
| 8423 | |
| 8424 __ bind(Ldone); | |
|
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8425 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); |
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8426 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign |
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|
8427 |
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|
8428 %} |
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|
8429 ins_pipe( pipe_slow ); |
|
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8430 %} |
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|
8431 |
| 0 | 8432 // Integer Shift Instructions |
| 8433 // Shift Left by one | |
| 8434 instruct shlI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{ | |
| 8435 match(Set dst (LShiftI dst shift)); | |
| 8436 effect(KILL cr); | |
| 8437 | |
| 8438 size(2); | |
| 8439 format %{ "SHL $dst,$shift" %} | |
| 8440 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 8441 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8442 ins_pipe( ialu_reg ); | |
| 8443 %} | |
| 8444 | |
| 8445 // Shift Left by 8-bit immediate | |
| 8446 instruct salI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{ | |
| 8447 match(Set dst (LShiftI dst shift)); | |
| 8448 effect(KILL cr); | |
| 8449 | |
| 8450 size(3); | |
| 8451 format %{ "SHL $dst,$shift" %} | |
| 8452 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 8453 ins_encode( RegOpcImm( dst, shift) ); | |
| 8454 ins_pipe( ialu_reg ); | |
| 8455 %} | |
| 8456 | |
| 8457 // Shift Left by variable | |
| 8458 instruct salI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 8459 match(Set dst (LShiftI dst shift)); | |
| 8460 effect(KILL cr); | |
| 8461 | |
| 8462 size(2); | |
| 8463 format %{ "SHL $dst,$shift" %} | |
| 8464 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 8465 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8466 ins_pipe( ialu_reg_reg ); | |
| 8467 %} | |
| 8468 | |
| 8469 // Arithmetic shift right by one | |
| 8470 instruct sarI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{ | |
| 8471 match(Set dst (RShiftI dst shift)); | |
| 8472 effect(KILL cr); | |
| 8473 | |
| 8474 size(2); | |
| 8475 format %{ "SAR $dst,$shift" %} | |
| 8476 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8477 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8478 ins_pipe( ialu_reg ); | |
| 8479 %} | |
| 8480 | |
| 8481 // Arithmetic shift right by one | |
| 8482 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{ | |
| 8483 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 8484 effect(KILL cr); | |
| 8485 format %{ "SAR $dst,$shift" %} | |
| 8486 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 8487 ins_encode( OpcP, RMopc_Mem(secondary,dst) ); | |
| 8488 ins_pipe( ialu_mem_imm ); | |
| 8489 %} | |
| 8490 | |
| 8491 // Arithmetic Shift Right by 8-bit immediate | |
| 8492 instruct sarI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{ | |
| 8493 match(Set dst (RShiftI dst shift)); | |
| 8494 effect(KILL cr); | |
| 8495 | |
| 8496 size(3); | |
| 8497 format %{ "SAR $dst,$shift" %} | |
| 8498 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8499 ins_encode( RegOpcImm( dst, shift ) ); | |
| 8500 ins_pipe( ialu_mem_imm ); | |
| 8501 %} | |
| 8502 | |
| 8503 // Arithmetic Shift Right by 8-bit immediate | |
| 8504 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{ | |
| 8505 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 8506 effect(KILL cr); | |
| 8507 | |
| 8508 format %{ "SAR $dst,$shift" %} | |
| 8509 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8510 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) ); | |
| 8511 ins_pipe( ialu_mem_imm ); | |
| 8512 %} | |
| 8513 | |
| 8514 // Arithmetic Shift Right by variable | |
| 8515 instruct sarI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 8516 match(Set dst (RShiftI dst shift)); | |
| 8517 effect(KILL cr); | |
| 8518 | |
| 8519 size(2); | |
| 8520 format %{ "SAR $dst,$shift" %} | |
| 8521 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 8522 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8523 ins_pipe( ialu_reg_reg ); | |
| 8524 %} | |
| 8525 | |
| 8526 // Logical shift right by one | |
| 8527 instruct shrI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{ | |
| 8528 match(Set dst (URShiftI dst shift)); | |
| 8529 effect(KILL cr); | |
| 8530 | |
| 8531 size(2); | |
| 8532 format %{ "SHR $dst,$shift" %} | |
| 8533 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 8534 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8535 ins_pipe( ialu_reg ); | |
| 8536 %} | |
| 8537 | |
| 8538 // Logical Shift Right by 8-bit immediate | |
| 8539 instruct shrI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{ | |
| 8540 match(Set dst (URShiftI dst shift)); | |
| 8541 effect(KILL cr); | |
| 8542 | |
| 8543 size(3); | |
| 8544 format %{ "SHR $dst,$shift" %} | |
| 8545 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 8546 ins_encode( RegOpcImm( dst, shift) ); | |
| 8547 ins_pipe( ialu_reg ); | |
| 8548 %} | |
| 8549 | |
|
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8550 |
| 0 | 8551 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24. |
| 8552 // This idiom is used by the compiler for the i2b bytecode. | |
| 785 | 8553 instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour) %{ |
| 0 | 8554 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour)); |
| 8555 | |
| 8556 size(3); | |
| 8557 format %{ "MOVSX $dst,$src :8" %} | |
| 785 | 8558 ins_encode %{ |
| 8559 __ movsbl($dst$$Register, $src$$Register); | |
| 8560 %} | |
| 8561 ins_pipe(ialu_reg_reg); | |
| 0 | 8562 %} |
| 8563 | |
| 8564 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16. | |
| 8565 // This idiom is used by the compiler the i2s bytecode. | |
| 785 | 8566 instruct i2s(eRegI dst, xRegI src, immI_16 sixteen) %{ |
| 0 | 8567 match(Set dst (RShiftI (LShiftI src sixteen) sixteen)); |
| 8568 | |
| 8569 size(3); | |
| 8570 format %{ "MOVSX $dst,$src :16" %} | |
| 785 | 8571 ins_encode %{ |
| 8572 __ movswl($dst$$Register, $src$$Register); | |
| 8573 %} | |
| 8574 ins_pipe(ialu_reg_reg); | |
| 0 | 8575 %} |
| 8576 | |
| 8577 | |
| 8578 // Logical Shift Right by variable | |
| 8579 instruct shrI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 8580 match(Set dst (URShiftI dst shift)); | |
| 8581 effect(KILL cr); | |
| 8582 | |
| 8583 size(2); | |
| 8584 format %{ "SHR $dst,$shift" %} | |
| 8585 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 8586 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8587 ins_pipe( ialu_reg_reg ); | |
| 8588 %} | |
| 8589 | |
| 8590 | |
| 8591 //----------Logical Instructions----------------------------------------------- | |
| 8592 //----------Integer Logical Instructions--------------------------------------- | |
| 8593 // And Instructions | |
| 8594 // And Register with Register | |
| 8595 instruct andI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ | |
| 8596 match(Set dst (AndI dst src)); | |
| 8597 effect(KILL cr); | |
| 8598 | |
| 8599 size(2); | |
| 8600 format %{ "AND $dst,$src" %} | |
| 8601 opcode(0x23); | |
| 8602 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8603 ins_pipe( ialu_reg_reg ); | |
| 8604 %} | |
| 8605 | |
| 8606 // And Register with Immediate | |
| 8607 instruct andI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ | |
| 8608 match(Set dst (AndI dst src)); | |
| 8609 effect(KILL cr); | |
| 8610 | |
| 8611 format %{ "AND $dst,$src" %} | |
| 8612 opcode(0x81,0x04); /* Opcode 81 /4 */ | |
| 8613 // ins_encode( RegImm( dst, src) ); | |
| 8614 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8615 ins_pipe( ialu_reg ); | |
| 8616 %} | |
| 8617 | |
| 8618 // And Register with Memory | |
| 8619 instruct andI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ | |
| 8620 match(Set dst (AndI dst (LoadI src))); | |
| 8621 effect(KILL cr); | |
| 8622 | |
| 8623 ins_cost(125); | |
| 8624 format %{ "AND $dst,$src" %} | |
| 8625 opcode(0x23); | |
| 8626 ins_encode( OpcP, RegMem( dst, src) ); | |
| 8627 ins_pipe( ialu_reg_mem ); | |
| 8628 %} | |
| 8629 | |
| 8630 // And Memory with Register | |
| 8631 instruct andI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ | |
| 8632 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 8633 effect(KILL cr); | |
| 8634 | |
| 8635 ins_cost(150); | |
| 8636 format %{ "AND $dst,$src" %} | |
| 8637 opcode(0x21); /* Opcode 21 /r */ | |
| 8638 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 8639 ins_pipe( ialu_mem_reg ); | |
| 8640 %} | |
| 8641 | |
| 8642 // And Memory with Immediate | |
| 8643 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 8644 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 8645 effect(KILL cr); | |
| 8646 | |
| 8647 ins_cost(125); | |
| 8648 format %{ "AND $dst,$src" %} | |
| 8649 opcode(0x81, 0x4); /* Opcode 81 /4 id */ | |
| 8650 // ins_encode( MemImm( dst, src) ); | |
| 8651 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 8652 ins_pipe( ialu_mem_imm ); | |
| 8653 %} | |
| 8654 | |
| 8655 // Or Instructions | |
| 8656 // Or Register with Register | |
| 8657 instruct orI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ | |
| 8658 match(Set dst (OrI dst src)); | |
| 8659 effect(KILL cr); | |
| 8660 | |
| 8661 size(2); | |
| 8662 format %{ "OR $dst,$src" %} | |
| 8663 opcode(0x0B); | |
| 8664 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8665 ins_pipe( ialu_reg_reg ); | |
| 8666 %} | |
| 8667 | |
|
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8668 instruct orI_eReg_castP2X(eRegI dst, eRegP src, eFlagsReg cr) %{ |
|
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8669 match(Set dst (OrI dst (CastP2X src))); |
|
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|
8670 effect(KILL cr); |
|
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|
8671 |
|
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|
8672 size(2); |
|
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|
8673 format %{ "OR $dst,$src" %} |
|
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|
8674 opcode(0x0B); |
|
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|
8675 ins_encode( OpcP, RegReg( dst, src) ); |
|
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|
8676 ins_pipe( ialu_reg_reg ); |
|
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|
8677 %} |
|
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|
8678 |
|
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|
8679 |
| 0 | 8680 // Or Register with Immediate |
| 8681 instruct orI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ | |
| 8682 match(Set dst (OrI dst src)); | |
| 8683 effect(KILL cr); | |
| 8684 | |
| 8685 format %{ "OR $dst,$src" %} | |
| 8686 opcode(0x81,0x01); /* Opcode 81 /1 id */ | |
| 8687 // ins_encode( RegImm( dst, src) ); | |
| 8688 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8689 ins_pipe( ialu_reg ); | |
| 8690 %} | |
| 8691 | |
| 8692 // Or Register with Memory | |
| 8693 instruct orI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ | |
| 8694 match(Set dst (OrI dst (LoadI src))); | |
| 8695 effect(KILL cr); | |
| 8696 | |
| 8697 ins_cost(125); | |
| 8698 format %{ "OR $dst,$src" %} | |
| 8699 opcode(0x0B); | |
| 8700 ins_encode( OpcP, RegMem( dst, src) ); | |
| 8701 ins_pipe( ialu_reg_mem ); | |
| 8702 %} | |
| 8703 | |
| 8704 // Or Memory with Register | |
| 8705 instruct orI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ | |
| 8706 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 8707 effect(KILL cr); | |
| 8708 | |
| 8709 ins_cost(150); | |
| 8710 format %{ "OR $dst,$src" %} | |
| 8711 opcode(0x09); /* Opcode 09 /r */ | |
| 8712 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 8713 ins_pipe( ialu_mem_reg ); | |
| 8714 %} | |
| 8715 | |
| 8716 // Or Memory with Immediate | |
| 8717 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 8718 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 8719 effect(KILL cr); | |
| 8720 | |
| 8721 ins_cost(125); | |
| 8722 format %{ "OR $dst,$src" %} | |
| 8723 opcode(0x81,0x1); /* Opcode 81 /1 id */ | |
| 8724 // ins_encode( MemImm( dst, src) ); | |
| 8725 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 8726 ins_pipe( ialu_mem_imm ); | |
| 8727 %} | |
| 8728 | |
| 8729 // ROL/ROR | |
| 8730 // ROL expand | |
| 8731 instruct rolI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{ | |
| 8732 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8733 | |
| 8734 format %{ "ROL $dst, $shift" %} | |
| 8735 opcode(0xD1, 0x0); /* Opcode D1 /0 */ | |
| 8736 ins_encode( OpcP, RegOpc( dst )); | |
| 8737 ins_pipe( ialu_reg ); | |
| 8738 %} | |
| 8739 | |
| 8740 instruct rolI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{ | |
| 8741 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8742 | |
| 8743 format %{ "ROL $dst, $shift" %} | |
| 8744 opcode(0xC1, 0x0); /*Opcode /C1 /0 */ | |
| 8745 ins_encode( RegOpcImm(dst, shift) ); | |
| 8746 ins_pipe(ialu_reg); | |
| 8747 %} | |
| 8748 | |
| 8749 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 8750 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8751 | |
| 8752 format %{ "ROL $dst, $shift" %} | |
| 8753 opcode(0xD3, 0x0); /* Opcode D3 /0 */ | |
| 8754 ins_encode(OpcP, RegOpc(dst)); | |
| 8755 ins_pipe( ialu_reg_reg ); | |
| 8756 %} | |
| 8757 // end of ROL expand | |
| 8758 | |
| 8759 // ROL 32bit by one once | |
| 8760 instruct rolI_eReg_i1(eRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{ | |
| 8761 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 8762 | |
| 8763 expand %{ | |
| 8764 rolI_eReg_imm1(dst, lshift, cr); | |
| 8765 %} | |
| 8766 %} | |
| 8767 | |
| 8768 // ROL 32bit var by imm8 once | |
| 8769 instruct rolI_eReg_i8(eRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{ | |
| 8770 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); | |
| 8771 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 8772 | |
| 8773 expand %{ | |
| 8774 rolI_eReg_imm8(dst, lshift, cr); | |
| 8775 %} | |
| 8776 %} | |
| 8777 | |
| 8778 // ROL 32bit var by var once | |
| 8779 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{ | |
| 8780 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift)))); | |
| 8781 | |
| 8782 expand %{ | |
| 8783 rolI_eReg_CL(dst, shift, cr); | |
| 8784 %} | |
| 8785 %} | |
| 8786 | |
| 8787 // ROL 32bit var by var once | |
| 8788 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{ | |
| 8789 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift)))); | |
| 8790 | |
| 8791 expand %{ | |
| 8792 rolI_eReg_CL(dst, shift, cr); | |
| 8793 %} | |
| 8794 %} | |
| 8795 | |
| 8796 // ROR expand | |
| 8797 instruct rorI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{ | |
| 8798 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8799 | |
| 8800 format %{ "ROR $dst, $shift" %} | |
| 8801 opcode(0xD1,0x1); /* Opcode D1 /1 */ | |
| 8802 ins_encode( OpcP, RegOpc( dst ) ); | |
| 8803 ins_pipe( ialu_reg ); | |
| 8804 %} | |
| 8805 | |
| 8806 instruct rorI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{ | |
| 8807 effect (USE_DEF dst, USE shift, KILL cr); | |
| 8808 | |
| 8809 format %{ "ROR $dst, $shift" %} | |
| 8810 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */ | |
| 8811 ins_encode( RegOpcImm(dst, shift) ); | |
| 8812 ins_pipe( ialu_reg ); | |
| 8813 %} | |
| 8814 | |
| 8815 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{ | |
| 8816 effect(USE_DEF dst, USE shift, KILL cr); | |
| 8817 | |
| 8818 format %{ "ROR $dst, $shift" %} | |
| 8819 opcode(0xD3, 0x1); /* Opcode D3 /1 */ | |
| 8820 ins_encode(OpcP, RegOpc(dst)); | |
| 8821 ins_pipe( ialu_reg_reg ); | |
| 8822 %} | |
| 8823 // end of ROR expand | |
| 8824 | |
| 8825 // ROR right once | |
| 8826 instruct rorI_eReg_i1(eRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{ | |
| 8827 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 8828 | |
| 8829 expand %{ | |
| 8830 rorI_eReg_imm1(dst, rshift, cr); | |
| 8831 %} | |
| 8832 %} | |
| 8833 | |
| 8834 // ROR 32bit by immI8 once | |
| 8835 instruct rorI_eReg_i8(eRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{ | |
| 8836 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); | |
| 8837 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 8838 | |
| 8839 expand %{ | |
| 8840 rorI_eReg_imm8(dst, rshift, cr); | |
| 8841 %} | |
| 8842 %} | |
| 8843 | |
| 8844 // ROR 32bit var by var once | |
| 8845 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{ | |
| 8846 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift)))); | |
| 8847 | |
| 8848 expand %{ | |
| 8849 rorI_eReg_CL(dst, shift, cr); | |
| 8850 %} | |
| 8851 %} | |
| 8852 | |
| 8853 // ROR 32bit var by var once | |
| 8854 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{ | |
| 8855 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift)))); | |
| 8856 | |
| 8857 expand %{ | |
| 8858 rorI_eReg_CL(dst, shift, cr); | |
| 8859 %} | |
| 8860 %} | |
| 8861 | |
| 8862 // Xor Instructions | |
| 8863 // Xor Register with Register | |
| 8864 instruct xorI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ | |
| 8865 match(Set dst (XorI dst src)); | |
| 8866 effect(KILL cr); | |
| 8867 | |
| 8868 size(2); | |
| 8869 format %{ "XOR $dst,$src" %} | |
| 8870 opcode(0x33); | |
| 8871 ins_encode( OpcP, RegReg( dst, src) ); | |
| 8872 ins_pipe( ialu_reg_reg ); | |
| 8873 %} | |
| 8874 | |
| 403 | 8875 // Xor Register with Immediate -1 |
| 8876 instruct xorI_eReg_im1(eRegI dst, immI_M1 imm) %{ | |
| 8877 match(Set dst (XorI dst imm)); | |
| 8878 | |
| 8879 size(2); | |
| 8880 format %{ "NOT $dst" %} | |
| 8881 ins_encode %{ | |
| 8882 __ notl($dst$$Register); | |
| 8883 %} | |
| 8884 ins_pipe( ialu_reg ); | |
| 8885 %} | |
| 8886 | |
| 0 | 8887 // Xor Register with Immediate |
| 8888 instruct xorI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ | |
| 8889 match(Set dst (XorI dst src)); | |
| 8890 effect(KILL cr); | |
| 8891 | |
| 8892 format %{ "XOR $dst,$src" %} | |
| 8893 opcode(0x81,0x06); /* Opcode 81 /6 id */ | |
| 8894 // ins_encode( RegImm( dst, src) ); | |
| 8895 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); | |
| 8896 ins_pipe( ialu_reg ); | |
| 8897 %} | |
| 8898 | |
| 8899 // Xor Register with Memory | |
| 8900 instruct xorI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ | |
| 8901 match(Set dst (XorI dst (LoadI src))); | |
| 8902 effect(KILL cr); | |
| 8903 | |
| 8904 ins_cost(125); | |
| 8905 format %{ "XOR $dst,$src" %} | |
| 8906 opcode(0x33); | |
| 8907 ins_encode( OpcP, RegMem(dst, src) ); | |
| 8908 ins_pipe( ialu_reg_mem ); | |
| 8909 %} | |
| 8910 | |
| 8911 // Xor Memory with Register | |
| 8912 instruct xorI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ | |
| 8913 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 8914 effect(KILL cr); | |
| 8915 | |
| 8916 ins_cost(150); | |
| 8917 format %{ "XOR $dst,$src" %} | |
| 8918 opcode(0x31); /* Opcode 31 /r */ | |
| 8919 ins_encode( OpcP, RegMem( src, dst ) ); | |
| 8920 ins_pipe( ialu_mem_reg ); | |
| 8921 %} | |
| 8922 | |
| 8923 // Xor Memory with Immediate | |
| 8924 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ | |
| 8925 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 8926 effect(KILL cr); | |
| 8927 | |
| 8928 ins_cost(125); | |
| 8929 format %{ "XOR $dst,$src" %} | |
| 8930 opcode(0x81,0x6); /* Opcode 81 /6 id */ | |
| 8931 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); | |
| 8932 ins_pipe( ialu_mem_imm ); | |
| 8933 %} | |
| 8934 | |
| 8935 //----------Convert Int to Boolean--------------------------------------------- | |
| 8936 | |
| 8937 instruct movI_nocopy(eRegI dst, eRegI src) %{ | |
| 8938 effect( DEF dst, USE src ); | |
| 8939 format %{ "MOV $dst,$src" %} | |
| 8940 ins_encode( enc_Copy( dst, src) ); | |
| 8941 ins_pipe( ialu_reg_reg ); | |
| 8942 %} | |
| 8943 | |
| 8944 instruct ci2b( eRegI dst, eRegI src, eFlagsReg cr ) %{ | |
| 8945 effect( USE_DEF dst, USE src, KILL cr ); | |
| 8946 | |
| 8947 size(4); | |
| 8948 format %{ "NEG $dst\n\t" | |
| 8949 "ADC $dst,$src" %} | |
| 8950 ins_encode( neg_reg(dst), | |
| 8951 OpcRegReg(0x13,dst,src) ); | |
| 8952 ins_pipe( ialu_reg_reg_long ); | |
| 8953 %} | |
| 8954 | |
| 8955 instruct convI2B( eRegI dst, eRegI src, eFlagsReg cr ) %{ | |
| 8956 match(Set dst (Conv2B src)); | |
| 8957 | |
| 8958 expand %{ | |
| 8959 movI_nocopy(dst,src); | |
| 8960 ci2b(dst,src,cr); | |
| 8961 %} | |
| 8962 %} | |
| 8963 | |
| 8964 instruct movP_nocopy(eRegI dst, eRegP src) %{ | |
| 8965 effect( DEF dst, USE src ); | |
| 8966 format %{ "MOV $dst,$src" %} | |
| 8967 ins_encode( enc_Copy( dst, src) ); | |
| 8968 ins_pipe( ialu_reg_reg ); | |
| 8969 %} | |
| 8970 | |
| 8971 instruct cp2b( eRegI dst, eRegP src, eFlagsReg cr ) %{ | |
| 8972 effect( USE_DEF dst, USE src, KILL cr ); | |
| 8973 format %{ "NEG $dst\n\t" | |
| 8974 "ADC $dst,$src" %} | |
| 8975 ins_encode( neg_reg(dst), | |
| 8976 OpcRegReg(0x13,dst,src) ); | |
| 8977 ins_pipe( ialu_reg_reg_long ); | |
| 8978 %} | |
| 8979 | |
| 8980 instruct convP2B( eRegI dst, eRegP src, eFlagsReg cr ) %{ | |
| 8981 match(Set dst (Conv2B src)); | |
| 8982 | |
| 8983 expand %{ | |
| 8984 movP_nocopy(dst,src); | |
| 8985 cp2b(dst,src,cr); | |
| 8986 %} | |
| 8987 %} | |
| 8988 | |
| 8989 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{ | |
| 8990 match(Set dst (CmpLTMask p q)); | |
| 8991 effect( KILL cr ); | |
| 8992 ins_cost(400); | |
| 8993 | |
| 8994 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination | |
| 8995 format %{ "XOR $dst,$dst\n\t" | |
| 8996 "CMP $p,$q\n\t" | |
| 8997 "SETlt $dst\n\t" | |
| 8998 "NEG $dst" %} | |
| 8999 ins_encode( OpcRegReg(0x33,dst,dst), | |
| 9000 OpcRegReg(0x3B,p,q), | |
| 9001 setLT_reg(dst), neg_reg(dst) ); | |
| 9002 ins_pipe( pipe_slow ); | |
| 9003 %} | |
| 9004 | |
| 9005 instruct cmpLTMask0( eRegI dst, immI0 zero, eFlagsReg cr ) %{ | |
| 9006 match(Set dst (CmpLTMask dst zero)); | |
| 9007 effect( DEF dst, KILL cr ); | |
| 9008 ins_cost(100); | |
| 9009 | |
| 9010 format %{ "SAR $dst,31" %} | |
| 9011 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 9012 ins_encode( RegOpcImm( dst, 0x1F ) ); | |
| 9013 ins_pipe( ialu_reg ); | |
| 9014 %} | |
| 9015 | |
| 9016 | |
| 9017 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{ | |
| 9018 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
| 9019 effect( KILL tmp, KILL cr ); | |
| 9020 ins_cost(400); | |
| 9021 // annoyingly, $tmp has no edges so you cant ask for it in | |
| 9022 // any format or encoding | |
| 9023 format %{ "SUB $p,$q\n\t" | |
| 9024 "SBB ECX,ECX\n\t" | |
| 9025 "AND ECX,$y\n\t" | |
| 9026 "ADD $p,ECX" %} | |
| 9027 ins_encode( enc_cmpLTP(p,q,y,tmp) ); | |
| 9028 ins_pipe( pipe_cmplt ); | |
| 9029 %} | |
| 9030 | |
| 9031 /* If I enable this, I encourage spilling in the inner loop of compress. | |
| 9032 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{ | |
| 9033 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q))); | |
| 9034 effect( USE_KILL tmp, KILL cr ); | |
| 9035 ins_cost(400); | |
| 9036 | |
| 9037 format %{ "SUB $p,$q\n\t" | |
| 9038 "SBB ECX,ECX\n\t" | |
| 9039 "AND ECX,$y\n\t" | |
| 9040 "ADD $p,ECX" %} | |
| 9041 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) ); | |
| 9042 %} | |
| 9043 */ | |
| 9044 | |
| 9045 //----------Long Instructions------------------------------------------------ | |
| 9046 // Add Long Register with Register | |
| 9047 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9048 match(Set dst (AddL dst src)); | |
| 9049 effect(KILL cr); | |
| 9050 ins_cost(200); | |
| 9051 format %{ "ADD $dst.lo,$src.lo\n\t" | |
| 9052 "ADC $dst.hi,$src.hi" %} | |
| 9053 opcode(0x03, 0x13); | |
| 9054 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) ); | |
| 9055 ins_pipe( ialu_reg_reg_long ); | |
| 9056 %} | |
| 9057 | |
| 9058 // Add Long Register with Immediate | |
| 9059 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9060 match(Set dst (AddL dst src)); | |
| 9061 effect(KILL cr); | |
| 9062 format %{ "ADD $dst.lo,$src.lo\n\t" | |
| 9063 "ADC $dst.hi,$src.hi" %} | |
| 9064 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */ | |
| 9065 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9066 ins_pipe( ialu_reg_long ); | |
| 9067 %} | |
| 9068 | |
| 9069 // Add Long Register with Memory | |
| 9070 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9071 match(Set dst (AddL dst (LoadL mem))); | |
| 9072 effect(KILL cr); | |
| 9073 ins_cost(125); | |
| 9074 format %{ "ADD $dst.lo,$mem\n\t" | |
| 9075 "ADC $dst.hi,$mem+4" %} | |
| 9076 opcode(0x03, 0x13); | |
| 9077 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9078 ins_pipe( ialu_reg_long_mem ); | |
| 9079 %} | |
| 9080 | |
| 9081 // Subtract Long Register with Register. | |
| 9082 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9083 match(Set dst (SubL dst src)); | |
| 9084 effect(KILL cr); | |
| 9085 ins_cost(200); | |
| 9086 format %{ "SUB $dst.lo,$src.lo\n\t" | |
| 9087 "SBB $dst.hi,$src.hi" %} | |
| 9088 opcode(0x2B, 0x1B); | |
| 9089 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) ); | |
| 9090 ins_pipe( ialu_reg_reg_long ); | |
| 9091 %} | |
| 9092 | |
| 9093 // Subtract Long Register with Immediate | |
| 9094 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9095 match(Set dst (SubL dst src)); | |
| 9096 effect(KILL cr); | |
| 9097 format %{ "SUB $dst.lo,$src.lo\n\t" | |
| 9098 "SBB $dst.hi,$src.hi" %} | |
| 9099 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */ | |
| 9100 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9101 ins_pipe( ialu_reg_long ); | |
| 9102 %} | |
| 9103 | |
| 9104 // Subtract Long Register with Memory | |
| 9105 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9106 match(Set dst (SubL dst (LoadL mem))); | |
| 9107 effect(KILL cr); | |
| 9108 ins_cost(125); | |
| 9109 format %{ "SUB $dst.lo,$mem\n\t" | |
| 9110 "SBB $dst.hi,$mem+4" %} | |
| 9111 opcode(0x2B, 0x1B); | |
| 9112 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9113 ins_pipe( ialu_reg_long_mem ); | |
| 9114 %} | |
| 9115 | |
| 9116 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{ | |
| 9117 match(Set dst (SubL zero dst)); | |
| 9118 effect(KILL cr); | |
| 9119 ins_cost(300); | |
| 9120 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %} | |
| 9121 ins_encode( neg_long(dst) ); | |
| 9122 ins_pipe( ialu_reg_reg_long ); | |
| 9123 %} | |
| 9124 | |
| 9125 // And Long Register with Register | |
| 9126 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9127 match(Set dst (AndL dst src)); | |
| 9128 effect(KILL cr); | |
| 9129 format %{ "AND $dst.lo,$src.lo\n\t" | |
| 9130 "AND $dst.hi,$src.hi" %} | |
| 9131 opcode(0x23,0x23); | |
| 9132 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 9133 ins_pipe( ialu_reg_reg_long ); | |
| 9134 %} | |
| 9135 | |
| 9136 // And Long Register with Immediate | |
| 9137 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9138 match(Set dst (AndL dst src)); | |
| 9139 effect(KILL cr); | |
| 9140 format %{ "AND $dst.lo,$src.lo\n\t" | |
| 9141 "AND $dst.hi,$src.hi" %} | |
| 9142 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */ | |
| 9143 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9144 ins_pipe( ialu_reg_long ); | |
| 9145 %} | |
| 9146 | |
| 9147 // And Long Register with Memory | |
| 9148 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9149 match(Set dst (AndL dst (LoadL mem))); | |
| 9150 effect(KILL cr); | |
| 9151 ins_cost(125); | |
| 9152 format %{ "AND $dst.lo,$mem\n\t" | |
| 9153 "AND $dst.hi,$mem+4" %} | |
| 9154 opcode(0x23, 0x23); | |
| 9155 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9156 ins_pipe( ialu_reg_long_mem ); | |
| 9157 %} | |
| 9158 | |
| 9159 // Or Long Register with Register | |
| 9160 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9161 match(Set dst (OrL dst src)); | |
| 9162 effect(KILL cr); | |
| 9163 format %{ "OR $dst.lo,$src.lo\n\t" | |
| 9164 "OR $dst.hi,$src.hi" %} | |
| 9165 opcode(0x0B,0x0B); | |
| 9166 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 9167 ins_pipe( ialu_reg_reg_long ); | |
| 9168 %} | |
| 9169 | |
| 9170 // Or Long Register with Immediate | |
| 9171 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9172 match(Set dst (OrL dst src)); | |
| 9173 effect(KILL cr); | |
| 9174 format %{ "OR $dst.lo,$src.lo\n\t" | |
| 9175 "OR $dst.hi,$src.hi" %} | |
| 9176 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */ | |
| 9177 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9178 ins_pipe( ialu_reg_long ); | |
| 9179 %} | |
| 9180 | |
| 9181 // Or Long Register with Memory | |
| 9182 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9183 match(Set dst (OrL dst (LoadL mem))); | |
| 9184 effect(KILL cr); | |
| 9185 ins_cost(125); | |
| 9186 format %{ "OR $dst.lo,$mem\n\t" | |
| 9187 "OR $dst.hi,$mem+4" %} | |
| 9188 opcode(0x0B,0x0B); | |
| 9189 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9190 ins_pipe( ialu_reg_long_mem ); | |
| 9191 %} | |
| 9192 | |
| 9193 // Xor Long Register with Register | |
| 9194 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ | |
| 9195 match(Set dst (XorL dst src)); | |
| 9196 effect(KILL cr); | |
| 9197 format %{ "XOR $dst.lo,$src.lo\n\t" | |
| 9198 "XOR $dst.hi,$src.hi" %} | |
| 9199 opcode(0x33,0x33); | |
| 9200 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); | |
| 9201 ins_pipe( ialu_reg_reg_long ); | |
| 9202 %} | |
| 9203 | |
| 403 | 9204 // Xor Long Register with Immediate -1 |
| 9205 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{ | |
| 9206 match(Set dst (XorL dst imm)); | |
| 9207 format %{ "NOT $dst.lo\n\t" | |
| 9208 "NOT $dst.hi" %} | |
| 9209 ins_encode %{ | |
| 9210 __ notl($dst$$Register); | |
| 9211 __ notl(HIGH_FROM_LOW($dst$$Register)); | |
| 9212 %} | |
| 9213 ins_pipe( ialu_reg_long ); | |
| 9214 %} | |
| 9215 | |
| 0 | 9216 // Xor Long Register with Immediate |
| 9217 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ | |
| 9218 match(Set dst (XorL dst src)); | |
| 9219 effect(KILL cr); | |
| 9220 format %{ "XOR $dst.lo,$src.lo\n\t" | |
| 9221 "XOR $dst.hi,$src.hi" %} | |
| 9222 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */ | |
| 9223 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); | |
| 9224 ins_pipe( ialu_reg_long ); | |
| 9225 %} | |
| 9226 | |
| 9227 // Xor Long Register with Memory | |
| 9228 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ | |
| 9229 match(Set dst (XorL dst (LoadL mem))); | |
| 9230 effect(KILL cr); | |
| 9231 ins_cost(125); | |
| 9232 format %{ "XOR $dst.lo,$mem\n\t" | |
| 9233 "XOR $dst.hi,$mem+4" %} | |
| 9234 opcode(0x33,0x33); | |
| 9235 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); | |
| 9236 ins_pipe( ialu_reg_long_mem ); | |
| 9237 %} | |
| 9238 | |
| 219 | 9239 // Shift Left Long by 1 |
| 9240 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{ | |
| 9241 predicate(UseNewLongLShift); | |
| 9242 match(Set dst (LShiftL dst cnt)); | |
| 9243 effect(KILL cr); | |
| 9244 ins_cost(100); | |
| 9245 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 9246 "ADC $dst.hi,$dst.hi" %} | |
| 9247 ins_encode %{ | |
| 9248 __ addl($dst$$Register,$dst$$Register); | |
| 9249 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9250 %} | |
| 9251 ins_pipe( ialu_reg_long ); | |
| 9252 %} | |
| 9253 | |
| 9254 // Shift Left Long by 2 | |
| 9255 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{ | |
| 9256 predicate(UseNewLongLShift); | |
| 9257 match(Set dst (LShiftL dst cnt)); | |
| 9258 effect(KILL cr); | |
| 9259 ins_cost(100); | |
| 9260 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 9261 "ADC $dst.hi,$dst.hi\n\t" | |
| 9262 "ADD $dst.lo,$dst.lo\n\t" | |
| 9263 "ADC $dst.hi,$dst.hi" %} | |
| 9264 ins_encode %{ | |
| 9265 __ addl($dst$$Register,$dst$$Register); | |
| 9266 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9267 __ addl($dst$$Register,$dst$$Register); | |
| 9268 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9269 %} | |
| 9270 ins_pipe( ialu_reg_long ); | |
| 9271 %} | |
| 9272 | |
| 9273 // Shift Left Long by 3 | |
| 9274 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{ | |
| 9275 predicate(UseNewLongLShift); | |
| 9276 match(Set dst (LShiftL dst cnt)); | |
| 9277 effect(KILL cr); | |
| 9278 ins_cost(100); | |
| 9279 format %{ "ADD $dst.lo,$dst.lo\n\t" | |
| 9280 "ADC $dst.hi,$dst.hi\n\t" | |
| 9281 "ADD $dst.lo,$dst.lo\n\t" | |
| 9282 "ADC $dst.hi,$dst.hi\n\t" | |
| 9283 "ADD $dst.lo,$dst.lo\n\t" | |
| 9284 "ADC $dst.hi,$dst.hi" %} | |
| 9285 ins_encode %{ | |
| 9286 __ addl($dst$$Register,$dst$$Register); | |
| 9287 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9288 __ addl($dst$$Register,$dst$$Register); | |
| 9289 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9290 __ addl($dst$$Register,$dst$$Register); | |
| 9291 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); | |
| 9292 %} | |
| 9293 ins_pipe( ialu_reg_long ); | |
| 9294 %} | |
| 9295 | |
| 0 | 9296 // Shift Left Long by 1-31 |
| 9297 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 9298 match(Set dst (LShiftL dst cnt)); | |
| 9299 effect(KILL cr); | |
| 9300 ins_cost(200); | |
| 9301 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t" | |
| 9302 "SHL $dst.lo,$cnt" %} | |
| 9303 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */ | |
| 9304 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 9305 ins_pipe( ialu_reg_long ); | |
| 9306 %} | |
| 9307 | |
| 9308 // Shift Left Long by 32-63 | |
| 9309 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 9310 match(Set dst (LShiftL dst cnt)); | |
| 9311 effect(KILL cr); | |
| 9312 ins_cost(300); | |
| 9313 format %{ "MOV $dst.hi,$dst.lo\n" | |
| 9314 "\tSHL $dst.hi,$cnt-32\n" | |
| 9315 "\tXOR $dst.lo,$dst.lo" %} | |
| 9316 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 9317 ins_encode( move_long_big_shift_clr(dst,cnt) ); | |
| 9318 ins_pipe( ialu_reg_long ); | |
| 9319 %} | |
| 9320 | |
| 9321 // Shift Left Long by variable | |
| 9322 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9323 match(Set dst (LShiftL dst shift)); | |
| 9324 effect(KILL cr); | |
| 9325 ins_cost(500+200); | |
| 9326 size(17); | |
| 9327 format %{ "TEST $shift,32\n\t" | |
| 9328 "JEQ,s small\n\t" | |
| 9329 "MOV $dst.hi,$dst.lo\n\t" | |
| 9330 "XOR $dst.lo,$dst.lo\n" | |
| 9331 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t" | |
| 9332 "SHL $dst.lo,$shift" %} | |
| 9333 ins_encode( shift_left_long( dst, shift ) ); | |
| 9334 ins_pipe( pipe_slow ); | |
| 9335 %} | |
| 9336 | |
| 9337 // Shift Right Long by 1-31 | |
| 9338 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 9339 match(Set dst (URShiftL dst cnt)); | |
| 9340 effect(KILL cr); | |
| 9341 ins_cost(200); | |
| 9342 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t" | |
| 9343 "SHR $dst.hi,$cnt" %} | |
| 9344 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */ | |
| 9345 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 9346 ins_pipe( ialu_reg_long ); | |
| 9347 %} | |
| 9348 | |
| 9349 // Shift Right Long by 32-63 | |
| 9350 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 9351 match(Set dst (URShiftL dst cnt)); | |
| 9352 effect(KILL cr); | |
| 9353 ins_cost(300); | |
| 9354 format %{ "MOV $dst.lo,$dst.hi\n" | |
| 9355 "\tSHR $dst.lo,$cnt-32\n" | |
| 9356 "\tXOR $dst.hi,$dst.hi" %} | |
| 9357 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 9358 ins_encode( move_long_big_shift_clr(dst,cnt) ); | |
| 9359 ins_pipe( ialu_reg_long ); | |
| 9360 %} | |
| 9361 | |
| 9362 // Shift Right Long by variable | |
| 9363 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9364 match(Set dst (URShiftL dst shift)); | |
| 9365 effect(KILL cr); | |
| 9366 ins_cost(600); | |
| 9367 size(17); | |
| 9368 format %{ "TEST $shift,32\n\t" | |
| 9369 "JEQ,s small\n\t" | |
| 9370 "MOV $dst.lo,$dst.hi\n\t" | |
| 9371 "XOR $dst.hi,$dst.hi\n" | |
| 9372 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t" | |
| 9373 "SHR $dst.hi,$shift" %} | |
| 9374 ins_encode( shift_right_long( dst, shift ) ); | |
| 9375 ins_pipe( pipe_slow ); | |
| 9376 %} | |
| 9377 | |
| 9378 // Shift Right Long by 1-31 | |
| 9379 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ | |
| 9380 match(Set dst (RShiftL dst cnt)); | |
| 9381 effect(KILL cr); | |
| 9382 ins_cost(200); | |
| 9383 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t" | |
| 9384 "SAR $dst.hi,$cnt" %} | |
| 9385 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */ | |
| 9386 ins_encode( move_long_small_shift(dst,cnt) ); | |
| 9387 ins_pipe( ialu_reg_long ); | |
| 9388 %} | |
| 9389 | |
| 9390 // Shift Right Long by 32-63 | |
| 9391 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ | |
| 9392 match(Set dst (RShiftL dst cnt)); | |
| 9393 effect(KILL cr); | |
| 9394 ins_cost(300); | |
| 9395 format %{ "MOV $dst.lo,$dst.hi\n" | |
| 9396 "\tSAR $dst.lo,$cnt-32\n" | |
| 9397 "\tSAR $dst.hi,31" %} | |
| 9398 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 9399 ins_encode( move_long_big_shift_sign(dst,cnt) ); | |
| 9400 ins_pipe( ialu_reg_long ); | |
| 9401 %} | |
| 9402 | |
| 9403 // Shift Right arithmetic Long by variable | |
| 9404 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ | |
| 9405 match(Set dst (RShiftL dst shift)); | |
| 9406 effect(KILL cr); | |
| 9407 ins_cost(600); | |
| 9408 size(18); | |
| 9409 format %{ "TEST $shift,32\n\t" | |
| 9410 "JEQ,s small\n\t" | |
| 9411 "MOV $dst.lo,$dst.hi\n\t" | |
| 9412 "SAR $dst.hi,31\n" | |
| 9413 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t" | |
| 9414 "SAR $dst.hi,$shift" %} | |
| 9415 ins_encode( shift_right_arith_long( dst, shift ) ); | |
| 9416 ins_pipe( pipe_slow ); | |
| 9417 %} | |
| 9418 | |
| 9419 | |
| 9420 //----------Double Instructions------------------------------------------------ | |
| 9421 // Double Math | |
| 9422 | |
| 9423 // Compare & branch | |
| 9424 | |
| 9425 // P6 version of float compare, sets condition codes in EFLAGS | |
|
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9426 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{ |
| 0 | 9427 predicate(VM_Version::supports_cmov() && UseSSE <=1); |
| 9428 match(Set cr (CmpD src1 src2)); | |
| 9429 effect(KILL rax); | |
| 9430 ins_cost(150); | |
| 9431 format %{ "FLD $src1\n\t" | |
| 9432 "FUCOMIP ST,$src2 // P6 instruction\n\t" | |
| 9433 "JNP exit\n\t" | |
| 9434 "MOV ah,1 // saw a NaN, set CF\n\t" | |
| 9435 "SAHF\n" | |
| 9436 "exit:\tNOP // avoid branch to branch" %} | |
| 9437 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ | |
|
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9438 ins_encode( Push_Reg_DPR(src1), |
| 0 | 9439 OpcP, RegOpc(src2), |
| 9440 cmpF_P6_fixup ); | |
| 9441 ins_pipe( pipe_slow ); | |
| 9442 %} | |
| 9443 | |
|
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9444 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{ |
|
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9445 predicate(VM_Version::supports_cmov() && UseSSE <=1); |
|
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9446 match(Set cr (CmpD src1 src2)); |
|
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9447 ins_cost(150); |
|
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9448 format %{ "FLD $src1\n\t" |
|
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9449 "FUCOMIP ST,$src2 // P6 instruction" %} |
|
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|
9450 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ |
|
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9451 ins_encode( Push_Reg_DPR(src1), |
|
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9452 OpcP, RegOpc(src2)); |
|
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|
9453 ins_pipe( pipe_slow ); |
|
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|
9454 %} |
|
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|
9455 |
| 0 | 9456 // Compare & branch |
|
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9457 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{ |
| 0 | 9458 predicate(UseSSE<=1); |
| 9459 match(Set cr (CmpD src1 src2)); | |
| 9460 effect(KILL rax); | |
| 9461 ins_cost(200); | |
| 9462 format %{ "FLD $src1\n\t" | |
| 9463 "FCOMp $src2\n\t" | |
| 9464 "FNSTSW AX\n\t" | |
| 9465 "TEST AX,0x400\n\t" | |
| 9466 "JZ,s flags\n\t" | |
| 9467 "MOV AH,1\t# unordered treat as LT\n" | |
| 9468 "flags:\tSAHF" %} | |
| 9469 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
|
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9470 ins_encode( Push_Reg_DPR(src1), |
| 0 | 9471 OpcP, RegOpc(src2), |
| 9472 fpu_flags); | |
| 9473 ins_pipe( pipe_slow ); | |
| 9474 %} | |
| 9475 | |
| 9476 // Compare vs zero into -1,0,1 | |
|
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9477 instruct cmpDPR_0(eRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 9478 predicate(UseSSE<=1); |
| 9479 match(Set dst (CmpD3 src1 zero)); | |
| 9480 effect(KILL cr, KILL rax); | |
| 9481 ins_cost(280); | |
| 9482 format %{ "FTSTD $dst,$src1" %} | |
| 9483 opcode(0xE4, 0xD9); | |
|
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9484 ins_encode( Push_Reg_DPR(src1), |
| 0 | 9485 OpcS, OpcP, PopFPU, |
| 9486 CmpF_Result(dst)); | |
| 9487 ins_pipe( pipe_slow ); | |
| 9488 %} | |
| 9489 | |
| 9490 // Compare into -1,0,1 | |
|
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9491 instruct cmpDPR_reg(eRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 9492 predicate(UseSSE<=1); |
| 9493 match(Set dst (CmpD3 src1 src2)); | |
| 9494 effect(KILL cr, KILL rax); | |
| 9495 ins_cost(300); | |
| 9496 format %{ "FCMPD $dst,$src1,$src2" %} | |
| 9497 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
|
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9498 ins_encode( Push_Reg_DPR(src1), |
| 0 | 9499 OpcP, RegOpc(src2), |
| 9500 CmpF_Result(dst)); | |
| 9501 ins_pipe( pipe_slow ); | |
| 9502 %} | |
| 9503 | |
| 9504 // float compare and set condition codes in EFLAGS by XMM regs | |
|
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9505 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{ |
| 0 | 9506 predicate(UseSSE>=2); |
| 4759 | 9507 match(Set cr (CmpD src1 src2)); |
| 9508 ins_cost(145); | |
| 9509 format %{ "UCOMISD $src1,$src2\n\t" | |
| 9510 "JNP,s exit\n\t" | |
| 9511 "PUSHF\t# saw NaN, set CF\n\t" | |
| 9512 "AND [rsp], #0xffffff2b\n\t" | |
| 9513 "POPF\n" | |
| 9514 "exit:" %} | |
| 9515 ins_encode %{ | |
| 9516 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9517 emit_cmpfp_fixup(_masm); | |
| 9518 %} | |
| 9519 ins_pipe( pipe_slow ); | |
| 9520 %} | |
| 9521 | |
|
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9522 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{ |
|
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|
9523 predicate(UseSSE>=2); |
| 4759 | 9524 match(Set cr (CmpD src1 src2)); |
|
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|
9525 ins_cost(100); |
| 4759 | 9526 format %{ "UCOMISD $src1,$src2" %} |
| 9527 ins_encode %{ | |
| 9528 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9529 %} | |
|
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|
9530 ins_pipe( pipe_slow ); |
|
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|
9531 %} |
|
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|
9532 |
| 0 | 9533 // float compare and set condition codes in EFLAGS by XMM regs |
|
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9534 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{ |
| 0 | 9535 predicate(UseSSE>=2); |
| 4759 | 9536 match(Set cr (CmpD src1 (LoadD src2))); |
| 0 | 9537 ins_cost(145); |
| 4759 | 9538 format %{ "UCOMISD $src1,$src2\n\t" |
| 9539 "JNP,s exit\n\t" | |
| 9540 "PUSHF\t# saw NaN, set CF\n\t" | |
| 9541 "AND [rsp], #0xffffff2b\n\t" | |
| 9542 "POPF\n" | |
| 9543 "exit:" %} | |
| 9544 ins_encode %{ | |
| 9545 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9546 emit_cmpfp_fixup(_masm); | |
| 9547 %} | |
| 9548 ins_pipe( pipe_slow ); | |
| 9549 %} | |
| 9550 | |
|
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9551 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{ |
|
415
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|
9552 predicate(UseSSE>=2); |
| 4759 | 9553 match(Set cr (CmpD src1 (LoadD src2))); |
|
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|
9554 ins_cost(100); |
| 4759 | 9555 format %{ "UCOMISD $src1,$src2" %} |
| 9556 ins_encode %{ | |
| 9557 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9558 %} | |
|
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|
9559 ins_pipe( pipe_slow ); |
|
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|
9560 %} |
|
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|
9561 |
| 0 | 9562 // Compare into -1,0,1 in XMM |
|
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9563 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{ |
| 0 | 9564 predicate(UseSSE>=2); |
| 9565 match(Set dst (CmpD3 src1 src2)); | |
| 9566 effect(KILL cr); | |
| 9567 ins_cost(255); | |
| 4759 | 9568 format %{ "UCOMISD $src1, $src2\n\t" |
| 9569 "MOV $dst, #-1\n\t" | |
| 9570 "JP,s done\n\t" | |
| 9571 "JB,s done\n\t" | |
| 9572 "SETNE $dst\n\t" | |
| 9573 "MOVZB $dst, $dst\n" | |
| 9574 "done:" %} | |
| 9575 ins_encode %{ | |
| 9576 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); | |
| 9577 emit_cmpfp3(_masm, $dst$$Register); | |
| 9578 %} | |
| 0 | 9579 ins_pipe( pipe_slow ); |
| 9580 %} | |
| 9581 | |
| 9582 // Compare into -1,0,1 in XMM and memory | |
|
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9583 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{ |
| 0 | 9584 predicate(UseSSE>=2); |
| 4759 | 9585 match(Set dst (CmpD3 src1 (LoadD src2))); |
| 0 | 9586 effect(KILL cr); |
| 9587 ins_cost(275); | |
| 4759 | 9588 format %{ "UCOMISD $src1, $src2\n\t" |
| 9589 "MOV $dst, #-1\n\t" | |
| 9590 "JP,s done\n\t" | |
| 9591 "JB,s done\n\t" | |
| 9592 "SETNE $dst\n\t" | |
| 9593 "MOVZB $dst, $dst\n" | |
| 9594 "done:" %} | |
| 9595 ins_encode %{ | |
| 9596 __ ucomisd($src1$$XMMRegister, $src2$$Address); | |
| 9597 emit_cmpfp3(_masm, $dst$$Register); | |
| 9598 %} | |
| 0 | 9599 ins_pipe( pipe_slow ); |
| 9600 %} | |
| 9601 | |
| 9602 | |
|
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9603 instruct subDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9604 predicate (UseSSE <=1); |
| 9605 match(Set dst (SubD dst src)); | |
| 9606 | |
| 9607 format %{ "FLD $src\n\t" | |
| 9608 "DSUBp $dst,ST" %} | |
| 9609 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */ | |
| 9610 ins_cost(150); | |
|
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|
9611 ins_encode( Push_Reg_DPR(src), |
| 0 | 9612 OpcP, RegOpc(dst) ); |
| 9613 ins_pipe( fpu_reg_reg ); | |
| 9614 %} | |
| 9615 | |
|
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9616 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{ |
| 0 | 9617 predicate (UseSSE <=1); |
| 9618 match(Set dst (RoundDouble (SubD src1 src2))); | |
| 9619 ins_cost(250); | |
| 9620 | |
| 9621 format %{ "FLD $src2\n\t" | |
| 9622 "DSUB ST,$src1\n\t" | |
| 9623 "FSTP_D $dst\t# D-round" %} | |
| 9624 opcode(0xD8, 0x5); | |
|
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9625 ins_encode( Push_Reg_DPR(src2), |
|
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9626 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) ); |
| 0 | 9627 ins_pipe( fpu_mem_reg_reg ); |
| 9628 %} | |
| 9629 | |
| 9630 | |
|
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9631 instruct subDPR_reg_mem(regDPR dst, memory src) %{ |
| 0 | 9632 predicate (UseSSE <=1); |
| 9633 match(Set dst (SubD dst (LoadD src))); | |
| 9634 ins_cost(150); | |
| 9635 | |
| 9636 format %{ "FLD $src\n\t" | |
| 9637 "DSUBp $dst,ST" %} | |
| 9638 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */ | |
| 9639 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 9640 OpcP, RegOpc(dst) ); | |
| 9641 ins_pipe( fpu_reg_mem ); | |
| 9642 %} | |
| 9643 | |
|
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9644 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9645 predicate (UseSSE<=1); |
| 9646 match(Set dst (AbsD src)); | |
| 9647 ins_cost(100); | |
| 9648 format %{ "FABS" %} | |
| 9649 opcode(0xE1, 0xD9); | |
| 9650 ins_encode( OpcS, OpcP ); | |
| 9651 ins_pipe( fpu_reg_reg ); | |
| 9652 %} | |
| 9653 | |
|
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9654 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9655 predicate(UseSSE<=1); |
| 9656 match(Set dst (NegD src)); | |
| 9657 ins_cost(100); | |
| 9658 format %{ "FCHS" %} | |
| 9659 opcode(0xE0, 0xD9); | |
| 9660 ins_encode( OpcS, OpcP ); | |
| 9661 ins_pipe( fpu_reg_reg ); | |
| 9662 %} | |
| 9663 | |
|
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9664 instruct addDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9665 predicate(UseSSE<=1); |
| 9666 match(Set dst (AddD dst src)); | |
| 9667 format %{ "FLD $src\n\t" | |
| 9668 "DADD $dst,ST" %} | |
| 9669 size(4); | |
| 9670 ins_cost(150); | |
| 9671 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/ | |
|
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9672 ins_encode( Push_Reg_DPR(src), |
| 0 | 9673 OpcP, RegOpc(dst) ); |
| 9674 ins_pipe( fpu_reg_reg ); | |
| 9675 %} | |
| 9676 | |
| 9677 | |
|
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9678 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{ |
| 0 | 9679 predicate(UseSSE<=1); |
| 9680 match(Set dst (RoundDouble (AddD src1 src2))); | |
| 9681 ins_cost(250); | |
| 9682 | |
| 9683 format %{ "FLD $src2\n\t" | |
| 9684 "DADD ST,$src1\n\t" | |
| 9685 "FSTP_D $dst\t# D-round" %} | |
| 9686 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/ | |
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9687 ins_encode( Push_Reg_DPR(src2), |
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9688 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) ); |
| 0 | 9689 ins_pipe( fpu_mem_reg_reg ); |
| 9690 %} | |
| 9691 | |
| 9692 | |
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9693 instruct addDPR_reg_mem(regDPR dst, memory src) %{ |
| 0 | 9694 predicate(UseSSE<=1); |
| 9695 match(Set dst (AddD dst (LoadD src))); | |
| 9696 ins_cost(150); | |
| 9697 | |
| 9698 format %{ "FLD $src\n\t" | |
| 9699 "DADDp $dst,ST" %} | |
| 9700 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */ | |
| 9701 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 9702 OpcP, RegOpc(dst) ); | |
| 9703 ins_pipe( fpu_reg_mem ); | |
| 9704 %} | |
| 9705 | |
| 9706 // add-to-memory | |
|
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9707 instruct addDPR_mem_reg(memory dst, regDPR src) %{ |
| 0 | 9708 predicate(UseSSE<=1); |
| 9709 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src)))); | |
| 9710 ins_cost(150); | |
| 9711 | |
| 9712 format %{ "FLD_D $dst\n\t" | |
| 9713 "DADD ST,$src\n\t" | |
| 9714 "FST_D $dst" %} | |
| 9715 opcode(0xDD, 0x0); | |
| 9716 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst), | |
| 9717 Opcode(0xD8), RegOpc(src), | |
| 9718 set_instruction_start, | |
| 9719 Opcode(0xDD), RMopc_Mem(0x03,dst) ); | |
| 9720 ins_pipe( fpu_reg_mem ); | |
| 9721 %} | |
| 9722 | |
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9723 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{ |
| 0 | 9724 predicate(UseSSE<=1); |
| 2008 | 9725 match(Set dst (AddD dst con)); |
| 0 | 9726 ins_cost(125); |
| 9727 format %{ "FLD1\n\t" | |
| 9728 "DADDp $dst,ST" %} | |
| 2008 | 9729 ins_encode %{ |
| 9730 __ fld1(); | |
| 9731 __ faddp($dst$$reg); | |
| 9732 %} | |
| 9733 ins_pipe(fpu_reg); | |
| 9734 %} | |
| 9735 | |
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9736 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{ |
| 0 | 9737 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 ); |
| 2008 | 9738 match(Set dst (AddD dst con)); |
| 0 | 9739 ins_cost(200); |
| 2008 | 9740 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9741 "DADDp $dst,ST" %} |
| 2008 | 9742 ins_encode %{ |
| 9743 __ fld_d($constantaddress($con)); | |
| 9744 __ faddp($dst$$reg); | |
| 9745 %} | |
| 9746 ins_pipe(fpu_reg_mem); | |
| 0 | 9747 %} |
| 9748 | |
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9749 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{ |
| 0 | 9750 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 ); |
| 9751 match(Set dst (RoundDouble (AddD src con))); | |
| 9752 ins_cost(200); | |
| 2008 | 9753 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9754 "DADD ST,$src\n\t" |
| 9755 "FSTP_D $dst\t# D-round" %} | |
| 2008 | 9756 ins_encode %{ |
| 9757 __ fld_d($constantaddress($con)); | |
| 9758 __ fadd($src$$reg); | |
| 9759 __ fstp_d(Address(rsp, $dst$$disp)); | |
| 9760 %} | |
| 9761 ins_pipe(fpu_mem_reg_con); | |
| 0 | 9762 %} |
| 9763 | |
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9764 instruct mulDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9765 predicate(UseSSE<=1); |
| 9766 match(Set dst (MulD dst src)); | |
| 9767 format %{ "FLD $src\n\t" | |
| 9768 "DMULp $dst,ST" %} | |
| 9769 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/ | |
| 9770 ins_cost(150); | |
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9771 ins_encode( Push_Reg_DPR(src), |
| 0 | 9772 OpcP, RegOpc(dst) ); |
| 9773 ins_pipe( fpu_reg_reg ); | |
| 9774 %} | |
| 9775 | |
| 9776 // Strict FP instruction biases argument before multiply then | |
| 9777 // biases result to avoid double rounding of subnormals. | |
| 9778 // | |
| 9779 // scale arg1 by multiplying arg1 by 2^(-15360) | |
| 9780 // load arg2 | |
| 9781 // multiply scaled arg1 by arg2 | |
| 9782 // rescale product by 2^(15360) | |
| 9783 // | |
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9784 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{ |
| 0 | 9785 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() ); |
| 9786 match(Set dst (MulD dst src)); | |
| 9787 ins_cost(1); // Select this instruction for all strict FP double multiplies | |
| 9788 | |
| 9789 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t" | |
| 9790 "DMULp $dst,ST\n\t" | |
| 9791 "FLD $src\n\t" | |
| 9792 "DMULp $dst,ST\n\t" | |
| 9793 "FLD StubRoutines::_fpu_subnormal_bias2\n\t" | |
| 9794 "DMULp $dst,ST\n\t" %} | |
| 9795 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/ | |
| 9796 ins_encode( strictfp_bias1(dst), | |
|
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9797 Push_Reg_DPR(src), |
| 0 | 9798 OpcP, RegOpc(dst), |
| 9799 strictfp_bias2(dst) ); | |
| 9800 ins_pipe( fpu_reg_reg ); | |
| 9801 %} | |
| 9802 | |
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9803 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{ |
| 0 | 9804 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 ); |
| 2008 | 9805 match(Set dst (MulD dst con)); |
| 0 | 9806 ins_cost(200); |
| 2008 | 9807 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" |
| 0 | 9808 "DMULp $dst,ST" %} |
| 2008 | 9809 ins_encode %{ |
| 9810 __ fld_d($constantaddress($con)); | |
| 9811 __ fmulp($dst$$reg); | |
| 9812 %} | |
| 9813 ins_pipe(fpu_reg_mem); | |
| 0 | 9814 %} |
| 9815 | |
| 9816 | |
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9817 instruct mulDPR_reg_mem(regDPR dst, memory src) %{ |
| 0 | 9818 predicate( UseSSE<=1 ); |
| 9819 match(Set dst (MulD dst (LoadD src))); | |
| 9820 ins_cost(200); | |
| 9821 format %{ "FLD_D $src\n\t" | |
| 9822 "DMULp $dst,ST" %} | |
| 9823 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */ | |
| 9824 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 9825 OpcP, RegOpc(dst) ); | |
| 9826 ins_pipe( fpu_reg_mem ); | |
| 9827 %} | |
| 9828 | |
| 9829 // | |
| 9830 // Cisc-alternate to reg-reg multiply | |
|
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9831 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{ |
| 0 | 9832 predicate( UseSSE<=1 ); |
| 9833 match(Set dst (MulD src (LoadD mem))); | |
| 9834 ins_cost(250); | |
| 9835 format %{ "FLD_D $mem\n\t" | |
| 9836 "DMUL ST,$src\n\t" | |
| 9837 "FSTP_D $dst" %} | |
| 9838 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */ | |
| 9839 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem), | |
|
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9840 OpcReg_FPR(src), |
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9841 Pop_Reg_DPR(dst) ); |
| 0 | 9842 ins_pipe( fpu_reg_reg_mem ); |
| 9843 %} | |
| 9844 | |
| 9845 | |
|
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9846 // MACRO3 -- addDPR a mulDPR |
| 0 | 9847 // This instruction is a '2-address' instruction in that the result goes |
| 9848 // back to src2. This eliminates a move from the macro; possibly the | |
| 9849 // register allocator will have to add it back (and maybe not). | |
|
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9850 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{ |
| 0 | 9851 predicate( UseSSE<=1 ); |
| 9852 match(Set src2 (AddD (MulD src0 src1) src2)); | |
| 9853 format %{ "FLD $src0\t# ===MACRO3d===\n\t" | |
| 9854 "DMUL ST,$src1\n\t" | |
| 9855 "DADDp $src2,ST" %} | |
| 9856 ins_cost(250); | |
| 9857 opcode(0xDD); /* LoadD DD /0 */ | |
|
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9858 ins_encode( Push_Reg_FPR(src0), |
| 0 | 9859 FMul_ST_reg(src1), |
| 9860 FAddP_reg_ST(src2) ); | |
| 9861 ins_pipe( fpu_reg_reg_reg ); | |
| 9862 %} | |
| 9863 | |
| 9864 | |
|
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9865 // MACRO3 -- subDPR a mulDPR |
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9866 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{ |
| 0 | 9867 predicate( UseSSE<=1 ); |
| 9868 match(Set src2 (SubD (MulD src0 src1) src2)); | |
| 9869 format %{ "FLD $src0\t# ===MACRO3d===\n\t" | |
| 9870 "DMUL ST,$src1\n\t" | |
| 9871 "DSUBRp $src2,ST" %} | |
| 9872 ins_cost(250); | |
|
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9873 ins_encode( Push_Reg_FPR(src0), |
| 0 | 9874 FMul_ST_reg(src1), |
| 9875 Opcode(0xDE), Opc_plus(0xE0,src2)); | |
| 9876 ins_pipe( fpu_reg_reg_reg ); | |
| 9877 %} | |
| 9878 | |
| 9879 | |
|
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9880 instruct divDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 9881 predicate( UseSSE<=1 ); |
| 9882 match(Set dst (DivD dst src)); | |
| 9883 | |
| 9884 format %{ "FLD $src\n\t" | |
| 9885 "FDIVp $dst,ST" %} | |
| 9886 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
| 9887 ins_cost(150); | |
|
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9888 ins_encode( Push_Reg_DPR(src), |
| 0 | 9889 OpcP, RegOpc(dst) ); |
| 9890 ins_pipe( fpu_reg_reg ); | |
| 9891 %} | |
| 9892 | |
| 9893 // Strict FP instruction biases argument before division then | |
| 9894 // biases result, to avoid double rounding of subnormals. | |
| 9895 // | |
| 9896 // scale dividend by multiplying dividend by 2^(-15360) | |
| 9897 // load divisor | |
| 9898 // divide scaled dividend by divisor | |
| 9899 // rescale quotient by 2^(15360) | |
| 9900 // | |
|
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9901 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{ |
| 0 | 9902 predicate (UseSSE<=1); |
| 9903 match(Set dst (DivD dst src)); | |
| 9904 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() ); | |
| 9905 ins_cost(01); | |
| 9906 | |
| 9907 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t" | |
| 9908 "DMULp $dst,ST\n\t" | |
| 9909 "FLD $src\n\t" | |
| 9910 "FDIVp $dst,ST\n\t" | |
| 9911 "FLD StubRoutines::_fpu_subnormal_bias2\n\t" | |
| 9912 "DMULp $dst,ST\n\t" %} | |
| 9913 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
| 9914 ins_encode( strictfp_bias1(dst), | |
|
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9915 Push_Reg_DPR(src), |
| 0 | 9916 OpcP, RegOpc(dst), |
| 9917 strictfp_bias2(dst) ); | |
| 9918 ins_pipe( fpu_reg_reg ); | |
| 9919 %} | |
| 9920 | |
|
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9921 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{ |
| 0 | 9922 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) ); |
| 9923 match(Set dst (RoundDouble (DivD src1 src2))); | |
| 9924 | |
| 9925 format %{ "FLD $src1\n\t" | |
| 9926 "FDIV ST,$src2\n\t" | |
| 9927 "FSTP_D $dst\t# D-round" %} | |
| 9928 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */ | |
|
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9929 ins_encode( Push_Reg_DPR(src1), |
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9930 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) ); |
| 0 | 9931 ins_pipe( fpu_mem_reg_reg ); |
| 9932 %} | |
| 9933 | |
| 9934 | |
|
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9935 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 9936 predicate(UseSSE<=1); |
| 9937 match(Set dst (ModD dst src)); | |
|
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9938 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS |
| 0 | 9939 |
| 9940 format %{ "DMOD $dst,$src" %} | |
| 9941 ins_cost(250); | |
|
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9942 ins_encode(Push_Reg_Mod_DPR(dst, src), |
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9943 emitModDPR(), |
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9944 Push_Result_Mod_DPR(src), |
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9945 Pop_Reg_DPR(dst)); |
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9946 ins_pipe( pipe_slow ); |
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9947 %} |
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9948 |
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|
9949 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 9950 predicate(UseSSE>=2); |
| 9951 match(Set dst (ModD src0 src1)); | |
| 9952 effect(KILL rax, KILL cr); | |
| 9953 | |
| 9954 format %{ "SUB ESP,8\t # DMOD\n" | |
| 9955 "\tMOVSD [ESP+0],$src1\n" | |
| 9956 "\tFLD_D [ESP+0]\n" | |
| 9957 "\tMOVSD [ESP+0],$src0\n" | |
| 9958 "\tFLD_D [ESP+0]\n" | |
| 9959 "loop:\tFPREM\n" | |
| 9960 "\tFWAIT\n" | |
| 9961 "\tFNSTSW AX\n" | |
| 9962 "\tSAHF\n" | |
| 9963 "\tJP loop\n" | |
| 9964 "\tFSTP_D [ESP+0]\n" | |
| 9965 "\tMOVSD $dst,[ESP+0]\n" | |
| 9966 "\tADD ESP,8\n" | |
| 9967 "\tFSTP ST0\t # Restore FPU Stack" | |
| 9968 %} | |
| 9969 ins_cost(250); | |
|
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9970 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU); |
|
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|
9971 ins_pipe( pipe_slow ); |
|
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|
9972 %} |
|
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|
9973 |
|
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|
9974 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9975 predicate (UseSSE<=1); |
| 9976 match(Set dst (SinD src)); | |
| 9977 ins_cost(1800); | |
| 9978 format %{ "DSIN $dst" %} | |
| 9979 opcode(0xD9, 0xFE); | |
| 9980 ins_encode( OpcP, OpcS ); | |
| 9981 ins_pipe( pipe_slow ); | |
| 9982 %} | |
| 9983 | |
|
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|
9984 instruct sinD_reg(regD dst, eFlagsReg cr) %{ |
| 0 | 9985 predicate (UseSSE>=2); |
| 9986 match(Set dst (SinD dst)); | |
|
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9987 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" |
| 0 | 9988 ins_cost(1800); |
| 9989 format %{ "DSIN $dst" %} | |
| 9990 opcode(0xD9, 0xFE); | |
|
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|
9991 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) ); |
|
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|
9992 ins_pipe( pipe_slow ); |
|
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|
9993 %} |
|
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|
9994 |
|
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|
9995 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 9996 predicate (UseSSE<=1); |
| 9997 match(Set dst (CosD src)); | |
| 9998 ins_cost(1800); | |
| 9999 format %{ "DCOS $dst" %} | |
| 10000 opcode(0xD9, 0xFF); | |
| 10001 ins_encode( OpcP, OpcS ); | |
| 10002 ins_pipe( pipe_slow ); | |
| 10003 %} | |
| 10004 | |
|
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|
10005 instruct cosD_reg(regD dst, eFlagsReg cr) %{ |
| 0 | 10006 predicate (UseSSE>=2); |
| 10007 match(Set dst (CosD dst)); | |
|
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|
10008 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" |
| 0 | 10009 ins_cost(1800); |
| 10010 format %{ "DCOS $dst" %} | |
| 10011 opcode(0xD9, 0xFF); | |
|
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|
10012 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) ); |
|
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|
10013 ins_pipe( pipe_slow ); |
|
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|
10014 %} |
|
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|
10015 |
|
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|
10016 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 10017 predicate (UseSSE<=1); |
| 10018 match(Set dst(TanD src)); | |
| 10019 format %{ "DTAN $dst" %} | |
| 10020 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan | |
| 10021 Opcode(0xDD), Opcode(0xD8)); // fstp st | |
| 10022 ins_pipe( pipe_slow ); | |
| 10023 %} | |
| 10024 | |
|
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|
10025 instruct tanD_reg(regD dst, eFlagsReg cr) %{ |
| 0 | 10026 predicate (UseSSE>=2); |
| 10027 match(Set dst(TanD dst)); | |
|
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|
10028 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" |
| 0 | 10029 format %{ "DTAN $dst" %} |
|
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|
10030 ins_encode( Push_SrcD(dst), |
| 0 | 10031 Opcode(0xD9), Opcode(0xF2), // fptan |
| 10032 Opcode(0xDD), Opcode(0xD8), // fstp st | |
|
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|
10033 Push_ResultD(dst) ); |
|
65149e74c706
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|
10034 ins_pipe( pipe_slow ); |
|
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|
10035 %} |
|
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|
10036 |
|
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|
10037 instruct atanDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 10038 predicate (UseSSE<=1); |
| 10039 match(Set dst(AtanD dst src)); | |
| 10040 format %{ "DATA $dst,$src" %} | |
| 10041 opcode(0xD9, 0xF3); | |
|
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|
10042 ins_encode( Push_Reg_DPR(src), |
| 0 | 10043 OpcP, OpcS, RegOpc(dst) ); |
| 10044 ins_pipe( pipe_slow ); | |
| 10045 %} | |
| 10046 | |
|
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|
10047 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{ |
| 0 | 10048 predicate (UseSSE>=2); |
| 10049 match(Set dst(AtanD dst src)); | |
|
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|
10050 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" |
| 0 | 10051 format %{ "DATA $dst,$src" %} |
| 10052 opcode(0xD9, 0xF3); | |
|
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|
10053 ins_encode( Push_SrcD(src), |
|
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|
10054 OpcP, OpcS, Push_ResultD(dst) ); |
|
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|
10055 ins_pipe( pipe_slow ); |
|
65149e74c706
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|
10056 %} |
|
65149e74c706
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changeset
|
10057 |
|
65149e74c706
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|
10058 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{ |
| 0 | 10059 predicate (UseSSE<=1); |
| 10060 match(Set dst (SqrtD src)); | |
| 10061 format %{ "DSQRT $dst,$src" %} | |
| 10062 opcode(0xFA, 0xD9); | |
|
4761
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|
10063 ins_encode( Push_Reg_DPR(src), |
|
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|
10064 OpcS, OpcP, Pop_Reg_DPR(dst) ); |
|
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|
10065 ins_pipe( pipe_slow ); |
|
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|
10066 %} |
|
65149e74c706
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changeset
|
10067 |
|
6084
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|
10068 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
| 0 | 10069 predicate (UseSSE<=1); |
| 10070 match(Set Y (PowD X Y)); // Raise X to the Yth power | |
|
6084
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|
10071 effect(KILL rax, KILL rdx, KILL rcx, KILL cr); |
|
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|
10072 format %{ "fast_pow $X $Y -> $Y // KILL $rax, $rcx, $rdx" %} |
|
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|
10073 ins_encode %{ |
|
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|
10074 __ subptr(rsp, 8); |
|
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|
10075 __ fld_s($X$$reg - 1); |
|
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|
10076 __ fast_pow(); |
|
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|
10077 __ addptr(rsp, 8); |
|
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|
10078 %} |
|
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changeset
|
10079 ins_pipe( pipe_slow ); |
|
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|
10080 %} |
|
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|
10081 |
|
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|
10082 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
| 0 | 10083 predicate (UseSSE>=2); |
| 10084 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power | |
|
6084
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|
10085 effect(KILL rax, KILL rdx, KILL rcx, KILL cr); |
|
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|
10086 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %} |
|
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|
10087 ins_encode %{ |
|
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|
10088 __ subptr(rsp, 8); |
|
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|
10089 __ movdbl(Address(rsp, 0), $src1$$XMMRegister); |
|
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|
10090 __ fld_d(Address(rsp, 0)); |
|
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|
10091 __ movdbl(Address(rsp, 0), $src0$$XMMRegister); |
|
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|
10092 __ fld_d(Address(rsp, 0)); |
|
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changeset
|
10093 __ fast_pow(); |
|
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|
10094 __ fstp_d(Address(rsp, 0)); |
|
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|
10095 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); |
|
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|
10096 __ addptr(rsp, 8); |
|
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changeset
|
10097 %} |
|
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changeset
|
10098 ins_pipe( pipe_slow ); |
|
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changeset
|
10099 %} |
|
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changeset
|
10100 |
|
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changeset
|
10101 |
|
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|
10102 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
| 0 | 10103 predicate (UseSSE<=1); |
| 10104 match(Set dpr1 (ExpD dpr1)); | |
|
6084
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|
10105 effect(KILL rax, KILL rcx, KILL rdx, KILL cr); |
|
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10106 format %{ "fast_exp $dpr1 -> $dpr1 // KILL $rax, $rcx, $rdx" %} |
|
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changeset
|
10107 ins_encode %{ |
|
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|
10108 __ fast_exp(); |
|
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|
10109 %} |
|
6759698e3140
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|
10110 ins_pipe( pipe_slow ); |
|
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|
10111 %} |
|
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|
10112 |
|
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|
10113 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ |
| 0 | 10114 predicate (UseSSE>=2); |
| 10115 match(Set dst (ExpD src)); | |
|
6084
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changeset
|
10116 effect(KILL rax, KILL rcx, KILL rdx, KILL cr); |
|
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|
10117 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %} |
|
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changeset
|
10118 ins_encode %{ |
|
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|
10119 __ subptr(rsp, 8); |
|
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|
10120 __ movdbl(Address(rsp, 0), $src$$XMMRegister); |
|
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|
10121 __ fld_d(Address(rsp, 0)); |
|
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|
10122 __ fast_exp(); |
|
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|
10123 __ fstp_d(Address(rsp, 0)); |
|
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|
10124 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); |
|
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|
10125 __ addptr(rsp, 8); |
|
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|
10126 %} |
|
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changeset
|
10127 ins_pipe( pipe_slow ); |
|
6759698e3140
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10128 %} |
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10129 |
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10130 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 10131 predicate (UseSSE<=1); |
| 10132 // The source Double operand on FPU stack | |
| 10133 match(Set dst (Log10D src)); | |
| 10134 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
| 10135 // fxch ; swap ST(0) with ST(1) | |
| 10136 // fyl2x ; compute log_10(2) * log_2(x) | |
| 10137 format %{ "FLDLG2 \t\t\t#Log10\n\t" | |
| 10138 "FXCH \n\t" | |
| 10139 "FYL2X \t\t\t# Q=Log10*Log_2(x)" | |
| 10140 %} | |
| 10141 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
| 10142 Opcode(0xD9), Opcode(0xC9), // fxch | |
| 10143 Opcode(0xD9), Opcode(0xF1)); // fyl2x | |
| 10144 | |
| 10145 ins_pipe( pipe_slow ); | |
| 10146 %} | |
| 10147 | |
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10148 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{ |
| 0 | 10149 predicate (UseSSE>=2); |
| 10150 effect(KILL cr); | |
| 10151 match(Set dst (Log10D src)); | |
| 10152 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
| 10153 // fyl2x ; compute log_10(2) * log_2(x) | |
| 10154 format %{ "FLDLG2 \t\t\t#Log10\n\t" | |
| 10155 "FYL2X \t\t\t# Q=Log10*Log_2(x)" | |
| 10156 %} | |
| 10157 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
|
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10158 Push_SrcD(src), |
| 0 | 10159 Opcode(0xD9), Opcode(0xF1), // fyl2x |
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10160 Push_ResultD(dst)); |
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10161 |
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10162 ins_pipe( pipe_slow ); |
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10163 %} |
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10164 |
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10165 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{ |
| 0 | 10166 predicate (UseSSE<=1); |
| 10167 // The source Double operand on FPU stack | |
| 10168 match(Set dst (LogD src)); | |
| 10169 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
| 10170 // fxch ; swap ST(0) with ST(1) | |
| 10171 // fyl2x ; compute log_e(2) * log_2(x) | |
| 10172 format %{ "FLDLN2 \t\t\t#Log_e\n\t" | |
| 10173 "FXCH \n\t" | |
| 10174 "FYL2X \t\t\t# Q=Log_e*Log_2(x)" | |
| 10175 %} | |
| 10176 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
| 10177 Opcode(0xD9), Opcode(0xC9), // fxch | |
| 10178 Opcode(0xD9), Opcode(0xF1)); // fyl2x | |
| 10179 | |
| 10180 ins_pipe( pipe_slow ); | |
| 10181 %} | |
| 10182 | |
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10183 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{ |
| 0 | 10184 predicate (UseSSE>=2); |
| 10185 effect(KILL cr); | |
| 10186 // The source and result Double operands in XMM registers | |
| 10187 match(Set dst (LogD src)); | |
| 10188 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
| 10189 // fyl2x ; compute log_e(2) * log_2(x) | |
| 10190 format %{ "FLDLN2 \t\t\t#Log_e\n\t" | |
| 10191 "FYL2X \t\t\t# Q=Log_e*Log_2(x)" | |
| 10192 %} | |
| 10193 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
|
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10194 Push_SrcD(src), |
| 0 | 10195 Opcode(0xD9), Opcode(0xF1), // fyl2x |
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10196 Push_ResultD(dst)); |
| 0 | 10197 ins_pipe( pipe_slow ); |
| 10198 %} | |
| 10199 | |
| 10200 //-------------Float Instructions------------------------------- | |
| 10201 // Float Math | |
| 10202 | |
| 10203 // Code for float compare: | |
| 10204 // fcompp(); | |
| 10205 // fwait(); fnstsw_ax(); | |
| 10206 // sahf(); | |
| 10207 // movl(dst, unordered_result); | |
| 10208 // jcc(Assembler::parity, exit); | |
| 10209 // movl(dst, less_result); | |
| 10210 // jcc(Assembler::below, exit); | |
| 10211 // movl(dst, equal_result); | |
| 10212 // jcc(Assembler::equal, exit); | |
| 10213 // movl(dst, greater_result); | |
| 10214 // exit: | |
| 10215 | |
| 10216 // P6 version of float compare, sets condition codes in EFLAGS | |
|
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10217 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{ |
| 0 | 10218 predicate(VM_Version::supports_cmov() && UseSSE == 0); |
| 10219 match(Set cr (CmpF src1 src2)); | |
| 10220 effect(KILL rax); | |
| 10221 ins_cost(150); | |
| 10222 format %{ "FLD $src1\n\t" | |
| 10223 "FUCOMIP ST,$src2 // P6 instruction\n\t" | |
| 10224 "JNP exit\n\t" | |
| 10225 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t" | |
| 10226 "SAHF\n" | |
| 10227 "exit:\tNOP // avoid branch to branch" %} | |
| 10228 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ | |
|
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10229 ins_encode( Push_Reg_DPR(src1), |
| 0 | 10230 OpcP, RegOpc(src2), |
| 10231 cmpF_P6_fixup ); | |
| 10232 ins_pipe( pipe_slow ); | |
| 10233 %} | |
| 10234 | |
|
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10235 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{ |
|
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10236 predicate(VM_Version::supports_cmov() && UseSSE == 0); |
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10237 match(Set cr (CmpF src1 src2)); |
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10238 ins_cost(100); |
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10239 format %{ "FLD $src1\n\t" |
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10240 "FUCOMIP ST,$src2 // P6 instruction" %} |
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10241 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ |
|
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10242 ins_encode( Push_Reg_DPR(src1), |
|
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10243 OpcP, RegOpc(src2)); |
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10244 ins_pipe( pipe_slow ); |
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10245 %} |
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10246 |
| 0 | 10247 |
| 10248 // Compare & branch | |
|
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10249 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{ |
| 0 | 10250 predicate(UseSSE == 0); |
| 10251 match(Set cr (CmpF src1 src2)); | |
| 10252 effect(KILL rax); | |
| 10253 ins_cost(200); | |
| 10254 format %{ "FLD $src1\n\t" | |
| 10255 "FCOMp $src2\n\t" | |
| 10256 "FNSTSW AX\n\t" | |
| 10257 "TEST AX,0x400\n\t" | |
| 10258 "JZ,s flags\n\t" | |
| 10259 "MOV AH,1\t# unordered treat as LT\n" | |
| 10260 "flags:\tSAHF" %} | |
| 10261 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
|
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10262 ins_encode( Push_Reg_DPR(src1), |
| 0 | 10263 OpcP, RegOpc(src2), |
| 10264 fpu_flags); | |
| 10265 ins_pipe( pipe_slow ); | |
| 10266 %} | |
| 10267 | |
| 10268 // Compare vs zero into -1,0,1 | |
|
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10269 instruct cmpFPR_0(eRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10270 predicate(UseSSE == 0); |
| 10271 match(Set dst (CmpF3 src1 zero)); | |
| 10272 effect(KILL cr, KILL rax); | |
| 10273 ins_cost(280); | |
| 10274 format %{ "FTSTF $dst,$src1" %} | |
| 10275 opcode(0xE4, 0xD9); | |
|
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10276 ins_encode( Push_Reg_DPR(src1), |
| 0 | 10277 OpcS, OpcP, PopFPU, |
| 10278 CmpF_Result(dst)); | |
| 10279 ins_pipe( pipe_slow ); | |
| 10280 %} | |
| 10281 | |
| 10282 // Compare into -1,0,1 | |
|
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10283 instruct cmpFPR_reg(eRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10284 predicate(UseSSE == 0); |
| 10285 match(Set dst (CmpF3 src1 src2)); | |
| 10286 effect(KILL cr, KILL rax); | |
| 10287 ins_cost(300); | |
| 10288 format %{ "FCMPF $dst,$src1,$src2" %} | |
| 10289 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ | |
|
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10290 ins_encode( Push_Reg_DPR(src1), |
| 0 | 10291 OpcP, RegOpc(src2), |
| 10292 CmpF_Result(dst)); | |
| 10293 ins_pipe( pipe_slow ); | |
| 10294 %} | |
| 10295 | |
| 10296 // float compare and set condition codes in EFLAGS by XMM regs | |
|
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10297 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{ |
| 0 | 10298 predicate(UseSSE>=1); |
| 4759 | 10299 match(Set cr (CmpF src1 src2)); |
| 0 | 10300 ins_cost(145); |
| 4759 | 10301 format %{ "UCOMISS $src1,$src2\n\t" |
| 10302 "JNP,s exit\n\t" | |
| 10303 "PUSHF\t# saw NaN, set CF\n\t" | |
| 10304 "AND [rsp], #0xffffff2b\n\t" | |
| 10305 "POPF\n" | |
| 10306 "exit:" %} | |
| 10307 ins_encode %{ | |
| 10308 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 10309 emit_cmpfp_fixup(_masm); | |
| 10310 %} | |
| 10311 ins_pipe( pipe_slow ); | |
| 10312 %} | |
| 10313 | |
|
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10314 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{ |
|
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10315 predicate(UseSSE>=1); |
| 4759 | 10316 match(Set cr (CmpF src1 src2)); |
|
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10317 ins_cost(100); |
| 4759 | 10318 format %{ "UCOMISS $src1,$src2" %} |
| 10319 ins_encode %{ | |
| 10320 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 10321 %} | |
|
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10322 ins_pipe( pipe_slow ); |
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|
10323 %} |
|
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|
10324 |
| 0 | 10325 // float compare and set condition codes in EFLAGS by XMM regs |
|
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10326 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{ |
| 0 | 10327 predicate(UseSSE>=1); |
| 4759 | 10328 match(Set cr (CmpF src1 (LoadF src2))); |
| 0 | 10329 ins_cost(165); |
| 4759 | 10330 format %{ "UCOMISS $src1,$src2\n\t" |
| 10331 "JNP,s exit\n\t" | |
| 10332 "PUSHF\t# saw NaN, set CF\n\t" | |
| 10333 "AND [rsp], #0xffffff2b\n\t" | |
| 10334 "POPF\n" | |
| 10335 "exit:" %} | |
| 10336 ins_encode %{ | |
| 10337 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 10338 emit_cmpfp_fixup(_masm); | |
| 10339 %} | |
| 10340 ins_pipe( pipe_slow ); | |
| 10341 %} | |
| 10342 | |
|
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10343 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{ |
|
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10344 predicate(UseSSE>=1); |
| 4759 | 10345 match(Set cr (CmpF src1 (LoadF src2))); |
|
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10346 ins_cost(100); |
| 4759 | 10347 format %{ "UCOMISS $src1,$src2" %} |
| 10348 ins_encode %{ | |
| 10349 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 10350 %} | |
|
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10351 ins_pipe( pipe_slow ); |
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|
10352 %} |
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|
10353 |
| 0 | 10354 // Compare into -1,0,1 in XMM |
|
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10355 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{ |
| 0 | 10356 predicate(UseSSE>=1); |
| 10357 match(Set dst (CmpF3 src1 src2)); | |
| 10358 effect(KILL cr); | |
| 10359 ins_cost(255); | |
| 4759 | 10360 format %{ "UCOMISS $src1, $src2\n\t" |
| 10361 "MOV $dst, #-1\n\t" | |
| 10362 "JP,s done\n\t" | |
| 10363 "JB,s done\n\t" | |
| 10364 "SETNE $dst\n\t" | |
| 10365 "MOVZB $dst, $dst\n" | |
| 10366 "done:" %} | |
| 10367 ins_encode %{ | |
| 10368 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); | |
| 10369 emit_cmpfp3(_masm, $dst$$Register); | |
| 10370 %} | |
| 0 | 10371 ins_pipe( pipe_slow ); |
| 10372 %} | |
| 10373 | |
| 10374 // Compare into -1,0,1 in XMM and memory | |
|
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10375 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{ |
| 0 | 10376 predicate(UseSSE>=1); |
| 4759 | 10377 match(Set dst (CmpF3 src1 (LoadF src2))); |
| 0 | 10378 effect(KILL cr); |
| 10379 ins_cost(275); | |
| 4759 | 10380 format %{ "UCOMISS $src1, $src2\n\t" |
| 10381 "MOV $dst, #-1\n\t" | |
| 10382 "JP,s done\n\t" | |
| 10383 "JB,s done\n\t" | |
| 10384 "SETNE $dst\n\t" | |
| 10385 "MOVZB $dst, $dst\n" | |
| 10386 "done:" %} | |
| 10387 ins_encode %{ | |
| 10388 __ ucomiss($src1$$XMMRegister, $src2$$Address); | |
| 10389 emit_cmpfp3(_masm, $dst$$Register); | |
| 10390 %} | |
| 0 | 10391 ins_pipe( pipe_slow ); |
| 10392 %} | |
| 10393 | |
| 10394 // Spill to obtain 24-bit precision | |
|
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10395 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ |
| 0 | 10396 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10397 match(Set dst (SubF src1 src2)); | |
| 10398 | |
| 10399 format %{ "FSUB $dst,$src1 - $src2" %} | |
| 10400 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */ | |
|
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10401 ins_encode( Push_Reg_FPR(src1), |
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10402 OpcReg_FPR(src2), |
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10403 Pop_Mem_FPR(dst) ); |
| 0 | 10404 ins_pipe( fpu_mem_reg_reg ); |
| 10405 %} | |
| 10406 // | |
| 10407 // This instruction does not round to 24-bits | |
|
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10408 instruct subFPR_reg(regFPR dst, regFPR src) %{ |
| 0 | 10409 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10410 match(Set dst (SubF dst src)); | |
| 10411 | |
| 10412 format %{ "FSUB $dst,$src" %} | |
| 10413 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */ | |
|
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10414 ins_encode( Push_Reg_FPR(src), |
| 0 | 10415 OpcP, RegOpc(dst) ); |
| 10416 ins_pipe( fpu_reg_reg ); | |
| 10417 %} | |
| 10418 | |
| 10419 // Spill to obtain 24-bit precision | |
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10420 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ |
| 0 | 10421 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10422 match(Set dst (AddF src1 src2)); | |
| 10423 | |
| 10424 format %{ "FADD $dst,$src1,$src2" %} | |
| 10425 opcode(0xD8, 0x0); /* D8 C0+i */ | |
|
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10426 ins_encode( Push_Reg_FPR(src2), |
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10427 OpcReg_FPR(src1), |
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10428 Pop_Mem_FPR(dst) ); |
| 0 | 10429 ins_pipe( fpu_mem_reg_reg ); |
| 10430 %} | |
| 10431 // | |
| 10432 // This instruction does not round to 24-bits | |
|
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10433 instruct addFPR_reg(regFPR dst, regFPR src) %{ |
| 0 | 10434 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10435 match(Set dst (AddF dst src)); | |
| 10436 | |
| 10437 format %{ "FLD $src\n\t" | |
| 10438 "FADDp $dst,ST" %} | |
| 10439 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/ | |
|
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10440 ins_encode( Push_Reg_FPR(src), |
| 0 | 10441 OpcP, RegOpc(dst) ); |
| 10442 ins_pipe( fpu_reg_reg ); | |
| 10443 %} | |
| 10444 | |
|
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10445 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{ |
| 0 | 10446 predicate(UseSSE==0); |
| 10447 match(Set dst (AbsF src)); | |
| 10448 ins_cost(100); | |
| 10449 format %{ "FABS" %} | |
| 10450 opcode(0xE1, 0xD9); | |
| 10451 ins_encode( OpcS, OpcP ); | |
| 10452 ins_pipe( fpu_reg_reg ); | |
| 10453 %} | |
| 10454 | |
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10455 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{ |
| 0 | 10456 predicate(UseSSE==0); |
| 10457 match(Set dst (NegF src)); | |
| 10458 ins_cost(100); | |
| 10459 format %{ "FCHS" %} | |
| 10460 opcode(0xE0, 0xD9); | |
| 10461 ins_encode( OpcS, OpcP ); | |
| 10462 ins_pipe( fpu_reg_reg ); | |
| 10463 %} | |
| 10464 | |
|
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10465 // Cisc-alternate to addFPR_reg |
| 0 | 10466 // Spill to obtain 24-bit precision |
|
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10467 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{ |
| 0 | 10468 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10469 match(Set dst (AddF src1 (LoadF src2))); | |
| 10470 | |
| 10471 format %{ "FLD $src2\n\t" | |
| 10472 "FADD ST,$src1\n\t" | |
| 10473 "FSTP_S $dst" %} | |
| 10474 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 10475 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
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10476 OpcReg_FPR(src1), |
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10477 Pop_Mem_FPR(dst) ); |
| 0 | 10478 ins_pipe( fpu_mem_reg_mem ); |
| 10479 %} | |
| 10480 // | |
|
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10481 // Cisc-alternate to addFPR_reg |
| 0 | 10482 // This instruction does not round to 24-bits |
|
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10483 instruct addFPR_reg_mem(regFPR dst, memory src) %{ |
| 0 | 10484 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10485 match(Set dst (AddF dst (LoadF src))); | |
| 10486 | |
| 10487 format %{ "FADD $dst,$src" %} | |
| 10488 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */ | |
| 10489 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), | |
| 10490 OpcP, RegOpc(dst) ); | |
| 10491 ins_pipe( fpu_reg_mem ); | |
| 10492 %} | |
| 10493 | |
| 10494 // // Following two instructions for _222_mpegaudio | |
| 10495 // Spill to obtain 24-bit precision | |
|
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10496 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{ |
| 0 | 10497 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10498 match(Set dst (AddF src1 src2)); | |
| 10499 | |
| 10500 format %{ "FADD $dst,$src1,$src2" %} | |
| 10501 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 10502 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1), | |
|
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10503 OpcReg_FPR(src2), |
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10504 Pop_Mem_FPR(dst) ); |
| 0 | 10505 ins_pipe( fpu_mem_reg_mem ); |
| 10506 %} | |
| 10507 | |
| 10508 // Cisc-spill variant | |
| 10509 // Spill to obtain 24-bit precision | |
|
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10510 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{ |
| 0 | 10511 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10512 match(Set dst (AddF src1 (LoadF src2))); | |
| 10513 | |
| 10514 format %{ "FADD $dst,$src1,$src2 cisc" %} | |
| 10515 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ | |
| 10516 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 10517 set_instruction_start, | |
| 10518 OpcP, RMopc_Mem(secondary,src1), | |
|
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10519 Pop_Mem_FPR(dst) ); |
| 0 | 10520 ins_pipe( fpu_mem_mem_mem ); |
| 10521 %} | |
| 10522 | |
| 10523 // Spill to obtain 24-bit precision | |
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10524 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{ |
| 0 | 10525 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10526 match(Set dst (AddF src1 src2)); | |
| 10527 | |
| 10528 format %{ "FADD $dst,$src1,$src2" %} | |
| 10529 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */ | |
| 10530 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 10531 set_instruction_start, | |
| 10532 OpcP, RMopc_Mem(secondary,src1), | |
|
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10533 Pop_Mem_FPR(dst) ); |
| 0 | 10534 ins_pipe( fpu_mem_mem_mem ); |
| 10535 %} | |
| 10536 | |
| 10537 | |
| 10538 // Spill to obtain 24-bit precision | |
|
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10539 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{ |
| 0 | 10540 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 2008 | 10541 match(Set dst (AddF src con)); |
| 10542 format %{ "FLD $src\n\t" | |
| 10543 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 0 | 10544 "FSTP_S $dst" %} |
| 2008 | 10545 ins_encode %{ |
| 10546 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 10547 __ fadd_s($constantaddress($con)); | |
| 10548 __ fstp_s(Address(rsp, $dst$$disp)); | |
| 10549 %} | |
| 10550 ins_pipe(fpu_mem_reg_con); | |
| 0 | 10551 %} |
| 10552 // | |
| 10553 // This instruction does not round to 24-bits | |
|
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10554 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{ |
| 0 | 10555 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 2008 | 10556 match(Set dst (AddF src con)); |
| 10557 format %{ "FLD $src\n\t" | |
| 10558 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 10559 "FSTP $dst" %} | |
| 10560 ins_encode %{ | |
| 10561 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 10562 __ fadd_s($constantaddress($con)); | |
| 10563 __ fstp_d($dst$$reg); | |
| 10564 %} | |
| 10565 ins_pipe(fpu_reg_reg_con); | |
| 0 | 10566 %} |
| 10567 | |
| 10568 // Spill to obtain 24-bit precision | |
|
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10569 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ |
| 0 | 10570 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10571 match(Set dst (MulF src1 src2)); | |
| 10572 | |
| 10573 format %{ "FLD $src1\n\t" | |
| 10574 "FMUL $src2\n\t" | |
| 10575 "FSTP_S $dst" %} | |
| 10576 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */ | |
|
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10577 ins_encode( Push_Reg_FPR(src1), |
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10578 OpcReg_FPR(src2), |
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10579 Pop_Mem_FPR(dst) ); |
| 0 | 10580 ins_pipe( fpu_mem_reg_reg ); |
| 10581 %} | |
| 10582 // | |
| 10583 // This instruction does not round to 24-bits | |
|
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10584 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{ |
| 0 | 10585 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10586 match(Set dst (MulF src1 src2)); | |
| 10587 | |
| 10588 format %{ "FLD $src1\n\t" | |
| 10589 "FMUL $src2\n\t" | |
| 10590 "FSTP_S $dst" %} | |
| 10591 opcode(0xD8, 0x1); /* D8 C8+i */ | |
|
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10592 ins_encode( Push_Reg_FPR(src2), |
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10593 OpcReg_FPR(src1), |
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10594 Pop_Reg_FPR(dst) ); |
| 0 | 10595 ins_pipe( fpu_reg_reg_reg ); |
| 10596 %} | |
| 10597 | |
| 10598 | |
| 10599 // Spill to obtain 24-bit precision | |
| 10600 // Cisc-alternate to reg-reg multiply | |
|
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10601 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{ |
| 0 | 10602 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10603 match(Set dst (MulF src1 (LoadF src2))); | |
| 10604 | |
| 10605 format %{ "FLD_S $src2\n\t" | |
| 10606 "FMUL $src1\n\t" | |
| 10607 "FSTP_S $dst" %} | |
| 10608 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */ | |
| 10609 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
|
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10610 OpcReg_FPR(src1), |
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10611 Pop_Mem_FPR(dst) ); |
| 0 | 10612 ins_pipe( fpu_mem_reg_mem ); |
| 10613 %} | |
| 10614 // | |
| 10615 // This instruction does not round to 24-bits | |
| 10616 // Cisc-alternate to reg-reg multiply | |
|
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10617 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{ |
| 0 | 10618 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10619 match(Set dst (MulF src1 (LoadF src2))); | |
| 10620 | |
| 10621 format %{ "FMUL $dst,$src1,$src2" %} | |
| 10622 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */ | |
| 10623 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
|
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10624 OpcReg_FPR(src1), |
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10625 Pop_Reg_FPR(dst) ); |
| 0 | 10626 ins_pipe( fpu_reg_reg_mem ); |
| 10627 %} | |
| 10628 | |
| 10629 // Spill to obtain 24-bit precision | |
|
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10630 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{ |
| 0 | 10631 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10632 match(Set dst (MulF src1 src2)); | |
| 10633 | |
| 10634 format %{ "FMUL $dst,$src1,$src2" %} | |
| 10635 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */ | |
| 10636 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), | |
| 10637 set_instruction_start, | |
| 10638 OpcP, RMopc_Mem(secondary,src1), | |
|
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10639 Pop_Mem_FPR(dst) ); |
| 0 | 10640 ins_pipe( fpu_mem_mem_mem ); |
| 10641 %} | |
| 10642 | |
| 10643 // Spill to obtain 24-bit precision | |
|
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10644 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{ |
| 0 | 10645 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 2008 | 10646 match(Set dst (MulF src con)); |
| 10647 | |
| 10648 format %{ "FLD $src\n\t" | |
| 10649 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 10650 "FSTP_S $dst" %} | |
| 10651 ins_encode %{ | |
| 10652 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 10653 __ fmul_s($constantaddress($con)); | |
| 10654 __ fstp_s(Address(rsp, $dst$$disp)); | |
| 10655 %} | |
| 10656 ins_pipe(fpu_mem_reg_con); | |
| 0 | 10657 %} |
| 10658 // | |
| 10659 // This instruction does not round to 24-bits | |
|
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10660 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{ |
| 0 | 10661 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 2008 | 10662 match(Set dst (MulF src con)); |
| 10663 | |
| 10664 format %{ "FLD $src\n\t" | |
| 10665 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t" | |
| 10666 "FSTP $dst" %} | |
| 10667 ins_encode %{ | |
| 10668 __ fld_s($src$$reg - 1); // FLD ST(i-1) | |
| 10669 __ fmul_s($constantaddress($con)); | |
| 10670 __ fstp_d($dst$$reg); | |
| 10671 %} | |
| 10672 ins_pipe(fpu_reg_reg_con); | |
| 0 | 10673 %} |
| 10674 | |
| 10675 | |
| 10676 // | |
|
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10677 // MACRO1 -- subsume unshared load into mulFPR |
| 0 | 10678 // This instruction does not round to 24-bits |
|
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10679 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{ |
| 0 | 10680 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10681 match(Set dst (MulF (LoadF mem1) src)); | |
| 10682 | |
| 10683 format %{ "FLD $mem1 ===MACRO1===\n\t" | |
| 10684 "FMUL ST,$src\n\t" | |
| 10685 "FSTP $dst" %} | |
| 10686 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */ | |
| 10687 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1), | |
|
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10688 OpcReg_FPR(src), |
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10689 Pop_Reg_FPR(dst) ); |
| 0 | 10690 ins_pipe( fpu_reg_reg_mem ); |
| 10691 %} | |
| 10692 // | |
|
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10693 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load |
| 0 | 10694 // This instruction does not round to 24-bits |
|
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10695 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{ |
| 0 | 10696 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10697 match(Set dst (AddF (MulF (LoadF mem1) src1) src2)); | |
| 10698 ins_cost(95); | |
| 10699 | |
| 10700 format %{ "FLD $mem1 ===MACRO2===\n\t" | |
|
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10701 "FMUL ST,$src1 subsume mulFPR left load\n\t" |
| 0 | 10702 "FADD ST,$src2\n\t" |
| 10703 "FSTP $dst" %} | |
| 10704 opcode(0xD9); /* LoadF D9 /0 */ | |
| 10705 ins_encode( OpcP, RMopc_Mem(0x00,mem1), | |
| 10706 FMul_ST_reg(src1), | |
| 10707 FAdd_ST_reg(src2), | |
|
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10708 Pop_Reg_FPR(dst) ); |
| 0 | 10709 ins_pipe( fpu_reg_mem_reg_reg ); |
| 10710 %} | |
| 10711 | |
|
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10712 // MACRO3 -- addFPR a mulFPR |
| 0 | 10713 // This instruction does not round to 24-bits. It is a '2-address' |
| 10714 // instruction in that the result goes back to src2. This eliminates | |
| 10715 // a move from the macro; possibly the register allocator will have | |
| 10716 // to add it back (and maybe not). | |
|
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10717 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{ |
| 0 | 10718 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10719 match(Set src2 (AddF (MulF src0 src1) src2)); | |
| 10720 | |
| 10721 format %{ "FLD $src0 ===MACRO3===\n\t" | |
| 10722 "FMUL ST,$src1\n\t" | |
| 10723 "FADDP $src2,ST" %} | |
| 10724 opcode(0xD9); /* LoadF D9 /0 */ | |
|
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10725 ins_encode( Push_Reg_FPR(src0), |
| 0 | 10726 FMul_ST_reg(src1), |
| 10727 FAddP_reg_ST(src2) ); | |
| 10728 ins_pipe( fpu_reg_reg_reg ); | |
| 10729 %} | |
| 10730 | |
|
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10731 // MACRO4 -- divFPR subFPR |
| 0 | 10732 // This instruction does not round to 24-bits |
|
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10733 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{ |
| 0 | 10734 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10735 match(Set dst (DivF (SubF src2 src1) src3)); | |
| 10736 | |
| 10737 format %{ "FLD $src2 ===MACRO4===\n\t" | |
| 10738 "FSUB ST,$src1\n\t" | |
| 10739 "FDIV ST,$src3\n\t" | |
| 10740 "FSTP $dst" %} | |
| 10741 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
|
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10742 ins_encode( Push_Reg_FPR(src2), |
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10743 subFPR_divFPR_encode(src1,src3), |
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10744 Pop_Reg_FPR(dst) ); |
| 0 | 10745 ins_pipe( fpu_reg_reg_reg_reg ); |
| 10746 %} | |
| 10747 | |
| 10748 // Spill to obtain 24-bit precision | |
|
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10749 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ |
| 0 | 10750 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10751 match(Set dst (DivF src1 src2)); | |
| 10752 | |
| 10753 format %{ "FDIV $dst,$src1,$src2" %} | |
| 10754 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/ | |
|
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10755 ins_encode( Push_Reg_FPR(src1), |
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10756 OpcReg_FPR(src2), |
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10757 Pop_Mem_FPR(dst) ); |
| 0 | 10758 ins_pipe( fpu_mem_reg_reg ); |
| 10759 %} | |
| 10760 // | |
| 10761 // This instruction does not round to 24-bits | |
|
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10762 instruct divFPR_reg(regFPR dst, regFPR src) %{ |
| 0 | 10763 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10764 match(Set dst (DivF dst src)); | |
| 10765 | |
| 10766 format %{ "FDIV $dst,$src" %} | |
| 10767 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ | |
|
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10768 ins_encode( Push_Reg_FPR(src), |
| 0 | 10769 OpcP, RegOpc(dst) ); |
| 10770 ins_pipe( fpu_reg_reg ); | |
| 10771 %} | |
| 10772 | |
| 10773 | |
| 10774 // Spill to obtain 24-bit precision | |
|
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10775 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10776 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 10777 match(Set dst (ModF src1 src2)); | |
|
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10778 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS |
| 0 | 10779 |
| 10780 format %{ "FMOD $dst,$src1,$src2" %} | |
|
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10781 ins_encode( Push_Reg_Mod_DPR(src1, src2), |
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10782 emitModDPR(), |
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10783 Push_Result_Mod_DPR(src2), |
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10784 Pop_Mem_FPR(dst)); |
| 0 | 10785 ins_pipe( pipe_slow ); |
| 10786 %} | |
| 10787 // | |
| 10788 // This instruction does not round to 24-bits | |
|
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10789 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10790 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 10791 match(Set dst (ModF dst src)); | |
|
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10792 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS |
| 0 | 10793 |
| 10794 format %{ "FMOD $dst,$src" %} | |
|
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10795 ins_encode(Push_Reg_Mod_DPR(dst, src), |
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10796 emitModDPR(), |
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10797 Push_Result_Mod_DPR(src), |
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10798 Pop_Reg_FPR(dst)); |
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10799 ins_pipe( pipe_slow ); |
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10800 %} |
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10801 |
|
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10802 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{ |
| 0 | 10803 predicate(UseSSE>=1); |
| 10804 match(Set dst (ModF src0 src1)); | |
| 10805 effect(KILL rax, KILL cr); | |
| 10806 format %{ "SUB ESP,4\t # FMOD\n" | |
| 10807 "\tMOVSS [ESP+0],$src1\n" | |
| 10808 "\tFLD_S [ESP+0]\n" | |
| 10809 "\tMOVSS [ESP+0],$src0\n" | |
| 10810 "\tFLD_S [ESP+0]\n" | |
| 10811 "loop:\tFPREM\n" | |
| 10812 "\tFWAIT\n" | |
| 10813 "\tFNSTSW AX\n" | |
| 10814 "\tSAHF\n" | |
| 10815 "\tJP loop\n" | |
| 10816 "\tFSTP_S [ESP+0]\n" | |
| 10817 "\tMOVSS $dst,[ESP+0]\n" | |
| 10818 "\tADD ESP,4\n" | |
| 10819 "\tFSTP ST0\t # Restore FPU Stack" | |
| 10820 %} | |
| 10821 ins_cost(250); | |
|
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10822 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU); |
| 0 | 10823 ins_pipe( pipe_slow ); |
| 10824 %} | |
| 10825 | |
| 10826 | |
| 10827 //----------Arithmetic Conversion Instructions--------------------------------- | |
| 10828 // The conversions operations are all Alpha sorted. Please keep it that way! | |
| 10829 | |
|
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10830 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{ |
| 0 | 10831 predicate(UseSSE==0); |
| 10832 match(Set dst (RoundFloat src)); | |
| 10833 ins_cost(125); | |
| 10834 format %{ "FST_S $dst,$src\t# F-round" %} | |
|
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10835 ins_encode( Pop_Mem_Reg_FPR(dst, src) ); |
| 0 | 10836 ins_pipe( fpu_mem_reg ); |
| 10837 %} | |
| 10838 | |
|
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10839 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{ |
| 0 | 10840 predicate(UseSSE<=1); |
| 10841 match(Set dst (RoundDouble src)); | |
| 10842 ins_cost(125); | |
| 10843 format %{ "FST_D $dst,$src\t# D-round" %} | |
|
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10844 ins_encode( Pop_Mem_Reg_DPR(dst, src) ); |
| 0 | 10845 ins_pipe( fpu_mem_reg ); |
| 10846 %} | |
| 10847 | |
| 10848 // Force rounding to 24-bit precision and 6-bit exponent | |
|
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10849 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{ |
| 0 | 10850 predicate(UseSSE==0); |
| 10851 match(Set dst (ConvD2F src)); | |
| 10852 format %{ "FST_S $dst,$src\t# F-round" %} | |
| 10853 expand %{ | |
| 10854 roundFloat_mem_reg(dst,src); | |
| 10855 %} | |
| 10856 %} | |
| 10857 | |
| 10858 // Force rounding to 24-bit precision and 6-bit exponent | |
|
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10859 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{ |
| 0 | 10860 predicate(UseSSE==1); |
| 10861 match(Set dst (ConvD2F src)); | |
| 10862 effect( KILL cr ); | |
| 10863 format %{ "SUB ESP,4\n\t" | |
| 10864 "FST_S [ESP],$src\t# F-round\n\t" | |
| 10865 "MOVSS $dst,[ESP]\n\t" | |
| 10866 "ADD ESP,4" %} | |
| 4759 | 10867 ins_encode %{ |
| 10868 __ subptr(rsp, 4); | |
| 10869 if ($src$$reg != FPR1L_enc) { | |
| 10870 __ fld_s($src$$reg-1); | |
| 10871 __ fstp_s(Address(rsp, 0)); | |
| 10872 } else { | |
| 10873 __ fst_s(Address(rsp, 0)); | |
| 10874 } | |
| 10875 __ movflt($dst$$XMMRegister, Address(rsp, 0)); | |
| 10876 __ addptr(rsp, 4); | |
| 10877 %} | |
| 0 | 10878 ins_pipe( pipe_slow ); |
| 10879 %} | |
| 10880 | |
| 10881 // Force rounding double precision to single precision | |
|
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10882 instruct convD2F_reg(regF dst, regD src) %{ |
| 0 | 10883 predicate(UseSSE>=2); |
| 10884 match(Set dst (ConvD2F src)); | |
| 10885 format %{ "CVTSD2SS $dst,$src\t# F-round" %} | |
| 4759 | 10886 ins_encode %{ |
| 10887 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister); | |
| 10888 %} | |
| 0 | 10889 ins_pipe( pipe_slow ); |
| 10890 %} | |
| 10891 | |
|
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10892 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{ |
| 0 | 10893 predicate(UseSSE==0); |
| 10894 match(Set dst (ConvF2D src)); | |
| 10895 format %{ "FST_S $dst,$src\t# D-round" %} | |
|
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10896 ins_encode( Pop_Reg_Reg_DPR(dst, src)); |
| 0 | 10897 ins_pipe( fpu_reg_reg ); |
| 10898 %} | |
| 10899 | |
|
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10900 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{ |
| 0 | 10901 predicate(UseSSE==1); |
| 10902 match(Set dst (ConvF2D src)); | |
| 10903 format %{ "FST_D $dst,$src\t# D-round" %} | |
| 10904 expand %{ | |
| 10905 roundDouble_mem_reg(dst,src); | |
| 10906 %} | |
| 10907 %} | |
| 10908 | |
|
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10909 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{ |
| 0 | 10910 predicate(UseSSE==1); |
| 10911 match(Set dst (ConvF2D src)); | |
| 10912 effect( KILL cr ); | |
| 10913 format %{ "SUB ESP,4\n\t" | |
| 10914 "MOVSS [ESP] $src\n\t" | |
| 10915 "FLD_S [ESP]\n\t" | |
| 10916 "ADD ESP,4\n\t" | |
| 10917 "FSTP $dst\t# D-round" %} | |
| 4759 | 10918 ins_encode %{ |
| 10919 __ subptr(rsp, 4); | |
| 10920 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 10921 __ fld_s(Address(rsp, 0)); | |
| 10922 __ addptr(rsp, 4); | |
| 10923 __ fstp_d($dst$$reg); | |
| 10924 %} | |
| 0 | 10925 ins_pipe( pipe_slow ); |
| 10926 %} | |
| 10927 | |
|
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10928 instruct convF2D_reg(regD dst, regF src) %{ |
| 0 | 10929 predicate(UseSSE>=2); |
| 10930 match(Set dst (ConvF2D src)); | |
| 10931 format %{ "CVTSS2SD $dst,$src\t# D-round" %} | |
| 4759 | 10932 ins_encode %{ |
| 10933 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister); | |
| 10934 %} | |
| 0 | 10935 ins_pipe( pipe_slow ); |
| 10936 %} | |
| 10937 | |
| 10938 // Convert a double to an int. If the double is a NAN, stuff a zero in instead. | |
|
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10939 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{ |
| 0 | 10940 predicate(UseSSE<=1); |
| 10941 match(Set dst (ConvD2I src)); | |
| 10942 effect( KILL tmp, KILL cr ); | |
| 10943 format %{ "FLD $src\t# Convert double to int \n\t" | |
| 10944 "FLDCW trunc mode\n\t" | |
| 10945 "SUB ESP,4\n\t" | |
| 10946 "FISTp [ESP + #0]\n\t" | |
| 10947 "FLDCW std/24-bit mode\n\t" | |
| 10948 "POP EAX\n\t" | |
| 10949 "CMP EAX,0x80000000\n\t" | |
| 10950 "JNE,s fast\n\t" | |
| 10951 "FLD_D $src\n\t" | |
| 10952 "CALL d2i_wrapper\n" | |
| 10953 "fast:" %} | |
|
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10954 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) ); |
| 0 | 10955 ins_pipe( pipe_slow ); |
| 10956 %} | |
| 10957 | |
| 10958 // Convert a double to an int. If the double is a NAN, stuff a zero in instead. | |
|
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10959 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{ |
| 0 | 10960 predicate(UseSSE>=2); |
| 10961 match(Set dst (ConvD2I src)); | |
| 10962 effect( KILL tmp, KILL cr ); | |
| 10963 format %{ "CVTTSD2SI $dst, $src\n\t" | |
| 10964 "CMP $dst,0x80000000\n\t" | |
| 10965 "JNE,s fast\n\t" | |
| 10966 "SUB ESP, 8\n\t" | |
| 10967 "MOVSD [ESP], $src\n\t" | |
| 10968 "FLD_D [ESP]\n\t" | |
| 10969 "ADD ESP, 8\n\t" | |
| 10970 "CALL d2i_wrapper\n" | |
| 10971 "fast:" %} | |
| 4759 | 10972 ins_encode %{ |
| 10973 Label fast; | |
| 10974 __ cvttsd2sil($dst$$Register, $src$$XMMRegister); | |
| 10975 __ cmpl($dst$$Register, 0x80000000); | |
| 10976 __ jccb(Assembler::notEqual, fast); | |
| 10977 __ subptr(rsp, 8); | |
| 10978 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 10979 __ fld_d(Address(rsp, 0)); | |
| 10980 __ addptr(rsp, 8); | |
| 10981 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper()))); | |
| 10982 __ bind(fast); | |
| 10983 %} | |
| 0 | 10984 ins_pipe( pipe_slow ); |
| 10985 %} | |
| 10986 | |
|
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10987 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{ |
| 0 | 10988 predicate(UseSSE<=1); |
| 10989 match(Set dst (ConvD2L src)); | |
| 10990 effect( KILL cr ); | |
| 10991 format %{ "FLD $src\t# Convert double to long\n\t" | |
| 10992 "FLDCW trunc mode\n\t" | |
| 10993 "SUB ESP,8\n\t" | |
| 10994 "FISTp [ESP + #0]\n\t" | |
| 10995 "FLDCW std/24-bit mode\n\t" | |
| 10996 "POP EAX\n\t" | |
| 10997 "POP EDX\n\t" | |
| 10998 "CMP EDX,0x80000000\n\t" | |
| 10999 "JNE,s fast\n\t" | |
| 11000 "TEST EAX,EAX\n\t" | |
| 11001 "JNE,s fast\n\t" | |
| 11002 "FLD $src\n\t" | |
| 11003 "CALL d2l_wrapper\n" | |
| 11004 "fast:" %} | |
|
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11005 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) ); |
| 0 | 11006 ins_pipe( pipe_slow ); |
| 11007 %} | |
| 11008 | |
| 11009 // XMM lacks a float/double->long conversion, so use the old FPU stack. | |
|
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11010 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{ |
| 0 | 11011 predicate (UseSSE>=2); |
| 11012 match(Set dst (ConvD2L src)); | |
| 11013 effect( KILL cr ); | |
| 11014 format %{ "SUB ESP,8\t# Convert double to long\n\t" | |
| 11015 "MOVSD [ESP],$src\n\t" | |
| 11016 "FLD_D [ESP]\n\t" | |
| 11017 "FLDCW trunc mode\n\t" | |
| 11018 "FISTp [ESP + #0]\n\t" | |
| 11019 "FLDCW std/24-bit mode\n\t" | |
| 11020 "POP EAX\n\t" | |
| 11021 "POP EDX\n\t" | |
| 11022 "CMP EDX,0x80000000\n\t" | |
| 11023 "JNE,s fast\n\t" | |
| 11024 "TEST EAX,EAX\n\t" | |
| 11025 "JNE,s fast\n\t" | |
| 11026 "SUB ESP,8\n\t" | |
| 11027 "MOVSD [ESP],$src\n\t" | |
| 11028 "FLD_D [ESP]\n\t" | |
| 4759 | 11029 "ADD ESP,8\n\t" |
| 0 | 11030 "CALL d2l_wrapper\n" |
| 11031 "fast:" %} | |
| 4759 | 11032 ins_encode %{ |
| 11033 Label fast; | |
| 11034 __ subptr(rsp, 8); | |
| 11035 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 11036 __ fld_d(Address(rsp, 0)); | |
| 11037 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); | |
| 11038 __ fistp_d(Address(rsp, 0)); | |
| 11039 // Restore the rounding mode, mask the exception | |
| 11040 if (Compile::current()->in_24_bit_fp_mode()) { | |
| 11041 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 11042 } else { | |
| 11043 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 11044 } | |
| 11045 // Load the converted long, adjust CPU stack | |
| 11046 __ pop(rax); | |
| 11047 __ pop(rdx); | |
| 11048 __ cmpl(rdx, 0x80000000); | |
| 11049 __ jccb(Assembler::notEqual, fast); | |
| 11050 __ testl(rax, rax); | |
| 11051 __ jccb(Assembler::notEqual, fast); | |
| 11052 __ subptr(rsp, 8); | |
| 11053 __ movdbl(Address(rsp, 0), $src$$XMMRegister); | |
| 11054 __ fld_d(Address(rsp, 0)); | |
| 11055 __ addptr(rsp, 8); | |
| 11056 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper()))); | |
| 11057 __ bind(fast); | |
| 11058 %} | |
| 0 | 11059 ins_pipe( pipe_slow ); |
| 11060 %} | |
| 11061 | |
| 11062 // Convert a double to an int. Java semantics require we do complex | |
| 11063 // manglations in the corner cases. So we set the rounding mode to | |
| 11064 // 'zero', store the darned double down as an int, and reset the | |
| 11065 // rounding mode to 'nearest'. The hardware stores a flag value down | |
| 11066 // if we would overflow or converted a NAN; we check for this and | |
| 11067 // and go the slow path if needed. | |
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11068 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{ |
| 0 | 11069 predicate(UseSSE==0); |
| 11070 match(Set dst (ConvF2I src)); | |
| 11071 effect( KILL tmp, KILL cr ); | |
| 11072 format %{ "FLD $src\t# Convert float to int \n\t" | |
| 11073 "FLDCW trunc mode\n\t" | |
| 11074 "SUB ESP,4\n\t" | |
| 11075 "FISTp [ESP + #0]\n\t" | |
| 11076 "FLDCW std/24-bit mode\n\t" | |
| 11077 "POP EAX\n\t" | |
| 11078 "CMP EAX,0x80000000\n\t" | |
| 11079 "JNE,s fast\n\t" | |
| 11080 "FLD $src\n\t" | |
| 11081 "CALL d2i_wrapper\n" | |
| 11082 "fast:" %} | |
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11083 // DPR2I_encoding works for FPR2I |
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11084 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) ); |
| 0 | 11085 ins_pipe( pipe_slow ); |
| 11086 %} | |
| 11087 | |
| 11088 // Convert a float in xmm to an int reg. | |
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11089 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{ |
| 0 | 11090 predicate(UseSSE>=1); |
| 11091 match(Set dst (ConvF2I src)); | |
| 11092 effect( KILL tmp, KILL cr ); | |
| 11093 format %{ "CVTTSS2SI $dst, $src\n\t" | |
| 11094 "CMP $dst,0x80000000\n\t" | |
| 11095 "JNE,s fast\n\t" | |
| 11096 "SUB ESP, 4\n\t" | |
| 11097 "MOVSS [ESP], $src\n\t" | |
| 11098 "FLD [ESP]\n\t" | |
| 11099 "ADD ESP, 4\n\t" | |
| 11100 "CALL d2i_wrapper\n" | |
| 11101 "fast:" %} | |
| 4759 | 11102 ins_encode %{ |
| 11103 Label fast; | |
| 11104 __ cvttss2sil($dst$$Register, $src$$XMMRegister); | |
| 11105 __ cmpl($dst$$Register, 0x80000000); | |
| 11106 __ jccb(Assembler::notEqual, fast); | |
| 11107 __ subptr(rsp, 4); | |
| 11108 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 11109 __ fld_s(Address(rsp, 0)); | |
| 11110 __ addptr(rsp, 4); | |
| 11111 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper()))); | |
| 11112 __ bind(fast); | |
| 11113 %} | |
| 0 | 11114 ins_pipe( pipe_slow ); |
| 11115 %} | |
| 11116 | |
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11117 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{ |
| 0 | 11118 predicate(UseSSE==0); |
| 11119 match(Set dst (ConvF2L src)); | |
| 11120 effect( KILL cr ); | |
| 11121 format %{ "FLD $src\t# Convert float to long\n\t" | |
| 11122 "FLDCW trunc mode\n\t" | |
| 11123 "SUB ESP,8\n\t" | |
| 11124 "FISTp [ESP + #0]\n\t" | |
| 11125 "FLDCW std/24-bit mode\n\t" | |
| 11126 "POP EAX\n\t" | |
| 11127 "POP EDX\n\t" | |
| 11128 "CMP EDX,0x80000000\n\t" | |
| 11129 "JNE,s fast\n\t" | |
| 11130 "TEST EAX,EAX\n\t" | |
| 11131 "JNE,s fast\n\t" | |
| 11132 "FLD $src\n\t" | |
| 11133 "CALL d2l_wrapper\n" | |
| 11134 "fast:" %} | |
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11135 // DPR2L_encoding works for FPR2L |
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11136 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) ); |
| 0 | 11137 ins_pipe( pipe_slow ); |
| 11138 %} | |
| 11139 | |
| 11140 // XMM lacks a float/double->long conversion, so use the old FPU stack. | |
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11141 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{ |
| 0 | 11142 predicate (UseSSE>=1); |
| 11143 match(Set dst (ConvF2L src)); | |
| 11144 effect( KILL cr ); | |
| 11145 format %{ "SUB ESP,8\t# Convert float to long\n\t" | |
| 11146 "MOVSS [ESP],$src\n\t" | |
| 11147 "FLD_S [ESP]\n\t" | |
| 11148 "FLDCW trunc mode\n\t" | |
| 11149 "FISTp [ESP + #0]\n\t" | |
| 11150 "FLDCW std/24-bit mode\n\t" | |
| 11151 "POP EAX\n\t" | |
| 11152 "POP EDX\n\t" | |
| 11153 "CMP EDX,0x80000000\n\t" | |
| 11154 "JNE,s fast\n\t" | |
| 11155 "TEST EAX,EAX\n\t" | |
| 11156 "JNE,s fast\n\t" | |
| 11157 "SUB ESP,4\t# Convert float to long\n\t" | |
| 11158 "MOVSS [ESP],$src\n\t" | |
| 11159 "FLD_S [ESP]\n\t" | |
| 11160 "ADD ESP,4\n\t" | |
| 11161 "CALL d2l_wrapper\n" | |
| 11162 "fast:" %} | |
| 4759 | 11163 ins_encode %{ |
| 11164 Label fast; | |
| 11165 __ subptr(rsp, 8); | |
| 11166 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 11167 __ fld_s(Address(rsp, 0)); | |
| 11168 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); | |
| 11169 __ fistp_d(Address(rsp, 0)); | |
| 11170 // Restore the rounding mode, mask the exception | |
| 11171 if (Compile::current()->in_24_bit_fp_mode()) { | |
| 11172 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 11173 } else { | |
| 11174 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 11175 } | |
| 11176 // Load the converted long, adjust CPU stack | |
| 11177 __ pop(rax); | |
| 11178 __ pop(rdx); | |
| 11179 __ cmpl(rdx, 0x80000000); | |
| 11180 __ jccb(Assembler::notEqual, fast); | |
| 11181 __ testl(rax, rax); | |
| 11182 __ jccb(Assembler::notEqual, fast); | |
| 11183 __ subptr(rsp, 4); | |
| 11184 __ movflt(Address(rsp, 0), $src$$XMMRegister); | |
| 11185 __ fld_s(Address(rsp, 0)); | |
| 11186 __ addptr(rsp, 4); | |
| 11187 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper()))); | |
| 11188 __ bind(fast); | |
| 11189 %} | |
| 0 | 11190 ins_pipe( pipe_slow ); |
| 11191 %} | |
| 11192 | |
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11193 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{ |
| 0 | 11194 predicate( UseSSE<=1 ); |
| 11195 match(Set dst (ConvI2D src)); | |
| 11196 format %{ "FILD $src\n\t" | |
| 11197 "FSTP $dst" %} | |
| 11198 opcode(0xDB, 0x0); /* DB /0 */ | |
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11199 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst)); |
| 0 | 11200 ins_pipe( fpu_reg_mem ); |
| 11201 %} | |
| 11202 | |
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11203 instruct convI2D_reg(regD dst, eRegI src) %{ |
| 71 | 11204 predicate( UseSSE>=2 && !UseXmmI2D ); |
| 0 | 11205 match(Set dst (ConvI2D src)); |
| 11206 format %{ "CVTSI2SD $dst,$src" %} | |
| 4759 | 11207 ins_encode %{ |
| 11208 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register); | |
| 11209 %} | |
| 0 | 11210 ins_pipe( pipe_slow ); |
| 11211 %} | |
| 11212 | |
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11213 instruct convI2D_mem(regD dst, memory mem) %{ |
| 0 | 11214 predicate( UseSSE>=2 ); |
| 11215 match(Set dst (ConvI2D (LoadI mem))); | |
| 11216 format %{ "CVTSI2SD $dst,$mem" %} | |
| 4759 | 11217 ins_encode %{ |
| 11218 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address); | |
| 11219 %} | |
| 0 | 11220 ins_pipe( pipe_slow ); |
| 11221 %} | |
| 11222 | |
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11223 instruct convXI2D_reg(regD dst, eRegI src) |
| 71 | 11224 %{ |
| 11225 predicate( UseSSE>=2 && UseXmmI2D ); | |
| 11226 match(Set dst (ConvI2D src)); | |
| 11227 | |
| 11228 format %{ "MOVD $dst,$src\n\t" | |
| 11229 "CVTDQ2PD $dst,$dst\t# i2d" %} | |
| 11230 ins_encode %{ | |
| 304 | 11231 __ movdl($dst$$XMMRegister, $src$$Register); |
| 71 | 11232 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister); |
| 11233 %} | |
| 11234 ins_pipe(pipe_slow); // XXX | |
| 11235 %} | |
| 11236 | |
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11237 instruct convI2DPR_mem(regDPR dst, memory mem) %{ |
| 0 | 11238 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr()); |
| 11239 match(Set dst (ConvI2D (LoadI mem))); | |
| 11240 format %{ "FILD $mem\n\t" | |
| 11241 "FSTP $dst" %} | |
| 11242 opcode(0xDB); /* DB /0 */ | |
| 11243 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
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11244 Pop_Reg_DPR(dst)); |
| 0 | 11245 ins_pipe( fpu_reg_mem ); |
| 11246 %} | |
| 11247 | |
| 11248 // Convert a byte to a float; no rounding step needed. | |
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11249 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{ |
| 0 | 11250 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 ); |
| 11251 match(Set dst (ConvI2F src)); | |
| 11252 format %{ "FILD $src\n\t" | |
| 11253 "FSTP $dst" %} | |
| 11254 | |
| 11255 opcode(0xDB, 0x0); /* DB /0 */ | |
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11256 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst)); |
| 0 | 11257 ins_pipe( fpu_reg_mem ); |
| 11258 %} | |
| 11259 | |
| 11260 // In 24-bit mode, force exponent rounding by storing back out | |
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11261 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{ |
| 0 | 11262 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 11263 match(Set dst (ConvI2F src)); | |
| 11264 ins_cost(200); | |
| 11265 format %{ "FILD $src\n\t" | |
| 11266 "FSTP_S $dst" %} | |
| 11267 opcode(0xDB, 0x0); /* DB /0 */ | |
| 11268 ins_encode( Push_Mem_I(src), | |
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11269 Pop_Mem_FPR(dst)); |
| 0 | 11270 ins_pipe( fpu_mem_mem ); |
| 11271 %} | |
| 11272 | |
| 11273 // In 24-bit mode, force exponent rounding by storing back out | |
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11274 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{ |
| 0 | 11275 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); |
| 11276 match(Set dst (ConvI2F (LoadI mem))); | |
| 11277 ins_cost(200); | |
| 11278 format %{ "FILD $mem\n\t" | |
| 11279 "FSTP_S $dst" %} | |
| 11280 opcode(0xDB); /* DB /0 */ | |
| 11281 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
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11282 Pop_Mem_FPR(dst)); |
| 0 | 11283 ins_pipe( fpu_mem_mem ); |
| 11284 %} | |
| 11285 | |
| 11286 // This instruction does not round to 24-bits | |
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11287 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{ |
| 0 | 11288 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 11289 match(Set dst (ConvI2F src)); | |
| 11290 format %{ "FILD $src\n\t" | |
| 11291 "FSTP $dst" %} | |
| 11292 opcode(0xDB, 0x0); /* DB /0 */ | |
| 11293 ins_encode( Push_Mem_I(src), | |
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11294 Pop_Reg_FPR(dst)); |
| 0 | 11295 ins_pipe( fpu_reg_mem ); |
| 11296 %} | |
| 11297 | |
| 11298 // This instruction does not round to 24-bits | |
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11299 instruct convI2FPR_mem(regFPR dst, memory mem) %{ |
| 0 | 11300 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); |
| 11301 match(Set dst (ConvI2F (LoadI mem))); | |
| 11302 format %{ "FILD $mem\n\t" | |
| 11303 "FSTP $dst" %} | |
| 11304 opcode(0xDB); /* DB /0 */ | |
| 11305 ins_encode( OpcP, RMopc_Mem(0x00,mem), | |
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11306 Pop_Reg_FPR(dst)); |
| 0 | 11307 ins_pipe( fpu_reg_mem ); |
| 11308 %} | |
| 11309 | |
| 11310 // Convert an int to a float in xmm; no rounding step needed. | |
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11311 instruct convI2F_reg(regF dst, eRegI src) %{ |
| 71 | 11312 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F ); |
| 0 | 11313 match(Set dst (ConvI2F src)); |
| 11314 format %{ "CVTSI2SS $dst, $src" %} | |
| 4759 | 11315 ins_encode %{ |
| 11316 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register); | |
| 11317 %} | |
| 0 | 11318 ins_pipe( pipe_slow ); |
| 11319 %} | |
| 11320 | |
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11321 instruct convXI2F_reg(regF dst, eRegI src) |
| 71 | 11322 %{ |
| 11323 predicate( UseSSE>=2 && UseXmmI2F ); | |
| 11324 match(Set dst (ConvI2F src)); | |
| 11325 | |
| 11326 format %{ "MOVD $dst,$src\n\t" | |
| 11327 "CVTDQ2PS $dst,$dst\t# i2f" %} | |
| 11328 ins_encode %{ | |
| 304 | 11329 __ movdl($dst$$XMMRegister, $src$$Register); |
| 71 | 11330 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister); |
| 11331 %} | |
| 11332 ins_pipe(pipe_slow); // XXX | |
| 11333 %} | |
| 11334 | |
| 0 | 11335 instruct convI2L_reg( eRegL dst, eRegI src, eFlagsReg cr) %{ |
| 11336 match(Set dst (ConvI2L src)); | |
| 11337 effect(KILL cr); | |
| 624 | 11338 ins_cost(375); |
| 0 | 11339 format %{ "MOV $dst.lo,$src\n\t" |
| 11340 "MOV $dst.hi,$src\n\t" | |
| 11341 "SAR $dst.hi,31" %} | |
| 11342 ins_encode(convert_int_long(dst,src)); | |
| 11343 ins_pipe( ialu_reg_reg_long ); | |
| 11344 %} | |
| 11345 | |
| 11346 // Zero-extend convert int to long | |
| 11347 instruct convI2L_reg_zex(eRegL dst, eRegI src, immL_32bits mask, eFlagsReg flags ) %{ | |
| 11348 match(Set dst (AndL (ConvI2L src) mask) ); | |
| 11349 effect( KILL flags ); | |
| 624 | 11350 ins_cost(250); |
| 0 | 11351 format %{ "MOV $dst.lo,$src\n\t" |
| 11352 "XOR $dst.hi,$dst.hi" %} | |
| 11353 opcode(0x33); // XOR | |
| 11354 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) ); | |
| 11355 ins_pipe( ialu_reg_reg_long ); | |
| 11356 %} | |
| 11357 | |
| 11358 // Zero-extend long | |
| 11359 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{ | |
| 11360 match(Set dst (AndL src mask) ); | |
| 11361 effect( KILL flags ); | |
| 624 | 11362 ins_cost(250); |
| 0 | 11363 format %{ "MOV $dst.lo,$src.lo\n\t" |
| 11364 "XOR $dst.hi,$dst.hi\n\t" %} | |
| 11365 opcode(0x33); // XOR | |
| 11366 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) ); | |
| 11367 ins_pipe( ialu_reg_reg_long ); | |
| 11368 %} | |
| 11369 | |
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11370 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{ |
| 0 | 11371 predicate (UseSSE<=1); |
| 11372 match(Set dst (ConvL2D src)); | |
| 11373 effect( KILL cr ); | |
| 11374 format %{ "PUSH $src.hi\t# Convert long to double\n\t" | |
| 11375 "PUSH $src.lo\n\t" | |
| 11376 "FILD ST,[ESP + #0]\n\t" | |
| 11377 "ADD ESP,8\n\t" | |
| 11378 "FSTP_D $dst\t# D-round" %} | |
| 11379 opcode(0xDF, 0x5); /* DF /5 */ | |
|
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11380 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst)); |
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11381 ins_pipe( pipe_slow ); |
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11382 %} |
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11383 |
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11384 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{ |
| 0 | 11385 predicate (UseSSE>=2); |
| 11386 match(Set dst (ConvL2D src)); | |
| 11387 effect( KILL cr ); | |
| 11388 format %{ "PUSH $src.hi\t# Convert long to double\n\t" | |
| 11389 "PUSH $src.lo\n\t" | |
| 11390 "FILD_D [ESP]\n\t" | |
| 11391 "FSTP_D [ESP]\n\t" | |
| 11392 "MOVSD $dst,[ESP]\n\t" | |
| 11393 "ADD ESP,8" %} | |
| 11394 opcode(0xDF, 0x5); /* DF /5 */ | |
|
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11395 ins_encode(convert_long_double2(src), Push_ResultD(dst)); |
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11396 ins_pipe( pipe_slow ); |
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11397 %} |
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11398 |
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11399 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{ |
| 0 | 11400 predicate (UseSSE>=1); |
| 11401 match(Set dst (ConvL2F src)); | |
| 11402 effect( KILL cr ); | |
| 11403 format %{ "PUSH $src.hi\t# Convert long to single float\n\t" | |
| 11404 "PUSH $src.lo\n\t" | |
| 11405 "FILD_D [ESP]\n\t" | |
| 11406 "FSTP_S [ESP]\n\t" | |
| 11407 "MOVSS $dst,[ESP]\n\t" | |
| 11408 "ADD ESP,8" %} | |
| 11409 opcode(0xDF, 0x5); /* DF /5 */ | |
|
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11410 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8)); |
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11411 ins_pipe( pipe_slow ); |
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11412 %} |
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11413 |
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11414 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{ |
| 0 | 11415 match(Set dst (ConvL2F src)); |
| 11416 effect( KILL cr ); | |
| 11417 format %{ "PUSH $src.hi\t# Convert long to single float\n\t" | |
| 11418 "PUSH $src.lo\n\t" | |
| 11419 "FILD ST,[ESP + #0]\n\t" | |
| 11420 "ADD ESP,8\n\t" | |
| 11421 "FSTP_S $dst\t# F-round" %} | |
| 11422 opcode(0xDF, 0x5); /* DF /5 */ | |
|
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11423 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst)); |
| 0 | 11424 ins_pipe( pipe_slow ); |
| 11425 %} | |
| 11426 | |
| 11427 instruct convL2I_reg( eRegI dst, eRegL src ) %{ | |
| 11428 match(Set dst (ConvL2I src)); | |
| 11429 effect( DEF dst, USE src ); | |
| 11430 format %{ "MOV $dst,$src.lo" %} | |
| 11431 ins_encode(enc_CopyL_Lo(dst,src)); | |
| 11432 ins_pipe( ialu_reg_reg ); | |
| 11433 %} | |
| 11434 | |
| 11435 | |
| 11436 instruct MoveF2I_stack_reg(eRegI dst, stackSlotF src) %{ | |
| 11437 match(Set dst (MoveF2I src)); | |
| 11438 effect( DEF dst, USE src ); | |
| 11439 ins_cost(100); | |
| 11440 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %} | |
| 4759 | 11441 ins_encode %{ |
| 11442 __ movl($dst$$Register, Address(rsp, $src$$disp)); | |
| 11443 %} | |
| 0 | 11444 ins_pipe( ialu_reg_mem ); |
| 11445 %} | |
| 11446 | |
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11447 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{ |
| 0 | 11448 predicate(UseSSE==0); |
| 11449 match(Set dst (MoveF2I src)); | |
| 11450 effect( DEF dst, USE src ); | |
| 11451 | |
| 11452 ins_cost(125); | |
| 11453 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %} | |
|
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11454 ins_encode( Pop_Mem_Reg_FPR(dst, src) ); |
| 0 | 11455 ins_pipe( fpu_mem_reg ); |
| 11456 %} | |
| 11457 | |
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11458 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{ |
| 0 | 11459 predicate(UseSSE>=1); |
| 11460 match(Set dst (MoveF2I src)); | |
| 11461 effect( DEF dst, USE src ); | |
| 11462 | |
| 11463 ins_cost(95); | |
| 11464 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %} | |
| 4759 | 11465 ins_encode %{ |
| 11466 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 11467 %} | |
| 0 | 11468 ins_pipe( pipe_slow ); |
| 11469 %} | |
| 11470 | |
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11471 instruct MoveF2I_reg_reg_sse(eRegI dst, regF src) %{ |
| 0 | 11472 predicate(UseSSE>=2); |
| 11473 match(Set dst (MoveF2I src)); | |
| 11474 effect( DEF dst, USE src ); | |
| 11475 ins_cost(85); | |
| 11476 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %} | |
| 4759 | 11477 ins_encode %{ |
| 11478 __ movdl($dst$$Register, $src$$XMMRegister); | |
| 11479 %} | |
| 0 | 11480 ins_pipe( pipe_slow ); |
| 11481 %} | |
| 11482 | |
| 11483 instruct MoveI2F_reg_stack(stackSlotF dst, eRegI src) %{ | |
| 11484 match(Set dst (MoveI2F src)); | |
| 11485 effect( DEF dst, USE src ); | |
| 11486 | |
| 11487 ins_cost(100); | |
| 11488 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %} | |
| 4759 | 11489 ins_encode %{ |
| 11490 __ movl(Address(rsp, $dst$$disp), $src$$Register); | |
| 11491 %} | |
| 0 | 11492 ins_pipe( ialu_mem_reg ); |
| 11493 %} | |
| 11494 | |
| 11495 | |
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11496 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{ |
| 0 | 11497 predicate(UseSSE==0); |
| 11498 match(Set dst (MoveI2F src)); | |
| 11499 effect(DEF dst, USE src); | |
| 11500 | |
| 11501 ins_cost(125); | |
| 11502 format %{ "FLD_S $src\n\t" | |
| 11503 "FSTP $dst\t# MoveI2F_stack_reg" %} | |
| 11504 opcode(0xD9); /* D9 /0, FLD m32real */ | |
| 11505 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
|
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11506 Pop_Reg_FPR(dst) ); |
| 0 | 11507 ins_pipe( fpu_reg_mem ); |
| 11508 %} | |
| 11509 | |
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11510 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{ |
| 0 | 11511 predicate(UseSSE>=1); |
| 11512 match(Set dst (MoveI2F src)); | |
| 11513 effect( DEF dst, USE src ); | |
| 11514 | |
| 11515 ins_cost(95); | |
| 11516 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %} | |
| 4759 | 11517 ins_encode %{ |
| 11518 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 11519 %} | |
| 0 | 11520 ins_pipe( pipe_slow ); |
| 11521 %} | |
| 11522 | |
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11523 instruct MoveI2F_reg_reg_sse(regF dst, eRegI src) %{ |
| 0 | 11524 predicate(UseSSE>=2); |
| 11525 match(Set dst (MoveI2F src)); | |
| 11526 effect( DEF dst, USE src ); | |
| 11527 | |
| 11528 ins_cost(85); | |
| 11529 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %} | |
| 4759 | 11530 ins_encode %{ |
| 11531 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 11532 %} | |
| 0 | 11533 ins_pipe( pipe_slow ); |
| 11534 %} | |
| 11535 | |
| 11536 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{ | |
| 11537 match(Set dst (MoveD2L src)); | |
| 11538 effect(DEF dst, USE src); | |
| 11539 | |
| 11540 ins_cost(250); | |
| 11541 format %{ "MOV $dst.lo,$src\n\t" | |
| 11542 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %} | |
| 11543 opcode(0x8B, 0x8B); | |
| 11544 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src)); | |
| 11545 ins_pipe( ialu_mem_long_reg ); | |
| 11546 %} | |
| 11547 | |
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11548 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{ |
| 0 | 11549 predicate(UseSSE<=1); |
| 11550 match(Set dst (MoveD2L src)); | |
| 11551 effect(DEF dst, USE src); | |
| 11552 | |
| 11553 ins_cost(125); | |
| 11554 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %} | |
|
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11555 ins_encode( Pop_Mem_Reg_DPR(dst, src) ); |
| 0 | 11556 ins_pipe( fpu_mem_reg ); |
| 11557 %} | |
| 11558 | |
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11559 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{ |
| 0 | 11560 predicate(UseSSE>=2); |
| 11561 match(Set dst (MoveD2L src)); | |
| 11562 effect(DEF dst, USE src); | |
| 11563 ins_cost(95); | |
| 11564 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %} | |
| 4759 | 11565 ins_encode %{ |
| 11566 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister); | |
| 11567 %} | |
| 0 | 11568 ins_pipe( pipe_slow ); |
| 11569 %} | |
| 11570 | |
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11571 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{ |
| 0 | 11572 predicate(UseSSE>=2); |
| 11573 match(Set dst (MoveD2L src)); | |
| 11574 effect(DEF dst, USE src, TEMP tmp); | |
| 11575 ins_cost(85); | |
| 11576 format %{ "MOVD $dst.lo,$src\n\t" | |
| 11577 "PSHUFLW $tmp,$src,0x4E\n\t" | |
| 11578 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %} | |
| 4759 | 11579 ins_encode %{ |
| 11580 __ movdl($dst$$Register, $src$$XMMRegister); | |
| 11581 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e); | |
| 11582 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister); | |
| 11583 %} | |
| 0 | 11584 ins_pipe( pipe_slow ); |
| 11585 %} | |
| 11586 | |
| 11587 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{ | |
| 11588 match(Set dst (MoveL2D src)); | |
| 11589 effect(DEF dst, USE src); | |
| 11590 | |
| 11591 ins_cost(200); | |
| 11592 format %{ "MOV $dst,$src.lo\n\t" | |
| 11593 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %} | |
| 11594 opcode(0x89, 0x89); | |
| 11595 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) ); | |
| 11596 ins_pipe( ialu_mem_long_reg ); | |
| 11597 %} | |
| 11598 | |
| 11599 | |
|
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11600 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{ |
| 0 | 11601 predicate(UseSSE<=1); |
| 11602 match(Set dst (MoveL2D src)); | |
| 11603 effect(DEF dst, USE src); | |
| 11604 ins_cost(125); | |
| 11605 | |
| 11606 format %{ "FLD_D $src\n\t" | |
| 11607 "FSTP $dst\t# MoveL2D_stack_reg" %} | |
| 11608 opcode(0xDD); /* DD /0, FLD m64real */ | |
| 11609 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), | |
|
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11610 Pop_Reg_DPR(dst) ); |
| 0 | 11611 ins_pipe( fpu_reg_mem ); |
| 11612 %} | |
| 11613 | |
| 11614 | |
|
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11615 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{ |
| 0 | 11616 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper); |
| 11617 match(Set dst (MoveL2D src)); | |
| 11618 effect(DEF dst, USE src); | |
| 11619 | |
| 11620 ins_cost(95); | |
| 11621 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %} | |
| 4759 | 11622 ins_encode %{ |
| 11623 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 11624 %} | |
| 0 | 11625 ins_pipe( pipe_slow ); |
| 11626 %} | |
| 11627 | |
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11628 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{ |
| 0 | 11629 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper); |
| 11630 match(Set dst (MoveL2D src)); | |
| 11631 effect(DEF dst, USE src); | |
| 11632 | |
| 11633 ins_cost(95); | |
| 11634 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %} | |
| 4759 | 11635 ins_encode %{ |
| 11636 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 11637 %} | |
| 0 | 11638 ins_pipe( pipe_slow ); |
| 11639 %} | |
| 11640 | |
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11641 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{ |
| 0 | 11642 predicate(UseSSE>=2); |
| 11643 match(Set dst (MoveL2D src)); | |
| 11644 effect(TEMP dst, USE src, TEMP tmp); | |
| 11645 ins_cost(85); | |
| 11646 format %{ "MOVD $dst,$src.lo\n\t" | |
| 11647 "MOVD $tmp,$src.hi\n\t" | |
| 11648 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %} | |
| 4759 | 11649 ins_encode %{ |
| 11650 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 11651 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register)); | |
| 11652 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister); | |
| 11653 %} | |
| 0 | 11654 ins_pipe( pipe_slow ); |
| 11655 %} | |
| 11656 | |
| 11657 // Replicate scalar to packed byte (1 byte) values in xmm | |
|
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11658 instruct Repl8B_reg(regD dst, regD src) %{ |
| 0 | 11659 predicate(UseSSE>=2); |
| 11660 match(Set dst (Replicate8B src)); | |
| 11661 format %{ "MOVDQA $dst,$src\n\t" | |
| 11662 "PUNPCKLBW $dst,$dst\n\t" | |
| 11663 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} | |
| 4759 | 11664 ins_encode %{ |
| 11665 if ($dst$$reg != $src$$reg) { | |
| 11666 __ movdqa($dst$$XMMRegister, $src$$XMMRegister); | |
| 11667 } | |
| 11668 __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister); | |
| 11669 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); | |
| 11670 %} | |
| 0 | 11671 ins_pipe( pipe_slow ); |
| 11672 %} | |
| 11673 | |
| 11674 // Replicate scalar to packed byte (1 byte) values in xmm | |
|
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11675 instruct Repl8B_eRegI(regD dst, eRegI src) %{ |
| 0 | 11676 predicate(UseSSE>=2); |
| 11677 match(Set dst (Replicate8B src)); | |
| 11678 format %{ "MOVD $dst,$src\n\t" | |
| 11679 "PUNPCKLBW $dst,$dst\n\t" | |
| 11680 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} | |
| 4759 | 11681 ins_encode %{ |
| 11682 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 11683 __ punpcklbw($dst$$XMMRegister, $dst$$XMMRegister); | |
| 11684 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); | |
| 11685 %} | |
| 0 | 11686 ins_pipe( pipe_slow ); |
| 11687 %} | |
| 11688 | |
| 11689 // Replicate scalar zero to packed byte (1 byte) values in xmm | |
|
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11690 instruct Repl8B_immI0(regD dst, immI0 zero) %{ |
| 0 | 11691 predicate(UseSSE>=2); |
| 11692 match(Set dst (Replicate8B zero)); | |
| 11693 format %{ "PXOR $dst,$dst\t! replicate8B" %} | |
| 4759 | 11694 ins_encode %{ |
| 11695 __ pxor($dst$$XMMRegister, $dst$$XMMRegister); | |
| 11696 %} | |
| 0 | 11697 ins_pipe( fpu_reg_reg ); |
| 11698 %} | |
| 11699 | |
| 11700 // Replicate scalar to packed shore (2 byte) values in xmm | |
|
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11701 instruct Repl4S_reg(regD dst, regD src) %{ |
| 0 | 11702 predicate(UseSSE>=2); |
| 11703 match(Set dst (Replicate4S src)); | |
| 11704 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %} | |
| 4759 | 11705 ins_encode %{ |
| 11706 __ pshuflw($dst$$XMMRegister, $src$$XMMRegister, 0x00); | |
| 11707 %} | |
| 0 | 11708 ins_pipe( fpu_reg_reg ); |
| 11709 %} | |
| 11710 | |
| 11711 // Replicate scalar to packed shore (2 byte) values in xmm | |
|
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11712 instruct Repl4S_eRegI(regD dst, eRegI src) %{ |
| 0 | 11713 predicate(UseSSE>=2); |
| 11714 match(Set dst (Replicate4S src)); | |
| 11715 format %{ "MOVD $dst,$src\n\t" | |
| 11716 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %} | |
| 4759 | 11717 ins_encode %{ |
| 11718 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 11719 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); | |
| 11720 %} | |
| 0 | 11721 ins_pipe( fpu_reg_reg ); |
| 11722 %} | |
| 11723 | |
| 11724 // Replicate scalar zero to packed short (2 byte) values in xmm | |
|
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11725 instruct Repl4S_immI0(regD dst, immI0 zero) %{ |
| 0 | 11726 predicate(UseSSE>=2); |
| 11727 match(Set dst (Replicate4S zero)); | |
| 11728 format %{ "PXOR $dst,$dst\t! replicate4S" %} | |
| 4759 | 11729 ins_encode %{ |
| 11730 __ pxor($dst$$XMMRegister, $dst$$XMMRegister); | |
| 11731 %} | |
| 0 | 11732 ins_pipe( fpu_reg_reg ); |
| 11733 %} | |
| 11734 | |
| 11735 // Replicate scalar to packed char (2 byte) values in xmm | |
|
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11736 instruct Repl4C_reg(regD dst, regD src) %{ |
| 0 | 11737 predicate(UseSSE>=2); |
| 11738 match(Set dst (Replicate4C src)); | |
| 11739 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %} | |
| 4759 | 11740 ins_encode %{ |
| 11741 __ pshuflw($dst$$XMMRegister, $src$$XMMRegister, 0x00); | |
| 11742 %} | |
| 0 | 11743 ins_pipe( fpu_reg_reg ); |
| 11744 %} | |
| 11745 | |
| 11746 // Replicate scalar to packed char (2 byte) values in xmm | |
|
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11747 instruct Repl4C_eRegI(regD dst, eRegI src) %{ |
| 0 | 11748 predicate(UseSSE>=2); |
| 11749 match(Set dst (Replicate4C src)); | |
| 11750 format %{ "MOVD $dst,$src\n\t" | |
| 11751 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %} | |
| 4759 | 11752 ins_encode %{ |
| 11753 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 11754 __ pshuflw($dst$$XMMRegister, $dst$$XMMRegister, 0x00); | |
| 11755 %} | |
| 0 | 11756 ins_pipe( fpu_reg_reg ); |
| 11757 %} | |
| 11758 | |
| 11759 // Replicate scalar zero to packed char (2 byte) values in xmm | |
|
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11760 instruct Repl4C_immI0(regD dst, immI0 zero) %{ |
| 0 | 11761 predicate(UseSSE>=2); |
| 11762 match(Set dst (Replicate4C zero)); | |
| 11763 format %{ "PXOR $dst,$dst\t! replicate4C" %} | |
| 4759 | 11764 ins_encode %{ |
| 11765 __ pxor($dst$$XMMRegister, $dst$$XMMRegister); | |
| 11766 %} | |
| 0 | 11767 ins_pipe( fpu_reg_reg ); |
| 11768 %} | |
| 11769 | |
| 11770 // Replicate scalar to packed integer (4 byte) values in xmm | |
|
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11771 instruct Repl2I_reg(regD dst, regD src) %{ |
| 0 | 11772 predicate(UseSSE>=2); |
| 11773 match(Set dst (Replicate2I src)); | |
| 11774 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %} | |
| 4759 | 11775 ins_encode %{ |
| 11776 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0x00); | |
| 11777 %} | |
| 0 | 11778 ins_pipe( fpu_reg_reg ); |
| 11779 %} | |
| 11780 | |
| 11781 // Replicate scalar to packed integer (4 byte) values in xmm | |
|
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11782 instruct Repl2I_eRegI(regD dst, eRegI src) %{ |
| 0 | 11783 predicate(UseSSE>=2); |
| 11784 match(Set dst (Replicate2I src)); | |
| 11785 format %{ "MOVD $dst,$src\n\t" | |
| 11786 "PSHUFD $dst,$dst,0x00\t! replicate2I" %} | |
| 4759 | 11787 ins_encode %{ |
| 11788 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 11789 __ pshufd($dst$$XMMRegister, $dst$$XMMRegister, 0x00); | |
| 11790 %} | |
| 0 | 11791 ins_pipe( fpu_reg_reg ); |
| 11792 %} | |
| 11793 | |
| 11794 // Replicate scalar zero to packed integer (2 byte) values in xmm | |
|
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11795 instruct Repl2I_immI0(regD dst, immI0 zero) %{ |
| 0 | 11796 predicate(UseSSE>=2); |
| 11797 match(Set dst (Replicate2I zero)); | |
| 11798 format %{ "PXOR $dst,$dst\t! replicate2I" %} | |
| 4759 | 11799 ins_encode %{ |
| 11800 __ pxor($dst$$XMMRegister, $dst$$XMMRegister); | |
| 11801 %} | |
| 0 | 11802 ins_pipe( fpu_reg_reg ); |
| 11803 %} | |
| 11804 | |
| 11805 // Replicate scalar to packed single precision floating point values in xmm | |
|
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11806 instruct Repl2F_reg(regD dst, regD src) %{ |
| 0 | 11807 predicate(UseSSE>=2); |
| 11808 match(Set dst (Replicate2F src)); | |
| 11809 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} | |
| 4759 | 11810 ins_encode %{ |
| 11811 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0xe0); | |
| 11812 %} | |
| 0 | 11813 ins_pipe( fpu_reg_reg ); |
| 11814 %} | |
| 11815 | |
| 11816 // Replicate scalar to packed single precision floating point values in xmm | |
|
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11817 instruct Repl2F_regF(regD dst, regF src) %{ |
| 0 | 11818 predicate(UseSSE>=2); |
| 11819 match(Set dst (Replicate2F src)); | |
| 11820 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} | |
| 4759 | 11821 ins_encode %{ |
| 11822 __ pshufd($dst$$XMMRegister, $src$$XMMRegister, 0xe0); | |
| 11823 %} | |
| 0 | 11824 ins_pipe( fpu_reg_reg ); |
| 11825 %} | |
| 11826 | |
| 11827 // Replicate scalar to packed single precision floating point values in xmm | |
|
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11828 instruct Repl2F_immF0(regD dst, immF0 zero) %{ |
| 0 | 11829 predicate(UseSSE>=2); |
| 11830 match(Set dst (Replicate2F zero)); | |
| 11831 format %{ "PXOR $dst,$dst\t! replicate2F" %} | |
| 4759 | 11832 ins_encode %{ |
| 11833 __ pxor($dst$$XMMRegister, $dst$$XMMRegister); | |
| 11834 %} | |
| 0 | 11835 ins_pipe( fpu_reg_reg ); |
| 11836 %} | |
| 11837 | |
| 11838 // ======================================================================= | |
| 11839 // fast clearing of an array | |
| 11840 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{ | |
| 11841 match(Set dummy (ClearArray cnt base)); | |
| 11842 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); | |
| 11843 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t" | |
| 11844 "XOR EAX,EAX\n\t" | |
| 11845 "REP STOS\t# store EAX into [EDI++] while ECX--" %} | |
| 11846 opcode(0,0x4); | |
| 11847 ins_encode( Opcode(0xD1), RegOpc(ECX), | |
| 11848 OpcRegReg(0x33,EAX,EAX), | |
| 11849 Opcode(0xF3), Opcode(0xAB) ); | |
| 11850 ins_pipe( pipe_slow ); | |
| 11851 %} | |
| 11852 | |
| 2262 | 11853 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2, |
|
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11854 eAXRegI result, regD tmp1, eFlagsReg cr) %{ |
|
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11855 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
| 2262 | 11856 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr); |
| 11857 | |
| 11858 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %} | |
|
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|
11859 ins_encode %{ |
|
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|
11860 __ string_compare($str1$$Register, $str2$$Register, |
|
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11861 $cnt1$$Register, $cnt2$$Register, $result$$Register, |
| 2262 | 11862 $tmp1$$XMMRegister); |
|
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|
11863 %} |
| 681 | 11864 ins_pipe( pipe_slow ); |
| 11865 %} | |
| 11866 | |
| 11867 // fast string equals | |
|
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11868 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result, |
|
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11869 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{ |
|
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11870 match(Set result (StrEquals (Binary str1 str2) cnt)); |
|
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11871 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr); |
|
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|
11872 |
|
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|
11873 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %} |
|
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|
11874 ins_encode %{ |
|
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|
11875 __ char_arrays_equals(false, $str1$$Register, $str2$$Register, |
|
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|
11876 $cnt$$Register, $result$$Register, $tmp3$$Register, |
|
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|
11877 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
|
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|
11878 %} |
|
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|
11879 ins_pipe( pipe_slow ); |
|
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|
11880 %} |
|
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|
11881 |
|
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|
11882 // fast search of substring with known size. |
|
41d4973cf100
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|
11883 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2, |
|
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11884 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{ |
|
2320
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|
11885 predicate(UseSSE42Intrinsics); |
|
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|
11886 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2))); |
|
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|
11887 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr); |
|
41d4973cf100
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|
11888 |
|
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|
11889 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %} |
|
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|
11890 ins_encode %{ |
|
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|
11891 int icnt2 = (int)$int_cnt2$$constant; |
|
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|
11892 if (icnt2 >= 8) { |
|
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|
11893 // IndexOf for constant substrings with size >= 8 elements |
|
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|
11894 // which don't need to be loaded through stack. |
|
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|
11895 __ string_indexofC8($str1$$Register, $str2$$Register, |
|
41d4973cf100
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|
11896 $cnt1$$Register, $cnt2$$Register, |
|
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|
11897 icnt2, $result$$Register, |
|
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|
11898 $vec$$XMMRegister, $tmp$$Register); |
|
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|
11899 } else { |
|
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|
11900 // Small strings are loaded through stack if they cross page boundary. |
|
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|
11901 __ string_indexof($str1$$Register, $str2$$Register, |
|
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|
11902 $cnt1$$Register, $cnt2$$Register, |
|
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|
11903 icnt2, $result$$Register, |
|
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|
11904 $vec$$XMMRegister, $tmp$$Register); |
|
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|
11905 } |
|
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|
11906 %} |
|
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|
11907 ins_pipe( pipe_slow ); |
|
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|
11908 %} |
|
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|
11909 |
|
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11910 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2, |
|
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11911 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{ |
| 681 | 11912 predicate(UseSSE42Intrinsics); |
|
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11913 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2))); |
|
2320
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|
11914 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr); |
|
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|
11915 |
|
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|
11916 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %} |
|
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|
11917 ins_encode %{ |
|
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|
11918 __ string_indexof($str1$$Register, $str2$$Register, |
|
2320
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11919 $cnt1$$Register, $cnt2$$Register, |
|
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|
11920 (-1), $result$$Register, |
|
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|
11921 $vec$$XMMRegister, $tmp$$Register); |
|
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|
11922 %} |
| 0 | 11923 ins_pipe( pipe_slow ); |
| 11924 %} | |
| 11925 | |
|
169
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|
11926 // fast array equals |
|
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|
11927 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result, |
|
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11928 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr) |
|
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11929 %{ |
|
169
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|
11930 match(Set result (AryEq ary1 ary2)); |
| 681 | 11931 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr); |
|
169
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|
11932 //ins_cost(300); |
|
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|
11933 |
|
986
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11934 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %} |
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11935 ins_encode %{ |
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11936 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register, |
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11937 $tmp3$$Register, $result$$Register, $tmp4$$Register, |
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11938 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
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11939 %} |
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11940 ins_pipe( pipe_slow ); |
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11941 %} |
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11942 |
| 0 | 11943 //----------Control Flow Instructions------------------------------------------ |
| 11944 // Signed compare Instructions | |
| 11945 instruct compI_eReg(eFlagsReg cr, eRegI op1, eRegI op2) %{ | |
| 11946 match(Set cr (CmpI op1 op2)); | |
| 11947 effect( DEF cr, USE op1, USE op2 ); | |
| 11948 format %{ "CMP $op1,$op2" %} | |
| 11949 opcode(0x3B); /* Opcode 3B /r */ | |
| 11950 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 11951 ins_pipe( ialu_cr_reg_reg ); | |
| 11952 %} | |
| 11953 | |
| 11954 instruct compI_eReg_imm(eFlagsReg cr, eRegI op1, immI op2) %{ | |
| 11955 match(Set cr (CmpI op1 op2)); | |
| 11956 effect( DEF cr, USE op1 ); | |
| 11957 format %{ "CMP $op1,$op2" %} | |
| 11958 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 11959 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */ | |
| 11960 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 11961 ins_pipe( ialu_cr_reg_imm ); | |
| 11962 %} | |
| 11963 | |
| 11964 // Cisc-spilled version of cmpI_eReg | |
| 11965 instruct compI_eReg_mem(eFlagsReg cr, eRegI op1, memory op2) %{ | |
| 11966 match(Set cr (CmpI op1 (LoadI op2))); | |
| 11967 | |
| 11968 format %{ "CMP $op1,$op2" %} | |
| 11969 ins_cost(500); | |
| 11970 opcode(0x3B); /* Opcode 3B /r */ | |
| 11971 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 11972 ins_pipe( ialu_cr_reg_mem ); | |
| 11973 %} | |
| 11974 | |
| 11975 instruct testI_reg( eFlagsReg cr, eRegI src, immI0 zero ) %{ | |
| 11976 match(Set cr (CmpI src zero)); | |
| 11977 effect( DEF cr, USE src ); | |
| 11978 | |
| 11979 format %{ "TEST $src,$src" %} | |
| 11980 opcode(0x85); | |
| 11981 ins_encode( OpcP, RegReg( src, src ) ); | |
| 11982 ins_pipe( ialu_cr_reg_imm ); | |
| 11983 %} | |
| 11984 | |
| 11985 instruct testI_reg_imm( eFlagsReg cr, eRegI src, immI con, immI0 zero ) %{ | |
| 11986 match(Set cr (CmpI (AndI src con) zero)); | |
| 11987 | |
| 11988 format %{ "TEST $src,$con" %} | |
| 11989 opcode(0xF7,0x00); | |
| 11990 ins_encode( OpcP, RegOpc(src), Con32(con) ); | |
| 11991 ins_pipe( ialu_cr_reg_imm ); | |
| 11992 %} | |
| 11993 | |
| 11994 instruct testI_reg_mem( eFlagsReg cr, eRegI src, memory mem, immI0 zero ) %{ | |
| 11995 match(Set cr (CmpI (AndI src mem) zero)); | |
| 11996 | |
| 11997 format %{ "TEST $src,$mem" %} | |
| 11998 opcode(0x85); | |
| 11999 ins_encode( OpcP, RegMem( src, mem ) ); | |
| 12000 ins_pipe( ialu_cr_reg_mem ); | |
| 12001 %} | |
| 12002 | |
| 12003 // Unsigned compare Instructions; really, same as signed except they | |
| 12004 // produce an eFlagsRegU instead of eFlagsReg. | |
| 12005 instruct compU_eReg(eFlagsRegU cr, eRegI op1, eRegI op2) %{ | |
| 12006 match(Set cr (CmpU op1 op2)); | |
| 12007 | |
| 12008 format %{ "CMPu $op1,$op2" %} | |
| 12009 opcode(0x3B); /* Opcode 3B /r */ | |
| 12010 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 12011 ins_pipe( ialu_cr_reg_reg ); | |
| 12012 %} | |
| 12013 | |
| 12014 instruct compU_eReg_imm(eFlagsRegU cr, eRegI op1, immI op2) %{ | |
| 12015 match(Set cr (CmpU op1 op2)); | |
| 12016 | |
| 12017 format %{ "CMPu $op1,$op2" %} | |
| 12018 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 12019 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 12020 ins_pipe( ialu_cr_reg_imm ); | |
| 12021 %} | |
| 12022 | |
| 12023 // // Cisc-spilled version of cmpU_eReg | |
| 12024 instruct compU_eReg_mem(eFlagsRegU cr, eRegI op1, memory op2) %{ | |
| 12025 match(Set cr (CmpU op1 (LoadI op2))); | |
| 12026 | |
| 12027 format %{ "CMPu $op1,$op2" %} | |
| 12028 ins_cost(500); | |
| 12029 opcode(0x3B); /* Opcode 3B /r */ | |
| 12030 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 12031 ins_pipe( ialu_cr_reg_mem ); | |
| 12032 %} | |
| 12033 | |
| 12034 // // Cisc-spilled version of cmpU_eReg | |
| 12035 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, eRegI op2) %{ | |
| 12036 // match(Set cr (CmpU (LoadI op1) op2)); | |
| 12037 // | |
| 12038 // format %{ "CMPu $op1,$op2" %} | |
| 12039 // ins_cost(500); | |
| 12040 // opcode(0x39); /* Opcode 39 /r */ | |
| 12041 // ins_encode( OpcP, RegMem( op1, op2) ); | |
| 12042 //%} | |
| 12043 | |
| 12044 instruct testU_reg( eFlagsRegU cr, eRegI src, immI0 zero ) %{ | |
| 12045 match(Set cr (CmpU src zero)); | |
| 12046 | |
| 12047 format %{ "TESTu $src,$src" %} | |
| 12048 opcode(0x85); | |
| 12049 ins_encode( OpcP, RegReg( src, src ) ); | |
| 12050 ins_pipe( ialu_cr_reg_imm ); | |
| 12051 %} | |
| 12052 | |
| 12053 // Unsigned pointer compare Instructions | |
| 12054 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{ | |
| 12055 match(Set cr (CmpP op1 op2)); | |
| 12056 | |
| 12057 format %{ "CMPu $op1,$op2" %} | |
| 12058 opcode(0x3B); /* Opcode 3B /r */ | |
| 12059 ins_encode( OpcP, RegReg( op1, op2) ); | |
| 12060 ins_pipe( ialu_cr_reg_reg ); | |
| 12061 %} | |
| 12062 | |
| 12063 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{ | |
| 12064 match(Set cr (CmpP op1 op2)); | |
| 12065 | |
| 12066 format %{ "CMPu $op1,$op2" %} | |
| 12067 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 12068 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); | |
| 12069 ins_pipe( ialu_cr_reg_imm ); | |
| 12070 %} | |
| 12071 | |
| 12072 // // Cisc-spilled version of cmpP_eReg | |
| 12073 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{ | |
| 12074 match(Set cr (CmpP op1 (LoadP op2))); | |
| 12075 | |
| 12076 format %{ "CMPu $op1,$op2" %} | |
| 12077 ins_cost(500); | |
| 12078 opcode(0x3B); /* Opcode 3B /r */ | |
| 12079 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 12080 ins_pipe( ialu_cr_reg_mem ); | |
| 12081 %} | |
| 12082 | |
| 12083 // // Cisc-spilled version of cmpP_eReg | |
| 12084 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{ | |
| 12085 // match(Set cr (CmpP (LoadP op1) op2)); | |
| 12086 // | |
| 12087 // format %{ "CMPu $op1,$op2" %} | |
| 12088 // ins_cost(500); | |
| 12089 // opcode(0x39); /* Opcode 39 /r */ | |
| 12090 // ins_encode( OpcP, RegMem( op1, op2) ); | |
| 12091 //%} | |
| 12092 | |
| 12093 // Compare raw pointer (used in out-of-heap check). | |
| 12094 // Only works because non-oop pointers must be raw pointers | |
| 12095 // and raw pointers have no anti-dependencies. | |
| 12096 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{ | |
| 12097 predicate( !n->in(2)->in(2)->bottom_type()->isa_oop_ptr() ); | |
| 12098 match(Set cr (CmpP op1 (LoadP op2))); | |
| 12099 | |
| 12100 format %{ "CMPu $op1,$op2" %} | |
| 12101 opcode(0x3B); /* Opcode 3B /r */ | |
| 12102 ins_encode( OpcP, RegMem( op1, op2) ); | |
| 12103 ins_pipe( ialu_cr_reg_mem ); | |
| 12104 %} | |
| 12105 | |
| 12106 // | |
| 12107 // This will generate a signed flags result. This should be ok | |
| 12108 // since any compare to a zero should be eq/neq. | |
| 12109 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{ | |
| 12110 match(Set cr (CmpP src zero)); | |
| 12111 | |
| 12112 format %{ "TEST $src,$src" %} | |
| 12113 opcode(0x85); | |
| 12114 ins_encode( OpcP, RegReg( src, src ) ); | |
| 12115 ins_pipe( ialu_cr_reg_imm ); | |
| 12116 %} | |
| 12117 | |
| 12118 // Cisc-spilled version of testP_reg | |
| 12119 // This will generate a signed flags result. This should be ok | |
| 12120 // since any compare to a zero should be eq/neq. | |
| 12121 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{ | |
| 12122 match(Set cr (CmpP (LoadP op) zero)); | |
| 12123 | |
| 12124 format %{ "TEST $op,0xFFFFFFFF" %} | |
| 12125 ins_cost(500); | |
| 12126 opcode(0xF7); /* Opcode F7 /0 */ | |
| 12127 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) ); | |
| 12128 ins_pipe( ialu_cr_reg_imm ); | |
| 12129 %} | |
| 12130 | |
| 12131 // Yanked all unsigned pointer compare operations. | |
| 12132 // Pointer compares are done with CmpP which is already unsigned. | |
| 12133 | |
| 12134 //----------Max and Min-------------------------------------------------------- | |
| 12135 // Min Instructions | |
| 12136 //// | |
| 12137 // *** Min and Max using the conditional move are slower than the | |
| 12138 // *** branch version on a Pentium III. | |
| 12139 // // Conditional move for min | |
| 12140 //instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{ | |
| 12141 // effect( USE_DEF op2, USE op1, USE cr ); | |
| 12142 // format %{ "CMOVlt $op2,$op1\t! min" %} | |
| 12143 // opcode(0x4C,0x0F); | |
| 12144 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); | |
| 12145 // ins_pipe( pipe_cmov_reg ); | |
| 12146 //%} | |
| 12147 // | |
| 12148 //// Min Register with Register (P6 version) | |
| 12149 //instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{ | |
| 12150 // predicate(VM_Version::supports_cmov() ); | |
| 12151 // match(Set op2 (MinI op1 op2)); | |
| 12152 // ins_cost(200); | |
| 12153 // expand %{ | |
| 12154 // eFlagsReg cr; | |
| 12155 // compI_eReg(cr,op1,op2); | |
| 12156 // cmovI_reg_lt(op2,op1,cr); | |
| 12157 // %} | |
| 12158 //%} | |
| 12159 | |
| 12160 // Min Register with Register (generic version) | |
| 12161 instruct minI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{ | |
| 12162 match(Set dst (MinI dst src)); | |
| 12163 effect(KILL flags); | |
| 12164 ins_cost(300); | |
| 12165 | |
| 12166 format %{ "MIN $dst,$src" %} | |
| 12167 opcode(0xCC); | |
| 12168 ins_encode( min_enc(dst,src) ); | |
| 12169 ins_pipe( pipe_slow ); | |
| 12170 %} | |
| 12171 | |
| 12172 // Max Register with Register | |
| 12173 // *** Min and Max using the conditional move are slower than the | |
| 12174 // *** branch version on a Pentium III. | |
| 12175 // // Conditional move for max | |
| 12176 //instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{ | |
| 12177 // effect( USE_DEF op2, USE op1, USE cr ); | |
| 12178 // format %{ "CMOVgt $op2,$op1\t! max" %} | |
| 12179 // opcode(0x4F,0x0F); | |
| 12180 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); | |
| 12181 // ins_pipe( pipe_cmov_reg ); | |
| 12182 //%} | |
| 12183 // | |
| 12184 // // Max Register with Register (P6 version) | |
| 12185 //instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{ | |
| 12186 // predicate(VM_Version::supports_cmov() ); | |
| 12187 // match(Set op2 (MaxI op1 op2)); | |
| 12188 // ins_cost(200); | |
| 12189 // expand %{ | |
| 12190 // eFlagsReg cr; | |
| 12191 // compI_eReg(cr,op1,op2); | |
| 12192 // cmovI_reg_gt(op2,op1,cr); | |
| 12193 // %} | |
| 12194 //%} | |
| 12195 | |
| 12196 // Max Register with Register (generic version) | |
| 12197 instruct maxI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{ | |
| 12198 match(Set dst (MaxI dst src)); | |
| 12199 effect(KILL flags); | |
| 12200 ins_cost(300); | |
| 12201 | |
| 12202 format %{ "MAX $dst,$src" %} | |
| 12203 opcode(0xCC); | |
| 12204 ins_encode( max_enc(dst,src) ); | |
| 12205 ins_pipe( pipe_slow ); | |
| 12206 %} | |
| 12207 | |
| 12208 // ============================================================================ | |
| 3345 | 12209 // Counted Loop limit node which represents exact final iterator value. |
| 12210 // Note: the resulting value should fit into integer range since | |
| 12211 // counted loops have limit check on overflow. | |
| 12212 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{ | |
| 12213 match(Set limit (LoopLimit (Binary init limit) stride)); | |
| 12214 effect(TEMP limit_hi, TEMP tmp, KILL flags); | |
| 12215 ins_cost(300); | |
| 12216 | |
| 12217 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %} | |
| 12218 ins_encode %{ | |
| 12219 int strd = (int)$stride$$constant; | |
| 12220 assert(strd != 1 && strd != -1, "sanity"); | |
| 12221 int m1 = (strd > 0) ? 1 : -1; | |
| 12222 // Convert limit to long (EAX:EDX) | |
| 12223 __ cdql(); | |
| 12224 // Convert init to long (init:tmp) | |
| 12225 __ movl($tmp$$Register, $init$$Register); | |
| 12226 __ sarl($tmp$$Register, 31); | |
| 12227 // $limit - $init | |
| 12228 __ subl($limit$$Register, $init$$Register); | |
| 12229 __ sbbl($limit_hi$$Register, $tmp$$Register); | |
| 12230 // + ($stride - 1) | |
| 12231 if (strd > 0) { | |
| 12232 __ addl($limit$$Register, (strd - 1)); | |
| 12233 __ adcl($limit_hi$$Register, 0); | |
| 12234 __ movl($tmp$$Register, strd); | |
| 12235 } else { | |
| 12236 __ addl($limit$$Register, (strd + 1)); | |
| 12237 __ adcl($limit_hi$$Register, -1); | |
| 12238 __ lneg($limit_hi$$Register, $limit$$Register); | |
| 12239 __ movl($tmp$$Register, -strd); | |
| 12240 } | |
| 12241 // signed devision: (EAX:EDX) / pos_stride | |
| 12242 __ idivl($tmp$$Register); | |
| 12243 if (strd < 0) { | |
| 12244 // restore sign | |
| 12245 __ negl($tmp$$Register); | |
| 12246 } | |
| 12247 // (EAX) * stride | |
| 12248 __ mull($tmp$$Register); | |
| 12249 // + init (ignore upper bits) | |
| 12250 __ addl($limit$$Register, $init$$Register); | |
| 12251 %} | |
| 12252 ins_pipe( pipe_slow ); | |
| 12253 %} | |
| 12254 | |
| 12255 // ============================================================================ | |
| 0 | 12256 // Branch Instructions |
| 12257 // Jump Table | |
| 12258 instruct jumpXtnd(eRegI switch_val) %{ | |
| 12259 match(Jump switch_val); | |
| 12260 ins_cost(350); | |
| 2008 | 12261 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %} |
| 12262 ins_encode %{ | |
| 0 | 12263 // Jump to Address(table_base + switch_reg) |
| 12264 Address index(noreg, $switch_val$$Register, Address::times_1); | |
| 2008 | 12265 __ jump(ArrayAddress($constantaddress, index)); |
| 0 | 12266 %} |
| 12267 ins_pipe(pipe_jmp); | |
| 12268 %} | |
| 12269 | |
| 12270 // Jump Direct - Label defines a relative address from JMP+1 | |
| 12271 instruct jmpDir(label labl) %{ | |
| 12272 match(Goto); | |
| 12273 effect(USE labl); | |
| 12274 | |
| 12275 ins_cost(300); | |
| 12276 format %{ "JMP $labl" %} | |
| 12277 size(5); | |
| 3851 | 12278 ins_encode %{ |
| 12279 Label* L = $labl$$label; | |
| 12280 __ jmp(*L, false); // Always long jump | |
| 12281 %} | |
| 0 | 12282 ins_pipe( pipe_jmp ); |
| 12283 %} | |
| 12284 | |
| 12285 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12286 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 12287 match(If cop cr); | |
| 12288 effect(USE labl); | |
| 12289 | |
| 12290 ins_cost(300); | |
| 12291 format %{ "J$cop $labl" %} | |
| 12292 size(6); | |
| 3851 | 12293 ins_encode %{ |
| 12294 Label* L = $labl$$label; | |
| 12295 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12296 %} | |
| 0 | 12297 ins_pipe( pipe_jcc ); |
| 12298 %} | |
| 12299 | |
| 12300 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12301 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 12302 match(CountedLoopEnd cop cr); | |
| 12303 effect(USE labl); | |
| 12304 | |
| 12305 ins_cost(300); | |
| 12306 format %{ "J$cop $labl\t# Loop end" %} | |
| 12307 size(6); | |
| 3851 | 12308 ins_encode %{ |
| 12309 Label* L = $labl$$label; | |
| 12310 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12311 %} | |
| 0 | 12312 ins_pipe( pipe_jcc ); |
| 12313 %} | |
| 12314 | |
| 12315 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12316 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 12317 match(CountedLoopEnd cop cmp); | |
| 12318 effect(USE labl); | |
| 12319 | |
| 12320 ins_cost(300); | |
| 12321 format %{ "J$cop,u $labl\t# Loop end" %} | |
| 12322 size(6); | |
| 3851 | 12323 ins_encode %{ |
| 12324 Label* L = $labl$$label; | |
| 12325 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12326 %} | |
| 0 | 12327 ins_pipe( pipe_jcc ); |
| 12328 %} | |
| 12329 | |
|
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12330 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
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12331 match(CountedLoopEnd cop cmp); |
|
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12332 effect(USE labl); |
|
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diff
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12333 |
|
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12334 ins_cost(200); |
|
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|
12335 format %{ "J$cop,u $labl\t# Loop end" %} |
|
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|
12336 size(6); |
| 3851 | 12337 ins_encode %{ |
| 12338 Label* L = $labl$$label; | |
| 12339 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12340 %} | |
|
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12341 ins_pipe( pipe_jcc ); |
|
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|
12342 %} |
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12343 |
| 0 | 12344 // Jump Direct Conditional - using unsigned comparison |
| 12345 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 12346 match(If cop cmp); | |
| 12347 effect(USE labl); | |
| 12348 | |
| 12349 ins_cost(300); | |
| 12350 format %{ "J$cop,u $labl" %} | |
| 12351 size(6); | |
| 3851 | 12352 ins_encode %{ |
| 12353 Label* L = $labl$$label; | |
| 12354 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12355 %} | |
|
415
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|
12356 ins_pipe(pipe_jcc); |
|
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403
diff
changeset
|
12357 %} |
|
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parents:
403
diff
changeset
|
12358 |
|
4d9884b01ba6
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diff
changeset
|
12359 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
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diff
changeset
|
12360 match(If cop cmp); |
|
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diff
changeset
|
12361 effect(USE labl); |
|
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403
diff
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|
12362 |
|
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diff
changeset
|
12363 ins_cost(200); |
|
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diff
changeset
|
12364 format %{ "J$cop,u $labl" %} |
|
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never
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diff
changeset
|
12365 size(6); |
| 3851 | 12366 ins_encode %{ |
| 12367 Label* L = $labl$$label; | |
| 12368 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump | |
| 12369 %} | |
|
415
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|
12370 ins_pipe(pipe_jcc); |
|
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diff
changeset
|
12371 %} |
|
4d9884b01ba6
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403
diff
changeset
|
12372 |
|
4d9884b01ba6
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never
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diff
changeset
|
12373 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
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403
diff
changeset
|
12374 match(If cop cmp); |
|
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never
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403
diff
changeset
|
12375 effect(USE labl); |
|
4d9884b01ba6
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403
diff
changeset
|
12376 |
|
4d9884b01ba6
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diff
changeset
|
12377 ins_cost(200); |
|
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diff
changeset
|
12378 format %{ $$template |
|
4d9884b01ba6
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never
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diff
changeset
|
12379 if ($cop$$cmpcode == Assembler::notEqual) { |
|
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|
12380 $$emit$$"JP,u $labl\n\t" |
|
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|
12381 $$emit$$"J$cop,u $labl" |
|
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changeset
|
12382 } else { |
|
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changeset
|
12383 $$emit$$"JP,u done\n\t" |
|
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changeset
|
12384 $$emit$$"J$cop,u $labl\n\t" |
|
4d9884b01ba6
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changeset
|
12385 $$emit$$"done:" |
|
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diff
changeset
|
12386 } |
|
4d9884b01ba6
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never
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diff
changeset
|
12387 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
12388 ins_encode %{ |
|
4d9884b01ba6
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diff
changeset
|
12389 Label* l = $labl$$label; |
|
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never
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diff
changeset
|
12390 if ($cop$$cmpcode == Assembler::notEqual) { |
| 3851 | 12391 __ jcc(Assembler::parity, *l, false); |
| 12392 __ jcc(Assembler::notEqual, *l, false); | |
|
415
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|
12393 } else if ($cop$$cmpcode == Assembler::equal) { |
| 3851 | 12394 Label done; |
| 12395 __ jccb(Assembler::parity, done); | |
| 12396 __ jcc(Assembler::equal, *l, false); | |
| 12397 __ bind(done); | |
|
415
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changeset
|
12398 } else { |
|
4d9884b01ba6
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diff
changeset
|
12399 ShouldNotReachHere(); |
|
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diff
changeset
|
12400 } |
|
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diff
changeset
|
12401 %} |
|
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changeset
|
12402 ins_pipe(pipe_jcc); |
| 0 | 12403 %} |
| 12404 | |
| 12405 // ============================================================================ | |
| 12406 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass | |
| 12407 // array for an instance of the superklass. Set a hidden internal cache on a | |
| 12408 // hit (cache is checked with exposed code in gen_subtype_check()). Return | |
| 12409 // NZ for a miss or zero for a hit. The encoding ALSO sets flags. | |
| 12410 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{ | |
| 12411 match(Set result (PartialSubtypeCheck sub super)); | |
| 12412 effect( KILL rcx, KILL cr ); | |
| 12413 | |
| 12414 ins_cost(1100); // slightly larger than the next version | |
|
644
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
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changeset
|
12415 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t" |
| 0 | 12416 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t" |
| 12417 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t" | |
| 12418 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t" | |
| 12419 "JNE,s miss\t\t# Missed: EDI not-zero\n\t" | |
| 12420 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t" | |
| 12421 "XOR $result,$result\t\t Hit: EDI zero\n\t" | |
| 12422 "miss:\t" %} | |
| 12423 | |
| 12424 opcode(0x1); // Force a XOR of EDI | |
| 12425 ins_encode( enc_PartialSubtypeCheck() ); | |
| 12426 ins_pipe( pipe_slow ); | |
| 12427 %} | |
| 12428 | |
| 12429 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{ | |
| 12430 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero)); | |
| 12431 effect( KILL rcx, KILL result ); | |
| 12432 | |
| 12433 ins_cost(1000); | |
|
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changeset
|
12434 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t" |
| 0 | 12435 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t" |
| 12436 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t" | |
| 12437 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t" | |
| 12438 "JNE,s miss\t\t# Missed: flags NZ\n\t" | |
| 12439 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t" | |
| 12440 "miss:\t" %} | |
| 12441 | |
| 12442 opcode(0x0); // No need to XOR EDI | |
| 12443 ins_encode( enc_PartialSubtypeCheck() ); | |
| 12444 ins_pipe( pipe_slow ); | |
| 12445 %} | |
| 12446 | |
| 12447 // ============================================================================ | |
| 12448 // Branch Instructions -- short offset versions | |
| 12449 // | |
| 12450 // These instructions are used to replace jumps of a long offset (the default | |
| 12451 // match) with jumps of a shorter offset. These instructions are all tagged | |
| 12452 // with the ins_short_branch attribute, which causes the ADLC to suppress the | |
| 12453 // match rules in general matching. Instead, the ADLC generates a conversion | |
| 12454 // method in the MachNode which can be used to do in-place replacement of the | |
| 12455 // long variant with the shorter variant. The compiler will determine if a | |
| 12456 // branch can be taken by the is_short_branch_offset() predicate in the machine | |
| 12457 // specific code section of the file. | |
| 12458 | |
| 12459 // Jump Direct - Label defines a relative address from JMP+1 | |
| 12460 instruct jmpDir_short(label labl) %{ | |
| 12461 match(Goto); | |
| 12462 effect(USE labl); | |
| 12463 | |
| 12464 ins_cost(300); | |
| 12465 format %{ "JMP,s $labl" %} | |
| 12466 size(2); | |
| 3851 | 12467 ins_encode %{ |
| 12468 Label* L = $labl$$label; | |
| 12469 __ jmpb(*L); | |
| 12470 %} | |
| 0 | 12471 ins_pipe( pipe_jmp ); |
| 12472 ins_short_branch(1); | |
| 12473 %} | |
| 12474 | |
| 12475 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12476 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 12477 match(If cop cr); | |
| 12478 effect(USE labl); | |
| 12479 | |
| 12480 ins_cost(300); | |
| 12481 format %{ "J$cop,s $labl" %} | |
| 12482 size(2); | |
| 3851 | 12483 ins_encode %{ |
| 12484 Label* L = $labl$$label; | |
| 12485 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12486 %} | |
| 0 | 12487 ins_pipe( pipe_jcc ); |
| 12488 ins_short_branch(1); | |
| 12489 %} | |
| 12490 | |
| 12491 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12492 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{ | |
| 12493 match(CountedLoopEnd cop cr); | |
| 12494 effect(USE labl); | |
| 12495 | |
| 12496 ins_cost(300); | |
|
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diff
changeset
|
12497 format %{ "J$cop,s $labl\t# Loop end" %} |
| 0 | 12498 size(2); |
| 3851 | 12499 ins_encode %{ |
| 12500 Label* L = $labl$$label; | |
| 12501 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12502 %} | |
| 0 | 12503 ins_pipe( pipe_jcc ); |
| 12504 ins_short_branch(1); | |
| 12505 %} | |
| 12506 | |
| 12507 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12508 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 12509 match(CountedLoopEnd cop cmp); | |
| 12510 effect(USE labl); | |
| 12511 | |
| 12512 ins_cost(300); | |
|
415
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6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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403
diff
changeset
|
12513 format %{ "J$cop,us $labl\t# Loop end" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12514 size(2); |
| 3851 | 12515 ins_encode %{ |
| 12516 Label* L = $labl$$label; | |
| 12517 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12518 %} | |
|
415
4d9884b01ba6
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diff
changeset
|
12519 ins_pipe( pipe_jcc ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12520 ins_short_branch(1); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
12521 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
12522 |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
12523 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
12524 match(CountedLoopEnd cop cmp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12525 effect(USE labl); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12526 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12527 ins_cost(300); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12528 format %{ "J$cop,us $labl\t# Loop end" %} |
| 0 | 12529 size(2); |
| 3851 | 12530 ins_encode %{ |
| 12531 Label* L = $labl$$label; | |
| 12532 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12533 %} | |
| 0 | 12534 ins_pipe( pipe_jcc ); |
| 12535 ins_short_branch(1); | |
| 12536 %} | |
| 12537 | |
| 12538 // Jump Direct Conditional - using unsigned comparison | |
| 12539 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{ | |
| 12540 match(If cop cmp); | |
| 12541 effect(USE labl); | |
| 12542 | |
| 12543 ins_cost(300); | |
| 12544 format %{ "J$cop,us $labl" %} | |
| 12545 size(2); | |
| 3851 | 12546 ins_encode %{ |
| 12547 Label* L = $labl$$label; | |
| 12548 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12549 %} | |
| 0 | 12550 ins_pipe( pipe_jcc ); |
| 12551 ins_short_branch(1); | |
| 12552 %} | |
| 12553 | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12554 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12555 match(If cop cmp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12556 effect(USE labl); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12557 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12558 ins_cost(300); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12559 format %{ "J$cop,us $labl" %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12560 size(2); |
| 3851 | 12561 ins_encode %{ |
| 12562 Label* L = $labl$$label; | |
| 12563 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); | |
| 12564 %} | |
|
415
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
12565 ins_pipe( pipe_jcc ); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12566 ins_short_branch(1); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12567 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12568 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12569 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
12570 match(If cop cmp); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12571 effect(USE labl); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12572 |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12573 ins_cost(300); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12574 format %{ $$template |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12575 if ($cop$$cmpcode == Assembler::notEqual) { |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
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parents:
403
diff
changeset
|
12576 $$emit$$"JP,u,s $labl\n\t" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12577 $$emit$$"J$cop,u,s $labl" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12578 } else { |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
12579 $$emit$$"JP,u,s done\n\t" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12580 $$emit$$"J$cop,u,s $labl\n\t" |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12581 $$emit$$"done:" |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
12582 } |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
12583 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12584 size(4); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
12585 ins_encode %{ |
|
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12586 Label* l = $labl$$label; |
|
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|
12587 if ($cop$$cmpcode == Assembler::notEqual) { |
| 3851 | 12588 __ jccb(Assembler::parity, *l); |
| 12589 __ jccb(Assembler::notEqual, *l); | |
|
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|
12590 } else if ($cop$$cmpcode == Assembler::equal) { |
| 3851 | 12591 Label done; |
| 12592 __ jccb(Assembler::parity, done); | |
| 12593 __ jccb(Assembler::equal, *l); | |
| 12594 __ bind(done); | |
|
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12595 } else { |
| 3851 | 12596 ShouldNotReachHere(); |
| 12597 } | |
|
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|
12598 %} |
|
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|
12599 ins_pipe(pipe_jcc); |
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12600 ins_short_branch(1); |
|
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|
12601 %} |
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|
12602 |
| 0 | 12603 // ============================================================================ |
| 12604 // Long Compare | |
| 12605 // | |
| 12606 // Currently we hold longs in 2 registers. Comparing such values efficiently | |
| 12607 // is tricky. The flavor of compare used depends on whether we are testing | |
| 12608 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. | |
| 12609 // The GE test is the negated LT test. The LE test can be had by commuting | |
| 12610 // the operands (yielding a GE test) and then negating; negate again for the | |
| 12611 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the | |
| 12612 // NE test is negated from that. | |
| 12613 | |
| 12614 // Due to a shortcoming in the ADLC, it mixes up expressions like: | |
| 12615 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the | |
| 12616 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections | |
| 12617 // are collapsed internally in the ADLC's dfa-gen code. The match for | |
| 12618 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the | |
| 12619 // foo match ends up with the wrong leaf. One fix is to not match both | |
| 12620 // reg-reg and reg-zero forms of long-compare. This is unfortunate because | |
| 12621 // both forms beat the trinary form of long-compare and both are very useful | |
| 12622 // on Intel which has so few registers. | |
| 12623 | |
| 12624 // Manifest a CmpL result in an integer register. Very painful. | |
| 12625 // This is the test to avoid. | |
| 12626 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{ | |
| 12627 match(Set dst (CmpL3 src1 src2)); | |
| 12628 effect( KILL flags ); | |
| 12629 ins_cost(1000); | |
| 12630 format %{ "XOR $dst,$dst\n\t" | |
| 12631 "CMP $src1.hi,$src2.hi\n\t" | |
| 12632 "JLT,s m_one\n\t" | |
| 12633 "JGT,s p_one\n\t" | |
| 12634 "CMP $src1.lo,$src2.lo\n\t" | |
| 12635 "JB,s m_one\n\t" | |
| 12636 "JEQ,s done\n" | |
| 12637 "p_one:\tINC $dst\n\t" | |
| 12638 "JMP,s done\n" | |
| 12639 "m_one:\tDEC $dst\n" | |
| 12640 "done:" %} | |
| 12641 ins_encode %{ | |
| 12642 Label p_one, m_one, done; | |
| 304 | 12643 __ xorptr($dst$$Register, $dst$$Register); |
| 0 | 12644 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register)); |
| 12645 __ jccb(Assembler::less, m_one); | |
| 12646 __ jccb(Assembler::greater, p_one); | |
| 12647 __ cmpl($src1$$Register, $src2$$Register); | |
| 12648 __ jccb(Assembler::below, m_one); | |
| 12649 __ jccb(Assembler::equal, done); | |
| 12650 __ bind(p_one); | |
| 304 | 12651 __ incrementl($dst$$Register); |
| 0 | 12652 __ jmpb(done); |
| 12653 __ bind(m_one); | |
| 304 | 12654 __ decrementl($dst$$Register); |
| 0 | 12655 __ bind(done); |
| 12656 %} | |
| 12657 ins_pipe( pipe_slow ); | |
| 12658 %} | |
| 12659 | |
| 12660 //====== | |
| 12661 // Manifest a CmpL result in the normal flags. Only good for LT or GE | |
| 12662 // compares. Can be used for LE or GT compares by reversing arguments. | |
| 12663 // NOT GOOD FOR EQ/NE tests. | |
| 12664 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{ | |
| 12665 match( Set flags (CmpL src zero )); | |
| 12666 ins_cost(100); | |
| 12667 format %{ "TEST $src.hi,$src.hi" %} | |
| 12668 opcode(0x85); | |
| 12669 ins_encode( OpcP, RegReg_Hi2( src, src ) ); | |
| 12670 ins_pipe( ialu_cr_reg_reg ); | |
| 12671 %} | |
| 12672 | |
| 12673 // Manifest a CmpL result in the normal flags. Only good for LT or GE | |
| 12674 // compares. Can be used for LE or GT compares by reversing arguments. | |
| 12675 // NOT GOOD FOR EQ/NE tests. | |
| 12676 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, eRegI tmp ) %{ | |
| 12677 match( Set flags (CmpL src1 src2 )); | |
| 12678 effect( TEMP tmp ); | |
| 12679 ins_cost(300); | |
| 12680 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t" | |
| 12681 "MOV $tmp,$src1.hi\n\t" | |
| 12682 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %} | |
| 12683 ins_encode( long_cmp_flags2( src1, src2, tmp ) ); | |
| 12684 ins_pipe( ialu_cr_reg_reg ); | |
| 12685 %} | |
| 12686 | |
| 12687 // Long compares reg < zero/req OR reg >= zero/req. | |
| 12688 // Just a wrapper for a normal branch, plus the predicate test. | |
| 12689 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{ | |
| 12690 match(If cmp flags); | |
| 12691 effect(USE labl); | |
| 12692 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); | |
| 12693 expand %{ | |
| 12694 jmpCon(cmp,flags,labl); // JLT or JGE... | |
| 12695 %} | |
| 12696 %} | |
| 12697 | |
| 12698 // Compare 2 longs and CMOVE longs. | |
| 12699 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{ | |
| 12700 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 12701 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 12702 ins_cost(400); | |
| 12703 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12704 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12705 opcode(0x0F,0x40); | |
| 12706 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 12707 ins_pipe( pipe_cmov_reg_long ); | |
| 12708 %} | |
| 12709 | |
| 12710 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{ | |
| 12711 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 12712 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 12713 ins_cost(500); | |
| 12714 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12715 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12716 opcode(0x0F,0x40); | |
| 12717 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 12718 ins_pipe( pipe_cmov_reg_long ); | |
| 12719 %} | |
| 12720 | |
| 12721 // Compare 2 longs and CMOVE ints. | |
| 12722 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, eRegI src) %{ | |
| 12723 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 12724 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 12725 ins_cost(200); | |
| 12726 format %{ "CMOV$cmp $dst,$src" %} | |
| 12727 opcode(0x0F,0x40); | |
| 12728 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12729 ins_pipe( pipe_cmov_reg ); | |
| 12730 %} | |
| 12731 | |
| 12732 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, memory src) %{ | |
| 12733 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 12734 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 12735 ins_cost(250); | |
| 12736 format %{ "CMOV$cmp $dst,$src" %} | |
| 12737 opcode(0x0F,0x40); | |
| 12738 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 12739 ins_pipe( pipe_cmov_mem ); | |
| 12740 %} | |
| 12741 | |
| 12742 // Compare 2 longs and CMOVE ints. | |
| 12743 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{ | |
| 12744 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); | |
| 12745 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 12746 ins_cost(200); | |
| 12747 format %{ "CMOV$cmp $dst,$src" %} | |
| 12748 opcode(0x0F,0x40); | |
| 12749 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12750 ins_pipe( pipe_cmov_reg ); | |
| 12751 %} | |
| 12752 | |
| 12753 // Compare 2 longs and CMOVE doubles | |
|
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12754 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{ |
| 0 | 12755 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); |
| 12756 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12757 ins_cost(200); | |
| 12758 expand %{ | |
|
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12759 fcmovDPR_regS(cmp,flags,dst,src); |
| 0 | 12760 %} |
| 12761 %} | |
| 12762 | |
| 12763 // Compare 2 longs and CMOVE doubles | |
|
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12764 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{ |
| 0 | 12765 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); |
| 12766 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12767 ins_cost(200); | |
| 12768 expand %{ | |
|
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12769 fcmovD_regS(cmp,flags,dst,src); |
|
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12770 %} |
|
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|
12771 %} |
|
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|
12772 |
|
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12773 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{ |
|
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12774 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); |
|
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12775 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
|
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12776 ins_cost(200); |
|
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|
12777 expand %{ |
|
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|
12778 fcmovFPR_regS(cmp,flags,dst,src); |
| 0 | 12779 %} |
| 12780 %} | |
| 12781 | |
| 12782 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{ | |
|
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12783 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); |
| 0 | 12784 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
| 12785 ins_cost(200); | |
| 12786 expand %{ | |
| 12787 fcmovF_regS(cmp,flags,dst,src); | |
| 12788 %} | |
| 12789 %} | |
| 12790 | |
| 12791 //====== | |
| 12792 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. | |
| 12793 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, eRegI tmp ) %{ | |
| 12794 match( Set flags (CmpL src zero )); | |
| 12795 effect(TEMP tmp); | |
| 12796 ins_cost(200); | |
| 12797 format %{ "MOV $tmp,$src.lo\n\t" | |
| 12798 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %} | |
| 12799 ins_encode( long_cmp_flags0( src, tmp ) ); | |
| 12800 ins_pipe( ialu_reg_reg_long ); | |
| 12801 %} | |
| 12802 | |
| 12803 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. | |
| 12804 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{ | |
| 12805 match( Set flags (CmpL src1 src2 )); | |
| 12806 ins_cost(200+300); | |
| 12807 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t" | |
| 12808 "JNE,s skip\n\t" | |
| 12809 "CMP $src1.hi,$src2.hi\n\t" | |
| 12810 "skip:\t" %} | |
| 12811 ins_encode( long_cmp_flags1( src1, src2 ) ); | |
| 12812 ins_pipe( ialu_cr_reg_reg ); | |
| 12813 %} | |
| 12814 | |
| 12815 // Long compare reg == zero/reg OR reg != zero/reg | |
| 12816 // Just a wrapper for a normal branch, plus the predicate test. | |
| 12817 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{ | |
| 12818 match(If cmp flags); | |
| 12819 effect(USE labl); | |
| 12820 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); | |
| 12821 expand %{ | |
| 12822 jmpCon(cmp,flags,labl); // JEQ or JNE... | |
| 12823 %} | |
| 12824 %} | |
| 12825 | |
| 12826 // Compare 2 longs and CMOVE longs. | |
| 12827 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{ | |
| 12828 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 12829 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 12830 ins_cost(400); | |
| 12831 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12832 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12833 opcode(0x0F,0x40); | |
| 12834 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 12835 ins_pipe( pipe_cmov_reg_long ); | |
| 12836 %} | |
| 12837 | |
| 12838 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{ | |
| 12839 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 12840 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 12841 ins_cost(500); | |
| 12842 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12843 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12844 opcode(0x0F,0x40); | |
| 12845 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 12846 ins_pipe( pipe_cmov_reg_long ); | |
| 12847 %} | |
| 12848 | |
| 12849 // Compare 2 longs and CMOVE ints. | |
| 12850 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, eRegI src) %{ | |
| 12851 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 12852 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 12853 ins_cost(200); | |
| 12854 format %{ "CMOV$cmp $dst,$src" %} | |
| 12855 opcode(0x0F,0x40); | |
| 12856 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12857 ins_pipe( pipe_cmov_reg ); | |
| 12858 %} | |
| 12859 | |
| 12860 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, memory src) %{ | |
| 12861 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 12862 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 12863 ins_cost(250); | |
| 12864 format %{ "CMOV$cmp $dst,$src" %} | |
| 12865 opcode(0x0F,0x40); | |
| 12866 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 12867 ins_pipe( pipe_cmov_mem ); | |
| 12868 %} | |
| 12869 | |
| 12870 // Compare 2 longs and CMOVE ints. | |
| 12871 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{ | |
| 12872 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); | |
| 12873 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 12874 ins_cost(200); | |
| 12875 format %{ "CMOV$cmp $dst,$src" %} | |
| 12876 opcode(0x0F,0x40); | |
| 12877 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12878 ins_pipe( pipe_cmov_reg ); | |
| 12879 %} | |
| 12880 | |
| 12881 // Compare 2 longs and CMOVE doubles | |
|
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12882 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{ |
| 0 | 12883 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); |
| 12884 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12885 ins_cost(200); | |
| 12886 expand %{ | |
|
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12887 fcmovDPR_regS(cmp,flags,dst,src); |
| 0 | 12888 %} |
| 12889 %} | |
| 12890 | |
| 12891 // Compare 2 longs and CMOVE doubles | |
|
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12892 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{ |
| 0 | 12893 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); |
| 12894 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 12895 ins_cost(200); | |
| 12896 expand %{ | |
|
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12897 fcmovD_regS(cmp,flags,dst,src); |
|
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12898 %} |
|
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|
12899 %} |
|
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|
12900 |
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12901 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{ |
|
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12902 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); |
|
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12903 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
|
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12904 ins_cost(200); |
|
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|
12905 expand %{ |
|
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|
12906 fcmovFPR_regS(cmp,flags,dst,src); |
| 0 | 12907 %} |
| 12908 %} | |
| 12909 | |
| 12910 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{ | |
|
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12911 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); |
| 0 | 12912 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
| 12913 ins_cost(200); | |
| 12914 expand %{ | |
| 12915 fcmovF_regS(cmp,flags,dst,src); | |
| 12916 %} | |
| 12917 %} | |
| 12918 | |
| 12919 //====== | |
| 12920 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares. | |
| 12921 // Same as cmpL_reg_flags_LEGT except must negate src | |
| 12922 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, eRegI tmp ) %{ | |
| 12923 match( Set flags (CmpL src zero )); | |
| 12924 effect( TEMP tmp ); | |
| 12925 ins_cost(300); | |
| 12926 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t" | |
| 12927 "CMP $tmp,$src.lo\n\t" | |
| 12928 "SBB $tmp,$src.hi\n\t" %} | |
| 12929 ins_encode( long_cmp_flags3(src, tmp) ); | |
| 12930 ins_pipe( ialu_reg_reg_long ); | |
| 12931 %} | |
| 12932 | |
| 12933 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares. | |
| 12934 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands | |
| 12935 // requires a commuted test to get the same result. | |
| 12936 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, eRegI tmp ) %{ | |
| 12937 match( Set flags (CmpL src1 src2 )); | |
| 12938 effect( TEMP tmp ); | |
| 12939 ins_cost(300); | |
| 12940 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t" | |
| 12941 "MOV $tmp,$src2.hi\n\t" | |
| 12942 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %} | |
| 12943 ins_encode( long_cmp_flags2( src2, src1, tmp ) ); | |
| 12944 ins_pipe( ialu_cr_reg_reg ); | |
| 12945 %} | |
| 12946 | |
| 12947 // Long compares reg < zero/req OR reg >= zero/req. | |
| 12948 // Just a wrapper for a normal branch, plus the predicate test | |
| 12949 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{ | |
| 12950 match(If cmp flags); | |
| 12951 effect(USE labl); | |
| 12952 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le ); | |
| 12953 ins_cost(300); | |
| 12954 expand %{ | |
| 12955 jmpCon(cmp,flags,labl); // JGT or JLE... | |
| 12956 %} | |
| 12957 %} | |
| 12958 | |
| 12959 // Compare 2 longs and CMOVE longs. | |
| 12960 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{ | |
| 12961 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); | |
| 12962 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 12963 ins_cost(400); | |
| 12964 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12965 "CMOV$cmp $dst.hi,$src.hi" %} | |
| 12966 opcode(0x0F,0x40); | |
| 12967 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); | |
| 12968 ins_pipe( pipe_cmov_reg_long ); | |
| 12969 %} | |
| 12970 | |
| 12971 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{ | |
| 12972 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); | |
| 12973 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 12974 ins_cost(500); | |
| 12975 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" | |
| 12976 "CMOV$cmp $dst.hi,$src.hi+4" %} | |
| 12977 opcode(0x0F,0x40); | |
| 12978 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); | |
| 12979 ins_pipe( pipe_cmov_reg_long ); | |
| 12980 %} | |
| 12981 | |
| 12982 // Compare 2 longs and CMOVE ints. | |
| 12983 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, eRegI src) %{ | |
| 12984 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 12985 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); | |
| 12986 ins_cost(200); | |
| 12987 format %{ "CMOV$cmp $dst,$src" %} | |
| 12988 opcode(0x0F,0x40); | |
| 12989 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 12990 ins_pipe( pipe_cmov_reg ); | |
| 12991 %} | |
| 12992 | |
| 12993 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, memory src) %{ | |
| 12994 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 12995 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); | |
| 12996 ins_cost(250); | |
| 12997 format %{ "CMOV$cmp $dst,$src" %} | |
| 12998 opcode(0x0F,0x40); | |
| 12999 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); | |
| 13000 ins_pipe( pipe_cmov_mem ); | |
| 13001 %} | |
| 13002 | |
| 13003 // Compare 2 longs and CMOVE ptrs. | |
| 13004 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{ | |
| 13005 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); | |
| 13006 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); | |
| 13007 ins_cost(200); | |
| 13008 format %{ "CMOV$cmp $dst,$src" %} | |
| 13009 opcode(0x0F,0x40); | |
| 13010 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); | |
| 13011 ins_pipe( pipe_cmov_reg ); | |
| 13012 %} | |
| 13013 | |
| 13014 // Compare 2 longs and CMOVE doubles | |
|
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13015 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{ |
| 0 | 13016 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); |
| 13017 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 13018 ins_cost(200); | |
| 13019 expand %{ | |
|
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13020 fcmovDPR_regS(cmp,flags,dst,src); |
| 0 | 13021 %} |
| 13022 %} | |
| 13023 | |
| 13024 // Compare 2 longs and CMOVE doubles | |
|
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13025 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{ |
| 0 | 13026 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); |
| 13027 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); | |
| 13028 ins_cost(200); | |
| 13029 expand %{ | |
|
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13030 fcmovD_regS(cmp,flags,dst,src); |
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13031 %} |
|
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13032 %} |
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13033 |
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13034 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{ |
|
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13035 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); |
|
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13036 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
|
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13037 ins_cost(200); |
|
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13038 expand %{ |
|
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13039 fcmovFPR_regS(cmp,flags,dst,src); |
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13040 %} |
|
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|
13041 %} |
|
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13042 |
| 0 | 13043 |
| 13044 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{ | |
|
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13045 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); |
| 0 | 13046 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); |
| 13047 ins_cost(200); | |
| 13048 expand %{ | |
| 13049 fcmovF_regS(cmp,flags,dst,src); | |
| 13050 %} | |
| 13051 %} | |
| 13052 | |
| 13053 | |
| 13054 // ============================================================================ | |
| 13055 // Procedure Call/Return Instructions | |
| 13056 // Call Java Static Instruction | |
| 13057 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 13058 // compute_padding() functions will have to be adjusted. | |
| 13059 instruct CallStaticJavaDirect(method meth) %{ | |
| 13060 match(CallStaticJava); | |
|
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13061 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
| 0 | 13062 effect(USE meth); |
| 13063 | |
| 13064 ins_cost(300); | |
| 13065 format %{ "CALL,static " %} | |
| 13066 opcode(0xE8); /* E8 cd */ | |
| 13067 ins_encode( pre_call_FPU, | |
| 13068 Java_Static_Call( meth ), | |
| 13069 call_epilog, | |
| 13070 post_call_FPU ); | |
| 13071 ins_pipe( pipe_slow ); | |
| 13072 ins_alignment(4); | |
| 13073 %} | |
| 13074 | |
|
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|
13075 // Call Java Static Instruction (method handle version) |
|
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13076 // Note: If this code changes, the corresponding ret_addr_offset() and |
|
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|
13077 // compute_padding() functions will have to be adjusted. |
| 1567 | 13078 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{ |
|
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|
13079 match(CallStaticJava); |
|
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|
13080 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); |
|
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|
13081 effect(USE meth); |
|
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|
13082 // EBP is saved by all callees (for interpreter stack correction). |
|
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|
13083 // We use it here for a similar purpose, in {preserve,restore}_SP. |
|
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|
13084 |
|
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|
13085 ins_cost(300); |
|
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|
13086 format %{ "CALL,static/MethodHandle " %} |
|
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|
13087 opcode(0xE8); /* E8 cd */ |
|
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|
13088 ins_encode( pre_call_FPU, |
|
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|
13089 preserve_SP, |
|
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|
13090 Java_Static_Call( meth ), |
|
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|
13091 restore_SP, |
|
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|
13092 call_epilog, |
|
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13093 post_call_FPU ); |
|
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13094 ins_pipe( pipe_slow ); |
|
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13095 ins_alignment(4); |
|
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|
13096 %} |
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13097 |
| 0 | 13098 // Call Java Dynamic Instruction |
| 13099 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 13100 // compute_padding() functions will have to be adjusted. | |
| 13101 instruct CallDynamicJavaDirect(method meth) %{ | |
| 13102 match(CallDynamicJava); | |
| 13103 effect(USE meth); | |
| 13104 | |
| 13105 ins_cost(300); | |
| 13106 format %{ "MOV EAX,(oop)-1\n\t" | |
| 13107 "CALL,dynamic" %} | |
| 13108 opcode(0xE8); /* E8 cd */ | |
| 13109 ins_encode( pre_call_FPU, | |
| 13110 Java_Dynamic_Call( meth ), | |
| 13111 call_epilog, | |
| 13112 post_call_FPU ); | |
| 13113 ins_pipe( pipe_slow ); | |
| 13114 ins_alignment(4); | |
| 13115 %} | |
| 13116 | |
| 13117 // Call Runtime Instruction | |
| 13118 instruct CallRuntimeDirect(method meth) %{ | |
| 13119 match(CallRuntime ); | |
| 13120 effect(USE meth); | |
| 13121 | |
| 13122 ins_cost(300); | |
| 13123 format %{ "CALL,runtime " %} | |
| 13124 opcode(0xE8); /* E8 cd */ | |
| 13125 // Use FFREEs to clear entries in float stack | |
| 13126 ins_encode( pre_call_FPU, | |
| 13127 FFree_Float_Stack_All, | |
| 13128 Java_To_Runtime( meth ), | |
| 13129 post_call_FPU ); | |
| 13130 ins_pipe( pipe_slow ); | |
| 13131 %} | |
| 13132 | |
| 13133 // Call runtime without safepoint | |
| 13134 instruct CallLeafDirect(method meth) %{ | |
| 13135 match(CallLeaf); | |
| 13136 effect(USE meth); | |
| 13137 | |
| 13138 ins_cost(300); | |
| 13139 format %{ "CALL_LEAF,runtime " %} | |
| 13140 opcode(0xE8); /* E8 cd */ | |
| 13141 ins_encode( pre_call_FPU, | |
| 13142 FFree_Float_Stack_All, | |
| 13143 Java_To_Runtime( meth ), | |
| 13144 Verify_FPU_For_Leaf, post_call_FPU ); | |
| 13145 ins_pipe( pipe_slow ); | |
| 13146 %} | |
| 13147 | |
| 13148 instruct CallLeafNoFPDirect(method meth) %{ | |
| 13149 match(CallLeafNoFP); | |
| 13150 effect(USE meth); | |
| 13151 | |
| 13152 ins_cost(300); | |
| 13153 format %{ "CALL_LEAF_NOFP,runtime " %} | |
| 13154 opcode(0xE8); /* E8 cd */ | |
| 13155 ins_encode(Java_To_Runtime(meth)); | |
| 13156 ins_pipe( pipe_slow ); | |
| 13157 %} | |
| 13158 | |
| 13159 | |
| 13160 // Return Instruction | |
| 13161 // Remove the return address & jump to it. | |
| 13162 instruct Ret() %{ | |
| 13163 match(Return); | |
| 13164 format %{ "RET" %} | |
| 13165 opcode(0xC3); | |
| 13166 ins_encode(OpcP); | |
| 13167 ins_pipe( pipe_jmp ); | |
| 13168 %} | |
| 13169 | |
| 13170 // Tail Call; Jump from runtime stub to Java code. | |
| 13171 // Also known as an 'interprocedural jump'. | |
| 13172 // Target of jump will eventually return to caller. | |
| 13173 // TailJump below removes the return address. | |
| 13174 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{ | |
| 13175 match(TailCall jump_target method_oop ); | |
| 13176 ins_cost(300); | |
| 13177 format %{ "JMP $jump_target \t# EBX holds method oop" %} | |
| 13178 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 13179 ins_encode( OpcP, RegOpc(jump_target) ); | |
| 13180 ins_pipe( pipe_jmp ); | |
| 13181 %} | |
| 13182 | |
| 13183 | |
| 13184 // Tail Jump; remove the return address; jump to target. | |
| 13185 // TailCall above leaves the return address around. | |
| 13186 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{ | |
| 13187 match( TailJump jump_target ex_oop ); | |
| 13188 ins_cost(300); | |
| 13189 format %{ "POP EDX\t# pop return address into dummy\n\t" | |
| 13190 "JMP $jump_target " %} | |
| 13191 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 13192 ins_encode( enc_pop_rdx, | |
| 13193 OpcP, RegOpc(jump_target) ); | |
| 13194 ins_pipe( pipe_jmp ); | |
| 13195 %} | |
| 13196 | |
| 13197 // Create exception oop: created by stack-crawling runtime code. | |
| 13198 // Created exception is now available to this handler, and is setup | |
| 13199 // just prior to jumping to this handler. No code emitted. | |
| 13200 instruct CreateException( eAXRegP ex_oop ) | |
| 13201 %{ | |
| 13202 match(Set ex_oop (CreateEx)); | |
| 13203 | |
| 13204 size(0); | |
| 13205 // use the following format syntax | |
| 13206 format %{ "# exception oop is in EAX; no code emitted" %} | |
| 13207 ins_encode(); | |
| 13208 ins_pipe( empty ); | |
| 13209 %} | |
| 13210 | |
| 13211 | |
| 13212 // Rethrow exception: | |
| 13213 // The exception oop will come in the first argument position. | |
| 13214 // Then JUMP (not call) to the rethrow stub code. | |
| 13215 instruct RethrowException() | |
| 13216 %{ | |
| 13217 match(Rethrow); | |
| 13218 | |
| 13219 // use the following format syntax | |
| 13220 format %{ "JMP rethrow_stub" %} | |
| 13221 ins_encode(enc_rethrow); | |
| 13222 ins_pipe( pipe_jmp ); | |
| 13223 %} | |
| 13224 | |
| 13225 // inlined locking and unlocking | |
| 13226 | |
| 13227 | |
| 4777 | 13228 instruct cmpFastLock( eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{ |
| 0 | 13229 match( Set cr (FastLock object box) ); |
| 4777 | 13230 effect( TEMP tmp, TEMP scr, USE_KILL box ); |
| 0 | 13231 ins_cost(300); |
| 4777 | 13232 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %} |
| 0 | 13233 ins_encode( Fast_Lock(object,box,tmp,scr) ); |
| 13234 ins_pipe( pipe_slow ); | |
| 13235 %} | |
| 13236 | |
| 13237 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{ | |
| 13238 match( Set cr (FastUnlock object box) ); | |
| 4777 | 13239 effect( TEMP tmp, USE_KILL box ); |
| 0 | 13240 ins_cost(300); |
| 4777 | 13241 format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %} |
| 0 | 13242 ins_encode( Fast_Unlock(object,box,tmp) ); |
| 13243 ins_pipe( pipe_slow ); | |
| 13244 %} | |
| 13245 | |
| 13246 | |
| 13247 | |
| 13248 // ============================================================================ | |
| 13249 // Safepoint Instruction | |
| 13250 instruct safePoint_poll(eFlagsReg cr) %{ | |
| 13251 match(SafePoint); | |
| 13252 effect(KILL cr); | |
| 13253 | |
| 13254 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page. | |
| 13255 // On SPARC that might be acceptable as we can generate the address with | |
| 13256 // just a sethi, saving an or. By polling at offset 0 we can end up | |
| 13257 // putting additional pressure on the index-0 in the D$. Because of | |
| 13258 // alignment (just like the situation at hand) the lower indices tend | |
| 13259 // to see more traffic. It'd be better to change the polling address | |
| 13260 // to offset 0 of the last $line in the polling page. | |
| 13261 | |
| 13262 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %} | |
| 13263 ins_cost(125); | |
| 13264 size(6) ; | |
| 13265 ins_encode( Safepoint_Poll() ); | |
| 13266 ins_pipe( ialu_reg_mem ); | |
| 13267 %} | |
| 13268 | |
| 4950 | 13269 |
| 13270 // ============================================================================ | |
| 13271 // This name is KNOWN by the ADLC and cannot be changed. | |
| 13272 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type | |
| 13273 // for this guy. | |
| 13274 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{ | |
| 13275 match(Set dst (ThreadLocal)); | |
| 13276 effect(DEF dst, KILL cr); | |
| 13277 | |
| 13278 format %{ "MOV $dst, Thread::current()" %} | |
| 13279 ins_encode %{ | |
| 13280 Register dstReg = as_Register($dst$$reg); | |
| 13281 __ get_thread(dstReg); | |
| 13282 %} | |
| 13283 ins_pipe( ialu_reg_fat ); | |
| 13284 %} | |
| 13285 | |
| 13286 | |
| 13287 | |
| 0 | 13288 //----------PEEPHOLE RULES----------------------------------------------------- |
| 13289 // These must follow all instruction definitions as they use the names | |
| 13290 // defined in the instructions definitions. | |
| 13291 // | |
| 605 | 13292 // peepmatch ( root_instr_name [preceding_instruction]* ); |
| 0 | 13293 // |
| 13294 // peepconstraint %{ | |
| 13295 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
| 13296 // [, ...] ); | |
| 13297 // // instruction numbers are zero-based using left to right order in peepmatch | |
| 13298 // | |
| 13299 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
| 13300 // // provide an instruction_number.operand_name for each operand that appears | |
| 13301 // // in the replacement instruction's match rule | |
| 13302 // | |
| 13303 // ---------VM FLAGS--------------------------------------------------------- | |
| 13304 // | |
| 13305 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
| 13306 // | |
| 13307 // Each peephole rule is given an identifying number starting with zero and | |
| 13308 // increasing by one in the order seen by the parser. An individual peephole | |
| 13309 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
| 13310 // on the command-line. | |
| 13311 // | |
| 13312 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
| 13313 // | |
| 13314 // Only match adjacent instructions in same basic block | |
| 13315 // Only equality constraints | |
| 13316 // Only constraints between operands, not (0.dest_reg == EAX_enc) | |
| 13317 // Only one replacement instruction | |
| 13318 // | |
| 13319 // ---------EXAMPLE---------------------------------------------------------- | |
| 13320 // | |
| 13321 // // pertinent parts of existing instructions in architecture description | |
| 13322 // instruct movI(eRegI dst, eRegI src) %{ | |
| 13323 // match(Set dst (CopyI src)); | |
| 13324 // %} | |
| 13325 // | |
| 13326 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ | |
| 13327 // match(Set dst (AddI dst src)); | |
| 13328 // effect(KILL cr); | |
| 13329 // %} | |
| 13330 // | |
| 13331 // // Change (inc mov) to lea | |
| 13332 // peephole %{ | |
| 13333 // // increment preceeded by register-register move | |
| 13334 // peepmatch ( incI_eReg movI ); | |
| 13335 // // require that the destination register of the increment | |
| 13336 // // match the destination register of the move | |
| 13337 // peepconstraint ( 0.dst == 1.dst ); | |
| 13338 // // construct a replacement instruction that sets | |
| 13339 // // the destination to ( move's source register + one ) | |
| 13340 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13341 // %} | |
| 13342 // | |
| 13343 // Implementation no longer uses movX instructions since | |
| 13344 // machine-independent system no longer uses CopyX nodes. | |
| 13345 // | |
| 13346 // peephole %{ | |
| 13347 // peepmatch ( incI_eReg movI ); | |
| 13348 // peepconstraint ( 0.dst == 1.dst ); | |
| 13349 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13350 // %} | |
| 13351 // | |
| 13352 // peephole %{ | |
| 13353 // peepmatch ( decI_eReg movI ); | |
| 13354 // peepconstraint ( 0.dst == 1.dst ); | |
| 13355 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13356 // %} | |
| 13357 // | |
| 13358 // peephole %{ | |
| 13359 // peepmatch ( addI_eReg_imm movI ); | |
| 13360 // peepconstraint ( 0.dst == 1.dst ); | |
| 13361 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13362 // %} | |
| 13363 // | |
| 13364 // peephole %{ | |
| 13365 // peepmatch ( addP_eReg_imm movP ); | |
| 13366 // peepconstraint ( 0.dst == 1.dst ); | |
| 13367 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) ); | |
| 13368 // %} | |
| 13369 | |
| 13370 // // Change load of spilled value to only a spill | |
| 13371 // instruct storeI(memory mem, eRegI src) %{ | |
| 13372 // match(Set mem (StoreI mem src)); | |
| 13373 // %} | |
| 13374 // | |
| 13375 // instruct loadI(eRegI dst, memory mem) %{ | |
| 13376 // match(Set dst (LoadI mem)); | |
| 13377 // %} | |
| 13378 // | |
| 13379 peephole %{ | |
| 13380 peepmatch ( loadI storeI ); | |
| 13381 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); | |
| 13382 peepreplace ( storeI( 1.mem 1.mem 1.src ) ); | |
| 13383 %} | |
| 13384 | |
| 13385 //----------SMARTSPILL RULES--------------------------------------------------- | |
| 13386 // These must follow all instruction definitions as they use the names | |
| 13387 // defined in the instructions definitions. |