Mercurial > hg > graal-compiler
annotate src/cpu/x86/vm/sharedRuntime_x86_64.cpp @ 6725:da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
Summary: Remove PermGen, allocate meta-data in metaspace linked to class loaders, rewrite GC walking, rewrite and rename metadata to be C++ classes
Reviewed-by: jmasa, stefank, never, coleenp, kvn, brutisso, mgerdin, dholmes, jrose, twisti, roland
Contributed-by: jmasa <jon.masamitsu@oracle.com>, stefank <stefan.karlsson@oracle.com>, mgerdin <mikael.gerdin@oracle.com>, never <tom.rodriguez@oracle.com>
| author | coleenp |
|---|---|
| date | Sat, 01 Sep 2012 13:25:18 -0400 |
| parents | 1d7922586cf6 |
| children | 8a02ca5e5576 |
| rev | line source |
|---|---|
| 0 | 1 /* |
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2 * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #include "precompiled.hpp" |
| 26 #include "asm/assembler.hpp" | |
| 27 #include "assembler_x86.inline.hpp" | |
| 28 #include "code/debugInfoRec.hpp" | |
| 29 #include "code/icBuffer.hpp" | |
| 30 #include "code/vtableStubs.hpp" | |
| 31 #include "interpreter/interpreter.hpp" | |
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32 #include "oops/compiledICHolder.hpp" |
| 1972 | 33 #include "prims/jvmtiRedefineClassesTrace.hpp" |
| 34 #include "runtime/sharedRuntime.hpp" | |
| 35 #include "runtime/vframeArray.hpp" | |
| 36 #include "vmreg_x86.inline.hpp" | |
| 37 #ifdef COMPILER1 | |
| 38 #include "c1/c1_Runtime1.hpp" | |
| 39 #endif | |
| 40 #ifdef COMPILER2 | |
| 41 #include "opto/runtime.hpp" | |
| 42 #endif | |
| 0 | 43 |
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44 #define __ masm-> |
| 0 | 45 |
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46 const int StackAlignmentInSlots = StackAlignmentInBytes / VMRegImpl::stack_slot_size; |
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47 |
| 0 | 48 class SimpleRuntimeFrame { |
| 49 | |
| 50 public: | |
| 51 | |
| 52 // Most of the runtime stubs have this simple frame layout. | |
| 53 // This class exists to make the layout shared in one place. | |
| 54 // Offsets are for compiler stack slots, which are jints. | |
| 55 enum layout { | |
| 56 // The frame sender code expects that rbp will be in the "natural" place and | |
| 57 // will override any oopMap setting for it. We must therefore force the layout | |
| 58 // so that it agrees with the frame sender code. | |
| 59 rbp_off = frame::arg_reg_save_area_bytes/BytesPerInt, | |
| 60 rbp_off2, | |
| 61 return_off, return_off2, | |
| 62 framesize | |
| 63 }; | |
| 64 }; | |
| 65 | |
| 66 class RegisterSaver { | |
| 67 // Capture info about frame layout. Layout offsets are in jint | |
| 68 // units because compiler frame slots are jints. | |
| 69 #define DEF_XMM_OFFS(regnum) xmm ## regnum ## _off = xmm_off + (regnum)*16/BytesPerInt, xmm ## regnum ## H_off | |
| 70 enum layout { | |
| 71 fpu_state_off = frame::arg_reg_save_area_bytes/BytesPerInt, // fxsave save area | |
| 72 xmm_off = fpu_state_off + 160/BytesPerInt, // offset in fxsave save area | |
| 73 DEF_XMM_OFFS(0), | |
| 74 DEF_XMM_OFFS(1), | |
| 75 DEF_XMM_OFFS(2), | |
| 76 DEF_XMM_OFFS(3), | |
| 77 DEF_XMM_OFFS(4), | |
| 78 DEF_XMM_OFFS(5), | |
| 79 DEF_XMM_OFFS(6), | |
| 80 DEF_XMM_OFFS(7), | |
| 81 DEF_XMM_OFFS(8), | |
| 82 DEF_XMM_OFFS(9), | |
| 83 DEF_XMM_OFFS(10), | |
| 84 DEF_XMM_OFFS(11), | |
| 85 DEF_XMM_OFFS(12), | |
| 86 DEF_XMM_OFFS(13), | |
| 87 DEF_XMM_OFFS(14), | |
| 88 DEF_XMM_OFFS(15), | |
| 89 fpu_state_end = fpu_state_off + ((FPUStateSizeInWords-1)*wordSize / BytesPerInt), | |
| 90 fpu_stateH_end, | |
| 91 r15_off, r15H_off, | |
| 92 r14_off, r14H_off, | |
| 93 r13_off, r13H_off, | |
| 94 r12_off, r12H_off, | |
| 95 r11_off, r11H_off, | |
| 96 r10_off, r10H_off, | |
| 97 r9_off, r9H_off, | |
| 98 r8_off, r8H_off, | |
| 99 rdi_off, rdiH_off, | |
| 100 rsi_off, rsiH_off, | |
| 101 ignore_off, ignoreH_off, // extra copy of rbp | |
| 102 rsp_off, rspH_off, | |
| 103 rbx_off, rbxH_off, | |
| 104 rdx_off, rdxH_off, | |
| 105 rcx_off, rcxH_off, | |
| 106 rax_off, raxH_off, | |
| 107 // 16-byte stack alignment fill word: see MacroAssembler::push/pop_IU_state | |
| 108 align_off, alignH_off, | |
| 109 flags_off, flagsH_off, | |
| 110 // The frame sender code expects that rbp will be in the "natural" place and | |
| 111 // will override any oopMap setting for it. We must therefore force the layout | |
| 112 // so that it agrees with the frame sender code. | |
| 113 rbp_off, rbpH_off, // copy of rbp we will restore | |
| 114 return_off, returnH_off, // slot for return address | |
| 115 reg_save_size // size in compiler stack slots | |
| 116 }; | |
| 117 | |
| 118 public: | |
| 119 static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words); | |
| 120 static void restore_live_registers(MacroAssembler* masm); | |
| 121 | |
| 122 // Offsets into the register save area | |
| 123 // Used by deoptimization when it is managing result register | |
| 124 // values on its own | |
| 125 | |
| 126 static int rax_offset_in_bytes(void) { return BytesPerInt * rax_off; } | |
| 304 | 127 static int rdx_offset_in_bytes(void) { return BytesPerInt * rdx_off; } |
| 0 | 128 static int rbx_offset_in_bytes(void) { return BytesPerInt * rbx_off; } |
| 129 static int xmm0_offset_in_bytes(void) { return BytesPerInt * xmm0_off; } | |
| 130 static int return_offset_in_bytes(void) { return BytesPerInt * return_off; } | |
| 131 | |
| 132 // During deoptimization only the result registers need to be restored, | |
| 133 // all the other values have already been extracted. | |
| 134 static void restore_result_registers(MacroAssembler* masm); | |
| 135 }; | |
| 136 | |
| 137 OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words) { | |
| 138 | |
| 139 // Always make the frame size 16-byte aligned | |
| 140 int frame_size_in_bytes = round_to(additional_frame_words*wordSize + | |
| 141 reg_save_size*BytesPerInt, 16); | |
| 142 // OopMap frame size is in compiler stack slots (jint's) not bytes or words | |
| 143 int frame_size_in_slots = frame_size_in_bytes / BytesPerInt; | |
| 144 // The caller will allocate additional_frame_words | |
| 145 int additional_frame_slots = additional_frame_words*wordSize / BytesPerInt; | |
| 146 // CodeBlob frame size is in words. | |
| 147 int frame_size_in_words = frame_size_in_bytes / wordSize; | |
| 148 *total_frame_words = frame_size_in_words; | |
| 149 | |
| 150 // Save registers, fpu state, and flags. | |
| 151 // We assume caller has already pushed the return address onto the | |
| 152 // stack, so rsp is 8-byte aligned here. | |
| 153 // We push rpb twice in this sequence because we want the real rbp | |
| 154 // to be under the return like a normal enter. | |
| 155 | |
| 156 __ enter(); // rsp becomes 16-byte aligned here | |
| 157 __ push_CPU_state(); // Push a multiple of 16 bytes | |
| 158 if (frame::arg_reg_save_area_bytes != 0) { | |
| 159 // Allocate argument register save area | |
| 304 | 160 __ subptr(rsp, frame::arg_reg_save_area_bytes); |
| 0 | 161 } |
| 162 | |
| 163 // Set an oopmap for the call site. This oopmap will map all | |
| 164 // oop-registers and debug-info registers as callee-saved. This | |
| 165 // will allow deoptimization at this safepoint to find all possible | |
| 166 // debug-info recordings, as well as let GC find all oops. | |
| 167 | |
| 168 OopMapSet *oop_maps = new OopMapSet(); | |
| 169 OopMap* map = new OopMap(frame_size_in_slots, 0); | |
| 170 map->set_callee_saved(VMRegImpl::stack2reg( rax_off + additional_frame_slots), rax->as_VMReg()); | |
| 171 map->set_callee_saved(VMRegImpl::stack2reg( rcx_off + additional_frame_slots), rcx->as_VMReg()); | |
| 172 map->set_callee_saved(VMRegImpl::stack2reg( rdx_off + additional_frame_slots), rdx->as_VMReg()); | |
| 173 map->set_callee_saved(VMRegImpl::stack2reg( rbx_off + additional_frame_slots), rbx->as_VMReg()); | |
| 174 // rbp location is known implicitly by the frame sender code, needs no oopmap | |
| 175 // and the location where rbp was saved by is ignored | |
| 176 map->set_callee_saved(VMRegImpl::stack2reg( rsi_off + additional_frame_slots), rsi->as_VMReg()); | |
| 177 map->set_callee_saved(VMRegImpl::stack2reg( rdi_off + additional_frame_slots), rdi->as_VMReg()); | |
| 178 map->set_callee_saved(VMRegImpl::stack2reg( r8_off + additional_frame_slots), r8->as_VMReg()); | |
| 179 map->set_callee_saved(VMRegImpl::stack2reg( r9_off + additional_frame_slots), r9->as_VMReg()); | |
| 180 map->set_callee_saved(VMRegImpl::stack2reg( r10_off + additional_frame_slots), r10->as_VMReg()); | |
| 181 map->set_callee_saved(VMRegImpl::stack2reg( r11_off + additional_frame_slots), r11->as_VMReg()); | |
| 182 map->set_callee_saved(VMRegImpl::stack2reg( r12_off + additional_frame_slots), r12->as_VMReg()); | |
| 183 map->set_callee_saved(VMRegImpl::stack2reg( r13_off + additional_frame_slots), r13->as_VMReg()); | |
| 184 map->set_callee_saved(VMRegImpl::stack2reg( r14_off + additional_frame_slots), r14->as_VMReg()); | |
| 185 map->set_callee_saved(VMRegImpl::stack2reg( r15_off + additional_frame_slots), r15->as_VMReg()); | |
| 186 map->set_callee_saved(VMRegImpl::stack2reg(xmm0_off + additional_frame_slots), xmm0->as_VMReg()); | |
| 187 map->set_callee_saved(VMRegImpl::stack2reg(xmm1_off + additional_frame_slots), xmm1->as_VMReg()); | |
| 188 map->set_callee_saved(VMRegImpl::stack2reg(xmm2_off + additional_frame_slots), xmm2->as_VMReg()); | |
| 189 map->set_callee_saved(VMRegImpl::stack2reg(xmm3_off + additional_frame_slots), xmm3->as_VMReg()); | |
| 190 map->set_callee_saved(VMRegImpl::stack2reg(xmm4_off + additional_frame_slots), xmm4->as_VMReg()); | |
| 191 map->set_callee_saved(VMRegImpl::stack2reg(xmm5_off + additional_frame_slots), xmm5->as_VMReg()); | |
| 192 map->set_callee_saved(VMRegImpl::stack2reg(xmm6_off + additional_frame_slots), xmm6->as_VMReg()); | |
| 193 map->set_callee_saved(VMRegImpl::stack2reg(xmm7_off + additional_frame_slots), xmm7->as_VMReg()); | |
| 194 map->set_callee_saved(VMRegImpl::stack2reg(xmm8_off + additional_frame_slots), xmm8->as_VMReg()); | |
| 195 map->set_callee_saved(VMRegImpl::stack2reg(xmm9_off + additional_frame_slots), xmm9->as_VMReg()); | |
| 196 map->set_callee_saved(VMRegImpl::stack2reg(xmm10_off + additional_frame_slots), xmm10->as_VMReg()); | |
| 197 map->set_callee_saved(VMRegImpl::stack2reg(xmm11_off + additional_frame_slots), xmm11->as_VMReg()); | |
| 198 map->set_callee_saved(VMRegImpl::stack2reg(xmm12_off + additional_frame_slots), xmm12->as_VMReg()); | |
| 199 map->set_callee_saved(VMRegImpl::stack2reg(xmm13_off + additional_frame_slots), xmm13->as_VMReg()); | |
| 200 map->set_callee_saved(VMRegImpl::stack2reg(xmm14_off + additional_frame_slots), xmm14->as_VMReg()); | |
| 201 map->set_callee_saved(VMRegImpl::stack2reg(xmm15_off + additional_frame_slots), xmm15->as_VMReg()); | |
| 202 | |
| 203 // %%% These should all be a waste but we'll keep things as they were for now | |
| 204 if (true) { | |
| 205 map->set_callee_saved(VMRegImpl::stack2reg( raxH_off + additional_frame_slots), | |
| 206 rax->as_VMReg()->next()); | |
| 207 map->set_callee_saved(VMRegImpl::stack2reg( rcxH_off + additional_frame_slots), | |
| 208 rcx->as_VMReg()->next()); | |
| 209 map->set_callee_saved(VMRegImpl::stack2reg( rdxH_off + additional_frame_slots), | |
| 210 rdx->as_VMReg()->next()); | |
| 211 map->set_callee_saved(VMRegImpl::stack2reg( rbxH_off + additional_frame_slots), | |
| 212 rbx->as_VMReg()->next()); | |
| 213 // rbp location is known implicitly by the frame sender code, needs no oopmap | |
| 214 map->set_callee_saved(VMRegImpl::stack2reg( rsiH_off + additional_frame_slots), | |
| 215 rsi->as_VMReg()->next()); | |
| 216 map->set_callee_saved(VMRegImpl::stack2reg( rdiH_off + additional_frame_slots), | |
| 217 rdi->as_VMReg()->next()); | |
| 218 map->set_callee_saved(VMRegImpl::stack2reg( r8H_off + additional_frame_slots), | |
| 219 r8->as_VMReg()->next()); | |
| 220 map->set_callee_saved(VMRegImpl::stack2reg( r9H_off + additional_frame_slots), | |
| 221 r9->as_VMReg()->next()); | |
| 222 map->set_callee_saved(VMRegImpl::stack2reg( r10H_off + additional_frame_slots), | |
| 223 r10->as_VMReg()->next()); | |
| 224 map->set_callee_saved(VMRegImpl::stack2reg( r11H_off + additional_frame_slots), | |
| 225 r11->as_VMReg()->next()); | |
| 226 map->set_callee_saved(VMRegImpl::stack2reg( r12H_off + additional_frame_slots), | |
| 227 r12->as_VMReg()->next()); | |
| 228 map->set_callee_saved(VMRegImpl::stack2reg( r13H_off + additional_frame_slots), | |
| 229 r13->as_VMReg()->next()); | |
| 230 map->set_callee_saved(VMRegImpl::stack2reg( r14H_off + additional_frame_slots), | |
| 231 r14->as_VMReg()->next()); | |
| 232 map->set_callee_saved(VMRegImpl::stack2reg( r15H_off + additional_frame_slots), | |
| 233 r15->as_VMReg()->next()); | |
| 234 map->set_callee_saved(VMRegImpl::stack2reg(xmm0H_off + additional_frame_slots), | |
| 235 xmm0->as_VMReg()->next()); | |
| 236 map->set_callee_saved(VMRegImpl::stack2reg(xmm1H_off + additional_frame_slots), | |
| 237 xmm1->as_VMReg()->next()); | |
| 238 map->set_callee_saved(VMRegImpl::stack2reg(xmm2H_off + additional_frame_slots), | |
| 239 xmm2->as_VMReg()->next()); | |
| 240 map->set_callee_saved(VMRegImpl::stack2reg(xmm3H_off + additional_frame_slots), | |
| 241 xmm3->as_VMReg()->next()); | |
| 242 map->set_callee_saved(VMRegImpl::stack2reg(xmm4H_off + additional_frame_slots), | |
| 243 xmm4->as_VMReg()->next()); | |
| 244 map->set_callee_saved(VMRegImpl::stack2reg(xmm5H_off + additional_frame_slots), | |
| 245 xmm5->as_VMReg()->next()); | |
| 246 map->set_callee_saved(VMRegImpl::stack2reg(xmm6H_off + additional_frame_slots), | |
| 247 xmm6->as_VMReg()->next()); | |
| 248 map->set_callee_saved(VMRegImpl::stack2reg(xmm7H_off + additional_frame_slots), | |
| 249 xmm7->as_VMReg()->next()); | |
| 250 map->set_callee_saved(VMRegImpl::stack2reg(xmm8H_off + additional_frame_slots), | |
| 251 xmm8->as_VMReg()->next()); | |
| 252 map->set_callee_saved(VMRegImpl::stack2reg(xmm9H_off + additional_frame_slots), | |
| 253 xmm9->as_VMReg()->next()); | |
| 254 map->set_callee_saved(VMRegImpl::stack2reg(xmm10H_off + additional_frame_slots), | |
| 255 xmm10->as_VMReg()->next()); | |
| 256 map->set_callee_saved(VMRegImpl::stack2reg(xmm11H_off + additional_frame_slots), | |
| 257 xmm11->as_VMReg()->next()); | |
| 258 map->set_callee_saved(VMRegImpl::stack2reg(xmm12H_off + additional_frame_slots), | |
| 259 xmm12->as_VMReg()->next()); | |
| 260 map->set_callee_saved(VMRegImpl::stack2reg(xmm13H_off + additional_frame_slots), | |
| 261 xmm13->as_VMReg()->next()); | |
| 262 map->set_callee_saved(VMRegImpl::stack2reg(xmm14H_off + additional_frame_slots), | |
| 263 xmm14->as_VMReg()->next()); | |
| 264 map->set_callee_saved(VMRegImpl::stack2reg(xmm15H_off + additional_frame_slots), | |
| 265 xmm15->as_VMReg()->next()); | |
| 266 } | |
| 267 | |
| 268 return map; | |
| 269 } | |
| 270 | |
| 271 void RegisterSaver::restore_live_registers(MacroAssembler* masm) { | |
| 272 if (frame::arg_reg_save_area_bytes != 0) { | |
| 273 // Pop arg register save area | |
| 304 | 274 __ addptr(rsp, frame::arg_reg_save_area_bytes); |
| 0 | 275 } |
| 276 // Recover CPU state | |
| 277 __ pop_CPU_state(); | |
| 278 // Get the rbp described implicitly by the calling convention (no oopMap) | |
| 304 | 279 __ pop(rbp); |
| 0 | 280 } |
| 281 | |
| 282 void RegisterSaver::restore_result_registers(MacroAssembler* masm) { | |
| 283 | |
| 284 // Just restore result register. Only used by deoptimization. By | |
| 285 // now any callee save register that needs to be restored to a c2 | |
| 286 // caller of the deoptee has been extracted into the vframeArray | |
| 287 // and will be stuffed into the c2i adapter we create for later | |
| 288 // restoration so only result registers need to be restored here. | |
| 289 | |
| 290 // Restore fp result register | |
| 291 __ movdbl(xmm0, Address(rsp, xmm0_offset_in_bytes())); | |
| 292 // Restore integer result register | |
| 304 | 293 __ movptr(rax, Address(rsp, rax_offset_in_bytes())); |
| 294 __ movptr(rdx, Address(rsp, rdx_offset_in_bytes())); | |
| 295 | |
| 0 | 296 // Pop all of the register save are off the stack except the return address |
| 304 | 297 __ addptr(rsp, return_offset_in_bytes()); |
| 0 | 298 } |
| 299 | |
| 300 // The java_calling_convention describes stack locations as ideal slots on | |
| 301 // a frame with no abi restrictions. Since we must observe abi restrictions | |
| 302 // (like the placement of the register window) the slots must be biased by | |
| 303 // the following value. | |
| 304 static int reg2offset_in(VMReg r) { | |
| 305 // Account for saved rbp and return address | |
| 306 // This should really be in_preserve_stack_slots | |
| 307 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size; | |
| 308 } | |
| 309 | |
| 310 static int reg2offset_out(VMReg r) { | |
| 311 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size; | |
| 312 } | |
| 313 | |
| 314 // --------------------------------------------------------------------------- | |
| 315 // Read the array of BasicTypes from a signature, and compute where the | |
| 316 // arguments should go. Values in the VMRegPair regs array refer to 4-byte | |
| 317 // quantities. Values less than VMRegImpl::stack0 are registers, those above | |
| 318 // refer to 4-byte stack slots. All stack slots are based off of the stack pointer | |
| 319 // as framesizes are fixed. | |
| 320 // VMRegImpl::stack0 refers to the first slot 0(sp). | |
| 321 // and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. Register | |
| 322 // up to RegisterImpl::number_of_registers) are the 64-bit | |
| 323 // integer registers. | |
| 324 | |
| 325 // Note: the INPUTS in sig_bt are in units of Java argument words, which are | |
| 326 // either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit | |
| 327 // units regardless of build. Of course for i486 there is no 64 bit build | |
| 328 | |
| 329 // The Java calling convention is a "shifted" version of the C ABI. | |
| 330 // By skipping the first C ABI register we can call non-static jni methods | |
| 331 // with small numbers of arguments without having to shuffle the arguments | |
| 332 // at all. Since we control the java ABI we ought to at least get some | |
| 333 // advantage out of it. | |
| 334 | |
| 335 int SharedRuntime::java_calling_convention(const BasicType *sig_bt, | |
| 336 VMRegPair *regs, | |
| 337 int total_args_passed, | |
| 338 int is_outgoing) { | |
| 339 | |
| 340 // Create the mapping between argument positions and | |
| 341 // registers. | |
| 342 static const Register INT_ArgReg[Argument::n_int_register_parameters_j] = { | |
| 343 j_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4, j_rarg5 | |
| 344 }; | |
| 345 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_j] = { | |
| 346 j_farg0, j_farg1, j_farg2, j_farg3, | |
| 347 j_farg4, j_farg5, j_farg6, j_farg7 | |
| 348 }; | |
| 349 | |
| 350 | |
| 351 uint int_args = 0; | |
| 352 uint fp_args = 0; | |
| 353 uint stk_args = 0; // inc by 2 each time | |
| 354 | |
| 355 for (int i = 0; i < total_args_passed; i++) { | |
| 356 switch (sig_bt[i]) { | |
| 357 case T_BOOLEAN: | |
| 358 case T_CHAR: | |
| 359 case T_BYTE: | |
| 360 case T_SHORT: | |
| 361 case T_INT: | |
| 362 if (int_args < Argument::n_int_register_parameters_j) { | |
| 363 regs[i].set1(INT_ArgReg[int_args++]->as_VMReg()); | |
| 364 } else { | |
| 365 regs[i].set1(VMRegImpl::stack2reg(stk_args)); | |
| 366 stk_args += 2; | |
| 367 } | |
| 368 break; | |
| 369 case T_VOID: | |
| 370 // halves of T_LONG or T_DOUBLE | |
| 371 assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half"); | |
| 372 regs[i].set_bad(); | |
| 373 break; | |
| 374 case T_LONG: | |
| 375 assert(sig_bt[i + 1] == T_VOID, "expecting half"); | |
| 376 // fall through | |
| 377 case T_OBJECT: | |
| 378 case T_ARRAY: | |
| 379 case T_ADDRESS: | |
| 380 if (int_args < Argument::n_int_register_parameters_j) { | |
| 381 regs[i].set2(INT_ArgReg[int_args++]->as_VMReg()); | |
| 382 } else { | |
| 383 regs[i].set2(VMRegImpl::stack2reg(stk_args)); | |
| 384 stk_args += 2; | |
| 385 } | |
| 386 break; | |
| 387 case T_FLOAT: | |
| 388 if (fp_args < Argument::n_float_register_parameters_j) { | |
| 389 regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg()); | |
| 390 } else { | |
| 391 regs[i].set1(VMRegImpl::stack2reg(stk_args)); | |
| 392 stk_args += 2; | |
| 393 } | |
| 394 break; | |
| 395 case T_DOUBLE: | |
| 396 assert(sig_bt[i + 1] == T_VOID, "expecting half"); | |
| 397 if (fp_args < Argument::n_float_register_parameters_j) { | |
| 398 regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg()); | |
| 399 } else { | |
| 400 regs[i].set2(VMRegImpl::stack2reg(stk_args)); | |
| 401 stk_args += 2; | |
| 402 } | |
| 403 break; | |
| 404 default: | |
| 405 ShouldNotReachHere(); | |
| 406 break; | |
| 407 } | |
| 408 } | |
| 409 | |
| 410 return round_to(stk_args, 2); | |
| 411 } | |
| 412 | |
| 413 // Patch the callers callsite with entry to compiled code if it exists. | |
| 414 static void patch_callers_callsite(MacroAssembler *masm) { | |
| 415 Label L; | |
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416 __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), (int32_t)NULL_WORD); |
| 0 | 417 __ jcc(Assembler::equal, L); |
| 418 | |
| 419 // Save the current stack pointer | |
| 304 | 420 __ mov(r13, rsp); |
| 0 | 421 // Schedule the branch target address early. |
| 422 // Call into the VM to patch the caller, then jump to compiled callee | |
| 423 // rax isn't live so capture return address while we easily can | |
| 304 | 424 __ movptr(rax, Address(rsp, 0)); |
| 0 | 425 |
| 426 // align stack so push_CPU_state doesn't fault | |
| 304 | 427 __ andptr(rsp, -(StackAlignmentInBytes)); |
| 0 | 428 __ push_CPU_state(); |
| 429 | |
| 430 // VM needs caller's callsite | |
| 431 // VM needs target method | |
| 432 // This needs to be a long call since we will relocate this adapter to | |
| 433 // the codeBuffer and it may not reach | |
| 434 | |
| 435 // Allocate argument register save area | |
| 436 if (frame::arg_reg_save_area_bytes != 0) { | |
| 304 | 437 __ subptr(rsp, frame::arg_reg_save_area_bytes); |
| 0 | 438 } |
| 304 | 439 __ mov(c_rarg0, rbx); |
| 440 __ mov(c_rarg1, rax); | |
| 0 | 441 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite))); |
| 442 | |
| 443 // De-allocate argument register save area | |
| 444 if (frame::arg_reg_save_area_bytes != 0) { | |
| 304 | 445 __ addptr(rsp, frame::arg_reg_save_area_bytes); |
| 0 | 446 } |
| 447 | |
| 448 __ pop_CPU_state(); | |
| 449 // restore sp | |
| 304 | 450 __ mov(rsp, r13); |
| 0 | 451 __ bind(L); |
| 452 } | |
| 453 | |
| 454 | |
| 455 static void gen_c2i_adapter(MacroAssembler *masm, | |
| 456 int total_args_passed, | |
| 457 int comp_args_on_stack, | |
| 458 const BasicType *sig_bt, | |
| 459 const VMRegPair *regs, | |
| 460 Label& skip_fixup) { | |
| 461 // Before we get into the guts of the C2I adapter, see if we should be here | |
| 462 // at all. We've come from compiled code and are attempting to jump to the | |
| 463 // interpreter, which means the caller made a static call to get here | |
| 464 // (vcalls always get a compiled target if there is one). Check for a | |
| 465 // compiled target. If there is one, we need to patch the caller's call. | |
| 466 patch_callers_callsite(masm); | |
| 467 | |
| 468 __ bind(skip_fixup); | |
| 469 | |
| 470 // Since all args are passed on the stack, total_args_passed * | |
| 471 // Interpreter::stackElementSize is the space we need. Plus 1 because | |
| 472 // we also account for the return address location since | |
| 473 // we store it first rather than hold it in rax across all the shuffling | |
| 474 | |
| 1506 | 475 int extraspace = (total_args_passed * Interpreter::stackElementSize) + wordSize; |
| 0 | 476 |
| 477 // stack is aligned, keep it that way | |
| 478 extraspace = round_to(extraspace, 2*wordSize); | |
| 479 | |
| 480 // Get return address | |
| 304 | 481 __ pop(rax); |
| 0 | 482 |
| 483 // set senderSP value | |
| 304 | 484 __ mov(r13, rsp); |
| 485 | |
| 486 __ subptr(rsp, extraspace); | |
| 0 | 487 |
| 488 // Store the return address in the expected location | |
| 304 | 489 __ movptr(Address(rsp, 0), rax); |
| 0 | 490 |
| 491 // Now write the args into the outgoing interpreter space | |
| 492 for (int i = 0; i < total_args_passed; i++) { | |
| 493 if (sig_bt[i] == T_VOID) { | |
| 494 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half"); | |
| 495 continue; | |
| 496 } | |
| 497 | |
| 498 // offset to start parameters | |
| 1506 | 499 int st_off = (total_args_passed - i) * Interpreter::stackElementSize; |
| 500 int next_off = st_off - Interpreter::stackElementSize; | |
| 0 | 501 |
| 502 // Say 4 args: | |
| 503 // i st_off | |
| 504 // 0 32 T_LONG | |
| 505 // 1 24 T_VOID | |
| 506 // 2 16 T_OBJECT | |
| 507 // 3 8 T_BOOL | |
| 508 // - 0 return address | |
| 509 // | |
| 510 // However to make thing extra confusing. Because we can fit a long/double in | |
| 511 // a single slot on a 64 bt vm and it would be silly to break them up, the interpreter | |
| 512 // leaves one slot empty and only stores to a single slot. In this case the | |
| 513 // slot that is occupied is the T_VOID slot. See I said it was confusing. | |
| 514 | |
| 515 VMReg r_1 = regs[i].first(); | |
| 516 VMReg r_2 = regs[i].second(); | |
| 517 if (!r_1->is_valid()) { | |
| 518 assert(!r_2->is_valid(), ""); | |
| 519 continue; | |
| 520 } | |
| 521 if (r_1->is_stack()) { | |
| 522 // memory to memory use rax | |
| 523 int ld_off = r_1->reg2stack() * VMRegImpl::stack_slot_size + extraspace; | |
| 524 if (!r_2->is_valid()) { | |
| 525 // sign extend?? | |
| 526 __ movl(rax, Address(rsp, ld_off)); | |
| 304 | 527 __ movptr(Address(rsp, st_off), rax); |
| 0 | 528 |
| 529 } else { | |
| 530 | |
| 531 __ movq(rax, Address(rsp, ld_off)); | |
| 532 | |
| 533 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG | |
| 534 // T_DOUBLE and T_LONG use two slots in the interpreter | |
| 535 if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) { | |
| 536 // ld_off == LSW, ld_off+wordSize == MSW | |
| 537 // st_off == MSW, next_off == LSW | |
| 538 __ movq(Address(rsp, next_off), rax); | |
| 539 #ifdef ASSERT | |
| 540 // Overwrite the unused slot with known junk | |
| 541 __ mov64(rax, CONST64(0xdeadffffdeadaaaa)); | |
| 304 | 542 __ movptr(Address(rsp, st_off), rax); |
| 0 | 543 #endif /* ASSERT */ |
| 544 } else { | |
| 545 __ movq(Address(rsp, st_off), rax); | |
| 546 } | |
| 547 } | |
| 548 } else if (r_1->is_Register()) { | |
| 549 Register r = r_1->as_Register(); | |
| 550 if (!r_2->is_valid()) { | |
| 551 // must be only an int (or less ) so move only 32bits to slot | |
| 552 // why not sign extend?? | |
| 553 __ movl(Address(rsp, st_off), r); | |
| 554 } else { | |
| 555 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG | |
| 556 // T_DOUBLE and T_LONG use two slots in the interpreter | |
| 557 if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) { | |
| 558 // long/double in gpr | |
| 559 #ifdef ASSERT | |
| 560 // Overwrite the unused slot with known junk | |
| 561 __ mov64(rax, CONST64(0xdeadffffdeadaaab)); | |
| 304 | 562 __ movptr(Address(rsp, st_off), rax); |
| 0 | 563 #endif /* ASSERT */ |
| 564 __ movq(Address(rsp, next_off), r); | |
| 565 } else { | |
| 304 | 566 __ movptr(Address(rsp, st_off), r); |
| 0 | 567 } |
| 568 } | |
| 569 } else { | |
| 570 assert(r_1->is_XMMRegister(), ""); | |
| 571 if (!r_2->is_valid()) { | |
| 572 // only a float use just part of the slot | |
| 573 __ movflt(Address(rsp, st_off), r_1->as_XMMRegister()); | |
| 574 } else { | |
| 575 #ifdef ASSERT | |
| 576 // Overwrite the unused slot with known junk | |
| 577 __ mov64(rax, CONST64(0xdeadffffdeadaaac)); | |
| 304 | 578 __ movptr(Address(rsp, st_off), rax); |
| 0 | 579 #endif /* ASSERT */ |
| 580 __ movdbl(Address(rsp, next_off), r_1->as_XMMRegister()); | |
| 581 } | |
| 582 } | |
| 583 } | |
| 584 | |
| 585 // Schedule the branch target address early. | |
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586 __ movptr(rcx, Address(rbx, in_bytes(Method::interpreter_entry_offset()))); |
| 0 | 587 __ jmp(rcx); |
| 588 } | |
| 589 | |
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590 static void range_check(MacroAssembler* masm, Register pc_reg, Register temp_reg, |
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591 address code_start, address code_end, |
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592 Label& L_ok) { |
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593 Label L_fail; |
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594 __ lea(temp_reg, ExternalAddress(code_start)); |
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595 __ cmpptr(pc_reg, temp_reg); |
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596 __ jcc(Assembler::belowEqual, L_fail); |
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597 __ lea(temp_reg, ExternalAddress(code_end)); |
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598 __ cmpptr(pc_reg, temp_reg); |
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599 __ jcc(Assembler::below, L_ok); |
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600 __ bind(L_fail); |
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601 } |
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602 |
| 0 | 603 static void gen_i2c_adapter(MacroAssembler *masm, |
| 604 int total_args_passed, | |
| 605 int comp_args_on_stack, | |
| 606 const BasicType *sig_bt, | |
| 607 const VMRegPair *regs) { | |
| 608 | |
| 609 // Note: r13 contains the senderSP on entry. We must preserve it since | |
| 610 // we may do a i2c -> c2i transition if we lose a race where compiled | |
| 611 // code goes non-entrant while we get args ready. | |
| 612 // In addition we use r13 to locate all the interpreter args as | |
| 613 // we must align the stack to 16 bytes on an i2c entry else we | |
| 614 // lose alignment we expect in all compiled code and register | |
| 615 // save code can segv when fxsave instructions find improperly | |
| 616 // aligned stack pointer. | |
| 617 | |
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618 // Adapters can be frameless because they do not require the caller |
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619 // to perform additional cleanup work, such as correcting the stack pointer. |
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620 // An i2c adapter is frameless because the *caller* frame, which is interpreted, |
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621 // routinely repairs its own stack pointer (from interpreter_frame_last_sp), |
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622 // even if a callee has modified the stack pointer. |
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623 // A c2i adapter is frameless because the *callee* frame, which is interpreted, |
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624 // routinely repairs its caller's stack pointer (from sender_sp, which is set |
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625 // up via the senderSP register). |
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626 // In other words, if *either* the caller or callee is interpreted, we can |
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627 // get the stack pointer repaired after a call. |
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628 // This is why c2i and i2c adapters cannot be indefinitely composed. |
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629 // In particular, if a c2i adapter were to somehow call an i2c adapter, |
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630 // both caller and callee would be compiled methods, and neither would |
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631 // clean up the stack pointer changes performed by the two adapters. |
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632 // If this happens, control eventually transfers back to the compiled |
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633 // caller, but with an uncorrected stack, causing delayed havoc. |
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634 |
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635 // Pick up the return address |
| 304 | 636 __ movptr(rax, Address(rsp, 0)); |
| 0 | 637 |
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638 if (VerifyAdapterCalls && |
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639 (Interpreter::code() != NULL || StubRoutines::code1() != NULL)) { |
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640 // So, let's test for cascading c2i/i2c adapters right now. |
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641 // assert(Interpreter::contains($return_addr) || |
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642 // StubRoutines::contains($return_addr), |
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643 // "i2c adapter must return to an interpreter frame"); |
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644 __ block_comment("verify_i2c { "); |
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645 Label L_ok; |
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646 if (Interpreter::code() != NULL) |
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647 range_check(masm, rax, r11, |
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648 Interpreter::code()->code_start(), Interpreter::code()->code_end(), |
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649 L_ok); |
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650 if (StubRoutines::code1() != NULL) |
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651 range_check(masm, rax, r11, |
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652 StubRoutines::code1()->code_begin(), StubRoutines::code1()->code_end(), |
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653 L_ok); |
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654 if (StubRoutines::code2() != NULL) |
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655 range_check(masm, rax, r11, |
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656 StubRoutines::code2()->code_begin(), StubRoutines::code2()->code_end(), |
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657 L_ok); |
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658 const char* msg = "i2c adapter must return to an interpreter frame"; |
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659 __ block_comment(msg); |
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660 __ stop(msg); |
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661 __ bind(L_ok); |
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662 __ block_comment("} verify_i2ce "); |
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663 } |
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664 |
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665 // Must preserve original SP for loading incoming arguments because |
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666 // we need to align the outgoing SP for compiled code. |
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667 __ movptr(r11, rsp); |
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668 |
| 0 | 669 // Cut-out for having no stack args. Since up to 2 int/oop args are passed |
| 670 // in registers, we will occasionally have no stack args. | |
| 671 int comp_words_on_stack = 0; | |
| 672 if (comp_args_on_stack) { | |
| 673 // Sig words on the stack are greater-than VMRegImpl::stack0. Those in | |
| 674 // registers are below. By subtracting stack0, we either get a negative | |
| 675 // number (all values in registers) or the maximum stack slot accessed. | |
| 676 | |
| 677 // Convert 4-byte c2 stack slots to words. | |
| 678 comp_words_on_stack = round_to(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord; | |
| 679 // Round up to miminum stack alignment, in wordSize | |
| 680 comp_words_on_stack = round_to(comp_words_on_stack, 2); | |
| 304 | 681 __ subptr(rsp, comp_words_on_stack * wordSize); |
| 0 | 682 } |
| 683 | |
| 684 | |
| 685 // Ensure compiled code always sees stack at proper alignment | |
| 304 | 686 __ andptr(rsp, -16); |
| 0 | 687 |
| 688 // push the return address and misalign the stack that youngest frame always sees | |
| 689 // as far as the placement of the call instruction | |
| 304 | 690 __ push(rax); |
| 0 | 691 |
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692 // Put saved SP in another register |
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693 const Register saved_sp = rax; |
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694 __ movptr(saved_sp, r11); |
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695 |
| 0 | 696 // Will jump to the compiled code just as if compiled code was doing it. |
| 697 // Pre-load the register-jump target early, to schedule it better. | |
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698 __ movptr(r11, Address(rbx, in_bytes(Method::from_compiled_offset()))); |
| 0 | 699 |
| 700 // Now generate the shuffle code. Pick up all register args and move the | |
| 701 // rest through the floating point stack top. | |
| 702 for (int i = 0; i < total_args_passed; i++) { | |
| 703 if (sig_bt[i] == T_VOID) { | |
| 704 // Longs and doubles are passed in native word order, but misaligned | |
| 705 // in the 32-bit build. | |
| 706 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half"); | |
| 707 continue; | |
| 708 } | |
| 709 | |
| 710 // Pick up 0, 1 or 2 words from SP+offset. | |
| 711 | |
| 712 assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(), | |
| 713 "scrambled load targets?"); | |
| 714 // Load in argument order going down. | |
| 1506 | 715 int ld_off = (total_args_passed - i)*Interpreter::stackElementSize; |
| 0 | 716 // Point to interpreter value (vs. tag) |
| 1506 | 717 int next_off = ld_off - Interpreter::stackElementSize; |
| 0 | 718 // |
| 719 // | |
| 720 // | |
| 721 VMReg r_1 = regs[i].first(); | |
| 722 VMReg r_2 = regs[i].second(); | |
| 723 if (!r_1->is_valid()) { | |
| 724 assert(!r_2->is_valid(), ""); | |
| 725 continue; | |
| 726 } | |
| 727 if (r_1->is_stack()) { | |
| 728 // Convert stack slot to an SP offset (+ wordSize to account for return address ) | |
| 729 int st_off = regs[i].first()->reg2stack()*VMRegImpl::stack_slot_size + wordSize; | |
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730 |
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731 // We can use r13 as a temp here because compiled code doesn't need r13 as an input |
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732 // and if we end up going thru a c2i because of a miss a reasonable value of r13 |
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733 // will be generated. |
| 0 | 734 if (!r_2->is_valid()) { |
| 735 // sign extend??? | |
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736 __ movl(r13, Address(saved_sp, ld_off)); |
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737 __ movptr(Address(rsp, st_off), r13); |
| 0 | 738 } else { |
| 739 // | |
| 740 // We are using two optoregs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE | |
| 741 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case | |
| 742 // So we must adjust where to pick up the data to match the interpreter. | |
| 743 // | |
| 744 // Interpreter local[n] == MSW, local[n+1] == LSW however locals | |
| 745 // are accessed as negative so LSW is at LOW address | |
| 746 | |
| 747 // ld_off is MSW so get LSW | |
| 748 const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)? | |
| 749 next_off : ld_off; | |
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750 __ movq(r13, Address(saved_sp, offset)); |
| 0 | 751 // st_off is LSW (i.e. reg.first()) |
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752 __ movq(Address(rsp, st_off), r13); |
| 0 | 753 } |
| 754 } else if (r_1->is_Register()) { // Register argument | |
| 755 Register r = r_1->as_Register(); | |
| 756 assert(r != rax, "must be different"); | |
| 757 if (r_2->is_valid()) { | |
| 758 // | |
| 759 // We are using two VMRegs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE | |
| 760 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case | |
| 761 // So we must adjust where to pick up the data to match the interpreter. | |
| 762 | |
| 763 const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)? | |
| 764 next_off : ld_off; | |
| 765 | |
| 766 // this can be a misaligned move | |
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767 __ movq(r, Address(saved_sp, offset)); |
| 0 | 768 } else { |
| 769 // sign extend and use a full word? | |
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770 __ movl(r, Address(saved_sp, ld_off)); |
| 0 | 771 } |
| 772 } else { | |
| 773 if (!r_2->is_valid()) { | |
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774 __ movflt(r_1->as_XMMRegister(), Address(saved_sp, ld_off)); |
| 0 | 775 } else { |
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776 __ movdbl(r_1->as_XMMRegister(), Address(saved_sp, next_off)); |
| 0 | 777 } |
| 778 } | |
| 779 } | |
| 780 | |
| 781 // 6243940 We might end up in handle_wrong_method if | |
| 782 // the callee is deoptimized as we race thru here. If that | |
| 783 // happens we don't want to take a safepoint because the | |
| 784 // caller frame will look interpreted and arguments are now | |
| 785 // "compiled" so it is much better to make this transition | |
| 786 // invisible to the stack walking code. Unfortunately if | |
| 787 // we try and find the callee by normal means a safepoint | |
| 788 // is possible. So we stash the desired callee in the thread | |
| 789 // and the vm will find there should this case occur. | |
| 790 | |
| 304 | 791 __ movptr(Address(r15_thread, JavaThread::callee_target_offset()), rbx); |
| 0 | 792 |
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793 // put Method* where a c2i would expect should we end up there |
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794 // only needed becaus eof c2 resolve stubs return Method* as a result in |
| 0 | 795 // rax |
| 304 | 796 __ mov(rax, rbx); |
| 0 | 797 __ jmp(r11); |
| 798 } | |
| 799 | |
| 800 // --------------------------------------------------------------- | |
| 801 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm, | |
| 802 int total_args_passed, | |
| 803 int comp_args_on_stack, | |
| 804 const BasicType *sig_bt, | |
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805 const VMRegPair *regs, |
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806 AdapterFingerPrint* fingerprint) { |
| 0 | 807 address i2c_entry = __ pc(); |
| 808 | |
| 809 gen_i2c_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs); | |
| 810 | |
| 811 // ------------------------------------------------------------------------- | |
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812 // Generate a C2I adapter. On entry we know rbx holds the Method* during calls |
| 0 | 813 // to the interpreter. The args start out packed in the compiled layout. They |
| 814 // need to be unpacked into the interpreter layout. This will almost always | |
| 815 // require some stack space. We grow the current (compiled) stack, then repack | |
| 816 // the args. We finally end in a jump to the generic interpreter entry point. | |
| 817 // On exit from the interpreter, the interpreter will restore our SP (lest the | |
| 818 // compiled code, which relys solely on SP and not RBP, get sick). | |
| 819 | |
| 820 address c2i_unverified_entry = __ pc(); | |
| 821 Label skip_fixup; | |
| 822 Label ok; | |
| 823 | |
| 824 Register holder = rax; | |
| 825 Register receiver = j_rarg0; | |
| 826 Register temp = rbx; | |
| 827 | |
| 828 { | |
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829 __ load_klass(temp, receiver); |
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830 __ cmpptr(temp, Address(holder, CompiledICHolder::holder_klass_offset())); |
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831 __ movptr(rbx, Address(holder, CompiledICHolder::holder_method_offset())); |
| 0 | 832 __ jcc(Assembler::equal, ok); |
| 833 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub())); | |
| 834 | |
| 835 __ bind(ok); | |
| 836 // Method might have been compiled since the call site was patched to | |
| 837 // interpreted if that is the case treat it as a miss so we can get | |
| 838 // the call site corrected. | |
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839 __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), (int32_t)NULL_WORD); |
| 0 | 840 __ jcc(Assembler::equal, skip_fixup); |
| 841 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub())); | |
| 842 } | |
| 843 | |
| 844 address c2i_entry = __ pc(); | |
| 845 | |
| 846 gen_c2i_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup); | |
| 847 | |
| 848 __ flush(); | |
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849 return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry); |
| 0 | 850 } |
| 851 | |
| 852 int SharedRuntime::c_calling_convention(const BasicType *sig_bt, | |
| 853 VMRegPair *regs, | |
| 854 int total_args_passed) { | |
| 855 // We return the amount of VMRegImpl stack slots we need to reserve for all | |
| 856 // the arguments NOT counting out_preserve_stack_slots. | |
| 857 | |
| 858 // NOTE: These arrays will have to change when c1 is ported | |
| 859 #ifdef _WIN64 | |
| 860 static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = { | |
| 861 c_rarg0, c_rarg1, c_rarg2, c_rarg3 | |
| 862 }; | |
| 863 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_c] = { | |
| 864 c_farg0, c_farg1, c_farg2, c_farg3 | |
| 865 }; | |
| 866 #else | |
| 867 static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = { | |
| 868 c_rarg0, c_rarg1, c_rarg2, c_rarg3, c_rarg4, c_rarg5 | |
| 869 }; | |
| 870 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_c] = { | |
| 871 c_farg0, c_farg1, c_farg2, c_farg3, | |
| 872 c_farg4, c_farg5, c_farg6, c_farg7 | |
| 873 }; | |
| 874 #endif // _WIN64 | |
| 875 | |
| 876 | |
| 877 uint int_args = 0; | |
| 878 uint fp_args = 0; | |
| 879 uint stk_args = 0; // inc by 2 each time | |
| 880 | |
| 881 for (int i = 0; i < total_args_passed; i++) { | |
| 882 switch (sig_bt[i]) { | |
| 883 case T_BOOLEAN: | |
| 884 case T_CHAR: | |
| 885 case T_BYTE: | |
| 886 case T_SHORT: | |
| 887 case T_INT: | |
| 888 if (int_args < Argument::n_int_register_parameters_c) { | |
| 889 regs[i].set1(INT_ArgReg[int_args++]->as_VMReg()); | |
| 890 #ifdef _WIN64 | |
| 891 fp_args++; | |
| 892 // Allocate slots for callee to stuff register args the stack. | |
| 893 stk_args += 2; | |
| 894 #endif | |
| 895 } else { | |
| 896 regs[i].set1(VMRegImpl::stack2reg(stk_args)); | |
| 897 stk_args += 2; | |
| 898 } | |
| 899 break; | |
| 900 case T_LONG: | |
| 901 assert(sig_bt[i + 1] == T_VOID, "expecting half"); | |
| 902 // fall through | |
| 903 case T_OBJECT: | |
| 904 case T_ARRAY: | |
| 905 case T_ADDRESS: | |
| 906 if (int_args < Argument::n_int_register_parameters_c) { | |
| 907 regs[i].set2(INT_ArgReg[int_args++]->as_VMReg()); | |
| 908 #ifdef _WIN64 | |
| 909 fp_args++; | |
| 910 stk_args += 2; | |
| 911 #endif | |
| 912 } else { | |
| 913 regs[i].set2(VMRegImpl::stack2reg(stk_args)); | |
| 914 stk_args += 2; | |
| 915 } | |
| 916 break; | |
| 917 case T_FLOAT: | |
| 918 if (fp_args < Argument::n_float_register_parameters_c) { | |
| 919 regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg()); | |
| 920 #ifdef _WIN64 | |
| 921 int_args++; | |
| 922 // Allocate slots for callee to stuff register args the stack. | |
| 923 stk_args += 2; | |
| 924 #endif | |
| 925 } else { | |
| 926 regs[i].set1(VMRegImpl::stack2reg(stk_args)); | |
| 927 stk_args += 2; | |
| 928 } | |
| 929 break; | |
| 930 case T_DOUBLE: | |
| 931 assert(sig_bt[i + 1] == T_VOID, "expecting half"); | |
| 932 if (fp_args < Argument::n_float_register_parameters_c) { | |
| 933 regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg()); | |
| 934 #ifdef _WIN64 | |
| 935 int_args++; | |
| 936 // Allocate slots for callee to stuff register args the stack. | |
| 937 stk_args += 2; | |
| 938 #endif | |
| 939 } else { | |
| 940 regs[i].set2(VMRegImpl::stack2reg(stk_args)); | |
| 941 stk_args += 2; | |
| 942 } | |
| 943 break; | |
| 944 case T_VOID: // Halves of longs and doubles | |
| 945 assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half"); | |
| 946 regs[i].set_bad(); | |
| 947 break; | |
| 948 default: | |
| 949 ShouldNotReachHere(); | |
| 950 break; | |
| 951 } | |
| 952 } | |
| 953 #ifdef _WIN64 | |
| 954 // windows abi requires that we always allocate enough stack space | |
| 955 // for 4 64bit registers to be stored down. | |
| 956 if (stk_args < 8) { | |
| 957 stk_args = 8; | |
| 958 } | |
| 959 #endif // _WIN64 | |
| 960 | |
| 961 return stk_args; | |
| 962 } | |
| 963 | |
| 964 // On 64 bit we will store integer like items to the stack as | |
| 965 // 64 bits items (sparc abi) even though java would only store | |
| 966 // 32bits for a parameter. On 32bit it will simply be 32 bits | |
| 967 // So this routine will do 32->32 on 32bit and 32->64 on 64bit | |
| 968 static void move32_64(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { | |
| 969 if (src.first()->is_stack()) { | |
| 970 if (dst.first()->is_stack()) { | |
| 971 // stack to stack | |
| 972 __ movslq(rax, Address(rbp, reg2offset_in(src.first()))); | |
| 973 __ movq(Address(rsp, reg2offset_out(dst.first())), rax); | |
| 974 } else { | |
| 975 // stack to reg | |
| 976 __ movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()))); | |
| 977 } | |
| 978 } else if (dst.first()->is_stack()) { | |
| 979 // reg to stack | |
| 980 // Do we really have to sign extend??? | |
| 981 // __ movslq(src.first()->as_Register(), src.first()->as_Register()); | |
| 982 __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register()); | |
| 983 } else { | |
| 984 // Do we really have to sign extend??? | |
| 985 // __ movslq(dst.first()->as_Register(), src.first()->as_Register()); | |
| 986 if (dst.first() != src.first()) { | |
| 987 __ movq(dst.first()->as_Register(), src.first()->as_Register()); | |
| 988 } | |
| 989 } | |
| 990 } | |
| 991 | |
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992 static void move_ptr(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { |
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993 if (src.first()->is_stack()) { |
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994 if (dst.first()->is_stack()) { |
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995 // stack to stack |
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996 __ movq(rax, Address(rbp, reg2offset_in(src.first()))); |
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997 __ movq(Address(rsp, reg2offset_out(dst.first())), rax); |
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998 } else { |
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999 // stack to reg |
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1000 __ movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()))); |
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1001 } |
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1002 } else if (dst.first()->is_stack()) { |
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1003 // reg to stack |
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1004 __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register()); |
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1005 } else { |
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1006 if (dst.first() != src.first()) { |
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1007 __ movq(dst.first()->as_Register(), src.first()->as_Register()); |
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1008 } |
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1009 } |
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1010 } |
| 0 | 1011 |
| 1012 // An oop arg. Must pass a handle not the oop itself | |
| 1013 static void object_move(MacroAssembler* masm, | |
| 1014 OopMap* map, | |
| 1015 int oop_handle_offset, | |
| 1016 int framesize_in_slots, | |
| 1017 VMRegPair src, | |
| 1018 VMRegPair dst, | |
| 1019 bool is_receiver, | |
| 1020 int* receiver_offset) { | |
| 1021 | |
| 1022 // must pass a handle. First figure out the location we use as a handle | |
| 1023 | |
| 1024 Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register(); | |
| 1025 | |
| 1026 // See if oop is NULL if it is we need no handle | |
| 1027 | |
| 1028 if (src.first()->is_stack()) { | |
| 1029 | |
| 1030 // Oop is already on the stack as an argument | |
| 1031 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots(); | |
| 1032 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots)); | |
| 1033 if (is_receiver) { | |
| 1034 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size; | |
| 1035 } | |
| 1036 | |
| 304 | 1037 __ cmpptr(Address(rbp, reg2offset_in(src.first())), (int32_t)NULL_WORD); |
| 1038 __ lea(rHandle, Address(rbp, reg2offset_in(src.first()))); | |
| 0 | 1039 // conditionally move a NULL |
| 304 | 1040 __ cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first()))); |
| 0 | 1041 } else { |
| 1042 | |
| 1043 // Oop is in an a register we must store it to the space we reserve | |
| 1044 // on the stack for oop_handles and pass a handle if oop is non-NULL | |
| 1045 | |
| 1046 const Register rOop = src.first()->as_Register(); | |
| 1047 int oop_slot; | |
| 1048 if (rOop == j_rarg0) | |
| 1049 oop_slot = 0; | |
| 1050 else if (rOop == j_rarg1) | |
| 1051 oop_slot = 1; | |
| 1052 else if (rOop == j_rarg2) | |
| 1053 oop_slot = 2; | |
| 1054 else if (rOop == j_rarg3) | |
| 1055 oop_slot = 3; | |
| 1056 else if (rOop == j_rarg4) | |
| 1057 oop_slot = 4; | |
| 1058 else { | |
| 1059 assert(rOop == j_rarg5, "wrong register"); | |
| 1060 oop_slot = 5; | |
| 1061 } | |
| 1062 | |
| 1063 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset; | |
| 1064 int offset = oop_slot*VMRegImpl::stack_slot_size; | |
| 1065 | |
| 1066 map->set_oop(VMRegImpl::stack2reg(oop_slot)); | |
| 1067 // Store oop in handle area, may be NULL | |
| 304 | 1068 __ movptr(Address(rsp, offset), rOop); |
| 0 | 1069 if (is_receiver) { |
| 1070 *receiver_offset = offset; | |
| 1071 } | |
| 1072 | |
| 304 | 1073 __ cmpptr(rOop, (int32_t)NULL_WORD); |
| 1074 __ lea(rHandle, Address(rsp, offset)); | |
| 0 | 1075 // conditionally move a NULL from the handle area where it was just stored |
| 304 | 1076 __ cmovptr(Assembler::equal, rHandle, Address(rsp, offset)); |
| 0 | 1077 } |
| 1078 | |
| 1079 // If arg is on the stack then place it otherwise it is already in correct reg. | |
| 1080 if (dst.first()->is_stack()) { | |
| 304 | 1081 __ movptr(Address(rsp, reg2offset_out(dst.first())), rHandle); |
| 0 | 1082 } |
| 1083 } | |
| 1084 | |
| 1085 // A float arg may have to do float reg int reg conversion | |
| 1086 static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { | |
| 1087 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move"); | |
| 1088 | |
| 1089 // The calling conventions assures us that each VMregpair is either | |
| 1090 // all really one physical register or adjacent stack slots. | |
| 1091 // This greatly simplifies the cases here compared to sparc. | |
| 1092 | |
| 1093 if (src.first()->is_stack()) { | |
| 1094 if (dst.first()->is_stack()) { | |
| 1095 __ movl(rax, Address(rbp, reg2offset_in(src.first()))); | |
| 304 | 1096 __ movptr(Address(rsp, reg2offset_out(dst.first())), rax); |
| 0 | 1097 } else { |
| 1098 // stack to reg | |
| 1099 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters"); | |
| 1100 __ movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()))); | |
| 1101 } | |
| 1102 } else if (dst.first()->is_stack()) { | |
| 1103 // reg to stack | |
| 1104 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters"); | |
| 1105 __ movflt(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister()); | |
| 1106 } else { | |
| 1107 // reg to reg | |
| 1108 // In theory these overlap but the ordering is such that this is likely a nop | |
| 1109 if ( src.first() != dst.first()) { | |
| 1110 __ movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister()); | |
| 1111 } | |
| 1112 } | |
| 1113 } | |
| 1114 | |
| 1115 // A long move | |
| 1116 static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { | |
| 1117 | |
| 1118 // The calling conventions assures us that each VMregpair is either | |
| 1119 // all really one physical register or adjacent stack slots. | |
| 1120 // This greatly simplifies the cases here compared to sparc. | |
| 1121 | |
| 1122 if (src.is_single_phys_reg() ) { | |
| 1123 if (dst.is_single_phys_reg()) { | |
| 1124 if (dst.first() != src.first()) { | |
| 304 | 1125 __ mov(dst.first()->as_Register(), src.first()->as_Register()); |
| 0 | 1126 } |
| 1127 } else { | |
| 1128 assert(dst.is_single_reg(), "not a stack pair"); | |
| 1129 __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register()); | |
| 1130 } | |
| 1131 } else if (dst.is_single_phys_reg()) { | |
| 1132 assert(src.is_single_reg(), "not a stack pair"); | |
| 1133 __ movq(dst.first()->as_Register(), Address(rbp, reg2offset_out(src.first()))); | |
| 1134 } else { | |
| 1135 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs"); | |
| 1136 __ movq(rax, Address(rbp, reg2offset_in(src.first()))); | |
| 1137 __ movq(Address(rsp, reg2offset_out(dst.first())), rax); | |
| 1138 } | |
| 1139 } | |
| 1140 | |
| 1141 // A double move | |
| 1142 static void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { | |
| 1143 | |
| 1144 // The calling conventions assures us that each VMregpair is either | |
| 1145 // all really one physical register or adjacent stack slots. | |
| 1146 // This greatly simplifies the cases here compared to sparc. | |
| 1147 | |
| 1148 if (src.is_single_phys_reg() ) { | |
| 1149 if (dst.is_single_phys_reg()) { | |
| 1150 // In theory these overlap but the ordering is such that this is likely a nop | |
| 1151 if ( src.first() != dst.first()) { | |
| 1152 __ movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister()); | |
| 1153 } | |
| 1154 } else { | |
| 1155 assert(dst.is_single_reg(), "not a stack pair"); | |
| 1156 __ movdbl(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister()); | |
| 1157 } | |
| 1158 } else if (dst.is_single_phys_reg()) { | |
| 1159 assert(src.is_single_reg(), "not a stack pair"); | |
| 1160 __ movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_out(src.first()))); | |
| 1161 } else { | |
| 1162 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs"); | |
| 1163 __ movq(rax, Address(rbp, reg2offset_in(src.first()))); | |
| 1164 __ movq(Address(rsp, reg2offset_out(dst.first())), rax); | |
| 1165 } | |
| 1166 } | |
| 1167 | |
| 1168 | |
| 1169 void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) { | |
| 1170 // We always ignore the frame_slots arg and just use the space just below frame pointer | |
| 1171 // which by this time is free to use | |
| 1172 switch (ret_type) { | |
| 1173 case T_FLOAT: | |
| 1174 __ movflt(Address(rbp, -wordSize), xmm0); | |
| 1175 break; | |
| 1176 case T_DOUBLE: | |
| 1177 __ movdbl(Address(rbp, -wordSize), xmm0); | |
| 1178 break; | |
| 1179 case T_VOID: break; | |
| 1180 default: { | |
| 304 | 1181 __ movptr(Address(rbp, -wordSize), rax); |
| 0 | 1182 } |
| 1183 } | |
| 1184 } | |
| 1185 | |
| 1186 void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) { | |
| 1187 // We always ignore the frame_slots arg and just use the space just below frame pointer | |
| 1188 // which by this time is free to use | |
| 1189 switch (ret_type) { | |
| 1190 case T_FLOAT: | |
| 1191 __ movflt(xmm0, Address(rbp, -wordSize)); | |
| 1192 break; | |
| 1193 case T_DOUBLE: | |
| 1194 __ movdbl(xmm0, Address(rbp, -wordSize)); | |
| 1195 break; | |
| 1196 case T_VOID: break; | |
| 1197 default: { | |
| 304 | 1198 __ movptr(rax, Address(rbp, -wordSize)); |
| 0 | 1199 } |
| 1200 } | |
| 1201 } | |
| 1202 | |
| 1203 static void save_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) { | |
| 1204 for ( int i = first_arg ; i < arg_count ; i++ ) { | |
| 1205 if (args[i].first()->is_Register()) { | |
| 304 | 1206 __ push(args[i].first()->as_Register()); |
| 0 | 1207 } else if (args[i].first()->is_XMMRegister()) { |
| 304 | 1208 __ subptr(rsp, 2*wordSize); |
| 0 | 1209 __ movdbl(Address(rsp, 0), args[i].first()->as_XMMRegister()); |
| 1210 } | |
| 1211 } | |
| 1212 } | |
| 1213 | |
| 1214 static void restore_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) { | |
| 1215 for ( int i = arg_count - 1 ; i >= first_arg ; i-- ) { | |
| 1216 if (args[i].first()->is_Register()) { | |
| 304 | 1217 __ pop(args[i].first()->as_Register()); |
| 0 | 1218 } else if (args[i].first()->is_XMMRegister()) { |
| 1219 __ movdbl(args[i].first()->as_XMMRegister(), Address(rsp, 0)); | |
| 304 | 1220 __ addptr(rsp, 2*wordSize); |
| 0 | 1221 } |
| 1222 } | |
| 1223 } | |
| 1224 | |
|
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1225 |
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1226 static void save_or_restore_arguments(MacroAssembler* masm, |
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1227 const int stack_slots, |
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1228 const int total_in_args, |
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1229 const int arg_save_area, |
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1230 OopMap* map, |
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1231 VMRegPair* in_regs, |
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1232 BasicType* in_sig_bt) { |
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1233 // if map is non-NULL then the code should store the values, |
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1234 // otherwise it should load them. |
| 5905 | 1235 int slot = arg_save_area; |
|
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1236 // Save down double word first |
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1237 for ( int i = 0; i < total_in_args; i++) { |
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1238 if (in_regs[i].first()->is_XMMRegister() && in_sig_bt[i] == T_DOUBLE) { |
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1239 int offset = slot * VMRegImpl::stack_slot_size; |
| 5905 | 1240 slot += VMRegImpl::slots_per_word; |
| 1241 assert(slot <= stack_slots, "overflow"); | |
|
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1242 if (map != NULL) { |
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1243 __ movdbl(Address(rsp, offset), in_regs[i].first()->as_XMMRegister()); |
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1244 } else { |
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1245 __ movdbl(in_regs[i].first()->as_XMMRegister(), Address(rsp, offset)); |
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1246 } |
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1247 } |
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1248 if (in_regs[i].first()->is_Register() && |
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1249 (in_sig_bt[i] == T_LONG || in_sig_bt[i] == T_ARRAY)) { |
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1250 int offset = slot * VMRegImpl::stack_slot_size; |
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1251 if (map != NULL) { |
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1252 __ movq(Address(rsp, offset), in_regs[i].first()->as_Register()); |
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1253 if (in_sig_bt[i] == T_ARRAY) { |
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1254 map->set_oop(VMRegImpl::stack2reg(slot));; |
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1255 } |
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1256 } else { |
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1257 __ movq(in_regs[i].first()->as_Register(), Address(rsp, offset)); |
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1258 } |
| 5907 | 1259 slot += VMRegImpl::slots_per_word; |
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1260 } |
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1261 } |
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1262 // Save or restore single word registers |
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1263 for ( int i = 0; i < total_in_args; i++) { |
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1264 if (in_regs[i].first()->is_Register()) { |
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1265 int offset = slot * VMRegImpl::stack_slot_size; |
| 5905 | 1266 slot++; |
| 1267 assert(slot <= stack_slots, "overflow"); | |
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1268 |
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1269 // Value is in an input register pass we must flush it to the stack |
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1270 const Register reg = in_regs[i].first()->as_Register(); |
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1271 switch (in_sig_bt[i]) { |
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1272 case T_BOOLEAN: |
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1273 case T_CHAR: |
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1274 case T_BYTE: |
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1275 case T_SHORT: |
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1276 case T_INT: |
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1277 if (map != NULL) { |
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1278 __ movl(Address(rsp, offset), reg); |
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1279 } else { |
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1280 __ movl(reg, Address(rsp, offset)); |
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1281 } |
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1282 break; |
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1283 case T_ARRAY: |
|
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1284 case T_LONG: |
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1285 // handled above |
|
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1286 break; |
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1287 case T_OBJECT: |
|
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1288 default: ShouldNotReachHere(); |
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1289 } |
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1290 } else if (in_regs[i].first()->is_XMMRegister()) { |
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1291 if (in_sig_bt[i] == T_FLOAT) { |
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1292 int offset = slot * VMRegImpl::stack_slot_size; |
| 5905 | 1293 slot++; |
| 1294 assert(slot <= stack_slots, "overflow"); | |
|
4873
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1295 if (map != NULL) { |
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1296 __ movflt(Address(rsp, offset), in_regs[i].first()->as_XMMRegister()); |
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1297 } else { |
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1298 __ movflt(in_regs[i].first()->as_XMMRegister(), Address(rsp, offset)); |
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1299 } |
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1300 } |
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1301 } else if (in_regs[i].first()->is_stack()) { |
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1302 if (in_sig_bt[i] == T_ARRAY && map != NULL) { |
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1303 int offset_in_older_frame = in_regs[i].first()->reg2stack() + SharedRuntime::out_preserve_stack_slots(); |
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1304 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + stack_slots)); |
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1305 } |
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1306 } |
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1307 } |
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1308 } |
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1309 |
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1310 |
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1311 // Check GC_locker::needs_gc and enter the runtime if it's true. This |
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1312 // keeps a new JNI critical region from starting until a GC has been |
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1313 // forced. Save down any oops in registers and describe them in an |
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1314 // OopMap. |
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1315 static void check_needs_gc_for_critical_native(MacroAssembler* masm, |
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1316 int stack_slots, |
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1317 int total_c_args, |
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1318 int total_in_args, |
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1319 int arg_save_area, |
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1320 OopMapSet* oop_maps, |
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1321 VMRegPair* in_regs, |
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1322 BasicType* in_sig_bt) { |
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1323 __ block_comment("check GC_locker::needs_gc"); |
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1324 Label cont; |
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1325 __ cmp8(ExternalAddress((address)GC_locker::needs_gc_address()), false); |
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1326 __ jcc(Assembler::equal, cont); |
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1327 |
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1328 // Save down any incoming oops and call into the runtime to halt for a GC |
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1329 |
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1330 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/); |
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1331 save_or_restore_arguments(masm, stack_slots, total_in_args, |
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1332 arg_save_area, map, in_regs, in_sig_bt); |
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1333 |
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1334 address the_pc = __ pc(); |
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1335 oop_maps->add_gc_map( __ offset(), map); |
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1336 __ set_last_Java_frame(rsp, noreg, the_pc); |
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1337 |
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1338 __ block_comment("block_for_jni_critical"); |
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1339 __ movptr(c_rarg0, r15_thread); |
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1340 __ mov(r12, rsp); // remember sp |
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1341 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows |
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1342 __ andptr(rsp, -16); // align stack as required by ABI |
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1343 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::block_for_jni_critical))); |
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1344 __ mov(rsp, r12); // restore sp |
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1345 __ reinit_heapbase(); |
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1346 |
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1347 __ reset_last_Java_frame(false, true); |
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1348 |
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1349 save_or_restore_arguments(masm, stack_slots, total_in_args, |
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1350 arg_save_area, NULL, in_regs, in_sig_bt); |
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1351 |
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1352 __ bind(cont); |
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1353 #ifdef ASSERT |
|
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1354 if (StressCriticalJNINatives) { |
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1355 // Stress register saving |
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1356 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/); |
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1357 save_or_restore_arguments(masm, stack_slots, total_in_args, |
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1358 arg_save_area, map, in_regs, in_sig_bt); |
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1359 // Destroy argument registers |
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1360 for (int i = 0; i < total_in_args - 1; i++) { |
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1361 if (in_regs[i].first()->is_Register()) { |
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1362 const Register reg = in_regs[i].first()->as_Register(); |
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1363 __ xorptr(reg, reg); |
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1364 } else if (in_regs[i].first()->is_XMMRegister()) { |
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1365 __ xorpd(in_regs[i].first()->as_XMMRegister(), in_regs[i].first()->as_XMMRegister()); |
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1366 } else if (in_regs[i].first()->is_FloatRegister()) { |
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1367 ShouldNotReachHere(); |
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1368 } else if (in_regs[i].first()->is_stack()) { |
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1369 // Nothing to do |
|
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1370 } else { |
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1371 ShouldNotReachHere(); |
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1372 } |
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1373 if (in_sig_bt[i] == T_LONG || in_sig_bt[i] == T_DOUBLE) { |
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1374 i++; |
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1375 } |
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1376 } |
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1377 |
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1378 save_or_restore_arguments(masm, stack_slots, total_in_args, |
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1379 arg_save_area, NULL, in_regs, in_sig_bt); |
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1380 } |
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1381 #endif |
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1382 } |
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1383 |
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1384 // Unpack an array argument into a pointer to the body and the length |
|
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1385 // if the array is non-null, otherwise pass 0 for both. |
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1386 static void unpack_array_argument(MacroAssembler* masm, VMRegPair reg, BasicType in_elem_type, VMRegPair body_arg, VMRegPair length_arg) { |
|
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1387 Register tmp_reg = rax; |
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1388 assert(!body_arg.first()->is_Register() || body_arg.first()->as_Register() != tmp_reg, |
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1389 "possible collision"); |
|
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1390 assert(!length_arg.first()->is_Register() || length_arg.first()->as_Register() != tmp_reg, |
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1391 "possible collision"); |
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1392 |
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1393 // Pass the length, ptr pair |
|
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1394 Label is_null, done; |
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1395 VMRegPair tmp; |
|
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1396 tmp.set_ptr(tmp_reg->as_VMReg()); |
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1397 if (reg.first()->is_stack()) { |
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1398 // Load the arg up from the stack |
|
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1399 move_ptr(masm, reg, tmp); |
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1400 reg = tmp; |
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1401 } |
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1402 __ testptr(reg.first()->as_Register(), reg.first()->as_Register()); |
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1403 __ jccb(Assembler::equal, is_null); |
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1404 __ lea(tmp_reg, Address(reg.first()->as_Register(), arrayOopDesc::base_offset_in_bytes(in_elem_type))); |
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1405 move_ptr(masm, tmp, body_arg); |
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1406 // load the length relative to the body. |
|
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1407 __ movl(tmp_reg, Address(tmp_reg, arrayOopDesc::length_offset_in_bytes() - |
|
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1408 arrayOopDesc::base_offset_in_bytes(in_elem_type))); |
|
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|
1409 move32_64(masm, tmp, length_arg); |
|
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1410 __ jmpb(done); |
|
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1411 __ bind(is_null); |
|
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1412 // Pass zeros |
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1413 __ xorptr(tmp_reg, tmp_reg); |
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1414 move_ptr(masm, tmp, body_arg); |
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1415 move32_64(masm, tmp, length_arg); |
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1416 __ bind(done); |
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1417 } |
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1418 |
| 5905 | 1419 |
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1420 // Different signatures may require very different orders for the move |
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1421 // to avoid clobbering other arguments. There's no simple way to |
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1422 // order them safely. Compute a safe order for issuing stores and |
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1423 // break any cycles in those stores. This code is fairly general but |
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1424 // it's not necessary on the other platforms so we keep it in the |
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1425 // platform dependent code instead of moving it into a shared file. |
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1426 // (See bugs 7013347 & 7145024.) |
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1427 // Note that this code is specific to LP64. |
| 5905 | 1428 class ComputeMoveOrder: public StackObj { |
| 1429 class MoveOperation: public ResourceObj { | |
| 1430 friend class ComputeMoveOrder; | |
| 1431 private: | |
| 1432 VMRegPair _src; | |
| 1433 VMRegPair _dst; | |
| 1434 int _src_index; | |
| 1435 int _dst_index; | |
| 1436 bool _processed; | |
| 1437 MoveOperation* _next; | |
| 1438 MoveOperation* _prev; | |
| 1439 | |
| 1440 static int get_id(VMRegPair r) { | |
| 1441 return r.first()->value(); | |
| 1442 } | |
| 1443 | |
| 1444 public: | |
| 1445 MoveOperation(int src_index, VMRegPair src, int dst_index, VMRegPair dst): | |
| 1446 _src(src) | |
| 1447 , _src_index(src_index) | |
| 1448 , _dst(dst) | |
| 1449 , _dst_index(dst_index) | |
| 1450 , _next(NULL) | |
| 1451 , _prev(NULL) | |
| 1452 , _processed(false) { | |
| 1453 } | |
| 1454 | |
| 1455 VMRegPair src() const { return _src; } | |
| 1456 int src_id() const { return get_id(src()); } | |
| 1457 int src_index() const { return _src_index; } | |
| 1458 VMRegPair dst() const { return _dst; } | |
| 1459 void set_dst(int i, VMRegPair dst) { _dst_index = i, _dst = dst; } | |
| 1460 int dst_index() const { return _dst_index; } | |
| 1461 int dst_id() const { return get_id(dst()); } | |
| 1462 MoveOperation* next() const { return _next; } | |
| 1463 MoveOperation* prev() const { return _prev; } | |
| 1464 void set_processed() { _processed = true; } | |
| 1465 bool is_processed() const { return _processed; } | |
| 1466 | |
| 1467 // insert | |
| 1468 void break_cycle(VMRegPair temp_register) { | |
| 1469 // create a new store following the last store | |
| 1470 // to move from the temp_register to the original | |
| 1471 MoveOperation* new_store = new MoveOperation(-1, temp_register, dst_index(), dst()); | |
| 1472 | |
| 1473 // break the cycle of links and insert new_store at the end | |
| 1474 // break the reverse link. | |
| 1475 MoveOperation* p = prev(); | |
| 1476 assert(p->next() == this, "must be"); | |
| 1477 _prev = NULL; | |
| 1478 p->_next = new_store; | |
| 1479 new_store->_prev = p; | |
| 1480 | |
| 1481 // change the original store to save it's value in the temp. | |
| 1482 set_dst(-1, temp_register); | |
| 1483 } | |
| 1484 | |
| 1485 void link(GrowableArray<MoveOperation*>& killer) { | |
| 1486 // link this store in front the store that it depends on | |
| 1487 MoveOperation* n = killer.at_grow(src_id(), NULL); | |
| 1488 if (n != NULL) { | |
| 1489 assert(_next == NULL && n->_prev == NULL, "shouldn't have been set yet"); | |
| 1490 _next = n; | |
| 1491 n->_prev = this; | |
| 1492 } | |
| 1493 } | |
| 1494 }; | |
| 1495 | |
| 1496 private: | |
| 1497 GrowableArray<MoveOperation*> edges; | |
| 1498 | |
| 1499 public: | |
| 1500 ComputeMoveOrder(int total_in_args, VMRegPair* in_regs, int total_c_args, VMRegPair* out_regs, | |
| 1501 BasicType* in_sig_bt, GrowableArray<int>& arg_order, VMRegPair tmp_vmreg) { | |
| 1502 // Move operations where the dest is the stack can all be | |
| 1503 // scheduled first since they can't interfere with the other moves. | |
| 1504 for (int i = total_in_args - 1, c_arg = total_c_args - 1; i >= 0; i--, c_arg--) { | |
| 1505 if (in_sig_bt[i] == T_ARRAY) { | |
| 1506 c_arg--; | |
| 1507 if (out_regs[c_arg].first()->is_stack() && | |
| 1508 out_regs[c_arg + 1].first()->is_stack()) { | |
| 1509 arg_order.push(i); | |
| 1510 arg_order.push(c_arg); | |
| 1511 } else { | |
| 1512 if (out_regs[c_arg].first()->is_stack() || | |
| 1513 in_regs[i].first() == out_regs[c_arg].first()) { | |
| 1514 add_edge(i, in_regs[i].first(), c_arg, out_regs[c_arg + 1]); | |
| 1515 } else { | |
| 1516 add_edge(i, in_regs[i].first(), c_arg, out_regs[c_arg]); | |
| 1517 } | |
| 1518 } | |
| 1519 } else if (in_sig_bt[i] == T_VOID) { | |
| 1520 arg_order.push(i); | |
| 1521 arg_order.push(c_arg); | |
| 1522 } else { | |
| 1523 if (out_regs[c_arg].first()->is_stack() || | |
| 1524 in_regs[i].first() == out_regs[c_arg].first()) { | |
| 1525 arg_order.push(i); | |
| 1526 arg_order.push(c_arg); | |
| 1527 } else { | |
| 1528 add_edge(i, in_regs[i].first(), c_arg, out_regs[c_arg]); | |
| 1529 } | |
| 1530 } | |
| 1531 } | |
| 1532 // Break any cycles in the register moves and emit the in the | |
| 1533 // proper order. | |
| 1534 GrowableArray<MoveOperation*>* stores = get_store_order(tmp_vmreg); | |
| 1535 for (int i = 0; i < stores->length(); i++) { | |
| 1536 arg_order.push(stores->at(i)->src_index()); | |
| 1537 arg_order.push(stores->at(i)->dst_index()); | |
| 1538 } | |
| 1539 } | |
| 1540 | |
| 1541 // Collected all the move operations | |
| 1542 void add_edge(int src_index, VMRegPair src, int dst_index, VMRegPair dst) { | |
| 1543 if (src.first() == dst.first()) return; | |
| 1544 edges.append(new MoveOperation(src_index, src, dst_index, dst)); | |
| 1545 } | |
| 1546 | |
| 1547 // Walk the edges breaking cycles between moves. The result list | |
| 1548 // can be walked in order to produce the proper set of loads | |
| 1549 GrowableArray<MoveOperation*>* get_store_order(VMRegPair temp_register) { | |
| 1550 // Record which moves kill which values | |
| 1551 GrowableArray<MoveOperation*> killer; | |
| 1552 for (int i = 0; i < edges.length(); i++) { | |
| 1553 MoveOperation* s = edges.at(i); | |
| 1554 assert(killer.at_grow(s->dst_id(), NULL) == NULL, "only one killer"); | |
| 1555 killer.at_put_grow(s->dst_id(), s, NULL); | |
| 1556 } | |
| 1557 assert(killer.at_grow(MoveOperation::get_id(temp_register), NULL) == NULL, | |
| 1558 "make sure temp isn't in the registers that are killed"); | |
| 1559 | |
| 1560 // create links between loads and stores | |
| 1561 for (int i = 0; i < edges.length(); i++) { | |
| 1562 edges.at(i)->link(killer); | |
| 1563 } | |
| 1564 | |
| 1565 // at this point, all the move operations are chained together | |
| 1566 // in a doubly linked list. Processing it backwards finds | |
| 1567 // the beginning of the chain, forwards finds the end. If there's | |
| 1568 // a cycle it can be broken at any point, so pick an edge and walk | |
| 1569 // backward until the list ends or we end where we started. | |
| 1570 GrowableArray<MoveOperation*>* stores = new GrowableArray<MoveOperation*>(); | |
| 1571 for (int e = 0; e < edges.length(); e++) { | |
| 1572 MoveOperation* s = edges.at(e); | |
| 1573 if (!s->is_processed()) { | |
| 1574 MoveOperation* start = s; | |
| 1575 // search for the beginning of the chain or cycle | |
| 1576 while (start->prev() != NULL && start->prev() != s) { | |
| 1577 start = start->prev(); | |
| 1578 } | |
| 1579 if (start->prev() == s) { | |
| 1580 start->break_cycle(temp_register); | |
| 1581 } | |
| 1582 // walk the chain forward inserting to store list | |
| 1583 while (start != NULL) { | |
| 1584 stores->append(start); | |
| 1585 start->set_processed(); | |
| 1586 start = start->next(); | |
| 1587 } | |
| 1588 } | |
| 1589 } | |
| 1590 return stores; | |
| 1591 } | |
| 1592 }; | |
| 1593 | |
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1594 static void verify_oop_args(MacroAssembler* masm, |
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1595 int total_args_passed, |
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1596 const BasicType* sig_bt, |
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1597 const VMRegPair* regs) { |
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1598 Register temp_reg = rbx; // not part of any compiled calling seq |
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1599 if (VerifyOops) { |
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1600 for (int i = 0; i < total_args_passed; i++) { |
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1601 if (sig_bt[i] == T_OBJECT || |
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1602 sig_bt[i] == T_ARRAY) { |
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1603 VMReg r = regs[i].first(); |
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1604 assert(r->is_valid(), "bad oop arg"); |
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1605 if (r->is_stack()) { |
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1606 __ movptr(temp_reg, Address(rsp, r->reg2stack() * VMRegImpl::stack_slot_size + wordSize)); |
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1607 __ verify_oop(temp_reg); |
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1608 } else { |
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1609 __ verify_oop(r->as_Register()); |
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1610 } |
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1611 } |
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1612 } |
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1613 } |
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1614 } |
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1615 |
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1616 static void gen_special_dispatch(MacroAssembler* masm, |
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1617 int total_args_passed, |
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1618 int comp_args_on_stack, |
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1619 vmIntrinsics::ID special_dispatch, |
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1620 const BasicType* sig_bt, |
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1621 const VMRegPair* regs) { |
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1622 verify_oop_args(masm, total_args_passed, sig_bt, regs); |
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1623 |
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1624 // Now write the args into the outgoing interpreter space |
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1625 bool has_receiver = false; |
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1626 Register receiver_reg = noreg; |
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1627 int member_arg_pos = -1; |
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1628 Register member_reg = noreg; |
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1629 int ref_kind = MethodHandles::signature_polymorphic_intrinsic_ref_kind(special_dispatch); |
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1630 if (ref_kind != 0) { |
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1631 member_arg_pos = total_args_passed - 1; // trailing MemberName argument |
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1632 member_reg = rbx; // known to be free at this point |
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1633 has_receiver = MethodHandles::ref_kind_has_receiver(ref_kind); |
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1634 } else if (special_dispatch == vmIntrinsics::_invokeBasic) { |
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1635 has_receiver = true; |
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1636 } else { |
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1637 guarantee(false, err_msg("special_dispatch=%d", special_dispatch)); |
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1638 } |
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1639 |
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1640 if (member_reg != noreg) { |
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1641 // Load the member_arg into register, if necessary. |
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1642 assert(member_arg_pos >= 0 && member_arg_pos < total_args_passed, "oob"); |
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1643 assert(sig_bt[member_arg_pos] == T_OBJECT, "dispatch argument must be an object"); |
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1644 VMReg r = regs[member_arg_pos].first(); |
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1645 assert(r->is_valid(), "bad member arg"); |
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1646 if (r->is_stack()) { |
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1647 __ movptr(member_reg, Address(rsp, r->reg2stack() * VMRegImpl::stack_slot_size + wordSize)); |
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1648 } else { |
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1649 // no data motion is needed |
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1650 member_reg = r->as_Register(); |
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1651 } |
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1652 } |
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1653 |
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1654 if (has_receiver) { |
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1655 // Make sure the receiver is loaded into a register. |
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1656 assert(total_args_passed > 0, "oob"); |
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1657 assert(sig_bt[0] == T_OBJECT, "receiver argument must be an object"); |
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1658 VMReg r = regs[0].first(); |
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1659 assert(r->is_valid(), "bad receiver arg"); |
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1660 if (r->is_stack()) { |
|
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1661 // Porting note: This assumes that compiled calling conventions always |
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1662 // pass the receiver oop in a register. If this is not true on some |
|
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1663 // platform, pick a temp and load the receiver from stack. |
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1664 assert(false, "receiver always in a register"); |
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1665 receiver_reg = j_rarg0; // known to be free at this point |
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1666 __ movptr(receiver_reg, Address(rsp, r->reg2stack() * VMRegImpl::stack_slot_size + wordSize)); |
|
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1667 } else { |
|
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1668 // no data motion is needed |
|
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1669 receiver_reg = r->as_Register(); |
|
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1670 } |
|
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1671 } |
|
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1672 |
|
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1673 // Figure out which address we are really jumping to: |
|
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1674 MethodHandles::generate_method_handle_dispatch(masm, special_dispatch, |
|
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1675 receiver_reg, member_reg, /*for_compiler_entry:*/ true); |
|
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1676 } |
| 5905 | 1677 |
| 0 | 1678 // --------------------------------------------------------------------------- |
| 1679 // Generate a native wrapper for a given method. The method takes arguments | |
| 1680 // in the Java compiled code convention, marshals them to the native | |
| 1681 // convention (handlizes oops, etc), transitions to native, makes the call, | |
| 1682 // returns to java state (possibly blocking), unhandlizes any result and | |
| 1683 // returns. | |
|
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1684 // |
|
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1685 // Critical native functions are a shorthand for the use of |
|
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1686 // GetPrimtiveArrayCritical and disallow the use of any other JNI |
|
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1687 // functions. The wrapper is expected to unpack the arguments before |
|
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1688 // passing them to the callee and perform checks before and after the |
|
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1689 // native call to ensure that they GC_locker |
|
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1690 // lock_critical/unlock_critical semantics are followed. Some other |
|
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1691 // parts of JNI setup are skipped like the tear down of the JNI handle |
|
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1692 // block and the check for pending exceptions it's impossible for them |
|
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1693 // to be thrown. |
|
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1694 // |
|
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1695 // They are roughly structured like this: |
|
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1696 // if (GC_locker::needs_gc()) |
|
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1697 // SharedRuntime::block_for_jni_critical(); |
|
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1698 // tranistion to thread_in_native |
|
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1699 // unpack arrray arguments and call native entry point |
|
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1700 // check for safepoint in progress |
|
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1701 // check if any thread suspend flags are set |
|
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1702 // call into JVM and possible unlock the JNI critical |
|
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1703 // if a GC was suppressed while in the critical native. |
|
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1704 // transition back to thread_in_Java |
|
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1705 // return to caller |
|
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1706 // |
|
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|
1707 nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm, |
| 0 | 1708 methodHandle method, |
|
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1709 int compile_id, |
| 0 | 1710 int total_in_args, |
| 1711 int comp_args_on_stack, | |
|
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1712 BasicType* in_sig_bt, |
|
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1713 VMRegPair* in_regs, |
| 0 | 1714 BasicType ret_type) { |
|
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1715 if (method->is_method_handle_intrinsic()) { |
|
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1716 vmIntrinsics::ID iid = method->intrinsic_id(); |
|
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1717 intptr_t start = (intptr_t)__ pc(); |
|
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1718 int vep_offset = ((intptr_t)__ pc()) - start; |
|
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1719 gen_special_dispatch(masm, |
|
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|
1720 total_in_args, |
|
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|
1721 comp_args_on_stack, |
|
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1722 method->intrinsic_id(), |
|
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|
1723 in_sig_bt, |
|
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|
1724 in_regs); |
|
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|
1725 int frame_complete = ((intptr_t)__ pc()) - start; // not complete, period |
|
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|
1726 __ flush(); |
|
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|
1727 int stack_slots = SharedRuntime::out_preserve_stack_slots(); // no out slots at all, actually |
|
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|
1728 return nmethod::new_native_nmethod(method, |
|
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|
1729 compile_id, |
|
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|
1730 masm->code(), |
|
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|
1731 vep_offset, |
|
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|
1732 frame_complete, |
|
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|
1733 stack_slots / VMRegImpl::slots_per_word, |
|
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|
1734 in_ByteSize(-1), |
|
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|
1735 in_ByteSize(-1), |
|
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|
1736 (OopMapSet*)NULL); |
|
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|
1737 } |
|
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|
1738 bool is_critical_native = true; |
|
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|
1739 address native_func = method->critical_native_function(); |
|
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|
1740 if (native_func == NULL) { |
|
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|
1741 native_func = method->native_function(); |
|
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|
1742 is_critical_native = false; |
|
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|
1743 } |
|
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|
1744 assert(native_func != NULL, "must have function"); |
|
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|
1745 |
| 0 | 1746 // An OopMap for lock (and class if static) |
| 1747 OopMapSet *oop_maps = new OopMapSet(); | |
| 1748 intptr_t start = (intptr_t)__ pc(); | |
| 1749 | |
| 1750 // We have received a description of where all the java arg are located | |
| 1751 // on entry to the wrapper. We need to convert these args to where | |
| 1752 // the jni function will expect them. To figure out where they go | |
| 1753 // we convert the java signature to a C signature by inserting | |
| 1754 // the hidden arguments as arg[0] and possibly arg[1] (static method) | |
| 1755 | |
|
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|
1756 int total_c_args = total_in_args; |
|
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|
1757 if (!is_critical_native) { |
|
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|
1758 total_c_args += 1; |
|
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|
1759 if (method->is_static()) { |
|
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|
1760 total_c_args++; |
|
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|
1761 } |
|
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|
1762 } else { |
|
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|
1763 for (int i = 0; i < total_in_args; i++) { |
|
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|
1764 if (in_sig_bt[i] == T_ARRAY) { |
|
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|
1765 total_c_args++; |
|
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|
1766 } |
|
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|
1767 } |
| 0 | 1768 } |
| 1769 | |
| 1770 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args); | |
|
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|
1771 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args); |
|
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|
1772 BasicType* in_elem_bt = NULL; |
| 0 | 1773 |
| 1774 int argc = 0; | |
|
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|
1775 if (!is_critical_native) { |
|
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|
1776 out_sig_bt[argc++] = T_ADDRESS; |
|
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|
1777 if (method->is_static()) { |
|
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|
1778 out_sig_bt[argc++] = T_OBJECT; |
|
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|
1779 } |
|
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|
1780 |
|
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|
1781 for (int i = 0; i < total_in_args ; i++ ) { |
|
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|
1782 out_sig_bt[argc++] = in_sig_bt[i]; |
|
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|
1783 } |
|
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|
1784 } else { |
|
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|
1785 Thread* THREAD = Thread::current(); |
|
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|
1786 in_elem_bt = NEW_RESOURCE_ARRAY(BasicType, total_in_args); |
|
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|
1787 SignatureStream ss(method->signature()); |
|
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|
1788 for (int i = 0; i < total_in_args ; i++ ) { |
|
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|
1789 if (in_sig_bt[i] == T_ARRAY) { |
|
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|
1790 // Arrays are passed as int, elem* pair |
|
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|
1791 out_sig_bt[argc++] = T_INT; |
|
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|
1792 out_sig_bt[argc++] = T_ADDRESS; |
|
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|
1793 Symbol* atype = ss.as_symbol(CHECK_NULL); |
|
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|
1794 const char* at = atype->as_C_string(); |
|
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|
1795 if (strlen(at) == 2) { |
|
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|
1796 assert(at[0] == '[', "must be"); |
|
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|
1797 switch (at[1]) { |
|
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|
1798 case 'B': in_elem_bt[i] = T_BYTE; break; |
|
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1799 case 'C': in_elem_bt[i] = T_CHAR; break; |
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1800 case 'D': in_elem_bt[i] = T_DOUBLE; break; |
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1801 case 'F': in_elem_bt[i] = T_FLOAT; break; |
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1802 case 'I': in_elem_bt[i] = T_INT; break; |
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1803 case 'J': in_elem_bt[i] = T_LONG; break; |
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1804 case 'S': in_elem_bt[i] = T_SHORT; break; |
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1805 case 'Z': in_elem_bt[i] = T_BOOLEAN; break; |
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1806 default: ShouldNotReachHere(); |
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1807 } |
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1808 } |
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1809 } else { |
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1810 out_sig_bt[argc++] = in_sig_bt[i]; |
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1811 in_elem_bt[i] = T_VOID; |
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1812 } |
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1813 if (in_sig_bt[i] != T_VOID) { |
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1814 assert(in_sig_bt[i] == ss.type(), "must match"); |
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1815 ss.next(); |
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1816 } |
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1817 } |
| 0 | 1818 } |
| 1819 | |
| 1820 // Now figure out where the args must be stored and how much stack space | |
| 1821 // they require. | |
| 1822 int out_arg_slots; | |
| 1823 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args); | |
| 1824 | |
| 1825 // Compute framesize for the wrapper. We need to handlize all oops in | |
| 1826 // incoming registers | |
| 1827 | |
| 1828 // Calculate the total number of stack slots we will need. | |
| 1829 | |
| 1830 // First count the abi requirement plus all of the outgoing args | |
| 1831 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots; | |
| 1832 | |
| 1833 // Now the space for the inbound oop handle area | |
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1834 int total_save_slots = 6 * VMRegImpl::slots_per_word; // 6 arguments passed in registers |
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1835 if (is_critical_native) { |
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1836 // Critical natives may have to call out so they need a save area |
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1837 // for register arguments. |
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1838 int double_slots = 0; |
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1839 int single_slots = 0; |
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1840 for ( int i = 0; i < total_in_args; i++) { |
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1841 if (in_regs[i].first()->is_Register()) { |
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1842 const Register reg = in_regs[i].first()->as_Register(); |
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1843 switch (in_sig_bt[i]) { |
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1844 case T_BOOLEAN: |
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1845 case T_BYTE: |
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1846 case T_SHORT: |
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1847 case T_CHAR: |
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1848 case T_INT: single_slots++; break; |
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1849 case T_ARRAY: // specific to LP64 (7145024) |
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1850 case T_LONG: double_slots++; break; |
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1851 default: ShouldNotReachHere(); |
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1852 } |
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1853 } else if (in_regs[i].first()->is_XMMRegister()) { |
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1854 switch (in_sig_bt[i]) { |
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1855 case T_FLOAT: single_slots++; break; |
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1856 case T_DOUBLE: double_slots++; break; |
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1857 default: ShouldNotReachHere(); |
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1858 } |
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1859 } else if (in_regs[i].first()->is_FloatRegister()) { |
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1860 ShouldNotReachHere(); |
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1861 } |
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1862 } |
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1863 total_save_slots = double_slots * 2 + single_slots; |
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1864 // align the save area |
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1865 if (double_slots != 0) { |
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1866 stack_slots = round_to(stack_slots, 2); |
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1867 } |
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1868 } |
| 0 | 1869 |
| 1870 int oop_handle_offset = stack_slots; | |
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1871 stack_slots += total_save_slots; |
| 0 | 1872 |
| 1873 // Now any space we need for handlizing a klass if static method | |
| 1874 | |
| 1875 int klass_slot_offset = 0; | |
| 1876 int klass_offset = -1; | |
| 1877 int lock_slot_offset = 0; | |
| 1878 bool is_static = false; | |
| 1879 | |
| 1880 if (method->is_static()) { | |
| 1881 klass_slot_offset = stack_slots; | |
| 1882 stack_slots += VMRegImpl::slots_per_word; | |
| 1883 klass_offset = klass_slot_offset * VMRegImpl::stack_slot_size; | |
| 1884 is_static = true; | |
| 1885 } | |
| 1886 | |
| 1887 // Plus a lock if needed | |
| 1888 | |
| 1889 if (method->is_synchronized()) { | |
| 1890 lock_slot_offset = stack_slots; | |
| 1891 stack_slots += VMRegImpl::slots_per_word; | |
| 1892 } | |
| 1893 | |
| 1894 // Now a place (+2) to save return values or temp during shuffling | |
| 1895 // + 4 for return address (which we own) and saved rbp | |
| 1896 stack_slots += 6; | |
| 1897 | |
| 1898 // Ok The space we have allocated will look like: | |
| 1899 // | |
| 1900 // | |
| 1901 // FP-> | | | |
| 1902 // |---------------------| | |
| 1903 // | 2 slots for moves | | |
| 1904 // |---------------------| | |
| 1905 // | lock box (if sync) | | |
| 1906 // |---------------------| <- lock_slot_offset | |
| 1907 // | klass (if static) | | |
| 1908 // |---------------------| <- klass_slot_offset | |
| 1909 // | oopHandle area | | |
| 1910 // |---------------------| <- oop_handle_offset (6 java arg registers) | |
| 1911 // | outbound memory | | |
| 1912 // | based arguments | | |
| 1913 // | | | |
| 1914 // |---------------------| | |
| 1915 // | | | |
| 1916 // SP-> | out_preserved_slots | | |
| 1917 // | |
| 1918 // | |
| 1919 | |
| 1920 | |
| 1921 // Now compute actual number of stack words we need rounding to make | |
| 1922 // stack properly aligned. | |
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1923 stack_slots = round_to(stack_slots, StackAlignmentInSlots); |
| 0 | 1924 |
| 1925 int stack_size = stack_slots * VMRegImpl::stack_slot_size; | |
| 1926 | |
| 1927 // First thing make an ic check to see if we should even be here | |
| 1928 | |
| 1929 // We are free to use all registers as temps without saving them and | |
| 1930 // restoring them except rbp. rbp is the only callee save register | |
| 1931 // as far as the interpreter and the compiler(s) are concerned. | |
| 1932 | |
| 1933 | |
| 1934 const Register ic_reg = rax; | |
| 1935 const Register receiver = j_rarg0; | |
| 1936 | |
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1937 Label hit; |
| 0 | 1938 Label exception_pending; |
| 1939 | |
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1940 assert_different_registers(ic_reg, receiver, rscratch1); |
| 0 | 1941 __ verify_oop(receiver); |
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1942 __ load_klass(rscratch1, receiver); |
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1943 __ cmpq(ic_reg, rscratch1); |
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1944 __ jcc(Assembler::equal, hit); |
| 0 | 1945 |
| 1946 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub())); | |
| 1947 | |
| 1948 // Verified entry point must be aligned | |
| 1949 __ align(8); | |
| 1950 | |
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1951 __ bind(hit); |
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1952 |
| 0 | 1953 int vep_offset = ((intptr_t)__ pc()) - start; |
| 1954 | |
| 1955 // The instruction at the verified entry point must be 5 bytes or longer | |
| 1956 // because it can be patched on the fly by make_non_entrant. The stack bang | |
| 1957 // instruction fits that requirement. | |
| 1958 | |
| 1959 // Generate stack overflow check | |
| 1960 | |
| 1961 if (UseStackBanging) { | |
| 1962 __ bang_stack_with_offset(StackShadowPages*os::vm_page_size()); | |
| 1963 } else { | |
| 1964 // need a 5 byte instruction to allow MT safe patching to non-entrant | |
| 1965 __ fat_nop(); | |
| 1966 } | |
| 1967 | |
| 1968 // Generate a new frame for the wrapper. | |
| 1969 __ enter(); | |
| 1970 // -2 because return address is already present and so is saved rbp | |
| 304 | 1971 __ subptr(rsp, stack_size - 2*wordSize); |
| 0 | 1972 |
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1973 // Frame is now completed as far as size and linkage. |
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1974 int frame_complete = ((intptr_t)__ pc()) - start; |
| 0 | 1975 |
| 1976 #ifdef ASSERT | |
| 1977 { | |
| 1978 Label L; | |
| 304 | 1979 __ mov(rax, rsp); |
| 605 | 1980 __ andptr(rax, -16); // must be 16 byte boundary (see amd64 ABI) |
| 304 | 1981 __ cmpptr(rax, rsp); |
| 0 | 1982 __ jcc(Assembler::equal, L); |
| 1983 __ stop("improperly aligned stack"); | |
| 1984 __ bind(L); | |
| 1985 } | |
| 1986 #endif /* ASSERT */ | |
| 1987 | |
| 1988 | |
| 1989 // We use r14 as the oop handle for the receiver/klass | |
| 1990 // It is callee save so it survives the call to native | |
| 1991 | |
| 1992 const Register oop_handle_reg = r14; | |
| 1993 | |
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1994 if (is_critical_native) { |
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1995 check_needs_gc_for_critical_native(masm, stack_slots, total_c_args, total_in_args, |
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1996 oop_handle_offset, oop_maps, in_regs, in_sig_bt); |
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1997 } |
| 0 | 1998 |
| 1999 // | |
| 2000 // We immediately shuffle the arguments so that any vm call we have to | |
| 2001 // make from here on out (sync slow path, jvmti, etc.) we will have | |
| 2002 // captured the oops from our caller and have a valid oopMap for | |
| 2003 // them. | |
| 2004 | |
| 2005 // ----------------- | |
| 2006 // The Grand Shuffle | |
| 2007 | |
| 2008 // The Java calling convention is either equal (linux) or denser (win64) than the | |
| 2009 // c calling convention. However the because of the jni_env argument the c calling | |
| 2010 // convention always has at least one more (and two for static) arguments than Java. | |
| 2011 // Therefore if we move the args from java -> c backwards then we will never have | |
| 2012 // a register->register conflict and we don't have to build a dependency graph | |
| 2013 // and figure out how to break any cycles. | |
| 2014 // | |
| 2015 | |
| 2016 // Record esp-based slot for receiver on stack for non-static methods | |
| 2017 int receiver_offset = -1; | |
| 2018 | |
| 2019 // This is a trick. We double the stack slots so we can claim | |
| 2020 // the oops in the caller's frame. Since we are sure to have | |
| 2021 // more args than the caller doubling is enough to make | |
| 2022 // sure we can capture all the incoming oop args from the | |
| 2023 // caller. | |
| 2024 // | |
| 2025 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/); | |
| 2026 | |
| 2027 // Mark location of rbp (someday) | |
| 2028 // map->set_callee_saved(VMRegImpl::stack2reg( stack_slots - 2), stack_slots * 2, 0, vmreg(rbp)); | |
| 2029 | |
| 2030 // Use eax, ebx as temporaries during any memory-memory moves we have to do | |
| 2031 // All inbound args are referenced based on rbp and all outbound args via rsp. | |
| 2032 | |
| 2033 | |
| 2034 #ifdef ASSERT | |
| 2035 bool reg_destroyed[RegisterImpl::number_of_registers]; | |
| 2036 bool freg_destroyed[XMMRegisterImpl::number_of_registers]; | |
| 2037 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) { | |
| 2038 reg_destroyed[r] = false; | |
| 2039 } | |
| 2040 for ( int f = 0 ; f < XMMRegisterImpl::number_of_registers ; f++ ) { | |
| 2041 freg_destroyed[f] = false; | |
| 2042 } | |
| 2043 | |
| 2044 #endif /* ASSERT */ | |
| 2045 | |
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2046 // This may iterate in two different directions depending on the |
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2047 // kind of native it is. The reason is that for regular JNI natives |
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2048 // the incoming and outgoing registers are offset upwards and for |
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2049 // critical natives they are offset down. |
| 5905 | 2050 GrowableArray<int> arg_order(2 * total_in_args); |
| 2051 VMRegPair tmp_vmreg; | |
| 2052 tmp_vmreg.set1(rbx->as_VMReg()); | |
| 2053 | |
| 2054 if (!is_critical_native) { | |
| 2055 for (int i = total_in_args - 1, c_arg = total_c_args - 1; i >= 0; i--, c_arg--) { | |
| 2056 arg_order.push(i); | |
| 2057 arg_order.push(c_arg); | |
| 2058 } | |
| 2059 } else { | |
| 2060 // Compute a valid move order, using tmp_vmreg to break any cycles | |
| 2061 ComputeMoveOrder cmo(total_in_args, in_regs, total_c_args, out_regs, in_sig_bt, arg_order, tmp_vmreg); | |
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2062 } |
| 5905 | 2063 |
| 2064 int temploc = -1; | |
| 2065 for (int ai = 0; ai < arg_order.length(); ai += 2) { | |
| 2066 int i = arg_order.at(ai); | |
| 2067 int c_arg = arg_order.at(ai + 1); | |
| 2068 __ block_comment(err_msg("move %d -> %d", i, c_arg)); | |
| 2069 if (c_arg == -1) { | |
| 2070 assert(is_critical_native, "should only be required for critical natives"); | |
| 2071 // This arg needs to be moved to a temporary | |
| 2072 __ mov(tmp_vmreg.first()->as_Register(), in_regs[i].first()->as_Register()); | |
| 2073 in_regs[i] = tmp_vmreg; | |
| 2074 temploc = i; | |
| 2075 continue; | |
| 2076 } else if (i == -1) { | |
| 2077 assert(is_critical_native, "should only be required for critical natives"); | |
| 2078 // Read from the temporary location | |
| 2079 assert(temploc != -1, "must be valid"); | |
| 2080 i = temploc; | |
| 2081 temploc = -1; | |
| 2082 } | |
| 0 | 2083 #ifdef ASSERT |
| 2084 if (in_regs[i].first()->is_Register()) { | |
| 2085 assert(!reg_destroyed[in_regs[i].first()->as_Register()->encoding()], "destroyed reg!"); | |
| 2086 } else if (in_regs[i].first()->is_XMMRegister()) { | |
| 2087 assert(!freg_destroyed[in_regs[i].first()->as_XMMRegister()->encoding()], "destroyed reg!"); | |
| 2088 } | |
| 2089 if (out_regs[c_arg].first()->is_Register()) { | |
| 2090 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true; | |
| 2091 } else if (out_regs[c_arg].first()->is_XMMRegister()) { | |
| 2092 freg_destroyed[out_regs[c_arg].first()->as_XMMRegister()->encoding()] = true; | |
| 2093 } | |
| 2094 #endif /* ASSERT */ | |
| 2095 switch (in_sig_bt[i]) { | |
| 2096 case T_ARRAY: | |
|
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2097 if (is_critical_native) { |
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2098 unpack_array_argument(masm, in_regs[i], in_elem_bt[i], out_regs[c_arg + 1], out_regs[c_arg]); |
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2099 c_arg++; |
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2100 #ifdef ASSERT |
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2101 if (out_regs[c_arg].first()->is_Register()) { |
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2102 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true; |
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2103 } else if (out_regs[c_arg].first()->is_XMMRegister()) { |
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2104 freg_destroyed[out_regs[c_arg].first()->as_XMMRegister()->encoding()] = true; |
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2105 } |
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2106 #endif |
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2107 break; |
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2108 } |
| 0 | 2109 case T_OBJECT: |
|
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2110 assert(!is_critical_native, "no oop arguments"); |
| 0 | 2111 object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg], |
| 2112 ((i == 0) && (!is_static)), | |
| 2113 &receiver_offset); | |
| 2114 break; | |
| 2115 case T_VOID: | |
| 2116 break; | |
| 2117 | |
| 2118 case T_FLOAT: | |
| 2119 float_move(masm, in_regs[i], out_regs[c_arg]); | |
| 2120 break; | |
| 2121 | |
| 2122 case T_DOUBLE: | |
| 2123 assert( i + 1 < total_in_args && | |
| 2124 in_sig_bt[i + 1] == T_VOID && | |
| 2125 out_sig_bt[c_arg+1] == T_VOID, "bad arg list"); | |
| 2126 double_move(masm, in_regs[i], out_regs[c_arg]); | |
| 2127 break; | |
| 2128 | |
| 2129 case T_LONG : | |
| 2130 long_move(masm, in_regs[i], out_regs[c_arg]); | |
| 2131 break; | |
| 2132 | |
| 2133 case T_ADDRESS: assert(false, "found T_ADDRESS in java args"); | |
| 2134 | |
| 2135 default: | |
| 2136 move32_64(masm, in_regs[i], out_regs[c_arg]); | |
| 2137 } | |
| 2138 } | |
| 2139 | |
| 2140 // point c_arg at the first arg that is already loaded in case we | |
| 2141 // need to spill before we call out | |
| 5905 | 2142 int c_arg = total_c_args - total_in_args; |
| 0 | 2143 |
| 2144 // Pre-load a static method's oop into r14. Used both by locking code and | |
| 2145 // the normal JNI call code. | |
|
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2146 if (method->is_static() && !is_critical_native) { |
| 0 | 2147 |
| 2148 // load oop into a register | |
| 2149 __ movoop(oop_handle_reg, JNIHandles::make_local(Klass::cast(method->method_holder())->java_mirror())); | |
| 2150 | |
| 2151 // Now handlize the static class mirror it's known not-null. | |
| 304 | 2152 __ movptr(Address(rsp, klass_offset), oop_handle_reg); |
| 0 | 2153 map->set_oop(VMRegImpl::stack2reg(klass_slot_offset)); |
| 2154 | |
| 2155 // Now get the handle | |
| 304 | 2156 __ lea(oop_handle_reg, Address(rsp, klass_offset)); |
| 0 | 2157 // store the klass handle as second argument |
| 304 | 2158 __ movptr(c_rarg1, oop_handle_reg); |
| 0 | 2159 // and protect the arg if we must spill |
| 2160 c_arg--; | |
| 2161 } | |
| 2162 | |
| 2163 // Change state to native (we save the return address in the thread, since it might not | |
| 2164 // be pushed on the stack when we do a a stack traversal). It is enough that the pc() | |
| 2165 // points into the right code segment. It does not have to be the correct return pc. | |
| 2166 // We use the same pc/oopMap repeatedly when we call out | |
| 2167 | |
| 2168 intptr_t the_pc = (intptr_t) __ pc(); | |
| 2169 oop_maps->add_gc_map(the_pc - start, map); | |
| 2170 | |
| 2171 __ set_last_Java_frame(rsp, noreg, (address)the_pc); | |
| 2172 | |
| 2173 | |
| 2174 // We have all of the arguments setup at this point. We must not touch any register | |
| 2175 // argument registers at this point (what if we save/restore them there are no oop? | |
| 2176 | |
| 2177 { | |
| 2178 SkipIfEqual skip(masm, &DTraceMethodProbes, false); | |
| 2179 // protect the args we've loaded | |
| 2180 save_args(masm, total_c_args, c_arg, out_regs); | |
|
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2181 __ mov_metadata(c_rarg1, method()); |
| 0 | 2182 __ call_VM_leaf( |
| 2183 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry), | |
| 2184 r15_thread, c_rarg1); | |
| 2185 restore_args(masm, total_c_args, c_arg, out_regs); | |
| 2186 } | |
| 2187 | |
|
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2188 // RedefineClasses() tracing support for obsolete method entry |
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2189 if (RC_TRACE_IN_RANGE(0x00001000, 0x00002000)) { |
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2190 // protect the args we've loaded |
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2191 save_args(masm, total_c_args, c_arg, out_regs); |
|
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2192 __ mov_metadata(c_rarg1, method()); |
|
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2193 __ call_VM_leaf( |
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2194 CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry), |
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2195 r15_thread, c_rarg1); |
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2196 restore_args(masm, total_c_args, c_arg, out_regs); |
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2197 } |
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2198 |
| 0 | 2199 // Lock a synchronized method |
| 2200 | |
| 2201 // Register definitions used by locking and unlocking | |
| 2202 | |
| 2203 const Register swap_reg = rax; // Must use rax for cmpxchg instruction | |
| 2204 const Register obj_reg = rbx; // Will contain the oop | |
| 2205 const Register lock_reg = r13; // Address of compiler lock object (BasicLock) | |
| 2206 const Register old_hdr = r13; // value of old header at unlock time | |
| 2207 | |
| 2208 Label slow_path_lock; | |
| 2209 Label lock_done; | |
| 2210 | |
| 2211 if (method->is_synchronized()) { | |
|
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2212 assert(!is_critical_native, "unhandled"); |
| 0 | 2213 |
| 2214 | |
| 2215 const int mark_word_offset = BasicLock::displaced_header_offset_in_bytes(); | |
| 2216 | |
| 2217 // Get the handle (the 2nd argument) | |
| 304 | 2218 __ mov(oop_handle_reg, c_rarg1); |
| 0 | 2219 |
| 2220 // Get address of the box | |
| 2221 | |
| 304 | 2222 __ lea(lock_reg, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size)); |
| 0 | 2223 |
| 2224 // Load the oop from the handle | |
| 304 | 2225 __ movptr(obj_reg, Address(oop_handle_reg, 0)); |
| 0 | 2226 |
| 2227 if (UseBiasedLocking) { | |
| 2228 __ biased_locking_enter(lock_reg, obj_reg, swap_reg, rscratch1, false, lock_done, &slow_path_lock); | |
| 2229 } | |
| 2230 | |
| 2231 // Load immediate 1 into swap_reg %rax | |
| 2232 __ movl(swap_reg, 1); | |
| 2233 | |
| 2234 // Load (object->mark() | 1) into swap_reg %rax | |
| 304 | 2235 __ orptr(swap_reg, Address(obj_reg, 0)); |
| 0 | 2236 |
| 2237 // Save (object->mark() | 1) into BasicLock's displaced header | |
| 304 | 2238 __ movptr(Address(lock_reg, mark_word_offset), swap_reg); |
| 0 | 2239 |
| 2240 if (os::is_MP()) { | |
| 2241 __ lock(); | |
| 2242 } | |
| 2243 | |
| 2244 // src -> dest iff dest == rax else rax <- dest | |
| 304 | 2245 __ cmpxchgptr(lock_reg, Address(obj_reg, 0)); |
| 0 | 2246 __ jcc(Assembler::equal, lock_done); |
| 2247 | |
| 2248 // Hmm should this move to the slow path code area??? | |
| 2249 | |
| 2250 // Test if the oopMark is an obvious stack pointer, i.e., | |
| 2251 // 1) (mark & 3) == 0, and | |
| 2252 // 2) rsp <= mark < mark + os::pagesize() | |
| 2253 // These 3 tests can be done by evaluating the following | |
| 2254 // expression: ((mark - rsp) & (3 - os::vm_page_size())), | |
| 2255 // assuming both stack pointer and pagesize have their | |
| 2256 // least significant 2 bits clear. | |
| 2257 // NOTE: the oopMark is in swap_reg %rax as the result of cmpxchg | |
| 2258 | |
| 304 | 2259 __ subptr(swap_reg, rsp); |
| 2260 __ andptr(swap_reg, 3 - os::vm_page_size()); | |
| 0 | 2261 |
| 2262 // Save the test result, for recursive case, the result is zero | |
| 304 | 2263 __ movptr(Address(lock_reg, mark_word_offset), swap_reg); |
| 0 | 2264 __ jcc(Assembler::notEqual, slow_path_lock); |
| 2265 | |
| 2266 // Slow path will re-enter here | |
| 2267 | |
| 2268 __ bind(lock_done); | |
| 2269 } | |
| 2270 | |
| 2271 | |
| 2272 // Finally just about ready to make the JNI call | |
| 2273 | |
| 2274 | |
| 2275 // get JNIEnv* which is first argument to native | |
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2276 if (!is_critical_native) { |
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2277 __ lea(c_rarg0, Address(r15_thread, in_bytes(JavaThread::jni_environment_offset()))); |
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2278 } |
| 0 | 2279 |
| 2280 // Now set thread in native | |
| 304 | 2281 __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_native); |
| 0 | 2282 |
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2283 __ call(RuntimeAddress(native_func)); |
| 0 | 2284 |
| 2285 // Either restore the MXCSR register after returning from the JNI Call | |
| 2286 // or verify that it wasn't changed. | |
| 2287 if (RestoreMXCSROnJNICalls) { | |
| 304 | 2288 __ ldmxcsr(ExternalAddress(StubRoutines::x86::mxcsr_std())); |
| 0 | 2289 |
| 2290 } | |
| 2291 else if (CheckJNICalls ) { | |
| 304 | 2292 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::verify_mxcsr_entry()))); |
| 0 | 2293 } |
| 2294 | |
| 2295 | |
| 2296 // Unpack native results. | |
| 2297 switch (ret_type) { | |
| 2298 case T_BOOLEAN: __ c2bool(rax); break; | |
| 2299 case T_CHAR : __ movzwl(rax, rax); break; | |
| 2300 case T_BYTE : __ sign_extend_byte (rax); break; | |
| 2301 case T_SHORT : __ sign_extend_short(rax); break; | |
| 2302 case T_INT : /* nothing to do */ break; | |
| 2303 case T_DOUBLE : | |
| 2304 case T_FLOAT : | |
| 2305 // Result is in xmm0 we'll save as needed | |
| 2306 break; | |
| 2307 case T_ARRAY: // Really a handle | |
| 2308 case T_OBJECT: // Really a handle | |
| 2309 break; // can't de-handlize until after safepoint check | |
| 2310 case T_VOID: break; | |
| 2311 case T_LONG: break; | |
| 2312 default : ShouldNotReachHere(); | |
| 2313 } | |
| 2314 | |
| 2315 // Switch thread to "native transition" state before reading the synchronization state. | |
| 2316 // This additional state is necessary because reading and testing the synchronization | |
| 2317 // state is not atomic w.r.t. GC, as this scenario demonstrates: | |
| 2318 // Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted. | |
| 2319 // VM thread changes sync state to synchronizing and suspends threads for GC. | |
| 2320 // Thread A is resumed to finish this native method, but doesn't block here since it | |
| 2321 // didn't see any synchronization is progress, and escapes. | |
| 304 | 2322 __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_native_trans); |
| 0 | 2323 |
| 2324 if(os::is_MP()) { | |
| 2325 if (UseMembar) { | |
| 2326 // Force this write out before the read below | |
| 2327 __ membar(Assembler::Membar_mask_bits( | |
| 2328 Assembler::LoadLoad | Assembler::LoadStore | | |
| 2329 Assembler::StoreLoad | Assembler::StoreStore)); | |
| 2330 } else { | |
| 2331 // Write serialization page so VM thread can do a pseudo remote membar. | |
| 2332 // We use the current thread pointer to calculate a thread specific | |
| 2333 // offset to write to within the page. This minimizes bus traffic | |
| 2334 // due to cache line collision. | |
| 2335 __ serialize_memory(r15_thread, rcx); | |
| 2336 } | |
| 2337 } | |
| 2338 | |
|
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2339 Label after_transition; |
| 0 | 2340 |
| 2341 // check for safepoint operation in progress and/or pending suspend requests | |
| 2342 { | |
| 2343 Label Continue; | |
| 2344 | |
| 2345 __ cmp32(ExternalAddress((address)SafepointSynchronize::address_of_state()), | |
| 2346 SafepointSynchronize::_not_synchronized); | |
| 2347 | |
| 2348 Label L; | |
| 2349 __ jcc(Assembler::notEqual, L); | |
| 2350 __ cmpl(Address(r15_thread, JavaThread::suspend_flags_offset()), 0); | |
| 2351 __ jcc(Assembler::equal, Continue); | |
| 2352 __ bind(L); | |
| 2353 | |
| 2354 // Don't use call_VM as it will see a possible pending exception and forward it | |
| 2355 // and never return here preventing us from clearing _last_native_pc down below. | |
| 2356 // Also can't use call_VM_leaf either as it will check to see if rsi & rdi are | |
| 2357 // preserved and correspond to the bcp/locals pointers. So we do a runtime call | |
| 2358 // by hand. | |
| 2359 // | |
| 2360 save_native_result(masm, ret_type, stack_slots); | |
| 304 | 2361 __ mov(c_rarg0, r15_thread); |
| 2362 __ mov(r12, rsp); // remember sp | |
| 2363 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows | |
| 2364 __ andptr(rsp, -16); // align stack as required by ABI | |
|
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2365 if (!is_critical_native) { |
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2366 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans))); |
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2367 } else { |
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2368 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans_and_transition))); |
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2369 } |
| 304 | 2370 __ mov(rsp, r12); // restore sp |
|
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2371 __ reinit_heapbase(); |
| 0 | 2372 // Restore any method result value |
| 2373 restore_native_result(masm, ret_type, stack_slots); | |
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2374 |
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2375 if (is_critical_native) { |
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2376 // The call above performed the transition to thread_in_Java so |
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2377 // skip the transition logic below. |
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2378 __ jmpb(after_transition); |
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2379 } |
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2380 |
| 0 | 2381 __ bind(Continue); |
| 2382 } | |
| 2383 | |
| 2384 // change thread state | |
| 2385 __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_Java); | |
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2386 __ bind(after_transition); |
| 0 | 2387 |
| 2388 Label reguard; | |
| 2389 Label reguard_done; | |
| 2390 __ cmpl(Address(r15_thread, JavaThread::stack_guard_state_offset()), JavaThread::stack_guard_yellow_disabled); | |
| 2391 __ jcc(Assembler::equal, reguard); | |
| 2392 __ bind(reguard_done); | |
| 2393 | |
| 2394 // native result if any is live | |
| 2395 | |
| 2396 // Unlock | |
| 2397 Label unlock_done; | |
| 2398 Label slow_path_unlock; | |
| 2399 if (method->is_synchronized()) { | |
| 2400 | |
| 2401 // Get locked oop from the handle we passed to jni | |
| 304 | 2402 __ movptr(obj_reg, Address(oop_handle_reg, 0)); |
| 0 | 2403 |
| 2404 Label done; | |
| 2405 | |
| 2406 if (UseBiasedLocking) { | |
| 2407 __ biased_locking_exit(obj_reg, old_hdr, done); | |
| 2408 } | |
| 2409 | |
| 2410 // Simple recursive lock? | |
| 2411 | |
| 304 | 2412 __ cmpptr(Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size), (int32_t)NULL_WORD); |
| 0 | 2413 __ jcc(Assembler::equal, done); |
| 2414 | |
| 2415 // Must save rax if if it is live now because cmpxchg must use it | |
| 2416 if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) { | |
| 2417 save_native_result(masm, ret_type, stack_slots); | |
| 2418 } | |
| 2419 | |
| 2420 | |
| 2421 // get address of the stack lock | |
| 304 | 2422 __ lea(rax, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size)); |
| 0 | 2423 // get old displaced header |
| 304 | 2424 __ movptr(old_hdr, Address(rax, 0)); |
| 0 | 2425 |
| 2426 // Atomic swap old header if oop still contains the stack lock | |
| 2427 if (os::is_MP()) { | |
| 2428 __ lock(); | |
| 2429 } | |
| 304 | 2430 __ cmpxchgptr(old_hdr, Address(obj_reg, 0)); |
| 0 | 2431 __ jcc(Assembler::notEqual, slow_path_unlock); |
| 2432 | |
| 2433 // slow path re-enters here | |
| 2434 __ bind(unlock_done); | |
| 2435 if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) { | |
| 2436 restore_native_result(masm, ret_type, stack_slots); | |
| 2437 } | |
| 2438 | |
| 2439 __ bind(done); | |
| 2440 | |
| 2441 } | |
| 2442 { | |
| 2443 SkipIfEqual skip(masm, &DTraceMethodProbes, false); | |
| 2444 save_native_result(masm, ret_type, stack_slots); | |
|
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2445 __ mov_metadata(c_rarg1, method()); |
| 0 | 2446 __ call_VM_leaf( |
| 2447 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), | |
| 2448 r15_thread, c_rarg1); | |
| 2449 restore_native_result(masm, ret_type, stack_slots); | |
| 2450 } | |
| 2451 | |
| 2452 __ reset_last_Java_frame(false, true); | |
| 2453 | |
| 2454 // Unpack oop result | |
| 2455 if (ret_type == T_OBJECT || ret_type == T_ARRAY) { | |
| 2456 Label L; | |
| 304 | 2457 __ testptr(rax, rax); |
| 0 | 2458 __ jcc(Assembler::zero, L); |
| 304 | 2459 __ movptr(rax, Address(rax, 0)); |
| 0 | 2460 __ bind(L); |
| 2461 __ verify_oop(rax); | |
| 2462 } | |
| 2463 | |
|
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2464 if (!is_critical_native) { |
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2465 // reset handle block |
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2466 __ movptr(rcx, Address(r15_thread, JavaThread::active_handles_offset())); |
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2467 __ movptr(Address(rcx, JNIHandleBlock::top_offset_in_bytes()), (int32_t)NULL_WORD); |
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2468 } |
| 0 | 2469 |
| 2470 // pop our frame | |
| 2471 | |
| 2472 __ leave(); | |
| 2473 | |
|
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2474 if (!is_critical_native) { |
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2475 // Any exception pending? |
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2476 __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD); |
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2477 __ jcc(Assembler::notEqual, exception_pending); |
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2478 } |
| 0 | 2479 |
| 2480 // Return | |
| 2481 | |
| 2482 __ ret(0); | |
| 2483 | |
| 2484 // Unexpected paths are out of line and go here | |
| 2485 | |
|
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2486 if (!is_critical_native) { |
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2487 // forward the exception |
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2488 __ bind(exception_pending); |
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2489 |
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2490 // and forward the exception |
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2491 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry())); |
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2492 } |
| 0 | 2493 |
| 2494 // Slow path locking & unlocking | |
| 2495 if (method->is_synchronized()) { | |
| 2496 | |
| 2497 // BEGIN Slow path lock | |
| 2498 __ bind(slow_path_lock); | |
| 2499 | |
| 2500 // has last_Java_frame setup. No exceptions so do vanilla call not call_VM | |
| 2501 // args are (oop obj, BasicLock* lock, JavaThread* thread) | |
| 2502 | |
| 2503 // protect the args we've loaded | |
| 2504 save_args(masm, total_c_args, c_arg, out_regs); | |
| 2505 | |
| 304 | 2506 __ mov(c_rarg0, obj_reg); |
| 2507 __ mov(c_rarg1, lock_reg); | |
| 2508 __ mov(c_rarg2, r15_thread); | |
| 0 | 2509 |
| 2510 // Not a leaf but we have last_Java_frame setup as we want | |
| 2511 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C), 3); | |
| 2512 restore_args(masm, total_c_args, c_arg, out_regs); | |
| 2513 | |
| 2514 #ifdef ASSERT | |
| 2515 { Label L; | |
| 304 | 2516 __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD); |
| 0 | 2517 __ jcc(Assembler::equal, L); |
| 2518 __ stop("no pending exception allowed on exit from monitorenter"); | |
| 2519 __ bind(L); | |
| 2520 } | |
| 2521 #endif | |
| 2522 __ jmp(lock_done); | |
| 2523 | |
| 2524 // END Slow path lock | |
| 2525 | |
| 2526 // BEGIN Slow path unlock | |
| 2527 __ bind(slow_path_unlock); | |
| 2528 | |
| 2529 // If we haven't already saved the native result we must save it now as xmm registers | |
| 2530 // are still exposed. | |
| 2531 | |
| 2532 if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) { | |
| 2533 save_native_result(masm, ret_type, stack_slots); | |
| 2534 } | |
| 2535 | |
| 304 | 2536 __ lea(c_rarg1, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size)); |
| 2537 | |
| 2538 __ mov(c_rarg0, obj_reg); | |
| 2539 __ mov(r12, rsp); // remember sp | |
| 2540 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows | |
| 2541 __ andptr(rsp, -16); // align stack as required by ABI | |
| 0 | 2542 |
| 2543 // Save pending exception around call to VM (which contains an EXCEPTION_MARK) | |
| 2544 // NOTE that obj_reg == rbx currently | |
| 304 | 2545 __ movptr(rbx, Address(r15_thread, in_bytes(Thread::pending_exception_offset()))); |
| 2546 __ movptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD); | |
| 0 | 2547 |
| 2548 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C))); | |
| 304 | 2549 __ mov(rsp, r12); // restore sp |
|
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2550 __ reinit_heapbase(); |
| 0 | 2551 #ifdef ASSERT |
| 2552 { | |
| 2553 Label L; | |
| 304 | 2554 __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int)NULL_WORD); |
| 0 | 2555 __ jcc(Assembler::equal, L); |
| 2556 __ stop("no pending exception allowed on exit complete_monitor_unlocking_C"); | |
| 2557 __ bind(L); | |
| 2558 } | |
| 2559 #endif /* ASSERT */ | |
| 2560 | |
| 304 | 2561 __ movptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), rbx); |
| 0 | 2562 |
| 2563 if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) { | |
| 2564 restore_native_result(masm, ret_type, stack_slots); | |
| 2565 } | |
| 2566 __ jmp(unlock_done); | |
| 2567 | |
| 2568 // END Slow path unlock | |
| 2569 | |
| 2570 } // synchronized | |
| 2571 | |
| 2572 // SLOW PATH Reguard the stack if needed | |
| 2573 | |
| 2574 __ bind(reguard); | |
| 2575 save_native_result(masm, ret_type, stack_slots); | |
| 304 | 2576 __ mov(r12, rsp); // remember sp |
| 2577 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows | |
| 2578 __ andptr(rsp, -16); // align stack as required by ABI | |
| 0 | 2579 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages))); |
| 304 | 2580 __ mov(rsp, r12); // restore sp |
|
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2581 __ reinit_heapbase(); |
| 0 | 2582 restore_native_result(masm, ret_type, stack_slots); |
| 2583 // and continue | |
| 2584 __ jmp(reguard_done); | |
| 2585 | |
| 2586 | |
| 2587 | |
| 2588 __ flush(); | |
| 2589 | |
| 2590 nmethod *nm = nmethod::new_native_nmethod(method, | |
|
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2591 compile_id, |
| 0 | 2592 masm->code(), |
| 2593 vep_offset, | |
| 2594 frame_complete, | |
| 2595 stack_slots / VMRegImpl::slots_per_word, | |
| 2596 (is_static ? in_ByteSize(klass_offset) : in_ByteSize(receiver_offset)), | |
| 2597 in_ByteSize(lock_slot_offset*VMRegImpl::stack_slot_size), | |
| 2598 oop_maps); | |
|
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2599 |
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2600 if (is_critical_native) { |
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|
2601 nm->set_lazy_critical_native(true); |
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2602 } |
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2603 |
| 0 | 2604 return nm; |
| 2605 | |
| 2606 } | |
| 2607 | |
|
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2608 #ifdef HAVE_DTRACE_H |
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2609 // --------------------------------------------------------------------------- |
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2610 // Generate a dtrace nmethod for a given signature. The method takes arguments |
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2611 // in the Java compiled code convention, marshals them to the native |
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2612 // abi and then leaves nops at the position you would expect to call a native |
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2613 // function. When the probe is enabled the nops are replaced with a trap |
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2614 // instruction that dtrace inserts and the trace will cause a notification |
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2615 // to dtrace. |
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2616 // |
|
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2617 // The probes are only able to take primitive types and java/lang/String as |
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2618 // arguments. No other java types are allowed. Strings are converted to utf8 |
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2619 // strings so that from dtrace point of view java strings are converted to C |
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2620 // strings. There is an arbitrary fixed limit on the total space that a method |
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2621 // can use for converting the strings. (256 chars per string in the signature). |
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2622 // So any java string larger then this is truncated. |
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2623 |
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2624 static int fp_offset[ConcreteRegisterImpl::number_of_registers] = { 0 }; |
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2625 static bool offsets_initialized = false; |
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2626 |
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2627 |
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2628 nmethod *SharedRuntime::generate_dtrace_nmethod(MacroAssembler *masm, |
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2629 methodHandle method) { |
|
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2630 |
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2631 |
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2632 // generate_dtrace_nmethod is guarded by a mutex so we are sure to |
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2633 // be single threaded in this method. |
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2634 assert(AdapterHandlerLibrary_lock->owned_by_self(), "must be"); |
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2635 |
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2636 if (!offsets_initialized) { |
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2637 fp_offset[c_rarg0->as_VMReg()->value()] = -1 * wordSize; |
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2638 fp_offset[c_rarg1->as_VMReg()->value()] = -2 * wordSize; |
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2639 fp_offset[c_rarg2->as_VMReg()->value()] = -3 * wordSize; |
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2640 fp_offset[c_rarg3->as_VMReg()->value()] = -4 * wordSize; |
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2641 fp_offset[c_rarg4->as_VMReg()->value()] = -5 * wordSize; |
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2642 fp_offset[c_rarg5->as_VMReg()->value()] = -6 * wordSize; |
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2643 |
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2644 fp_offset[c_farg0->as_VMReg()->value()] = -7 * wordSize; |
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2645 fp_offset[c_farg1->as_VMReg()->value()] = -8 * wordSize; |
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2646 fp_offset[c_farg2->as_VMReg()->value()] = -9 * wordSize; |
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2647 fp_offset[c_farg3->as_VMReg()->value()] = -10 * wordSize; |
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2648 fp_offset[c_farg4->as_VMReg()->value()] = -11 * wordSize; |
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2649 fp_offset[c_farg5->as_VMReg()->value()] = -12 * wordSize; |
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2650 fp_offset[c_farg6->as_VMReg()->value()] = -13 * wordSize; |
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2651 fp_offset[c_farg7->as_VMReg()->value()] = -14 * wordSize; |
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2652 |
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2653 offsets_initialized = true; |
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2654 } |
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2655 // Fill in the signature array, for the calling-convention call. |
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2656 int total_args_passed = method->size_of_parameters(); |
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2657 |
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2658 BasicType* in_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed); |
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2659 VMRegPair *in_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed); |
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2660 |
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2661 // The signature we are going to use for the trap that dtrace will see |
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2662 // java/lang/String is converted. We drop "this" and any other object |
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2663 // is converted to NULL. (A one-slot java/lang/Long object reference |
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2664 // is converted to a two-slot long, which is why we double the allocation). |
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2665 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed * 2); |
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2666 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed * 2); |
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2667 |
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2668 int i=0; |
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2669 int total_strings = 0; |
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2670 int first_arg_to_pass = 0; |
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2671 int total_c_args = 0; |
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2672 |
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2673 // Skip the receiver as dtrace doesn't want to see it |
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2674 if( !method->is_static() ) { |
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2675 in_sig_bt[i++] = T_OBJECT; |
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2676 first_arg_to_pass = 1; |
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2677 } |
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2678 |
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2679 // We need to convert the java args to where a native (non-jni) function |
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2680 // would expect them. To figure out where they go we convert the java |
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2681 // signature to a C signature. |
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2682 |
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2683 SignatureStream ss(method->signature()); |
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2684 for ( ; !ss.at_return_type(); ss.next()) { |
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2685 BasicType bt = ss.type(); |
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2686 in_sig_bt[i++] = bt; // Collect remaining bits of signature |
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2687 out_sig_bt[total_c_args++] = bt; |
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2688 if( bt == T_OBJECT) { |
|
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2689 Symbol* s = ss.as_symbol_or_null(); // symbol is created |
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2690 if (s == vmSymbols::java_lang_String()) { |
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2691 total_strings++; |
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2692 out_sig_bt[total_c_args-1] = T_ADDRESS; |
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2693 } else if (s == vmSymbols::java_lang_Boolean() || |
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2694 s == vmSymbols::java_lang_Character() || |
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2695 s == vmSymbols::java_lang_Byte() || |
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2696 s == vmSymbols::java_lang_Short() || |
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2697 s == vmSymbols::java_lang_Integer() || |
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2698 s == vmSymbols::java_lang_Float()) { |
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2699 out_sig_bt[total_c_args-1] = T_INT; |
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2700 } else if (s == vmSymbols::java_lang_Long() || |
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2701 s == vmSymbols::java_lang_Double()) { |
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2702 out_sig_bt[total_c_args-1] = T_LONG; |
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2703 out_sig_bt[total_c_args++] = T_VOID; |
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2704 } |
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2705 } else if ( bt == T_LONG || bt == T_DOUBLE ) { |
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2706 in_sig_bt[i++] = T_VOID; // Longs & doubles take 2 Java slots |
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2707 // We convert double to long |
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2708 out_sig_bt[total_c_args-1] = T_LONG; |
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2709 out_sig_bt[total_c_args++] = T_VOID; |
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2710 } else if ( bt == T_FLOAT) { |
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2711 // We convert float to int |
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2712 out_sig_bt[total_c_args-1] = T_INT; |
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2713 } |
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2714 } |
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2715 |
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2716 assert(i==total_args_passed, "validly parsed signature"); |
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2717 |
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2718 // Now get the compiled-Java layout as input arguments |
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2719 int comp_args_on_stack; |
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2720 comp_args_on_stack = SharedRuntime::java_calling_convention( |
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2721 in_sig_bt, in_regs, total_args_passed, false); |
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2722 |
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2723 // Now figure out where the args must be stored and how much stack space |
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2724 // they require (neglecting out_preserve_stack_slots but space for storing |
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2725 // the 1st six register arguments). It's weird see int_stk_helper. |
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2726 |
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2727 int out_arg_slots; |
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2728 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args); |
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2729 |
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2730 // Calculate the total number of stack slots we will need. |
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2731 |
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2732 // First count the abi requirement plus all of the outgoing args |
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2733 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots; |
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2734 |
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2735 // Now space for the string(s) we must convert |
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2736 int* string_locs = NEW_RESOURCE_ARRAY(int, total_strings + 1); |
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2737 for (i = 0; i < total_strings ; i++) { |
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2738 string_locs[i] = stack_slots; |
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2739 stack_slots += max_dtrace_string_size / VMRegImpl::stack_slot_size; |
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2740 } |
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2741 |
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2742 // Plus the temps we might need to juggle register args |
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2743 // regs take two slots each |
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2744 stack_slots += (Argument::n_int_register_parameters_c + |
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2745 Argument::n_float_register_parameters_c) * 2; |
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2746 |
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2747 |
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2748 // + 4 for return address (which we own) and saved rbp, |
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2749 |
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2750 stack_slots += 4; |
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2751 |
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2752 // Ok The space we have allocated will look like: |
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2753 // |
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2754 // |
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2755 // FP-> | | |
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2756 // |---------------------| |
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2757 // | string[n] | |
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2758 // |---------------------| <- string_locs[n] |
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2759 // | string[n-1] | |
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2760 // |---------------------| <- string_locs[n-1] |
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2761 // | ... | |
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2762 // | ... | |
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2763 // |---------------------| <- string_locs[1] |
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2764 // | string[0] | |
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2765 // |---------------------| <- string_locs[0] |
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2766 // | outbound memory | |
|
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2767 // | based arguments | |
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2768 // | | |
|
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2769 // |---------------------| |
|
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2770 // | | |
|
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2771 // SP-> | out_preserved_slots | |
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2772 // |
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2773 // |
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2774 |
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2775 // Now compute actual number of stack words we need rounding to make |
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2776 // stack properly aligned. |
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2777 stack_slots = round_to(stack_slots, 4 * VMRegImpl::slots_per_word); |
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2778 |
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2779 int stack_size = stack_slots * VMRegImpl::stack_slot_size; |
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2780 |
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2781 intptr_t start = (intptr_t)__ pc(); |
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2782 |
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2783 // First thing make an ic check to see if we should even be here |
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2784 |
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2785 // We are free to use all registers as temps without saving them and |
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2786 // restoring them except rbp. rbp, is the only callee save register |
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2787 // as far as the interpreter and the compiler(s) are concerned. |
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2788 |
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2789 const Register ic_reg = rax; |
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2790 const Register receiver = rcx; |
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2791 Label hit; |
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2792 Label exception_pending; |
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2793 |
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2794 |
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2795 __ verify_oop(receiver); |
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2796 __ cmpl(ic_reg, Address(receiver, oopDesc::klass_offset_in_bytes())); |
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2797 __ jcc(Assembler::equal, hit); |
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2798 |
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2799 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub())); |
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2800 |
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2801 // verified entry must be aligned for code patching. |
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2802 // and the first 5 bytes must be in the same cache line |
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2803 // if we align at 8 then we will be sure 5 bytes are in the same line |
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2804 __ align(8); |
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2805 |
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2806 __ bind(hit); |
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2807 |
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2808 int vep_offset = ((intptr_t)__ pc()) - start; |
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2809 |
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2810 |
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2811 // The instruction at the verified entry point must be 5 bytes or longer |
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2812 // because it can be patched on the fly by make_non_entrant. The stack bang |
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2813 // instruction fits that requirement. |
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2814 |
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2815 // Generate stack overflow check |
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2816 |
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2817 if (UseStackBanging) { |
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2818 if (stack_size <= StackShadowPages*os::vm_page_size()) { |
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2819 __ bang_stack_with_offset(StackShadowPages*os::vm_page_size()); |
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2820 } else { |
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2821 __ movl(rax, stack_size); |
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2822 __ bang_stack_size(rax, rbx); |
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2823 } |
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2824 } else { |
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2825 // need a 5 byte instruction to allow MT safe patching to non-entrant |
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2826 __ fat_nop(); |
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2827 } |
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2828 |
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2829 assert(((uintptr_t)__ pc() - start - vep_offset) >= 5, |
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2830 "valid size for make_non_entrant"); |
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2831 |
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2832 // Generate a new frame for the wrapper. |
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2833 __ enter(); |
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2834 |
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2835 // -4 because return address is already present and so is saved rbp, |
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2836 if (stack_size - 2*wordSize != 0) { |
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2837 __ subq(rsp, stack_size - 2*wordSize); |
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2838 } |
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2839 |
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2840 // Frame is now completed as far a size and linkage. |
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2841 |
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2842 int frame_complete = ((intptr_t)__ pc()) - start; |
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2843 |
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2844 int c_arg, j_arg; |
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2845 |
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2846 // State of input register args |
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2847 |
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2848 bool live[ConcreteRegisterImpl::number_of_registers]; |
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2849 |
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2850 live[j_rarg0->as_VMReg()->value()] = false; |
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2851 live[j_rarg1->as_VMReg()->value()] = false; |
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2852 live[j_rarg2->as_VMReg()->value()] = false; |
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2853 live[j_rarg3->as_VMReg()->value()] = false; |
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2854 live[j_rarg4->as_VMReg()->value()] = false; |
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2855 live[j_rarg5->as_VMReg()->value()] = false; |
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2856 |
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2857 live[j_farg0->as_VMReg()->value()] = false; |
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2858 live[j_farg1->as_VMReg()->value()] = false; |
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2859 live[j_farg2->as_VMReg()->value()] = false; |
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2860 live[j_farg3->as_VMReg()->value()] = false; |
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2861 live[j_farg4->as_VMReg()->value()] = false; |
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2862 live[j_farg5->as_VMReg()->value()] = false; |
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2863 live[j_farg6->as_VMReg()->value()] = false; |
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2864 live[j_farg7->as_VMReg()->value()] = false; |
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2865 |
|
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2866 |
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2867 bool rax_is_zero = false; |
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2868 |
|
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2869 // All args (except strings) destined for the stack are moved first |
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2870 for (j_arg = first_arg_to_pass, c_arg = 0 ; |
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2871 j_arg < total_args_passed ; j_arg++, c_arg++ ) { |
|
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2872 VMRegPair src = in_regs[j_arg]; |
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2873 VMRegPair dst = out_regs[c_arg]; |
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2874 |
|
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2875 // Get the real reg value or a dummy (rsp) |
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2876 |
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2877 int src_reg = src.first()->is_reg() ? |
|
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2878 src.first()->value() : |
|
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2879 rsp->as_VMReg()->value(); |
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2880 |
|
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2881 bool useless = in_sig_bt[j_arg] == T_ARRAY || |
|
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2882 (in_sig_bt[j_arg] == T_OBJECT && |
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2883 out_sig_bt[c_arg] != T_INT && |
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2884 out_sig_bt[c_arg] != T_ADDRESS && |
|
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2885 out_sig_bt[c_arg] != T_LONG); |
|
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6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2886 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
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113
diff
changeset
|
2887 live[src_reg] = !useless; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2888 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2889 if (dst.first()->is_stack()) { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
2890 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2891 // Even though a string arg in a register is still live after this loop |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
2892 // after the string conversion loop (next) it will be dead so we take |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2893 // advantage of that now for simpler code to manage live. |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2894 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2895 live[src_reg] = false; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
2896 switch (in_sig_bt[j_arg]) { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
2897 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2898 case T_ARRAY: |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
2899 case T_OBJECT: |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
2900 { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2901 Address stack_dst(rsp, reg2offset_out(dst.first())); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2902 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2903 if (out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2904 // need to unbox a one-word value |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
2905 Register in_reg = rax; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2906 if ( src.first()->is_reg() ) { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2907 in_reg = src.first()->as_Register(); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
2908 } else { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2909 __ movq(rax, Address(rbp, reg2offset_in(src.first()))); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
2910 rax_is_zero = false; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2911 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2912 Label skipUnbox; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2913 __ movptr(Address(rsp, reg2offset_out(dst.first())), |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
2914 (int32_t)NULL_WORD); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
2915 __ testq(in_reg, in_reg); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
2916 __ jcc(Assembler::zero, skipUnbox); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2917 |
|
165
437d03ea40b1
6703888: Compressed Oops: use the 32-bits gap after klass in a object
kvn
parents:
116
diff
changeset
|
2918 BasicType bt = out_sig_bt[c_arg]; |
|
437d03ea40b1
6703888: Compressed Oops: use the 32-bits gap after klass in a object
kvn
parents:
116
diff
changeset
|
2919 int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt); |
|
116
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2920 Address src1(in_reg, box_offset); |
|
165
437d03ea40b1
6703888: Compressed Oops: use the 32-bits gap after klass in a object
kvn
parents:
116
diff
changeset
|
2921 if ( bt == T_LONG ) { |
|
116
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
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|
2922 __ movq(in_reg, src1); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2923 __ movq(stack_dst, in_reg); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2924 assert(out_sig_bt[c_arg+1] == T_VOID, "must be"); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2925 ++c_arg; // skip over T_VOID to keep the loop indices in sync |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2926 } else { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2927 __ movl(in_reg, src1); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2928 __ movl(stack_dst, in_reg); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2929 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2930 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2931 __ bind(skipUnbox); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2932 } else if (out_sig_bt[c_arg] != T_ADDRESS) { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2933 // Convert the arg to NULL |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2934 if (!rax_is_zero) { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2935 __ xorq(rax, rax); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2936 rax_is_zero = true; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2937 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2938 __ movq(stack_dst, rax); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2939 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2940 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2941 break; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2942 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2943 case T_VOID: |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2944 break; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2945 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2946 case T_FLOAT: |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2947 // This does the right thing since we know it is destined for the |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2948 // stack |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2949 float_move(masm, src, dst); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2950 break; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2951 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2952 case T_DOUBLE: |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2953 // This does the right thing since we know it is destined for the |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2954 // stack |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2955 double_move(masm, src, dst); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2956 break; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2957 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2958 case T_LONG : |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2959 long_move(masm, src, dst); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2960 break; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2961 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2962 case T_ADDRESS: assert(false, "found T_ADDRESS in java args"); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2963 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2964 default: |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2965 move32_64(masm, src, dst); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2966 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2967 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2968 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2969 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2970 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2971 // If we have any strings we must store any register based arg to the stack |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2972 // This includes any still live xmm registers too. |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2973 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2974 int sid = 0; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2975 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2976 if (total_strings > 0 ) { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2977 for (j_arg = first_arg_to_pass, c_arg = 0 ; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2978 j_arg < total_args_passed ; j_arg++, c_arg++ ) { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2979 VMRegPair src = in_regs[j_arg]; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2980 VMRegPair dst = out_regs[c_arg]; |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2981 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2982 if (src.first()->is_reg()) { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2983 Address src_tmp(rbp, fp_offset[src.first()->value()]); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2984 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2985 // string oops were left untouched by the previous loop even if the |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2986 // eventual (converted) arg is destined for the stack so park them |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2987 // away now (except for first) |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2988 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2989 if (out_sig_bt[c_arg] == T_ADDRESS) { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2990 Address utf8_addr = Address( |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2991 rsp, string_locs[sid++] * VMRegImpl::stack_slot_size); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2992 if (sid != 1) { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2993 // The first string arg won't be killed until after the utf8 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2994 // conversion |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2995 __ movq(utf8_addr, src.first()->as_Register()); |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2996 } |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2997 } else if (dst.first()->is_reg()) { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2998 if (in_sig_bt[j_arg] == T_FLOAT || in_sig_bt[j_arg] == T_DOUBLE) { |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
2999 |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3000 // Convert the xmm register to an int and store it in the reserved |
|
018d5b58dd4f
6537506: Provide a mechanism for specifying Java-level USDT-like dtrace probes
kamg
parents:
113
diff
changeset
|
3001 // location for the eventual c register arg |
|
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3002 XMMRegister f = src.first()->as_XMMRegister(); |
|
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3003 if (in_sig_bt[j_arg] == T_FLOAT) { |
|
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3004 __ movflt(src_tmp, f); |
|
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3005 } else { |
|
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3006 __ movdbl(src_tmp, f); |
|
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|
3007 } |
|
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|
3008 } else { |
|
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3009 // If the arg is an oop type we don't support don't bother to store |
|
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3010 // it remember string was handled above. |
|
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3011 bool useless = in_sig_bt[j_arg] == T_ARRAY || |
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3012 (in_sig_bt[j_arg] == T_OBJECT && |
|
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3013 out_sig_bt[c_arg] != T_INT && |
|
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3014 out_sig_bt[c_arg] != T_LONG); |
|
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3015 |
|
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3016 if (!useless) { |
|
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3017 __ movq(src_tmp, src.first()->as_Register()); |
|
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3018 } |
|
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|
3019 } |
|
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|
3020 } |
|
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|
3021 } |
|
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3022 if (in_sig_bt[j_arg] == T_OBJECT && out_sig_bt[c_arg] == T_LONG) { |
|
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3023 assert(out_sig_bt[c_arg+1] == T_VOID, "must be"); |
|
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3024 ++c_arg; // skip over T_VOID to keep the loop indices in sync |
|
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3025 } |
|
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|
3026 } |
|
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|
3027 |
|
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|
3028 // Now that the volatile registers are safe, convert all the strings |
|
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3029 sid = 0; |
|
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3030 |
|
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3031 for (j_arg = first_arg_to_pass, c_arg = 0 ; |
|
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3032 j_arg < total_args_passed ; j_arg++, c_arg++ ) { |
|
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3033 if (out_sig_bt[c_arg] == T_ADDRESS) { |
|
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3034 // It's a string |
|
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3035 Address utf8_addr = Address( |
|
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|
3036 rsp, string_locs[sid++] * VMRegImpl::stack_slot_size); |
|
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3037 // The first string we find might still be in the original java arg |
|
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3038 // register |
|
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|
3039 |
|
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|
3040 VMReg src = in_regs[j_arg].first(); |
|
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|
3041 |
|
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|
3042 // We will need to eventually save the final argument to the trap |
|
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3043 // in the von-volatile location dedicated to src. This is the offset |
|
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3044 // from fp we will use. |
|
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3045 int src_off = src->is_reg() ? |
|
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3046 fp_offset[src->value()] : reg2offset_in(src); |
|
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3047 |
|
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|
3048 // This is where the argument will eventually reside |
|
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3049 VMRegPair dst = out_regs[c_arg]; |
|
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|
3050 |
|
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|
3051 if (src->is_reg()) { |
|
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|
3052 if (sid == 1) { |
|
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|
3053 __ movq(c_rarg0, src->as_Register()); |
|
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|
3054 } else { |
|
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|
3055 __ movq(c_rarg0, utf8_addr); |
|
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|
3056 } |
|
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|
3057 } else { |
|
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|
3058 // arg is still in the original location |
|
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|
3059 __ movq(c_rarg0, Address(rbp, reg2offset_in(src))); |
|
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|
3060 } |
|
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|
3061 Label done, convert; |
|
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|
3062 |
|
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|
3063 // see if the oop is NULL |
|
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|
3064 __ testq(c_rarg0, c_rarg0); |
|
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|
3065 __ jcc(Assembler::notEqual, convert); |
|
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|
3066 |
|
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|
3067 if (dst.first()->is_reg()) { |
|
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|
3068 // Save the ptr to utf string in the origina src loc or the tmp |
|
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|
3069 // dedicated to it |
|
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|
3070 __ movq(Address(rbp, src_off), c_rarg0); |
|
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|
3071 } else { |
|
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|
3072 __ movq(Address(rsp, reg2offset_out(dst.first())), c_rarg0); |
|
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|
3073 } |
|
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|
3074 __ jmp(done); |
|
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|
3075 |
|
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|
3076 __ bind(convert); |
|
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|
3077 |
|
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|
3078 __ lea(c_rarg1, utf8_addr); |
|
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|
3079 if (dst.first()->is_reg()) { |
|
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|
3080 __ movq(Address(rbp, src_off), c_rarg1); |
|
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|
3081 } else { |
|
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|
3082 __ movq(Address(rsp, reg2offset_out(dst.first())), c_rarg1); |
|
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|
3083 } |
|
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|
3084 // And do the conversion |
|
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|
3085 __ call(RuntimeAddress( |
|
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|
3086 CAST_FROM_FN_PTR(address, SharedRuntime::get_utf))); |
|
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|
3087 |
|
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|
3088 __ bind(done); |
|
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|
3089 } |
|
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|
3090 if (in_sig_bt[j_arg] == T_OBJECT && out_sig_bt[c_arg] == T_LONG) { |
|
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|
3091 assert(out_sig_bt[c_arg+1] == T_VOID, "must be"); |
|
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|
3092 ++c_arg; // skip over T_VOID to keep the loop indices in sync |
|
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|
3093 } |
|
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|
3094 } |
|
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|
3095 // The get_utf call killed all the c_arg registers |
|
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|
3096 live[c_rarg0->as_VMReg()->value()] = false; |
|
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|
3097 live[c_rarg1->as_VMReg()->value()] = false; |
|
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|
3098 live[c_rarg2->as_VMReg()->value()] = false; |
|
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|
3099 live[c_rarg3->as_VMReg()->value()] = false; |
|
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|
3100 live[c_rarg4->as_VMReg()->value()] = false; |
|
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|
3101 live[c_rarg5->as_VMReg()->value()] = false; |
|
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|
3102 |
|
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|
3103 live[c_farg0->as_VMReg()->value()] = false; |
|
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|
3104 live[c_farg1->as_VMReg()->value()] = false; |
|
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|
3105 live[c_farg2->as_VMReg()->value()] = false; |
|
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|
3106 live[c_farg3->as_VMReg()->value()] = false; |
|
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|
3107 live[c_farg4->as_VMReg()->value()] = false; |
|
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|
3108 live[c_farg5->as_VMReg()->value()] = false; |
|
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|
3109 live[c_farg6->as_VMReg()->value()] = false; |
|
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|
3110 live[c_farg7->as_VMReg()->value()] = false; |
|
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|
3111 } |
|
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|
3112 |
|
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|
3113 // Now we can finally move the register args to their desired locations |
|
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|
3114 |
|
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3115 rax_is_zero = false; |
|
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3116 |
|
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3117 for (j_arg = first_arg_to_pass, c_arg = 0 ; |
|
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3118 j_arg < total_args_passed ; j_arg++, c_arg++ ) { |
|
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3119 |
|
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3120 VMRegPair src = in_regs[j_arg]; |
|
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3121 VMRegPair dst = out_regs[c_arg]; |
|
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3122 |
|
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3123 // Only need to look for args destined for the interger registers (since we |
|
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3124 // convert float/double args to look like int/long outbound) |
|
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3125 if (dst.first()->is_reg()) { |
|
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3126 Register r = dst.first()->as_Register(); |
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3127 |
|
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3128 // Check if the java arg is unsupported and thereofre useless |
|
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3129 bool useless = in_sig_bt[j_arg] == T_ARRAY || |
|
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3130 (in_sig_bt[j_arg] == T_OBJECT && |
|
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3131 out_sig_bt[c_arg] != T_INT && |
|
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3132 out_sig_bt[c_arg] != T_ADDRESS && |
|
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3133 out_sig_bt[c_arg] != T_LONG); |
|
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3134 |
|
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|
3135 |
|
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3136 // If we're going to kill an existing arg save it first |
|
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3137 if (live[dst.first()->value()]) { |
|
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3138 // you can't kill yourself |
|
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3139 if (src.first() != dst.first()) { |
|
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3140 __ movq(Address(rbp, fp_offset[dst.first()->value()]), r); |
|
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|
3141 } |
|
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|
3142 } |
|
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|
3143 if (src.first()->is_reg()) { |
|
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3144 if (live[src.first()->value()] ) { |
|
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3145 if (in_sig_bt[j_arg] == T_FLOAT) { |
|
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3146 __ movdl(r, src.first()->as_XMMRegister()); |
|
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3147 } else if (in_sig_bt[j_arg] == T_DOUBLE) { |
|
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3148 __ movdq(r, src.first()->as_XMMRegister()); |
|
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3149 } else if (r != src.first()->as_Register()) { |
|
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3150 if (!useless) { |
|
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3151 __ movq(r, src.first()->as_Register()); |
|
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|
3152 } |
|
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|
3153 } |
|
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|
3154 } else { |
|
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3155 // If the arg is an oop type we don't support don't bother to store |
|
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|
3156 // it |
|
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|
3157 if (!useless) { |
|
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|
3158 if (in_sig_bt[j_arg] == T_DOUBLE || |
|
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3159 in_sig_bt[j_arg] == T_LONG || |
|
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3160 in_sig_bt[j_arg] == T_OBJECT ) { |
|
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3161 __ movq(r, Address(rbp, fp_offset[src.first()->value()])); |
|
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|
3162 } else { |
|
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|
3163 __ movl(r, Address(rbp, fp_offset[src.first()->value()])); |
|
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|
3164 } |
|
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|
3165 } |
|
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|
3166 } |
|
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|
3167 live[src.first()->value()] = false; |
|
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|
3168 } else if (!useless) { |
|
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|
3169 // full sized move even for int should be ok |
|
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|
3170 __ movq(r, Address(rbp, reg2offset_in(src.first()))); |
|
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|
3171 } |
|
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113
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|
3172 |
|
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|
3173 // At this point r has the original java arg in the final location |
|
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|
3174 // (assuming it wasn't useless). If the java arg was an oop |
|
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|
3175 // we have a bit more to do |
|
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|
3176 |
|
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|
3177 if (in_sig_bt[j_arg] == T_ARRAY || in_sig_bt[j_arg] == T_OBJECT ) { |
|
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|
3178 if (out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) { |
|
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|
3179 // need to unbox a one-word value |
|
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|
3180 Label skip; |
|
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|
3181 __ testq(r, r); |
|
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|
3182 __ jcc(Assembler::equal, skip); |
|
165
437d03ea40b1
6703888: Compressed Oops: use the 32-bits gap after klass in a object
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|
3183 BasicType bt = out_sig_bt[c_arg]; |
|
437d03ea40b1
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|
3184 int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt); |
|
116
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|
3185 Address src1(r, box_offset); |
|
165
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|
3186 if ( bt == T_LONG ) { |
|
116
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|
3187 __ movq(r, src1); |
|
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|
3188 } else { |
|
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|
3189 __ movl(r, src1); |
|
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|
3190 } |
|
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|
3191 __ bind(skip); |
|
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|
3192 |
|
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|
3193 } else if (out_sig_bt[c_arg] != T_ADDRESS) { |
|
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|
3194 // Convert the arg to NULL |
|
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|
3195 __ xorq(r, r); |
|
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|
3196 } |
|
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|
3197 } |
|
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|
3198 |
|
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|
3199 // dst can longer be holding an input value |
|
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|
3200 live[dst.first()->value()] = false; |
|
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|
3201 } |
|
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|
3202 if (in_sig_bt[j_arg] == T_OBJECT && out_sig_bt[c_arg] == T_LONG) { |
|
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|
3203 assert(out_sig_bt[c_arg+1] == T_VOID, "must be"); |
|
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|
3204 ++c_arg; // skip over T_VOID to keep the loop indices in sync |
|
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|
3205 } |
|
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|
3206 } |
|
018d5b58dd4f
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|
3207 |
|
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|
3208 |
|
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|
3209 // Ok now we are done. Need to place the nop that dtrace wants in order to |
|
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|
3210 // patch in the trap |
|
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|
3211 int patch_offset = ((intptr_t)__ pc()) - start; |
|
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|
3212 |
|
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|
3213 __ nop(); |
|
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|
3214 |
|
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|
3215 |
|
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|
3216 // Return |
|
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|
3217 |
|
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|
3218 __ leave(); |
|
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|
3219 __ ret(0); |
|
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|
3220 |
|
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|
3221 __ flush(); |
|
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|
3222 |
|
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|
3223 nmethod *nm = nmethod::new_dtrace_nmethod( |
|
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3224 method, masm->code(), vep_offset, patch_offset, frame_complete, |
|
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|
3225 stack_slots / VMRegImpl::slots_per_word); |
|
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|
3226 return nm; |
|
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|
3227 |
|
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|
3228 } |
|
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3229 |
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3230 #endif // HAVE_DTRACE_H |
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3231 |
| 0 | 3232 // this function returns the adjust size (in number of words) to a c2i adapter |
| 3233 // activation for use during deoptimization | |
| 3234 int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals ) { | |
| 1506 | 3235 return (callee_locals - callee_parameters) * Interpreter::stackElementWords; |
| 0 | 3236 } |
| 3237 | |
| 3238 | |
| 3239 uint SharedRuntime::out_preserve_stack_slots() { | |
| 3240 return 0; | |
| 3241 } | |
| 3242 | |
| 3243 | |
| 3244 //------------------------------generate_deopt_blob---------------------------- | |
| 3245 void SharedRuntime::generate_deopt_blob() { | |
| 3246 // Allocate space for the code | |
| 3247 ResourceMark rm; | |
| 3248 // Setup code generation tools | |
| 3249 CodeBuffer buffer("deopt_blob", 2048, 1024); | |
| 3250 MacroAssembler* masm = new MacroAssembler(&buffer); | |
| 3251 int frame_size_in_words; | |
| 3252 OopMap* map = NULL; | |
| 3253 OopMapSet *oop_maps = new OopMapSet(); | |
| 3254 | |
| 3255 // ------------- | |
| 3256 // This code enters when returning to a de-optimized nmethod. A return | |
| 3257 // address has been pushed on the the stack, and return values are in | |
| 3258 // registers. | |
| 3259 // If we are doing a normal deopt then we were called from the patched | |
| 3260 // nmethod from the point we returned to the nmethod. So the return | |
| 3261 // address on the stack is wrong by NativeCall::instruction_size | |
| 3262 // We will adjust the value so it looks like we have the original return | |
| 3263 // address on the stack (like when we eagerly deoptimized). | |
| 3264 // In the case of an exception pending when deoptimizing, we enter | |
| 3265 // with a return address on the stack that points after the call we patched | |
| 3266 // into the exception handler. We have the following register state from, | |
| 3267 // e.g., the forward exception stub (see stubGenerator_x86_64.cpp). | |
| 3268 // rax: exception oop | |
| 3269 // rbx: exception handler | |
| 3270 // rdx: throwing pc | |
| 3271 // So in this case we simply jam rdx into the useless return address and | |
| 3272 // the stack looks just like we want. | |
| 3273 // | |
| 3274 // At this point we need to de-opt. We save the argument return | |
| 3275 // registers. We call the first C routine, fetch_unroll_info(). This | |
| 3276 // routine captures the return values and returns a structure which | |
| 3277 // describes the current frame size and the sizes of all replacement frames. | |
| 3278 // The current frame is compiled code and may contain many inlined | |
| 3279 // functions, each with their own JVM state. We pop the current frame, then | |
| 3280 // push all the new frames. Then we call the C routine unpack_frames() to | |
| 3281 // populate these frames. Finally unpack_frames() returns us the new target | |
| 3282 // address. Notice that callee-save registers are BLOWN here; they have | |
| 3283 // already been captured in the vframeArray at the time the return PC was | |
| 3284 // patched. | |
| 3285 address start = __ pc(); | |
| 3286 Label cont; | |
| 3287 | |
| 3288 // Prolog for non exception case! | |
| 3289 | |
| 3290 // Save everything in sight. | |
| 3291 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words); | |
| 3292 | |
| 3293 // Normal deoptimization. Save exec mode for unpack_frames. | |
|
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|
3294 __ movl(r14, Deoptimization::Unpack_deopt); // callee-saved |
| 0 | 3295 __ jmp(cont); |
| 304 | 3296 |
| 3297 int reexecute_offset = __ pc() - start; | |
| 3298 | |
| 3299 // Reexecute case | |
| 3300 // return address is the pc describes what bci to do re-execute at | |
| 3301 | |
| 3302 // No need to update map as each call to save_live_registers will produce identical oopmap | |
| 3303 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words); | |
| 3304 | |
| 3305 __ movl(r14, Deoptimization::Unpack_reexecute); // callee-saved | |
| 3306 __ jmp(cont); | |
| 3307 | |
| 0 | 3308 int exception_offset = __ pc() - start; |
| 3309 | |
| 3310 // Prolog for exception case | |
| 3311 | |
| 304 | 3312 // all registers are dead at this entry point, except for rax, and |
| 3313 // rdx which contain the exception oop and exception pc | |
| 3314 // respectively. Set them in TLS and fall thru to the | |
| 3315 // unpack_with_exception_in_tls entry point. | |
| 3316 | |
| 3317 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), rdx); | |
| 3318 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), rax); | |
| 3319 | |
| 3320 int exception_in_tls_offset = __ pc() - start; | |
| 3321 | |
| 3322 // new implementation because exception oop is now passed in JavaThread | |
| 3323 | |
| 3324 // Prolog for exception case | |
| 3325 // All registers must be preserved because they might be used by LinearScan | |
| 3326 // Exceptiop oop and throwing PC are passed in JavaThread | |
| 3327 // tos: stack at point of call to method that threw the exception (i.e. only | |
| 3328 // args are on the stack, no return address) | |
| 3329 | |
| 3330 // make room on stack for the return address | |
| 3331 // It will be patched later with the throwing pc. The correct value is not | |
| 3332 // available now because loading it from memory would destroy registers. | |
| 3333 __ push(0); | |
| 0 | 3334 |
| 3335 // Save everything in sight. | |
| 3336 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words); | |
| 3337 | |
| 304 | 3338 // Now it is safe to overwrite any register |
| 3339 | |
| 0 | 3340 // Deopt during an exception. Save exec mode for unpack_frames. |
|
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3341 __ movl(r14, Deoptimization::Unpack_exception); // callee-saved |
| 0 | 3342 |
| 304 | 3343 // load throwing pc from JavaThread and patch it as the return address |
| 3344 // of the current frame. Then clear the field in JavaThread | |
| 3345 | |
| 3346 __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset())); | |
| 3347 __ movptr(Address(rbp, wordSize), rdx); | |
| 3348 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD); | |
| 3349 | |
| 3350 #ifdef ASSERT | |
| 3351 // verify that there is really an exception oop in JavaThread | |
| 3352 __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset())); | |
| 3353 __ verify_oop(rax); | |
| 3354 | |
| 3355 // verify that there is no pending exception | |
| 3356 Label no_pending_exception; | |
| 3357 __ movptr(rax, Address(r15_thread, Thread::pending_exception_offset())); | |
| 3358 __ testptr(rax, rax); | |
| 3359 __ jcc(Assembler::zero, no_pending_exception); | |
| 3360 __ stop("must not have pending exception here"); | |
| 3361 __ bind(no_pending_exception); | |
| 3362 #endif | |
| 3363 | |
| 0 | 3364 __ bind(cont); |
| 3365 | |
| 3366 // Call C code. Need thread and this frame, but NOT official VM entry | |
| 3367 // crud. We cannot block on this call, no GC can happen. | |
| 3368 // | |
| 3369 // UnrollBlock* fetch_unroll_info(JavaThread* thread) | |
| 3370 | |
| 3371 // fetch_unroll_info needs to call last_java_frame(). | |
| 3372 | |
| 3373 __ set_last_Java_frame(noreg, noreg, NULL); | |
| 3374 #ifdef ASSERT | |
| 3375 { Label L; | |
| 304 | 3376 __ cmpptr(Address(r15_thread, |
| 0 | 3377 JavaThread::last_Java_fp_offset()), |
| 304 | 3378 (int32_t)0); |
| 0 | 3379 __ jcc(Assembler::equal, L); |
| 3380 __ stop("SharedRuntime::generate_deopt_blob: last_Java_fp not cleared"); | |
| 3381 __ bind(L); | |
| 3382 } | |
| 3383 #endif // ASSERT | |
| 304 | 3384 __ mov(c_rarg0, r15_thread); |
| 0 | 3385 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info))); |
| 3386 | |
| 3387 // Need to have an oopmap that tells fetch_unroll_info where to | |
| 3388 // find any register it might need. | |
| 3389 oop_maps->add_gc_map(__ pc() - start, map); | |
| 3390 | |
| 3391 __ reset_last_Java_frame(false, false); | |
| 3392 | |
| 3393 // Load UnrollBlock* into rdi | |
| 304 | 3394 __ mov(rdi, rax); |
| 3395 | |
| 3396 Label noException; | |
|
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|
3397 __ cmpl(r14, Deoptimization::Unpack_exception); // Was exception pending? |
| 304 | 3398 __ jcc(Assembler::notEqual, noException); |
| 3399 __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset())); | |
| 3400 // QQQ this is useless it was NULL above | |
| 3401 __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset())); | |
| 3402 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD); | |
| 3403 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD); | |
| 3404 | |
| 3405 __ verify_oop(rax); | |
| 3406 | |
| 3407 // Overwrite the result registers with the exception results. | |
| 3408 __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax); | |
| 3409 // I think this is useless | |
| 3410 __ movptr(Address(rsp, RegisterSaver::rdx_offset_in_bytes()), rdx); | |
| 3411 | |
| 3412 __ bind(noException); | |
| 0 | 3413 |
| 3414 // Only register save data is on the stack. | |
| 3415 // Now restore the result registers. Everything else is either dead | |
| 3416 // or captured in the vframeArray. | |
| 3417 RegisterSaver::restore_result_registers(masm); | |
| 3418 | |
| 3419 // All of the register save area has been popped of the stack. Only the | |
| 3420 // return address remains. | |
| 3421 | |
| 3422 // Pop all the frames we must move/replace. | |
| 3423 // | |
| 3424 // Frame picture (youngest to oldest) | |
| 3425 // 1: self-frame (no frame link) | |
| 3426 // 2: deopting frame (no frame link) | |
| 3427 // 3: caller of deopting frame (could be compiled/interpreted). | |
| 3428 // | |
| 3429 // Note: by leaving the return address of self-frame on the stack | |
| 3430 // and using the size of frame 2 to adjust the stack | |
| 3431 // when we are done the return to frame 3 will still be on the stack. | |
| 3432 | |
| 3433 // Pop deoptimized frame | |
| 3434 __ movl(rcx, Address(rdi, Deoptimization::UnrollBlock::size_of_deoptimized_frame_offset_in_bytes())); | |
| 304 | 3435 __ addptr(rsp, rcx); |
| 0 | 3436 |
| 3437 // rsp should be pointing at the return address to the caller (3) | |
| 3438 | |
| 3439 // Stack bang to make sure there's enough room for these interpreter frames. | |
| 3440 if (UseStackBanging) { | |
| 3441 __ movl(rbx, Address(rdi, Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes())); | |
| 3442 __ bang_stack_size(rbx, rcx); | |
| 3443 } | |
| 3444 | |
| 3445 // Load address of array of frame pcs into rcx | |
| 304 | 3446 __ movptr(rcx, Address(rdi, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes())); |
| 0 | 3447 |
| 3448 // Trash the old pc | |
| 304 | 3449 __ addptr(rsp, wordSize); |
| 0 | 3450 |
| 3451 // Load address of array of frame sizes into rsi | |
| 304 | 3452 __ movptr(rsi, Address(rdi, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes())); |
| 0 | 3453 |
| 3454 // Load counter into rdx | |
| 3455 __ movl(rdx, Address(rdi, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes())); | |
| 3456 | |
| 3457 // Pick up the initial fp we should save | |
|
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|
3458 __ movptr(rbp, Address(rdi, Deoptimization::UnrollBlock::initial_info_offset_in_bytes())); |
| 0 | 3459 |
| 3460 // Now adjust the caller's stack to make up for the extra locals | |
| 3461 // but record the original sp so that we can save it in the skeletal interpreter | |
| 3462 // frame and the stack walking of interpreter_sender will get the unextended sp | |
| 3463 // value and not the "real" sp value. | |
| 3464 | |
| 3465 const Register sender_sp = r8; | |
| 3466 | |
| 304 | 3467 __ mov(sender_sp, rsp); |
| 0 | 3468 __ movl(rbx, Address(rdi, |
| 3469 Deoptimization::UnrollBlock:: | |
| 3470 caller_adjustment_offset_in_bytes())); | |
| 304 | 3471 __ subptr(rsp, rbx); |
| 0 | 3472 |
| 3473 // Push interpreter frames in a loop | |
| 3474 Label loop; | |
| 3475 __ bind(loop); | |
| 304 | 3476 __ movptr(rbx, Address(rsi, 0)); // Load frame size |
| 3477 #ifdef CC_INTERP | |
| 3478 __ subptr(rbx, 4*wordSize); // we'll push pc and ebp by hand and | |
| 3479 #ifdef ASSERT | |
| 3480 __ push(0xDEADDEAD); // Make a recognizable pattern | |
| 3481 __ push(0xDEADDEAD); | |
| 3482 #else /* ASSERT */ | |
| 3483 __ subptr(rsp, 2*wordSize); // skip the "static long no_param" | |
| 3484 #endif /* ASSERT */ | |
| 3485 #else | |
| 3486 __ subptr(rbx, 2*wordSize); // We'll push pc and ebp by hand | |
| 3487 #endif // CC_INTERP | |
| 3488 __ pushptr(Address(rcx, 0)); // Save return address | |
| 0 | 3489 __ enter(); // Save old & set new ebp |
| 304 | 3490 __ subptr(rsp, rbx); // Prolog |
| 3491 #ifdef CC_INTERP | |
| 3492 __ movptr(Address(rbp, | |
| 3493 -(sizeof(BytecodeInterpreter)) + in_bytes(byte_offset_of(BytecodeInterpreter, _sender_sp))), | |
| 3494 sender_sp); // Make it walkable | |
| 3495 #else /* CC_INTERP */ | |
| 0 | 3496 // This value is corrected by layout_activation_impl |
| 304 | 3497 __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD ); |
| 3498 __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize), sender_sp); // Make it walkable | |
| 3499 #endif /* CC_INTERP */ | |
| 3500 __ mov(sender_sp, rsp); // Pass sender_sp to next frame | |
| 3501 __ addptr(rsi, wordSize); // Bump array pointer (sizes) | |
| 3502 __ addptr(rcx, wordSize); // Bump array pointer (pcs) | |
| 0 | 3503 __ decrementl(rdx); // Decrement counter |
| 3504 __ jcc(Assembler::notZero, loop); | |
| 304 | 3505 __ pushptr(Address(rcx, 0)); // Save final return address |
| 0 | 3506 |
| 3507 // Re-push self-frame | |
| 3508 __ enter(); // Save old & set new ebp | |
| 3509 | |
| 3510 // Allocate a full sized register save area. | |
| 3511 // Return address and rbp are in place, so we allocate two less words. | |
| 304 | 3512 __ subptr(rsp, (frame_size_in_words - 2) * wordSize); |
| 0 | 3513 |
| 3514 // Restore frame locals after moving the frame | |
| 3515 __ movdbl(Address(rsp, RegisterSaver::xmm0_offset_in_bytes()), xmm0); | |
| 304 | 3516 __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax); |
| 0 | 3517 |
| 3518 // Call C code. Need thread but NOT official VM entry | |
| 3519 // crud. We cannot block on this call, no GC can happen. Call should | |
| 3520 // restore return values to their stack-slots with the new SP. | |
| 3521 // | |
| 3522 // void Deoptimization::unpack_frames(JavaThread* thread, int exec_mode) | |
| 3523 | |
| 3524 // Use rbp because the frames look interpreted now | |
|
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3525 // Save "the_pc" since it cannot easily be retrieved using the last_java_SP after we aligned SP. |
|
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3526 // Don't need the precise return PC here, just precise enough to point into this code blob. |
|
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3527 address the_pc = __ pc(); |
|
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3528 __ set_last_Java_frame(noreg, rbp, the_pc); |
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3529 |
|
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3530 __ andptr(rsp, -(StackAlignmentInBytes)); // Fix stack alignment as required by ABI |
| 304 | 3531 __ mov(c_rarg0, r15_thread); |
|
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3532 __ movl(c_rarg1, r14); // second arg: exec_mode |
| 0 | 3533 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames))); |
|
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3534 // Revert SP alignment after call since we're going to do some SP relative addressing below |
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|
3535 __ movptr(rsp, Address(r15_thread, JavaThread::last_Java_sp_offset())); |
| 0 | 3536 |
| 3537 // Set an oopmap for the call site | |
|
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3538 // Use the same PC we used for the last java frame |
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|
3539 oop_maps->add_gc_map(the_pc - start, |
| 0 | 3540 new OopMap( frame_size_in_words, 0 )); |
| 3541 | |
|
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3542 // Clear fp AND pc |
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|
3543 __ reset_last_Java_frame(true, true); |
| 0 | 3544 |
| 3545 // Collect return values | |
| 3546 __ movdbl(xmm0, Address(rsp, RegisterSaver::xmm0_offset_in_bytes())); | |
| 304 | 3547 __ movptr(rax, Address(rsp, RegisterSaver::rax_offset_in_bytes())); |
| 3548 // I think this is useless (throwing pc?) | |
| 3549 __ movptr(rdx, Address(rsp, RegisterSaver::rdx_offset_in_bytes())); | |
| 0 | 3550 |
| 3551 // Pop self-frame. | |
| 3552 __ leave(); // Epilog | |
| 3553 | |
| 3554 // Jump to interpreter | |
| 3555 __ ret(0); | |
| 3556 | |
| 3557 // Make sure all code is generated | |
| 3558 masm->flush(); | |
| 3559 | |
| 304 | 3560 _deopt_blob = DeoptimizationBlob::create(&buffer, oop_maps, 0, exception_offset, reexecute_offset, frame_size_in_words); |
| 3561 _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset); | |
| 0 | 3562 } |
| 3563 | |
| 3564 #ifdef COMPILER2 | |
| 3565 //------------------------------generate_uncommon_trap_blob-------------------- | |
| 3566 void SharedRuntime::generate_uncommon_trap_blob() { | |
| 3567 // Allocate space for the code | |
| 3568 ResourceMark rm; | |
| 3569 // Setup code generation tools | |
| 3570 CodeBuffer buffer("uncommon_trap_blob", 2048, 1024); | |
| 3571 MacroAssembler* masm = new MacroAssembler(&buffer); | |
| 3572 | |
| 3573 assert(SimpleRuntimeFrame::framesize % 4 == 0, "sp not 16-byte aligned"); | |
| 3574 | |
| 3575 address start = __ pc(); | |
| 3576 | |
| 3577 // Push self-frame. We get here with a return address on the | |
| 3578 // stack, so rsp is 8-byte aligned until we allocate our frame. | |
| 304 | 3579 __ subptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Epilog! |
| 0 | 3580 |
| 3581 // No callee saved registers. rbp is assumed implicitly saved | |
| 304 | 3582 __ movptr(Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt), rbp); |
| 0 | 3583 |
| 3584 // compiler left unloaded_class_index in j_rarg0 move to where the | |
| 3585 // runtime expects it. | |
| 3586 __ movl(c_rarg1, j_rarg0); | |
| 3587 | |
| 3588 __ set_last_Java_frame(noreg, noreg, NULL); | |
| 3589 | |
| 3590 // Call C code. Need thread but NOT official VM entry | |
| 3591 // crud. We cannot block on this call, no GC can happen. Call should | |
| 3592 // capture callee-saved registers as well as return values. | |
| 3593 // Thread is in rdi already. | |
| 3594 // | |
| 3595 // UnrollBlock* uncommon_trap(JavaThread* thread, jint unloaded_class_index); | |
| 3596 | |
| 304 | 3597 __ mov(c_rarg0, r15_thread); |
| 0 | 3598 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap))); |
| 3599 | |
| 3600 // Set an oopmap for the call site | |
| 3601 OopMapSet* oop_maps = new OopMapSet(); | |
| 3602 OopMap* map = new OopMap(SimpleRuntimeFrame::framesize, 0); | |
| 3603 | |
| 3604 // location of rbp is known implicitly by the frame sender code | |
| 3605 | |
| 3606 oop_maps->add_gc_map(__ pc() - start, map); | |
| 3607 | |
| 3608 __ reset_last_Java_frame(false, false); | |
| 3609 | |
| 3610 // Load UnrollBlock* into rdi | |
| 304 | 3611 __ mov(rdi, rax); |
| 0 | 3612 |
| 3613 // Pop all the frames we must move/replace. | |
| 3614 // | |
| 3615 // Frame picture (youngest to oldest) | |
| 3616 // 1: self-frame (no frame link) | |
| 3617 // 2: deopting frame (no frame link) | |
| 3618 // 3: caller of deopting frame (could be compiled/interpreted). | |
| 3619 | |
| 3620 // Pop self-frame. We have no frame, and must rely only on rax and rsp. | |
| 304 | 3621 __ addptr(rsp, (SimpleRuntimeFrame::framesize - 2) << LogBytesPerInt); // Epilog! |
| 0 | 3622 |
| 3623 // Pop deoptimized frame (int) | |
| 3624 __ movl(rcx, Address(rdi, | |
| 3625 Deoptimization::UnrollBlock:: | |
| 3626 size_of_deoptimized_frame_offset_in_bytes())); | |
| 304 | 3627 __ addptr(rsp, rcx); |
| 0 | 3628 |
| 3629 // rsp should be pointing at the return address to the caller (3) | |
| 3630 | |
| 3631 // Stack bang to make sure there's enough room for these interpreter frames. | |
| 3632 if (UseStackBanging) { | |
| 3633 __ movl(rbx, Address(rdi ,Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes())); | |
| 3634 __ bang_stack_size(rbx, rcx); | |
| 3635 } | |
| 3636 | |
| 3637 // Load address of array of frame pcs into rcx (address*) | |
| 304 | 3638 __ movptr(rcx, |
| 3639 Address(rdi, | |
| 3640 Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes())); | |
| 0 | 3641 |
| 3642 // Trash the return pc | |
| 304 | 3643 __ addptr(rsp, wordSize); |
| 0 | 3644 |
| 3645 // Load address of array of frame sizes into rsi (intptr_t*) | |
| 304 | 3646 __ movptr(rsi, Address(rdi, |
| 3647 Deoptimization::UnrollBlock:: | |
| 3648 frame_sizes_offset_in_bytes())); | |
| 0 | 3649 |
| 3650 // Counter | |
| 3651 __ movl(rdx, Address(rdi, | |
| 3652 Deoptimization::UnrollBlock:: | |
| 3653 number_of_frames_offset_in_bytes())); // (int) | |
| 3654 | |
| 3655 // Pick up the initial fp we should save | |
| 304 | 3656 __ movptr(rbp, |
| 3657 Address(rdi, | |
|
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3658 Deoptimization::UnrollBlock::initial_info_offset_in_bytes())); |
| 0 | 3659 |
| 3660 // Now adjust the caller's stack to make up for the extra locals but | |
| 3661 // record the original sp so that we can save it in the skeletal | |
| 3662 // interpreter frame and the stack walking of interpreter_sender | |
| 3663 // will get the unextended sp value and not the "real" sp value. | |
| 3664 | |
| 3665 const Register sender_sp = r8; | |
| 3666 | |
| 304 | 3667 __ mov(sender_sp, rsp); |
| 0 | 3668 __ movl(rbx, Address(rdi, |
| 3669 Deoptimization::UnrollBlock:: | |
| 3670 caller_adjustment_offset_in_bytes())); // (int) | |
| 304 | 3671 __ subptr(rsp, rbx); |
| 0 | 3672 |
| 3673 // Push interpreter frames in a loop | |
| 3674 Label loop; | |
| 3675 __ bind(loop); | |
| 304 | 3676 __ movptr(rbx, Address(rsi, 0)); // Load frame size |
| 3677 __ subptr(rbx, 2 * wordSize); // We'll push pc and rbp by hand | |
| 3678 __ pushptr(Address(rcx, 0)); // Save return address | |
| 3679 __ enter(); // Save old & set new rbp | |
| 3680 __ subptr(rsp, rbx); // Prolog | |
|
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3681 #ifdef CC_INTERP |
|
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3682 __ movptr(Address(rbp, |
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3683 -(sizeof(BytecodeInterpreter)) + in_bytes(byte_offset_of(BytecodeInterpreter, _sender_sp))), |
|
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3684 sender_sp); // Make it walkable |
|
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3685 #else // CC_INTERP |
| 304 | 3686 __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize), |
| 3687 sender_sp); // Make it walkable | |
| 0 | 3688 // This value is corrected by layout_activation_impl |
| 304 | 3689 __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD ); |
|
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3690 #endif // CC_INTERP |
| 304 | 3691 __ mov(sender_sp, rsp); // Pass sender_sp to next frame |
| 3692 __ addptr(rsi, wordSize); // Bump array pointer (sizes) | |
| 3693 __ addptr(rcx, wordSize); // Bump array pointer (pcs) | |
| 3694 __ decrementl(rdx); // Decrement counter | |
| 0 | 3695 __ jcc(Assembler::notZero, loop); |
| 304 | 3696 __ pushptr(Address(rcx, 0)); // Save final return address |
| 0 | 3697 |
| 3698 // Re-push self-frame | |
| 3699 __ enter(); // Save old & set new rbp | |
| 304 | 3700 __ subptr(rsp, (SimpleRuntimeFrame::framesize - 4) << LogBytesPerInt); |
| 0 | 3701 // Prolog |
| 3702 | |
| 3703 // Use rbp because the frames look interpreted now | |
|
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3704 // Save "the_pc" since it cannot easily be retrieved using the last_java_SP after we aligned SP. |
|
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3705 // Don't need the precise return PC here, just precise enough to point into this code blob. |
|
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3706 address the_pc = __ pc(); |
|
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|
3707 __ set_last_Java_frame(noreg, rbp, the_pc); |
| 0 | 3708 |
| 3709 // Call C code. Need thread but NOT official VM entry | |
| 3710 // crud. We cannot block on this call, no GC can happen. Call should | |
| 3711 // restore return values to their stack-slots with the new SP. | |
| 3712 // Thread is in rdi already. | |
| 3713 // | |
| 3714 // BasicType unpack_frames(JavaThread* thread, int exec_mode); | |
| 3715 | |
|
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|
3716 __ andptr(rsp, -(StackAlignmentInBytes)); // Align SP as required by ABI |
| 304 | 3717 __ mov(c_rarg0, r15_thread); |
| 0 | 3718 __ movl(c_rarg1, Deoptimization::Unpack_uncommon_trap); |
| 3719 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames))); | |
| 3720 | |
| 3721 // Set an oopmap for the call site | |
|
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3722 // Use the same PC we used for the last java frame |
|
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|
3723 oop_maps->add_gc_map(the_pc - start, new OopMap(SimpleRuntimeFrame::framesize, 0)); |
|
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3724 |
|
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|
3725 // Clear fp AND pc |
|
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|
3726 __ reset_last_Java_frame(true, true); |
| 0 | 3727 |
| 3728 // Pop self-frame. | |
| 3729 __ leave(); // Epilog | |
| 3730 | |
| 3731 // Jump to interpreter | |
| 3732 __ ret(0); | |
| 3733 | |
| 3734 // Make sure all code is generated | |
| 3735 masm->flush(); | |
| 3736 | |
| 3737 _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, oop_maps, | |
| 3738 SimpleRuntimeFrame::framesize >> 1); | |
| 3739 } | |
| 3740 #endif // COMPILER2 | |
| 3741 | |
| 3742 | |
| 3743 //------------------------------generate_handler_blob------ | |
| 3744 // | |
| 3745 // Generate a special Compile2Runtime blob that saves all registers, | |
| 3746 // and setup oopmap. | |
| 3747 // | |
|
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|
3748 SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, bool cause_return) { |
| 0 | 3749 assert(StubRoutines::forward_exception_entry() != NULL, |
| 3750 "must be generated before"); | |
| 3751 | |
| 3752 ResourceMark rm; | |
| 3753 OopMapSet *oop_maps = new OopMapSet(); | |
| 3754 OopMap* map; | |
| 3755 | |
| 3756 // Allocate space for the code. Setup code generation tools. | |
| 3757 CodeBuffer buffer("handler_blob", 2048, 1024); | |
| 3758 MacroAssembler* masm = new MacroAssembler(&buffer); | |
| 3759 | |
| 3760 address start = __ pc(); | |
| 3761 address call_pc = NULL; | |
| 3762 int frame_size_in_words; | |
| 3763 | |
| 3764 // Make room for return address (or push it again) | |
| 3765 if (!cause_return) { | |
| 304 | 3766 __ push(rbx); |
| 0 | 3767 } |
| 3768 | |
| 3769 // Save registers, fpu state, and flags | |
| 3770 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words); | |
| 3771 | |
| 3772 // The following is basically a call_VM. However, we need the precise | |
| 3773 // address of the call in order to generate an oopmap. Hence, we do all the | |
| 3774 // work outselves. | |
| 3775 | |
| 3776 __ set_last_Java_frame(noreg, noreg, NULL); | |
| 3777 | |
| 3778 // The return address must always be correct so that frame constructor never | |
| 3779 // sees an invalid pc. | |
| 3780 | |
| 3781 if (!cause_return) { | |
| 3782 // overwrite the dummy value we pushed on entry | |
| 304 | 3783 __ movptr(c_rarg0, Address(r15_thread, JavaThread::saved_exception_pc_offset())); |
| 3784 __ movptr(Address(rbp, wordSize), c_rarg0); | |
| 0 | 3785 } |
| 3786 | |
| 3787 // Do the call | |
| 304 | 3788 __ mov(c_rarg0, r15_thread); |
| 0 | 3789 __ call(RuntimeAddress(call_ptr)); |
| 3790 | |
| 3791 // Set an oopmap for the call site. This oopmap will map all | |
| 3792 // oop-registers and debug-info registers as callee-saved. This | |
| 3793 // will allow deoptimization at this safepoint to find all possible | |
| 3794 // debug-info recordings, as well as let GC find all oops. | |
| 3795 | |
| 3796 oop_maps->add_gc_map( __ pc() - start, map); | |
| 3797 | |
| 3798 Label noException; | |
| 3799 | |
| 3800 __ reset_last_Java_frame(false, false); | |
| 3801 | |
| 304 | 3802 __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD); |
| 0 | 3803 __ jcc(Assembler::equal, noException); |
| 3804 | |
| 3805 // Exception pending | |
| 3806 | |
| 3807 RegisterSaver::restore_live_registers(masm); | |
| 3808 | |
| 3809 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry())); | |
| 3810 | |
| 3811 // No exception case | |
| 3812 __ bind(noException); | |
| 3813 | |
| 3814 // Normal exit, restore registers and exit. | |
| 3815 RegisterSaver::restore_live_registers(masm); | |
| 3816 | |
| 3817 __ ret(0); | |
| 3818 | |
| 3819 // Make sure all code is generated | |
| 3820 masm->flush(); | |
| 3821 | |
| 3822 // Fill-out other meta info | |
| 3823 return SafepointBlob::create(&buffer, oop_maps, frame_size_in_words); | |
| 3824 } | |
| 3825 | |
| 3826 // | |
| 3827 // generate_resolve_blob - call resolution (static/virtual/opt-virtual/ic-miss | |
| 3828 // | |
| 3829 // Generate a stub that calls into vm to find out the proper destination | |
| 3830 // of a java call. All the argument registers are live at this point | |
| 3831 // but since this is generic code we don't know what they are and the caller | |
| 3832 // must do any gc of the args. | |
| 3833 // | |
|
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3834 RuntimeStub* SharedRuntime::generate_resolve_blob(address destination, const char* name) { |
| 0 | 3835 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before"); |
| 3836 | |
| 3837 // allocate space for the code | |
| 3838 ResourceMark rm; | |
| 3839 | |
| 3840 CodeBuffer buffer(name, 1000, 512); | |
| 3841 MacroAssembler* masm = new MacroAssembler(&buffer); | |
| 3842 | |
| 3843 int frame_size_in_words; | |
| 3844 | |
| 3845 OopMapSet *oop_maps = new OopMapSet(); | |
| 3846 OopMap* map = NULL; | |
| 3847 | |
| 3848 int start = __ offset(); | |
| 3849 | |
| 3850 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words); | |
| 3851 | |
| 3852 int frame_complete = __ offset(); | |
| 3853 | |
| 3854 __ set_last_Java_frame(noreg, noreg, NULL); | |
| 3855 | |
| 304 | 3856 __ mov(c_rarg0, r15_thread); |
| 0 | 3857 |
| 3858 __ call(RuntimeAddress(destination)); | |
| 3859 | |
| 3860 | |
| 3861 // Set an oopmap for the call site. | |
| 3862 // We need this not only for callee-saved registers, but also for volatile | |
| 3863 // registers that the compiler might be keeping live across a safepoint. | |
| 3864 | |
| 3865 oop_maps->add_gc_map( __ offset() - start, map); | |
| 3866 | |
| 3867 // rax contains the address we are going to jump to assuming no exception got installed | |
| 3868 | |
| 3869 // clear last_Java_sp | |
| 3870 __ reset_last_Java_frame(false, false); | |
| 3871 // check for pending exceptions | |
| 3872 Label pending; | |
| 304 | 3873 __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD); |
| 0 | 3874 __ jcc(Assembler::notEqual, pending); |
| 3875 | |
|
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3876 // get the returned Method* |
|
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3877 __ get_vm_result_2(rbx, r15_thread); |
| 304 | 3878 __ movptr(Address(rsp, RegisterSaver::rbx_offset_in_bytes()), rbx); |
| 3879 | |
| 3880 __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax); | |
| 0 | 3881 |
| 3882 RegisterSaver::restore_live_registers(masm); | |
| 3883 | |
| 3884 // We are back the the original state on entry and ready to go. | |
| 3885 | |
| 3886 __ jmp(rax); | |
| 3887 | |
| 3888 // Pending exception after the safepoint | |
| 3889 | |
| 3890 __ bind(pending); | |
| 3891 | |
| 3892 RegisterSaver::restore_live_registers(masm); | |
| 3893 | |
| 3894 // exception pending => remove activation and forward to exception handler | |
| 3895 | |
| 3896 __ movptr(Address(r15_thread, JavaThread::vm_result_offset()), (int)NULL_WORD); | |
| 3897 | |
| 304 | 3898 __ movptr(rax, Address(r15_thread, Thread::pending_exception_offset())); |
| 0 | 3899 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry())); |
| 3900 | |
| 3901 // ------------- | |
| 3902 // make sure all code is generated | |
| 3903 masm->flush(); | |
| 3904 | |
| 3905 // return the blob | |
| 3906 // frame_size_words or bytes?? | |
| 3907 return RuntimeStub::new_runtime_stub(name, &buffer, frame_complete, frame_size_in_words, oop_maps, true); | |
| 3908 } | |
| 3909 | |
| 3910 | |
| 3911 #ifdef COMPILER2 | |
| 3912 // This is here instead of runtime_x86_64.cpp because it uses SimpleRuntimeFrame | |
| 3913 // | |
| 3914 //------------------------------generate_exception_blob--------------------------- | |
| 3915 // creates exception blob at the end | |
| 3916 // Using exception blob, this code is jumped from a compiled method. | |
| 3917 // (see emit_exception_handler in x86_64.ad file) | |
| 3918 // | |
| 3919 // Given an exception pc at a call we call into the runtime for the | |
| 3920 // handler in this method. This handler might merely restore state | |
| 3921 // (i.e. callee save registers) unwind the frame and jump to the | |
| 3922 // exception handler for the nmethod if there is no Java level handler | |
| 3923 // for the nmethod. | |
| 3924 // | |
| 3925 // This code is entered with a jmp. | |
| 3926 // | |
| 3927 // Arguments: | |
| 3928 // rax: exception oop | |
| 3929 // rdx: exception pc | |
| 3930 // | |
| 3931 // Results: | |
| 3932 // rax: exception oop | |
| 3933 // rdx: exception pc in caller or ??? | |
| 3934 // destination: exception handler of caller | |
| 3935 // | |
| 3936 // Note: the exception pc MUST be at a call (precise debug information) | |
| 3937 // Registers rax, rdx, rcx, rsi, rdi, r8-r11 are not callee saved. | |
| 3938 // | |
| 3939 | |
| 3940 void OptoRuntime::generate_exception_blob() { | |
| 3941 assert(!OptoRuntime::is_callee_saved_register(RDX_num), ""); | |
| 3942 assert(!OptoRuntime::is_callee_saved_register(RAX_num), ""); | |
| 3943 assert(!OptoRuntime::is_callee_saved_register(RCX_num), ""); | |
| 3944 | |
| 3945 assert(SimpleRuntimeFrame::framesize % 4 == 0, "sp not 16-byte aligned"); | |
| 3946 | |
| 3947 // Allocate space for the code | |
| 3948 ResourceMark rm; | |
| 3949 // Setup code generation tools | |
| 3950 CodeBuffer buffer("exception_blob", 2048, 1024); | |
| 3951 MacroAssembler* masm = new MacroAssembler(&buffer); | |
| 3952 | |
| 3953 | |
| 3954 address start = __ pc(); | |
| 3955 | |
| 3956 // Exception pc is 'return address' for stack walker | |
| 304 | 3957 __ push(rdx); |
| 3958 __ subptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Prolog | |
| 0 | 3959 |
| 3960 // Save callee-saved registers. See x86_64.ad. | |
| 3961 | |
| 3962 // rbp is an implicitly saved callee saved register (i.e. the calling | |
| 3963 // convention will save restore it in prolog/epilog) Other than that | |
| 3964 // there are no callee save registers now that adapter frames are gone. | |
| 3965 | |
| 304 | 3966 __ movptr(Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt), rbp); |
| 0 | 3967 |
| 3968 // Store exception in Thread object. We cannot pass any arguments to the | |
| 3969 // handle_exception call, since we do not want to make any assumption | |
| 3970 // about the size of the frame where the exception happened in. | |
| 3971 // c_rarg0 is either rdi (Linux) or rcx (Windows). | |
| 304 | 3972 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()),rax); |
| 3973 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), rdx); | |
| 0 | 3974 |
| 3975 // This call does all the hard work. It checks if an exception handler | |
| 3976 // exists in the method. | |
| 3977 // If so, it returns the handler address. | |
| 3978 // If not, it prepares for stack-unwinding, restoring the callee-save | |
| 3979 // registers of the frame being removed. | |
| 3980 // | |
| 3981 // address OptoRuntime::handle_exception_C(JavaThread* thread) | |
| 3982 | |
|
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3983 // At a method handle call, the stack may not be properly aligned |
|
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3984 // when returning with an exception. |
|
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|
3985 address the_pc = __ pc(); |
|
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3986 __ set_last_Java_frame(noreg, noreg, the_pc); |
| 304 | 3987 __ mov(c_rarg0, r15_thread); |
|
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3988 __ andptr(rsp, -(StackAlignmentInBytes)); // Align stack |
| 0 | 3989 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, OptoRuntime::handle_exception_C))); |
| 3990 | |
| 3991 // Set an oopmap for the call site. This oopmap will only be used if we | |
| 3992 // are unwinding the stack. Hence, all locations will be dead. | |
| 3993 // Callee-saved registers will be the same as the frame above (i.e., | |
| 3994 // handle_exception_stub), since they were restored when we got the | |
| 3995 // exception. | |
| 3996 | |
| 3997 OopMapSet* oop_maps = new OopMapSet(); | |
| 3998 | |
|
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|
3999 oop_maps->add_gc_map(the_pc - start, new OopMap(SimpleRuntimeFrame::framesize, 0)); |
|
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|
4000 |
|
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|
4001 __ reset_last_Java_frame(false, true); |
| 0 | 4002 |
| 4003 // Restore callee-saved registers | |
| 4004 | |
| 4005 // rbp is an implicitly saved callee saved register (i.e. the calling | |
| 4006 // convention will save restore it in prolog/epilog) Other than that | |
| 4007 // there are no callee save registers no that adapter frames are gone. | |
| 4008 | |
| 304 | 4009 __ movptr(rbp, Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt)); |
| 4010 | |
| 4011 __ addptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Epilog | |
| 4012 __ pop(rdx); // No need for exception pc anymore | |
| 0 | 4013 |
| 4014 // rax: exception handler | |
| 4015 | |
|
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4016 // Restore SP from BP if the exception PC is a MethodHandle call site. |
|
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4017 __ cmpl(Address(r15_thread, JavaThread::is_method_handle_return_offset()), 0); |
| 1567 | 4018 __ cmovptr(Assembler::notEqual, rsp, rbp_mh_SP_save); |
|
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twisti
parents:
848
diff
changeset
|
4019 |
| 0 | 4020 // We have a handler in rax (could be deopt blob). |
| 304 | 4021 __ mov(r8, rax); |
| 0 | 4022 |
| 4023 // Get the exception oop | |
| 304 | 4024 __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset())); |
| 0 | 4025 // Get the exception pc in case we are deoptimized |
| 304 | 4026 __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset())); |
| 0 | 4027 #ifdef ASSERT |
| 4028 __ movptr(Address(r15_thread, JavaThread::exception_handler_pc_offset()), (int)NULL_WORD); | |
| 4029 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int)NULL_WORD); | |
| 4030 #endif | |
| 4031 // Clear the exception oop so GC no longer processes it as a root. | |
| 4032 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), (int)NULL_WORD); | |
| 4033 | |
| 4034 // rax: exception oop | |
| 4035 // r8: exception handler | |
| 4036 // rdx: exception pc | |
| 4037 // Jump to handler | |
| 4038 | |
| 4039 __ jmp(r8); | |
| 4040 | |
| 4041 // Make sure all code is generated | |
| 4042 masm->flush(); | |
| 4043 | |
| 4044 // Set exception blob | |
| 4045 _exception_blob = ExceptionBlob::create(&buffer, oop_maps, SimpleRuntimeFrame::framesize >> 1); | |
| 4046 } | |
| 4047 #endif // COMPILER2 |