annotate src/cpu/x86/vm/x86_64.ad @ 10169:e10e43e58e92

Merge
author dlong
date Wed, 24 Apr 2013 21:11:02 -0400
parents a6e09d6dd8e5 886d1fd67dc3
children 78603aa58b1e
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1 //
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2 // Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved.
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3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 //
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5 // This code is free software; you can redistribute it and/or modify it
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6 // under the terms of the GNU General Public License version 2 only, as
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7 // published by the Free Software Foundation.
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8 //
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9 // This code is distributed in the hope that it will be useful, but WITHOUT
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10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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12 // version 2 for more details (a copy is included in the LICENSE file that
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13 // accompanied this code).
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14 //
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15 // You should have received a copy of the GNU General Public License version
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16 // 2 along with this work; if not, write to the Free Software Foundation,
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17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 //
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c18cbe5936b8 6941466: Oracle rebranding changes for Hotspot repositories
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19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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20 // or visit www.oracle.com if you need additional information or have any
c18cbe5936b8 6941466: Oracle rebranding changes for Hotspot repositories
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21 // questions.
0
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22 //
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23 //
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24
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25 // AMD64 Architecture Description File
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26
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27 //----------REGISTER DEFINITION BLOCK------------------------------------------
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28 // This information is used by the matcher and the register allocator to
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29 // describe individual registers and classes of registers within the target
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30 // archtecture.
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31
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32 register %{
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33 //----------Architecture Description Register Definitions----------------------
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34 // General Registers
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35 // "reg_def" name ( register save type, C convention save type,
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36 // ideal register type, encoding );
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37 // Register Save Types:
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38 //
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39 // NS = No-Save: The register allocator assumes that these registers
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40 // can be used without saving upon entry to the method, &
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41 // that they do not need to be saved at call sites.
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42 //
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43 // SOC = Save-On-Call: The register allocator assumes that these registers
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44 // can be used without saving upon entry to the method,
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45 // but that they must be saved at call sites.
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46 //
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47 // SOE = Save-On-Entry: The register allocator assumes that these registers
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48 // must be saved before using them upon entry to the
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49 // method, but they do not need to be saved at call
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50 // sites.
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51 //
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52 // AS = Always-Save: The register allocator assumes that these registers
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53 // must be saved before using them upon entry to the
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54 // method, & that they must be saved at call sites.
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55 //
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56 // Ideal Register Type is used to determine how to save & restore a
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57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
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58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
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59 //
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60 // The encoding number is the actual bit-pattern placed into the opcodes.
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61
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62 // General Registers
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63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
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64 // used as byte registers)
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65
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66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
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67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
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68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
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69
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70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
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71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
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72
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73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
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74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
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75
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76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
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77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
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78
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79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
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80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
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81
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82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
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83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
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84
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85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
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86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
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87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
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88
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89 #ifdef _WIN64
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90
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91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
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92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
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93
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94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
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95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
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96
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97 #else
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98
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99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
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100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
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101
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102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
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103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
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104
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105 #endif
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106
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107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
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108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
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109
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110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
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111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
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112
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113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
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114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
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115
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116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
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117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
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118
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119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
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120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
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121
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122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
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123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
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124
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125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
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126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
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127
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128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
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129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
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130
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131
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132 // Floating Point Registers
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133
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134 // Specify priority of register selection within phases of register
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135 // allocation. Highest priority is first. A useful heuristic is to
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136 // give registers a low priority when they are required by machine
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137 // instructions, like EAX and EDX on I486, and choose no-save registers
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138 // before save-on-call, & save-on-call before save-on-entry. Registers
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139 // which participate in fixed calling sequences should come last.
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140 // Registers which are used as pairs must fall on an even boundary.
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141
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142 alloc_class chunk0(R10, R10_H,
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143 R11, R11_H,
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144 R8, R8_H,
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145 R9, R9_H,
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146 R12, R12_H,
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147 RCX, RCX_H,
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148 RBX, RBX_H,
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149 RDI, RDI_H,
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150 RDX, RDX_H,
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151 RSI, RSI_H,
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152 RAX, RAX_H,
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153 RBP, RBP_H,
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154 R13, R13_H,
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155 R14, R14_H,
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156 R15, R15_H,
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157 RSP, RSP_H);
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158
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159
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160 //----------Architecture Description Register Classes--------------------------
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161 // Several register classes are automatically defined based upon information in
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162 // this architecture description.
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163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
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164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
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165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
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166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
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167 //
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168
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169 // Class for all pointer registers (including RSP)
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170 reg_class any_reg(RAX, RAX_H,
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171 RDX, RDX_H,
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172 RBP, RBP_H,
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173 RDI, RDI_H,
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174 RSI, RSI_H,
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175 RCX, RCX_H,
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176 RBX, RBX_H,
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177 RSP, RSP_H,
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178 R8, R8_H,
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179 R9, R9_H,
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180 R10, R10_H,
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181 R11, R11_H,
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182 R12, R12_H,
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183 R13, R13_H,
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184 R14, R14_H,
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185 R15, R15_H);
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186
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187 // Class for all pointer registers except RSP
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188 reg_class ptr_reg(RAX, RAX_H,
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189 RDX, RDX_H,
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190 RBP, RBP_H,
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191 RDI, RDI_H,
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192 RSI, RSI_H,
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193 RCX, RCX_H,
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194 RBX, RBX_H,
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195 R8, R8_H,
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196 R9, R9_H,
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197 R10, R10_H,
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198 R11, R11_H,
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199 R13, R13_H,
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200 R14, R14_H);
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201
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202 // Class for all pointer registers except RAX and RSP
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203 reg_class ptr_no_rax_reg(RDX, RDX_H,
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204 RBP, RBP_H,
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205 RDI, RDI_H,
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206 RSI, RSI_H,
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207 RCX, RCX_H,
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208 RBX, RBX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
209 R8, R8_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
210 R9, R9_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
211 R10, R10_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
212 R11, R11_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
213 R13, R13_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
214 R14, R14_H);
a61af66fc99e Initial load
duke
parents:
diff changeset
215
a61af66fc99e Initial load
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parents:
diff changeset
216 reg_class ptr_no_rbp_reg(RDX, RDX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
217 RAX, RAX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
218 RDI, RDI_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
219 RSI, RSI_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
220 RCX, RCX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
221 RBX, RBX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
222 R8, R8_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
223 R9, R9_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
224 R10, R10_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
225 R11, R11_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
226 R13, R13_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
227 R14, R14_H);
a61af66fc99e Initial load
duke
parents:
diff changeset
228
a61af66fc99e Initial load
duke
parents:
diff changeset
229 // Class for all pointer registers except RAX, RBX and RSP
a61af66fc99e Initial load
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parents:
diff changeset
230 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
231 RBP, RBP_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
232 RDI, RDI_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
233 RSI, RSI_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
234 RCX, RCX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
235 R8, R8_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
236 R9, R9_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
237 R10, R10_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
238 R11, R11_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
239 R13, R13_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
240 R14, R14_H);
a61af66fc99e Initial load
duke
parents:
diff changeset
241
a61af66fc99e Initial load
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parents:
diff changeset
242 // Singleton class for RAX pointer register
a61af66fc99e Initial load
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parents:
diff changeset
243 reg_class ptr_rax_reg(RAX, RAX_H);
a61af66fc99e Initial load
duke
parents:
diff changeset
244
a61af66fc99e Initial load
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parents:
diff changeset
245 // Singleton class for RBX pointer register
a61af66fc99e Initial load
duke
parents:
diff changeset
246 reg_class ptr_rbx_reg(RBX, RBX_H);
a61af66fc99e Initial load
duke
parents:
diff changeset
247
a61af66fc99e Initial load
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parents:
diff changeset
248 // Singleton class for RSI pointer register
a61af66fc99e Initial load
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parents:
diff changeset
249 reg_class ptr_rsi_reg(RSI, RSI_H);
a61af66fc99e Initial load
duke
parents:
diff changeset
250
a61af66fc99e Initial load
duke
parents:
diff changeset
251 // Singleton class for RDI pointer register
a61af66fc99e Initial load
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parents:
diff changeset
252 reg_class ptr_rdi_reg(RDI, RDI_H);
a61af66fc99e Initial load
duke
parents:
diff changeset
253
a61af66fc99e Initial load
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parents:
diff changeset
254 // Singleton class for RBP pointer register
a61af66fc99e Initial load
duke
parents:
diff changeset
255 reg_class ptr_rbp_reg(RBP, RBP_H);
a61af66fc99e Initial load
duke
parents:
diff changeset
256
a61af66fc99e Initial load
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parents:
diff changeset
257 // Singleton class for stack pointer
a61af66fc99e Initial load
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parents:
diff changeset
258 reg_class ptr_rsp_reg(RSP, RSP_H);
a61af66fc99e Initial load
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parents:
diff changeset
259
a61af66fc99e Initial load
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parents:
diff changeset
260 // Singleton class for TLS pointer
a61af66fc99e Initial load
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parents:
diff changeset
261 reg_class ptr_r15_reg(R15, R15_H);
a61af66fc99e Initial load
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parents:
diff changeset
262
a61af66fc99e Initial load
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parents:
diff changeset
263 // Class for all long registers (except RSP)
a61af66fc99e Initial load
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parents:
diff changeset
264 reg_class long_reg(RAX, RAX_H,
a61af66fc99e Initial load
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parents:
diff changeset
265 RDX, RDX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
266 RBP, RBP_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
267 RDI, RDI_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
268 RSI, RSI_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
269 RCX, RCX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
270 RBX, RBX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
271 R8, R8_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
272 R9, R9_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
273 R10, R10_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
274 R11, R11_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
275 R13, R13_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
276 R14, R14_H);
a61af66fc99e Initial load
duke
parents:
diff changeset
277
a61af66fc99e Initial load
duke
parents:
diff changeset
278 // Class for all long registers except RAX, RDX (and RSP)
a61af66fc99e Initial load
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parents:
diff changeset
279 reg_class long_no_rax_rdx_reg(RBP, RBP_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
280 RDI, RDI_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
281 RSI, RSI_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
282 RCX, RCX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
283 RBX, RBX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
284 R8, R8_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
285 R9, R9_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
286 R10, R10_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
287 R11, R11_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
288 R13, R13_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
289 R14, R14_H);
a61af66fc99e Initial load
duke
parents:
diff changeset
290
a61af66fc99e Initial load
duke
parents:
diff changeset
291 // Class for all long registers except RCX (and RSP)
a61af66fc99e Initial load
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parents:
diff changeset
292 reg_class long_no_rcx_reg(RBP, RBP_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
293 RDI, RDI_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
294 RSI, RSI_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
295 RAX, RAX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
296 RDX, RDX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
297 RBX, RBX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
298 R8, R8_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
299 R9, R9_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
300 R10, R10_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
301 R11, R11_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
302 R13, R13_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
303 R14, R14_H);
a61af66fc99e Initial load
duke
parents:
diff changeset
304
a61af66fc99e Initial load
duke
parents:
diff changeset
305 // Class for all long registers except RAX (and RSP)
a61af66fc99e Initial load
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parents:
diff changeset
306 reg_class long_no_rax_reg(RBP, RBP_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
307 RDX, RDX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
308 RDI, RDI_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
309 RSI, RSI_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
310 RCX, RCX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
311 RBX, RBX_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
312 R8, R8_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
313 R9, R9_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
314 R10, R10_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
315 R11, R11_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
316 R13, R13_H,
a61af66fc99e Initial load
duke
parents:
diff changeset
317 R14, R14_H);
a61af66fc99e Initial load
duke
parents:
diff changeset
318
a61af66fc99e Initial load
duke
parents:
diff changeset
319 // Singleton class for RAX long register
a61af66fc99e Initial load
duke
parents:
diff changeset
320 reg_class long_rax_reg(RAX, RAX_H);
a61af66fc99e Initial load
duke
parents:
diff changeset
321
a61af66fc99e Initial load
duke
parents:
diff changeset
322 // Singleton class for RCX long register
a61af66fc99e Initial load
duke
parents:
diff changeset
323 reg_class long_rcx_reg(RCX, RCX_H);
a61af66fc99e Initial load
duke
parents:
diff changeset
324
a61af66fc99e Initial load
duke
parents:
diff changeset
325 // Singleton class for RDX long register
a61af66fc99e Initial load
duke
parents:
diff changeset
326 reg_class long_rdx_reg(RDX, RDX_H);
a61af66fc99e Initial load
duke
parents:
diff changeset
327
a61af66fc99e Initial load
duke
parents:
diff changeset
328 // Class for all int registers (except RSP)
a61af66fc99e Initial load
duke
parents:
diff changeset
329 reg_class int_reg(RAX,
a61af66fc99e Initial load
duke
parents:
diff changeset
330 RDX,
a61af66fc99e Initial load
duke
parents:
diff changeset
331 RBP,
a61af66fc99e Initial load
duke
parents:
diff changeset
332 RDI,
a61af66fc99e Initial load
duke
parents:
diff changeset
333 RSI,
a61af66fc99e Initial load
duke
parents:
diff changeset
334 RCX,
a61af66fc99e Initial load
duke
parents:
diff changeset
335 RBX,
a61af66fc99e Initial load
duke
parents:
diff changeset
336 R8,
a61af66fc99e Initial load
duke
parents:
diff changeset
337 R9,
a61af66fc99e Initial load
duke
parents:
diff changeset
338 R10,
a61af66fc99e Initial load
duke
parents:
diff changeset
339 R11,
a61af66fc99e Initial load
duke
parents:
diff changeset
340 R13,
a61af66fc99e Initial load
duke
parents:
diff changeset
341 R14);
a61af66fc99e Initial load
duke
parents:
diff changeset
342
a61af66fc99e Initial load
duke
parents:
diff changeset
343 // Class for all int registers except RCX (and RSP)
a61af66fc99e Initial load
duke
parents:
diff changeset
344 reg_class int_no_rcx_reg(RAX,
a61af66fc99e Initial load
duke
parents:
diff changeset
345 RDX,
a61af66fc99e Initial load
duke
parents:
diff changeset
346 RBP,
a61af66fc99e Initial load
duke
parents:
diff changeset
347 RDI,
a61af66fc99e Initial load
duke
parents:
diff changeset
348 RSI,
a61af66fc99e Initial load
duke
parents:
diff changeset
349 RBX,
a61af66fc99e Initial load
duke
parents:
diff changeset
350 R8,
a61af66fc99e Initial load
duke
parents:
diff changeset
351 R9,
a61af66fc99e Initial load
duke
parents:
diff changeset
352 R10,
a61af66fc99e Initial load
duke
parents:
diff changeset
353 R11,
a61af66fc99e Initial load
duke
parents:
diff changeset
354 R13,
a61af66fc99e Initial load
duke
parents:
diff changeset
355 R14);
a61af66fc99e Initial load
duke
parents:
diff changeset
356
a61af66fc99e Initial load
duke
parents:
diff changeset
357 // Class for all int registers except RAX, RDX (and RSP)
a61af66fc99e Initial load
duke
parents:
diff changeset
358 reg_class int_no_rax_rdx_reg(RBP,
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
359 RDI,
0
a61af66fc99e Initial load
duke
parents:
diff changeset
360 RSI,
a61af66fc99e Initial load
duke
parents:
diff changeset
361 RCX,
a61af66fc99e Initial load
duke
parents:
diff changeset
362 RBX,
a61af66fc99e Initial load
duke
parents:
diff changeset
363 R8,
a61af66fc99e Initial load
duke
parents:
diff changeset
364 R9,
a61af66fc99e Initial load
duke
parents:
diff changeset
365 R10,
a61af66fc99e Initial load
duke
parents:
diff changeset
366 R11,
a61af66fc99e Initial load
duke
parents:
diff changeset
367 R13,
a61af66fc99e Initial load
duke
parents:
diff changeset
368 R14);
a61af66fc99e Initial load
duke
parents:
diff changeset
369
a61af66fc99e Initial load
duke
parents:
diff changeset
370 // Singleton class for RAX int register
a61af66fc99e Initial load
duke
parents:
diff changeset
371 reg_class int_rax_reg(RAX);
a61af66fc99e Initial load
duke
parents:
diff changeset
372
a61af66fc99e Initial load
duke
parents:
diff changeset
373 // Singleton class for RBX int register
a61af66fc99e Initial load
duke
parents:
diff changeset
374 reg_class int_rbx_reg(RBX);
a61af66fc99e Initial load
duke
parents:
diff changeset
375
a61af66fc99e Initial load
duke
parents:
diff changeset
376 // Singleton class for RCX int register
a61af66fc99e Initial load
duke
parents:
diff changeset
377 reg_class int_rcx_reg(RCX);
a61af66fc99e Initial load
duke
parents:
diff changeset
378
a61af66fc99e Initial load
duke
parents:
diff changeset
379 // Singleton class for RCX int register
a61af66fc99e Initial load
duke
parents:
diff changeset
380 reg_class int_rdx_reg(RDX);
a61af66fc99e Initial load
duke
parents:
diff changeset
381
a61af66fc99e Initial load
duke
parents:
diff changeset
382 // Singleton class for RCX int register
a61af66fc99e Initial load
duke
parents:
diff changeset
383 reg_class int_rdi_reg(RDI);
a61af66fc99e Initial load
duke
parents:
diff changeset
384
a61af66fc99e Initial load
duke
parents:
diff changeset
385 // Singleton class for instruction pointer
a61af66fc99e Initial load
duke
parents:
diff changeset
386 // reg_class ip_reg(RIP);
a61af66fc99e Initial load
duke
parents:
diff changeset
387
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
388 %}
0
a61af66fc99e Initial load
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parents:
diff changeset
389
a61af66fc99e Initial load
duke
parents:
diff changeset
390 //----------SOURCE BLOCK-------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
391 // This is a block of C++ code which provides values, functions, and
a61af66fc99e Initial load
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parents:
diff changeset
392 // definitions necessary in the rest of the architecture description
a61af66fc99e Initial load
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parents:
diff changeset
393 source %{
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
394 #define RELOC_IMM64 Assembler::imm_operand
0
a61af66fc99e Initial load
duke
parents:
diff changeset
395 #define RELOC_DISP32 Assembler::disp32_operand
a61af66fc99e Initial load
duke
parents:
diff changeset
396
a61af66fc99e Initial load
duke
parents:
diff changeset
397 #define __ _masm.
a61af66fc99e Initial load
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parents:
diff changeset
398
1137
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
399 static int preserve_SP_size() {
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
400 return 3; // rex.w, op, rm(reg/reg)
1137
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
401 }
8873
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
402 static int clear_avx_size() {
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
403 return (Compile::current()->max_vector_size() > 16) ? 3 : 0; // vzeroupper
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
404 }
1137
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
405
0
a61af66fc99e Initial load
duke
parents:
diff changeset
406 // !!!!! Special hack to get all types of calls to specify the byte offset
a61af66fc99e Initial load
duke
parents:
diff changeset
407 // from the start of the call to the point where the return address
a61af66fc99e Initial load
duke
parents:
diff changeset
408 // will point.
a61af66fc99e Initial load
duke
parents:
diff changeset
409 int MachCallStaticJavaNode::ret_addr_offset()
a61af66fc99e Initial load
duke
parents:
diff changeset
410 {
1137
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
411 int offset = 5; // 5 bytes from start of call to where return address points
8873
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
412 offset += clear_avx_size();
1137
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
413 if (_method_handle_invoke)
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
414 offset += preserve_SP_size();
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
415 return offset;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
416 }
a61af66fc99e Initial load
duke
parents:
diff changeset
417
a61af66fc99e Initial load
duke
parents:
diff changeset
418 int MachCallDynamicJavaNode::ret_addr_offset()
a61af66fc99e Initial load
duke
parents:
diff changeset
419 {
8873
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
420 int offset = 15; // 15 bytes from start of call to where return address points
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
421 offset += clear_avx_size();
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
422 return offset;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
423 }
a61af66fc99e Initial load
duke
parents:
diff changeset
424
8873
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
425 int MachCallRuntimeNode::ret_addr_offset() {
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
426 int offset = 13; // movq r10,#addr; callq (r10)
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
427 offset += clear_avx_size();
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
428 return offset;
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
429 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
430
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
431 // Indicate if the safepoint node needs the polling page as an input,
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
432 // it does if the polling page is more than disp32 away.
0
a61af66fc99e Initial load
duke
parents:
diff changeset
433 bool SafePointNode::needs_polling_address_input()
a61af66fc99e Initial load
duke
parents:
diff changeset
434 {
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
435 return Assembler::is_polling_page_far();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
436 }
a61af66fc99e Initial load
duke
parents:
diff changeset
437
a61af66fc99e Initial load
duke
parents:
diff changeset
438 //
a61af66fc99e Initial load
duke
parents:
diff changeset
439 // Compute padding required for nodes which need alignment
a61af66fc99e Initial load
duke
parents:
diff changeset
440 //
a61af66fc99e Initial load
duke
parents:
diff changeset
441
a61af66fc99e Initial load
duke
parents:
diff changeset
442 // The address of the call instruction needs to be 4-byte aligned to
a61af66fc99e Initial load
duke
parents:
diff changeset
443 // ensure that it does not span a cache line so that it can be patched.
a61af66fc99e Initial load
duke
parents:
diff changeset
444 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
a61af66fc99e Initial load
duke
parents:
diff changeset
445 {
8873
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
446 current_offset += clear_avx_size(); // skip vzeroupper
0
a61af66fc99e Initial load
duke
parents:
diff changeset
447 current_offset += 1; // skip call opcode byte
a61af66fc99e Initial load
duke
parents:
diff changeset
448 return round_to(current_offset, alignment_required()) - current_offset;
a61af66fc99e Initial load
duke
parents:
diff changeset
449 }
a61af66fc99e Initial load
duke
parents:
diff changeset
450
a61af66fc99e Initial load
duke
parents:
diff changeset
451 // The address of the call instruction needs to be 4-byte aligned to
a61af66fc99e Initial load
duke
parents:
diff changeset
452 // ensure that it does not span a cache line so that it can be patched.
1137
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
453 int CallStaticJavaHandleNode::compute_padding(int current_offset) const
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
454 {
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
455 current_offset += preserve_SP_size(); // skip mov rbp, rsp
8873
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
456 current_offset += clear_avx_size(); // skip vzeroupper
1137
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
457 current_offset += 1; // skip call opcode byte
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
458 return round_to(current_offset, alignment_required()) - current_offset;
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
459 }
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
460
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
461 // The address of the call instruction needs to be 4-byte aligned to
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
462 // ensure that it does not span a cache line so that it can be patched.
0
a61af66fc99e Initial load
duke
parents:
diff changeset
463 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
a61af66fc99e Initial load
duke
parents:
diff changeset
464 {
8873
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
465 current_offset += clear_avx_size(); // skip vzeroupper
0
a61af66fc99e Initial load
duke
parents:
diff changeset
466 current_offset += 11; // skip movq instruction + call opcode byte
a61af66fc99e Initial load
duke
parents:
diff changeset
467 return round_to(current_offset, alignment_required()) - current_offset;
a61af66fc99e Initial load
duke
parents:
diff changeset
468 }
a61af66fc99e Initial load
duke
parents:
diff changeset
469
a61af66fc99e Initial load
duke
parents:
diff changeset
470 // EMIT_RM()
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
471 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
472 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
473 cbuf.insts()->emit_int8(c);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
474 }
a61af66fc99e Initial load
duke
parents:
diff changeset
475
a61af66fc99e Initial load
duke
parents:
diff changeset
476 // EMIT_CC()
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
477 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
478 unsigned char c = (unsigned char) (f1 | f2);
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
479 cbuf.insts()->emit_int8(c);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
480 }
a61af66fc99e Initial load
duke
parents:
diff changeset
481
a61af66fc99e Initial load
duke
parents:
diff changeset
482 // EMIT_OPCODE()
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
483 void emit_opcode(CodeBuffer &cbuf, int code) {
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
484 cbuf.insts()->emit_int8((unsigned char) code);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
485 }
a61af66fc99e Initial load
duke
parents:
diff changeset
486
a61af66fc99e Initial load
duke
parents:
diff changeset
487 // EMIT_OPCODE() w/ relocation information
a61af66fc99e Initial load
duke
parents:
diff changeset
488 void emit_opcode(CodeBuffer &cbuf,
a61af66fc99e Initial load
duke
parents:
diff changeset
489 int code, relocInfo::relocType reloc, int offset, int format)
a61af66fc99e Initial load
duke
parents:
diff changeset
490 {
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
491 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
492 emit_opcode(cbuf, code);
a61af66fc99e Initial load
duke
parents:
diff changeset
493 }
a61af66fc99e Initial load
duke
parents:
diff changeset
494
a61af66fc99e Initial load
duke
parents:
diff changeset
495 // EMIT_D8()
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
496 void emit_d8(CodeBuffer &cbuf, int d8) {
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
497 cbuf.insts()->emit_int8((unsigned char) d8);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
498 }
a61af66fc99e Initial load
duke
parents:
diff changeset
499
a61af66fc99e Initial load
duke
parents:
diff changeset
500 // EMIT_D16()
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
501 void emit_d16(CodeBuffer &cbuf, int d16) {
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
502 cbuf.insts()->emit_int16(d16);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
503 }
a61af66fc99e Initial load
duke
parents:
diff changeset
504
a61af66fc99e Initial load
duke
parents:
diff changeset
505 // EMIT_D32()
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
506 void emit_d32(CodeBuffer &cbuf, int d32) {
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
507 cbuf.insts()->emit_int32(d32);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
508 }
a61af66fc99e Initial load
duke
parents:
diff changeset
509
a61af66fc99e Initial load
duke
parents:
diff changeset
510 // EMIT_D64()
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
511 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
512 cbuf.insts()->emit_int64(d64);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
513 }
a61af66fc99e Initial load
duke
parents:
diff changeset
514
a61af66fc99e Initial load
duke
parents:
diff changeset
515 // emit 32 bit value and construct relocation entry from relocInfo::relocType
a61af66fc99e Initial load
duke
parents:
diff changeset
516 void emit_d32_reloc(CodeBuffer& cbuf,
a61af66fc99e Initial load
duke
parents:
diff changeset
517 int d32,
a61af66fc99e Initial load
duke
parents:
diff changeset
518 relocInfo::relocType reloc,
a61af66fc99e Initial load
duke
parents:
diff changeset
519 int format)
a61af66fc99e Initial load
duke
parents:
diff changeset
520 {
a61af66fc99e Initial load
duke
parents:
diff changeset
521 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
522 cbuf.relocate(cbuf.insts_mark(), reloc, format);
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
523 cbuf.insts()->emit_int32(d32);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
524 }
a61af66fc99e Initial load
duke
parents:
diff changeset
525
a61af66fc99e Initial load
duke
parents:
diff changeset
526 // emit 32 bit value and construct relocation entry from RelocationHolder
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
527 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
528 #ifdef ASSERT
a61af66fc99e Initial load
duke
parents:
diff changeset
529 if (rspec.reloc()->type() == relocInfo::oop_type &&
a61af66fc99e Initial load
duke
parents:
diff changeset
530 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
6725
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 6614
diff changeset
531 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop");
989
148e5441d916 6863023: need non-perm oops in code cache for JSR 292
jrose
parents: 986
diff changeset
532 assert(oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code");
0
a61af66fc99e Initial load
duke
parents:
diff changeset
533 }
a61af66fc99e Initial load
duke
parents:
diff changeset
534 #endif
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
535 cbuf.relocate(cbuf.insts_mark(), rspec, format);
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
536 cbuf.insts()->emit_int32(d32);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
537 }
a61af66fc99e Initial load
duke
parents:
diff changeset
538
a61af66fc99e Initial load
duke
parents:
diff changeset
539 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
540 address next_ip = cbuf.insts_end() + 4;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
541 emit_d32_reloc(cbuf, (int) (addr - next_ip),
a61af66fc99e Initial load
duke
parents:
diff changeset
542 external_word_Relocation::spec(addr),
a61af66fc99e Initial load
duke
parents:
diff changeset
543 RELOC_DISP32);
a61af66fc99e Initial load
duke
parents:
diff changeset
544 }
a61af66fc99e Initial load
duke
parents:
diff changeset
545
a61af66fc99e Initial load
duke
parents:
diff changeset
546
a61af66fc99e Initial load
duke
parents:
diff changeset
547 // emit 64 bit value and construct relocation entry from relocInfo::relocType
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
548 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
549 cbuf.relocate(cbuf.insts_mark(), reloc, format);
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
550 cbuf.insts()->emit_int64(d64);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
551 }
a61af66fc99e Initial load
duke
parents:
diff changeset
552
a61af66fc99e Initial load
duke
parents:
diff changeset
553 // emit 64 bit value and construct relocation entry from RelocationHolder
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
554 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
555 #ifdef ASSERT
a61af66fc99e Initial load
duke
parents:
diff changeset
556 if (rspec.reloc()->type() == relocInfo::oop_type &&
a61af66fc99e Initial load
duke
parents:
diff changeset
557 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
6725
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 6614
diff changeset
558 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop");
989
148e5441d916 6863023: need non-perm oops in code cache for JSR 292
jrose
parents: 986
diff changeset
559 assert(oop(d64)->is_oop() && (ScavengeRootsInCode || !oop(d64)->is_scavengable()),
148e5441d916 6863023: need non-perm oops in code cache for JSR 292
jrose
parents: 986
diff changeset
560 "cannot embed scavengable oops in code");
0
a61af66fc99e Initial load
duke
parents:
diff changeset
561 }
a61af66fc99e Initial load
duke
parents:
diff changeset
562 #endif
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
563 cbuf.relocate(cbuf.insts_mark(), rspec, format);
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
564 cbuf.insts()->emit_int64(d64);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
565 }
a61af66fc99e Initial load
duke
parents:
diff changeset
566
a61af66fc99e Initial load
duke
parents:
diff changeset
567 // Access stack slot for load or store
a61af66fc99e Initial load
duke
parents:
diff changeset
568 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
a61af66fc99e Initial load
duke
parents:
diff changeset
569 {
a61af66fc99e Initial load
duke
parents:
diff changeset
570 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
a61af66fc99e Initial load
duke
parents:
diff changeset
571 if (-0x80 <= disp && disp < 0x80) {
a61af66fc99e Initial load
duke
parents:
diff changeset
572 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
a61af66fc99e Initial load
duke
parents:
diff changeset
573 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
a61af66fc99e Initial load
duke
parents:
diff changeset
574 emit_d8(cbuf, disp); // Displacement // R/M byte
a61af66fc99e Initial load
duke
parents:
diff changeset
575 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
576 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
a61af66fc99e Initial load
duke
parents:
diff changeset
577 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
a61af66fc99e Initial load
duke
parents:
diff changeset
578 emit_d32(cbuf, disp); // Displacement // R/M byte
a61af66fc99e Initial load
duke
parents:
diff changeset
579 }
a61af66fc99e Initial load
duke
parents:
diff changeset
580 }
a61af66fc99e Initial load
duke
parents:
diff changeset
581
a61af66fc99e Initial load
duke
parents:
diff changeset
582 // rRegI ereg, memory mem) %{ // emit_reg_mem
a61af66fc99e Initial load
duke
parents:
diff changeset
583 void encode_RegMem(CodeBuffer &cbuf,
a61af66fc99e Initial load
duke
parents:
diff changeset
584 int reg,
6725
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 6614
diff changeset
585 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc)
0
a61af66fc99e Initial load
duke
parents:
diff changeset
586 {
6725
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 6614
diff changeset
587 assert(disp_reloc == relocInfo::none, "cannot have disp");
0
a61af66fc99e Initial load
duke
parents:
diff changeset
588 int regenc = reg & 7;
a61af66fc99e Initial load
duke
parents:
diff changeset
589 int baseenc = base & 7;
a61af66fc99e Initial load
duke
parents:
diff changeset
590 int indexenc = index & 7;
a61af66fc99e Initial load
duke
parents:
diff changeset
591
a61af66fc99e Initial load
duke
parents:
diff changeset
592 // There is no index & no scale, use form without SIB byte
a61af66fc99e Initial load
duke
parents:
diff changeset
593 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
a61af66fc99e Initial load
duke
parents:
diff changeset
594 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
a61af66fc99e Initial load
duke
parents:
diff changeset
595 if (disp == 0 && base != RBP_enc && base != R13_enc) {
a61af66fc99e Initial load
duke
parents:
diff changeset
596 emit_rm(cbuf, 0x0, regenc, baseenc); // *
6725
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 6614
diff changeset
597 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
598 // If 8-bit displacement, mode 0x1
a61af66fc99e Initial load
duke
parents:
diff changeset
599 emit_rm(cbuf, 0x1, regenc, baseenc); // *
a61af66fc99e Initial load
duke
parents:
diff changeset
600 emit_d8(cbuf, disp);
a61af66fc99e Initial load
duke
parents:
diff changeset
601 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
602 // If 32-bit displacement
a61af66fc99e Initial load
duke
parents:
diff changeset
603 if (base == -1) { // Special flag for absolute address
a61af66fc99e Initial load
duke
parents:
diff changeset
604 emit_rm(cbuf, 0x0, regenc, 0x5); // *
6725
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 6614
diff changeset
605 if (disp_reloc != relocInfo::none) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
606 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
a61af66fc99e Initial load
duke
parents:
diff changeset
607 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
608 emit_d32(cbuf, disp);
a61af66fc99e Initial load
duke
parents:
diff changeset
609 }
a61af66fc99e Initial load
duke
parents:
diff changeset
610 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
611 // Normal base + offset
a61af66fc99e Initial load
duke
parents:
diff changeset
612 emit_rm(cbuf, 0x2, regenc, baseenc); // *
6725
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 6614
diff changeset
613 if (disp_reloc != relocInfo::none) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
614 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
a61af66fc99e Initial load
duke
parents:
diff changeset
615 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
616 emit_d32(cbuf, disp);
a61af66fc99e Initial load
duke
parents:
diff changeset
617 }
a61af66fc99e Initial load
duke
parents:
diff changeset
618 }
a61af66fc99e Initial load
duke
parents:
diff changeset
619 }
a61af66fc99e Initial load
duke
parents:
diff changeset
620 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
621 // Else, encode with the SIB byte
a61af66fc99e Initial load
duke
parents:
diff changeset
622 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
a61af66fc99e Initial load
duke
parents:
diff changeset
623 if (disp == 0 && base != RBP_enc && base != R13_enc) {
a61af66fc99e Initial load
duke
parents:
diff changeset
624 // If no displacement
a61af66fc99e Initial load
duke
parents:
diff changeset
625 emit_rm(cbuf, 0x0, regenc, 0x4); // *
a61af66fc99e Initial load
duke
parents:
diff changeset
626 emit_rm(cbuf, scale, indexenc, baseenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
627 } else {
6725
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 6614
diff changeset
628 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
629 // If 8-bit displacement, mode 0x1
a61af66fc99e Initial load
duke
parents:
diff changeset
630 emit_rm(cbuf, 0x1, regenc, 0x4); // *
a61af66fc99e Initial load
duke
parents:
diff changeset
631 emit_rm(cbuf, scale, indexenc, baseenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
632 emit_d8(cbuf, disp);
a61af66fc99e Initial load
duke
parents:
diff changeset
633 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
634 // If 32-bit displacement
a61af66fc99e Initial load
duke
parents:
diff changeset
635 if (base == 0x04 ) {
a61af66fc99e Initial load
duke
parents:
diff changeset
636 emit_rm(cbuf, 0x2, regenc, 0x4);
a61af66fc99e Initial load
duke
parents:
diff changeset
637 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
a61af66fc99e Initial load
duke
parents:
diff changeset
638 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
639 emit_rm(cbuf, 0x2, regenc, 0x4);
a61af66fc99e Initial load
duke
parents:
diff changeset
640 emit_rm(cbuf, scale, indexenc, baseenc); // *
a61af66fc99e Initial load
duke
parents:
diff changeset
641 }
6725
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 6614
diff changeset
642 if (disp_reloc != relocInfo::none) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
643 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
a61af66fc99e Initial load
duke
parents:
diff changeset
644 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
645 emit_d32(cbuf, disp);
a61af66fc99e Initial load
duke
parents:
diff changeset
646 }
a61af66fc99e Initial load
duke
parents:
diff changeset
647 }
a61af66fc99e Initial load
duke
parents:
diff changeset
648 }
a61af66fc99e Initial load
duke
parents:
diff changeset
649 }
a61af66fc99e Initial load
duke
parents:
diff changeset
650 }
a61af66fc99e Initial load
duke
parents:
diff changeset
651
3783
de6a837d75cf 7056380: VM crashes with SIGSEGV in compiled code
never
parents: 3738
diff changeset
652 // This could be in MacroAssembler but it's fairly C2 specific
de6a837d75cf 7056380: VM crashes with SIGSEGV in compiled code
never
parents: 3738
diff changeset
653 void emit_cmpfp_fixup(MacroAssembler& _masm) {
de6a837d75cf 7056380: VM crashes with SIGSEGV in compiled code
never
parents: 3738
diff changeset
654 Label exit;
de6a837d75cf 7056380: VM crashes with SIGSEGV in compiled code
never
parents: 3738
diff changeset
655 __ jccb(Assembler::noParity, exit);
de6a837d75cf 7056380: VM crashes with SIGSEGV in compiled code
never
parents: 3738
diff changeset
656 __ pushf();
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
657 //
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
658 // comiss/ucomiss instructions set ZF,PF,CF flags and
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
659 // zero OF,AF,SF for NaN values.
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
660 // Fixup flags by zeroing ZF,PF so that compare of NaN
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
661 // values returns 'less than' result (CF is set).
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
662 // Leave the rest of flags unchanged.
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
663 //
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
664 // 7 6 5 4 3 2 1 0
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
665 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
666 // 0 0 1 0 1 0 1 1 (0x2B)
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
667 //
3783
de6a837d75cf 7056380: VM crashes with SIGSEGV in compiled code
never
parents: 3738
diff changeset
668 __ andq(Address(rsp, 0), 0xffffff2b);
de6a837d75cf 7056380: VM crashes with SIGSEGV in compiled code
never
parents: 3738
diff changeset
669 __ popf();
de6a837d75cf 7056380: VM crashes with SIGSEGV in compiled code
never
parents: 3738
diff changeset
670 __ bind(exit);
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
671 }
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
672
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
673 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
674 Label done;
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
675 __ movl(dst, -1);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
676 __ jcc(Assembler::parity, done);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
677 __ jcc(Assembler::below, done);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
678 __ setb(Assembler::notEqual, dst);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
679 __ movzbl(dst, dst);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
680 __ bind(done);
3783
de6a837d75cf 7056380: VM crashes with SIGSEGV in compiled code
never
parents: 3738
diff changeset
681 }
de6a837d75cf 7056380: VM crashes with SIGSEGV in compiled code
never
parents: 3738
diff changeset
682
0
a61af66fc99e Initial load
duke
parents:
diff changeset
683
a61af66fc99e Initial load
duke
parents:
diff changeset
684 //=============================================================================
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
685 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
686
4114
6729bbc1fcd6 7003454: order constants in constant table by number of references in code
twisti
parents: 4047
diff changeset
687 int Compile::ConstantTable::calculate_table_base_offset() const {
6729bbc1fcd6 7003454: order constants in constant table by number of references in code
twisti
parents: 4047
diff changeset
688 return 0; // absolute addressing, no offset
6729bbc1fcd6 7003454: order constants in constant table by number of references in code
twisti
parents: 4047
diff changeset
689 }
6729bbc1fcd6 7003454: order constants in constant table by number of references in code
twisti
parents: 4047
diff changeset
690
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
691 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
692 // Empty encoding
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
693 }
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
694
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
695 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
696 return 0;
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
697 }
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
698
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
699 #ifndef PRODUCT
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
700 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
701 st->print("# MachConstantBaseNode (empty encoding)");
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
702 }
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
703 #endif
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
704
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
705
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
706 //=============================================================================
0
a61af66fc99e Initial load
duke
parents:
diff changeset
707 #ifndef PRODUCT
4947
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
708 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
709 Compile* C = ra_->C;
a61af66fc99e Initial load
duke
parents:
diff changeset
710
a61af66fc99e Initial load
duke
parents:
diff changeset
711 int framesize = C->frame_slots() << LogBytesPerInt;
a61af66fc99e Initial load
duke
parents:
diff changeset
712 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
4947
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
713 // Remove wordSize for return addr which is already pushed.
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
714 framesize -= wordSize;
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
715
0
a61af66fc99e Initial load
duke
parents:
diff changeset
716 if (C->need_stack_bang(framesize)) {
4947
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
717 framesize -= wordSize;
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
718 st->print("# stack bang");
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
719 st->print("\n\t");
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
720 st->print("pushq rbp\t# Save rbp");
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
721 if (framesize) {
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
722 st->print("\n\t");
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
723 st->print("subq rsp, #%d\t# Create frame",framesize);
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
724 }
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
725 } else {
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
726 st->print("subq rsp, #%d\t# Create frame",framesize);
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
727 st->print("\n\t");
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
728 framesize -= wordSize;
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
729 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
730 }
a61af66fc99e Initial load
duke
parents:
diff changeset
731
a61af66fc99e Initial load
duke
parents:
diff changeset
732 if (VerifyStackAtCalls) {
4947
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
733 st->print("\n\t");
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
734 framesize -= wordSize;
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
735 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
736 #ifdef ASSERT
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
737 st->print("\n\t");
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
738 st->print("# stack alignment check");
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
739 #endif
0
a61af66fc99e Initial load
duke
parents:
diff changeset
740 }
4947
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
741 st->cr();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
742 }
a61af66fc99e Initial load
duke
parents:
diff changeset
743 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
744
4947
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
745 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
746 Compile* C = ra_->C;
4947
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
747 MacroAssembler _masm(&cbuf);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
748
a61af66fc99e Initial load
duke
parents:
diff changeset
749 int framesize = C->frame_slots() << LogBytesPerInt;
4947
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
750
fd8114661503 7125136: SIGILL on linux amd64 in gc/ArrayJuggle/Juggle29
kvn
parents: 4777
diff changeset
751 __ verified_entry(framesize, C->need_stack_bang(framesize), false);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
752
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
753 C->set_frame_complete(cbuf.insts_size());
0
a61af66fc99e Initial load
duke
parents:
diff changeset
754
4114
6729bbc1fcd6 7003454: order constants in constant table by number of references in code
twisti
parents: 4047
diff changeset
755 if (C->has_mach_constant_base_node()) {
6729bbc1fcd6 7003454: order constants in constant table by number of references in code
twisti
parents: 4047
diff changeset
756 // NOTE: We set the table base offset here because users might be
6729bbc1fcd6 7003454: order constants in constant table by number of references in code
twisti
parents: 4047
diff changeset
757 // emitted before MachConstantBaseNode.
6729bbc1fcd6 7003454: order constants in constant table by number of references in code
twisti
parents: 4047
diff changeset
758 Compile::ConstantTable& constant_table = C->constant_table();
6729bbc1fcd6 7003454: order constants in constant table by number of references in code
twisti
parents: 4047
diff changeset
759 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
6729bbc1fcd6 7003454: order constants in constant table by number of references in code
twisti
parents: 4047
diff changeset
760 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
761 }
a61af66fc99e Initial load
duke
parents:
diff changeset
762
a61af66fc99e Initial load
duke
parents:
diff changeset
763 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
a61af66fc99e Initial load
duke
parents:
diff changeset
764 {
a61af66fc99e Initial load
duke
parents:
diff changeset
765 return MachNode::size(ra_); // too many variables; just compute it
a61af66fc99e Initial load
duke
parents:
diff changeset
766 // the hard way
a61af66fc99e Initial load
duke
parents:
diff changeset
767 }
a61af66fc99e Initial load
duke
parents:
diff changeset
768
a61af66fc99e Initial load
duke
parents:
diff changeset
769 int MachPrologNode::reloc() const
a61af66fc99e Initial load
duke
parents:
diff changeset
770 {
a61af66fc99e Initial load
duke
parents:
diff changeset
771 return 0; // a large enough number
a61af66fc99e Initial load
duke
parents:
diff changeset
772 }
a61af66fc99e Initial load
duke
parents:
diff changeset
773
a61af66fc99e Initial load
duke
parents:
diff changeset
774 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
775 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
776 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
a61af66fc99e Initial load
duke
parents:
diff changeset
777 {
a61af66fc99e Initial load
duke
parents:
diff changeset
778 Compile* C = ra_->C;
8873
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
779 if (C->max_vector_size() > 16) {
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
780 st->print("vzeroupper");
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
781 st->cr(); st->print("\t");
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
782 }
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
783
0
a61af66fc99e Initial load
duke
parents:
diff changeset
784 int framesize = C->frame_slots() << LogBytesPerInt;
a61af66fc99e Initial load
duke
parents:
diff changeset
785 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
a61af66fc99e Initial load
duke
parents:
diff changeset
786 // Remove word for return adr already pushed
a61af66fc99e Initial load
duke
parents:
diff changeset
787 // and RBP
a61af66fc99e Initial load
duke
parents:
diff changeset
788 framesize -= 2*wordSize;
a61af66fc99e Initial load
duke
parents:
diff changeset
789
a61af66fc99e Initial load
duke
parents:
diff changeset
790 if (framesize) {
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
791 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
792 st->print("\t");
a61af66fc99e Initial load
duke
parents:
diff changeset
793 }
a61af66fc99e Initial load
duke
parents:
diff changeset
794
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
795 st->print_cr("popq rbp");
0
a61af66fc99e Initial load
duke
parents:
diff changeset
796 if (do_polling() && C->is_method_compilation()) {
a61af66fc99e Initial load
duke
parents:
diff changeset
797 st->print("\t");
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
798 if (Assembler::is_polling_page_far()) {
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
799 st->print_cr("movq rscratch1, #polling_page_address\n\t"
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
800 "testl rax, [rscratch1]\t"
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
801 "# Safepoint: poll for GC");
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
802 } else {
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
803 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t"
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
804 "# Safepoint: poll for GC");
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
805 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
806 }
a61af66fc99e Initial load
duke
parents:
diff changeset
807 }
a61af66fc99e Initial load
duke
parents:
diff changeset
808 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
809
a61af66fc99e Initial load
duke
parents:
diff changeset
810 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
a61af66fc99e Initial load
duke
parents:
diff changeset
811 {
a61af66fc99e Initial load
duke
parents:
diff changeset
812 Compile* C = ra_->C;
8873
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
813 if (C->max_vector_size() > 16) {
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
814 // Clear upper bits of YMM registers when current compiled code uses
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
815 // wide vectors to avoid AVX <-> SSE transition penalty during call.
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
816 MacroAssembler _masm(&cbuf);
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
817 __ vzeroupper();
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
818 }
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
819
0
a61af66fc99e Initial load
duke
parents:
diff changeset
820 int framesize = C->frame_slots() << LogBytesPerInt;
a61af66fc99e Initial load
duke
parents:
diff changeset
821 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
a61af66fc99e Initial load
duke
parents:
diff changeset
822 // Remove word for return adr already pushed
a61af66fc99e Initial load
duke
parents:
diff changeset
823 // and RBP
a61af66fc99e Initial load
duke
parents:
diff changeset
824 framesize -= 2*wordSize;
a61af66fc99e Initial load
duke
parents:
diff changeset
825
a61af66fc99e Initial load
duke
parents:
diff changeset
826 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
a61af66fc99e Initial load
duke
parents:
diff changeset
827
a61af66fc99e Initial load
duke
parents:
diff changeset
828 if (framesize) {
a61af66fc99e Initial load
duke
parents:
diff changeset
829 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
830 if (framesize < 0x80) {
a61af66fc99e Initial load
duke
parents:
diff changeset
831 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
a61af66fc99e Initial load
duke
parents:
diff changeset
832 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
a61af66fc99e Initial load
duke
parents:
diff changeset
833 emit_d8(cbuf, framesize);
a61af66fc99e Initial load
duke
parents:
diff changeset
834 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
835 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
a61af66fc99e Initial load
duke
parents:
diff changeset
836 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
a61af66fc99e Initial load
duke
parents:
diff changeset
837 emit_d32(cbuf, framesize);
a61af66fc99e Initial load
duke
parents:
diff changeset
838 }
a61af66fc99e Initial load
duke
parents:
diff changeset
839 }
a61af66fc99e Initial load
duke
parents:
diff changeset
840
a61af66fc99e Initial load
duke
parents:
diff changeset
841 // popq rbp
a61af66fc99e Initial load
duke
parents:
diff changeset
842 emit_opcode(cbuf, 0x58 | RBP_enc);
a61af66fc99e Initial load
duke
parents:
diff changeset
843
a61af66fc99e Initial load
duke
parents:
diff changeset
844 if (do_polling() && C->is_method_compilation()) {
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
845 MacroAssembler _masm(&cbuf);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
846 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
847 if (Assembler::is_polling_page_far()) {
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
848 __ lea(rscratch1, polling_page);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
849 __ relocate(relocInfo::poll_return_type);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
850 __ testl(rax, Address(rscratch1, 0));
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
851 } else {
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
852 __ testl(rax, polling_page);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
853 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
854 }
a61af66fc99e Initial load
duke
parents:
diff changeset
855 }
a61af66fc99e Initial load
duke
parents:
diff changeset
856
a61af66fc99e Initial load
duke
parents:
diff changeset
857 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
a61af66fc99e Initial load
duke
parents:
diff changeset
858 {
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
859 return MachNode::size(ra_); // too many variables; just compute it
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
860 // the hard way
0
a61af66fc99e Initial load
duke
parents:
diff changeset
861 }
a61af66fc99e Initial load
duke
parents:
diff changeset
862
a61af66fc99e Initial load
duke
parents:
diff changeset
863 int MachEpilogNode::reloc() const
a61af66fc99e Initial load
duke
parents:
diff changeset
864 {
a61af66fc99e Initial load
duke
parents:
diff changeset
865 return 2; // a large enough number
a61af66fc99e Initial load
duke
parents:
diff changeset
866 }
a61af66fc99e Initial load
duke
parents:
diff changeset
867
a61af66fc99e Initial load
duke
parents:
diff changeset
868 const Pipeline* MachEpilogNode::pipeline() const
a61af66fc99e Initial load
duke
parents:
diff changeset
869 {
a61af66fc99e Initial load
duke
parents:
diff changeset
870 return MachNode::pipeline_class();
a61af66fc99e Initial load
duke
parents:
diff changeset
871 }
a61af66fc99e Initial load
duke
parents:
diff changeset
872
a61af66fc99e Initial load
duke
parents:
diff changeset
873 int MachEpilogNode::safepoint_offset() const
a61af66fc99e Initial load
duke
parents:
diff changeset
874 {
a61af66fc99e Initial load
duke
parents:
diff changeset
875 return 0;
a61af66fc99e Initial load
duke
parents:
diff changeset
876 }
a61af66fc99e Initial load
duke
parents:
diff changeset
877
a61af66fc99e Initial load
duke
parents:
diff changeset
878 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
879
a61af66fc99e Initial load
duke
parents:
diff changeset
880 enum RC {
a61af66fc99e Initial load
duke
parents:
diff changeset
881 rc_bad,
a61af66fc99e Initial load
duke
parents:
diff changeset
882 rc_int,
a61af66fc99e Initial load
duke
parents:
diff changeset
883 rc_float,
a61af66fc99e Initial load
duke
parents:
diff changeset
884 rc_stack
a61af66fc99e Initial load
duke
parents:
diff changeset
885 };
a61af66fc99e Initial load
duke
parents:
diff changeset
886
a61af66fc99e Initial load
duke
parents:
diff changeset
887 static enum RC rc_class(OptoReg::Name reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
888 {
a61af66fc99e Initial load
duke
parents:
diff changeset
889 if( !OptoReg::is_valid(reg) ) return rc_bad;
a61af66fc99e Initial load
duke
parents:
diff changeset
890
a61af66fc99e Initial load
duke
parents:
diff changeset
891 if (OptoReg::is_stack(reg)) return rc_stack;
a61af66fc99e Initial load
duke
parents:
diff changeset
892
a61af66fc99e Initial load
duke
parents:
diff changeset
893 VMReg r = OptoReg::as_VMReg(reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
894
a61af66fc99e Initial load
duke
parents:
diff changeset
895 if (r->is_Register()) return rc_int;
a61af66fc99e Initial load
duke
parents:
diff changeset
896
a61af66fc99e Initial load
duke
parents:
diff changeset
897 assert(r->is_XMMRegister(), "must be");
a61af66fc99e Initial load
duke
parents:
diff changeset
898 return rc_float;
a61af66fc99e Initial load
duke
parents:
diff changeset
899 }
a61af66fc99e Initial load
duke
parents:
diff changeset
900
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
901 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
902 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
903 int src_hi, int dst_hi, uint ireg, outputStream* st);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
904
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
905 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
906 int stack_offset, int reg, uint ireg, outputStream* st);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
907
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
908 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
909 int dst_offset, uint ireg, outputStream* st) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
910 if (cbuf) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
911 MacroAssembler _masm(cbuf);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
912 switch (ireg) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
913 case Op_VecS:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
914 __ movq(Address(rsp, -8), rax);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
915 __ movl(rax, Address(rsp, src_offset));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
916 __ movl(Address(rsp, dst_offset), rax);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
917 __ movq(rax, Address(rsp, -8));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
918 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
919 case Op_VecD:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
920 __ pushq(Address(rsp, src_offset));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
921 __ popq (Address(rsp, dst_offset));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
922 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
923 case Op_VecX:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
924 __ pushq(Address(rsp, src_offset));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
925 __ popq (Address(rsp, dst_offset));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
926 __ pushq(Address(rsp, src_offset+8));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
927 __ popq (Address(rsp, dst_offset+8));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
928 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
929 case Op_VecY:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
930 __ vmovdqu(Address(rsp, -32), xmm0);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
931 __ vmovdqu(xmm0, Address(rsp, src_offset));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
932 __ vmovdqu(Address(rsp, dst_offset), xmm0);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
933 __ vmovdqu(xmm0, Address(rsp, -32));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
934 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
935 default:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
936 ShouldNotReachHere();
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
937 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
938 #ifndef PRODUCT
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
939 } else {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
940 switch (ireg) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
941 case Op_VecS:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
942 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
943 "movl rax, [rsp + #%d]\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
944 "movl [rsp + #%d], rax\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
945 "movq rax, [rsp - #8]",
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
946 src_offset, dst_offset);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
947 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
948 case Op_VecD:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
949 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
950 "popq [rsp + #%d]",
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
951 src_offset, dst_offset);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
952 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
953 case Op_VecX:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
954 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
955 "popq [rsp + #%d]\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
956 "pushq [rsp + #%d]\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
957 "popq [rsp + #%d]",
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
958 src_offset, dst_offset, src_offset+8, dst_offset+8);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
959 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
960 case Op_VecY:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
961 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
962 "vmovdqu xmm0, [rsp + #%d]\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
963 "vmovdqu [rsp + #%d], xmm0\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
964 "vmovdqu xmm0, [rsp - #32]",
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
965 src_offset, dst_offset);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
966 break;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
967 default:
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
968 ShouldNotReachHere();
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
969 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
970 #endif
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
971 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
972 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
973
0
a61af66fc99e Initial load
duke
parents:
diff changeset
974 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
a61af66fc99e Initial load
duke
parents:
diff changeset
975 PhaseRegAlloc* ra_,
a61af66fc99e Initial load
duke
parents:
diff changeset
976 bool do_size,
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
977 outputStream* st) const {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
978 assert(cbuf != NULL || st != NULL, "sanity");
0
a61af66fc99e Initial load
duke
parents:
diff changeset
979 // Get registers to move
a61af66fc99e Initial load
duke
parents:
diff changeset
980 OptoReg::Name src_second = ra_->get_reg_second(in(1));
a61af66fc99e Initial load
duke
parents:
diff changeset
981 OptoReg::Name src_first = ra_->get_reg_first(in(1));
a61af66fc99e Initial load
duke
parents:
diff changeset
982 OptoReg::Name dst_second = ra_->get_reg_second(this);
a61af66fc99e Initial load
duke
parents:
diff changeset
983 OptoReg::Name dst_first = ra_->get_reg_first(this);
a61af66fc99e Initial load
duke
parents:
diff changeset
984
a61af66fc99e Initial load
duke
parents:
diff changeset
985 enum RC src_second_rc = rc_class(src_second);
a61af66fc99e Initial load
duke
parents:
diff changeset
986 enum RC src_first_rc = rc_class(src_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
987 enum RC dst_second_rc = rc_class(dst_second);
a61af66fc99e Initial load
duke
parents:
diff changeset
988 enum RC dst_first_rc = rc_class(dst_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
989
a61af66fc99e Initial load
duke
parents:
diff changeset
990 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
a61af66fc99e Initial load
duke
parents:
diff changeset
991 "must move at least 1 register" );
a61af66fc99e Initial load
duke
parents:
diff changeset
992
a61af66fc99e Initial load
duke
parents:
diff changeset
993 if (src_first == dst_first && src_second == dst_second) {
a61af66fc99e Initial load
duke
parents:
diff changeset
994 // Self copy, no move
a61af66fc99e Initial load
duke
parents:
diff changeset
995 return 0;
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
996 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
997 if (bottom_type()->isa_vect() != NULL) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
998 uint ireg = ideal_reg();
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
999 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1000 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1001 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1002 // mem -> mem
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1003 int src_offset = ra_->reg2offset(src_first);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1004 int dst_offset = ra_->reg2offset(dst_first);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1005 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1006 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1007 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1008 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1009 int stack_offset = ra_->reg2offset(dst_first);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1010 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1011 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1012 int stack_offset = ra_->reg2offset(src_first);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1013 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1014 } else {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1015 ShouldNotReachHere();
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1016 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1017 return 0;
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1018 }
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1019 if (src_first_rc == rc_stack) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1020 // mem ->
a61af66fc99e Initial load
duke
parents:
diff changeset
1021 if (dst_first_rc == rc_stack) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1022 // mem -> mem
a61af66fc99e Initial load
duke
parents:
diff changeset
1023 assert(src_second != dst_first, "overlap");
a61af66fc99e Initial load
duke
parents:
diff changeset
1024 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1025 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1026 // 64-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1027 int src_offset = ra_->reg2offset(src_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1028 int dst_offset = ra_->reg2offset(dst_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1029 if (cbuf) {
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1030 MacroAssembler _masm(cbuf);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1031 __ pushq(Address(rsp, src_offset));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1032 __ popq (Address(rsp, dst_offset));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1033 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1034 } else {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1035 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1036 "popq [rsp + #%d]",
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1037 src_offset, dst_offset);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1038 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1039 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1040 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1041 // 32-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1042 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1043 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1044 // No pushl/popl, so:
a61af66fc99e Initial load
duke
parents:
diff changeset
1045 int src_offset = ra_->reg2offset(src_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1046 int dst_offset = ra_->reg2offset(dst_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1047 if (cbuf) {
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1048 MacroAssembler _masm(cbuf);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1049 __ movq(Address(rsp, -8), rax);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1050 __ movl(rax, Address(rsp, src_offset));
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1051 __ movl(Address(rsp, dst_offset), rax);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1052 __ movq(rax, Address(rsp, -8));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1053 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1054 } else {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1055 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1056 "movl rax, [rsp + #%d]\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1057 "movl [rsp + #%d], rax\n\t"
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1058 "movq rax, [rsp - #8]",
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1059 src_offset, dst_offset);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1060 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1061 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1062 }
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1063 return 0;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1064 } else if (dst_first_rc == rc_int) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1065 // mem -> gpr
a61af66fc99e Initial load
duke
parents:
diff changeset
1066 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1067 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1068 // 64-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1069 int offset = ra_->reg2offset(src_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1070 if (cbuf) {
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1071 MacroAssembler _masm(cbuf);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1072 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1073 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1074 } else {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1075 st->print("movq %s, [rsp + #%d]\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1076 Matcher::regName[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1077 offset);
a61af66fc99e Initial load
duke
parents:
diff changeset
1078 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1079 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1080 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1081 // 32-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1082 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1083 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1084 int offset = ra_->reg2offset(src_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1085 if (cbuf) {
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1086 MacroAssembler _masm(cbuf);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1087 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1088 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1089 } else {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1090 st->print("movl %s, [rsp + #%d]\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1091 Matcher::regName[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1092 offset);
a61af66fc99e Initial load
duke
parents:
diff changeset
1093 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1094 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1095 }
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1096 return 0;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1097 } else if (dst_first_rc == rc_float) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1098 // mem-> xmm
a61af66fc99e Initial load
duke
parents:
diff changeset
1099 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1100 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1101 // 64-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1102 int offset = ra_->reg2offset(src_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1103 if (cbuf) {
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1104 MacroAssembler _masm(cbuf);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1105 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1106 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1107 } else {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1108 st->print("%s %s, [rsp + #%d]\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1109 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
a61af66fc99e Initial load
duke
parents:
diff changeset
1110 Matcher::regName[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1111 offset);
a61af66fc99e Initial load
duke
parents:
diff changeset
1112 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1113 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1114 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1115 // 32-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1116 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1117 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1118 int offset = ra_->reg2offset(src_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1119 if (cbuf) {
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1120 MacroAssembler _masm(cbuf);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1121 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1122 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1123 } else {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1124 st->print("movss %s, [rsp + #%d]\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1125 Matcher::regName[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1126 offset);
a61af66fc99e Initial load
duke
parents:
diff changeset
1127 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1128 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1129 }
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1130 return 0;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1131 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1132 } else if (src_first_rc == rc_int) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1133 // gpr ->
a61af66fc99e Initial load
duke
parents:
diff changeset
1134 if (dst_first_rc == rc_stack) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1135 // gpr -> mem
a61af66fc99e Initial load
duke
parents:
diff changeset
1136 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1137 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1138 // 64-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1139 int offset = ra_->reg2offset(dst_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1140 if (cbuf) {
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1141 MacroAssembler _masm(cbuf);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1142 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1143 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1144 } else {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1145 st->print("movq [rsp + #%d], %s\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1146 offset,
a61af66fc99e Initial load
duke
parents:
diff changeset
1147 Matcher::regName[src_first]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1148 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1149 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1150 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1151 // 32-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1152 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1153 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1154 int offset = ra_->reg2offset(dst_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1155 if (cbuf) {
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1156 MacroAssembler _masm(cbuf);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1157 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1158 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1159 } else {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1160 st->print("movl [rsp + #%d], %s\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1161 offset,
a61af66fc99e Initial load
duke
parents:
diff changeset
1162 Matcher::regName[src_first]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1163 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1164 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1165 }
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1166 return 0;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1167 } else if (dst_first_rc == rc_int) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1168 // gpr -> gpr
a61af66fc99e Initial load
duke
parents:
diff changeset
1169 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1170 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1171 // 64-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1172 if (cbuf) {
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1173 MacroAssembler _masm(cbuf);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1174 __ movq(as_Register(Matcher::_regEncode[dst_first]),
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1175 as_Register(Matcher::_regEncode[src_first]));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1176 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1177 } else {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1178 st->print("movq %s, %s\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1179 Matcher::regName[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1180 Matcher::regName[src_first]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1181 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1182 }
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1183 return 0;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1184 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1185 // 32-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1186 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1187 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1188 if (cbuf) {
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1189 MacroAssembler _masm(cbuf);
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1190 __ movl(as_Register(Matcher::_regEncode[dst_first]),
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1191 as_Register(Matcher::_regEncode[src_first]));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1192 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1193 } else {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1194 st->print("movl %s, %s\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1195 Matcher::regName[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1196 Matcher::regName[src_first]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1197 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1198 }
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1199 return 0;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1200 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1201 } else if (dst_first_rc == rc_float) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1202 // gpr -> xmm
a61af66fc99e Initial load
duke
parents:
diff changeset
1203 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1204 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1205 // 64-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1206 if (cbuf) {
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1207 MacroAssembler _masm(cbuf);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1208 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1209 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1210 } else {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1211 st->print("movdq %s, %s\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1212 Matcher::regName[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1213 Matcher::regName[src_first]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1214 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1215 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1216 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1217 // 32-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1218 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1219 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1220 if (cbuf) {
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1221 MacroAssembler _masm(cbuf);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1222 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1223 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1224 } else {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1225 st->print("movdl %s, %s\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1226 Matcher::regName[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1227 Matcher::regName[src_first]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1228 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1229 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1230 }
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1231 return 0;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1232 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1233 } else if (src_first_rc == rc_float) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1234 // xmm ->
a61af66fc99e Initial load
duke
parents:
diff changeset
1235 if (dst_first_rc == rc_stack) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1236 // xmm -> mem
a61af66fc99e Initial load
duke
parents:
diff changeset
1237 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1238 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1239 // 64-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1240 int offset = ra_->reg2offset(dst_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1241 if (cbuf) {
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1242 MacroAssembler _masm(cbuf);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1243 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1244 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1245 } else {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1246 st->print("movsd [rsp + #%d], %s\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1247 offset,
a61af66fc99e Initial load
duke
parents:
diff changeset
1248 Matcher::regName[src_first]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1249 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1250 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1251 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1252 // 32-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1253 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1254 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1255 int offset = ra_->reg2offset(dst_first);
a61af66fc99e Initial load
duke
parents:
diff changeset
1256 if (cbuf) {
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1257 MacroAssembler _masm(cbuf);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1258 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1259 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1260 } else {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1261 st->print("movss [rsp + #%d], %s\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1262 offset,
a61af66fc99e Initial load
duke
parents:
diff changeset
1263 Matcher::regName[src_first]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1264 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1265 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1266 }
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1267 return 0;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1268 } else if (dst_first_rc == rc_int) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1269 // xmm -> gpr
a61af66fc99e Initial load
duke
parents:
diff changeset
1270 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1271 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1272 // 64-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1273 if (cbuf) {
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1274 MacroAssembler _masm(cbuf);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1275 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1276 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1277 } else {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1278 st->print("movdq %s, %s\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1279 Matcher::regName[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1280 Matcher::regName[src_first]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1281 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1282 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1283 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1284 // 32-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1285 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1286 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1287 if (cbuf) {
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1288 MacroAssembler _masm(cbuf);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1289 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1290 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1291 } else {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1292 st->print("movdl %s, %s\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1293 Matcher::regName[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1294 Matcher::regName[src_first]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1295 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1296 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1297 }
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1298 return 0;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1299 } else if (dst_first_rc == rc_float) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1300 // xmm -> xmm
a61af66fc99e Initial load
duke
parents:
diff changeset
1301 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
a61af66fc99e Initial load
duke
parents:
diff changeset
1302 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1303 // 64-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1304 if (cbuf) {
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1305 MacroAssembler _masm(cbuf);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1306 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1307 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1308 } else {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1309 st->print("%s %s, %s\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1310 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
a61af66fc99e Initial load
duke
parents:
diff changeset
1311 Matcher::regName[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1312 Matcher::regName[src_first]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1313 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1314 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1315 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1316 // 32-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1317 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1318 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
a61af66fc99e Initial load
duke
parents:
diff changeset
1319 if (cbuf) {
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1320 MacroAssembler _masm(cbuf);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
1321 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1322 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1323 } else {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1324 st->print("%s %s, %s\t# spill",
a61af66fc99e Initial load
duke
parents:
diff changeset
1325 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
a61af66fc99e Initial load
duke
parents:
diff changeset
1326 Matcher::regName[dst_first],
a61af66fc99e Initial load
duke
parents:
diff changeset
1327 Matcher::regName[src_first]);
a61af66fc99e Initial load
duke
parents:
diff changeset
1328 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1329 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1330 }
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1331 return 0;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1332 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1333 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1334
a61af66fc99e Initial load
duke
parents:
diff changeset
1335 assert(0," foo ");
a61af66fc99e Initial load
duke
parents:
diff changeset
1336 Unimplemented();
a61af66fc99e Initial load
duke
parents:
diff changeset
1337 return 0;
a61af66fc99e Initial load
duke
parents:
diff changeset
1338 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1339
a61af66fc99e Initial load
duke
parents:
diff changeset
1340 #ifndef PRODUCT
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1341 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1342 implementation(NULL, ra_, false, st);
a61af66fc99e Initial load
duke
parents:
diff changeset
1343 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1344 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1345
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1346 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1347 implementation(&cbuf, ra_, false, NULL);
a61af66fc99e Initial load
duke
parents:
diff changeset
1348 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1349
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1350 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1351 return MachNode::size(ra_);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1352 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1353
a61af66fc99e Initial load
duke
parents:
diff changeset
1354 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
1355 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1356 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
a61af66fc99e Initial load
duke
parents:
diff changeset
1357 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1358 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
a61af66fc99e Initial load
duke
parents:
diff changeset
1359 int reg = ra_->get_reg_first(this);
a61af66fc99e Initial load
duke
parents:
diff changeset
1360 st->print("leaq %s, [rsp + #%d]\t# box lock",
a61af66fc99e Initial load
duke
parents:
diff changeset
1361 Matcher::regName[reg], offset);
a61af66fc99e Initial load
duke
parents:
diff changeset
1362 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1363 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1364
a61af66fc99e Initial load
duke
parents:
diff changeset
1365 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
a61af66fc99e Initial load
duke
parents:
diff changeset
1366 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1367 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
a61af66fc99e Initial load
duke
parents:
diff changeset
1368 int reg = ra_->get_encode(this);
a61af66fc99e Initial load
duke
parents:
diff changeset
1369 if (offset >= 0x80) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1370 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
a61af66fc99e Initial load
duke
parents:
diff changeset
1371 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
a61af66fc99e Initial load
duke
parents:
diff changeset
1372 emit_rm(cbuf, 0x2, reg & 7, 0x04);
a61af66fc99e Initial load
duke
parents:
diff changeset
1373 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
a61af66fc99e Initial load
duke
parents:
diff changeset
1374 emit_d32(cbuf, offset);
a61af66fc99e Initial load
duke
parents:
diff changeset
1375 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1376 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
a61af66fc99e Initial load
duke
parents:
diff changeset
1377 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
a61af66fc99e Initial load
duke
parents:
diff changeset
1378 emit_rm(cbuf, 0x1, reg & 7, 0x04);
a61af66fc99e Initial load
duke
parents:
diff changeset
1379 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
a61af66fc99e Initial load
duke
parents:
diff changeset
1380 emit_d8(cbuf, offset);
a61af66fc99e Initial load
duke
parents:
diff changeset
1381 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1382 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1383
a61af66fc99e Initial load
duke
parents:
diff changeset
1384 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
a61af66fc99e Initial load
duke
parents:
diff changeset
1385 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1386 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
a61af66fc99e Initial load
duke
parents:
diff changeset
1387 return (offset < 0x80) ? 5 : 8; // REX
a61af66fc99e Initial load
duke
parents:
diff changeset
1388 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1389
a61af66fc99e Initial load
duke
parents:
diff changeset
1390 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
1391 #ifndef PRODUCT
a61af66fc99e Initial load
duke
parents:
diff changeset
1392 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
a61af66fc99e Initial load
duke
parents:
diff changeset
1393 {
6848
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
1394 if (UseCompressedKlassPointers) {
1571
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1395 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
6848
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
1396 if (Universe::narrow_klass_shift() != 0) {
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
1397 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
1571
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1398 }
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1399 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
1400 } else {
1571
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1401 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1402 "# Inline cache check");
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
1403 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1404 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1571
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1405 st->print_cr("\tnop\t# nops to align entry point");
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1406 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1407 #endif
a61af66fc99e Initial load
duke
parents:
diff changeset
1408
a61af66fc99e Initial load
duke
parents:
diff changeset
1409 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
a61af66fc99e Initial load
duke
parents:
diff changeset
1410 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1411 MacroAssembler masm(&cbuf);
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
1412 uint insts_size = cbuf.insts_size();
6848
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
1413 if (UseCompressedKlassPointers) {
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
1414 masm.load_klass(rscratch1, j_rarg0);
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
1415 masm.cmpptr(rax, rscratch1);
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
1416 } else {
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
1417 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
1418 }
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1419
a61af66fc99e Initial load
duke
parents:
diff changeset
1420 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
a61af66fc99e Initial load
duke
parents:
diff changeset
1421
a61af66fc99e Initial load
duke
parents:
diff changeset
1422 /* WARNING these NOPs are critical so that verified entry point is properly
1571
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1423 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
1424 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1571
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1425 if (OptoBreakpoint) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1426 // Leave space for int3
1571
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1427 nops_cnt -= 1;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1428 }
1571
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1429 nops_cnt &= 0x3; // Do not add nops if code is aligned.
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1430 if (nops_cnt > 0)
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1431 masm.nop(nops_cnt);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1432 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1433
a61af66fc99e Initial load
duke
parents:
diff changeset
1434 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
a61af66fc99e Initial load
duke
parents:
diff changeset
1435 {
1571
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1436 return MachNode::size(ra_); // too many variables; just compute it
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
1437 // the hard way
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1438 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1439
a61af66fc99e Initial load
duke
parents:
diff changeset
1440
a61af66fc99e Initial load
duke
parents:
diff changeset
1441 //=============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
1442 uint size_exception_handler()
a61af66fc99e Initial load
duke
parents:
diff changeset
1443 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1444 // NativeCall instruction size is the same as NativeJump.
a61af66fc99e Initial load
duke
parents:
diff changeset
1445 // Note that this value is also credited (in output.cpp) to
a61af66fc99e Initial load
duke
parents:
diff changeset
1446 // the size of the code section.
a61af66fc99e Initial load
duke
parents:
diff changeset
1447 return NativeJump::instruction_size;
a61af66fc99e Initial load
duke
parents:
diff changeset
1448 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1449
a61af66fc99e Initial load
duke
parents:
diff changeset
1450 // Emit exception handler code.
a61af66fc99e Initial load
duke
parents:
diff changeset
1451 int emit_exception_handler(CodeBuffer& cbuf)
a61af66fc99e Initial load
duke
parents:
diff changeset
1452 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1453
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
1454 // Note that the code buffer's insts_mark is always relative to insts.
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1455 // That's why we must use the macroassembler to generate a handler.
a61af66fc99e Initial load
duke
parents:
diff changeset
1456 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
1457 address base =
a61af66fc99e Initial load
duke
parents:
diff changeset
1458 __ start_a_stub(size_exception_handler());
a61af66fc99e Initial load
duke
parents:
diff changeset
1459 if (base == NULL) return 0; // CodeBuffer::expand failed
a61af66fc99e Initial load
duke
parents:
diff changeset
1460 int offset = __ offset();
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
1461 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1462 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
a61af66fc99e Initial load
duke
parents:
diff changeset
1463 __ end_a_stub();
a61af66fc99e Initial load
duke
parents:
diff changeset
1464 return offset;
a61af66fc99e Initial load
duke
parents:
diff changeset
1465 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1466
a61af66fc99e Initial load
duke
parents:
diff changeset
1467 uint size_deopt_handler()
a61af66fc99e Initial load
duke
parents:
diff changeset
1468 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1469 // three 5 byte instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
1470 return 15;
a61af66fc99e Initial load
duke
parents:
diff changeset
1471 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1472
a61af66fc99e Initial load
duke
parents:
diff changeset
1473 // Emit deopt handler code.
a61af66fc99e Initial load
duke
parents:
diff changeset
1474 int emit_deopt_handler(CodeBuffer& cbuf)
a61af66fc99e Initial load
duke
parents:
diff changeset
1475 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1476
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
1477 // Note that the code buffer's insts_mark is always relative to insts.
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1478 // That's why we must use the macroassembler to generate a handler.
a61af66fc99e Initial load
duke
parents:
diff changeset
1479 MacroAssembler _masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
1480 address base =
a61af66fc99e Initial load
duke
parents:
diff changeset
1481 __ start_a_stub(size_deopt_handler());
a61af66fc99e Initial load
duke
parents:
diff changeset
1482 if (base == NULL) return 0; // CodeBuffer::expand failed
a61af66fc99e Initial load
duke
parents:
diff changeset
1483 int offset = __ offset();
a61af66fc99e Initial load
duke
parents:
diff changeset
1484 address the_pc = (address) __ pc();
a61af66fc99e Initial load
duke
parents:
diff changeset
1485 Label next;
a61af66fc99e Initial load
duke
parents:
diff changeset
1486 // push a "the_pc" on the stack without destroying any registers
a61af66fc99e Initial load
duke
parents:
diff changeset
1487 // as they all may be live.
a61af66fc99e Initial load
duke
parents:
diff changeset
1488
a61af66fc99e Initial load
duke
parents:
diff changeset
1489 // push address of "next"
a61af66fc99e Initial load
duke
parents:
diff changeset
1490 __ call(next, relocInfo::none); // reloc none is fine since it is a disp32
a61af66fc99e Initial load
duke
parents:
diff changeset
1491 __ bind(next);
a61af66fc99e Initial load
duke
parents:
diff changeset
1492 // adjust it so it matches "the_pc"
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
1493 __ subptr(Address(rsp, 0), __ offset() - offset);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1494 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
a61af66fc99e Initial load
duke
parents:
diff changeset
1495 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
a61af66fc99e Initial load
duke
parents:
diff changeset
1496 __ end_a_stub();
a61af66fc99e Initial load
duke
parents:
diff changeset
1497 return offset;
a61af66fc99e Initial load
duke
parents:
diff changeset
1498 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1499
a61af66fc99e Initial load
duke
parents:
diff changeset
1500 int Matcher::regnum_to_fpu_offset(int regnum)
a61af66fc99e Initial load
duke
parents:
diff changeset
1501 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1502 return regnum - 32; // The FP registers are in the second chunk
a61af66fc99e Initial load
duke
parents:
diff changeset
1503 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1504
a61af66fc99e Initial load
duke
parents:
diff changeset
1505 // This is UltraSparc specific, true just means we have fast l2f conversion
a61af66fc99e Initial load
duke
parents:
diff changeset
1506 const bool Matcher::convL2FSupported(void) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1507 return true;
a61af66fc99e Initial load
duke
parents:
diff changeset
1508 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1509
a61af66fc99e Initial load
duke
parents:
diff changeset
1510 // Is this branch offset short enough that a short branch can be used?
a61af66fc99e Initial load
duke
parents:
diff changeset
1511 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1512 // NOTE: If the platform does not provide any short branch variants, then
a61af66fc99e Initial load
duke
parents:
diff changeset
1513 // this method should return false for offset 0.
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
1514 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
1515 // The passed offset is relative to address of the branch.
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
1516 // On 86 a branch displacement is calculated relative to address
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
1517 // of a next instruction.
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
1518 offset -= br_size;
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
1519
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
1520 // the short version of jmpConUCF2 contains multiple branches,
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
1521 // making the reach slightly less
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
1522 if (rule == jmpConUCF2_rule)
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
1523 return (-126 <= offset && offset <= 125);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
1524 return (-128 <= offset && offset <= 127);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1525 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1526
a61af66fc99e Initial load
duke
parents:
diff changeset
1527 const bool Matcher::isSimpleConstant64(jlong value) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1528 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
a61af66fc99e Initial load
duke
parents:
diff changeset
1529 //return value == (int) value; // Cf. storeImmL and immL32.
a61af66fc99e Initial load
duke
parents:
diff changeset
1530
a61af66fc99e Initial load
duke
parents:
diff changeset
1531 // Probably always true, even if a temp register is required.
a61af66fc99e Initial load
duke
parents:
diff changeset
1532 return true;
a61af66fc99e Initial load
duke
parents:
diff changeset
1533 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1534
a61af66fc99e Initial load
duke
parents:
diff changeset
1535 // The ecx parameter to rep stosq for the ClearArray node is in words.
a61af66fc99e Initial load
duke
parents:
diff changeset
1536 const bool Matcher::init_array_count_is_in_bytes = false;
a61af66fc99e Initial load
duke
parents:
diff changeset
1537
a61af66fc99e Initial load
duke
parents:
diff changeset
1538 // Threshold size for cleararray.
a61af66fc99e Initial load
duke
parents:
diff changeset
1539 const int Matcher::init_array_short_size = 8 * BytesPerLong;
a61af66fc99e Initial load
duke
parents:
diff changeset
1540
4047
d8cb48376797 7097546: Optimize use of CMOVE instructions
kvn
parents: 3854
diff changeset
1541 // No additional cost for CMOVL.
d8cb48376797 7097546: Optimize use of CMOVE instructions
kvn
parents: 3854
diff changeset
1542 const int Matcher::long_cmove_cost() { return 0; }
d8cb48376797 7097546: Optimize use of CMOVE instructions
kvn
parents: 3854
diff changeset
1543
d8cb48376797 7097546: Optimize use of CMOVE instructions
kvn
parents: 3854
diff changeset
1544 // No CMOVF/CMOVD with SSE2
d8cb48376797 7097546: Optimize use of CMOVE instructions
kvn
parents: 3854
diff changeset
1545 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
d8cb48376797 7097546: Optimize use of CMOVE instructions
kvn
parents: 3854
diff changeset
1546
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1547 // Should the Matcher clone shifts on addressing modes, expecting them
a61af66fc99e Initial load
duke
parents:
diff changeset
1548 // to be subsumed into complex addressing expressions or compute them
a61af66fc99e Initial load
duke
parents:
diff changeset
1549 // into registers? True for Intel but false for most RISCs
a61af66fc99e Initial load
duke
parents:
diff changeset
1550 const bool Matcher::clone_shift_expressions = true;
a61af66fc99e Initial load
duke
parents:
diff changeset
1551
2401
7e88bdae86ec 7029017: Additional architecture support for c2 compiler
roland
parents: 2320
diff changeset
1552 // Do we need to mask the count passed to shift instructions or does
7e88bdae86ec 7029017: Additional architecture support for c2 compiler
roland
parents: 2320
diff changeset
1553 // the cpu only look at the lower 5/6 bits anyway?
7e88bdae86ec 7029017: Additional architecture support for c2 compiler
roland
parents: 2320
diff changeset
1554 const bool Matcher::need_masked_shift_count = false;
7e88bdae86ec 7029017: Additional architecture support for c2 compiler
roland
parents: 2320
diff changeset
1555
1575
3657cb01ffc5 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 1571
diff changeset
1556 bool Matcher::narrow_oop_use_complex_address() {
3657cb01ffc5 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 1571
diff changeset
1557 assert(UseCompressedOops, "only for compressed oops code");
3657cb01ffc5 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 1571
diff changeset
1558 return (LogMinObjAlignmentInBytes <= 3);
3657cb01ffc5 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 1571
diff changeset
1559 }
3657cb01ffc5 6954029: Improve implicit null check generation with compressed oops
kvn
parents: 1571
diff changeset
1560
6848
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
1561 bool Matcher::narrow_klass_use_complex_address() {
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
1562 assert(UseCompressedKlassPointers, "only for compressed klass code");
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
1563 return (LogKlassAlignmentInBytes <= 3);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
1564 }
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
1565
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1566 // Is it better to copy float constants, or load them directly from
a61af66fc99e Initial load
duke
parents:
diff changeset
1567 // memory? Intel can load a float constant from a direct address,
a61af66fc99e Initial load
duke
parents:
diff changeset
1568 // requiring no extra registers. Most RISCs will have to materialize
a61af66fc99e Initial load
duke
parents:
diff changeset
1569 // an address into a register first, so they would do better to copy
a61af66fc99e Initial load
duke
parents:
diff changeset
1570 // the constant from stack.
a61af66fc99e Initial load
duke
parents:
diff changeset
1571 const bool Matcher::rematerialize_float_constants = true; // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
1572
a61af66fc99e Initial load
duke
parents:
diff changeset
1573 // If CPU can load and store mis-aligned doubles directly then no
a61af66fc99e Initial load
duke
parents:
diff changeset
1574 // fixup is needed. Else we split the double into 2 integer pieces
a61af66fc99e Initial load
duke
parents:
diff changeset
1575 // and move it piece-by-piece. Only happens when passing doubles into
a61af66fc99e Initial load
duke
parents:
diff changeset
1576 // C code as the Java calling convention forces doubles to be aligned.
a61af66fc99e Initial load
duke
parents:
diff changeset
1577 const bool Matcher::misaligned_doubles_ok = true;
a61af66fc99e Initial load
duke
parents:
diff changeset
1578
a61af66fc99e Initial load
duke
parents:
diff changeset
1579 // No-op on amd64
a61af66fc99e Initial load
duke
parents:
diff changeset
1580 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
a61af66fc99e Initial load
duke
parents:
diff changeset
1581
a61af66fc99e Initial load
duke
parents:
diff changeset
1582 // Advertise here if the CPU requires explicit rounding operations to
a61af66fc99e Initial load
duke
parents:
diff changeset
1583 // implement the UseStrictFP mode.
a61af66fc99e Initial load
duke
parents:
diff changeset
1584 const bool Matcher::strict_fp_requires_explicit_rounding = true;
a61af66fc99e Initial load
duke
parents:
diff changeset
1585
1274
2883969d09e7 6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents: 1137
diff changeset
1586 // Are floats conerted to double when stored to stack during deoptimization?
2883969d09e7 6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents: 1137
diff changeset
1587 // On x64 it is stored without convertion so we can use normal access.
2883969d09e7 6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents: 1137
diff changeset
1588 bool Matcher::float_in_double() { return false; }
2883969d09e7 6910664: C2: java/util/Arrays/Sorting.java fails with DeoptimizeALot flag
kvn
parents: 1137
diff changeset
1589
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1590 // Do ints take an entire long register or just half?
a61af66fc99e Initial load
duke
parents:
diff changeset
1591 const bool Matcher::int_in_long = true;
a61af66fc99e Initial load
duke
parents:
diff changeset
1592
a61af66fc99e Initial load
duke
parents:
diff changeset
1593 // Return whether or not this register is ever used as an argument.
a61af66fc99e Initial load
duke
parents:
diff changeset
1594 // This function is used on startup to build the trampoline stubs in
a61af66fc99e Initial load
duke
parents:
diff changeset
1595 // generateOptoStub. Registers not mentioned will be killed by the VM
a61af66fc99e Initial load
duke
parents:
diff changeset
1596 // call in the trampoline, and arguments in those registers not be
a61af66fc99e Initial load
duke
parents:
diff changeset
1597 // available to the callee.
a61af66fc99e Initial load
duke
parents:
diff changeset
1598 bool Matcher::can_be_java_arg(int reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
1599 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1600 return
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1601 reg == RDI_num || reg == RDI_H_num ||
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1602 reg == RSI_num || reg == RSI_H_num ||
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1603 reg == RDX_num || reg == RDX_H_num ||
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1604 reg == RCX_num || reg == RCX_H_num ||
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1605 reg == R8_num || reg == R8_H_num ||
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1606 reg == R9_num || reg == R9_H_num ||
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1607 reg == R12_num || reg == R12_H_num ||
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1608 reg == XMM0_num || reg == XMM0b_num ||
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1609 reg == XMM1_num || reg == XMM1b_num ||
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1610 reg == XMM2_num || reg == XMM2b_num ||
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1611 reg == XMM3_num || reg == XMM3b_num ||
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1612 reg == XMM4_num || reg == XMM4b_num ||
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1613 reg == XMM5_num || reg == XMM5b_num ||
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1614 reg == XMM6_num || reg == XMM6b_num ||
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
1615 reg == XMM7_num || reg == XMM7b_num;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1616 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1617
a61af66fc99e Initial load
duke
parents:
diff changeset
1618 bool Matcher::is_spillable_arg(int reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
1619 {
a61af66fc99e Initial load
duke
parents:
diff changeset
1620 return can_be_java_arg(reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
1621 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1622
1914
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents: 1827
diff changeset
1623 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents: 1827
diff changeset
1624 // In 64 bit mode a code which use multiply when
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents: 1827
diff changeset
1625 // devisor is constant is faster than hardware
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents: 1827
diff changeset
1626 // DIV instruction (it uses MulHiL).
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents: 1827
diff changeset
1627 return false;
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents: 1827
diff changeset
1628 }
ae065c367d93 6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
kvn
parents: 1827
diff changeset
1629
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1630 // Register for DIVI projection of divmodI
a61af66fc99e Initial load
duke
parents:
diff changeset
1631 RegMask Matcher::divI_proj_mask() {
4121
db2e64ca2d5a 7090968: Allow adlc register class to depend on runtime conditions
roland
parents: 4114
diff changeset
1632 return INT_RAX_REG_mask();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1633 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1634
a61af66fc99e Initial load
duke
parents:
diff changeset
1635 // Register for MODI projection of divmodI
a61af66fc99e Initial load
duke
parents:
diff changeset
1636 RegMask Matcher::modI_proj_mask() {
4121
db2e64ca2d5a 7090968: Allow adlc register class to depend on runtime conditions
roland
parents: 4114
diff changeset
1637 return INT_RDX_REG_mask();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1638 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1639
a61af66fc99e Initial load
duke
parents:
diff changeset
1640 // Register for DIVL projection of divmodL
a61af66fc99e Initial load
duke
parents:
diff changeset
1641 RegMask Matcher::divL_proj_mask() {
4121
db2e64ca2d5a 7090968: Allow adlc register class to depend on runtime conditions
roland
parents: 4114
diff changeset
1642 return LONG_RAX_REG_mask();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1643 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1644
a61af66fc99e Initial load
duke
parents:
diff changeset
1645 // Register for MODL projection of divmodL
a61af66fc99e Initial load
duke
parents:
diff changeset
1646 RegMask Matcher::modL_proj_mask() {
4121
db2e64ca2d5a 7090968: Allow adlc register class to depend on runtime conditions
roland
parents: 4114
diff changeset
1647 return LONG_RDX_REG_mask();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1648 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1649
1137
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
1650 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
4121
db2e64ca2d5a 7090968: Allow adlc register class to depend on runtime conditions
roland
parents: 4114
diff changeset
1651 return PTR_RBP_REG_mask();
1137
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
1652 }
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
1653
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1654 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1655
a61af66fc99e Initial load
duke
parents:
diff changeset
1656 //----------ENCODING BLOCK-----------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
1657 // This block specifies the encoding classes used by the compiler to
a61af66fc99e Initial load
duke
parents:
diff changeset
1658 // output byte streams. Encoding classes are parameterized macros
a61af66fc99e Initial load
duke
parents:
diff changeset
1659 // used by Machine Instruction Nodes in order to generate the bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1660 // encoding of the instruction. Operands specify their base encoding
a61af66fc99e Initial load
duke
parents:
diff changeset
1661 // interface with the interface keyword. There are currently
a61af66fc99e Initial load
duke
parents:
diff changeset
1662 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
a61af66fc99e Initial load
duke
parents:
diff changeset
1663 // COND_INTER. REG_INTER causes an operand to generate a function
a61af66fc99e Initial load
duke
parents:
diff changeset
1664 // which returns its register number when queried. CONST_INTER causes
a61af66fc99e Initial load
duke
parents:
diff changeset
1665 // an operand to generate a function which returns the value of the
a61af66fc99e Initial load
duke
parents:
diff changeset
1666 // constant when queried. MEMORY_INTER causes an operand to generate
a61af66fc99e Initial load
duke
parents:
diff changeset
1667 // four functions which return the Base Register, the Index Register,
a61af66fc99e Initial load
duke
parents:
diff changeset
1668 // the Scale Value, and the Offset Value of the operand when queried.
a61af66fc99e Initial load
duke
parents:
diff changeset
1669 // COND_INTER causes an operand to generate six functions which return
a61af66fc99e Initial load
duke
parents:
diff changeset
1670 // the encoding code (ie - encoding bits for the instruction)
a61af66fc99e Initial load
duke
parents:
diff changeset
1671 // associated with each basic boolean condition for a conditional
a61af66fc99e Initial load
duke
parents:
diff changeset
1672 // instruction.
a61af66fc99e Initial load
duke
parents:
diff changeset
1673 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1674 // Instructions specify two basic values for encoding. Again, a
a61af66fc99e Initial load
duke
parents:
diff changeset
1675 // function is available to check if the constant displacement is an
a61af66fc99e Initial load
duke
parents:
diff changeset
1676 // oop. They use the ins_encode keyword to specify their encoding
a61af66fc99e Initial load
duke
parents:
diff changeset
1677 // classes (which must be a sequence of enc_class names, and their
a61af66fc99e Initial load
duke
parents:
diff changeset
1678 // parameters, specified in the encoding block), and they use the
a61af66fc99e Initial load
duke
parents:
diff changeset
1679 // opcode keyword to specify, in order, their primary, secondary, and
a61af66fc99e Initial load
duke
parents:
diff changeset
1680 // tertiary opcode. Only the opcode sections which a particular
a61af66fc99e Initial load
duke
parents:
diff changeset
1681 // instruction needs for encoding need to be specified.
a61af66fc99e Initial load
duke
parents:
diff changeset
1682 encode %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1683 // Build emit functions for each basic byte or larger field in the
a61af66fc99e Initial load
duke
parents:
diff changeset
1684 // intel encoding scheme (opcode, rm, sib, immediate), and call them
a61af66fc99e Initial load
duke
parents:
diff changeset
1685 // from C++ code in the enc_class source block. Emit functions will
a61af66fc99e Initial load
duke
parents:
diff changeset
1686 // live in the main source block for now. In future, we can
a61af66fc99e Initial load
duke
parents:
diff changeset
1687 // generalize this by adding a syntax that specifies the sizes of
a61af66fc99e Initial load
duke
parents:
diff changeset
1688 // fields in an order, so that the adlc can build the emit functions
a61af66fc99e Initial load
duke
parents:
diff changeset
1689 // automagically
a61af66fc99e Initial load
duke
parents:
diff changeset
1690
a61af66fc99e Initial load
duke
parents:
diff changeset
1691 // Emit primary opcode
a61af66fc99e Initial load
duke
parents:
diff changeset
1692 enc_class OpcP
a61af66fc99e Initial load
duke
parents:
diff changeset
1693 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1694 emit_opcode(cbuf, $primary);
a61af66fc99e Initial load
duke
parents:
diff changeset
1695 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1696
a61af66fc99e Initial load
duke
parents:
diff changeset
1697 // Emit secondary opcode
a61af66fc99e Initial load
duke
parents:
diff changeset
1698 enc_class OpcS
a61af66fc99e Initial load
duke
parents:
diff changeset
1699 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1700 emit_opcode(cbuf, $secondary);
a61af66fc99e Initial load
duke
parents:
diff changeset
1701 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1702
a61af66fc99e Initial load
duke
parents:
diff changeset
1703 // Emit tertiary opcode
a61af66fc99e Initial load
duke
parents:
diff changeset
1704 enc_class OpcT
a61af66fc99e Initial load
duke
parents:
diff changeset
1705 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1706 emit_opcode(cbuf, $tertiary);
a61af66fc99e Initial load
duke
parents:
diff changeset
1707 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1708
a61af66fc99e Initial load
duke
parents:
diff changeset
1709 // Emit opcode directly
a61af66fc99e Initial load
duke
parents:
diff changeset
1710 enc_class Opcode(immI d8)
a61af66fc99e Initial load
duke
parents:
diff changeset
1711 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1712 emit_opcode(cbuf, $d8$$constant);
a61af66fc99e Initial load
duke
parents:
diff changeset
1713 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1714
a61af66fc99e Initial load
duke
parents:
diff changeset
1715 // Emit size prefix
a61af66fc99e Initial load
duke
parents:
diff changeset
1716 enc_class SizePrefix
a61af66fc99e Initial load
duke
parents:
diff changeset
1717 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1718 emit_opcode(cbuf, 0x66);
a61af66fc99e Initial load
duke
parents:
diff changeset
1719 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1720
a61af66fc99e Initial load
duke
parents:
diff changeset
1721 enc_class reg(rRegI reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
1722 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1723 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
1724 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1725
a61af66fc99e Initial load
duke
parents:
diff changeset
1726 enc_class reg_reg(rRegI dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
1727 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1728 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
1729 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1730
a61af66fc99e Initial load
duke
parents:
diff changeset
1731 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
1732 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1733 emit_opcode(cbuf, $opcode$$constant);
a61af66fc99e Initial load
duke
parents:
diff changeset
1734 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
1735 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1736
a61af66fc99e Initial load
duke
parents:
diff changeset
1737 enc_class cdql_enc(no_rax_rdx_RegI div)
a61af66fc99e Initial load
duke
parents:
diff changeset
1738 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1739 // Full implementation of Java idiv and irem; checks for
a61af66fc99e Initial load
duke
parents:
diff changeset
1740 // special case as described in JVM spec., p.243 & p.271.
a61af66fc99e Initial load
duke
parents:
diff changeset
1741 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1742 // normal case special case
a61af66fc99e Initial load
duke
parents:
diff changeset
1743 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1744 // input : rax: dividend min_int
a61af66fc99e Initial load
duke
parents:
diff changeset
1745 // reg: divisor -1
a61af66fc99e Initial load
duke
parents:
diff changeset
1746 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1747 // output: rax: quotient (= rax idiv reg) min_int
a61af66fc99e Initial load
duke
parents:
diff changeset
1748 // rdx: remainder (= rax irem reg) 0
a61af66fc99e Initial load
duke
parents:
diff changeset
1749 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1750 // Code sequnce:
a61af66fc99e Initial load
duke
parents:
diff changeset
1751 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1752 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
a61af66fc99e Initial load
duke
parents:
diff changeset
1753 // 5: 75 07/08 jne e <normal>
a61af66fc99e Initial load
duke
parents:
diff changeset
1754 // 7: 33 d2 xor %edx,%edx
a61af66fc99e Initial load
duke
parents:
diff changeset
1755 // [div >= 8 -> offset + 1]
a61af66fc99e Initial load
duke
parents:
diff changeset
1756 // [REX_B]
a61af66fc99e Initial load
duke
parents:
diff changeset
1757 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
a61af66fc99e Initial load
duke
parents:
diff changeset
1758 // c: 74 03/04 je 11 <done>
a61af66fc99e Initial load
duke
parents:
diff changeset
1759 // 000000000000000e <normal>:
a61af66fc99e Initial load
duke
parents:
diff changeset
1760 // e: 99 cltd
a61af66fc99e Initial load
duke
parents:
diff changeset
1761 // [div >= 8 -> offset + 1]
a61af66fc99e Initial load
duke
parents:
diff changeset
1762 // [REX_B]
a61af66fc99e Initial load
duke
parents:
diff changeset
1763 // f: f7 f9 idiv $div
a61af66fc99e Initial load
duke
parents:
diff changeset
1764 // 0000000000000011 <done>:
a61af66fc99e Initial load
duke
parents:
diff changeset
1765
a61af66fc99e Initial load
duke
parents:
diff changeset
1766 // cmp $0x80000000,%eax
a61af66fc99e Initial load
duke
parents:
diff changeset
1767 emit_opcode(cbuf, 0x3d);
a61af66fc99e Initial load
duke
parents:
diff changeset
1768 emit_d8(cbuf, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
1769 emit_d8(cbuf, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
1770 emit_d8(cbuf, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
1771 emit_d8(cbuf, 0x80);
a61af66fc99e Initial load
duke
parents:
diff changeset
1772
a61af66fc99e Initial load
duke
parents:
diff changeset
1773 // jne e <normal>
a61af66fc99e Initial load
duke
parents:
diff changeset
1774 emit_opcode(cbuf, 0x75);
a61af66fc99e Initial load
duke
parents:
diff changeset
1775 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
a61af66fc99e Initial load
duke
parents:
diff changeset
1776
a61af66fc99e Initial load
duke
parents:
diff changeset
1777 // xor %edx,%edx
a61af66fc99e Initial load
duke
parents:
diff changeset
1778 emit_opcode(cbuf, 0x33);
a61af66fc99e Initial load
duke
parents:
diff changeset
1779 emit_d8(cbuf, 0xD2);
a61af66fc99e Initial load
duke
parents:
diff changeset
1780
a61af66fc99e Initial load
duke
parents:
diff changeset
1781 // cmp $0xffffffffffffffff,%ecx
a61af66fc99e Initial load
duke
parents:
diff changeset
1782 if ($div$$reg >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1783 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
1784 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1785 emit_opcode(cbuf, 0x83);
a61af66fc99e Initial load
duke
parents:
diff changeset
1786 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
1787 emit_d8(cbuf, 0xFF);
a61af66fc99e Initial load
duke
parents:
diff changeset
1788
a61af66fc99e Initial load
duke
parents:
diff changeset
1789 // je 11 <done>
a61af66fc99e Initial load
duke
parents:
diff changeset
1790 emit_opcode(cbuf, 0x74);
a61af66fc99e Initial load
duke
parents:
diff changeset
1791 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
a61af66fc99e Initial load
duke
parents:
diff changeset
1792
a61af66fc99e Initial load
duke
parents:
diff changeset
1793 // <normal>
a61af66fc99e Initial load
duke
parents:
diff changeset
1794 // cltd
a61af66fc99e Initial load
duke
parents:
diff changeset
1795 emit_opcode(cbuf, 0x99);
a61af66fc99e Initial load
duke
parents:
diff changeset
1796
a61af66fc99e Initial load
duke
parents:
diff changeset
1797 // idivl (note: must be emitted by the user of this rule)
a61af66fc99e Initial load
duke
parents:
diff changeset
1798 // <done>
a61af66fc99e Initial load
duke
parents:
diff changeset
1799 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1800
a61af66fc99e Initial load
duke
parents:
diff changeset
1801 enc_class cdqq_enc(no_rax_rdx_RegL div)
a61af66fc99e Initial load
duke
parents:
diff changeset
1802 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1803 // Full implementation of Java ldiv and lrem; checks for
a61af66fc99e Initial load
duke
parents:
diff changeset
1804 // special case as described in JVM spec., p.243 & p.271.
a61af66fc99e Initial load
duke
parents:
diff changeset
1805 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1806 // normal case special case
a61af66fc99e Initial load
duke
parents:
diff changeset
1807 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1808 // input : rax: dividend min_long
a61af66fc99e Initial load
duke
parents:
diff changeset
1809 // reg: divisor -1
a61af66fc99e Initial load
duke
parents:
diff changeset
1810 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1811 // output: rax: quotient (= rax idiv reg) min_long
a61af66fc99e Initial load
duke
parents:
diff changeset
1812 // rdx: remainder (= rax irem reg) 0
a61af66fc99e Initial load
duke
parents:
diff changeset
1813 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1814 // Code sequnce:
a61af66fc99e Initial load
duke
parents:
diff changeset
1815 //
a61af66fc99e Initial load
duke
parents:
diff changeset
1816 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
a61af66fc99e Initial load
duke
parents:
diff changeset
1817 // 7: 00 00 80
a61af66fc99e Initial load
duke
parents:
diff changeset
1818 // a: 48 39 d0 cmp %rdx,%rax
a61af66fc99e Initial load
duke
parents:
diff changeset
1819 // d: 75 08 jne 17 <normal>
a61af66fc99e Initial load
duke
parents:
diff changeset
1820 // f: 33 d2 xor %edx,%edx
a61af66fc99e Initial load
duke
parents:
diff changeset
1821 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
a61af66fc99e Initial load
duke
parents:
diff changeset
1822 // 15: 74 05 je 1c <done>
a61af66fc99e Initial load
duke
parents:
diff changeset
1823 // 0000000000000017 <normal>:
a61af66fc99e Initial load
duke
parents:
diff changeset
1824 // 17: 48 99 cqto
a61af66fc99e Initial load
duke
parents:
diff changeset
1825 // 19: 48 f7 f9 idiv $div
a61af66fc99e Initial load
duke
parents:
diff changeset
1826 // 000000000000001c <done>:
a61af66fc99e Initial load
duke
parents:
diff changeset
1827
a61af66fc99e Initial load
duke
parents:
diff changeset
1828 // mov $0x8000000000000000,%rdx
a61af66fc99e Initial load
duke
parents:
diff changeset
1829 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
1830 emit_opcode(cbuf, 0xBA);
a61af66fc99e Initial load
duke
parents:
diff changeset
1831 emit_d8(cbuf, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
1832 emit_d8(cbuf, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
1833 emit_d8(cbuf, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
1834 emit_d8(cbuf, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
1835 emit_d8(cbuf, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
1836 emit_d8(cbuf, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
1837 emit_d8(cbuf, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
1838 emit_d8(cbuf, 0x80);
a61af66fc99e Initial load
duke
parents:
diff changeset
1839
a61af66fc99e Initial load
duke
parents:
diff changeset
1840 // cmp %rdx,%rax
a61af66fc99e Initial load
duke
parents:
diff changeset
1841 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
1842 emit_opcode(cbuf, 0x39);
a61af66fc99e Initial load
duke
parents:
diff changeset
1843 emit_d8(cbuf, 0xD0);
a61af66fc99e Initial load
duke
parents:
diff changeset
1844
a61af66fc99e Initial load
duke
parents:
diff changeset
1845 // jne 17 <normal>
a61af66fc99e Initial load
duke
parents:
diff changeset
1846 emit_opcode(cbuf, 0x75);
a61af66fc99e Initial load
duke
parents:
diff changeset
1847 emit_d8(cbuf, 0x08);
a61af66fc99e Initial load
duke
parents:
diff changeset
1848
a61af66fc99e Initial load
duke
parents:
diff changeset
1849 // xor %edx,%edx
a61af66fc99e Initial load
duke
parents:
diff changeset
1850 emit_opcode(cbuf, 0x33);
a61af66fc99e Initial load
duke
parents:
diff changeset
1851 emit_d8(cbuf, 0xD2);
a61af66fc99e Initial load
duke
parents:
diff changeset
1852
a61af66fc99e Initial load
duke
parents:
diff changeset
1853 // cmp $0xffffffffffffffff,$div
a61af66fc99e Initial load
duke
parents:
diff changeset
1854 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
1855 emit_opcode(cbuf, 0x83);
a61af66fc99e Initial load
duke
parents:
diff changeset
1856 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
1857 emit_d8(cbuf, 0xFF);
a61af66fc99e Initial load
duke
parents:
diff changeset
1858
a61af66fc99e Initial load
duke
parents:
diff changeset
1859 // je 1e <done>
a61af66fc99e Initial load
duke
parents:
diff changeset
1860 emit_opcode(cbuf, 0x74);
a61af66fc99e Initial load
duke
parents:
diff changeset
1861 emit_d8(cbuf, 0x05);
a61af66fc99e Initial load
duke
parents:
diff changeset
1862
a61af66fc99e Initial load
duke
parents:
diff changeset
1863 // <normal>
a61af66fc99e Initial load
duke
parents:
diff changeset
1864 // cqto
a61af66fc99e Initial load
duke
parents:
diff changeset
1865 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
1866 emit_opcode(cbuf, 0x99);
a61af66fc99e Initial load
duke
parents:
diff changeset
1867
a61af66fc99e Initial load
duke
parents:
diff changeset
1868 // idivq (note: must be emitted by the user of this rule)
a61af66fc99e Initial load
duke
parents:
diff changeset
1869 // <done>
a61af66fc99e Initial load
duke
parents:
diff changeset
1870 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1871
a61af66fc99e Initial load
duke
parents:
diff changeset
1872 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
a61af66fc99e Initial load
duke
parents:
diff changeset
1873 enc_class OpcSE(immI imm)
a61af66fc99e Initial load
duke
parents:
diff changeset
1874 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1875 // Emit primary opcode and set sign-extend bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1876 // Check for 8-bit immediate, and set sign extend bit in opcode
a61af66fc99e Initial load
duke
parents:
diff changeset
1877 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1878 emit_opcode(cbuf, $primary | 0x02);
a61af66fc99e Initial load
duke
parents:
diff changeset
1879 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1880 // 32-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
1881 emit_opcode(cbuf, $primary);
a61af66fc99e Initial load
duke
parents:
diff changeset
1882 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1883 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1884
a61af66fc99e Initial load
duke
parents:
diff changeset
1885 enc_class OpcSErm(rRegI dst, immI imm)
a61af66fc99e Initial load
duke
parents:
diff changeset
1886 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1887 // OpcSEr/m
a61af66fc99e Initial load
duke
parents:
diff changeset
1888 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
1889 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1890 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
1891 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
1892 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1893 // Emit primary opcode and set sign-extend bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1894 // Check for 8-bit immediate, and set sign extend bit in opcode
a61af66fc99e Initial load
duke
parents:
diff changeset
1895 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1896 emit_opcode(cbuf, $primary | 0x02);
a61af66fc99e Initial load
duke
parents:
diff changeset
1897 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1898 // 32-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
1899 emit_opcode(cbuf, $primary);
a61af66fc99e Initial load
duke
parents:
diff changeset
1900 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1901 // Emit r/m byte with secondary opcode, after primary opcode.
a61af66fc99e Initial load
duke
parents:
diff changeset
1902 emit_rm(cbuf, 0x3, $secondary, dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
1903 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1904
a61af66fc99e Initial load
duke
parents:
diff changeset
1905 enc_class OpcSErm_wide(rRegL dst, immI imm)
a61af66fc99e Initial load
duke
parents:
diff changeset
1906 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1907 // OpcSEr/m
a61af66fc99e Initial load
duke
parents:
diff changeset
1908 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
1909 if (dstenc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1910 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
1911 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1912 emit_opcode(cbuf, Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
1913 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
1914 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1915 // Emit primary opcode and set sign-extend bit
a61af66fc99e Initial load
duke
parents:
diff changeset
1916 // Check for 8-bit immediate, and set sign extend bit in opcode
a61af66fc99e Initial load
duke
parents:
diff changeset
1917 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1918 emit_opcode(cbuf, $primary | 0x02);
a61af66fc99e Initial load
duke
parents:
diff changeset
1919 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1920 // 32-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
1921 emit_opcode(cbuf, $primary);
a61af66fc99e Initial load
duke
parents:
diff changeset
1922 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1923 // Emit r/m byte with secondary opcode, after primary opcode.
a61af66fc99e Initial load
duke
parents:
diff changeset
1924 emit_rm(cbuf, 0x3, $secondary, dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
1925 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1926
a61af66fc99e Initial load
duke
parents:
diff changeset
1927 enc_class Con8or32(immI imm)
a61af66fc99e Initial load
duke
parents:
diff changeset
1928 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1929 // Check for 8-bit immediate, and set sign extend bit in opcode
a61af66fc99e Initial load
duke
parents:
diff changeset
1930 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
a61af66fc99e Initial load
duke
parents:
diff changeset
1931 $$$emit8$imm$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
1932 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
1933 // 32-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
1934 $$$emit32$imm$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
1935 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1936 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1937
a61af66fc99e Initial load
duke
parents:
diff changeset
1938 enc_class opc2_reg(rRegI dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
1939 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1940 // BSWAP
a61af66fc99e Initial load
duke
parents:
diff changeset
1941 emit_cc(cbuf, $secondary, $dst$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
1942 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1943
a61af66fc99e Initial load
duke
parents:
diff changeset
1944 enc_class opc3_reg(rRegI dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
1945 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1946 // BSWAP
a61af66fc99e Initial load
duke
parents:
diff changeset
1947 emit_cc(cbuf, $tertiary, $dst$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
1948 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1949
a61af66fc99e Initial load
duke
parents:
diff changeset
1950 enc_class reg_opc(rRegI div)
a61af66fc99e Initial load
duke
parents:
diff changeset
1951 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1952 // INC, DEC, IDIV, IMOD, JMP indirect, ...
a61af66fc99e Initial load
duke
parents:
diff changeset
1953 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
1954 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1955
a61af66fc99e Initial load
duke
parents:
diff changeset
1956 enc_class enc_cmov(cmpOp cop)
a61af66fc99e Initial load
duke
parents:
diff changeset
1957 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1958 // CMOV
a61af66fc99e Initial load
duke
parents:
diff changeset
1959 $$$emit8$primary;
a61af66fc99e Initial load
duke
parents:
diff changeset
1960 emit_cc(cbuf, $secondary, $cop$$cmpcode);
a61af66fc99e Initial load
duke
parents:
diff changeset
1961 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1962
a61af66fc99e Initial load
duke
parents:
diff changeset
1963 enc_class enc_PartialSubtypeCheck()
a61af66fc99e Initial load
duke
parents:
diff changeset
1964 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
1965 Register Rrdi = as_Register(RDI_enc); // result register
a61af66fc99e Initial load
duke
parents:
diff changeset
1966 Register Rrax = as_Register(RAX_enc); // super class
a61af66fc99e Initial load
duke
parents:
diff changeset
1967 Register Rrcx = as_Register(RCX_enc); // killed
a61af66fc99e Initial load
duke
parents:
diff changeset
1968 Register Rrsi = as_Register(RSI_enc); // sub class
644
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 643
diff changeset
1969 Label miss;
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 643
diff changeset
1970 const bool set_cond_codes = true;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1971
a61af66fc99e Initial load
duke
parents:
diff changeset
1972 MacroAssembler _masm(&cbuf);
644
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 643
diff changeset
1973 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 643
diff changeset
1974 NULL, &miss,
c517646eef23 6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents: 643
diff changeset
1975 /*set_cond_codes:*/ true);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1976 if ($primary) {
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
1977 __ xorptr(Rrdi, Rrdi);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
1978 }
a61af66fc99e Initial load
duke
parents:
diff changeset
1979 __ bind(miss);
a61af66fc99e Initial load
duke
parents:
diff changeset
1980 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
1981
8873
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
1982 enc_class clear_avx %{
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
1983 debug_only(int off0 = cbuf.insts_size());
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
1984 if (ra_->C->max_vector_size() > 16) {
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
1985 // Clear upper bits of YMM registers when current compiled code uses
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
1986 // wide vectors to avoid AVX <-> SSE transition penalty during call.
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
1987 MacroAssembler _masm(&cbuf);
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
1988 __ vzeroupper();
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
1989 }
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
1990 debug_only(int off1 = cbuf.insts_size());
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
1991 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
1992 %}
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
1993
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
1994 enc_class Java_To_Runtime(method meth) %{
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
1995 // No relocation needed
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
1996 MacroAssembler _masm(&cbuf);
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
1997 __ mov64(r10, (int64_t) $meth$$method);
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
1998 __ call(r10);
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
1999 %}
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
2000
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2001 enc_class Java_To_Interpreter(method meth)
a61af66fc99e Initial load
duke
parents:
diff changeset
2002 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2003 // CALL Java_To_Interpreter
a61af66fc99e Initial load
duke
parents:
diff changeset
2004 // This is the instruction starting address for relocation info.
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2005 cbuf.set_insts_mark();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2006 $$$emit8$primary;
a61af66fc99e Initial load
duke
parents:
diff changeset
2007 // CALL directly to the runtime
a61af66fc99e Initial load
duke
parents:
diff changeset
2008 emit_d32_reloc(cbuf,
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2009 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2010 runtime_call_Relocation::spec(),
a61af66fc99e Initial load
duke
parents:
diff changeset
2011 RELOC_DISP32);
a61af66fc99e Initial load
duke
parents:
diff changeset
2012 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2013
a61af66fc99e Initial load
duke
parents:
diff changeset
2014 enc_class Java_Static_Call(method meth)
a61af66fc99e Initial load
duke
parents:
diff changeset
2015 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2016 // JAVA STATIC CALL
a61af66fc99e Initial load
duke
parents:
diff changeset
2017 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
a61af66fc99e Initial load
duke
parents:
diff changeset
2018 // determine who we intended to call.
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2019 cbuf.set_insts_mark();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2020 $$$emit8$primary;
a61af66fc99e Initial load
duke
parents:
diff changeset
2021
a61af66fc99e Initial load
duke
parents:
diff changeset
2022 if (!_method) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2023 emit_d32_reloc(cbuf,
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2024 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2025 runtime_call_Relocation::spec(),
a61af66fc99e Initial load
duke
parents:
diff changeset
2026 RELOC_DISP32);
a61af66fc99e Initial load
duke
parents:
diff changeset
2027 } else if (_optimized_virtual) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2028 emit_d32_reloc(cbuf,
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2029 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2030 opt_virtual_call_Relocation::spec(),
a61af66fc99e Initial load
duke
parents:
diff changeset
2031 RELOC_DISP32);
a61af66fc99e Initial load
duke
parents:
diff changeset
2032 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2033 emit_d32_reloc(cbuf,
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2034 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2035 static_call_Relocation::spec(),
a61af66fc99e Initial load
duke
parents:
diff changeset
2036 RELOC_DISP32);
a61af66fc99e Initial load
duke
parents:
diff changeset
2037 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2038 if (_method) {
10168
a6e09d6dd8e5 8003853: specify offset of IC load in java_to_interp stub
dlong
parents: 8873
diff changeset
2039 // Emit stub for static call.
a6e09d6dd8e5 8003853: specify offset of IC load in java_to_interp stub
dlong
parents: 8873
diff changeset
2040 CompiledStaticCall::emit_to_interp_stub(cbuf);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2041 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2042 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2043
6725
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 6614
diff changeset
2044 enc_class Java_Dynamic_Call(method meth) %{
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 6614
diff changeset
2045 MacroAssembler _masm(&cbuf);
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 6614
diff changeset
2046 __ ic_call((address)$meth$$method);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2047 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2048
a61af66fc99e Initial load
duke
parents:
diff changeset
2049 enc_class Java_Compiled_Call(method meth)
a61af66fc99e Initial load
duke
parents:
diff changeset
2050 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2051 // JAVA COMPILED CALL
6725
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 6614
diff changeset
2052 int disp = in_bytes(Method:: from_compiled_offset());
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2053
a61af66fc99e Initial load
duke
parents:
diff changeset
2054 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
a61af66fc99e Initial load
duke
parents:
diff changeset
2055 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
a61af66fc99e Initial load
duke
parents:
diff changeset
2056
a61af66fc99e Initial load
duke
parents:
diff changeset
2057 // callq *disp(%rax)
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2058 cbuf.set_insts_mark();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2059 $$$emit8$primary;
a61af66fc99e Initial load
duke
parents:
diff changeset
2060 if (disp < 0x80) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2061 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
a61af66fc99e Initial load
duke
parents:
diff changeset
2062 emit_d8(cbuf, disp); // Displacement
a61af66fc99e Initial load
duke
parents:
diff changeset
2063 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2064 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
a61af66fc99e Initial load
duke
parents:
diff changeset
2065 emit_d32(cbuf, disp); // Displacement
a61af66fc99e Initial load
duke
parents:
diff changeset
2066 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2067 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2068
a61af66fc99e Initial load
duke
parents:
diff changeset
2069 enc_class reg_opc_imm(rRegI dst, immI8 shift)
a61af66fc99e Initial load
duke
parents:
diff changeset
2070 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2071 // SAL, SAR, SHR
a61af66fc99e Initial load
duke
parents:
diff changeset
2072 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2073 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2074 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2075 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2076 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2077 $$$emit8$primary;
a61af66fc99e Initial load
duke
parents:
diff changeset
2078 emit_rm(cbuf, 0x3, $secondary, dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2079 $$$emit8$shift$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
2080 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2081
a61af66fc99e Initial load
duke
parents:
diff changeset
2082 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
a61af66fc99e Initial load
duke
parents:
diff changeset
2083 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2084 // SAL, SAR, SHR
a61af66fc99e Initial load
duke
parents:
diff changeset
2085 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2086 if (dstenc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2087 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
2088 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2089 emit_opcode(cbuf, Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2090 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2091 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2092 $$$emit8$primary;
a61af66fc99e Initial load
duke
parents:
diff changeset
2093 emit_rm(cbuf, 0x3, $secondary, dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2094 $$$emit8$shift$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
2095 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2096
a61af66fc99e Initial load
duke
parents:
diff changeset
2097 enc_class load_immI(rRegI dst, immI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2098 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2099 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2100 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2101 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2102 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2103 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2104 emit_opcode(cbuf, 0xB8 | dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2105 $$$emit32$src$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
2106 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2107
a61af66fc99e Initial load
duke
parents:
diff changeset
2108 enc_class load_immL(rRegL dst, immL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2109 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2110 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2111 if (dstenc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2112 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
2113 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2114 emit_opcode(cbuf, Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2115 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2116 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2117 emit_opcode(cbuf, 0xB8 | dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2118 emit_d64(cbuf, $src$$constant);
a61af66fc99e Initial load
duke
parents:
diff changeset
2119 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2120
a61af66fc99e Initial load
duke
parents:
diff changeset
2121 enc_class load_immUL32(rRegL dst, immUL32 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2122 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2123 // same as load_immI, but this time we care about zeroes in the high word
a61af66fc99e Initial load
duke
parents:
diff changeset
2124 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2125 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2126 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2127 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2128 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2129 emit_opcode(cbuf, 0xB8 | dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2130 $$$emit32$src$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
2131 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2132
a61af66fc99e Initial load
duke
parents:
diff changeset
2133 enc_class load_immL32(rRegL dst, immL32 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2134 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2135 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2136 if (dstenc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2137 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
2138 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2139 emit_opcode(cbuf, Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2140 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2141 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2142 emit_opcode(cbuf, 0xC7);
a61af66fc99e Initial load
duke
parents:
diff changeset
2143 emit_rm(cbuf, 0x03, 0x00, dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2144 $$$emit32$src$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
2145 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2146
a61af66fc99e Initial load
duke
parents:
diff changeset
2147 enc_class load_immP31(rRegP dst, immP32 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2148 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2149 // same as load_immI, but this time we care about zeroes in the high word
a61af66fc99e Initial load
duke
parents:
diff changeset
2150 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2151 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2152 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2153 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2154 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2155 emit_opcode(cbuf, 0xB8 | dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2156 $$$emit32$src$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
2157 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2158
a61af66fc99e Initial load
duke
parents:
diff changeset
2159 enc_class load_immP(rRegP dst, immP src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2160 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2161 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2162 if (dstenc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2163 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
2164 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2165 emit_opcode(cbuf, Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2166 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2167 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2168 emit_opcode(cbuf, 0xB8 | dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2169 // This next line should be generated from ADLC
6725
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 6614
diff changeset
2170 if ($src->constant_reloc() != relocInfo::none) {
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 6614
diff changeset
2171 emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2172 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2173 emit_d64(cbuf, $src$$constant);
a61af66fc99e Initial load
duke
parents:
diff changeset
2174 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2175 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2176
a61af66fc99e Initial load
duke
parents:
diff changeset
2177 enc_class Con32(immI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2178 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2179 // Output immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
2180 $$$emit32$src$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
2181 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2182
a61af66fc99e Initial load
duke
parents:
diff changeset
2183 enc_class Con64(immL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2184 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2185 // Output immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
2186 emit_d64($src$$constant);
a61af66fc99e Initial load
duke
parents:
diff changeset
2187 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2188
a61af66fc99e Initial load
duke
parents:
diff changeset
2189 enc_class Con32F_as_bits(immF src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2190 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2191 // Output Float immediate bits
a61af66fc99e Initial load
duke
parents:
diff changeset
2192 jfloat jf = $src$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
2193 jint jf_as_bits = jint_cast(jf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2194 emit_d32(cbuf, jf_as_bits);
a61af66fc99e Initial load
duke
parents:
diff changeset
2195 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2196
a61af66fc99e Initial load
duke
parents:
diff changeset
2197 enc_class Con16(immI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2198 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2199 // Output immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
2200 $$$emit16$src$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
2201 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2202
a61af66fc99e Initial load
duke
parents:
diff changeset
2203 // How is this different from Con32??? XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
2204 enc_class Con_d32(immI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2205 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2206 emit_d32(cbuf,$src$$constant);
a61af66fc99e Initial load
duke
parents:
diff changeset
2207 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2208
a61af66fc99e Initial load
duke
parents:
diff changeset
2209 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
a61af66fc99e Initial load
duke
parents:
diff changeset
2210 // Output immediate memory reference
a61af66fc99e Initial load
duke
parents:
diff changeset
2211 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
a61af66fc99e Initial load
duke
parents:
diff changeset
2212 emit_d32(cbuf, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
2213 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2214
a61af66fc99e Initial load
duke
parents:
diff changeset
2215 enc_class lock_prefix()
a61af66fc99e Initial load
duke
parents:
diff changeset
2216 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2217 if (os::is_MP()) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2218 emit_opcode(cbuf, 0xF0); // lock
a61af66fc99e Initial load
duke
parents:
diff changeset
2219 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2220 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2221
a61af66fc99e Initial load
duke
parents:
diff changeset
2222 enc_class REX_mem(memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
2223 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2224 if ($mem$$base >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2225 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2226 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2227 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2228 emit_opcode(cbuf, Assembler::REX_XB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2229 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2230 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2231 if ($mem$$index >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2232 emit_opcode(cbuf, Assembler::REX_X);
a61af66fc99e Initial load
duke
parents:
diff changeset
2233 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2234 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2235 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2236
a61af66fc99e Initial load
duke
parents:
diff changeset
2237 enc_class REX_mem_wide(memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
2238 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2239 if ($mem$$base >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2240 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2241 emit_opcode(cbuf, Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2242 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2243 emit_opcode(cbuf, Assembler::REX_WXB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2244 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2245 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2246 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2247 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
2248 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2249 emit_opcode(cbuf, Assembler::REX_WX);
a61af66fc99e Initial load
duke
parents:
diff changeset
2250 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2251 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2252 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2253
a61af66fc99e Initial load
duke
parents:
diff changeset
2254 // for byte regs
a61af66fc99e Initial load
duke
parents:
diff changeset
2255 enc_class REX_breg(rRegI reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
2256 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2257 if ($reg$$reg >= 4) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2258 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2259 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2260 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2261
a61af66fc99e Initial load
duke
parents:
diff changeset
2262 // for byte regs
a61af66fc99e Initial load
duke
parents:
diff changeset
2263 enc_class REX_reg_breg(rRegI dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2264 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2265 if ($dst$$reg < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2266 if ($src$$reg >= 4) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2267 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2268 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2269 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2270 if ($src$$reg < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2271 emit_opcode(cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
2272 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2273 emit_opcode(cbuf, Assembler::REX_RB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2274 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2275 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2276 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2277
a61af66fc99e Initial load
duke
parents:
diff changeset
2278 // for byte regs
a61af66fc99e Initial load
duke
parents:
diff changeset
2279 enc_class REX_breg_mem(rRegI reg, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
2280 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2281 if ($reg$$reg < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2282 if ($mem$$base < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2283 if ($mem$$index >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2284 emit_opcode(cbuf, Assembler::REX_X);
a61af66fc99e Initial load
duke
parents:
diff changeset
2285 } else if ($reg$$reg >= 4) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2286 emit_opcode(cbuf, Assembler::REX);
a61af66fc99e Initial load
duke
parents:
diff changeset
2287 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2288 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2289 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2290 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2291 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2292 emit_opcode(cbuf, Assembler::REX_XB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2293 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2294 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2295 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2296 if ($mem$$base < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2297 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2298 emit_opcode(cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
2299 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2300 emit_opcode(cbuf, Assembler::REX_RX);
a61af66fc99e Initial load
duke
parents:
diff changeset
2301 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2302 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2303 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2304 emit_opcode(cbuf, Assembler::REX_RB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2305 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2306 emit_opcode(cbuf, Assembler::REX_RXB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2307 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2308 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2309 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2310 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2311
a61af66fc99e Initial load
duke
parents:
diff changeset
2312 enc_class REX_reg(rRegI reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
2313 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2314 if ($reg$$reg >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2315 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2316 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2317 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2318
a61af66fc99e Initial load
duke
parents:
diff changeset
2319 enc_class REX_reg_wide(rRegI reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
2320 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2321 if ($reg$$reg < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2322 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
2323 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2324 emit_opcode(cbuf, Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2325 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2326 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2327
a61af66fc99e Initial load
duke
parents:
diff changeset
2328 enc_class REX_reg_reg(rRegI dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2329 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2330 if ($dst$$reg < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2331 if ($src$$reg >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2332 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2333 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2334 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2335 if ($src$$reg < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2336 emit_opcode(cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
2337 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2338 emit_opcode(cbuf, Assembler::REX_RB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2339 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2340 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2341 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2342
a61af66fc99e Initial load
duke
parents:
diff changeset
2343 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
2344 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2345 if ($dst$$reg < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2346 if ($src$$reg < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2347 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
2348 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2349 emit_opcode(cbuf, Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2350 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2351 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2352 if ($src$$reg < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2353 emit_opcode(cbuf, Assembler::REX_WR);
a61af66fc99e Initial load
duke
parents:
diff changeset
2354 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2355 emit_opcode(cbuf, Assembler::REX_WRB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2356 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2357 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2358 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2359
a61af66fc99e Initial load
duke
parents:
diff changeset
2360 enc_class REX_reg_mem(rRegI reg, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
2361 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2362 if ($reg$$reg < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2363 if ($mem$$base < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2364 if ($mem$$index >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2365 emit_opcode(cbuf, Assembler::REX_X);
a61af66fc99e Initial load
duke
parents:
diff changeset
2366 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2367 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2368 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2369 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2370 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2371 emit_opcode(cbuf, Assembler::REX_XB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2372 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2373 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2374 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2375 if ($mem$$base < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2376 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2377 emit_opcode(cbuf, Assembler::REX_R);
a61af66fc99e Initial load
duke
parents:
diff changeset
2378 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2379 emit_opcode(cbuf, Assembler::REX_RX);
a61af66fc99e Initial load
duke
parents:
diff changeset
2380 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2381 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2382 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2383 emit_opcode(cbuf, Assembler::REX_RB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2384 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2385 emit_opcode(cbuf, Assembler::REX_RXB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2386 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2387 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2388 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2389 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2390
a61af66fc99e Initial load
duke
parents:
diff changeset
2391 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
2392 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2393 if ($reg$$reg < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2394 if ($mem$$base < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2395 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2396 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
2397 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2398 emit_opcode(cbuf, Assembler::REX_WX);
a61af66fc99e Initial load
duke
parents:
diff changeset
2399 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2400 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2401 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2402 emit_opcode(cbuf, Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2403 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2404 emit_opcode(cbuf, Assembler::REX_WXB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2405 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2406 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2407 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2408 if ($mem$$base < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2409 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2410 emit_opcode(cbuf, Assembler::REX_WR);
a61af66fc99e Initial load
duke
parents:
diff changeset
2411 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2412 emit_opcode(cbuf, Assembler::REX_WRX);
a61af66fc99e Initial load
duke
parents:
diff changeset
2413 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2414 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2415 if ($mem$$index < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2416 emit_opcode(cbuf, Assembler::REX_WRB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2417 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2418 emit_opcode(cbuf, Assembler::REX_WRXB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2419 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2420 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2421 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2422 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2423
a61af66fc99e Initial load
duke
parents:
diff changeset
2424 enc_class reg_mem(rRegI ereg, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
2425 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2426 // High registers handle in encode_RegMem
a61af66fc99e Initial load
duke
parents:
diff changeset
2427 int reg = $ereg$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2428 int base = $mem$$base;
a61af66fc99e Initial load
duke
parents:
diff changeset
2429 int index = $mem$$index;
a61af66fc99e Initial load
duke
parents:
diff changeset
2430 int scale = $mem$$scale;
a61af66fc99e Initial load
duke
parents:
diff changeset
2431 int disp = $mem$$disp;
6725
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 6614
diff changeset
2432 relocInfo::relocType disp_reloc = $mem->disp_reloc();
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 6614
diff changeset
2433
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 6614
diff changeset
2434 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2435 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2436
a61af66fc99e Initial load
duke
parents:
diff changeset
2437 enc_class RM_opc_mem(immI rm_opcode, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
2438 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2439 int rm_byte_opcode = $rm_opcode$$constant;
a61af66fc99e Initial load
duke
parents:
diff changeset
2440
a61af66fc99e Initial load
duke
parents:
diff changeset
2441 // High registers handle in encode_RegMem
a61af66fc99e Initial load
duke
parents:
diff changeset
2442 int base = $mem$$base;
a61af66fc99e Initial load
duke
parents:
diff changeset
2443 int index = $mem$$index;
a61af66fc99e Initial load
duke
parents:
diff changeset
2444 int scale = $mem$$scale;
a61af66fc99e Initial load
duke
parents:
diff changeset
2445 int displace = $mem$$disp;
a61af66fc99e Initial load
duke
parents:
diff changeset
2446
6725
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 6614
diff changeset
2447 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2448 // working with static
a61af66fc99e Initial load
duke
parents:
diff changeset
2449 // globals
a61af66fc99e Initial load
duke
parents:
diff changeset
2450 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
6725
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 6614
diff changeset
2451 disp_reloc);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2452 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2453
a61af66fc99e Initial load
duke
parents:
diff changeset
2454 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
a61af66fc99e Initial load
duke
parents:
diff changeset
2455 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2456 int reg_encoding = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2457 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
a61af66fc99e Initial load
duke
parents:
diff changeset
2458 int index = 0x04; // 0x04 indicates no index
a61af66fc99e Initial load
duke
parents:
diff changeset
2459 int scale = 0x00; // 0x00 indicates no scale
a61af66fc99e Initial load
duke
parents:
diff changeset
2460 int displace = $src1$$constant; // 0x00 indicates no displacement
6725
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 6614
diff changeset
2461 relocInfo::relocType disp_reloc = relocInfo::none;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2462 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
6725
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 6614
diff changeset
2463 disp_reloc);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2464 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2465
a61af66fc99e Initial load
duke
parents:
diff changeset
2466 enc_class neg_reg(rRegI dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
2467 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2468 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2469 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2470 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2471 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2472 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2473 // NEG $dst
a61af66fc99e Initial load
duke
parents:
diff changeset
2474 emit_opcode(cbuf, 0xF7);
a61af66fc99e Initial load
duke
parents:
diff changeset
2475 emit_rm(cbuf, 0x3, 0x03, dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2476 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2477
a61af66fc99e Initial load
duke
parents:
diff changeset
2478 enc_class neg_reg_wide(rRegI dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
2479 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2480 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2481 if (dstenc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2482 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
2483 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2484 emit_opcode(cbuf, Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2485 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2486 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2487 // NEG $dst
a61af66fc99e Initial load
duke
parents:
diff changeset
2488 emit_opcode(cbuf, 0xF7);
a61af66fc99e Initial load
duke
parents:
diff changeset
2489 emit_rm(cbuf, 0x3, 0x03, dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2490 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2491
a61af66fc99e Initial load
duke
parents:
diff changeset
2492 enc_class setLT_reg(rRegI dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
2493 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2494 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2495 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2496 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2497 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2498 } else if (dstenc >= 4) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2499 emit_opcode(cbuf, Assembler::REX);
a61af66fc99e Initial load
duke
parents:
diff changeset
2500 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2501 // SETLT $dst
a61af66fc99e Initial load
duke
parents:
diff changeset
2502 emit_opcode(cbuf, 0x0F);
a61af66fc99e Initial load
duke
parents:
diff changeset
2503 emit_opcode(cbuf, 0x9C);
a61af66fc99e Initial load
duke
parents:
diff changeset
2504 emit_rm(cbuf, 0x3, 0x0, dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2505 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2506
a61af66fc99e Initial load
duke
parents:
diff changeset
2507 enc_class setNZ_reg(rRegI dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
2508 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2509 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2510 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2511 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2512 dstenc -= 8;
a61af66fc99e Initial load
duke
parents:
diff changeset
2513 } else if (dstenc >= 4) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2514 emit_opcode(cbuf, Assembler::REX);
a61af66fc99e Initial load
duke
parents:
diff changeset
2515 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2516 // SETNZ $dst
a61af66fc99e Initial load
duke
parents:
diff changeset
2517 emit_opcode(cbuf, 0x0F);
a61af66fc99e Initial load
duke
parents:
diff changeset
2518 emit_opcode(cbuf, 0x95);
a61af66fc99e Initial load
duke
parents:
diff changeset
2519 emit_rm(cbuf, 0x3, 0x0, dstenc);
a61af66fc99e Initial load
duke
parents:
diff changeset
2520 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2521
a61af66fc99e Initial load
duke
parents:
diff changeset
2522
a61af66fc99e Initial load
duke
parents:
diff changeset
2523 // Compare the lonogs and set -1, 0, or 1 into dst
a61af66fc99e Initial load
duke
parents:
diff changeset
2524 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
2525 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2526 int src1enc = $src1$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2527 int src2enc = $src2$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2528 int dstenc = $dst$$reg;
a61af66fc99e Initial load
duke
parents:
diff changeset
2529
a61af66fc99e Initial load
duke
parents:
diff changeset
2530 // cmpq $src1, $src2
a61af66fc99e Initial load
duke
parents:
diff changeset
2531 if (src1enc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2532 if (src2enc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2533 emit_opcode(cbuf, Assembler::REX_W);
a61af66fc99e Initial load
duke
parents:
diff changeset
2534 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2535 emit_opcode(cbuf, Assembler::REX_WB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2536 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2537 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2538 if (src2enc < 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2539 emit_opcode(cbuf, Assembler::REX_WR);
a61af66fc99e Initial load
duke
parents:
diff changeset
2540 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2541 emit_opcode(cbuf, Assembler::REX_WRB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2542 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2543 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2544 emit_opcode(cbuf, 0x3B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2545 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
2546
a61af66fc99e Initial load
duke
parents:
diff changeset
2547 // movl $dst, -1
a61af66fc99e Initial load
duke
parents:
diff changeset
2548 if (dstenc >= 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2549 emit_opcode(cbuf, Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2550 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2551 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
a61af66fc99e Initial load
duke
parents:
diff changeset
2552 emit_d32(cbuf, -1);
a61af66fc99e Initial load
duke
parents:
diff changeset
2553
a61af66fc99e Initial load
duke
parents:
diff changeset
2554 // jl,s done
a61af66fc99e Initial load
duke
parents:
diff changeset
2555 emit_opcode(cbuf, 0x7C);
a61af66fc99e Initial load
duke
parents:
diff changeset
2556 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
a61af66fc99e Initial load
duke
parents:
diff changeset
2557
a61af66fc99e Initial load
duke
parents:
diff changeset
2558 // setne $dst
a61af66fc99e Initial load
duke
parents:
diff changeset
2559 if (dstenc >= 4) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2560 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
a61af66fc99e Initial load
duke
parents:
diff changeset
2561 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2562 emit_opcode(cbuf, 0x0F);
a61af66fc99e Initial load
duke
parents:
diff changeset
2563 emit_opcode(cbuf, 0x95);
a61af66fc99e Initial load
duke
parents:
diff changeset
2564 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
a61af66fc99e Initial load
duke
parents:
diff changeset
2565
a61af66fc99e Initial load
duke
parents:
diff changeset
2566 // movzbl $dst, $dst
a61af66fc99e Initial load
duke
parents:
diff changeset
2567 if (dstenc >= 4) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2568 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
a61af66fc99e Initial load
duke
parents:
diff changeset
2569 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2570 emit_opcode(cbuf, 0x0F);
a61af66fc99e Initial load
duke
parents:
diff changeset
2571 emit_opcode(cbuf, 0xB6);
a61af66fc99e Initial load
duke
parents:
diff changeset
2572 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
a61af66fc99e Initial load
duke
parents:
diff changeset
2573 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2574
a61af66fc99e Initial load
duke
parents:
diff changeset
2575 enc_class Push_ResultXD(regD dst) %{
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
2576 MacroAssembler _masm(&cbuf);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
2577 __ fstp_d(Address(rsp, 0));
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
2578 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
2579 __ addptr(rsp, 8);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2580 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2581
a61af66fc99e Initial load
duke
parents:
diff changeset
2582 enc_class Push_SrcXD(regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2583 MacroAssembler _masm(&cbuf);
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
2584 __ subptr(rsp, 8);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
2585 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
2586 __ fld_d(Address(rsp, 0));
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
2587 %}
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
2588
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2589
a61af66fc99e Initial load
duke
parents:
diff changeset
2590 // obj: object to lock
a61af66fc99e Initial load
duke
parents:
diff changeset
2591 // box: box address (header location) -- killed
a61af66fc99e Initial load
duke
parents:
diff changeset
2592 // tmp: rax -- killed
a61af66fc99e Initial load
duke
parents:
diff changeset
2593 // scr: rbx -- killed
a61af66fc99e Initial load
duke
parents:
diff changeset
2594 //
a61af66fc99e Initial load
duke
parents:
diff changeset
2595 // What follows is a direct transliteration of fast_lock() and fast_unlock()
a61af66fc99e Initial load
duke
parents:
diff changeset
2596 // from i486.ad. See that file for comments.
a61af66fc99e Initial load
duke
parents:
diff changeset
2597 // TODO: where possible switch from movq (r, 0) to movl(r,0) and
a61af66fc99e Initial load
duke
parents:
diff changeset
2598 // use the shorter encoding. (Movl clears the high-order 32-bits).
a61af66fc99e Initial load
duke
parents:
diff changeset
2599
a61af66fc99e Initial load
duke
parents:
diff changeset
2600
a61af66fc99e Initial load
duke
parents:
diff changeset
2601 enc_class Fast_Lock(rRegP obj, rRegP box, rax_RegI tmp, rRegP scr)
a61af66fc99e Initial load
duke
parents:
diff changeset
2602 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2603 Register objReg = as_Register((int)$obj$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2604 Register boxReg = as_Register((int)$box$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2605 Register tmpReg = as_Register($tmp$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2606 Register scrReg = as_Register($scr$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2607 MacroAssembler masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2608
a61af66fc99e Initial load
duke
parents:
diff changeset
2609 // Verify uniqueness of register assignments -- necessary but not sufficient
a61af66fc99e Initial load
duke
parents:
diff changeset
2610 assert (objReg != boxReg && objReg != tmpReg &&
a61af66fc99e Initial load
duke
parents:
diff changeset
2611 objReg != scrReg && tmpReg != scrReg, "invariant") ;
a61af66fc99e Initial load
duke
parents:
diff changeset
2612
a61af66fc99e Initial load
duke
parents:
diff changeset
2613 if (_counters != NULL) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2614 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
a61af66fc99e Initial load
duke
parents:
diff changeset
2615 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2616 if (EmitSync & 1) {
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2617 // Without cast to int32_t a movptr will destroy r10 which is typically obj
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2618 masm.movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2619 masm.cmpptr(rsp, (int32_t)NULL_WORD) ;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2620 } else
a61af66fc99e Initial load
duke
parents:
diff changeset
2621 if (EmitSync & 2) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2622 Label DONE_LABEL;
a61af66fc99e Initial load
duke
parents:
diff changeset
2623 if (UseBiasedLocking) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2624 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
a61af66fc99e Initial load
duke
parents:
diff changeset
2625 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
a61af66fc99e Initial load
duke
parents:
diff changeset
2626 }
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2627 // QQQ was movl...
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2628 masm.movptr(tmpReg, 0x1);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2629 masm.orptr(tmpReg, Address(objReg, 0));
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2630 masm.movptr(Address(boxReg, 0), tmpReg);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2631 if (os::is_MP()) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2632 masm.lock();
a61af66fc99e Initial load
duke
parents:
diff changeset
2633 }
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2634 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2635 masm.jcc(Assembler::equal, DONE_LABEL);
a61af66fc99e Initial load
duke
parents:
diff changeset
2636
a61af66fc99e Initial load
duke
parents:
diff changeset
2637 // Recursive locking
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2638 masm.subptr(tmpReg, rsp);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2639 masm.andptr(tmpReg, 7 - os::vm_page_size());
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2640 masm.movptr(Address(boxReg, 0), tmpReg);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2641
a61af66fc99e Initial load
duke
parents:
diff changeset
2642 masm.bind(DONE_LABEL);
a61af66fc99e Initial load
duke
parents:
diff changeset
2643 masm.nop(); // avoid branch to branch
a61af66fc99e Initial load
duke
parents:
diff changeset
2644 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2645 Label DONE_LABEL, IsInflated, Egress;
a61af66fc99e Initial load
duke
parents:
diff changeset
2646
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2647 masm.movptr(tmpReg, Address(objReg, 0)) ;
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2648 masm.testl (tmpReg, 0x02) ; // inflated vs stack-locked|neutral|biased
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2649 masm.jcc (Assembler::notZero, IsInflated) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2650
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2651 // it's stack-locked, biased or neutral
a61af66fc99e Initial load
duke
parents:
diff changeset
2652 // TODO: optimize markword triage order to reduce the number of
a61af66fc99e Initial load
duke
parents:
diff changeset
2653 // conditional branches in the most common cases.
a61af66fc99e Initial load
duke
parents:
diff changeset
2654 // Beware -- there's a subtle invariant that fetch of the markword
a61af66fc99e Initial load
duke
parents:
diff changeset
2655 // at [FETCH], below, will never observe a biased encoding (*101b).
a61af66fc99e Initial load
duke
parents:
diff changeset
2656 // If this invariant is not held we'll suffer exclusion (safety) failure.
a61af66fc99e Initial load
duke
parents:
diff changeset
2657
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
2658 if (UseBiasedLocking && !UseOptoBiasInlining) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2659 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, true, DONE_LABEL, NULL, _counters);
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2660 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2661 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2662
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2663 // was q will it destroy high?
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2664 masm.orl (tmpReg, 1) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2665 masm.movptr(Address(boxReg, 0), tmpReg) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2666 if (os::is_MP()) { masm.lock(); }
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2667 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2668 if (_counters != NULL) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2669 masm.cond_inc32(Assembler::equal,
a61af66fc99e Initial load
duke
parents:
diff changeset
2670 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
a61af66fc99e Initial load
duke
parents:
diff changeset
2671 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2672 masm.jcc (Assembler::equal, DONE_LABEL);
a61af66fc99e Initial load
duke
parents:
diff changeset
2673
a61af66fc99e Initial load
duke
parents:
diff changeset
2674 // Recursive locking
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2675 masm.subptr(tmpReg, rsp);
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2676 masm.andptr(tmpReg, 7 - os::vm_page_size());
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2677 masm.movptr(Address(boxReg, 0), tmpReg);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2678 if (_counters != NULL) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2679 masm.cond_inc32(Assembler::equal,
a61af66fc99e Initial load
duke
parents:
diff changeset
2680 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
a61af66fc99e Initial load
duke
parents:
diff changeset
2681 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2682 masm.jmp (DONE_LABEL) ;
a61af66fc99e Initial load
duke
parents:
diff changeset
2683
a61af66fc99e Initial load
duke
parents:
diff changeset
2684 masm.bind (IsInflated) ;
a61af66fc99e Initial load
duke
parents:
diff changeset
2685 // It's inflated
a61af66fc99e Initial load
duke
parents:
diff changeset
2686
a61af66fc99e Initial load
duke
parents:
diff changeset
2687 // TODO: someday avoid the ST-before-CAS penalty by
a61af66fc99e Initial load
duke
parents:
diff changeset
2688 // relocating (deferring) the following ST.
a61af66fc99e Initial load
duke
parents:
diff changeset
2689 // We should also think about trying a CAS without having
a61af66fc99e Initial load
duke
parents:
diff changeset
2690 // fetched _owner. If the CAS is successful we may
a61af66fc99e Initial load
duke
parents:
diff changeset
2691 // avoid an RTO->RTS upgrade on the $line.
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2692 // Without cast to int32_t a movptr will destroy r10 which is typically obj
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2693 masm.movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2694
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2695 masm.mov (boxReg, tmpReg) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2696 masm.movptr (tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2697 masm.testptr(tmpReg, tmpReg) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2698 masm.jcc (Assembler::notZero, DONE_LABEL) ;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2699
a61af66fc99e Initial load
duke
parents:
diff changeset
2700 // It's inflated and appears unlocked
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2701 if (os::is_MP()) { masm.lock(); }
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2702 masm.cmpxchgptr(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2703 // Intentional fall-through into DONE_LABEL ...
a61af66fc99e Initial load
duke
parents:
diff changeset
2704
a61af66fc99e Initial load
duke
parents:
diff changeset
2705 masm.bind (DONE_LABEL) ;
a61af66fc99e Initial load
duke
parents:
diff changeset
2706 masm.nop () ; // avoid jmp to jmp
a61af66fc99e Initial load
duke
parents:
diff changeset
2707 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2708 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2709
a61af66fc99e Initial load
duke
parents:
diff changeset
2710 // obj: object to unlock
a61af66fc99e Initial load
duke
parents:
diff changeset
2711 // box: box address (displaced header location), killed
a61af66fc99e Initial load
duke
parents:
diff changeset
2712 // RBX: killed tmp; cannot be obj nor box
a61af66fc99e Initial load
duke
parents:
diff changeset
2713 enc_class Fast_Unlock(rRegP obj, rax_RegP box, rRegP tmp)
a61af66fc99e Initial load
duke
parents:
diff changeset
2714 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2715
a61af66fc99e Initial load
duke
parents:
diff changeset
2716 Register objReg = as_Register($obj$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2717 Register boxReg = as_Register($box$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2718 Register tmpReg = as_Register($tmp$$reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
2719 MacroAssembler masm(&cbuf);
a61af66fc99e Initial load
duke
parents:
diff changeset
2720
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2721 if (EmitSync & 4) {
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2722 masm.cmpptr(rsp, 0) ;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2723 } else
a61af66fc99e Initial load
duke
parents:
diff changeset
2724 if (EmitSync & 8) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2725 Label DONE_LABEL;
a61af66fc99e Initial load
duke
parents:
diff changeset
2726 if (UseBiasedLocking) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2727 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
a61af66fc99e Initial load
duke
parents:
diff changeset
2728 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2729
a61af66fc99e Initial load
duke
parents:
diff changeset
2730 // Check whether the displaced header is 0
a61af66fc99e Initial load
duke
parents:
diff changeset
2731 //(=> recursive unlock)
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2732 masm.movptr(tmpReg, Address(boxReg, 0));
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2733 masm.testptr(tmpReg, tmpReg);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2734 masm.jcc(Assembler::zero, DONE_LABEL);
a61af66fc99e Initial load
duke
parents:
diff changeset
2735
a61af66fc99e Initial load
duke
parents:
diff changeset
2736 // If not recursive lock, reset the header to displaced header
a61af66fc99e Initial load
duke
parents:
diff changeset
2737 if (os::is_MP()) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2738 masm.lock();
a61af66fc99e Initial load
duke
parents:
diff changeset
2739 }
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2740 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2741 masm.bind(DONE_LABEL);
a61af66fc99e Initial load
duke
parents:
diff changeset
2742 masm.nop(); // avoid branch to branch
a61af66fc99e Initial load
duke
parents:
diff changeset
2743 } else {
a61af66fc99e Initial load
duke
parents:
diff changeset
2744 Label DONE_LABEL, Stacked, CheckSucc ;
a61af66fc99e Initial load
duke
parents:
diff changeset
2745
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
2746 if (UseBiasedLocking && !UseOptoBiasInlining) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2747 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
a61af66fc99e Initial load
duke
parents:
diff changeset
2748 }
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2749
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2750 masm.movptr(tmpReg, Address(objReg, 0)) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2751 masm.cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2752 masm.jcc (Assembler::zero, DONE_LABEL) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2753 masm.testl (tmpReg, 0x02) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2754 masm.jcc (Assembler::zero, Stacked) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2755
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2756 // It's inflated
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2757 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2758 masm.xorptr(boxReg, r15_thread) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2759 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2760 masm.jcc (Assembler::notZero, DONE_LABEL) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2761 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2762 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2763 masm.jcc (Assembler::notZero, CheckSucc) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2764 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2765 masm.jmp (DONE_LABEL) ;
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2766
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2767 if ((EmitSync & 65536) == 0) {
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2768 Label LSuccess, LGoSlowPath ;
a61af66fc99e Initial load
duke
parents:
diff changeset
2769 masm.bind (CheckSucc) ;
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2770 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2771 masm.jcc (Assembler::zero, LGoSlowPath) ;
a61af66fc99e Initial load
duke
parents:
diff changeset
2772
a61af66fc99e Initial load
duke
parents:
diff changeset
2773 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the
a61af66fc99e Initial load
duke
parents:
diff changeset
2774 // the explicit ST;MEMBAR combination, but masm doesn't currently support
a61af66fc99e Initial load
duke
parents:
diff changeset
2775 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc
a61af66fc99e Initial load
duke
parents:
diff changeset
2776 // are all faster when the write buffer is populated.
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2777 masm.movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2778 if (os::is_MP()) {
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2779 masm.lock () ; masm.addl (Address(rsp, 0), 0) ;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2780 }
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2781 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2782 masm.jcc (Assembler::notZero, LSuccess) ;
a61af66fc99e Initial load
duke
parents:
diff changeset
2783
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2784 masm.movptr (boxReg, (int32_t)NULL_WORD) ; // box is really EAX
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2785 if (os::is_MP()) { masm.lock(); }
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2786 masm.cmpxchgptr(r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2787 masm.jcc (Assembler::notEqual, LSuccess) ;
a61af66fc99e Initial load
duke
parents:
diff changeset
2788 // Intentional fall-through into slow-path
a61af66fc99e Initial load
duke
parents:
diff changeset
2789
a61af66fc99e Initial load
duke
parents:
diff changeset
2790 masm.bind (LGoSlowPath) ;
a61af66fc99e Initial load
duke
parents:
diff changeset
2791 masm.orl (boxReg, 1) ; // set ICC.ZF=0 to indicate failure
a61af66fc99e Initial load
duke
parents:
diff changeset
2792 masm.jmp (DONE_LABEL) ;
a61af66fc99e Initial load
duke
parents:
diff changeset
2793
a61af66fc99e Initial load
duke
parents:
diff changeset
2794 masm.bind (LSuccess) ;
a61af66fc99e Initial load
duke
parents:
diff changeset
2795 masm.testl (boxReg, 0) ; // set ICC.ZF=1 to indicate success
a61af66fc99e Initial load
duke
parents:
diff changeset
2796 masm.jmp (DONE_LABEL) ;
a61af66fc99e Initial load
duke
parents:
diff changeset
2797 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2798
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2799 masm.bind (Stacked) ;
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2800 masm.movptr(tmpReg, Address (boxReg, 0)) ; // re-fetch
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
2801 if (os::is_MP()) { masm.lock(); }
304
dc7f315e41f7 5108146: Merge i486 and amd64 cpu directories
never
parents: 235
diff changeset
2802 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2803
a61af66fc99e Initial load
duke
parents:
diff changeset
2804 if (EmitSync & 65536) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2805 masm.bind (CheckSucc) ;
a61af66fc99e Initial load
duke
parents:
diff changeset
2806 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2807 masm.bind(DONE_LABEL);
a61af66fc99e Initial load
duke
parents:
diff changeset
2808 if (EmitSync & 32768) {
a61af66fc99e Initial load
duke
parents:
diff changeset
2809 masm.nop(); // avoid branch to branch
a61af66fc99e Initial load
duke
parents:
diff changeset
2810 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2811 }
a61af66fc99e Initial load
duke
parents:
diff changeset
2812 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2813
169
9148c65abefc 6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents: 168
diff changeset
2814
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2815 enc_class enc_rethrow()
a61af66fc99e Initial load
duke
parents:
diff changeset
2816 %{
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2817 cbuf.set_insts_mark();
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2818 emit_opcode(cbuf, 0xE9); // jmp entry
a61af66fc99e Initial load
duke
parents:
diff changeset
2819 emit_d32_reloc(cbuf,
1748
3e8fbc61cee8 6978355: renaming for 6961697
twisti
parents: 1730
diff changeset
2820 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2821 runtime_call_Relocation::spec(),
a61af66fc99e Initial load
duke
parents:
diff changeset
2822 RELOC_DISP32);
a61af66fc99e Initial load
duke
parents:
diff changeset
2823 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2824
a61af66fc99e Initial load
duke
parents:
diff changeset
2825 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2826
a61af66fc99e Initial load
duke
parents:
diff changeset
2827
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
2828
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2829 //----------FRAME--------------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
2830 // Definition of frame structure and management information.
a61af66fc99e Initial load
duke
parents:
diff changeset
2831 //
a61af66fc99e Initial load
duke
parents:
diff changeset
2832 // S T A C K L A Y O U T Allocators stack-slot number
a61af66fc99e Initial load
duke
parents:
diff changeset
2833 // | (to get allocators register number
a61af66fc99e Initial load
duke
parents:
diff changeset
2834 // G Owned by | | v add OptoReg::stack0())
a61af66fc99e Initial load
duke
parents:
diff changeset
2835 // r CALLER | |
a61af66fc99e Initial load
duke
parents:
diff changeset
2836 // o | +--------+ pad to even-align allocators stack-slot
a61af66fc99e Initial load
duke
parents:
diff changeset
2837 // w V | pad0 | numbers; owned by CALLER
a61af66fc99e Initial load
duke
parents:
diff changeset
2838 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
a61af66fc99e Initial load
duke
parents:
diff changeset
2839 // h ^ | in | 5
a61af66fc99e Initial load
duke
parents:
diff changeset
2840 // | | args | 4 Holes in incoming args owned by SELF
a61af66fc99e Initial load
duke
parents:
diff changeset
2841 // | | | | 3
a61af66fc99e Initial load
duke
parents:
diff changeset
2842 // | | +--------+
a61af66fc99e Initial load
duke
parents:
diff changeset
2843 // V | | old out| Empty on Intel, window on Sparc
a61af66fc99e Initial load
duke
parents:
diff changeset
2844 // | old |preserve| Must be even aligned.
a61af66fc99e Initial load
duke
parents:
diff changeset
2845 // | SP-+--------+----> Matcher::_old_SP, even aligned
a61af66fc99e Initial load
duke
parents:
diff changeset
2846 // | | in | 3 area for Intel ret address
a61af66fc99e Initial load
duke
parents:
diff changeset
2847 // Owned by |preserve| Empty on Sparc.
a61af66fc99e Initial load
duke
parents:
diff changeset
2848 // SELF +--------+
a61af66fc99e Initial load
duke
parents:
diff changeset
2849 // | | pad2 | 2 pad to align old SP
a61af66fc99e Initial load
duke
parents:
diff changeset
2850 // | +--------+ 1
a61af66fc99e Initial load
duke
parents:
diff changeset
2851 // | | locks | 0
a61af66fc99e Initial load
duke
parents:
diff changeset
2852 // | +--------+----> OptoReg::stack0(), even aligned
a61af66fc99e Initial load
duke
parents:
diff changeset
2853 // | | pad1 | 11 pad to align new SP
a61af66fc99e Initial load
duke
parents:
diff changeset
2854 // | +--------+
a61af66fc99e Initial load
duke
parents:
diff changeset
2855 // | | | 10
a61af66fc99e Initial load
duke
parents:
diff changeset
2856 // | | spills | 9 spills
a61af66fc99e Initial load
duke
parents:
diff changeset
2857 // V | | 8 (pad0 slot for callee)
a61af66fc99e Initial load
duke
parents:
diff changeset
2858 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
a61af66fc99e Initial load
duke
parents:
diff changeset
2859 // ^ | out | 7
a61af66fc99e Initial load
duke
parents:
diff changeset
2860 // | | args | 6 Holes in outgoing args owned by CALLEE
a61af66fc99e Initial load
duke
parents:
diff changeset
2861 // Owned by +--------+
a61af66fc99e Initial load
duke
parents:
diff changeset
2862 // CALLEE | new out| 6 Empty on Intel, window on Sparc
a61af66fc99e Initial load
duke
parents:
diff changeset
2863 // | new |preserve| Must be even-aligned.
a61af66fc99e Initial load
duke
parents:
diff changeset
2864 // | SP-+--------+----> Matcher::_new_SP, even aligned
a61af66fc99e Initial load
duke
parents:
diff changeset
2865 // | | |
a61af66fc99e Initial load
duke
parents:
diff changeset
2866 //
a61af66fc99e Initial load
duke
parents:
diff changeset
2867 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
a61af66fc99e Initial load
duke
parents:
diff changeset
2868 // known from SELF's arguments and the Java calling convention.
a61af66fc99e Initial load
duke
parents:
diff changeset
2869 // Region 6-7 is determined per call site.
a61af66fc99e Initial load
duke
parents:
diff changeset
2870 // Note 2: If the calling convention leaves holes in the incoming argument
a61af66fc99e Initial load
duke
parents:
diff changeset
2871 // area, those holes are owned by SELF. Holes in the outgoing area
a61af66fc99e Initial load
duke
parents:
diff changeset
2872 // are owned by the CALLEE. Holes should not be nessecary in the
a61af66fc99e Initial load
duke
parents:
diff changeset
2873 // incoming area, as the Java calling convention is completely under
a61af66fc99e Initial load
duke
parents:
diff changeset
2874 // the control of the AD file. Doubles can be sorted and packed to
a61af66fc99e Initial load
duke
parents:
diff changeset
2875 // avoid holes. Holes in the outgoing arguments may be nessecary for
a61af66fc99e Initial load
duke
parents:
diff changeset
2876 // varargs C calling conventions.
a61af66fc99e Initial load
duke
parents:
diff changeset
2877 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
a61af66fc99e Initial load
duke
parents:
diff changeset
2878 // even aligned with pad0 as needed.
a61af66fc99e Initial load
duke
parents:
diff changeset
2879 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
a61af66fc99e Initial load
duke
parents:
diff changeset
2880 // region 6-11 is even aligned; it may be padded out more so that
a61af66fc99e Initial load
duke
parents:
diff changeset
2881 // the region from SP to FP meets the minimum stack alignment.
a61af66fc99e Initial load
duke
parents:
diff changeset
2882 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
a61af66fc99e Initial load
duke
parents:
diff changeset
2883 // alignment. Region 11, pad1, may be dynamically extended so that
a61af66fc99e Initial load
duke
parents:
diff changeset
2884 // SP meets the minimum alignment.
a61af66fc99e Initial load
duke
parents:
diff changeset
2885
a61af66fc99e Initial load
duke
parents:
diff changeset
2886 frame
a61af66fc99e Initial load
duke
parents:
diff changeset
2887 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2888 // What direction does stack grow in (assumed to be same for C & Java)
a61af66fc99e Initial load
duke
parents:
diff changeset
2889 stack_direction(TOWARDS_LOW);
a61af66fc99e Initial load
duke
parents:
diff changeset
2890
a61af66fc99e Initial load
duke
parents:
diff changeset
2891 // These three registers define part of the calling convention
a61af66fc99e Initial load
duke
parents:
diff changeset
2892 // between compiled code and the interpreter.
a61af66fc99e Initial load
duke
parents:
diff changeset
2893 inline_cache_reg(RAX); // Inline Cache Register
a61af66fc99e Initial load
duke
parents:
diff changeset
2894 interpreter_method_oop_reg(RBX); // Method Oop Register when
a61af66fc99e Initial load
duke
parents:
diff changeset
2895 // calling interpreter
a61af66fc99e Initial load
duke
parents:
diff changeset
2896
a61af66fc99e Initial load
duke
parents:
diff changeset
2897 // Optional: name the operand used by cisc-spilling to access
a61af66fc99e Initial load
duke
parents:
diff changeset
2898 // [stack_pointer + offset]
a61af66fc99e Initial load
duke
parents:
diff changeset
2899 cisc_spilling_operand_name(indOffset32);
a61af66fc99e Initial load
duke
parents:
diff changeset
2900
a61af66fc99e Initial load
duke
parents:
diff changeset
2901 // Number of stack slots consumed by locking an object
a61af66fc99e Initial load
duke
parents:
diff changeset
2902 sync_stack_slots(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
2903
a61af66fc99e Initial load
duke
parents:
diff changeset
2904 // Compiled code's Frame Pointer
a61af66fc99e Initial load
duke
parents:
diff changeset
2905 frame_pointer(RSP);
a61af66fc99e Initial load
duke
parents:
diff changeset
2906
a61af66fc99e Initial load
duke
parents:
diff changeset
2907 // Interpreter stores its frame pointer in a register which is
a61af66fc99e Initial load
duke
parents:
diff changeset
2908 // stored to the stack by I2CAdaptors.
a61af66fc99e Initial load
duke
parents:
diff changeset
2909 // I2CAdaptors convert from interpreted java to compiled java.
a61af66fc99e Initial load
duke
parents:
diff changeset
2910 interpreter_frame_pointer(RBP);
a61af66fc99e Initial load
duke
parents:
diff changeset
2911
a61af66fc99e Initial load
duke
parents:
diff changeset
2912 // Stack alignment requirement
a61af66fc99e Initial load
duke
parents:
diff changeset
2913 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
a61af66fc99e Initial load
duke
parents:
diff changeset
2914
a61af66fc99e Initial load
duke
parents:
diff changeset
2915 // Number of stack slots between incoming argument block and the start of
a61af66fc99e Initial load
duke
parents:
diff changeset
2916 // a new frame. The PROLOG must add this many slots to the stack. The
a61af66fc99e Initial load
duke
parents:
diff changeset
2917 // EPILOG must remove this many slots. amd64 needs two slots for
a61af66fc99e Initial load
duke
parents:
diff changeset
2918 // return address.
a61af66fc99e Initial load
duke
parents:
diff changeset
2919 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
a61af66fc99e Initial load
duke
parents:
diff changeset
2920
a61af66fc99e Initial load
duke
parents:
diff changeset
2921 // Number of outgoing stack slots killed above the out_preserve_stack_slots
a61af66fc99e Initial load
duke
parents:
diff changeset
2922 // for calls to C. Supports the var-args backing area for register parms.
a61af66fc99e Initial load
duke
parents:
diff changeset
2923 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
a61af66fc99e Initial load
duke
parents:
diff changeset
2924
a61af66fc99e Initial load
duke
parents:
diff changeset
2925 // The after-PROLOG location of the return address. Location of
a61af66fc99e Initial load
duke
parents:
diff changeset
2926 // return address specifies a type (REG or STACK) and a number
a61af66fc99e Initial load
duke
parents:
diff changeset
2927 // representing the register number (i.e. - use a register name) or
a61af66fc99e Initial load
duke
parents:
diff changeset
2928 // stack slot.
a61af66fc99e Initial load
duke
parents:
diff changeset
2929 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
a61af66fc99e Initial load
duke
parents:
diff changeset
2930 // Otherwise, it is above the locks and verification slot and alignment word
a61af66fc99e Initial load
duke
parents:
diff changeset
2931 return_addr(STACK - 2 +
4950
9b8ce46870df 7145346: VerifyStackAtCalls is broken
kvn
parents: 4947
diff changeset
2932 round_to((Compile::current()->in_preserve_stack_slots() +
9b8ce46870df 7145346: VerifyStackAtCalls is broken
kvn
parents: 4947
diff changeset
2933 Compile::current()->fixed_slots()),
9b8ce46870df 7145346: VerifyStackAtCalls is broken
kvn
parents: 4947
diff changeset
2934 stack_alignment_in_slots()));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2935
a61af66fc99e Initial load
duke
parents:
diff changeset
2936 // Body of function which returns an integer array locating
a61af66fc99e Initial load
duke
parents:
diff changeset
2937 // arguments either in registers or in stack slots. Passed an array
a61af66fc99e Initial load
duke
parents:
diff changeset
2938 // of ideal registers called "sig" and a "length" count. Stack-slot
a61af66fc99e Initial load
duke
parents:
diff changeset
2939 // offsets are based on outgoing arguments, i.e. a CALLER setting up
a61af66fc99e Initial load
duke
parents:
diff changeset
2940 // arguments for a CALLEE. Incoming stack arguments are
a61af66fc99e Initial load
duke
parents:
diff changeset
2941 // automatically biased by the preserve_stack_slots field above.
a61af66fc99e Initial load
duke
parents:
diff changeset
2942
a61af66fc99e Initial load
duke
parents:
diff changeset
2943 calling_convention
a61af66fc99e Initial load
duke
parents:
diff changeset
2944 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2945 // No difference between ingoing/outgoing just pass false
a61af66fc99e Initial load
duke
parents:
diff changeset
2946 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
a61af66fc99e Initial load
duke
parents:
diff changeset
2947 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2948
a61af66fc99e Initial load
duke
parents:
diff changeset
2949 c_calling_convention
a61af66fc99e Initial load
duke
parents:
diff changeset
2950 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2951 // This is obviously always outgoing
a61af66fc99e Initial load
duke
parents:
diff changeset
2952 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
a61af66fc99e Initial load
duke
parents:
diff changeset
2953 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2954
a61af66fc99e Initial load
duke
parents:
diff changeset
2955 // Location of compiled Java return values. Same as C for now.
a61af66fc99e Initial load
duke
parents:
diff changeset
2956 return_value
a61af66fc99e Initial load
duke
parents:
diff changeset
2957 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
2958 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
a61af66fc99e Initial load
duke
parents:
diff changeset
2959 "only return normal values");
a61af66fc99e Initial load
duke
parents:
diff changeset
2960
a61af66fc99e Initial load
duke
parents:
diff changeset
2961 static const int lo[Op_RegL + 1] = {
a61af66fc99e Initial load
duke
parents:
diff changeset
2962 0,
a61af66fc99e Initial load
duke
parents:
diff changeset
2963 0,
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
2964 RAX_num, // Op_RegN
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2965 RAX_num, // Op_RegI
a61af66fc99e Initial load
duke
parents:
diff changeset
2966 RAX_num, // Op_RegP
a61af66fc99e Initial load
duke
parents:
diff changeset
2967 XMM0_num, // Op_RegF
a61af66fc99e Initial load
duke
parents:
diff changeset
2968 XMM0_num, // Op_RegD
a61af66fc99e Initial load
duke
parents:
diff changeset
2969 RAX_num // Op_RegL
a61af66fc99e Initial load
duke
parents:
diff changeset
2970 };
a61af66fc99e Initial load
duke
parents:
diff changeset
2971 static const int hi[Op_RegL + 1] = {
a61af66fc99e Initial load
duke
parents:
diff changeset
2972 0,
a61af66fc99e Initial load
duke
parents:
diff changeset
2973 0,
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
2974 OptoReg::Bad, // Op_RegN
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2975 OptoReg::Bad, // Op_RegI
a61af66fc99e Initial load
duke
parents:
diff changeset
2976 RAX_H_num, // Op_RegP
a61af66fc99e Initial load
duke
parents:
diff changeset
2977 OptoReg::Bad, // Op_RegF
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
2978 XMM0b_num, // Op_RegD
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2979 RAX_H_num // Op_RegL
a61af66fc99e Initial load
duke
parents:
diff changeset
2980 };
6179
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
2981 // Excluded flags and vector registers.
8c92982cbbc4 7119644: Increase superword's vector size up to 256 bits
kvn
parents: 6143
diff changeset
2982 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 5, "missing type");
0
a61af66fc99e Initial load
duke
parents:
diff changeset
2983 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
a61af66fc99e Initial load
duke
parents:
diff changeset
2984 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2985 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
2986
a61af66fc99e Initial load
duke
parents:
diff changeset
2987 //----------ATTRIBUTES---------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
2988 //----------Operand Attributes-------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
2989 op_attrib op_cost(0); // Required cost attribute
a61af66fc99e Initial load
duke
parents:
diff changeset
2990
a61af66fc99e Initial load
duke
parents:
diff changeset
2991 //----------Instruction Attributes---------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
2992 ins_attrib ins_cost(100); // Required cost attribute
a61af66fc99e Initial load
duke
parents:
diff changeset
2993 ins_attrib ins_size(8); // Required size attribute (in bits)
a61af66fc99e Initial load
duke
parents:
diff changeset
2994 ins_attrib ins_short_branch(0); // Required flag: is this instruction
a61af66fc99e Initial load
duke
parents:
diff changeset
2995 // a non-matching short branch variant
a61af66fc99e Initial load
duke
parents:
diff changeset
2996 // of some long branch?
a61af66fc99e Initial load
duke
parents:
diff changeset
2997 ins_attrib ins_alignment(1); // Required alignment attribute (must
a61af66fc99e Initial load
duke
parents:
diff changeset
2998 // be a power of 2) specifies the
a61af66fc99e Initial load
duke
parents:
diff changeset
2999 // alignment that some part of the
a61af66fc99e Initial load
duke
parents:
diff changeset
3000 // instruction (not necessarily the
a61af66fc99e Initial load
duke
parents:
diff changeset
3001 // start) requires. If > 1, a
a61af66fc99e Initial load
duke
parents:
diff changeset
3002 // compute_padding() function must be
a61af66fc99e Initial load
duke
parents:
diff changeset
3003 // provided for the instruction
a61af66fc99e Initial load
duke
parents:
diff changeset
3004
a61af66fc99e Initial load
duke
parents:
diff changeset
3005 //----------OPERANDS-----------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
3006 // Operand definitions must precede instruction definitions for correct parsing
a61af66fc99e Initial load
duke
parents:
diff changeset
3007 // in the ADLC because operands constitute user defined types which are used in
a61af66fc99e Initial load
duke
parents:
diff changeset
3008 // instruction definitions.
a61af66fc99e Initial load
duke
parents:
diff changeset
3009
a61af66fc99e Initial load
duke
parents:
diff changeset
3010 //----------Simple Operands----------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
3011 // Immediate Operands
a61af66fc99e Initial load
duke
parents:
diff changeset
3012 // Integer Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
3013 operand immI()
a61af66fc99e Initial load
duke
parents:
diff changeset
3014 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3015 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3016
a61af66fc99e Initial load
duke
parents:
diff changeset
3017 op_cost(10);
a61af66fc99e Initial load
duke
parents:
diff changeset
3018 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3019 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3020 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3021
a61af66fc99e Initial load
duke
parents:
diff changeset
3022 // Constant for test vs zero
a61af66fc99e Initial load
duke
parents:
diff changeset
3023 operand immI0()
a61af66fc99e Initial load
duke
parents:
diff changeset
3024 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3025 predicate(n->get_int() == 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3026 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3027
a61af66fc99e Initial load
duke
parents:
diff changeset
3028 op_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3029 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3030 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3031 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3032
a61af66fc99e Initial load
duke
parents:
diff changeset
3033 // Constant for increment
a61af66fc99e Initial load
duke
parents:
diff changeset
3034 operand immI1()
a61af66fc99e Initial load
duke
parents:
diff changeset
3035 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3036 predicate(n->get_int() == 1);
a61af66fc99e Initial load
duke
parents:
diff changeset
3037 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3038
a61af66fc99e Initial load
duke
parents:
diff changeset
3039 op_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3040 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3041 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3042 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3043
a61af66fc99e Initial load
duke
parents:
diff changeset
3044 // Constant for decrement
a61af66fc99e Initial load
duke
parents:
diff changeset
3045 operand immI_M1()
a61af66fc99e Initial load
duke
parents:
diff changeset
3046 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3047 predicate(n->get_int() == -1);
a61af66fc99e Initial load
duke
parents:
diff changeset
3048 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3049
a61af66fc99e Initial load
duke
parents:
diff changeset
3050 op_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3051 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3052 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3053 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3054
a61af66fc99e Initial load
duke
parents:
diff changeset
3055 // Valid scale values for addressing modes
a61af66fc99e Initial load
duke
parents:
diff changeset
3056 operand immI2()
a61af66fc99e Initial load
duke
parents:
diff changeset
3057 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3058 predicate(0 <= n->get_int() && (n->get_int() <= 3));
a61af66fc99e Initial load
duke
parents:
diff changeset
3059 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3060
a61af66fc99e Initial load
duke
parents:
diff changeset
3061 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3062 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3063 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3064
a61af66fc99e Initial load
duke
parents:
diff changeset
3065 operand immI8()
a61af66fc99e Initial load
duke
parents:
diff changeset
3066 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3067 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
a61af66fc99e Initial load
duke
parents:
diff changeset
3068 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3069
a61af66fc99e Initial load
duke
parents:
diff changeset
3070 op_cost(5);
a61af66fc99e Initial load
duke
parents:
diff changeset
3071 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3072 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3073 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3074
a61af66fc99e Initial load
duke
parents:
diff changeset
3075 operand immI16()
a61af66fc99e Initial load
duke
parents:
diff changeset
3076 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3077 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
a61af66fc99e Initial load
duke
parents:
diff changeset
3078 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3079
a61af66fc99e Initial load
duke
parents:
diff changeset
3080 op_cost(10);
a61af66fc99e Initial load
duke
parents:
diff changeset
3081 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3082 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3083 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3084
a61af66fc99e Initial load
duke
parents:
diff changeset
3085 // Constant for long shifts
a61af66fc99e Initial load
duke
parents:
diff changeset
3086 operand immI_32()
a61af66fc99e Initial load
duke
parents:
diff changeset
3087 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3088 predicate( n->get_int() == 32 );
a61af66fc99e Initial load
duke
parents:
diff changeset
3089 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3090
a61af66fc99e Initial load
duke
parents:
diff changeset
3091 op_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3092 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3093 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3094 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3095
a61af66fc99e Initial load
duke
parents:
diff changeset
3096 // Constant for long shifts
a61af66fc99e Initial load
duke
parents:
diff changeset
3097 operand immI_64()
a61af66fc99e Initial load
duke
parents:
diff changeset
3098 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3099 predicate( n->get_int() == 64 );
a61af66fc99e Initial load
duke
parents:
diff changeset
3100 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3101
a61af66fc99e Initial load
duke
parents:
diff changeset
3102 op_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3103 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3104 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3105 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3106
a61af66fc99e Initial load
duke
parents:
diff changeset
3107 // Pointer Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
3108 operand immP()
a61af66fc99e Initial load
duke
parents:
diff changeset
3109 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3110 match(ConP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3111
a61af66fc99e Initial load
duke
parents:
diff changeset
3112 op_cost(10);
a61af66fc99e Initial load
duke
parents:
diff changeset
3113 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3114 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3115 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3116
a61af66fc99e Initial load
duke
parents:
diff changeset
3117 // NULL Pointer Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
3118 operand immP0()
a61af66fc99e Initial load
duke
parents:
diff changeset
3119 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3120 predicate(n->get_ptr() == 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3121 match(ConP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3122
a61af66fc99e Initial load
duke
parents:
diff changeset
3123 op_cost(5);
a61af66fc99e Initial load
duke
parents:
diff changeset
3124 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3125 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3126 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3127
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3128 // Pointer Immediate
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3129 operand immN() %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3130 match(ConN);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3131
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3132 op_cost(10);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3133 format %{ %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3134 interface(CONST_INTER);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3135 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3136
6848
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
3137 operand immNKlass() %{
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
3138 match(ConNKlass);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
3139
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
3140 op_cost(10);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
3141 format %{ %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
3142 interface(CONST_INTER);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
3143 %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
3144
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3145 // NULL Pointer Immediate
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3146 operand immN0() %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3147 predicate(n->get_narrowcon() == 0);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3148 match(ConN);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3149
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3150 op_cost(5);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3151 format %{ %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3152 interface(CONST_INTER);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3153 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3154
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3155 operand immP31()
a61af66fc99e Initial load
duke
parents:
diff changeset
3156 %{
6725
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 6614
diff changeset
3157 predicate(n->as_Type()->type()->reloc() == relocInfo::none
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3158 && (n->get_ptr() >> 31) == 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3159 match(ConP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3160
a61af66fc99e Initial load
duke
parents:
diff changeset
3161 op_cost(5);
a61af66fc99e Initial load
duke
parents:
diff changeset
3162 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3163 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3164 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3165
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3166
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3167 // Long Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
3168 operand immL()
a61af66fc99e Initial load
duke
parents:
diff changeset
3169 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3170 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3171
a61af66fc99e Initial load
duke
parents:
diff changeset
3172 op_cost(20);
a61af66fc99e Initial load
duke
parents:
diff changeset
3173 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3174 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3175 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3176
a61af66fc99e Initial load
duke
parents:
diff changeset
3177 // Long Immediate 8-bit
a61af66fc99e Initial load
duke
parents:
diff changeset
3178 operand immL8()
a61af66fc99e Initial load
duke
parents:
diff changeset
3179 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3180 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
a61af66fc99e Initial load
duke
parents:
diff changeset
3181 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3182
a61af66fc99e Initial load
duke
parents:
diff changeset
3183 op_cost(5);
a61af66fc99e Initial load
duke
parents:
diff changeset
3184 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3185 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3186 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3187
a61af66fc99e Initial load
duke
parents:
diff changeset
3188 // Long Immediate 32-bit unsigned
a61af66fc99e Initial load
duke
parents:
diff changeset
3189 operand immUL32()
a61af66fc99e Initial load
duke
parents:
diff changeset
3190 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3191 predicate(n->get_long() == (unsigned int) (n->get_long()));
a61af66fc99e Initial load
duke
parents:
diff changeset
3192 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3193
a61af66fc99e Initial load
duke
parents:
diff changeset
3194 op_cost(10);
a61af66fc99e Initial load
duke
parents:
diff changeset
3195 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3196 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3197 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3198
a61af66fc99e Initial load
duke
parents:
diff changeset
3199 // Long Immediate 32-bit signed
a61af66fc99e Initial load
duke
parents:
diff changeset
3200 operand immL32()
a61af66fc99e Initial load
duke
parents:
diff changeset
3201 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3202 predicate(n->get_long() == (int) (n->get_long()));
a61af66fc99e Initial load
duke
parents:
diff changeset
3203 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3204
a61af66fc99e Initial load
duke
parents:
diff changeset
3205 op_cost(15);
a61af66fc99e Initial load
duke
parents:
diff changeset
3206 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3207 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3208 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3209
a61af66fc99e Initial load
duke
parents:
diff changeset
3210 // Long Immediate zero
a61af66fc99e Initial load
duke
parents:
diff changeset
3211 operand immL0()
a61af66fc99e Initial load
duke
parents:
diff changeset
3212 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3213 predicate(n->get_long() == 0L);
a61af66fc99e Initial load
duke
parents:
diff changeset
3214 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3215
a61af66fc99e Initial load
duke
parents:
diff changeset
3216 op_cost(10);
a61af66fc99e Initial load
duke
parents:
diff changeset
3217 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3218 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3219 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3220
a61af66fc99e Initial load
duke
parents:
diff changeset
3221 // Constant for increment
a61af66fc99e Initial load
duke
parents:
diff changeset
3222 operand immL1()
a61af66fc99e Initial load
duke
parents:
diff changeset
3223 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3224 predicate(n->get_long() == 1);
a61af66fc99e Initial load
duke
parents:
diff changeset
3225 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3226
a61af66fc99e Initial load
duke
parents:
diff changeset
3227 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3228 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3229 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3230
a61af66fc99e Initial load
duke
parents:
diff changeset
3231 // Constant for decrement
a61af66fc99e Initial load
duke
parents:
diff changeset
3232 operand immL_M1()
a61af66fc99e Initial load
duke
parents:
diff changeset
3233 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3234 predicate(n->get_long() == -1);
a61af66fc99e Initial load
duke
parents:
diff changeset
3235 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3236
a61af66fc99e Initial load
duke
parents:
diff changeset
3237 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3238 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3239 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3240
a61af66fc99e Initial load
duke
parents:
diff changeset
3241 // Long Immediate: the value 10
a61af66fc99e Initial load
duke
parents:
diff changeset
3242 operand immL10()
a61af66fc99e Initial load
duke
parents:
diff changeset
3243 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3244 predicate(n->get_long() == 10);
a61af66fc99e Initial load
duke
parents:
diff changeset
3245 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3246
a61af66fc99e Initial load
duke
parents:
diff changeset
3247 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3248 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3249 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3250
a61af66fc99e Initial load
duke
parents:
diff changeset
3251 // Long immediate from 0 to 127.
a61af66fc99e Initial load
duke
parents:
diff changeset
3252 // Used for a shorter form of long mul by 10.
a61af66fc99e Initial load
duke
parents:
diff changeset
3253 operand immL_127()
a61af66fc99e Initial load
duke
parents:
diff changeset
3254 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3255 predicate(0 <= n->get_long() && n->get_long() < 0x80);
a61af66fc99e Initial load
duke
parents:
diff changeset
3256 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3257
a61af66fc99e Initial load
duke
parents:
diff changeset
3258 op_cost(10);
a61af66fc99e Initial load
duke
parents:
diff changeset
3259 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3260 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3261 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3262
a61af66fc99e Initial load
duke
parents:
diff changeset
3263 // Long Immediate: low 32-bit mask
a61af66fc99e Initial load
duke
parents:
diff changeset
3264 operand immL_32bits()
a61af66fc99e Initial load
duke
parents:
diff changeset
3265 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3266 predicate(n->get_long() == 0xFFFFFFFFL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3267 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3268 op_cost(20);
a61af66fc99e Initial load
duke
parents:
diff changeset
3269
a61af66fc99e Initial load
duke
parents:
diff changeset
3270 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3271 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3272 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3273
a61af66fc99e Initial load
duke
parents:
diff changeset
3274 // Float Immediate zero
a61af66fc99e Initial load
duke
parents:
diff changeset
3275 operand immF0()
a61af66fc99e Initial load
duke
parents:
diff changeset
3276 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3277 predicate(jint_cast(n->getf()) == 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3278 match(ConF);
a61af66fc99e Initial load
duke
parents:
diff changeset
3279
a61af66fc99e Initial load
duke
parents:
diff changeset
3280 op_cost(5);
a61af66fc99e Initial load
duke
parents:
diff changeset
3281 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3282 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3283 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3284
a61af66fc99e Initial load
duke
parents:
diff changeset
3285 // Float Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
3286 operand immF()
a61af66fc99e Initial load
duke
parents:
diff changeset
3287 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3288 match(ConF);
a61af66fc99e Initial load
duke
parents:
diff changeset
3289
a61af66fc99e Initial load
duke
parents:
diff changeset
3290 op_cost(15);
a61af66fc99e Initial load
duke
parents:
diff changeset
3291 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3292 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3293 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3294
a61af66fc99e Initial load
duke
parents:
diff changeset
3295 // Double Immediate zero
a61af66fc99e Initial load
duke
parents:
diff changeset
3296 operand immD0()
a61af66fc99e Initial load
duke
parents:
diff changeset
3297 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3298 predicate(jlong_cast(n->getd()) == 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3299 match(ConD);
a61af66fc99e Initial load
duke
parents:
diff changeset
3300
a61af66fc99e Initial load
duke
parents:
diff changeset
3301 op_cost(5);
a61af66fc99e Initial load
duke
parents:
diff changeset
3302 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3303 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3304 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3305
a61af66fc99e Initial load
duke
parents:
diff changeset
3306 // Double Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
3307 operand immD()
a61af66fc99e Initial load
duke
parents:
diff changeset
3308 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3309 match(ConD);
a61af66fc99e Initial load
duke
parents:
diff changeset
3310
a61af66fc99e Initial load
duke
parents:
diff changeset
3311 op_cost(15);
a61af66fc99e Initial load
duke
parents:
diff changeset
3312 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3313 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3314 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3315
a61af66fc99e Initial load
duke
parents:
diff changeset
3316 // Immediates for special shifts (sign extend)
a61af66fc99e Initial load
duke
parents:
diff changeset
3317
a61af66fc99e Initial load
duke
parents:
diff changeset
3318 // Constants for increment
a61af66fc99e Initial load
duke
parents:
diff changeset
3319 operand immI_16()
a61af66fc99e Initial load
duke
parents:
diff changeset
3320 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3321 predicate(n->get_int() == 16);
a61af66fc99e Initial load
duke
parents:
diff changeset
3322 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3323
a61af66fc99e Initial load
duke
parents:
diff changeset
3324 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3325 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3326 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3327
a61af66fc99e Initial load
duke
parents:
diff changeset
3328 operand immI_24()
a61af66fc99e Initial load
duke
parents:
diff changeset
3329 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3330 predicate(n->get_int() == 24);
a61af66fc99e Initial load
duke
parents:
diff changeset
3331 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3332
a61af66fc99e Initial load
duke
parents:
diff changeset
3333 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3334 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3335 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3336
a61af66fc99e Initial load
duke
parents:
diff changeset
3337 // Constant for byte-wide masking
a61af66fc99e Initial load
duke
parents:
diff changeset
3338 operand immI_255()
a61af66fc99e Initial load
duke
parents:
diff changeset
3339 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3340 predicate(n->get_int() == 255);
a61af66fc99e Initial load
duke
parents:
diff changeset
3341 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3342
a61af66fc99e Initial load
duke
parents:
diff changeset
3343 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3344 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3345 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3346
a61af66fc99e Initial load
duke
parents:
diff changeset
3347 // Constant for short-wide masking
a61af66fc99e Initial load
duke
parents:
diff changeset
3348 operand immI_65535()
a61af66fc99e Initial load
duke
parents:
diff changeset
3349 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3350 predicate(n->get_int() == 65535);
a61af66fc99e Initial load
duke
parents:
diff changeset
3351 match(ConI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3352
a61af66fc99e Initial load
duke
parents:
diff changeset
3353 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3354 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3355 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3356
a61af66fc99e Initial load
duke
parents:
diff changeset
3357 // Constant for byte-wide masking
a61af66fc99e Initial load
duke
parents:
diff changeset
3358 operand immL_255()
a61af66fc99e Initial load
duke
parents:
diff changeset
3359 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3360 predicate(n->get_long() == 255);
a61af66fc99e Initial load
duke
parents:
diff changeset
3361 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3362
a61af66fc99e Initial load
duke
parents:
diff changeset
3363 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3364 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3365 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3366
a61af66fc99e Initial load
duke
parents:
diff changeset
3367 // Constant for short-wide masking
a61af66fc99e Initial load
duke
parents:
diff changeset
3368 operand immL_65535()
a61af66fc99e Initial load
duke
parents:
diff changeset
3369 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3370 predicate(n->get_long() == 65535);
a61af66fc99e Initial load
duke
parents:
diff changeset
3371 match(ConL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3372
a61af66fc99e Initial load
duke
parents:
diff changeset
3373 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3374 interface(CONST_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3375 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3376
a61af66fc99e Initial load
duke
parents:
diff changeset
3377 // Register Operands
a61af66fc99e Initial load
duke
parents:
diff changeset
3378 // Integer Register
a61af66fc99e Initial load
duke
parents:
diff changeset
3379 operand rRegI()
a61af66fc99e Initial load
duke
parents:
diff changeset
3380 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3381 constraint(ALLOC_IN_RC(int_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3382 match(RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3383
a61af66fc99e Initial load
duke
parents:
diff changeset
3384 match(rax_RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3385 match(rbx_RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3386 match(rcx_RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3387 match(rdx_RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3388 match(rdi_RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3389
a61af66fc99e Initial load
duke
parents:
diff changeset
3390 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3391 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3392 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3393
a61af66fc99e Initial load
duke
parents:
diff changeset
3394 // Special Registers
a61af66fc99e Initial load
duke
parents:
diff changeset
3395 operand rax_RegI()
a61af66fc99e Initial load
duke
parents:
diff changeset
3396 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3397 constraint(ALLOC_IN_RC(int_rax_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3398 match(RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3399 match(rRegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3400
a61af66fc99e Initial load
duke
parents:
diff changeset
3401 format %{ "RAX" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3402 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3403 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3404
a61af66fc99e Initial load
duke
parents:
diff changeset
3405 // Special Registers
a61af66fc99e Initial load
duke
parents:
diff changeset
3406 operand rbx_RegI()
a61af66fc99e Initial load
duke
parents:
diff changeset
3407 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3408 constraint(ALLOC_IN_RC(int_rbx_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3409 match(RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3410 match(rRegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3411
a61af66fc99e Initial load
duke
parents:
diff changeset
3412 format %{ "RBX" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3413 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3414 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3415
a61af66fc99e Initial load
duke
parents:
diff changeset
3416 operand rcx_RegI()
a61af66fc99e Initial load
duke
parents:
diff changeset
3417 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3418 constraint(ALLOC_IN_RC(int_rcx_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3419 match(RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3420 match(rRegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3421
a61af66fc99e Initial load
duke
parents:
diff changeset
3422 format %{ "RCX" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3423 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3424 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3425
a61af66fc99e Initial load
duke
parents:
diff changeset
3426 operand rdx_RegI()
a61af66fc99e Initial load
duke
parents:
diff changeset
3427 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3428 constraint(ALLOC_IN_RC(int_rdx_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3429 match(RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3430 match(rRegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3431
a61af66fc99e Initial load
duke
parents:
diff changeset
3432 format %{ "RDX" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3433 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3434 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3435
a61af66fc99e Initial load
duke
parents:
diff changeset
3436 operand rdi_RegI()
a61af66fc99e Initial load
duke
parents:
diff changeset
3437 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3438 constraint(ALLOC_IN_RC(int_rdi_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3439 match(RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3440 match(rRegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3441
a61af66fc99e Initial load
duke
parents:
diff changeset
3442 format %{ "RDI" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3443 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3444 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3445
a61af66fc99e Initial load
duke
parents:
diff changeset
3446 operand no_rcx_RegI()
a61af66fc99e Initial load
duke
parents:
diff changeset
3447 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3448 constraint(ALLOC_IN_RC(int_no_rcx_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3449 match(RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3450 match(rax_RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3451 match(rbx_RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3452 match(rdx_RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3453 match(rdi_RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3454
a61af66fc99e Initial load
duke
parents:
diff changeset
3455 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3456 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3457 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3458
a61af66fc99e Initial load
duke
parents:
diff changeset
3459 operand no_rax_rdx_RegI()
a61af66fc99e Initial load
duke
parents:
diff changeset
3460 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3461 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3462 match(RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3463 match(rbx_RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3464 match(rcx_RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3465 match(rdi_RegI);
a61af66fc99e Initial load
duke
parents:
diff changeset
3466
a61af66fc99e Initial load
duke
parents:
diff changeset
3467 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3468 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3469 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3470
a61af66fc99e Initial load
duke
parents:
diff changeset
3471 // Pointer Register
a61af66fc99e Initial load
duke
parents:
diff changeset
3472 operand any_RegP()
a61af66fc99e Initial load
duke
parents:
diff changeset
3473 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3474 constraint(ALLOC_IN_RC(any_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3475 match(RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3476 match(rax_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3477 match(rbx_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3478 match(rdi_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3479 match(rsi_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3480 match(rbp_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3481 match(r15_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3482 match(rRegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3483
a61af66fc99e Initial load
duke
parents:
diff changeset
3484 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3485 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3486 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3487
a61af66fc99e Initial load
duke
parents:
diff changeset
3488 operand rRegP()
a61af66fc99e Initial load
duke
parents:
diff changeset
3489 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3490 constraint(ALLOC_IN_RC(ptr_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3491 match(RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3492 match(rax_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3493 match(rbx_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3494 match(rdi_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3495 match(rsi_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3496 match(rbp_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3497 match(r15_RegP); // See Q&A below about r15_RegP.
a61af66fc99e Initial load
duke
parents:
diff changeset
3498
a61af66fc99e Initial load
duke
parents:
diff changeset
3499 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3500 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3501 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3502
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3503 operand rRegN() %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3504 constraint(ALLOC_IN_RC(int_reg));
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3505 match(RegN);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3506
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3507 format %{ %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3508 interface(REG_INTER);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3509 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3510
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3511 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
a61af66fc99e Initial load
duke
parents:
diff changeset
3512 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
a61af66fc99e Initial load
duke
parents:
diff changeset
3513 // It's fine for an instruction input which expects rRegP to match a r15_RegP.
a61af66fc99e Initial load
duke
parents:
diff changeset
3514 // The output of an instruction is controlled by the allocator, which respects
a61af66fc99e Initial load
duke
parents:
diff changeset
3515 // register class masks, not match rules. Unless an instruction mentions
a61af66fc99e Initial load
duke
parents:
diff changeset
3516 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
a61af66fc99e Initial load
duke
parents:
diff changeset
3517 // by the allocator as an input.
a61af66fc99e Initial load
duke
parents:
diff changeset
3518
a61af66fc99e Initial load
duke
parents:
diff changeset
3519 operand no_rax_RegP()
a61af66fc99e Initial load
duke
parents:
diff changeset
3520 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3521 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3522 match(RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3523 match(rbx_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3524 match(rsi_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3525 match(rdi_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3526
a61af66fc99e Initial load
duke
parents:
diff changeset
3527 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3528 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3529 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3530
a61af66fc99e Initial load
duke
parents:
diff changeset
3531 operand no_rbp_RegP()
a61af66fc99e Initial load
duke
parents:
diff changeset
3532 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3533 constraint(ALLOC_IN_RC(ptr_no_rbp_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3534 match(RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3535 match(rbx_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3536 match(rsi_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3537 match(rdi_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3538
a61af66fc99e Initial load
duke
parents:
diff changeset
3539 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3540 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3541 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3542
a61af66fc99e Initial load
duke
parents:
diff changeset
3543 operand no_rax_rbx_RegP()
a61af66fc99e Initial load
duke
parents:
diff changeset
3544 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3545 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3546 match(RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3547 match(rsi_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3548 match(rdi_RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3549
a61af66fc99e Initial load
duke
parents:
diff changeset
3550 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3551 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3552 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3553
a61af66fc99e Initial load
duke
parents:
diff changeset
3554 // Special Registers
a61af66fc99e Initial load
duke
parents:
diff changeset
3555 // Return a pointer value
a61af66fc99e Initial load
duke
parents:
diff changeset
3556 operand rax_RegP()
a61af66fc99e Initial load
duke
parents:
diff changeset
3557 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3558 constraint(ALLOC_IN_RC(ptr_rax_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3559 match(RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3560 match(rRegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3561
a61af66fc99e Initial load
duke
parents:
diff changeset
3562 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3563 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3564 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3565
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3566 // Special Registers
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3567 // Return a compressed pointer value
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3568 operand rax_RegN()
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3569 %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3570 constraint(ALLOC_IN_RC(int_rax_reg));
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3571 match(RegN);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3572 match(rRegN);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3573
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3574 format %{ %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3575 interface(REG_INTER);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3576 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
3577
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3578 // Used in AtomicAdd
a61af66fc99e Initial load
duke
parents:
diff changeset
3579 operand rbx_RegP()
a61af66fc99e Initial load
duke
parents:
diff changeset
3580 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3581 constraint(ALLOC_IN_RC(ptr_rbx_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3582 match(RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3583 match(rRegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3584
a61af66fc99e Initial load
duke
parents:
diff changeset
3585 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3586 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3587 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3588
a61af66fc99e Initial load
duke
parents:
diff changeset
3589 operand rsi_RegP()
a61af66fc99e Initial load
duke
parents:
diff changeset
3590 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3591 constraint(ALLOC_IN_RC(ptr_rsi_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3592 match(RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3593 match(rRegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3594
a61af66fc99e Initial load
duke
parents:
diff changeset
3595 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3596 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3597 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3598
a61af66fc99e Initial load
duke
parents:
diff changeset
3599 // Used in rep stosq
a61af66fc99e Initial load
duke
parents:
diff changeset
3600 operand rdi_RegP()
a61af66fc99e Initial load
duke
parents:
diff changeset
3601 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3602 constraint(ALLOC_IN_RC(ptr_rdi_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3603 match(RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3604 match(rRegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3605
a61af66fc99e Initial load
duke
parents:
diff changeset
3606 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3607 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3608 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3609
a61af66fc99e Initial load
duke
parents:
diff changeset
3610 operand rbp_RegP()
a61af66fc99e Initial load
duke
parents:
diff changeset
3611 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3612 constraint(ALLOC_IN_RC(ptr_rbp_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3613 match(RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3614 match(rRegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3615
a61af66fc99e Initial load
duke
parents:
diff changeset
3616 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3617 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3618 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3619
a61af66fc99e Initial load
duke
parents:
diff changeset
3620 operand r15_RegP()
a61af66fc99e Initial load
duke
parents:
diff changeset
3621 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3622 constraint(ALLOC_IN_RC(ptr_r15_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3623 match(RegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3624 match(rRegP);
a61af66fc99e Initial load
duke
parents:
diff changeset
3625
a61af66fc99e Initial load
duke
parents:
diff changeset
3626 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3627 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3628 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3629
a61af66fc99e Initial load
duke
parents:
diff changeset
3630 operand rRegL()
a61af66fc99e Initial load
duke
parents:
diff changeset
3631 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3632 constraint(ALLOC_IN_RC(long_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3633 match(RegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3634 match(rax_RegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3635 match(rdx_RegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3636
a61af66fc99e Initial load
duke
parents:
diff changeset
3637 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3638 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3639 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3640
a61af66fc99e Initial load
duke
parents:
diff changeset
3641 // Special Registers
a61af66fc99e Initial load
duke
parents:
diff changeset
3642 operand no_rax_rdx_RegL()
a61af66fc99e Initial load
duke
parents:
diff changeset
3643 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3644 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3645 match(RegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3646 match(rRegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3647
a61af66fc99e Initial load
duke
parents:
diff changeset
3648 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3649 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3650 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3651
a61af66fc99e Initial load
duke
parents:
diff changeset
3652 operand no_rax_RegL()
a61af66fc99e Initial load
duke
parents:
diff changeset
3653 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3654 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3655 match(RegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3656 match(rRegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3657 match(rdx_RegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3658
a61af66fc99e Initial load
duke
parents:
diff changeset
3659 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3660 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3661 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3662
a61af66fc99e Initial load
duke
parents:
diff changeset
3663 operand no_rcx_RegL()
a61af66fc99e Initial load
duke
parents:
diff changeset
3664 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3665 constraint(ALLOC_IN_RC(long_no_rcx_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3666 match(RegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3667 match(rRegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3668
a61af66fc99e Initial load
duke
parents:
diff changeset
3669 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3670 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3671 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3672
a61af66fc99e Initial load
duke
parents:
diff changeset
3673 operand rax_RegL()
a61af66fc99e Initial load
duke
parents:
diff changeset
3674 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3675 constraint(ALLOC_IN_RC(long_rax_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3676 match(RegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3677 match(rRegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3678
a61af66fc99e Initial load
duke
parents:
diff changeset
3679 format %{ "RAX" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3680 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3681 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3682
a61af66fc99e Initial load
duke
parents:
diff changeset
3683 operand rcx_RegL()
a61af66fc99e Initial load
duke
parents:
diff changeset
3684 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3685 constraint(ALLOC_IN_RC(long_rcx_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3686 match(RegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3687 match(rRegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3688
a61af66fc99e Initial load
duke
parents:
diff changeset
3689 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3690 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3691 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3692
a61af66fc99e Initial load
duke
parents:
diff changeset
3693 operand rdx_RegL()
a61af66fc99e Initial load
duke
parents:
diff changeset
3694 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3695 constraint(ALLOC_IN_RC(long_rdx_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3696 match(RegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3697 match(rRegL);
a61af66fc99e Initial load
duke
parents:
diff changeset
3698
a61af66fc99e Initial load
duke
parents:
diff changeset
3699 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3700 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3701 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3702
a61af66fc99e Initial load
duke
parents:
diff changeset
3703 // Flags register, used as output of compare instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
3704 operand rFlagsReg()
a61af66fc99e Initial load
duke
parents:
diff changeset
3705 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3706 constraint(ALLOC_IN_RC(int_flags));
a61af66fc99e Initial load
duke
parents:
diff changeset
3707 match(RegFlags);
a61af66fc99e Initial load
duke
parents:
diff changeset
3708
a61af66fc99e Initial load
duke
parents:
diff changeset
3709 format %{ "RFLAGS" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3710 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3711 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3712
a61af66fc99e Initial load
duke
parents:
diff changeset
3713 // Flags register, used as output of FLOATING POINT compare instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
3714 operand rFlagsRegU()
a61af66fc99e Initial load
duke
parents:
diff changeset
3715 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3716 constraint(ALLOC_IN_RC(int_flags));
a61af66fc99e Initial load
duke
parents:
diff changeset
3717 match(RegFlags);
a61af66fc99e Initial load
duke
parents:
diff changeset
3718
a61af66fc99e Initial load
duke
parents:
diff changeset
3719 format %{ "RFLAGS_U" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3720 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3721 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3722
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
3723 operand rFlagsRegUCF() %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
3724 constraint(ALLOC_IN_RC(int_flags));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
3725 match(RegFlags);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
3726 predicate(false);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
3727
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
3728 format %{ "RFLAGS_U_CF" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
3729 interface(REG_INTER);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
3730 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
3731
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3732 // Float register operands
a61af66fc99e Initial load
duke
parents:
diff changeset
3733 operand regF()
a61af66fc99e Initial load
duke
parents:
diff changeset
3734 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3735 constraint(ALLOC_IN_RC(float_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3736 match(RegF);
a61af66fc99e Initial load
duke
parents:
diff changeset
3737
a61af66fc99e Initial load
duke
parents:
diff changeset
3738 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3739 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3740 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3741
a61af66fc99e Initial load
duke
parents:
diff changeset
3742 // Double register operands
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
3743 operand regD()
0
a61af66fc99e Initial load
duke
parents:
diff changeset
3744 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3745 constraint(ALLOC_IN_RC(double_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3746 match(RegD);
a61af66fc99e Initial load
duke
parents:
diff changeset
3747
a61af66fc99e Initial load
duke
parents:
diff changeset
3748 format %{ %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3749 interface(REG_INTER);
a61af66fc99e Initial load
duke
parents:
diff changeset
3750 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3751
a61af66fc99e Initial load
duke
parents:
diff changeset
3752 //----------Memory Operands----------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
3753 // Direct Memory Operand
a61af66fc99e Initial load
duke
parents:
diff changeset
3754 // operand direct(immP addr)
a61af66fc99e Initial load
duke
parents:
diff changeset
3755 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3756 // match(addr);
a61af66fc99e Initial load
duke
parents:
diff changeset
3757
a61af66fc99e Initial load
duke
parents:
diff changeset
3758 // format %{ "[$addr]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3759 // interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3760 // base(0xFFFFFFFF);
a61af66fc99e Initial load
duke
parents:
diff changeset
3761 // index(0x4);
a61af66fc99e Initial load
duke
parents:
diff changeset
3762 // scale(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3763 // disp($addr);
a61af66fc99e Initial load
duke
parents:
diff changeset
3764 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3765 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3766
a61af66fc99e Initial load
duke
parents:
diff changeset
3767 // Indirect Memory Operand
a61af66fc99e Initial load
duke
parents:
diff changeset
3768 operand indirect(any_RegP reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
3769 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3770 constraint(ALLOC_IN_RC(ptr_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3771 match(reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3772
a61af66fc99e Initial load
duke
parents:
diff changeset
3773 format %{ "[$reg]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3774 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3775 base($reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3776 index(0x4);
a61af66fc99e Initial load
duke
parents:
diff changeset
3777 scale(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3778 disp(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3779 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3780 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3781
a61af66fc99e Initial load
duke
parents:
diff changeset
3782 // Indirect Memory Plus Short Offset Operand
a61af66fc99e Initial load
duke
parents:
diff changeset
3783 operand indOffset8(any_RegP reg, immL8 off)
a61af66fc99e Initial load
duke
parents:
diff changeset
3784 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3785 constraint(ALLOC_IN_RC(ptr_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3786 match(AddP reg off);
a61af66fc99e Initial load
duke
parents:
diff changeset
3787
a61af66fc99e Initial load
duke
parents:
diff changeset
3788 format %{ "[$reg + $off (8-bit)]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3789 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3790 base($reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3791 index(0x4);
a61af66fc99e Initial load
duke
parents:
diff changeset
3792 scale(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3793 disp($off);
a61af66fc99e Initial load
duke
parents:
diff changeset
3794 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3795 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3796
a61af66fc99e Initial load
duke
parents:
diff changeset
3797 // Indirect Memory Plus Long Offset Operand
a61af66fc99e Initial load
duke
parents:
diff changeset
3798 operand indOffset32(any_RegP reg, immL32 off)
a61af66fc99e Initial load
duke
parents:
diff changeset
3799 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3800 constraint(ALLOC_IN_RC(ptr_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3801 match(AddP reg off);
a61af66fc99e Initial load
duke
parents:
diff changeset
3802
a61af66fc99e Initial load
duke
parents:
diff changeset
3803 format %{ "[$reg + $off (32-bit)]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3804 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3805 base($reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3806 index(0x4);
a61af66fc99e Initial load
duke
parents:
diff changeset
3807 scale(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3808 disp($off);
a61af66fc99e Initial load
duke
parents:
diff changeset
3809 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3810 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3811
a61af66fc99e Initial load
duke
parents:
diff changeset
3812 // Indirect Memory Plus Index Register Plus Offset Operand
a61af66fc99e Initial load
duke
parents:
diff changeset
3813 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
a61af66fc99e Initial load
duke
parents:
diff changeset
3814 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3815 constraint(ALLOC_IN_RC(ptr_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3816 match(AddP (AddP reg lreg) off);
a61af66fc99e Initial load
duke
parents:
diff changeset
3817
a61af66fc99e Initial load
duke
parents:
diff changeset
3818 op_cost(10);
a61af66fc99e Initial load
duke
parents:
diff changeset
3819 format %{"[$reg + $off + $lreg]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3820 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3821 base($reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3822 index($lreg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3823 scale(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3824 disp($off);
a61af66fc99e Initial load
duke
parents:
diff changeset
3825 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3826 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3827
a61af66fc99e Initial load
duke
parents:
diff changeset
3828 // Indirect Memory Plus Index Register Plus Offset Operand
a61af66fc99e Initial load
duke
parents:
diff changeset
3829 operand indIndex(any_RegP reg, rRegL lreg)
a61af66fc99e Initial load
duke
parents:
diff changeset
3830 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3831 constraint(ALLOC_IN_RC(ptr_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3832 match(AddP reg lreg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3833
a61af66fc99e Initial load
duke
parents:
diff changeset
3834 op_cost(10);
a61af66fc99e Initial load
duke
parents:
diff changeset
3835 format %{"[$reg + $lreg]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3836 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3837 base($reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3838 index($lreg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3839 scale(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3840 disp(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3841 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3842 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3843
a61af66fc99e Initial load
duke
parents:
diff changeset
3844 // Indirect Memory Times Scale Plus Index Register
a61af66fc99e Initial load
duke
parents:
diff changeset
3845 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
a61af66fc99e Initial load
duke
parents:
diff changeset
3846 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3847 constraint(ALLOC_IN_RC(ptr_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3848 match(AddP reg (LShiftL lreg scale));
a61af66fc99e Initial load
duke
parents:
diff changeset
3849
a61af66fc99e Initial load
duke
parents:
diff changeset
3850 op_cost(10);
a61af66fc99e Initial load
duke
parents:
diff changeset
3851 format %{"[$reg + $lreg << $scale]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3852 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3853 base($reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3854 index($lreg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3855 scale($scale);
a61af66fc99e Initial load
duke
parents:
diff changeset
3856 disp(0x0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3857 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3858 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3859
a61af66fc99e Initial load
duke
parents:
diff changeset
3860 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
a61af66fc99e Initial load
duke
parents:
diff changeset
3861 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
a61af66fc99e Initial load
duke
parents:
diff changeset
3862 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3863 constraint(ALLOC_IN_RC(ptr_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3864 match(AddP (AddP reg (LShiftL lreg scale)) off);
a61af66fc99e Initial load
duke
parents:
diff changeset
3865
a61af66fc99e Initial load
duke
parents:
diff changeset
3866 op_cost(10);
a61af66fc99e Initial load
duke
parents:
diff changeset
3867 format %{"[$reg + $off + $lreg << $scale]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3868 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3869 base($reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3870 index($lreg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3871 scale($scale);
a61af66fc99e Initial load
duke
parents:
diff changeset
3872 disp($off);
a61af66fc99e Initial load
duke
parents:
diff changeset
3873 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3874 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3875
a61af66fc99e Initial load
duke
parents:
diff changeset
3876 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
a61af66fc99e Initial load
duke
parents:
diff changeset
3877 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
a61af66fc99e Initial load
duke
parents:
diff changeset
3878 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3879 constraint(ALLOC_IN_RC(ptr_reg));
a61af66fc99e Initial load
duke
parents:
diff changeset
3880 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
3881 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
a61af66fc99e Initial load
duke
parents:
diff changeset
3882
a61af66fc99e Initial load
duke
parents:
diff changeset
3883 op_cost(10);
a61af66fc99e Initial load
duke
parents:
diff changeset
3884 format %{"[$reg + $off + $idx << $scale]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3885 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
3886 base($reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
3887 index($idx);
a61af66fc99e Initial load
duke
parents:
diff changeset
3888 scale($scale);
a61af66fc99e Initial load
duke
parents:
diff changeset
3889 disp($off);
a61af66fc99e Initial load
duke
parents:
diff changeset
3890 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3891 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
3892
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3893 // Indirect Narrow Oop Plus Offset Operand
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3894 // Note: x86 architecture doesn't support "scale * index + offset" without a base
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3895 // we can't free r12 even with Universe::narrow_oop_base() == NULL.
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3896 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
1571
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
3897 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8));
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3898 constraint(ALLOC_IN_RC(ptr_reg));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3899 match(AddP (DecodeN reg) off);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3900
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3901 op_cost(10);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3902 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3903 interface(MEMORY_INTER) %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3904 base(0xc); // R12
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3905 index($reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3906 scale(0x3);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3907 disp($off);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3908 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3909 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3910
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3911 // Indirect Memory Operand
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3912 operand indirectNarrow(rRegN reg)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3913 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3914 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3915 constraint(ALLOC_IN_RC(ptr_reg));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3916 match(DecodeN reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3917
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3918 format %{ "[$reg]" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3919 interface(MEMORY_INTER) %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3920 base($reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3921 index(0x4);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3922 scale(0x0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3923 disp(0x0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3924 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3925 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3926
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3927 // Indirect Memory Plus Short Offset Operand
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3928 operand indOffset8Narrow(rRegN reg, immL8 off)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3929 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3930 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3931 constraint(ALLOC_IN_RC(ptr_reg));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3932 match(AddP (DecodeN reg) off);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3933
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3934 format %{ "[$reg + $off (8-bit)]" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3935 interface(MEMORY_INTER) %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3936 base($reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3937 index(0x4);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3938 scale(0x0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3939 disp($off);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3940 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3941 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3942
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3943 // Indirect Memory Plus Long Offset Operand
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3944 operand indOffset32Narrow(rRegN reg, immL32 off)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3945 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3946 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3947 constraint(ALLOC_IN_RC(ptr_reg));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3948 match(AddP (DecodeN reg) off);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3949
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3950 format %{ "[$reg + $off (32-bit)]" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3951 interface(MEMORY_INTER) %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3952 base($reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3953 index(0x4);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3954 scale(0x0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3955 disp($off);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3956 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3957 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3958
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3959 // Indirect Memory Plus Index Register Plus Offset Operand
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3960 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3961 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3962 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3963 constraint(ALLOC_IN_RC(ptr_reg));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3964 match(AddP (AddP (DecodeN reg) lreg) off);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3965
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3966 op_cost(10);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3967 format %{"[$reg + $off + $lreg]" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3968 interface(MEMORY_INTER) %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3969 base($reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3970 index($lreg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3971 scale(0x0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3972 disp($off);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3973 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3974 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3975
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3976 // Indirect Memory Plus Index Register Plus Offset Operand
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3977 operand indIndexNarrow(rRegN reg, rRegL lreg)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3978 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3979 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3980 constraint(ALLOC_IN_RC(ptr_reg));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3981 match(AddP (DecodeN reg) lreg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3982
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3983 op_cost(10);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3984 format %{"[$reg + $lreg]" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3985 interface(MEMORY_INTER) %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3986 base($reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3987 index($lreg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3988 scale(0x0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3989 disp(0x0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3990 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3991 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3992
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3993 // Indirect Memory Times Scale Plus Index Register
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3994 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3995 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3996 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3997 constraint(ALLOC_IN_RC(ptr_reg));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3998 match(AddP (DecodeN reg) (LShiftL lreg scale));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
3999
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4000 op_cost(10);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4001 format %{"[$reg + $lreg << $scale]" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4002 interface(MEMORY_INTER) %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4003 base($reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4004 index($lreg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4005 scale($scale);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4006 disp(0x0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4007 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4008 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4009
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4010 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4011 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4012 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4013 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4014 constraint(ALLOC_IN_RC(ptr_reg));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4015 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4016
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4017 op_cost(10);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4018 format %{"[$reg + $off + $lreg << $scale]" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4019 interface(MEMORY_INTER) %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4020 base($reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4021 index($lreg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4022 scale($scale);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4023 disp($off);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4024 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4025 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4026
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4027 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4028 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4029 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4030 constraint(ALLOC_IN_RC(ptr_reg));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4031 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4032 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4033
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4034 op_cost(10);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4035 format %{"[$reg + $off + $idx << $scale]" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4036 interface(MEMORY_INTER) %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4037 base($reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4038 index($idx);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4039 scale($scale);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4040 disp($off);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4041 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4042 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4043
6848
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4044 operand indirectNarrowKlass(rRegN reg)
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4045 %{
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4046 predicate(Universe::narrow_klass_shift() == 0);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4047 constraint(ALLOC_IN_RC(ptr_reg));
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4048 match(DecodeNKlass reg);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4049
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4050 format %{ "[$reg]" %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4051 interface(MEMORY_INTER) %{
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4052 base($reg);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4053 index(0x4);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4054 scale(0x0);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4055 disp(0x0);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4056 %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4057 %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4058
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4059 operand indOffset8NarrowKlass(rRegN reg, immL8 off)
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4060 %{
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4061 predicate(Universe::narrow_klass_shift() == 0);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4062 constraint(ALLOC_IN_RC(ptr_reg));
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4063 match(AddP (DecodeNKlass reg) off);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4064
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4065 format %{ "[$reg + $off (8-bit)]" %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4066 interface(MEMORY_INTER) %{
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4067 base($reg);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4068 index(0x4);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4069 scale(0x0);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4070 disp($off);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4071 %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4072 %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4073
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4074 operand indOffset32NarrowKlass(rRegN reg, immL32 off)
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4075 %{
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4076 predicate(Universe::narrow_klass_shift() == 0);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4077 constraint(ALLOC_IN_RC(ptr_reg));
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4078 match(AddP (DecodeNKlass reg) off);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4079
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4080 format %{ "[$reg + $off (32-bit)]" %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4081 interface(MEMORY_INTER) %{
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4082 base($reg);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4083 index(0x4);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4084 scale(0x0);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4085 disp($off);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4086 %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4087 %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4088
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4089 operand indIndexOffsetNarrowKlass(rRegN reg, rRegL lreg, immL32 off)
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4090 %{
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4091 predicate(Universe::narrow_klass_shift() == 0);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4092 constraint(ALLOC_IN_RC(ptr_reg));
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4093 match(AddP (AddP (DecodeNKlass reg) lreg) off);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4094
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4095 op_cost(10);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4096 format %{"[$reg + $off + $lreg]" %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4097 interface(MEMORY_INTER) %{
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4098 base($reg);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4099 index($lreg);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4100 scale(0x0);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4101 disp($off);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4102 %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4103 %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4104
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4105 operand indIndexNarrowKlass(rRegN reg, rRegL lreg)
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4106 %{
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4107 predicate(Universe::narrow_klass_shift() == 0);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4108 constraint(ALLOC_IN_RC(ptr_reg));
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4109 match(AddP (DecodeNKlass reg) lreg);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4110
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4111 op_cost(10);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4112 format %{"[$reg + $lreg]" %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4113 interface(MEMORY_INTER) %{
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4114 base($reg);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4115 index($lreg);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4116 scale(0x0);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4117 disp(0x0);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4118 %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4119 %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4120
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4121 operand indIndexScaleNarrowKlass(rRegN reg, rRegL lreg, immI2 scale)
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4122 %{
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4123 predicate(Universe::narrow_klass_shift() == 0);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4124 constraint(ALLOC_IN_RC(ptr_reg));
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4125 match(AddP (DecodeNKlass reg) (LShiftL lreg scale));
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4126
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4127 op_cost(10);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4128 format %{"[$reg + $lreg << $scale]" %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4129 interface(MEMORY_INTER) %{
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4130 base($reg);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4131 index($lreg);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4132 scale($scale);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4133 disp(0x0);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4134 %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4135 %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4136
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4137 operand indIndexScaleOffsetNarrowKlass(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4138 %{
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4139 predicate(Universe::narrow_klass_shift() == 0);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4140 constraint(ALLOC_IN_RC(ptr_reg));
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4141 match(AddP (AddP (DecodeNKlass reg) (LShiftL lreg scale)) off);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4142
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4143 op_cost(10);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4144 format %{"[$reg + $off + $lreg << $scale]" %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4145 interface(MEMORY_INTER) %{
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4146 base($reg);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4147 index($lreg);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4148 scale($scale);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4149 disp($off);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4150 %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4151 %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4152
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4153 operand indCompressedKlassOffset(rRegN reg, immL32 off) %{
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4154 predicate(UseCompressedKlassPointers && (Universe::narrow_klass_shift() == Address::times_8));
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4155 constraint(ALLOC_IN_RC(ptr_reg));
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4156 match(AddP (DecodeNKlass reg) off);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4157
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4158 op_cost(10);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4159 format %{"[R12 + $reg << 3 + $off] (compressed klass addressing)" %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4160 interface(MEMORY_INTER) %{
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4161 base(0xc); // R12
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4162 index($reg);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4163 scale(0x3);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4164 disp($off);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4165 %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4166 %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4167
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4168 operand indPosIndexScaleOffsetNarrowKlass(rRegN reg, immL32 off, rRegI idx, immI2 scale)
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4169 %{
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4170 constraint(ALLOC_IN_RC(ptr_reg));
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4171 predicate(Universe::narrow_klass_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4172 match(AddP (AddP (DecodeNKlass reg) (LShiftL (ConvI2L idx) scale)) off);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4173
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4174 op_cost(10);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4175 format %{"[$reg + $off + $idx << $scale]" %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4176 interface(MEMORY_INTER) %{
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4177 base($reg);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4178 index($idx);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4179 scale($scale);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4180 disp($off);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4181 %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4182 %}
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4183
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4184 //----------Special Memory Operands--------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
4185 // Stack Slot Operand - This operand is used for loading and storing temporary
a61af66fc99e Initial load
duke
parents:
diff changeset
4186 // values on the stack where a match requires a value to
a61af66fc99e Initial load
duke
parents:
diff changeset
4187 // flow through memory.
a61af66fc99e Initial load
duke
parents:
diff changeset
4188 operand stackSlotP(sRegP reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
4189 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4190 constraint(ALLOC_IN_RC(stack_slots));
a61af66fc99e Initial load
duke
parents:
diff changeset
4191 // No match rule because this operand is only generated in matching
a61af66fc99e Initial load
duke
parents:
diff changeset
4192
a61af66fc99e Initial load
duke
parents:
diff changeset
4193 format %{ "[$reg]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4194 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4195 base(0x4); // RSP
a61af66fc99e Initial load
duke
parents:
diff changeset
4196 index(0x4); // No Index
a61af66fc99e Initial load
duke
parents:
diff changeset
4197 scale(0x0); // No Scale
a61af66fc99e Initial load
duke
parents:
diff changeset
4198 disp($reg); // Stack Offset
a61af66fc99e Initial load
duke
parents:
diff changeset
4199 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4200 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4201
a61af66fc99e Initial load
duke
parents:
diff changeset
4202 operand stackSlotI(sRegI reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
4203 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4204 constraint(ALLOC_IN_RC(stack_slots));
a61af66fc99e Initial load
duke
parents:
diff changeset
4205 // No match rule because this operand is only generated in matching
a61af66fc99e Initial load
duke
parents:
diff changeset
4206
a61af66fc99e Initial load
duke
parents:
diff changeset
4207 format %{ "[$reg]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4208 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4209 base(0x4); // RSP
a61af66fc99e Initial load
duke
parents:
diff changeset
4210 index(0x4); // No Index
a61af66fc99e Initial load
duke
parents:
diff changeset
4211 scale(0x0); // No Scale
a61af66fc99e Initial load
duke
parents:
diff changeset
4212 disp($reg); // Stack Offset
a61af66fc99e Initial load
duke
parents:
diff changeset
4213 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4214 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4215
a61af66fc99e Initial load
duke
parents:
diff changeset
4216 operand stackSlotF(sRegF reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
4217 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4218 constraint(ALLOC_IN_RC(stack_slots));
a61af66fc99e Initial load
duke
parents:
diff changeset
4219 // No match rule because this operand is only generated in matching
a61af66fc99e Initial load
duke
parents:
diff changeset
4220
a61af66fc99e Initial load
duke
parents:
diff changeset
4221 format %{ "[$reg]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4222 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4223 base(0x4); // RSP
a61af66fc99e Initial load
duke
parents:
diff changeset
4224 index(0x4); // No Index
a61af66fc99e Initial load
duke
parents:
diff changeset
4225 scale(0x0); // No Scale
a61af66fc99e Initial load
duke
parents:
diff changeset
4226 disp($reg); // Stack Offset
a61af66fc99e Initial load
duke
parents:
diff changeset
4227 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4228 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4229
a61af66fc99e Initial load
duke
parents:
diff changeset
4230 operand stackSlotD(sRegD reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
4231 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4232 constraint(ALLOC_IN_RC(stack_slots));
a61af66fc99e Initial load
duke
parents:
diff changeset
4233 // No match rule because this operand is only generated in matching
a61af66fc99e Initial load
duke
parents:
diff changeset
4234
a61af66fc99e Initial load
duke
parents:
diff changeset
4235 format %{ "[$reg]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4236 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4237 base(0x4); // RSP
a61af66fc99e Initial load
duke
parents:
diff changeset
4238 index(0x4); // No Index
a61af66fc99e Initial load
duke
parents:
diff changeset
4239 scale(0x0); // No Scale
a61af66fc99e Initial load
duke
parents:
diff changeset
4240 disp($reg); // Stack Offset
a61af66fc99e Initial load
duke
parents:
diff changeset
4241 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4242 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4243 operand stackSlotL(sRegL reg)
a61af66fc99e Initial load
duke
parents:
diff changeset
4244 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4245 constraint(ALLOC_IN_RC(stack_slots));
a61af66fc99e Initial load
duke
parents:
diff changeset
4246 // No match rule because this operand is only generated in matching
a61af66fc99e Initial load
duke
parents:
diff changeset
4247
a61af66fc99e Initial load
duke
parents:
diff changeset
4248 format %{ "[$reg]" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4249 interface(MEMORY_INTER) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4250 base(0x4); // RSP
a61af66fc99e Initial load
duke
parents:
diff changeset
4251 index(0x4); // No Index
a61af66fc99e Initial load
duke
parents:
diff changeset
4252 scale(0x0); // No Scale
a61af66fc99e Initial load
duke
parents:
diff changeset
4253 disp($reg); // Stack Offset
a61af66fc99e Initial load
duke
parents:
diff changeset
4254 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4255 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4256
a61af66fc99e Initial load
duke
parents:
diff changeset
4257 //----------Conditional Branch Operands----------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
4258 // Comparison Op - This is the operation of the comparison, and is limited to
a61af66fc99e Initial load
duke
parents:
diff changeset
4259 // the following set of codes:
a61af66fc99e Initial load
duke
parents:
diff changeset
4260 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
a61af66fc99e Initial load
duke
parents:
diff changeset
4261 //
a61af66fc99e Initial load
duke
parents:
diff changeset
4262 // Other attributes of the comparison, such as unsignedness, are specified
a61af66fc99e Initial load
duke
parents:
diff changeset
4263 // by the comparison instruction that sets a condition code flags register.
a61af66fc99e Initial load
duke
parents:
diff changeset
4264 // That result is represented by a flags operand whose subtype is appropriate
a61af66fc99e Initial load
duke
parents:
diff changeset
4265 // to the unsignedness (etc.) of the comparison.
a61af66fc99e Initial load
duke
parents:
diff changeset
4266 //
a61af66fc99e Initial load
duke
parents:
diff changeset
4267 // Later, the instruction which matches both the Comparison Op (a Bool) and
a61af66fc99e Initial load
duke
parents:
diff changeset
4268 // the flags (produced by the Cmp) specifies the coding of the comparison op
a61af66fc99e Initial load
duke
parents:
diff changeset
4269 // by matching a specific subtype of Bool operand below, such as cmpOpU.
a61af66fc99e Initial load
duke
parents:
diff changeset
4270
a61af66fc99e Initial load
duke
parents:
diff changeset
4271 // Comparision Code
a61af66fc99e Initial load
duke
parents:
diff changeset
4272 operand cmpOp()
a61af66fc99e Initial load
duke
parents:
diff changeset
4273 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4274 match(Bool);
a61af66fc99e Initial load
duke
parents:
diff changeset
4275
a61af66fc99e Initial load
duke
parents:
diff changeset
4276 format %{ "" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4277 interface(COND_INTER) %{
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4278 equal(0x4, "e");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4279 not_equal(0x5, "ne");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4280 less(0xC, "l");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4281 greater_equal(0xD, "ge");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4282 less_equal(0xE, "le");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4283 greater(0xF, "g");
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4284 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4285 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4286
a61af66fc99e Initial load
duke
parents:
diff changeset
4287 // Comparison Code, unsigned compare. Used by FP also, with
a61af66fc99e Initial load
duke
parents:
diff changeset
4288 // C2 (unordered) turned into GT or LT already. The other bits
a61af66fc99e Initial load
duke
parents:
diff changeset
4289 // C0 and C3 are turned into Carry & Zero flags.
a61af66fc99e Initial load
duke
parents:
diff changeset
4290 operand cmpOpU()
a61af66fc99e Initial load
duke
parents:
diff changeset
4291 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4292 match(Bool);
a61af66fc99e Initial load
duke
parents:
diff changeset
4293
a61af66fc99e Initial load
duke
parents:
diff changeset
4294 format %{ "" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4295 interface(COND_INTER) %{
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4296 equal(0x4, "e");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4297 not_equal(0x5, "ne");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4298 less(0x2, "b");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4299 greater_equal(0x3, "nb");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4300 less_equal(0x6, "be");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4301 greater(0x7, "nbe");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4302 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4303 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4304
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4305
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4306 // Floating comparisons that don't require any fixup for the unordered case
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4307 operand cmpOpUCF() %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4308 match(Bool);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4309 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4310 n->as_Bool()->_test._test == BoolTest::ge ||
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4311 n->as_Bool()->_test._test == BoolTest::le ||
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4312 n->as_Bool()->_test._test == BoolTest::gt);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4313 format %{ "" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4314 interface(COND_INTER) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4315 equal(0x4, "e");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4316 not_equal(0x5, "ne");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4317 less(0x2, "b");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4318 greater_equal(0x3, "nb");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4319 less_equal(0x6, "be");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4320 greater(0x7, "nbe");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4321 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4322 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4323
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4324
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4325 // Floating comparisons that can be fixed up with extra conditional jumps
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4326 operand cmpOpUCF2() %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4327 match(Bool);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4328 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4329 n->as_Bool()->_test._test == BoolTest::eq);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4330 format %{ "" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4331 interface(COND_INTER) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4332 equal(0x4, "e");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4333 not_equal(0x5, "ne");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4334 less(0x2, "b");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4335 greater_equal(0x3, "nb");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4336 less_equal(0x6, "be");
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
4337 greater(0x7, "nbe");
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4338 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4339 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4340
a61af66fc99e Initial load
duke
parents:
diff changeset
4341
a61af66fc99e Initial load
duke
parents:
diff changeset
4342 //----------OPERAND CLASSES----------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
4343 // Operand Classes are groups of operands that are used as to simplify
605
98cb887364d3 6810672: Comment typos
twisti
parents: 569
diff changeset
4344 // instruction definitions by not requiring the AD writer to specify separate
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4345 // instructions for every form of operand when the instruction accepts
a61af66fc99e Initial load
duke
parents:
diff changeset
4346 // multiple operand types with the same basic encoding and format. The classic
a61af66fc99e Initial load
duke
parents:
diff changeset
4347 // case of this is memory operands.
a61af66fc99e Initial load
duke
parents:
diff changeset
4348
a61af66fc99e Initial load
duke
parents:
diff changeset
4349 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
4350 indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset,
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4351 indCompressedOopOffset,
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4352 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
4353 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
6848
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4354 indIndexScaleOffsetNarrow, indPosIndexScaleOffsetNarrow,
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4355 indCompressedKlassOffset,
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4356 indirectNarrowKlass, indOffset8NarrowKlass, indOffset32NarrowKlass,
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4357 indIndexOffsetNarrowKlass, indIndexNarrowKlass, indIndexScaleNarrowKlass,
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
4358 indIndexScaleOffsetNarrowKlass, indPosIndexScaleOffsetNarrowKlass);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4359
a61af66fc99e Initial load
duke
parents:
diff changeset
4360 //----------PIPELINE-----------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
4361 // Rules which define the behavior of the target architectures pipeline.
a61af66fc99e Initial load
duke
parents:
diff changeset
4362 pipeline %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4363
a61af66fc99e Initial load
duke
parents:
diff changeset
4364 //----------ATTRIBUTES---------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
4365 attributes %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4366 variable_size_instructions; // Fixed size instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
4367 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
a61af66fc99e Initial load
duke
parents:
diff changeset
4368 instruction_unit_size = 1; // An instruction is 1 bytes long
a61af66fc99e Initial load
duke
parents:
diff changeset
4369 instruction_fetch_unit_size = 16; // The processor fetches one line
a61af66fc99e Initial load
duke
parents:
diff changeset
4370 instruction_fetch_units = 1; // of 16 bytes
a61af66fc99e Initial load
duke
parents:
diff changeset
4371
a61af66fc99e Initial load
duke
parents:
diff changeset
4372 // List of nop instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
4373 nops( MachNop );
a61af66fc99e Initial load
duke
parents:
diff changeset
4374 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4375
a61af66fc99e Initial load
duke
parents:
diff changeset
4376 //----------RESOURCES----------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
4377 // Resources are the functional units available to the machine
a61af66fc99e Initial load
duke
parents:
diff changeset
4378
a61af66fc99e Initial load
duke
parents:
diff changeset
4379 // Generic P2/P3 pipeline
a61af66fc99e Initial load
duke
parents:
diff changeset
4380 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
a61af66fc99e Initial load
duke
parents:
diff changeset
4381 // 3 instructions decoded per cycle.
a61af66fc99e Initial load
duke
parents:
diff changeset
4382 // 2 load/store ops per cycle, 1 branch, 1 FPU,
a61af66fc99e Initial load
duke
parents:
diff changeset
4383 // 3 ALU op, only ALU0 handles mul instructions.
a61af66fc99e Initial load
duke
parents:
diff changeset
4384 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
a61af66fc99e Initial load
duke
parents:
diff changeset
4385 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
a61af66fc99e Initial load
duke
parents:
diff changeset
4386 BR, FPU,
a61af66fc99e Initial load
duke
parents:
diff changeset
4387 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4388
a61af66fc99e Initial load
duke
parents:
diff changeset
4389 //----------PIPELINE DESCRIPTION-----------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
4390 // Pipeline Description specifies the stages in the machine's pipeline
a61af66fc99e Initial load
duke
parents:
diff changeset
4391
a61af66fc99e Initial load
duke
parents:
diff changeset
4392 // Generic P2/P3 pipeline
a61af66fc99e Initial load
duke
parents:
diff changeset
4393 pipe_desc(S0, S1, S2, S3, S4, S5);
a61af66fc99e Initial load
duke
parents:
diff changeset
4394
a61af66fc99e Initial load
duke
parents:
diff changeset
4395 //----------PIPELINE CLASSES---------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
4396 // Pipeline Classes describe the stages in which input and output are
a61af66fc99e Initial load
duke
parents:
diff changeset
4397 // referenced by the hardware pipeline.
a61af66fc99e Initial load
duke
parents:
diff changeset
4398
a61af66fc99e Initial load
duke
parents:
diff changeset
4399 // Naming convention: ialu or fpu
a61af66fc99e Initial load
duke
parents:
diff changeset
4400 // Then: _reg
a61af66fc99e Initial load
duke
parents:
diff changeset
4401 // Then: _reg if there is a 2nd register
a61af66fc99e Initial load
duke
parents:
diff changeset
4402 // Then: _long if it's a pair of instructions implementing a long
a61af66fc99e Initial load
duke
parents:
diff changeset
4403 // Then: _fat if it requires the big decoder
a61af66fc99e Initial load
duke
parents:
diff changeset
4404 // Or: _mem if it requires the big decoder and a memory unit.
a61af66fc99e Initial load
duke
parents:
diff changeset
4405
a61af66fc99e Initial load
duke
parents:
diff changeset
4406 // Integer ALU reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4407 pipe_class ialu_reg(rRegI dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
4408 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4409 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4410 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4411 dst : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4412 DECODE : S0; // any decoder
a61af66fc99e Initial load
duke
parents:
diff changeset
4413 ALU : S3; // any alu
a61af66fc99e Initial load
duke
parents:
diff changeset
4414 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4415
a61af66fc99e Initial load
duke
parents:
diff changeset
4416 // Long ALU reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4417 pipe_class ialu_reg_long(rRegL dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
4418 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4419 instruction_count(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4420 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4421 dst : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4422 DECODE : S0(2); // any 2 decoders
a61af66fc99e Initial load
duke
parents:
diff changeset
4423 ALU : S3(2); // both alus
a61af66fc99e Initial load
duke
parents:
diff changeset
4424 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4425
a61af66fc99e Initial load
duke
parents:
diff changeset
4426 // Integer ALU reg operation using big decoder
a61af66fc99e Initial load
duke
parents:
diff changeset
4427 pipe_class ialu_reg_fat(rRegI dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
4428 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4429 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4430 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4431 dst : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4432 D0 : S0; // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
4433 ALU : S3; // any alu
a61af66fc99e Initial load
duke
parents:
diff changeset
4434 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4435
a61af66fc99e Initial load
duke
parents:
diff changeset
4436 // Long ALU reg operation using big decoder
a61af66fc99e Initial load
duke
parents:
diff changeset
4437 pipe_class ialu_reg_long_fat(rRegL dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
4438 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4439 instruction_count(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4440 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4441 dst : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4442 D0 : S0(2); // big decoder only; twice
a61af66fc99e Initial load
duke
parents:
diff changeset
4443 ALU : S3(2); // any 2 alus
a61af66fc99e Initial load
duke
parents:
diff changeset
4444 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4445
a61af66fc99e Initial load
duke
parents:
diff changeset
4446 // Integer ALU reg-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4447 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
4448 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4449 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4450 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4451 src : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4452 DECODE : S0; // any decoder
a61af66fc99e Initial load
duke
parents:
diff changeset
4453 ALU : S3; // any alu
a61af66fc99e Initial load
duke
parents:
diff changeset
4454 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4455
a61af66fc99e Initial load
duke
parents:
diff changeset
4456 // Long ALU reg-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4457 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
4458 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4459 instruction_count(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4460 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4461 src : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4462 DECODE : S0(2); // any 2 decoders
a61af66fc99e Initial load
duke
parents:
diff changeset
4463 ALU : S3(2); // both alus
a61af66fc99e Initial load
duke
parents:
diff changeset
4464 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4465
a61af66fc99e Initial load
duke
parents:
diff changeset
4466 // Integer ALU reg-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4467 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
4468 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4469 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4470 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4471 src : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4472 D0 : S0; // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
4473 ALU : S3; // any alu
a61af66fc99e Initial load
duke
parents:
diff changeset
4474 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4475
a61af66fc99e Initial load
duke
parents:
diff changeset
4476 // Long ALU reg-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4477 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
4478 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4479 instruction_count(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4480 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4481 src : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4482 D0 : S0(2); // big decoder only; twice
a61af66fc99e Initial load
duke
parents:
diff changeset
4483 ALU : S3(2); // both alus
a61af66fc99e Initial load
duke
parents:
diff changeset
4484 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4485
a61af66fc99e Initial load
duke
parents:
diff changeset
4486 // Integer ALU reg-mem operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4487 pipe_class ialu_reg_mem(rRegI dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
4488 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4489 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4490 dst : S5(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4491 mem : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4492 D0 : S0; // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
4493 ALU : S4; // any alu
a61af66fc99e Initial load
duke
parents:
diff changeset
4494 MEM : S3; // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
4495 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4496
a61af66fc99e Initial load
duke
parents:
diff changeset
4497 // Integer mem operation (prefetch)
a61af66fc99e Initial load
duke
parents:
diff changeset
4498 pipe_class ialu_mem(memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
4499 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4500 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4501 mem : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4502 D0 : S0; // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
4503 MEM : S3; // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
4504 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4505
a61af66fc99e Initial load
duke
parents:
diff changeset
4506 // Integer Store to Memory
a61af66fc99e Initial load
duke
parents:
diff changeset
4507 pipe_class ialu_mem_reg(memory mem, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
4508 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4509 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4510 mem : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4511 src : S5(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4512 D0 : S0; // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
4513 ALU : S4; // any alu
a61af66fc99e Initial load
duke
parents:
diff changeset
4514 MEM : S3;
a61af66fc99e Initial load
duke
parents:
diff changeset
4515 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4516
a61af66fc99e Initial load
duke
parents:
diff changeset
4517 // // Long Store to Memory
a61af66fc99e Initial load
duke
parents:
diff changeset
4518 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
4519 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4520 // instruction_count(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4521 // mem : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4522 // src : S5(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4523 // D0 : S0(2); // big decoder only; twice
a61af66fc99e Initial load
duke
parents:
diff changeset
4524 // ALU : S4(2); // any 2 alus
a61af66fc99e Initial load
duke
parents:
diff changeset
4525 // MEM : S3(2); // Both mems
a61af66fc99e Initial load
duke
parents:
diff changeset
4526 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4527
a61af66fc99e Initial load
duke
parents:
diff changeset
4528 // Integer Store to Memory
a61af66fc99e Initial load
duke
parents:
diff changeset
4529 pipe_class ialu_mem_imm(memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
4530 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4531 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4532 mem : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4533 D0 : S0; // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
4534 ALU : S4; // any alu
a61af66fc99e Initial load
duke
parents:
diff changeset
4535 MEM : S3;
a61af66fc99e Initial load
duke
parents:
diff changeset
4536 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4537
a61af66fc99e Initial load
duke
parents:
diff changeset
4538 // Integer ALU0 reg-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4539 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
4540 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4541 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4542 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4543 src : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4544 D0 : S0; // Big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
4545 ALU0 : S3; // only alu0
a61af66fc99e Initial load
duke
parents:
diff changeset
4546 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4547
a61af66fc99e Initial load
duke
parents:
diff changeset
4548 // Integer ALU0 reg-mem operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4549 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
4550 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4551 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4552 dst : S5(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4553 mem : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4554 D0 : S0; // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
4555 ALU0 : S4; // ALU0 only
a61af66fc99e Initial load
duke
parents:
diff changeset
4556 MEM : S3; // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
4557 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4558
a61af66fc99e Initial load
duke
parents:
diff changeset
4559 // Integer ALU reg-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4560 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
a61af66fc99e Initial load
duke
parents:
diff changeset
4561 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4562 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4563 cr : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4564 src1 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4565 src2 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4566 DECODE : S0; // any decoder
a61af66fc99e Initial load
duke
parents:
diff changeset
4567 ALU : S3; // any alu
a61af66fc99e Initial load
duke
parents:
diff changeset
4568 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4569
a61af66fc99e Initial load
duke
parents:
diff changeset
4570 // Integer ALU reg-imm operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4571 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
a61af66fc99e Initial load
duke
parents:
diff changeset
4572 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4573 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4574 cr : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4575 src1 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4576 DECODE : S0; // any decoder
a61af66fc99e Initial load
duke
parents:
diff changeset
4577 ALU : S3; // any alu
a61af66fc99e Initial load
duke
parents:
diff changeset
4578 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4579
a61af66fc99e Initial load
duke
parents:
diff changeset
4580 // Integer ALU reg-mem operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4581 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
a61af66fc99e Initial load
duke
parents:
diff changeset
4582 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4583 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4584 cr : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4585 src1 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4586 src2 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4587 D0 : S0; // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
4588 ALU : S4; // any alu
a61af66fc99e Initial load
duke
parents:
diff changeset
4589 MEM : S3;
a61af66fc99e Initial load
duke
parents:
diff changeset
4590 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4591
a61af66fc99e Initial load
duke
parents:
diff changeset
4592 // Conditional move reg-reg
a61af66fc99e Initial load
duke
parents:
diff changeset
4593 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
a61af66fc99e Initial load
duke
parents:
diff changeset
4594 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4595 instruction_count(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
4596 y : S4(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4597 q : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4598 p : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4599 DECODE : S0(4); // any decoder
a61af66fc99e Initial load
duke
parents:
diff changeset
4600 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4601
a61af66fc99e Initial load
duke
parents:
diff changeset
4602 // Conditional move reg-reg
a61af66fc99e Initial load
duke
parents:
diff changeset
4603 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
4604 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4605 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4606 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4607 src : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4608 cr : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4609 DECODE : S0; // any decoder
a61af66fc99e Initial load
duke
parents:
diff changeset
4610 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4611
a61af66fc99e Initial load
duke
parents:
diff changeset
4612 // Conditional move reg-mem
a61af66fc99e Initial load
duke
parents:
diff changeset
4613 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
4614 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4615 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4616 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4617 src : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4618 cr : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4619 DECODE : S0; // any decoder
a61af66fc99e Initial load
duke
parents:
diff changeset
4620 MEM : S3;
a61af66fc99e Initial load
duke
parents:
diff changeset
4621 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4622
a61af66fc99e Initial load
duke
parents:
diff changeset
4623 // Conditional move reg-reg long
a61af66fc99e Initial load
duke
parents:
diff changeset
4624 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
4625 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4626 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4627 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4628 src : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4629 cr : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4630 DECODE : S0(2); // any 2 decoders
a61af66fc99e Initial load
duke
parents:
diff changeset
4631 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4632
a61af66fc99e Initial load
duke
parents:
diff changeset
4633 // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
4634 // // Conditional move double reg-reg
a61af66fc99e Initial load
duke
parents:
diff changeset
4635 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
4636 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4637 // single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4638 // dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4639 // src : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4640 // cr : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4641 // DECODE : S0; // any decoder
a61af66fc99e Initial load
duke
parents:
diff changeset
4642 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4643
a61af66fc99e Initial load
duke
parents:
diff changeset
4644 // Float reg-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4645 pipe_class fpu_reg(regD dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
4646 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4647 instruction_count(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4648 dst : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4649 DECODE : S0(2); // any 2 decoders
a61af66fc99e Initial load
duke
parents:
diff changeset
4650 FPU : S3;
a61af66fc99e Initial load
duke
parents:
diff changeset
4651 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4652
a61af66fc99e Initial load
duke
parents:
diff changeset
4653 // Float reg-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4654 pipe_class fpu_reg_reg(regD dst, regD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
4655 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4656 instruction_count(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4657 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4658 src : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4659 DECODE : S0(2); // any 2 decoders
a61af66fc99e Initial load
duke
parents:
diff changeset
4660 FPU : S3;
a61af66fc99e Initial load
duke
parents:
diff changeset
4661 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4662
a61af66fc99e Initial load
duke
parents:
diff changeset
4663 // Float reg-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4664 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
a61af66fc99e Initial load
duke
parents:
diff changeset
4665 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4666 instruction_count(3);
a61af66fc99e Initial load
duke
parents:
diff changeset
4667 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4668 src1 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4669 src2 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4670 DECODE : S0(3); // any 3 decoders
a61af66fc99e Initial load
duke
parents:
diff changeset
4671 FPU : S3(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4672 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4673
a61af66fc99e Initial load
duke
parents:
diff changeset
4674 // Float reg-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4675 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
a61af66fc99e Initial load
duke
parents:
diff changeset
4676 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4677 instruction_count(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
4678 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4679 src1 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4680 src2 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4681 src3 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4682 DECODE : S0(4); // any 3 decoders
a61af66fc99e Initial load
duke
parents:
diff changeset
4683 FPU : S3(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4684 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4685
a61af66fc99e Initial load
duke
parents:
diff changeset
4686 // Float reg-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4687 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
a61af66fc99e Initial load
duke
parents:
diff changeset
4688 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4689 instruction_count(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
4690 dst : S4(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4691 src1 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4692 src2 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4693 src3 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4694 DECODE : S1(3); // any 3 decoders
a61af66fc99e Initial load
duke
parents:
diff changeset
4695 D0 : S0; // Big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
4696 FPU : S3(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4697 MEM : S3;
a61af66fc99e Initial load
duke
parents:
diff changeset
4698 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4699
a61af66fc99e Initial load
duke
parents:
diff changeset
4700 // Float reg-mem operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4701 pipe_class fpu_reg_mem(regD dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
4702 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4703 instruction_count(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4704 dst : S5(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4705 mem : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4706 D0 : S0; // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
4707 DECODE : S1; // any decoder for FPU POP
a61af66fc99e Initial load
duke
parents:
diff changeset
4708 FPU : S4;
a61af66fc99e Initial load
duke
parents:
diff changeset
4709 MEM : S3; // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
4710 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4711
a61af66fc99e Initial load
duke
parents:
diff changeset
4712 // Float reg-mem operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4713 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
4714 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4715 instruction_count(3);
a61af66fc99e Initial load
duke
parents:
diff changeset
4716 dst : S5(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4717 src1 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4718 mem : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4719 D0 : S0; // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
4720 DECODE : S1(2); // any decoder for FPU POP
a61af66fc99e Initial load
duke
parents:
diff changeset
4721 FPU : S4;
a61af66fc99e Initial load
duke
parents:
diff changeset
4722 MEM : S3; // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
4723 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4724
a61af66fc99e Initial load
duke
parents:
diff changeset
4725 // Float mem-reg operation
a61af66fc99e Initial load
duke
parents:
diff changeset
4726 pipe_class fpu_mem_reg(memory mem, regD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
4727 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4728 instruction_count(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4729 src : S5(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4730 mem : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4731 DECODE : S0; // any decoder for FPU PUSH
a61af66fc99e Initial load
duke
parents:
diff changeset
4732 D0 : S1; // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
4733 FPU : S4;
a61af66fc99e Initial load
duke
parents:
diff changeset
4734 MEM : S3; // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
4735 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4736
a61af66fc99e Initial load
duke
parents:
diff changeset
4737 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
a61af66fc99e Initial load
duke
parents:
diff changeset
4738 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4739 instruction_count(3);
a61af66fc99e Initial load
duke
parents:
diff changeset
4740 src1 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4741 src2 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4742 mem : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4743 DECODE : S0(2); // any decoder for FPU PUSH
a61af66fc99e Initial load
duke
parents:
diff changeset
4744 D0 : S1; // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
4745 FPU : S4;
a61af66fc99e Initial load
duke
parents:
diff changeset
4746 MEM : S3; // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
4747 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4748
a61af66fc99e Initial load
duke
parents:
diff changeset
4749 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
a61af66fc99e Initial load
duke
parents:
diff changeset
4750 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4751 instruction_count(3);
a61af66fc99e Initial load
duke
parents:
diff changeset
4752 src1 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4753 src2 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4754 mem : S4(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4755 DECODE : S0; // any decoder for FPU PUSH
a61af66fc99e Initial load
duke
parents:
diff changeset
4756 D0 : S0(2); // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
4757 FPU : S4;
a61af66fc99e Initial load
duke
parents:
diff changeset
4758 MEM : S3(2); // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
4759 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4760
a61af66fc99e Initial load
duke
parents:
diff changeset
4761 pipe_class fpu_mem_mem(memory dst, memory src1)
a61af66fc99e Initial load
duke
parents:
diff changeset
4762 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4763 instruction_count(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4764 src1 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4765 dst : S4(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4766 D0 : S0(2); // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
4767 MEM : S3(2); // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
4768 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4769
a61af66fc99e Initial load
duke
parents:
diff changeset
4770 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
a61af66fc99e Initial load
duke
parents:
diff changeset
4771 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4772 instruction_count(3);
a61af66fc99e Initial load
duke
parents:
diff changeset
4773 src1 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4774 src2 : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4775 dst : S4(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4776 D0 : S0(3); // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
4777 FPU : S4;
a61af66fc99e Initial load
duke
parents:
diff changeset
4778 MEM : S3(3); // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
4779 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4780
a61af66fc99e Initial load
duke
parents:
diff changeset
4781 pipe_class fpu_mem_reg_con(memory mem, regD src1)
a61af66fc99e Initial load
duke
parents:
diff changeset
4782 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4783 instruction_count(3);
a61af66fc99e Initial load
duke
parents:
diff changeset
4784 src1 : S4(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4785 mem : S4(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4786 DECODE : S0; // any decoder for FPU PUSH
a61af66fc99e Initial load
duke
parents:
diff changeset
4787 D0 : S0(2); // big decoder only
a61af66fc99e Initial load
duke
parents:
diff changeset
4788 FPU : S4;
a61af66fc99e Initial load
duke
parents:
diff changeset
4789 MEM : S3(2); // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
4790 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4791
a61af66fc99e Initial load
duke
parents:
diff changeset
4792 // Float load constant
a61af66fc99e Initial load
duke
parents:
diff changeset
4793 pipe_class fpu_reg_con(regD dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
4794 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4795 instruction_count(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4796 dst : S5(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4797 D0 : S0; // big decoder only for the load
a61af66fc99e Initial load
duke
parents:
diff changeset
4798 DECODE : S1; // any decoder for FPU POP
a61af66fc99e Initial load
duke
parents:
diff changeset
4799 FPU : S4;
a61af66fc99e Initial load
duke
parents:
diff changeset
4800 MEM : S3; // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
4801 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4802
a61af66fc99e Initial load
duke
parents:
diff changeset
4803 // Float load constant
a61af66fc99e Initial load
duke
parents:
diff changeset
4804 pipe_class fpu_reg_reg_con(regD dst, regD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
4805 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4806 instruction_count(3);
a61af66fc99e Initial load
duke
parents:
diff changeset
4807 dst : S5(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4808 src : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4809 D0 : S0; // big decoder only for the load
a61af66fc99e Initial load
duke
parents:
diff changeset
4810 DECODE : S1(2); // any decoder for FPU POP
a61af66fc99e Initial load
duke
parents:
diff changeset
4811 FPU : S4;
a61af66fc99e Initial load
duke
parents:
diff changeset
4812 MEM : S3; // any mem
a61af66fc99e Initial load
duke
parents:
diff changeset
4813 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4814
a61af66fc99e Initial load
duke
parents:
diff changeset
4815 // UnConditional branch
a61af66fc99e Initial load
duke
parents:
diff changeset
4816 pipe_class pipe_jmp(label labl)
a61af66fc99e Initial load
duke
parents:
diff changeset
4817 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4818 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4819 BR : S3;
a61af66fc99e Initial load
duke
parents:
diff changeset
4820 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4821
a61af66fc99e Initial load
duke
parents:
diff changeset
4822 // Conditional branch
a61af66fc99e Initial load
duke
parents:
diff changeset
4823 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
a61af66fc99e Initial load
duke
parents:
diff changeset
4824 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4825 single_instruction;
a61af66fc99e Initial load
duke
parents:
diff changeset
4826 cr : S1(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4827 BR : S3;
a61af66fc99e Initial load
duke
parents:
diff changeset
4828 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4829
a61af66fc99e Initial load
duke
parents:
diff changeset
4830 // Allocation idiom
a61af66fc99e Initial load
duke
parents:
diff changeset
4831 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
a61af66fc99e Initial load
duke
parents:
diff changeset
4832 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4833 instruction_count(1); force_serialization;
a61af66fc99e Initial load
duke
parents:
diff changeset
4834 fixed_latency(6);
a61af66fc99e Initial load
duke
parents:
diff changeset
4835 heap_ptr : S3(read);
a61af66fc99e Initial load
duke
parents:
diff changeset
4836 DECODE : S0(3);
a61af66fc99e Initial load
duke
parents:
diff changeset
4837 D0 : S2;
a61af66fc99e Initial load
duke
parents:
diff changeset
4838 MEM : S3;
a61af66fc99e Initial load
duke
parents:
diff changeset
4839 ALU : S3(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4840 dst : S5(write);
a61af66fc99e Initial load
duke
parents:
diff changeset
4841 BR : S5;
a61af66fc99e Initial load
duke
parents:
diff changeset
4842 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4843
a61af66fc99e Initial load
duke
parents:
diff changeset
4844 // Generic big/slow expanded idiom
a61af66fc99e Initial load
duke
parents:
diff changeset
4845 pipe_class pipe_slow()
a61af66fc99e Initial load
duke
parents:
diff changeset
4846 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4847 instruction_count(10); multiple_bundles; force_serialization;
a61af66fc99e Initial load
duke
parents:
diff changeset
4848 fixed_latency(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
4849 D0 : S0(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4850 MEM : S3(2);
a61af66fc99e Initial load
duke
parents:
diff changeset
4851 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4852
a61af66fc99e Initial load
duke
parents:
diff changeset
4853 // The real do-nothing guy
a61af66fc99e Initial load
duke
parents:
diff changeset
4854 pipe_class empty()
a61af66fc99e Initial load
duke
parents:
diff changeset
4855 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4856 instruction_count(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
4857 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4858
a61af66fc99e Initial load
duke
parents:
diff changeset
4859 // Define the class for the Nop node
a61af66fc99e Initial load
duke
parents:
diff changeset
4860 define
a61af66fc99e Initial load
duke
parents:
diff changeset
4861 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4862 MachNop = empty;
a61af66fc99e Initial load
duke
parents:
diff changeset
4863 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4864
a61af66fc99e Initial load
duke
parents:
diff changeset
4865 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4866
a61af66fc99e Initial load
duke
parents:
diff changeset
4867 //----------INSTRUCTIONS-------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
4868 //
a61af66fc99e Initial load
duke
parents:
diff changeset
4869 // match -- States which machine-independent subtree may be replaced
a61af66fc99e Initial load
duke
parents:
diff changeset
4870 // by this instruction.
a61af66fc99e Initial load
duke
parents:
diff changeset
4871 // ins_cost -- The estimated cost of this instruction is used by instruction
a61af66fc99e Initial load
duke
parents:
diff changeset
4872 // selection to identify a minimum cost tree of machine
a61af66fc99e Initial load
duke
parents:
diff changeset
4873 // instructions that matches a tree of machine-independent
a61af66fc99e Initial load
duke
parents:
diff changeset
4874 // instructions.
a61af66fc99e Initial load
duke
parents:
diff changeset
4875 // format -- A string providing the disassembly for this instruction.
a61af66fc99e Initial load
duke
parents:
diff changeset
4876 // The value of an instruction's operand may be inserted
a61af66fc99e Initial load
duke
parents:
diff changeset
4877 // by referring to it with a '$' prefix.
a61af66fc99e Initial load
duke
parents:
diff changeset
4878 // opcode -- Three instruction opcodes may be provided. These are referred
a61af66fc99e Initial load
duke
parents:
diff changeset
4879 // to within an encode class as $primary, $secondary, and $tertiary
a61af66fc99e Initial load
duke
parents:
diff changeset
4880 // rrspectively. The primary opcode is commonly used to
a61af66fc99e Initial load
duke
parents:
diff changeset
4881 // indicate the type of machine instruction, while secondary
a61af66fc99e Initial load
duke
parents:
diff changeset
4882 // and tertiary are often used for prefix options or addressing
a61af66fc99e Initial load
duke
parents:
diff changeset
4883 // modes.
a61af66fc99e Initial load
duke
parents:
diff changeset
4884 // ins_encode -- A list of encode classes with parameters. The encode class
a61af66fc99e Initial load
duke
parents:
diff changeset
4885 // name must have been defined in an 'enc_class' specification
a61af66fc99e Initial load
duke
parents:
diff changeset
4886 // in the encode section of the architecture description.
a61af66fc99e Initial load
duke
parents:
diff changeset
4887
a61af66fc99e Initial load
duke
parents:
diff changeset
4888
a61af66fc99e Initial load
duke
parents:
diff changeset
4889 //----------Load/Store/Move Instructions---------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
4890 //----------Load Instructions--------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
4891
a61af66fc99e Initial load
duke
parents:
diff changeset
4892 // Load Byte (8 bit signed)
a61af66fc99e Initial load
duke
parents:
diff changeset
4893 instruct loadB(rRegI dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
4894 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4895 match(Set dst (LoadB mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
4896
a61af66fc99e Initial load
duke
parents:
diff changeset
4897 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
4898 format %{ "movsbl $dst, $mem\t# byte" %}
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4899
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4900 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4901 __ movsbl($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4902 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4903
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4904 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
4905 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4906
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4907 // Load Byte (8 bit signed) into Long Register
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4908 instruct loadB2L(rRegL dst, memory mem)
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4909 %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4910 match(Set dst (ConvI2L (LoadB mem)));
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4911
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4912 ins_cost(125);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4913 format %{ "movsbq $dst, $mem\t# byte -> long" %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4914
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4915 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4916 __ movsbq($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4917 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4918
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4919 ins_pipe(ialu_reg_mem);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4920 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4921
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4922 // Load Unsigned Byte (8 bit UNsigned)
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4923 instruct loadUB(rRegI dst, memory mem)
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4924 %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4925 match(Set dst (LoadUB mem));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4926
a61af66fc99e Initial load
duke
parents:
diff changeset
4927 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
4928 format %{ "movzbl $dst, $mem\t# ubyte" %}
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4929
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4930 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4931 __ movzbl($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4932 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4933
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4934 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
4935 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4936
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4937 // Load Unsigned Byte (8 bit UNsigned) into Long Register
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4938 instruct loadUB2L(rRegL dst, memory mem)
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4939 %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4940 match(Set dst (ConvI2L (LoadUB mem)));
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4941
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4942 ins_cost(125);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4943 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4944
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4945 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4946 __ movzbq($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4947 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4948
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4949 ins_pipe(ialu_reg_mem);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4950 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4951
824
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4952 // Load Unsigned Byte (8 bit UNsigned) with a 8-bit mask into Long Register
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4953 instruct loadUB2L_immI8(rRegL dst, memory mem, immI8 mask, rFlagsReg cr) %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4954 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4955 effect(KILL cr);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4956
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4957 format %{ "movzbq $dst, $mem\t# ubyte & 8-bit mask -> long\n\t"
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4958 "andl $dst, $mask" %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4959 ins_encode %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4960 Register Rdst = $dst$$Register;
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4961 __ movzbq(Rdst, $mem$$Address);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4962 __ andl(Rdst, $mask$$constant);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4963 %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4964 ins_pipe(ialu_reg_mem);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4965 %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
4966
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4967 // Load Short (16 bit signed)
a61af66fc99e Initial load
duke
parents:
diff changeset
4968 instruct loadS(rRegI dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
4969 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
4970 match(Set dst (LoadS mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
4971
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4972 ins_cost(125);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4973 format %{ "movswl $dst, $mem\t# short" %}
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4974
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4975 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4976 __ movswl($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4977 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4978
0
a61af66fc99e Initial load
duke
parents:
diff changeset
4979 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
4980 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
4981
785
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4982 // Load Short (16 bit signed) to Byte (8 bit signed)
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4983 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4984 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4985
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4986 ins_cost(125);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4987 format %{ "movsbl $dst, $mem\t# short -> byte" %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4988 ins_encode %{
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4989 __ movsbl($dst$$Register, $mem$$Address);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4990 %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4991 ins_pipe(ialu_reg_mem);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4992 %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
4993
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4994 // Load Short (16 bit signed) into Long Register
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4995 instruct loadS2L(rRegL dst, memory mem)
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4996 %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4997 match(Set dst (ConvI2L (LoadS mem)));
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4998
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
4999 ins_cost(125);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5000 format %{ "movswq $dst, $mem\t# short -> long" %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5001
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5002 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5003 __ movswq($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5004 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5005
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5006 ins_pipe(ialu_reg_mem);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5007 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5008
558
3b5ac9e7e6ea 6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents: 420
diff changeset
5009 // Load Unsigned Short/Char (16 bit UNsigned)
3b5ac9e7e6ea 6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents: 420
diff changeset
5010 instruct loadUS(rRegI dst, memory mem)
3b5ac9e7e6ea 6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents: 420
diff changeset
5011 %{
3b5ac9e7e6ea 6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents: 420
diff changeset
5012 match(Set dst (LoadUS mem));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5013
a61af66fc99e Initial load
duke
parents:
diff changeset
5014 ins_cost(125);
558
3b5ac9e7e6ea 6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents: 420
diff changeset
5015 format %{ "movzwl $dst, $mem\t# ushort/char" %}
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5016
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5017 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5018 __ movzwl($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5019 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5020
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5021 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5022 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5023
785
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5024 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5025 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5026 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5027
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5028 ins_cost(125);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5029 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5030 ins_encode %{
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5031 __ movsbl($dst$$Register, $mem$$Address);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5032 %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5033 ins_pipe(ialu_reg_mem);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5034 %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5035
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5036 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5037 instruct loadUS2L(rRegL dst, memory mem)
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5038 %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5039 match(Set dst (ConvI2L (LoadUS mem)));
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5040
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5041 ins_cost(125);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5042 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5043
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5044 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5045 __ movzwq($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5046 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5047
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5048 ins_pipe(ialu_reg_mem);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5049 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5050
824
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5051 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5052 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5053 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5054
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5055 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5056 ins_encode %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5057 __ movzbq($dst$$Register, $mem$$Address);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5058 %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5059 ins_pipe(ialu_reg_mem);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5060 %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5061
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5062 // Load Unsigned Short/Char (16 bit UNsigned) with mask into Long Register
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5063 instruct loadUS2L_immI16(rRegL dst, memory mem, immI16 mask, rFlagsReg cr) %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5064 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5065 effect(KILL cr);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5066
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5067 format %{ "movzwq $dst, $mem\t# ushort/char & 16-bit mask -> long\n\t"
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5068 "andl $dst, $mask" %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5069 ins_encode %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5070 Register Rdst = $dst$$Register;
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5071 __ movzwq(Rdst, $mem$$Address);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5072 __ andl(Rdst, $mask$$constant);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5073 %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5074 ins_pipe(ialu_reg_mem);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5075 %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5076
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5077 // Load Integer
a61af66fc99e Initial load
duke
parents:
diff changeset
5078 instruct loadI(rRegI dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
5079 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5080 match(Set dst (LoadI mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5081
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5082 ins_cost(125);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5083 format %{ "movl $dst, $mem\t# int" %}
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5084
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5085 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5086 __ movl($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5087 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5088
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5089 ins_pipe(ialu_reg_mem);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5090 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5091
785
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5092 // Load Integer (32 bit signed) to Byte (8 bit signed)
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5093 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5094 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5095
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5096 ins_cost(125);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5097 format %{ "movsbl $dst, $mem\t# int -> byte" %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5098 ins_encode %{
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5099 __ movsbl($dst$$Register, $mem$$Address);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5100 %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5101 ins_pipe(ialu_reg_mem);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5102 %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5103
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5104 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5105 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5106 match(Set dst (AndI (LoadI mem) mask));
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5107
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5108 ins_cost(125);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5109 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5110 ins_encode %{
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5111 __ movzbl($dst$$Register, $mem$$Address);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5112 %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5113 ins_pipe(ialu_reg_mem);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5114 %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5115
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5116 // Load Integer (32 bit signed) to Short (16 bit signed)
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5117 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5118 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5119
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5120 ins_cost(125);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5121 format %{ "movswl $dst, $mem\t# int -> short" %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5122 ins_encode %{
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5123 __ movswl($dst$$Register, $mem$$Address);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5124 %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5125 ins_pipe(ialu_reg_mem);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5126 %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5127
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5128 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5129 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5130 match(Set dst (AndI (LoadI mem) mask));
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5131
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5132 ins_cost(125);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5133 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5134 ins_encode %{
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5135 __ movzwl($dst$$Register, $mem$$Address);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5136 %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5137 ins_pipe(ialu_reg_mem);
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5138 %}
2056494941db 6814842: Load shortening optimizations
twisti
parents: 775
diff changeset
5139
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5140 // Load Integer into Long Register
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5141 instruct loadI2L(rRegL dst, memory mem)
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5142 %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5143 match(Set dst (ConvI2L (LoadI mem)));
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5144
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5145 ins_cost(125);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5146 format %{ "movslq $dst, $mem\t# int -> long" %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5147
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5148 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5149 __ movslq($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5150 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5151
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5152 ins_pipe(ialu_reg_mem);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5153 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5154
824
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5155 // Load Integer with mask 0xFF into Long Register
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5156 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5157 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5158
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5159 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5160 ins_encode %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5161 __ movzbq($dst$$Register, $mem$$Address);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5162 %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5163 ins_pipe(ialu_reg_mem);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5164 %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5165
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5166 // Load Integer with mask 0xFFFF into Long Register
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5167 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5168 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5169
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5170 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5171 ins_encode %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5172 __ movzwq($dst$$Register, $mem$$Address);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5173 %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5174 ins_pipe(ialu_reg_mem);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5175 %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5176
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5177 // Load Integer with a 32-bit mask into Long Register
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5178 instruct loadI2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5179 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5180 effect(KILL cr);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5181
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5182 format %{ "movl $dst, $mem\t# int & 32-bit mask -> long\n\t"
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5183 "andl $dst, $mask" %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5184 ins_encode %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5185 Register Rdst = $dst$$Register;
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5186 __ movl(Rdst, $mem$$Address);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5187 __ andl(Rdst, $mask$$constant);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5188 %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5189 ins_pipe(ialu_reg_mem);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5190 %}
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
5191
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5192 // Load Unsigned Integer into Long Register
6849
f6badecb7ea7 7199654: Remove LoadUI2LNode
vlivanov
parents: 6848
diff changeset
5193 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask)
f6badecb7ea7 7199654: Remove LoadUI2LNode
vlivanov
parents: 6848
diff changeset
5194 %{
f6badecb7ea7 7199654: Remove LoadUI2LNode
vlivanov
parents: 6848
diff changeset
5195 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5196
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5197 ins_cost(125);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5198 format %{ "movl $dst, $mem\t# uint -> long" %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5199
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5200 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5201 __ movl($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5202 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5203
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5204 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5205 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5206
a61af66fc99e Initial load
duke
parents:
diff changeset
5207 // Load Long
a61af66fc99e Initial load
duke
parents:
diff changeset
5208 instruct loadL(rRegL dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
5209 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5210 match(Set dst (LoadL mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5211
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5212 ins_cost(125);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5213 format %{ "movq $dst, $mem\t# long" %}
624
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5214
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5215 ins_encode %{
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5216 __ movq($dst$$Register, $mem$$Address);
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5217 %}
337400e7a5dd 6797305: Add LoadUB and LoadUI opcode class
twisti
parents: 622
diff changeset
5218
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5219 ins_pipe(ialu_reg_mem); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5220 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5221
a61af66fc99e Initial load
duke
parents:
diff changeset
5222 // Load Range
a61af66fc99e Initial load
duke
parents:
diff changeset
5223 instruct loadRange(rRegI dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
5224 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5225 match(Set dst (LoadRange mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5226
a61af66fc99e Initial load
duke
parents:
diff changeset
5227 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5228 format %{ "movl $dst, $mem\t# range" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5229 opcode(0x8B);
a61af66fc99e Initial load
duke
parents:
diff changeset
5230 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5231 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5232 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5233
a61af66fc99e Initial load
duke
parents:
diff changeset
5234 // Load Pointer
a61af66fc99e Initial load
duke
parents:
diff changeset
5235 instruct loadP(rRegP dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
5236 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5237 match(Set dst (LoadP mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5238
a61af66fc99e Initial load
duke
parents:
diff changeset
5239 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5240 format %{ "movq $dst, $mem\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5241 opcode(0x8B);
a61af66fc99e Initial load
duke
parents:
diff changeset
5242 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5243 ins_pipe(ialu_reg_mem); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5244 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5245
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5246 // Load Compressed Pointer
163
885ed790ecf0 6695810: null oop passed to encode_heap_oop_not_null
kvn
parents: 145
diff changeset
5247 instruct loadN(rRegN dst, memory mem)
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5248 %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5249 match(Set dst (LoadN mem));
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5250
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5251 ins_cost(125); // XXX
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5252 format %{ "movl $dst, $mem\t# compressed ptr" %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5253 ins_encode %{
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5254 __ movl($dst$$Register, $mem$$Address);
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5255 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5256 ins_pipe(ialu_reg_mem); // XXX
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5257 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5258
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5259
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5260 // Load Klass Pointer
a61af66fc99e Initial load
duke
parents:
diff changeset
5261 instruct loadKlass(rRegP dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
5262 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5263 match(Set dst (LoadKlass mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5264
a61af66fc99e Initial load
duke
parents:
diff changeset
5265 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5266 format %{ "movq $dst, $mem\t# class" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5267 opcode(0x8B);
a61af66fc99e Initial load
duke
parents:
diff changeset
5268 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5269 ins_pipe(ialu_reg_mem); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5270 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5271
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
5272 // Load narrow Klass Pointer
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
5273 instruct loadNKlass(rRegN dst, memory mem)
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
5274 %{
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
5275 match(Set dst (LoadNKlass mem));
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5276
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5277 ins_cost(125); // XXX
182
44abbb0d4c18 6709093: Compressed Oops: reduce size of compiled methods
kvn
parents: 169
diff changeset
5278 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5279 ins_encode %{
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5280 __ movl($dst$$Register, $mem$$Address);
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5281 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5282 ins_pipe(ialu_reg_mem); // XXX
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5283 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5284
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5285 // Load Float
a61af66fc99e Initial load
duke
parents:
diff changeset
5286 instruct loadF(regF dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
5287 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5288 match(Set dst (LoadF mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5289
a61af66fc99e Initial load
duke
parents:
diff changeset
5290 ins_cost(145); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5291 format %{ "movss $dst, $mem\t# float" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5292 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5293 __ movflt($dst$$XMMRegister, $mem$$Address);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5294 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5295 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5296 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5297
a61af66fc99e Initial load
duke
parents:
diff changeset
5298 // Load Double
a61af66fc99e Initial load
duke
parents:
diff changeset
5299 instruct loadD_partial(regD dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
5300 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5301 predicate(!UseXmmLoadAndClearUpper);
a61af66fc99e Initial load
duke
parents:
diff changeset
5302 match(Set dst (LoadD mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5303
a61af66fc99e Initial load
duke
parents:
diff changeset
5304 ins_cost(145); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5305 format %{ "movlpd $dst, $mem\t# double" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5306 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5307 __ movdbl($dst$$XMMRegister, $mem$$Address);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5308 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5309 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5310 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5311
a61af66fc99e Initial load
duke
parents:
diff changeset
5312 instruct loadD(regD dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
5313 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5314 predicate(UseXmmLoadAndClearUpper);
a61af66fc99e Initial load
duke
parents:
diff changeset
5315 match(Set dst (LoadD mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5316
a61af66fc99e Initial load
duke
parents:
diff changeset
5317 ins_cost(145); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5318 format %{ "movsd $dst, $mem\t# double" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5319 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5320 __ movdbl($dst$$XMMRegister, $mem$$Address);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5321 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5322 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5323 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5324
a61af66fc99e Initial load
duke
parents:
diff changeset
5325 // Load Effective Address
a61af66fc99e Initial load
duke
parents:
diff changeset
5326 instruct leaP8(rRegP dst, indOffset8 mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
5327 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5328 match(Set dst mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5329
a61af66fc99e Initial load
duke
parents:
diff changeset
5330 ins_cost(110); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5331 format %{ "leaq $dst, $mem\t# ptr 8" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5332 opcode(0x8D);
a61af66fc99e Initial load
duke
parents:
diff changeset
5333 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5334 ins_pipe(ialu_reg_reg_fat);
a61af66fc99e Initial load
duke
parents:
diff changeset
5335 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5336
a61af66fc99e Initial load
duke
parents:
diff changeset
5337 instruct leaP32(rRegP dst, indOffset32 mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
5338 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5339 match(Set dst mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5340
a61af66fc99e Initial load
duke
parents:
diff changeset
5341 ins_cost(110);
a61af66fc99e Initial load
duke
parents:
diff changeset
5342 format %{ "leaq $dst, $mem\t# ptr 32" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5343 opcode(0x8D);
a61af66fc99e Initial load
duke
parents:
diff changeset
5344 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5345 ins_pipe(ialu_reg_reg_fat);
a61af66fc99e Initial load
duke
parents:
diff changeset
5346 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5347
a61af66fc99e Initial load
duke
parents:
diff changeset
5348 // instruct leaPIdx(rRegP dst, indIndex mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
5349 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5350 // match(Set dst mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5351
a61af66fc99e Initial load
duke
parents:
diff changeset
5352 // ins_cost(110);
a61af66fc99e Initial load
duke
parents:
diff changeset
5353 // format %{ "leaq $dst, $mem\t# ptr idx" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5354 // opcode(0x8D);
a61af66fc99e Initial load
duke
parents:
diff changeset
5355 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5356 // ins_pipe(ialu_reg_reg_fat);
a61af66fc99e Initial load
duke
parents:
diff changeset
5357 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5358
a61af66fc99e Initial load
duke
parents:
diff changeset
5359 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
5360 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5361 match(Set dst mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5362
a61af66fc99e Initial load
duke
parents:
diff changeset
5363 ins_cost(110);
a61af66fc99e Initial load
duke
parents:
diff changeset
5364 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5365 opcode(0x8D);
a61af66fc99e Initial load
duke
parents:
diff changeset
5366 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5367 ins_pipe(ialu_reg_reg_fat);
a61af66fc99e Initial load
duke
parents:
diff changeset
5368 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5369
a61af66fc99e Initial load
duke
parents:
diff changeset
5370 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
5371 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5372 match(Set dst mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5373
a61af66fc99e Initial load
duke
parents:
diff changeset
5374 ins_cost(110);
a61af66fc99e Initial load
duke
parents:
diff changeset
5375 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5376 opcode(0x8D);
a61af66fc99e Initial load
duke
parents:
diff changeset
5377 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5378 ins_pipe(ialu_reg_reg_fat);
a61af66fc99e Initial load
duke
parents:
diff changeset
5379 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5380
a61af66fc99e Initial load
duke
parents:
diff changeset
5381 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
5382 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5383 match(Set dst mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5384
a61af66fc99e Initial load
duke
parents:
diff changeset
5385 ins_cost(110);
a61af66fc99e Initial load
duke
parents:
diff changeset
5386 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5387 opcode(0x8D);
a61af66fc99e Initial load
duke
parents:
diff changeset
5388 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5389 ins_pipe(ialu_reg_reg_fat);
a61af66fc99e Initial load
duke
parents:
diff changeset
5390 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5391
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5392 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5393 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5394 match(Set dst mem);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5395
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5396 ins_cost(110);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5397 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5398 opcode(0x8D);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5399 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5400 ins_pipe(ialu_reg_reg_fat);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5401 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5402
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5403 // Load Effective Address which uses Narrow (32-bits) oop
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5404 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5405 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5406 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5407 match(Set dst mem);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5408
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5409 ins_cost(110);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5410 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5411 opcode(0x8D);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5412 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5413 ins_pipe(ialu_reg_reg_fat);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5414 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5415
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5416 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5417 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5418 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5419 match(Set dst mem);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5420
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5421 ins_cost(110); // XXX
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5422 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5423 opcode(0x8D);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5424 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5425 ins_pipe(ialu_reg_reg_fat);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5426 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5427
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5428 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5429 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5430 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5431 match(Set dst mem);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5432
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5433 ins_cost(110);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5434 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5435 opcode(0x8D);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5436 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5437 ins_pipe(ialu_reg_reg_fat);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5438 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5439
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5440 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5441 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5442 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5443 match(Set dst mem);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5444
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5445 ins_cost(110);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5446 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5447 opcode(0x8D);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5448 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5449 ins_pipe(ialu_reg_reg_fat);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5450 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5451
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5452 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5453 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5454 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5455 match(Set dst mem);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5456
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5457 ins_cost(110);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5458 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5459 opcode(0x8D);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5460 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5461 ins_pipe(ialu_reg_reg_fat);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5462 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5463
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5464 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5465 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5466 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5467 match(Set dst mem);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5468
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5469 ins_cost(110);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5470 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5471 opcode(0x8D);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5472 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5473 ins_pipe(ialu_reg_reg_fat);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5474 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5475
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5476 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5477 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5478 predicate(Universe::narrow_oop_shift() == 0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5479 match(Set dst mem);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5480
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5481 ins_cost(110);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5482 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5483 opcode(0x8D);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5484 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5485 ins_pipe(ialu_reg_reg_fat);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5486 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5487
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5488 instruct loadConI(rRegI dst, immI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5489 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5490 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5491
a61af66fc99e Initial load
duke
parents:
diff changeset
5492 format %{ "movl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5493 ins_encode(load_immI(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5494 ins_pipe(ialu_reg_fat); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5495 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5496
a61af66fc99e Initial load
duke
parents:
diff changeset
5497 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
5498 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5499 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5500 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
5501
a61af66fc99e Initial load
duke
parents:
diff changeset
5502 ins_cost(50);
a61af66fc99e Initial load
duke
parents:
diff changeset
5503 format %{ "xorl $dst, $dst\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5504 opcode(0x33); /* + rd */
a61af66fc99e Initial load
duke
parents:
diff changeset
5505 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
5506 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
5507 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5508
a61af66fc99e Initial load
duke
parents:
diff changeset
5509 instruct loadConL(rRegL dst, immL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5510 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5511 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5512
a61af66fc99e Initial load
duke
parents:
diff changeset
5513 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
5514 format %{ "movq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5515 ins_encode(load_immL(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5516 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
5517 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5518
a61af66fc99e Initial load
duke
parents:
diff changeset
5519 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
5520 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5521 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5522 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
5523
a61af66fc99e Initial load
duke
parents:
diff changeset
5524 ins_cost(50);
a61af66fc99e Initial load
duke
parents:
diff changeset
5525 format %{ "xorl $dst, $dst\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5526 opcode(0x33); /* + rd */
a61af66fc99e Initial load
duke
parents:
diff changeset
5527 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
5528 ins_pipe(ialu_reg); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5529 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5530
a61af66fc99e Initial load
duke
parents:
diff changeset
5531 instruct loadConUL32(rRegL dst, immUL32 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5532 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5533 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5534
a61af66fc99e Initial load
duke
parents:
diff changeset
5535 ins_cost(60);
a61af66fc99e Initial load
duke
parents:
diff changeset
5536 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5537 ins_encode(load_immUL32(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5538 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
5539 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5540
a61af66fc99e Initial load
duke
parents:
diff changeset
5541 instruct loadConL32(rRegL dst, immL32 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5542 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5543 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5544
a61af66fc99e Initial load
duke
parents:
diff changeset
5545 ins_cost(70);
a61af66fc99e Initial load
duke
parents:
diff changeset
5546 format %{ "movq $dst, $src\t# long (32-bit)" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5547 ins_encode(load_immL32(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5548 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
5549 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5550
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
5551 instruct loadConP(rRegP dst, immP con) %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
5552 match(Set dst con);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
5553
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
5554 format %{ "movq $dst, $con\t# ptr" %}
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
5555 ins_encode(load_immP(dst, con));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5556 ins_pipe(ialu_reg_fat); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5557 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5558
a61af66fc99e Initial load
duke
parents:
diff changeset
5559 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
5560 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5561 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5562 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
5563
a61af66fc99e Initial load
duke
parents:
diff changeset
5564 ins_cost(50);
a61af66fc99e Initial load
duke
parents:
diff changeset
5565 format %{ "xorl $dst, $dst\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5566 opcode(0x33); /* + rd */
a61af66fc99e Initial load
duke
parents:
diff changeset
5567 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
5568 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
5569 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5570
a61af66fc99e Initial load
duke
parents:
diff changeset
5571 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
5572 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5573 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5574 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
5575
a61af66fc99e Initial load
duke
parents:
diff changeset
5576 ins_cost(60);
a61af66fc99e Initial load
duke
parents:
diff changeset
5577 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5578 ins_encode(load_immP31(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5579 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
5580 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5581
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
5582 instruct loadConF(regF dst, immF con) %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
5583 match(Set dst con);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5584 ins_cost(125);
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
5585 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
5586 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
5587 __ movflt($dst$$XMMRegister, $constantaddress($con));
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
5588 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5589 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
5590 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5591
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5592 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5593 match(Set dst src);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5594 effect(KILL cr);
124
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
5595 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5596 ins_encode %{
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5597 __ xorq($dst$$Register, $dst$$Register);
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5598 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5599 ins_pipe(ialu_reg);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5600 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5601
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
5602 instruct loadConN(rRegN dst, immN src) %{
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5603 match(Set dst src);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5604
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5605 ins_cost(125);
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
5606 format %{ "movl $dst, $src\t# compressed ptr" %}
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5607 ins_encode %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5608 address con = (address)$src$$constant;
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5609 if (con == NULL) {
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5610 ShouldNotReachHere();
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5611 } else {
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5612 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5613 }
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5614 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5615 ins_pipe(ialu_reg_fat); // XXX
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5616 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5617
6848
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5618 instruct loadConNKlass(rRegN dst, immNKlass src) %{
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5619 match(Set dst src);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5620
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5621 ins_cost(125);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5622 format %{ "movl $dst, $src\t# compressed klass ptr" %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5623 ins_encode %{
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5624 address con = (address)$src$$constant;
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5625 if (con == NULL) {
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5626 ShouldNotReachHere();
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5627 } else {
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5628 __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5629 }
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5630 %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5631 ins_pipe(ialu_reg_fat); // XXX
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5632 %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5633
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5634 instruct loadConF0(regF dst, immF0 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5635 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5636 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5637 ins_cost(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
5638
a61af66fc99e Initial load
duke
parents:
diff changeset
5639 format %{ "xorps $dst, $dst\t# float 0.0" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5640 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5641 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5642 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5643 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
5644 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5645
a61af66fc99e Initial load
duke
parents:
diff changeset
5646 // Use the same format since predicate() can not be used here.
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
5647 instruct loadConD(regD dst, immD con) %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
5648 match(Set dst con);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5649 ins_cost(125);
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
5650 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
5651 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
5652 __ movdbl($dst$$XMMRegister, $constantaddress($con));
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
5653 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5654 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
5655 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5656
a61af66fc99e Initial load
duke
parents:
diff changeset
5657 instruct loadConD0(regD dst, immD0 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5658 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5659 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5660 ins_cost(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
5661
a61af66fc99e Initial load
duke
parents:
diff changeset
5662 format %{ "xorpd $dst, $dst\t# double 0.0" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5663 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5664 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5665 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5666 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
5667 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5668
a61af66fc99e Initial load
duke
parents:
diff changeset
5669 instruct loadSSI(rRegI dst, stackSlotI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5670 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5671 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5672
a61af66fc99e Initial load
duke
parents:
diff changeset
5673 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
5674 format %{ "movl $dst, $src\t# int stk" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5675 opcode(0x8B);
a61af66fc99e Initial load
duke
parents:
diff changeset
5676 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5677 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5678 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5679
a61af66fc99e Initial load
duke
parents:
diff changeset
5680 instruct loadSSL(rRegL dst, stackSlotL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5681 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5682 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5683
a61af66fc99e Initial load
duke
parents:
diff changeset
5684 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
5685 format %{ "movq $dst, $src\t# long stk" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5686 opcode(0x8B);
a61af66fc99e Initial load
duke
parents:
diff changeset
5687 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5688 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5689 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5690
a61af66fc99e Initial load
duke
parents:
diff changeset
5691 instruct loadSSP(rRegP dst, stackSlotP src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5692 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5693 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5694
a61af66fc99e Initial load
duke
parents:
diff changeset
5695 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
5696 format %{ "movq $dst, $src\t# ptr stk" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5697 opcode(0x8B);
a61af66fc99e Initial load
duke
parents:
diff changeset
5698 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5699 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5700 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5701
a61af66fc99e Initial load
duke
parents:
diff changeset
5702 instruct loadSSF(regF dst, stackSlotF src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5703 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5704 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5705
a61af66fc99e Initial load
duke
parents:
diff changeset
5706 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
5707 format %{ "movss $dst, $src\t# float stk" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5708 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5709 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
5710 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5711 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5712 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5713
a61af66fc99e Initial load
duke
parents:
diff changeset
5714 // Use the same format since predicate() can not be used here.
a61af66fc99e Initial load
duke
parents:
diff changeset
5715 instruct loadSSD(regD dst, stackSlotD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5716 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5717 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
5718
a61af66fc99e Initial load
duke
parents:
diff changeset
5719 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
5720 format %{ "movsd $dst, $src\t# double stk" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5721 ins_encode %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5722 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
a61af66fc99e Initial load
duke
parents:
diff changeset
5723 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5724 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5725 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5726
a61af66fc99e Initial load
duke
parents:
diff changeset
5727 // Prefetch instructions.
a61af66fc99e Initial load
duke
parents:
diff changeset
5728 // Must be safe to execute with invalid address (cannot fault).
a61af66fc99e Initial load
duke
parents:
diff changeset
5729
a61af66fc99e Initial load
duke
parents:
diff changeset
5730 instruct prefetchr( memory mem ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5731 predicate(ReadPrefetchInstr==3);
a61af66fc99e Initial load
duke
parents:
diff changeset
5732 match(PrefetchRead mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5733 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
5734
a61af66fc99e Initial load
duke
parents:
diff changeset
5735 format %{ "PREFETCHR $mem\t# Prefetch into level 1 cache" %}
3854
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5736 ins_encode %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5737 __ prefetchr($mem$$Address);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5738 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5739 ins_pipe(ialu_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5740 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5741
a61af66fc99e Initial load
duke
parents:
diff changeset
5742 instruct prefetchrNTA( memory mem ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5743 predicate(ReadPrefetchInstr==0);
a61af66fc99e Initial load
duke
parents:
diff changeset
5744 match(PrefetchRead mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5745 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
5746
a61af66fc99e Initial load
duke
parents:
diff changeset
5747 format %{ "PREFETCHNTA $mem\t# Prefetch into non-temporal cache for read" %}
3854
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5748 ins_encode %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5749 __ prefetchnta($mem$$Address);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5750 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5751 ins_pipe(ialu_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5752 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5753
a61af66fc99e Initial load
duke
parents:
diff changeset
5754 instruct prefetchrT0( memory mem ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5755 predicate(ReadPrefetchInstr==1);
a61af66fc99e Initial load
duke
parents:
diff changeset
5756 match(PrefetchRead mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5757 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
5758
a61af66fc99e Initial load
duke
parents:
diff changeset
5759 format %{ "PREFETCHT0 $mem\t# prefetch into L1 and L2 caches for read" %}
3854
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5760 ins_encode %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5761 __ prefetcht0($mem$$Address);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5762 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5763 ins_pipe(ialu_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5764 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5765
a61af66fc99e Initial load
duke
parents:
diff changeset
5766 instruct prefetchrT2( memory mem ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5767 predicate(ReadPrefetchInstr==2);
a61af66fc99e Initial load
duke
parents:
diff changeset
5768 match(PrefetchRead mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5769 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
5770
a61af66fc99e Initial load
duke
parents:
diff changeset
5771 format %{ "PREFETCHT2 $mem\t# prefetch into L2 caches for read" %}
3854
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5772 ins_encode %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5773 __ prefetcht2($mem$$Address);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5774 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5775 ins_pipe(ialu_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5776 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5777
a61af66fc99e Initial load
duke
parents:
diff changeset
5778 instruct prefetchwNTA( memory mem ) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5779 match(PrefetchWrite mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5780 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
5781
a61af66fc99e Initial load
duke
parents:
diff changeset
5782 format %{ "PREFETCHNTA $mem\t# Prefetch to non-temporal cache for write" %}
3854
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5783 ins_encode %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5784 __ prefetchnta($mem$$Address);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5785 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5786 ins_pipe(ialu_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5787 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5788
3854
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5789 // Prefetch instructions for allocation.
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5790
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5791 instruct prefetchAlloc( memory mem ) %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5792 predicate(AllocatePrefetchInstr==3);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5793 match(PrefetchAllocation mem);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5794 ins_cost(125);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5795
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5796 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5797 ins_encode %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5798 __ prefetchw($mem$$Address);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5799 %}
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5800 ins_pipe(ialu_mem);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5801 %}
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5802
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5803 instruct prefetchAllocNTA( memory mem ) %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5804 predicate(AllocatePrefetchInstr==0);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5805 match(PrefetchAllocation mem);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5806 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
5807
3854
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5808 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5809 ins_encode %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5810 __ prefetchnta($mem$$Address);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5811 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5812 ins_pipe(ialu_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5813 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5814
3854
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5815 instruct prefetchAllocT0( memory mem ) %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5816 predicate(AllocatePrefetchInstr==1);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5817 match(PrefetchAllocation mem);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5818 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
5819
3854
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5820 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5821 ins_encode %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5822 __ prefetcht0($mem$$Address);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5823 %}
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5824 ins_pipe(ialu_mem);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5825 %}
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5826
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5827 instruct prefetchAllocT2( memory mem ) %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5828 predicate(AllocatePrefetchInstr==2);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5829 match(PrefetchAllocation mem);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5830 ins_cost(125);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5831
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5832 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5833 ins_encode %{
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5834 __ prefetcht2($mem$$Address);
1af104d6cf99 7079329: Adjust allocation prefetching for T4
kvn
parents: 3851
diff changeset
5835 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5836 ins_pipe(ialu_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
5837 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5838
a61af66fc99e Initial load
duke
parents:
diff changeset
5839 //----------Store Instructions-------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
5840
a61af66fc99e Initial load
duke
parents:
diff changeset
5841 // Store Byte
a61af66fc99e Initial load
duke
parents:
diff changeset
5842 instruct storeB(memory mem, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5843 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5844 match(Set mem (StoreB mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5845
a61af66fc99e Initial load
duke
parents:
diff changeset
5846 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5847 format %{ "movb $mem, $src\t# byte" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5848 opcode(0x88);
a61af66fc99e Initial load
duke
parents:
diff changeset
5849 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5850 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
5851 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5852
a61af66fc99e Initial load
duke
parents:
diff changeset
5853 // Store Char/Short
a61af66fc99e Initial load
duke
parents:
diff changeset
5854 instruct storeC(memory mem, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5855 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5856 match(Set mem (StoreC mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5857
a61af66fc99e Initial load
duke
parents:
diff changeset
5858 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5859 format %{ "movw $mem, $src\t# char/short" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5860 opcode(0x89);
a61af66fc99e Initial load
duke
parents:
diff changeset
5861 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5862 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
5863 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5864
a61af66fc99e Initial load
duke
parents:
diff changeset
5865 // Store Integer
a61af66fc99e Initial load
duke
parents:
diff changeset
5866 instruct storeI(memory mem, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5867 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5868 match(Set mem (StoreI mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5869
a61af66fc99e Initial load
duke
parents:
diff changeset
5870 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5871 format %{ "movl $mem, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5872 opcode(0x89);
a61af66fc99e Initial load
duke
parents:
diff changeset
5873 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5874 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
5875 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5876
a61af66fc99e Initial load
duke
parents:
diff changeset
5877 // Store Long
a61af66fc99e Initial load
duke
parents:
diff changeset
5878 instruct storeL(memory mem, rRegL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5879 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5880 match(Set mem (StoreL mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5881
a61af66fc99e Initial load
duke
parents:
diff changeset
5882 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5883 format %{ "movq $mem, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5884 opcode(0x89);
a61af66fc99e Initial load
duke
parents:
diff changeset
5885 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5886 ins_pipe(ialu_mem_reg); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5887 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5888
a61af66fc99e Initial load
duke
parents:
diff changeset
5889 // Store Pointer
a61af66fc99e Initial load
duke
parents:
diff changeset
5890 instruct storeP(memory mem, any_RegP src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5891 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5892 match(Set mem (StoreP mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5893
a61af66fc99e Initial load
duke
parents:
diff changeset
5894 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
5895 format %{ "movq $mem, $src\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5896 opcode(0x89);
a61af66fc99e Initial load
duke
parents:
diff changeset
5897 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
5898 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
5899 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5900
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5901 instruct storeImmP0(memory mem, immP0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5902 %{
6848
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5903 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5904 match(Set mem (StoreP mem zero));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5905
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5906 ins_cost(125); // XXX
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5907 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5908 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5909 __ movq($mem$$Address, r12);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5910 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5911 ins_pipe(ialu_mem_reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5912 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5913
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5914 // Store NULL Pointer, mark word, or other simple pointer constant.
a61af66fc99e Initial load
duke
parents:
diff changeset
5915 instruct storeImmP(memory mem, immP31 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
5916 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
5917 match(Set mem (StoreP mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5918
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5919 ins_cost(150); // XXX
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5920 format %{ "movq $mem, $src\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5921 opcode(0xC7); /* C7 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
5922 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
5923 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
5924 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
5925
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5926 // Store Compressed Pointer
163
885ed790ecf0 6695810: null oop passed to encode_heap_oop_not_null
kvn
parents: 145
diff changeset
5927 instruct storeN(memory mem, rRegN src)
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5928 %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5929 match(Set mem (StoreN mem src));
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5930
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5931 ins_cost(125); // XXX
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
5932 format %{ "movl $mem, $src\t# compressed ptr" %}
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5933 ins_encode %{
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5934 __ movl($mem$$Address, $src$$Register);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5935 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5936 ins_pipe(ialu_mem_reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5937 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5938
6848
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5939 instruct storeNKlass(memory mem, rRegN src)
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5940 %{
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5941 match(Set mem (StoreNKlass mem src));
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5942
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5943 ins_cost(125); // XXX
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5944 format %{ "movl $mem, $src\t# compressed klass ptr" %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5945 ins_encode %{
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5946 __ movl($mem$$Address, $src$$Register);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5947 %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5948 ins_pipe(ialu_mem_reg);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5949 %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5950
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5951 instruct storeImmN0(memory mem, immN0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5952 %{
6848
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5953 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_klass_base() == NULL);
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5954 match(Set mem (StoreN mem zero));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5955
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5956 ins_cost(125); // XXX
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5957 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5958 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5959 __ movl($mem$$Address, r12);
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5960 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5961 ins_pipe(ialu_mem_reg);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5962 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
5963
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5964 instruct storeImmN(memory mem, immN src)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5965 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5966 match(Set mem (StoreN mem src));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5967
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5968 ins_cost(150); // XXX
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5969 format %{ "movl $mem, $src\t# compressed ptr" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5970 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5971 address con = (address)$src$$constant;
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5972 if (con == NULL) {
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5973 __ movl($mem$$Address, (int32_t)0);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5974 } else {
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5975 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5976 }
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5977 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5978 ins_pipe(ialu_mem_imm);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5979 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5980
6848
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5981 instruct storeImmNKlass(memory mem, immNKlass src)
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5982 %{
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5983 match(Set mem (StoreNKlass mem src));
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5984
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5985 ins_cost(150); // XXX
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5986 format %{ "movl $mem, $src\t# compressed klass ptr" %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5987 ins_encode %{
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5988 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5989 %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5990 ins_pipe(ialu_mem_imm);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5991 %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5992
0
a61af66fc99e Initial load
duke
parents:
diff changeset
5993 // Store Integer Immediate
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5994 instruct storeImmI0(memory mem, immI0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5995 %{
6848
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
5996 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5997 match(Set mem (StoreI mem zero));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5998
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
5999 ins_cost(125); // XXX
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6000 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6001 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6002 __ movl($mem$$Address, r12);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6003 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6004 ins_pipe(ialu_mem_reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6005 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6006
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6007 instruct storeImmI(memory mem, immI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6008 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6009 match(Set mem (StoreI mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6010
a61af66fc99e Initial load
duke
parents:
diff changeset
6011 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
6012 format %{ "movl $mem, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6013 opcode(0xC7); /* C7 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
6014 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6015 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
6016 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6017
a61af66fc99e Initial load
duke
parents:
diff changeset
6018 // Store Long Immediate
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6019 instruct storeImmL0(memory mem, immL0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6020 %{
6848
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
6021 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6022 match(Set mem (StoreL mem zero));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6023
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6024 ins_cost(125); // XXX
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6025 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6026 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6027 __ movq($mem$$Address, r12);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6028 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6029 ins_pipe(ialu_mem_reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6030 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6031
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6032 instruct storeImmL(memory mem, immL32 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6033 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6034 match(Set mem (StoreL mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6035
a61af66fc99e Initial load
duke
parents:
diff changeset
6036 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
6037 format %{ "movq $mem, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6038 opcode(0xC7); /* C7 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
6039 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6040 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
6041 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6042
a61af66fc99e Initial load
duke
parents:
diff changeset
6043 // Store Short/Char Immediate
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6044 instruct storeImmC0(memory mem, immI0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6045 %{
6848
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
6046 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6047 match(Set mem (StoreC mem zero));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6048
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6049 ins_cost(125); // XXX
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6050 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6051 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6052 __ movw($mem$$Address, r12);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6053 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6054 ins_pipe(ialu_mem_reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6055 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6056
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6057 instruct storeImmI16(memory mem, immI16 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6058 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6059 predicate(UseStoreImmI16);
a61af66fc99e Initial load
duke
parents:
diff changeset
6060 match(Set mem (StoreC mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6061
a61af66fc99e Initial load
duke
parents:
diff changeset
6062 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
6063 format %{ "movw $mem, $src\t# short/char" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6064 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
a61af66fc99e Initial load
duke
parents:
diff changeset
6065 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6066 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
6067 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6068
a61af66fc99e Initial load
duke
parents:
diff changeset
6069 // Store Byte Immediate
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6070 instruct storeImmB0(memory mem, immI0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6071 %{
6848
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
6072 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6073 match(Set mem (StoreB mem zero));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6074
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6075 ins_cost(125); // XXX
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6076 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6077 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6078 __ movb($mem$$Address, r12);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6079 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6080 ins_pipe(ialu_mem_reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6081 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6082
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6083 instruct storeImmB(memory mem, immI8 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6084 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6085 match(Set mem (StoreB mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6086
a61af66fc99e Initial load
duke
parents:
diff changeset
6087 ins_cost(150); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6088 format %{ "movb $mem, $src\t# byte" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6089 opcode(0xC6); /* C6 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
6090 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6091 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
6092 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6093
a61af66fc99e Initial load
duke
parents:
diff changeset
6094 // Store CMS card-mark Immediate
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6095 instruct storeImmCM0_reg(memory mem, immI0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6096 %{
6848
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
6097 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6098 match(Set mem (StoreCM mem zero));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6099
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6100 ins_cost(125); // XXX
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6101 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6102 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6103 __ movb($mem$$Address, r12);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6104 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6105 ins_pipe(ialu_mem_reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6106 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6107
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6108 instruct storeImmCM0(memory mem, immI0 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6109 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6110 match(Set mem (StoreCM mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6111
a61af66fc99e Initial load
duke
parents:
diff changeset
6112 ins_cost(150); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6113 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6114 opcode(0xC6); /* C6 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
6115 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6116 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
6117 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6118
a61af66fc99e Initial load
duke
parents:
diff changeset
6119 // Store Float
a61af66fc99e Initial load
duke
parents:
diff changeset
6120 instruct storeF(memory mem, regF src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6121 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6122 match(Set mem (StoreF mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6123
a61af66fc99e Initial load
duke
parents:
diff changeset
6124 ins_cost(95); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6125 format %{ "movss $mem, $src\t# float" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6126 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6127 __ movflt($mem$$Address, $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6128 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6129 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6130 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6131
a61af66fc99e Initial load
duke
parents:
diff changeset
6132 // Store immediate Float value (it is faster than store from XMM register)
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6133 instruct storeF0(memory mem, immF0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6134 %{
6848
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
6135 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6136 match(Set mem (StoreF mem zero));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6137
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6138 ins_cost(25); // XXX
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6139 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6140 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6141 __ movl($mem$$Address, r12);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6142 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6143 ins_pipe(ialu_mem_reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6144 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6145
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6146 instruct storeF_imm(memory mem, immF src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6147 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6148 match(Set mem (StoreF mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6149
a61af66fc99e Initial load
duke
parents:
diff changeset
6150 ins_cost(50);
a61af66fc99e Initial load
duke
parents:
diff changeset
6151 format %{ "movl $mem, $src\t# float" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6152 opcode(0xC7); /* C7 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
6153 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6154 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
6155 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6156
a61af66fc99e Initial load
duke
parents:
diff changeset
6157 // Store Double
a61af66fc99e Initial load
duke
parents:
diff changeset
6158 instruct storeD(memory mem, regD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6159 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6160 match(Set mem (StoreD mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6161
a61af66fc99e Initial load
duke
parents:
diff changeset
6162 ins_cost(95); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6163 format %{ "movsd $mem, $src\t# double" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6164 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6165 __ movdbl($mem$$Address, $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6166 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6167 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6168 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6169
a61af66fc99e Initial load
duke
parents:
diff changeset
6170 // Store immediate double 0.0 (it is faster than store from XMM register)
a61af66fc99e Initial load
duke
parents:
diff changeset
6171 instruct storeD0_imm(memory mem, immD0 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6172 %{
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6173 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6174 match(Set mem (StoreD mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6175
a61af66fc99e Initial load
duke
parents:
diff changeset
6176 ins_cost(50);
a61af66fc99e Initial load
duke
parents:
diff changeset
6177 format %{ "movq $mem, $src\t# double 0." %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6178 opcode(0xC7); /* C7 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
6179 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6180 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
6181 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6182
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6183 instruct storeD0(memory mem, immD0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6184 %{
6848
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
6185 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6186 match(Set mem (StoreD mem zero));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6187
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6188 ins_cost(25); // XXX
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6189 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6190 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6191 __ movq($mem$$Address, r12);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6192 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6193 ins_pipe(ialu_mem_reg);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6194 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6195
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6196 instruct storeSSI(stackSlotI dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6197 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6198 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
6199
a61af66fc99e Initial load
duke
parents:
diff changeset
6200 ins_cost(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
6201 format %{ "movl $dst, $src\t# int stk" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6202 opcode(0x89);
a61af66fc99e Initial load
duke
parents:
diff changeset
6203 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
6204 ins_pipe( ialu_mem_reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
6205 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6206
a61af66fc99e Initial load
duke
parents:
diff changeset
6207 instruct storeSSL(stackSlotL dst, rRegL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6208 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6209 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
6210
a61af66fc99e Initial load
duke
parents:
diff changeset
6211 ins_cost(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
6212 format %{ "movq $dst, $src\t# long stk" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6213 opcode(0x89);
a61af66fc99e Initial load
duke
parents:
diff changeset
6214 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
6215 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6216 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6217
a61af66fc99e Initial load
duke
parents:
diff changeset
6218 instruct storeSSP(stackSlotP dst, rRegP src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6219 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6220 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
6221
a61af66fc99e Initial load
duke
parents:
diff changeset
6222 ins_cost(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
6223 format %{ "movq $dst, $src\t# ptr stk" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6224 opcode(0x89);
a61af66fc99e Initial load
duke
parents:
diff changeset
6225 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
6226 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6227 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6228
a61af66fc99e Initial load
duke
parents:
diff changeset
6229 instruct storeSSF(stackSlotF dst, regF src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6230 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6231 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
6232
a61af66fc99e Initial load
duke
parents:
diff changeset
6233 ins_cost(95); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6234 format %{ "movss $dst, $src\t# float stk" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6235 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6236 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6237 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6238 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6239 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6240
a61af66fc99e Initial load
duke
parents:
diff changeset
6241 instruct storeSSD(stackSlotD dst, regD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6242 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6243 match(Set dst src);
a61af66fc99e Initial load
duke
parents:
diff changeset
6244
a61af66fc99e Initial load
duke
parents:
diff changeset
6245 ins_cost(95); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6246 format %{ "movsd $dst, $src\t# double stk" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6247 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6248 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6249 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6250 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6251 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6252
a61af66fc99e Initial load
duke
parents:
diff changeset
6253 //----------BSWAP Instructions-------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
6254 instruct bytes_reverse_int(rRegI dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6255 match(Set dst (ReverseBytesI dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
6256
a61af66fc99e Initial load
duke
parents:
diff changeset
6257 format %{ "bswapl $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6258 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */
a61af66fc99e Initial load
duke
parents:
diff changeset
6259 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6260 ins_pipe( ialu_reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
6261 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6262
a61af66fc99e Initial load
duke
parents:
diff changeset
6263 instruct bytes_reverse_long(rRegL dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6264 match(Set dst (ReverseBytesL dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
6265
a61af66fc99e Initial load
duke
parents:
diff changeset
6266 format %{ "bswapq $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6267 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
a61af66fc99e Initial load
duke
parents:
diff changeset
6268 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6269 ins_pipe( ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6270 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6271
6138
ccaa67adfe5b 7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents: 6084
diff changeset
6272 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
1396
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
6273 match(Set dst (ReverseBytesUS dst));
6138
ccaa67adfe5b 7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents: 6084
diff changeset
6274 effect(KILL cr);
1396
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
6275
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
6276 format %{ "bswapl $dst\n\t"
1396
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
6277 "shrl $dst,16\n\t" %}
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
6278 ins_encode %{
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
6279 __ bswapl($dst$$Register);
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
6280 __ shrl($dst$$Register, 16);
1396
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
6281 %}
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
6282 ins_pipe( ialu_reg );
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
6283 %}
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
6284
6138
ccaa67adfe5b 7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents: 6084
diff changeset
6285 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
1396
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
6286 match(Set dst (ReverseBytesS dst));
6138
ccaa67adfe5b 7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents: 6084
diff changeset
6287 effect(KILL cr);
1396
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
6288
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
6289 format %{ "bswapl $dst\n\t"
1396
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
6290 "sar $dst,16\n\t" %}
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
6291 ins_encode %{
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
6292 __ bswapl($dst$$Register);
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
6293 __ sarl($dst$$Register, 16);
1396
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
6294 %}
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
6295 ins_pipe( ialu_reg );
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
6296 %}
d7f654633cfe 6946040: add intrinsic for short and char reverseBytes
never
parents: 1274
diff changeset
6297
775
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6298 //---------- Zeros Count Instructions ------------------------------------------
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6299
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6300 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6301 predicate(UseCountLeadingZerosInstruction);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6302 match(Set dst (CountLeadingZerosI src));
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6303 effect(KILL cr);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6304
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6305 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6306 ins_encode %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6307 __ lzcntl($dst$$Register, $src$$Register);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6308 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6309 ins_pipe(ialu_reg);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6310 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6311
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6312 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6313 predicate(!UseCountLeadingZerosInstruction);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6314 match(Set dst (CountLeadingZerosI src));
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6315 effect(KILL cr);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6316
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6317 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6318 "jnz skip\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6319 "movl $dst, -1\n"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6320 "skip:\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6321 "negl $dst\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6322 "addl $dst, 31" %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6323 ins_encode %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6324 Register Rdst = $dst$$Register;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6325 Register Rsrc = $src$$Register;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6326 Label skip;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6327 __ bsrl(Rdst, Rsrc);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6328 __ jccb(Assembler::notZero, skip);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6329 __ movl(Rdst, -1);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6330 __ bind(skip);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6331 __ negl(Rdst);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6332 __ addl(Rdst, BitsPerInt - 1);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6333 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6334 ins_pipe(ialu_reg);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6335 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6336
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6337 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6338 predicate(UseCountLeadingZerosInstruction);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6339 match(Set dst (CountLeadingZerosL src));
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6340 effect(KILL cr);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6341
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6342 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6343 ins_encode %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6344 __ lzcntq($dst$$Register, $src$$Register);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6345 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6346 ins_pipe(ialu_reg);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6347 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6348
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6349 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6350 predicate(!UseCountLeadingZerosInstruction);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6351 match(Set dst (CountLeadingZerosL src));
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6352 effect(KILL cr);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6353
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6354 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6355 "jnz skip\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6356 "movl $dst, -1\n"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6357 "skip:\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6358 "negl $dst\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6359 "addl $dst, 63" %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6360 ins_encode %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6361 Register Rdst = $dst$$Register;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6362 Register Rsrc = $src$$Register;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6363 Label skip;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6364 __ bsrq(Rdst, Rsrc);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6365 __ jccb(Assembler::notZero, skip);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6366 __ movl(Rdst, -1);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6367 __ bind(skip);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6368 __ negl(Rdst);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6369 __ addl(Rdst, BitsPerLong - 1);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6370 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6371 ins_pipe(ialu_reg);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6372 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6373
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6374 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6375 match(Set dst (CountTrailingZerosI src));
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6376 effect(KILL cr);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6377
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6378 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6379 "jnz done\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6380 "movl $dst, 32\n"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6381 "done:" %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6382 ins_encode %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6383 Register Rdst = $dst$$Register;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6384 Label done;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6385 __ bsfl(Rdst, $src$$Register);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6386 __ jccb(Assembler::notZero, done);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6387 __ movl(Rdst, BitsPerInt);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6388 __ bind(done);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6389 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6390 ins_pipe(ialu_reg);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6391 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6392
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6393 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6394 match(Set dst (CountTrailingZerosL src));
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6395 effect(KILL cr);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6396
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6397 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6398 "jnz done\n\t"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6399 "movl $dst, 64\n"
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6400 "done:" %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6401 ins_encode %{
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6402 Register Rdst = $dst$$Register;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6403 Label done;
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6404 __ bsfq(Rdst, $src$$Register);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6405 __ jccb(Assembler::notZero, done);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6406 __ movl(Rdst, BitsPerLong);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6407 __ bind(done);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6408 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6409 ins_pipe(ialu_reg);
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6410 %}
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6411
93c14e5562c4 6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents: 681
diff changeset
6412
643
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6413 //---------- Population Count Instructions -------------------------------------
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6414
6138
ccaa67adfe5b 7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents: 6084
diff changeset
6415 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
643
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6416 predicate(UsePopCountInstruction);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6417 match(Set dst (PopCountI src));
6138
ccaa67adfe5b 7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents: 6084
diff changeset
6418 effect(KILL cr);
643
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6419
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6420 format %{ "popcnt $dst, $src" %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6421 ins_encode %{
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6422 __ popcntl($dst$$Register, $src$$Register);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6423 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6424 ins_pipe(ialu_reg);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6425 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6426
6138
ccaa67adfe5b 7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents: 6084
diff changeset
6427 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
643
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6428 predicate(UsePopCountInstruction);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6429 match(Set dst (PopCountI (LoadI mem)));
6138
ccaa67adfe5b 7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents: 6084
diff changeset
6430 effect(KILL cr);
643
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6431
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6432 format %{ "popcnt $dst, $mem" %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6433 ins_encode %{
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6434 __ popcntl($dst$$Register, $mem$$Address);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6435 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6436 ins_pipe(ialu_reg);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6437 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6438
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6439 // Note: Long.bitCount(long) returns an int.
6138
ccaa67adfe5b 7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents: 6084
diff changeset
6440 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
643
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6441 predicate(UsePopCountInstruction);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6442 match(Set dst (PopCountL src));
6138
ccaa67adfe5b 7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents: 6084
diff changeset
6443 effect(KILL cr);
643
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6444
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6445 format %{ "popcnt $dst, $src" %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6446 ins_encode %{
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6447 __ popcntq($dst$$Register, $src$$Register);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6448 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6449 ins_pipe(ialu_reg);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6450 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6451
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6452 // Note: Long.bitCount(long) returns an int.
6138
ccaa67adfe5b 7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents: 6084
diff changeset
6453 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
643
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6454 predicate(UsePopCountInstruction);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6455 match(Set dst (PopCountL (LoadL mem)));
6138
ccaa67adfe5b 7063674: Wrong results from basic comparisons after calls to Long.bitCount(long)
twisti
parents: 6084
diff changeset
6456 effect(KILL cr);
643
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6457
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6458 format %{ "popcnt $dst, $mem" %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6459 ins_encode %{
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6460 __ popcntq($dst$$Register, $mem$$Address);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6461 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6462 ins_pipe(ialu_reg);
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6463 %}
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6464
c771b7f43bbf 6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents: 642
diff changeset
6465
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6466 //----------MemBar Instructions-----------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
6467 // Memory barrier flavors
a61af66fc99e Initial load
duke
parents:
diff changeset
6468
a61af66fc99e Initial load
duke
parents:
diff changeset
6469 instruct membar_acquire()
a61af66fc99e Initial load
duke
parents:
diff changeset
6470 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6471 match(MemBarAcquire);
a61af66fc99e Initial load
duke
parents:
diff changeset
6472 ins_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
6473
a61af66fc99e Initial load
duke
parents:
diff changeset
6474 size(0);
671
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
6475 format %{ "MEMBAR-acquire ! (empty encoding)" %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6476 ins_encode();
a61af66fc99e Initial load
duke
parents:
diff changeset
6477 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
6478 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6479
a61af66fc99e Initial load
duke
parents:
diff changeset
6480 instruct membar_acquire_lock()
a61af66fc99e Initial load
duke
parents:
diff changeset
6481 %{
3849
f1c12354c3f7 7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents: 3842
diff changeset
6482 match(MemBarAcquireLock);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6483 ins_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
6484
a61af66fc99e Initial load
duke
parents:
diff changeset
6485 size(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
6486 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6487 ins_encode();
a61af66fc99e Initial load
duke
parents:
diff changeset
6488 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
6489 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6490
a61af66fc99e Initial load
duke
parents:
diff changeset
6491 instruct membar_release()
a61af66fc99e Initial load
duke
parents:
diff changeset
6492 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6493 match(MemBarRelease);
a61af66fc99e Initial load
duke
parents:
diff changeset
6494 ins_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
6495
a61af66fc99e Initial load
duke
parents:
diff changeset
6496 size(0);
671
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
6497 format %{ "MEMBAR-release ! (empty encoding)" %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6498 ins_encode();
a61af66fc99e Initial load
duke
parents:
diff changeset
6499 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
6500 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6501
a61af66fc99e Initial load
duke
parents:
diff changeset
6502 instruct membar_release_lock()
a61af66fc99e Initial load
duke
parents:
diff changeset
6503 %{
3849
f1c12354c3f7 7074017: Introduce MemBarAcquireLock/MemBarReleaseLock nodes for monitor enter/exit code paths
roland
parents: 3842
diff changeset
6504 match(MemBarReleaseLock);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6505 ins_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
6506
a61af66fc99e Initial load
duke
parents:
diff changeset
6507 size(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
6508 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6509 ins_encode();
a61af66fc99e Initial load
duke
parents:
diff changeset
6510 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
6511 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6512
671
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
6513 instruct membar_volatile(rFlagsReg cr) %{
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6514 match(MemBarVolatile);
671
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
6515 effect(KILL cr);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6516 ins_cost(400);
a61af66fc99e Initial load
duke
parents:
diff changeset
6517
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
6518 format %{
671
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
6519 $$template
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
6520 if (os::is_MP()) {
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
6521 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
6522 } else {
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
6523 $$emit$$"MEMBAR-volatile ! (empty encoding)"
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
6524 }
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
6525 %}
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
6526 ins_encode %{
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
6527 __ membar(Assembler::StoreLoad);
d0994e5bebce 6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents: 647
diff changeset
6528 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6529 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
6530 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6531
a61af66fc99e Initial load
duke
parents:
diff changeset
6532 instruct unnecessary_membar_volatile()
a61af66fc99e Initial load
duke
parents:
diff changeset
6533 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6534 match(MemBarVolatile);
a61af66fc99e Initial load
duke
parents:
diff changeset
6535 predicate(Matcher::post_store_load_barrier(n));
a61af66fc99e Initial load
duke
parents:
diff changeset
6536 ins_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
6537
a61af66fc99e Initial load
duke
parents:
diff changeset
6538 size(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
6539 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6540 ins_encode();
a61af66fc99e Initial load
duke
parents:
diff changeset
6541 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
6542 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6543
4763
1dc233a8c7fe 7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents: 4762
diff changeset
6544 instruct membar_storestore() %{
1dc233a8c7fe 7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents: 4762
diff changeset
6545 match(MemBarStoreStore);
1dc233a8c7fe 7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents: 4762
diff changeset
6546 ins_cost(0);
1dc233a8c7fe 7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents: 4762
diff changeset
6547
1dc233a8c7fe 7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents: 4762
diff changeset
6548 size(0);
1dc233a8c7fe 7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents: 4762
diff changeset
6549 format %{ "MEMBAR-storestore (empty encoding)" %}
1dc233a8c7fe 7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents: 4762
diff changeset
6550 ins_encode( );
1dc233a8c7fe 7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents: 4762
diff changeset
6551 ins_pipe(empty);
1dc233a8c7fe 7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents: 4762
diff changeset
6552 %}
1dc233a8c7fe 7121140: Allocation paths require explicit memory synchronization operations for RMO systems
roland
parents: 4762
diff changeset
6553
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6554 //----------Move Instructions--------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
6555
a61af66fc99e Initial load
duke
parents:
diff changeset
6556 instruct castX2P(rRegP dst, rRegL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6557 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6558 match(Set dst (CastX2P src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6559
a61af66fc99e Initial load
duke
parents:
diff changeset
6560 format %{ "movq $dst, $src\t# long->ptr" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6561 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6562 if ($dst$$reg != $src$$reg) {
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6563 __ movptr($dst$$Register, $src$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6564 }
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6565 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6566 ins_pipe(ialu_reg_reg); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6567 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6568
a61af66fc99e Initial load
duke
parents:
diff changeset
6569 instruct castP2X(rRegL dst, rRegP src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6570 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6571 match(Set dst (CastP2X src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6572
a61af66fc99e Initial load
duke
parents:
diff changeset
6573 format %{ "movq $dst, $src\t# ptr -> long" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6574 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6575 if ($dst$$reg != $src$$reg) {
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6576 __ movptr($dst$$Register, $src$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6577 }
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6578 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6579 ins_pipe(ialu_reg_reg); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6580 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6581
6614
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6582 // Convert oop into int for vectors alignment masking
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6583 instruct convP2I(rRegI dst, rRegP src)
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6584 %{
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6585 match(Set dst (ConvL2I (CastP2X src)));
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6586
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6587 format %{ "movl $dst, $src\t# ptr -> int" %}
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6588 ins_encode %{
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6589 __ movl($dst$$Register, $src$$Register);
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6590 %}
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6591 ins_pipe(ialu_reg_reg); // XXX
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6592 %}
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6593
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6594 // Convert compressed oop into int for vectors alignment masking
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6595 // in case of 32bit oops (heap < 4Gb).
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6596 instruct convN2I(rRegI dst, rRegN src)
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6597 %{
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6598 predicate(Universe::narrow_oop_shift() == 0);
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6599 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6600
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6601 format %{ "movl $dst, $src\t# compressed ptr -> int" %}
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6602 ins_encode %{
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6603 __ movl($dst$$Register, $src$$Register);
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6604 %}
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6605 ins_pipe(ialu_reg_reg); // XXX
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
6606 %}
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6607
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6608 // Convert oop pointer into compressed form
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6609 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
221
1e026f8da827 6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents: 182
diff changeset
6610 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6611 match(Set dst (EncodeP src));
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6612 effect(KILL cr);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6613 format %{ "encode_heap_oop $dst,$src" %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6614 ins_encode %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6615 Register s = $src$$Register;
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6616 Register d = $dst$$Register;
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6617 if (s != d) {
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6618 __ movq(d, s);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6619 }
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6620 __ encode_heap_oop(d);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6621 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6622 ins_pipe(ialu_reg_long);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6623 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6624
124
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6625 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
221
1e026f8da827 6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents: 182
diff changeset
6626 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
124
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6627 match(Set dst (EncodeP src));
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6628 effect(KILL cr);
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6629 format %{ "encode_heap_oop_not_null $dst,$src" %}
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6630 ins_encode %{
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6631 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
124
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6632 %}
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6633 ins_pipe(ialu_reg_long);
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6634 %}
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6635
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6636 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
6725
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 6614
diff changeset
6637 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 6614
diff changeset
6638 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6639 match(Set dst (DecodeN src));
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6640 effect(KILL cr);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6641 format %{ "decode_heap_oop $dst,$src" %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6642 ins_encode %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6643 Register s = $src$$Register;
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6644 Register d = $dst$$Register;
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6645 if (s != d) {
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6646 __ movq(d, s);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6647 }
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6648 __ decode_heap_oop(d);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6649 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6650 ins_pipe(ialu_reg_long);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6651 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6652
1571
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
6653 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6725
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 6614
diff changeset
6654 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 6614
diff changeset
6655 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
124
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6656 match(Set dst (DecodeN src));
1571
2d127394260e 6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents: 1567
diff changeset
6657 effect(KILL cr);
124
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6658 format %{ "decode_heap_oop_not_null $dst,$src" %}
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6659 ins_encode %{
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6660 Register s = $src$$Register;
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6661 Register d = $dst$$Register;
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6662 if (s != d) {
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6663 __ decode_heap_oop_not_null(d, s);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6664 } else {
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6665 __ decode_heap_oop_not_null(d);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
6666 }
124
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6667 %}
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6668 ins_pipe(ialu_reg_long);
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6669 %}
b130b98db9cf 6689060: Escape Analysis does not work with Compressed Oops
kvn
parents: 113
diff changeset
6670
6848
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
6671 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
6672 match(Set dst (EncodePKlass src));
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
6673 effect(KILL cr);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
6674 format %{ "encode_heap_oop_not_null $dst,$src" %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
6675 ins_encode %{
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
6676 __ encode_klass_not_null($dst$$Register, $src$$Register);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
6677 %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
6678 ins_pipe(ialu_reg_long);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
6679 %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
6680
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
6681 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
6682 match(Set dst (DecodeNKlass src));
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
6683 effect(KILL cr);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
6684 format %{ "decode_heap_oop_not_null $dst,$src" %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
6685 ins_encode %{
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
6686 Register s = $src$$Register;
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
6687 Register d = $dst$$Register;
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
6688 if (s != d) {
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
6689 __ decode_klass_not_null(d, s);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
6690 } else {
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
6691 __ decode_klass_not_null(d);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
6692 }
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
6693 %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
6694 ins_pipe(ialu_reg_long);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
6695 %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
6696
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
6697
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6698 //----------Conditional Move---------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
6699 // Jump
a61af66fc99e Initial load
duke
parents:
diff changeset
6700 // dummy instruction for generating temp registers
a61af66fc99e Initial load
duke
parents:
diff changeset
6701 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6702 match(Jump (LShiftL switch_val shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
6703 ins_cost(350);
a61af66fc99e Initial load
duke
parents:
diff changeset
6704 predicate(false);
a61af66fc99e Initial load
duke
parents:
diff changeset
6705 effect(TEMP dest);
a61af66fc99e Initial load
duke
parents:
diff changeset
6706
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6707 format %{ "leaq $dest, [$constantaddress]\n\t"
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6708 "jmp [$dest + $switch_val << $shift]\n\t" %}
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6709 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6710 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6711 // to do that and the compiler is using that register as one it can allocate.
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6712 // So we build it all by hand.
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6713 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6714 // ArrayAddress dispatch(table, index);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6715 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6716 __ lea($dest$$Register, $constantaddress);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6717 __ jmp(dispatch);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6718 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6719 ins_pipe(pipe_jmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
6720 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6721
a61af66fc99e Initial load
duke
parents:
diff changeset
6722 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6723 match(Jump (AddL (LShiftL switch_val shift) offset));
a61af66fc99e Initial load
duke
parents:
diff changeset
6724 ins_cost(350);
a61af66fc99e Initial load
duke
parents:
diff changeset
6725 effect(TEMP dest);
a61af66fc99e Initial load
duke
parents:
diff changeset
6726
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6727 format %{ "leaq $dest, [$constantaddress]\n\t"
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6728 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6729 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6730 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6731 // to do that and the compiler is using that register as one it can allocate.
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6732 // So we build it all by hand.
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6733 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6734 // ArrayAddress dispatch(table, index);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6735 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6736 __ lea($dest$$Register, $constantaddress);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6737 __ jmp(dispatch);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6738 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6739 ins_pipe(pipe_jmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
6740 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6741
a61af66fc99e Initial load
duke
parents:
diff changeset
6742 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6743 match(Jump switch_val);
a61af66fc99e Initial load
duke
parents:
diff changeset
6744 ins_cost(350);
a61af66fc99e Initial load
duke
parents:
diff changeset
6745 effect(TEMP dest);
a61af66fc99e Initial load
duke
parents:
diff changeset
6746
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6747 format %{ "leaq $dest, [$constantaddress]\n\t"
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6748 "jmp [$dest + $switch_val]\n\t" %}
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6749 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6750 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6751 // to do that and the compiler is using that register as one it can allocate.
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6752 // So we build it all by hand.
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6753 // Address index(noreg, switch_reg, Address::times_1);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6754 // ArrayAddress dispatch(table, index);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6755 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6756 __ lea($dest$$Register, $constantaddress);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6757 __ jmp(dispatch);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
6758 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6759 ins_pipe(pipe_jmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
6760 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6761
a61af66fc99e Initial load
duke
parents:
diff changeset
6762 // Conditional move
a61af66fc99e Initial load
duke
parents:
diff changeset
6763 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
a61af66fc99e Initial load
duke
parents:
diff changeset
6764 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6765 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6766
a61af66fc99e Initial load
duke
parents:
diff changeset
6767 ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6768 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6769 opcode(0x0F, 0x40);
a61af66fc99e Initial load
duke
parents:
diff changeset
6770 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6771 ins_pipe(pipe_cmov_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6772 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6773
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6774 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6775 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6776
a61af66fc99e Initial load
duke
parents:
diff changeset
6777 ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6778 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6779 opcode(0x0F, 0x40);
a61af66fc99e Initial load
duke
parents:
diff changeset
6780 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6781 ins_pipe(pipe_cmov_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
6782 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6783
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6784 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6785 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6786 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6787 expand %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6788 cmovI_regU(cop, cr, dst, src);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6789 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6790 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6791
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6792 // Conditional move
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6793 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6794 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
a61af66fc99e Initial load
duke
parents:
diff changeset
6795
a61af66fc99e Initial load
duke
parents:
diff changeset
6796 ins_cost(250); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6797 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6798 opcode(0x0F, 0x40);
a61af66fc99e Initial load
duke
parents:
diff changeset
6799 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6800 ins_pipe(pipe_cmov_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
6801 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6802
a61af66fc99e Initial load
duke
parents:
diff changeset
6803 // Conditional move
a61af66fc99e Initial load
duke
parents:
diff changeset
6804 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6805 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6806 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
a61af66fc99e Initial load
duke
parents:
diff changeset
6807
a61af66fc99e Initial load
duke
parents:
diff changeset
6808 ins_cost(250); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6809 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6810 opcode(0x0F, 0x40);
a61af66fc99e Initial load
duke
parents:
diff changeset
6811 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6812 ins_pipe(pipe_cmov_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
6813 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6814
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6815 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6816 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6817 ins_cost(250);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6818 expand %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6819 cmovI_memU(cop, cr, dst, src);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6820 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6821 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6822
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6823 // Conditional move
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6824 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6825 %{
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6826 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6827
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6828 ins_cost(200); // XXX
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6829 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6830 opcode(0x0F, 0x40);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6831 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6832 ins_pipe(pipe_cmov_reg);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6833 %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6834
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6835 // Conditional move
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6836 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6837 %{
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6838 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6839
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6840 ins_cost(200); // XXX
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6841 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6842 opcode(0x0F, 0x40);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6843 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6844 ins_pipe(pipe_cmov_reg);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6845 %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6846
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6847 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6848 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6849 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6850 expand %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6851 cmovN_regU(cop, cr, dst, src);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6852 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6853 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6854
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
6855 // Conditional move
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6856 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
a61af66fc99e Initial load
duke
parents:
diff changeset
6857 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6858 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6859
a61af66fc99e Initial load
duke
parents:
diff changeset
6860 ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6861 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6862 opcode(0x0F, 0x40);
a61af66fc99e Initial load
duke
parents:
diff changeset
6863 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6864 ins_pipe(pipe_cmov_reg); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6865 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6866
a61af66fc99e Initial load
duke
parents:
diff changeset
6867 // Conditional move
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6868 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6869 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6870 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6871
a61af66fc99e Initial load
duke
parents:
diff changeset
6872 ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6873 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6874 opcode(0x0F, 0x40);
a61af66fc99e Initial load
duke
parents:
diff changeset
6875 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6876 ins_pipe(pipe_cmov_reg); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6877 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6878
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6879 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6880 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6881 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6882 expand %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6883 cmovP_regU(cop, cr, dst, src);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6884 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6885 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6886
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6887 // DISABLED: Requires the ADLC to emit a bottom_type call that
a61af66fc99e Initial load
duke
parents:
diff changeset
6888 // correctly meets the two pointer arguments; one is an incoming
a61af66fc99e Initial load
duke
parents:
diff changeset
6889 // register but the other is a memory operand. ALSO appears to
a61af66fc99e Initial load
duke
parents:
diff changeset
6890 // be buggy with implicit null checks.
a61af66fc99e Initial load
duke
parents:
diff changeset
6891 //
a61af66fc99e Initial load
duke
parents:
diff changeset
6892 //// Conditional move
a61af66fc99e Initial load
duke
parents:
diff changeset
6893 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6894 //%{
a61af66fc99e Initial load
duke
parents:
diff changeset
6895 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
a61af66fc99e Initial load
duke
parents:
diff changeset
6896 // ins_cost(250);
a61af66fc99e Initial load
duke
parents:
diff changeset
6897 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6898 // opcode(0x0F,0x40);
a61af66fc99e Initial load
duke
parents:
diff changeset
6899 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6900 // ins_pipe( pipe_cmov_mem );
a61af66fc99e Initial load
duke
parents:
diff changeset
6901 //%}
a61af66fc99e Initial load
duke
parents:
diff changeset
6902 //
a61af66fc99e Initial load
duke
parents:
diff changeset
6903 //// Conditional move
a61af66fc99e Initial load
duke
parents:
diff changeset
6904 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6905 //%{
a61af66fc99e Initial load
duke
parents:
diff changeset
6906 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
a61af66fc99e Initial load
duke
parents:
diff changeset
6907 // ins_cost(250);
a61af66fc99e Initial load
duke
parents:
diff changeset
6908 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6909 // opcode(0x0F,0x40);
a61af66fc99e Initial load
duke
parents:
diff changeset
6910 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
6911 // ins_pipe( pipe_cmov_mem );
a61af66fc99e Initial load
duke
parents:
diff changeset
6912 //%}
a61af66fc99e Initial load
duke
parents:
diff changeset
6913
a61af66fc99e Initial load
duke
parents:
diff changeset
6914 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6915 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6916 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6917
a61af66fc99e Initial load
duke
parents:
diff changeset
6918 ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6919 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6920 opcode(0x0F, 0x40);
a61af66fc99e Initial load
duke
parents:
diff changeset
6921 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6922 ins_pipe(pipe_cmov_reg); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6923 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6924
a61af66fc99e Initial load
duke
parents:
diff changeset
6925 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6926 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6927 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
a61af66fc99e Initial load
duke
parents:
diff changeset
6928
a61af66fc99e Initial load
duke
parents:
diff changeset
6929 ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6930 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6931 opcode(0x0F, 0x40);
a61af66fc99e Initial load
duke
parents:
diff changeset
6932 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6933 ins_pipe(pipe_cmov_mem); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6934 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6935
a61af66fc99e Initial load
duke
parents:
diff changeset
6936 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6937 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6938 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6939
a61af66fc99e Initial load
duke
parents:
diff changeset
6940 ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6941 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6942 opcode(0x0F, 0x40);
a61af66fc99e Initial load
duke
parents:
diff changeset
6943 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6944 ins_pipe(pipe_cmov_reg); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6945 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6946
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6947 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6948 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6949 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6950 expand %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6951 cmovL_regU(cop, cr, dst, src);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6952 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6953 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6954
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6955 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6956 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6957 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
a61af66fc99e Initial load
duke
parents:
diff changeset
6958
a61af66fc99e Initial load
duke
parents:
diff changeset
6959 ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6960 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6961 opcode(0x0F, 0x40);
a61af66fc99e Initial load
duke
parents:
diff changeset
6962 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
6963 ins_pipe(pipe_cmov_mem); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6964 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6965
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6966 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6967 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6968 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6969 expand %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6970 cmovL_memU(cop, cr, dst, src);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6971 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6972 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
6973
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6974 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6975 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6976 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
6977
a61af66fc99e Initial load
duke
parents:
diff changeset
6978 ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6979 format %{ "jn$cop skip\t# signed cmove float\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
6980 "movss $dst, $src\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
6981 "skip:" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6982 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6983 Label Lskip;
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6984 // Invert sense of branch from sense of CMOV
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6985 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6986 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6987 __ bind(Lskip);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
6988 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
6989 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
6990 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
6991
a61af66fc99e Initial load
duke
parents:
diff changeset
6992 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
6993 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
6994 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
a61af66fc99e Initial load
duke
parents:
diff changeset
6995
a61af66fc99e Initial load
duke
parents:
diff changeset
6996 // ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
6997 // format %{ "jn$cop skip\t# signed cmove float\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
6998 // "movss $dst, $src\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
6999 // "skip:" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7000 // ins_encode(enc_cmovf_mem_branch(cop, dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7001 // ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
7002 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7003
a61af66fc99e Initial load
duke
parents:
diff changeset
7004 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
a61af66fc99e Initial load
duke
parents:
diff changeset
7005 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7006 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7007
a61af66fc99e Initial load
duke
parents:
diff changeset
7008 ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7009 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7010 "movss $dst, $src\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
7011 "skip:" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
7012 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
7013 Label Lskip;
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
7014 // Invert sense of branch from sense of CMOV
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
7015 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
7016 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
7017 __ bind(Lskip);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
7018 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7019 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
7020 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7021
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7022 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7023 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7024 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7025 expand %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7026 cmovF_regU(cop, cr, dst, src);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7027 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7028 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7029
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7030 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
7031 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7032 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7033
a61af66fc99e Initial load
duke
parents:
diff changeset
7034 ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7035 format %{ "jn$cop skip\t# signed cmove double\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7036 "movsd $dst, $src\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
7037 "skip:" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
7038 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
7039 Label Lskip;
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
7040 // Invert sense of branch from sense of CMOV
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
7041 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
7042 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
7043 __ bind(Lskip);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
7044 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7045 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
7046 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7047
a61af66fc99e Initial load
duke
parents:
diff changeset
7048 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
7049 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7050 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7051
a61af66fc99e Initial load
duke
parents:
diff changeset
7052 ins_cost(200); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7053 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7054 "movsd $dst, $src\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
7055 "skip:" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
7056 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
7057 Label Lskip;
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
7058 // Invert sense of branch from sense of CMOV
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
7059 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
7060 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
7061 __ bind(Lskip);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
7062 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7063 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
7064 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7065
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7066 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7067 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7068 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7069 expand %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7070 cmovD_regU(cop, cr, dst, src);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7071 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7072 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
7073
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7074 //----------Arithmetic Instructions--------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
7075 //----------Addition Instructions----------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
7076
a61af66fc99e Initial load
duke
parents:
diff changeset
7077 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7078 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7079 match(Set dst (AddI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7080 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7081
a61af66fc99e Initial load
duke
parents:
diff changeset
7082 format %{ "addl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7083 opcode(0x03);
a61af66fc99e Initial load
duke
parents:
diff changeset
7084 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7085 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7086 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7087
a61af66fc99e Initial load
duke
parents:
diff changeset
7088 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7089 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7090 match(Set dst (AddI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7091 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7092
a61af66fc99e Initial load
duke
parents:
diff changeset
7093 format %{ "addl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7094 opcode(0x81, 0x00); /* /0 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
7095 ins_encode(OpcSErm(dst, src), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7096 ins_pipe( ialu_reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
7097 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7098
a61af66fc99e Initial load
duke
parents:
diff changeset
7099 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7100 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7101 match(Set dst (AddI dst (LoadI src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7102 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7103
a61af66fc99e Initial load
duke
parents:
diff changeset
7104 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7105 format %{ "addl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7106 opcode(0x03);
a61af66fc99e Initial load
duke
parents:
diff changeset
7107 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7108 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
7109 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7110
a61af66fc99e Initial load
duke
parents:
diff changeset
7111 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7112 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7113 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7114 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7115
a61af66fc99e Initial load
duke
parents:
diff changeset
7116 ins_cost(150); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7117 format %{ "addl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7118 opcode(0x01); /* Opcode 01 /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
7119 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7120 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7121 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7122
a61af66fc99e Initial load
duke
parents:
diff changeset
7123 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7124 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7125 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7126 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7127
a61af66fc99e Initial load
duke
parents:
diff changeset
7128 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7129 format %{ "addl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7130 opcode(0x81); /* Opcode 81 /0 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
7131 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7132 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7133 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7134
a61af66fc99e Initial load
duke
parents:
diff changeset
7135 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7136 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7137 predicate(UseIncDec);
a61af66fc99e Initial load
duke
parents:
diff changeset
7138 match(Set dst (AddI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7139 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7140
a61af66fc99e Initial load
duke
parents:
diff changeset
7141 format %{ "incl $dst\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7142 opcode(0xFF, 0x00); // FF /0
a61af66fc99e Initial load
duke
parents:
diff changeset
7143 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7144 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7145 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7146
a61af66fc99e Initial load
duke
parents:
diff changeset
7147 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7148 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7149 predicate(UseIncDec);
a61af66fc99e Initial load
duke
parents:
diff changeset
7150 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7151 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7152
a61af66fc99e Initial load
duke
parents:
diff changeset
7153 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7154 format %{ "incl $dst\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7155 opcode(0xFF); /* Opcode FF /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
7156 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7157 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7158 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7159
a61af66fc99e Initial load
duke
parents:
diff changeset
7160 // XXX why does that use AddI
a61af66fc99e Initial load
duke
parents:
diff changeset
7161 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7162 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7163 predicate(UseIncDec);
a61af66fc99e Initial load
duke
parents:
diff changeset
7164 match(Set dst (AddI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7165 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7166
a61af66fc99e Initial load
duke
parents:
diff changeset
7167 format %{ "decl $dst\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7168 opcode(0xFF, 0x01); // FF /1
a61af66fc99e Initial load
duke
parents:
diff changeset
7169 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7170 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7171 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7172
a61af66fc99e Initial load
duke
parents:
diff changeset
7173 // XXX why does that use AddI
a61af66fc99e Initial load
duke
parents:
diff changeset
7174 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7175 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7176 predicate(UseIncDec);
a61af66fc99e Initial load
duke
parents:
diff changeset
7177 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7178 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7179
a61af66fc99e Initial load
duke
parents:
diff changeset
7180 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7181 format %{ "decl $dst\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7182 opcode(0xFF); /* Opcode FF /1 */
a61af66fc99e Initial load
duke
parents:
diff changeset
7183 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7184 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7185 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7186
a61af66fc99e Initial load
duke
parents:
diff changeset
7187 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
a61af66fc99e Initial load
duke
parents:
diff changeset
7188 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7189 match(Set dst (AddI src0 src1));
a61af66fc99e Initial load
duke
parents:
diff changeset
7190
a61af66fc99e Initial load
duke
parents:
diff changeset
7191 ins_cost(110);
a61af66fc99e Initial load
duke
parents:
diff changeset
7192 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7193 opcode(0x8D); /* 0x8D /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
7194 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7195 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7196 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7197
a61af66fc99e Initial load
duke
parents:
diff changeset
7198 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7199 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7200 match(Set dst (AddL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7201 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7202
a61af66fc99e Initial load
duke
parents:
diff changeset
7203 format %{ "addq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7204 opcode(0x03);
a61af66fc99e Initial load
duke
parents:
diff changeset
7205 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7206 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7207 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7208
a61af66fc99e Initial load
duke
parents:
diff changeset
7209 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7210 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7211 match(Set dst (AddL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7212 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7213
a61af66fc99e Initial load
duke
parents:
diff changeset
7214 format %{ "addq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7215 opcode(0x81, 0x00); /* /0 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
7216 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7217 ins_pipe( ialu_reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
7218 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7219
a61af66fc99e Initial load
duke
parents:
diff changeset
7220 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7221 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7222 match(Set dst (AddL dst (LoadL src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7223 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7224
a61af66fc99e Initial load
duke
parents:
diff changeset
7225 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7226 format %{ "addq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7227 opcode(0x03);
a61af66fc99e Initial load
duke
parents:
diff changeset
7228 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7229 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
7230 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7231
a61af66fc99e Initial load
duke
parents:
diff changeset
7232 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7233 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7234 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7235 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7236
a61af66fc99e Initial load
duke
parents:
diff changeset
7237 ins_cost(150); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7238 format %{ "addq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7239 opcode(0x01); /* Opcode 01 /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
7240 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7241 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7242 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7243
a61af66fc99e Initial load
duke
parents:
diff changeset
7244 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7245 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7246 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7247 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7248
a61af66fc99e Initial load
duke
parents:
diff changeset
7249 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7250 format %{ "addq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7251 opcode(0x81); /* Opcode 81 /0 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
7252 ins_encode(REX_mem_wide(dst),
a61af66fc99e Initial load
duke
parents:
diff changeset
7253 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7254 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7255 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7256
a61af66fc99e Initial load
duke
parents:
diff changeset
7257 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7258 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7259 predicate(UseIncDec);
a61af66fc99e Initial load
duke
parents:
diff changeset
7260 match(Set dst (AddL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7261 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7262
a61af66fc99e Initial load
duke
parents:
diff changeset
7263 format %{ "incq $dst\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7264 opcode(0xFF, 0x00); // FF /0
a61af66fc99e Initial load
duke
parents:
diff changeset
7265 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7266 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7267 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7268
a61af66fc99e Initial load
duke
parents:
diff changeset
7269 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7270 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7271 predicate(UseIncDec);
a61af66fc99e Initial load
duke
parents:
diff changeset
7272 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7273 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7274
a61af66fc99e Initial load
duke
parents:
diff changeset
7275 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7276 format %{ "incq $dst\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7277 opcode(0xFF); /* Opcode FF /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
7278 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7279 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7280 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7281
a61af66fc99e Initial load
duke
parents:
diff changeset
7282 // XXX why does that use AddL
a61af66fc99e Initial load
duke
parents:
diff changeset
7283 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7284 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7285 predicate(UseIncDec);
a61af66fc99e Initial load
duke
parents:
diff changeset
7286 match(Set dst (AddL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7287 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7288
a61af66fc99e Initial load
duke
parents:
diff changeset
7289 format %{ "decq $dst\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7290 opcode(0xFF, 0x01); // FF /1
a61af66fc99e Initial load
duke
parents:
diff changeset
7291 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7292 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7293 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7294
a61af66fc99e Initial load
duke
parents:
diff changeset
7295 // XXX why does that use AddL
a61af66fc99e Initial load
duke
parents:
diff changeset
7296 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7297 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7298 predicate(UseIncDec);
a61af66fc99e Initial load
duke
parents:
diff changeset
7299 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7300 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7301
a61af66fc99e Initial load
duke
parents:
diff changeset
7302 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7303 format %{ "decq $dst\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7304 opcode(0xFF); /* Opcode FF /1 */
a61af66fc99e Initial load
duke
parents:
diff changeset
7305 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7306 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7307 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7308
a61af66fc99e Initial load
duke
parents:
diff changeset
7309 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
a61af66fc99e Initial load
duke
parents:
diff changeset
7310 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7311 match(Set dst (AddL src0 src1));
a61af66fc99e Initial load
duke
parents:
diff changeset
7312
a61af66fc99e Initial load
duke
parents:
diff changeset
7313 ins_cost(110);
a61af66fc99e Initial load
duke
parents:
diff changeset
7314 format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7315 opcode(0x8D); /* 0x8D /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
7316 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7317 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7318 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7319
a61af66fc99e Initial load
duke
parents:
diff changeset
7320 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7321 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7322 match(Set dst (AddP dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7323 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7324
a61af66fc99e Initial load
duke
parents:
diff changeset
7325 format %{ "addq $dst, $src\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7326 opcode(0x03);
a61af66fc99e Initial load
duke
parents:
diff changeset
7327 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7328 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7329 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7330
a61af66fc99e Initial load
duke
parents:
diff changeset
7331 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7332 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7333 match(Set dst (AddP dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7334 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7335
a61af66fc99e Initial load
duke
parents:
diff changeset
7336 format %{ "addq $dst, $src\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7337 opcode(0x81, 0x00); /* /0 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
7338 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7339 ins_pipe( ialu_reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
7340 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7341
a61af66fc99e Initial load
duke
parents:
diff changeset
7342 // XXX addP mem ops ????
a61af66fc99e Initial load
duke
parents:
diff changeset
7343
a61af66fc99e Initial load
duke
parents:
diff changeset
7344 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
a61af66fc99e Initial load
duke
parents:
diff changeset
7345 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7346 match(Set dst (AddP src0 src1));
a61af66fc99e Initial load
duke
parents:
diff changeset
7347
a61af66fc99e Initial load
duke
parents:
diff changeset
7348 ins_cost(110);
a61af66fc99e Initial load
duke
parents:
diff changeset
7349 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7350 opcode(0x8D); /* 0x8D /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
7351 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7352 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7353 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7354
a61af66fc99e Initial load
duke
parents:
diff changeset
7355 instruct checkCastPP(rRegP dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
7356 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7357 match(Set dst (CheckCastPP dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7358
a61af66fc99e Initial load
duke
parents:
diff changeset
7359 size(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7360 format %{ "# checkcastPP of $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7361 ins_encode(/* empty encoding */);
a61af66fc99e Initial load
duke
parents:
diff changeset
7362 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
7363 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7364
a61af66fc99e Initial load
duke
parents:
diff changeset
7365 instruct castPP(rRegP dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
7366 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7367 match(Set dst (CastPP dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7368
a61af66fc99e Initial load
duke
parents:
diff changeset
7369 size(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7370 format %{ "# castPP of $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7371 ins_encode(/* empty encoding */);
a61af66fc99e Initial load
duke
parents:
diff changeset
7372 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
7373 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7374
a61af66fc99e Initial load
duke
parents:
diff changeset
7375 instruct castII(rRegI dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
7376 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7377 match(Set dst (CastII dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7378
a61af66fc99e Initial load
duke
parents:
diff changeset
7379 size(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7380 format %{ "# castII of $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7381 ins_encode(/* empty encoding */);
a61af66fc99e Initial load
duke
parents:
diff changeset
7382 ins_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7383 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
7384 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7385
a61af66fc99e Initial load
duke
parents:
diff changeset
7386 // LoadP-locked same as a regular LoadP when used with compare-swap
a61af66fc99e Initial load
duke
parents:
diff changeset
7387 instruct loadPLocked(rRegP dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
7388 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7389 match(Set dst (LoadPLocked mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
7390
a61af66fc99e Initial load
duke
parents:
diff changeset
7391 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7392 format %{ "movq $dst, $mem\t# ptr locked" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7393 opcode(0x8B);
a61af66fc99e Initial load
duke
parents:
diff changeset
7394 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
7395 ins_pipe(ialu_reg_mem); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7396 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7397
a61af66fc99e Initial load
duke
parents:
diff changeset
7398 // Conditional-store of the updated heap-top.
a61af66fc99e Initial load
duke
parents:
diff changeset
7399 // Used during allocation of the shared heap.
a61af66fc99e Initial load
duke
parents:
diff changeset
7400 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
a61af66fc99e Initial load
duke
parents:
diff changeset
7401
a61af66fc99e Initial load
duke
parents:
diff changeset
7402 instruct storePConditional(memory heap_top_ptr,
a61af66fc99e Initial load
duke
parents:
diff changeset
7403 rax_RegP oldval, rRegP newval,
a61af66fc99e Initial load
duke
parents:
diff changeset
7404 rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7405 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7406 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
7407
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7408 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
a61af66fc99e Initial load
duke
parents:
diff changeset
7409 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7410 opcode(0x0F, 0xB1);
a61af66fc99e Initial load
duke
parents:
diff changeset
7411 ins_encode(lock_prefix,
a61af66fc99e Initial load
duke
parents:
diff changeset
7412 REX_reg_mem_wide(newval, heap_top_ptr),
a61af66fc99e Initial load
duke
parents:
diff changeset
7413 OpcP, OpcS,
a61af66fc99e Initial load
duke
parents:
diff changeset
7414 reg_mem(newval, heap_top_ptr));
a61af66fc99e Initial load
duke
parents:
diff changeset
7415 ins_pipe(pipe_cmpxchg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7416 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7417
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7418 // Conditional-store of an int value.
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7419 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7420 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7421 %{
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7422 match(Set cr (StoreIConditional mem (Binary oldval newval)));
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7423 effect(KILL oldval);
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7424
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7425 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7426 opcode(0x0F, 0xB1);
a61af66fc99e Initial load
duke
parents:
diff changeset
7427 ins_encode(lock_prefix,
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7428 REX_reg_mem(newval, mem),
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7429 OpcP, OpcS,
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7430 reg_mem(newval, mem));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7431 ins_pipe(pipe_cmpxchg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7432 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7433
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7434 // Conditional-store of a long value.
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7435 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7436 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7437 %{
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7438 match(Set cr (StoreLConditional mem (Binary oldval newval)));
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7439 effect(KILL oldval);
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7440
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7441 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7442 opcode(0x0F, 0xB1);
a61af66fc99e Initial load
duke
parents:
diff changeset
7443 ins_encode(lock_prefix,
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7444 REX_reg_mem_wide(newval, mem),
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7445 OpcP, OpcS,
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7446 reg_mem(newval, mem));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7447 ins_pipe(pipe_cmpxchg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7448 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7449
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7450
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
7451 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7452 instruct compareAndSwapP(rRegI res,
a61af66fc99e Initial load
duke
parents:
diff changeset
7453 memory mem_ptr,
a61af66fc99e Initial load
duke
parents:
diff changeset
7454 rax_RegP oldval, rRegP newval,
a61af66fc99e Initial load
duke
parents:
diff changeset
7455 rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7456 %{
6795
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7457 predicate(VM_Version::supports_cx8());
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7458 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7459 effect(KILL cr, KILL oldval);
a61af66fc99e Initial load
duke
parents:
diff changeset
7460
a61af66fc99e Initial load
duke
parents:
diff changeset
7461 format %{ "cmpxchgq $mem_ptr,$newval\t# "
a61af66fc99e Initial load
duke
parents:
diff changeset
7462 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7463 "sete $res\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7464 "movzbl $res, $res" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7465 opcode(0x0F, 0xB1);
a61af66fc99e Initial load
duke
parents:
diff changeset
7466 ins_encode(lock_prefix,
a61af66fc99e Initial load
duke
parents:
diff changeset
7467 REX_reg_mem_wide(newval, mem_ptr),
a61af66fc99e Initial load
duke
parents:
diff changeset
7468 OpcP, OpcS,
a61af66fc99e Initial load
duke
parents:
diff changeset
7469 reg_mem(newval, mem_ptr),
a61af66fc99e Initial load
duke
parents:
diff changeset
7470 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
a61af66fc99e Initial load
duke
parents:
diff changeset
7471 REX_reg_breg(res, res), // movzbl
a61af66fc99e Initial load
duke
parents:
diff changeset
7472 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
a61af66fc99e Initial load
duke
parents:
diff changeset
7473 ins_pipe( pipe_cmpxchg );
a61af66fc99e Initial load
duke
parents:
diff changeset
7474 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7475
a61af66fc99e Initial load
duke
parents:
diff changeset
7476 instruct compareAndSwapL(rRegI res,
a61af66fc99e Initial load
duke
parents:
diff changeset
7477 memory mem_ptr,
a61af66fc99e Initial load
duke
parents:
diff changeset
7478 rax_RegL oldval, rRegL newval,
a61af66fc99e Initial load
duke
parents:
diff changeset
7479 rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7480 %{
6795
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7481 predicate(VM_Version::supports_cx8());
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7482 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7483 effect(KILL cr, KILL oldval);
a61af66fc99e Initial load
duke
parents:
diff changeset
7484
a61af66fc99e Initial load
duke
parents:
diff changeset
7485 format %{ "cmpxchgq $mem_ptr,$newval\t# "
a61af66fc99e Initial load
duke
parents:
diff changeset
7486 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7487 "sete $res\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7488 "movzbl $res, $res" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7489 opcode(0x0F, 0xB1);
a61af66fc99e Initial load
duke
parents:
diff changeset
7490 ins_encode(lock_prefix,
a61af66fc99e Initial load
duke
parents:
diff changeset
7491 REX_reg_mem_wide(newval, mem_ptr),
a61af66fc99e Initial load
duke
parents:
diff changeset
7492 OpcP, OpcS,
a61af66fc99e Initial load
duke
parents:
diff changeset
7493 reg_mem(newval, mem_ptr),
a61af66fc99e Initial load
duke
parents:
diff changeset
7494 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
a61af66fc99e Initial load
duke
parents:
diff changeset
7495 REX_reg_breg(res, res), // movzbl
a61af66fc99e Initial load
duke
parents:
diff changeset
7496 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
a61af66fc99e Initial load
duke
parents:
diff changeset
7497 ins_pipe( pipe_cmpxchg );
a61af66fc99e Initial load
duke
parents:
diff changeset
7498 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7499
a61af66fc99e Initial load
duke
parents:
diff changeset
7500 instruct compareAndSwapI(rRegI res,
a61af66fc99e Initial load
duke
parents:
diff changeset
7501 memory mem_ptr,
a61af66fc99e Initial load
duke
parents:
diff changeset
7502 rax_RegI oldval, rRegI newval,
a61af66fc99e Initial load
duke
parents:
diff changeset
7503 rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7504 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7505 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7506 effect(KILL cr, KILL oldval);
a61af66fc99e Initial load
duke
parents:
diff changeset
7507
a61af66fc99e Initial load
duke
parents:
diff changeset
7508 format %{ "cmpxchgl $mem_ptr,$newval\t# "
a61af66fc99e Initial load
duke
parents:
diff changeset
7509 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7510 "sete $res\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7511 "movzbl $res, $res" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7512 opcode(0x0F, 0xB1);
a61af66fc99e Initial load
duke
parents:
diff changeset
7513 ins_encode(lock_prefix,
a61af66fc99e Initial load
duke
parents:
diff changeset
7514 REX_reg_mem(newval, mem_ptr),
a61af66fc99e Initial load
duke
parents:
diff changeset
7515 OpcP, OpcS,
a61af66fc99e Initial load
duke
parents:
diff changeset
7516 reg_mem(newval, mem_ptr),
a61af66fc99e Initial load
duke
parents:
diff changeset
7517 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
a61af66fc99e Initial load
duke
parents:
diff changeset
7518 REX_reg_breg(res, res), // movzbl
a61af66fc99e Initial load
duke
parents:
diff changeset
7519 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
a61af66fc99e Initial load
duke
parents:
diff changeset
7520 ins_pipe( pipe_cmpxchg );
a61af66fc99e Initial load
duke
parents:
diff changeset
7521 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7522
a61af66fc99e Initial load
duke
parents:
diff changeset
7523
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7524 instruct compareAndSwapN(rRegI res,
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7525 memory mem_ptr,
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7526 rax_RegN oldval, rRegN newval,
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7527 rFlagsReg cr) %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7528 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7529 effect(KILL cr, KILL oldval);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7530
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7531 format %{ "cmpxchgl $mem_ptr,$newval\t# "
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7532 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7533 "sete $res\n\t"
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7534 "movzbl $res, $res" %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7535 opcode(0x0F, 0xB1);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7536 ins_encode(lock_prefix,
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7537 REX_reg_mem(newval, mem_ptr),
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7538 OpcP, OpcS,
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7539 reg_mem(newval, mem_ptr),
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7540 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7541 REX_reg_breg(res, res), // movzbl
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7542 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7543 ins_pipe( pipe_cmpxchg );
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7544 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
7545
6795
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7546 instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7547 predicate(n->as_LoadStore()->result_not_used());
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7548 match(Set dummy (GetAndAddI mem add));
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7549 effect(KILL cr);
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7550 format %{ "ADDL [$mem],$add" %}
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7551 ins_encode %{
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7552 if (os::is_MP()) { __ lock(); }
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7553 __ addl($mem$$Address, $add$$constant);
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7554 %}
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7555 ins_pipe( pipe_cmpxchg );
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7556 %}
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7557
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7558 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7559 match(Set newval (GetAndAddI mem newval));
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7560 effect(KILL cr);
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7561 format %{ "XADDL [$mem],$newval" %}
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7562 ins_encode %{
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7563 if (os::is_MP()) { __ lock(); }
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7564 __ xaddl($mem$$Address, $newval$$Register);
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7565 %}
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7566 ins_pipe( pipe_cmpxchg );
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7567 %}
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7568
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7569 instruct xaddL_no_res( memory mem, Universe dummy, immL add, rFlagsReg cr) %{
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7570 predicate(n->as_LoadStore()->result_not_used());
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7571 match(Set dummy (GetAndAddL mem add));
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7572 effect(KILL cr);
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7573 format %{ "ADDQ [$mem],$add" %}
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7574 ins_encode %{
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7575 if (os::is_MP()) { __ lock(); }
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7576 __ addq($mem$$Address, $add$$constant);
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7577 %}
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7578 ins_pipe( pipe_cmpxchg );
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7579 %}
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7580
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7581 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7582 match(Set newval (GetAndAddL mem newval));
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7583 effect(KILL cr);
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7584 format %{ "XADDQ [$mem],$newval" %}
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7585 ins_encode %{
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7586 if (os::is_MP()) { __ lock(); }
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7587 __ xaddq($mem$$Address, $newval$$Register);
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7588 %}
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7589 ins_pipe( pipe_cmpxchg );
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7590 %}
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7591
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7592 instruct xchgI( memory mem, rRegI newval) %{
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7593 match(Set newval (GetAndSetI mem newval));
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7594 format %{ "XCHGL $newval,[$mem]" %}
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7595 ins_encode %{
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7596 __ xchgl($newval$$Register, $mem$$Address);
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7597 %}
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7598 ins_pipe( pipe_cmpxchg );
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7599 %}
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7600
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7601 instruct xchgL( memory mem, rRegL newval) %{
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7602 match(Set newval (GetAndSetL mem newval));
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7603 format %{ "XCHGL $newval,[$mem]" %}
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7604 ins_encode %{
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7605 __ xchgq($newval$$Register, $mem$$Address);
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7606 %}
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7607 ins_pipe( pipe_cmpxchg );
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7608 %}
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7609
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7610 instruct xchgP( memory mem, rRegP newval) %{
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7611 match(Set newval (GetAndSetP mem newval));
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7612 format %{ "XCHGQ $newval,[$mem]" %}
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7613 ins_encode %{
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7614 __ xchgq($newval$$Register, $mem$$Address);
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7615 %}
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7616 ins_pipe( pipe_cmpxchg );
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7617 %}
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7618
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7619 instruct xchgN( memory mem, rRegN newval) %{
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7620 match(Set newval (GetAndSetN mem newval));
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7621 format %{ "XCHGL $newval,$mem]" %}
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7622 ins_encode %{
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7623 __ xchgl($newval$$Register, $mem$$Address);
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7624 %}
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7625 ins_pipe( pipe_cmpxchg );
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7626 %}
7eca5de9e0b6 7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents: 6725
diff changeset
7627
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7628 //----------Subtraction Instructions-------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
7629
a61af66fc99e Initial load
duke
parents:
diff changeset
7630 // Integer Subtraction Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
7631 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7632 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7633 match(Set dst (SubI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7634 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7635
a61af66fc99e Initial load
duke
parents:
diff changeset
7636 format %{ "subl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7637 opcode(0x2B);
a61af66fc99e Initial load
duke
parents:
diff changeset
7638 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7639 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7640 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7641
a61af66fc99e Initial load
duke
parents:
diff changeset
7642 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7643 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7644 match(Set dst (SubI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7645 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7646
a61af66fc99e Initial load
duke
parents:
diff changeset
7647 format %{ "subl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7648 opcode(0x81, 0x05); /* Opcode 81 /5 */
a61af66fc99e Initial load
duke
parents:
diff changeset
7649 ins_encode(OpcSErm(dst, src), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7650 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7651 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7652
a61af66fc99e Initial load
duke
parents:
diff changeset
7653 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7654 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7655 match(Set dst (SubI dst (LoadI src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7656 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7657
a61af66fc99e Initial load
duke
parents:
diff changeset
7658 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
7659 format %{ "subl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7660 opcode(0x2B);
a61af66fc99e Initial load
duke
parents:
diff changeset
7661 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7662 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
7663 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7664
a61af66fc99e Initial load
duke
parents:
diff changeset
7665 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7666 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7667 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7668 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7669
a61af66fc99e Initial load
duke
parents:
diff changeset
7670 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
7671 format %{ "subl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7672 opcode(0x29); /* Opcode 29 /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
7673 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7674 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7675 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7676
a61af66fc99e Initial load
duke
parents:
diff changeset
7677 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7678 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7679 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7680 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7681
a61af66fc99e Initial load
duke
parents:
diff changeset
7682 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7683 format %{ "subl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7684 opcode(0x81); /* Opcode 81 /5 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
7685 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7686 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7687 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7688
a61af66fc99e Initial load
duke
parents:
diff changeset
7689 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7690 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7691 match(Set dst (SubL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7692 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7693
a61af66fc99e Initial load
duke
parents:
diff changeset
7694 format %{ "subq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7695 opcode(0x2B);
a61af66fc99e Initial load
duke
parents:
diff changeset
7696 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7697 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7698 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7699
a61af66fc99e Initial load
duke
parents:
diff changeset
7700 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7701 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7702 match(Set dst (SubL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7703 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7704
a61af66fc99e Initial load
duke
parents:
diff changeset
7705 format %{ "subq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7706 opcode(0x81, 0x05); /* Opcode 81 /5 */
a61af66fc99e Initial load
duke
parents:
diff changeset
7707 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7708 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7709 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7710
a61af66fc99e Initial load
duke
parents:
diff changeset
7711 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7712 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7713 match(Set dst (SubL dst (LoadL src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7714 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7715
a61af66fc99e Initial load
duke
parents:
diff changeset
7716 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
7717 format %{ "subq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7718 opcode(0x2B);
a61af66fc99e Initial load
duke
parents:
diff changeset
7719 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7720 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
7721 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7722
a61af66fc99e Initial load
duke
parents:
diff changeset
7723 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7724 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7725 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7726 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7727
a61af66fc99e Initial load
duke
parents:
diff changeset
7728 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
7729 format %{ "subq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7730 opcode(0x29); /* Opcode 29 /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
7731 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7732 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7733 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7734
a61af66fc99e Initial load
duke
parents:
diff changeset
7735 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7736 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7737 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7738 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7739
a61af66fc99e Initial load
duke
parents:
diff changeset
7740 ins_cost(125); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7741 format %{ "subq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7742 opcode(0x81); /* Opcode 81 /5 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
7743 ins_encode(REX_mem_wide(dst),
a61af66fc99e Initial load
duke
parents:
diff changeset
7744 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7745 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
7746 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7747
a61af66fc99e Initial load
duke
parents:
diff changeset
7748 // Subtract from a pointer
a61af66fc99e Initial load
duke
parents:
diff changeset
7749 // XXX hmpf???
a61af66fc99e Initial load
duke
parents:
diff changeset
7750 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7751 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7752 match(Set dst (AddP dst (SubI zero src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7753 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7754
a61af66fc99e Initial load
duke
parents:
diff changeset
7755 format %{ "subq $dst, $src\t# ptr - int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7756 opcode(0x2B);
a61af66fc99e Initial load
duke
parents:
diff changeset
7757 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7758 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7759 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7760
a61af66fc99e Initial load
duke
parents:
diff changeset
7761 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7762 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7763 match(Set dst (SubI zero dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7764 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7765
a61af66fc99e Initial load
duke
parents:
diff changeset
7766 format %{ "negl $dst\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7767 opcode(0xF7, 0x03); // Opcode F7 /3
a61af66fc99e Initial load
duke
parents:
diff changeset
7768 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7769 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7770 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7771
a61af66fc99e Initial load
duke
parents:
diff changeset
7772 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7773 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7774 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
a61af66fc99e Initial load
duke
parents:
diff changeset
7775 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7776
a61af66fc99e Initial load
duke
parents:
diff changeset
7777 format %{ "negl $dst\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7778 opcode(0xF7, 0x03); // Opcode F7 /3
a61af66fc99e Initial load
duke
parents:
diff changeset
7779 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7780 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7781 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7782
a61af66fc99e Initial load
duke
parents:
diff changeset
7783 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7784 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7785 match(Set dst (SubL zero dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7786 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7787
a61af66fc99e Initial load
duke
parents:
diff changeset
7788 format %{ "negq $dst\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7789 opcode(0xF7, 0x03); // Opcode F7 /3
a61af66fc99e Initial load
duke
parents:
diff changeset
7790 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7791 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7792 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7793
a61af66fc99e Initial load
duke
parents:
diff changeset
7794 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7795 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7796 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
a61af66fc99e Initial load
duke
parents:
diff changeset
7797 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7798
a61af66fc99e Initial load
duke
parents:
diff changeset
7799 format %{ "negq $dst\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7800 opcode(0xF7, 0x03); // Opcode F7 /3
a61af66fc99e Initial load
duke
parents:
diff changeset
7801 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
7802 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
7803 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7804
a61af66fc99e Initial load
duke
parents:
diff changeset
7805
a61af66fc99e Initial load
duke
parents:
diff changeset
7806 //----------Multiplication/Division Instructions-------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
7807 // Integer Multiplication Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
7808 // Multiply Register
a61af66fc99e Initial load
duke
parents:
diff changeset
7809
a61af66fc99e Initial load
duke
parents:
diff changeset
7810 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7811 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7812 match(Set dst (MulI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7813 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7814
a61af66fc99e Initial load
duke
parents:
diff changeset
7815 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
7816 format %{ "imull $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7817 opcode(0x0F, 0xAF);
a61af66fc99e Initial load
duke
parents:
diff changeset
7818 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7819 ins_pipe(ialu_reg_reg_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7820 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7821
a61af66fc99e Initial load
duke
parents:
diff changeset
7822 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7823 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7824 match(Set dst (MulI src imm));
a61af66fc99e Initial load
duke
parents:
diff changeset
7825 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7826
a61af66fc99e Initial load
duke
parents:
diff changeset
7827 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
7828 format %{ "imull $dst, $src, $imm\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7829 opcode(0x69); /* 69 /r id */
a61af66fc99e Initial load
duke
parents:
diff changeset
7830 ins_encode(REX_reg_reg(dst, src),
a61af66fc99e Initial load
duke
parents:
diff changeset
7831 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
a61af66fc99e Initial load
duke
parents:
diff changeset
7832 ins_pipe(ialu_reg_reg_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7833 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7834
a61af66fc99e Initial load
duke
parents:
diff changeset
7835 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7836 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7837 match(Set dst (MulI dst (LoadI src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7838 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7839
a61af66fc99e Initial load
duke
parents:
diff changeset
7840 ins_cost(350);
a61af66fc99e Initial load
duke
parents:
diff changeset
7841 format %{ "imull $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7842 opcode(0x0F, 0xAF);
a61af66fc99e Initial load
duke
parents:
diff changeset
7843 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7844 ins_pipe(ialu_reg_mem_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7845 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7846
a61af66fc99e Initial load
duke
parents:
diff changeset
7847 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7848 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7849 match(Set dst (MulI (LoadI src) imm));
a61af66fc99e Initial load
duke
parents:
diff changeset
7850 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7851
a61af66fc99e Initial load
duke
parents:
diff changeset
7852 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
7853 format %{ "imull $dst, $src, $imm\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7854 opcode(0x69); /* 69 /r id */
a61af66fc99e Initial load
duke
parents:
diff changeset
7855 ins_encode(REX_reg_mem(dst, src),
a61af66fc99e Initial load
duke
parents:
diff changeset
7856 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
a61af66fc99e Initial load
duke
parents:
diff changeset
7857 ins_pipe(ialu_reg_mem_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7858 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7859
a61af66fc99e Initial load
duke
parents:
diff changeset
7860 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7861 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7862 match(Set dst (MulL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7863 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7864
a61af66fc99e Initial load
duke
parents:
diff changeset
7865 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
7866 format %{ "imulq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7867 opcode(0x0F, 0xAF);
a61af66fc99e Initial load
duke
parents:
diff changeset
7868 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7869 ins_pipe(ialu_reg_reg_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7870 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7871
a61af66fc99e Initial load
duke
parents:
diff changeset
7872 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7873 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7874 match(Set dst (MulL src imm));
a61af66fc99e Initial load
duke
parents:
diff changeset
7875 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7876
a61af66fc99e Initial load
duke
parents:
diff changeset
7877 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
7878 format %{ "imulq $dst, $src, $imm\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7879 opcode(0x69); /* 69 /r id */
a61af66fc99e Initial load
duke
parents:
diff changeset
7880 ins_encode(REX_reg_reg_wide(dst, src),
a61af66fc99e Initial load
duke
parents:
diff changeset
7881 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
a61af66fc99e Initial load
duke
parents:
diff changeset
7882 ins_pipe(ialu_reg_reg_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7883 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7884
a61af66fc99e Initial load
duke
parents:
diff changeset
7885 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7886 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7887 match(Set dst (MulL dst (LoadL src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
7888 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7889
a61af66fc99e Initial load
duke
parents:
diff changeset
7890 ins_cost(350);
a61af66fc99e Initial load
duke
parents:
diff changeset
7891 format %{ "imulq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7892 opcode(0x0F, 0xAF);
a61af66fc99e Initial load
duke
parents:
diff changeset
7893 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
7894 ins_pipe(ialu_reg_mem_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7895 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7896
a61af66fc99e Initial load
duke
parents:
diff changeset
7897 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7898 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7899 match(Set dst (MulL (LoadL src) imm));
a61af66fc99e Initial load
duke
parents:
diff changeset
7900 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7901
a61af66fc99e Initial load
duke
parents:
diff changeset
7902 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
7903 format %{ "imulq $dst, $src, $imm\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7904 opcode(0x69); /* 69 /r id */
a61af66fc99e Initial load
duke
parents:
diff changeset
7905 ins_encode(REX_reg_mem_wide(dst, src),
a61af66fc99e Initial load
duke
parents:
diff changeset
7906 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
a61af66fc99e Initial load
duke
parents:
diff changeset
7907 ins_pipe(ialu_reg_mem_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7908 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7909
145
f3de1255b035 6603011: RFE: Optimize long division
rasbold
parents: 124
diff changeset
7910 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
f3de1255b035 6603011: RFE: Optimize long division
rasbold
parents: 124
diff changeset
7911 %{
f3de1255b035 6603011: RFE: Optimize long division
rasbold
parents: 124
diff changeset
7912 match(Set dst (MulHiL src rax));
f3de1255b035 6603011: RFE: Optimize long division
rasbold
parents: 124
diff changeset
7913 effect(USE_KILL rax, KILL cr);
f3de1255b035 6603011: RFE: Optimize long division
rasbold
parents: 124
diff changeset
7914
f3de1255b035 6603011: RFE: Optimize long division
rasbold
parents: 124
diff changeset
7915 ins_cost(300);
f3de1255b035 6603011: RFE: Optimize long division
rasbold
parents: 124
diff changeset
7916 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
f3de1255b035 6603011: RFE: Optimize long division
rasbold
parents: 124
diff changeset
7917 opcode(0xF7, 0x5); /* Opcode F7 /5 */
f3de1255b035 6603011: RFE: Optimize long division
rasbold
parents: 124
diff changeset
7918 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
f3de1255b035 6603011: RFE: Optimize long division
rasbold
parents: 124
diff changeset
7919 ins_pipe(ialu_reg_reg_alu0);
f3de1255b035 6603011: RFE: Optimize long division
rasbold
parents: 124
diff changeset
7920 %}
f3de1255b035 6603011: RFE: Optimize long division
rasbold
parents: 124
diff changeset
7921
0
a61af66fc99e Initial load
duke
parents:
diff changeset
7922 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
a61af66fc99e Initial load
duke
parents:
diff changeset
7923 rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7924 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7925 match(Set rax (DivI rax div));
a61af66fc99e Initial load
duke
parents:
diff changeset
7926 effect(KILL rdx, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7927
a61af66fc99e Initial load
duke
parents:
diff changeset
7928 ins_cost(30*100+10*100); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7929 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7930 "jne,s normal\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7931 "xorl rdx, rdx\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7932 "cmpl $div, -1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7933 "je,s done\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
7934 "normal: cdql\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7935 "idivl $div\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
7936 "done:" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7937 opcode(0xF7, 0x7); /* Opcode F7 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
7938 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
a61af66fc99e Initial load
duke
parents:
diff changeset
7939 ins_pipe(ialu_reg_reg_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7940 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7941
a61af66fc99e Initial load
duke
parents:
diff changeset
7942 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
a61af66fc99e Initial load
duke
parents:
diff changeset
7943 rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7944 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7945 match(Set rax (DivL rax div));
a61af66fc99e Initial load
duke
parents:
diff changeset
7946 effect(KILL rdx, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7947
a61af66fc99e Initial load
duke
parents:
diff changeset
7948 ins_cost(30*100+10*100); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7949 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7950 "cmpq rax, rdx\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7951 "jne,s normal\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7952 "xorl rdx, rdx\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7953 "cmpq $div, -1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7954 "je,s done\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
7955 "normal: cdqq\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7956 "idivq $div\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
7957 "done:" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7958 opcode(0xF7, 0x7); /* Opcode F7 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
7959 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
a61af66fc99e Initial load
duke
parents:
diff changeset
7960 ins_pipe(ialu_reg_reg_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
7961 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7962
a61af66fc99e Initial load
duke
parents:
diff changeset
7963 // Integer DIVMOD with Register, both quotient and mod results
a61af66fc99e Initial load
duke
parents:
diff changeset
7964 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
a61af66fc99e Initial load
duke
parents:
diff changeset
7965 rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7966 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7967 match(DivModI rax div);
a61af66fc99e Initial load
duke
parents:
diff changeset
7968 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7969
a61af66fc99e Initial load
duke
parents:
diff changeset
7970 ins_cost(30*100+10*100); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7971 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7972 "jne,s normal\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7973 "xorl rdx, rdx\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7974 "cmpl $div, -1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7975 "je,s done\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
7976 "normal: cdql\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7977 "idivl $div\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
7978 "done:" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7979 opcode(0xF7, 0x7); /* Opcode F7 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
7980 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
a61af66fc99e Initial load
duke
parents:
diff changeset
7981 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
7982 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
7983
a61af66fc99e Initial load
duke
parents:
diff changeset
7984 // Long DIVMOD with Register, both quotient and mod results
a61af66fc99e Initial load
duke
parents:
diff changeset
7985 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
a61af66fc99e Initial load
duke
parents:
diff changeset
7986 rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
7987 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
7988 match(DivModL rax div);
a61af66fc99e Initial load
duke
parents:
diff changeset
7989 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
7990
a61af66fc99e Initial load
duke
parents:
diff changeset
7991 ins_cost(30*100+10*100); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
7992 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7993 "cmpq rax, rdx\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7994 "jne,s normal\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7995 "xorl rdx, rdx\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7996 "cmpq $div, -1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7997 "je,s done\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
7998 "normal: cdqq\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
7999 "idivq $div\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
8000 "done:" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8001 opcode(0xF7, 0x7); /* Opcode F7 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8002 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
a61af66fc99e Initial load
duke
parents:
diff changeset
8003 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
8004 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8005
a61af66fc99e Initial load
duke
parents:
diff changeset
8006 //----------- DivL-By-Constant-Expansions--------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
8007 // DivI cases are handled by the compiler
a61af66fc99e Initial load
duke
parents:
diff changeset
8008
605
98cb887364d3 6810672: Comment typos
twisti
parents: 569
diff changeset
8009 // Magic constant, reciprocal of 10
0
a61af66fc99e Initial load
duke
parents:
diff changeset
8010 instruct loadConL_0x6666666666666667(rRegL dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
8011 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8012 effect(DEF dst);
a61af66fc99e Initial load
duke
parents:
diff changeset
8013
a61af66fc99e Initial load
duke
parents:
diff changeset
8014 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8015 ins_encode(load_immL(dst, 0x6666666666666667));
a61af66fc99e Initial load
duke
parents:
diff changeset
8016 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8017 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8018
a61af66fc99e Initial load
duke
parents:
diff changeset
8019 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8020 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8021 effect(DEF dst, USE src, USE_KILL rax, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8022
a61af66fc99e Initial load
duke
parents:
diff changeset
8023 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8024 opcode(0xF7, 0x5); /* Opcode F7 /5 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8025 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8026 ins_pipe(ialu_reg_reg_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
8027 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8028
a61af66fc99e Initial load
duke
parents:
diff changeset
8029 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8030 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8031 effect(USE_DEF dst, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8032
a61af66fc99e Initial load
duke
parents:
diff changeset
8033 format %{ "sarq $dst, #63\t# Used in div-by-10" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8034 opcode(0xC1, 0x7); /* C1 /7 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
8035 ins_encode(reg_opc_imm_wide(dst, 0x3F));
a61af66fc99e Initial load
duke
parents:
diff changeset
8036 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8037 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8038
a61af66fc99e Initial load
duke
parents:
diff changeset
8039 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8040 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8041 effect(USE_DEF dst, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8042
a61af66fc99e Initial load
duke
parents:
diff changeset
8043 format %{ "sarq $dst, #2\t# Used in div-by-10" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8044 opcode(0xC1, 0x7); /* C1 /7 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
8045 ins_encode(reg_opc_imm_wide(dst, 0x2));
a61af66fc99e Initial load
duke
parents:
diff changeset
8046 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8047 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8048
a61af66fc99e Initial load
duke
parents:
diff changeset
8049 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
a61af66fc99e Initial load
duke
parents:
diff changeset
8050 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8051 match(Set dst (DivL src div));
a61af66fc99e Initial load
duke
parents:
diff changeset
8052
a61af66fc99e Initial load
duke
parents:
diff changeset
8053 ins_cost((5+8)*100);
a61af66fc99e Initial load
duke
parents:
diff changeset
8054 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8055 rax_RegL rax; // Killed temp
a61af66fc99e Initial load
duke
parents:
diff changeset
8056 rFlagsReg cr; // Killed
a61af66fc99e Initial load
duke
parents:
diff changeset
8057 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
a61af66fc99e Initial load
duke
parents:
diff changeset
8058 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
a61af66fc99e Initial load
duke
parents:
diff changeset
8059 sarL_rReg_63(src, cr); // sarq src, 63
a61af66fc99e Initial load
duke
parents:
diff changeset
8060 sarL_rReg_2(dst, cr); // sarq rdx, 2
a61af66fc99e Initial load
duke
parents:
diff changeset
8061 subL_rReg(dst, src, cr); // subl rdx, src
a61af66fc99e Initial load
duke
parents:
diff changeset
8062 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8063 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8064
a61af66fc99e Initial load
duke
parents:
diff changeset
8065 //-----------------------------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
8066
a61af66fc99e Initial load
duke
parents:
diff changeset
8067 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
a61af66fc99e Initial load
duke
parents:
diff changeset
8068 rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8069 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8070 match(Set rdx (ModI rax div));
a61af66fc99e Initial load
duke
parents:
diff changeset
8071 effect(KILL rax, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8072
a61af66fc99e Initial load
duke
parents:
diff changeset
8073 ins_cost(300); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
8074 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8075 "jne,s normal\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8076 "xorl rdx, rdx\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8077 "cmpl $div, -1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8078 "je,s done\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
8079 "normal: cdql\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8080 "idivl $div\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
8081 "done:" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8082 opcode(0xF7, 0x7); /* Opcode F7 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8083 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
a61af66fc99e Initial load
duke
parents:
diff changeset
8084 ins_pipe(ialu_reg_reg_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
8085 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8086
a61af66fc99e Initial load
duke
parents:
diff changeset
8087 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
a61af66fc99e Initial load
duke
parents:
diff changeset
8088 rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8089 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8090 match(Set rdx (ModL rax div));
a61af66fc99e Initial load
duke
parents:
diff changeset
8091 effect(KILL rax, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8092
a61af66fc99e Initial load
duke
parents:
diff changeset
8093 ins_cost(300); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
8094 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8095 "cmpq rax, rdx\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8096 "jne,s normal\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8097 "xorl rdx, rdx\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8098 "cmpq $div, -1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8099 "je,s done\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
8100 "normal: cdqq\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
8101 "idivq $div\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
8102 "done:" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8103 opcode(0xF7, 0x7); /* Opcode F7 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8104 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
a61af66fc99e Initial load
duke
parents:
diff changeset
8105 ins_pipe(ialu_reg_reg_alu0);
a61af66fc99e Initial load
duke
parents:
diff changeset
8106 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8107
a61af66fc99e Initial load
duke
parents:
diff changeset
8108 // Integer Shift Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
8109 // Shift Left by one
a61af66fc99e Initial load
duke
parents:
diff changeset
8110 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8111 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8112 match(Set dst (LShiftI dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8113 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8114
a61af66fc99e Initial load
duke
parents:
diff changeset
8115 format %{ "sall $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8116 opcode(0xD1, 0x4); /* D1 /4 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8117 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8118 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8119 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8120
a61af66fc99e Initial load
duke
parents:
diff changeset
8121 // Shift Left by one
a61af66fc99e Initial load
duke
parents:
diff changeset
8122 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8123 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8124 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8125 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8126
a61af66fc99e Initial load
duke
parents:
diff changeset
8127 format %{ "sall $dst, $shift\t" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8128 opcode(0xD1, 0x4); /* D1 /4 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8129 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8130 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8131 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8132
a61af66fc99e Initial load
duke
parents:
diff changeset
8133 // Shift Left by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8134 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8135 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8136 match(Set dst (LShiftI dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8137 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8138
a61af66fc99e Initial load
duke
parents:
diff changeset
8139 format %{ "sall $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8140 opcode(0xC1, 0x4); /* C1 /4 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
8141 ins_encode(reg_opc_imm(dst, shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8142 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8143 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8144
a61af66fc99e Initial load
duke
parents:
diff changeset
8145 // Shift Left by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8146 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8147 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8148 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8149 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8150
a61af66fc99e Initial load
duke
parents:
diff changeset
8151 format %{ "sall $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8152 opcode(0xC1, 0x4); /* C1 /4 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
8153 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8154 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8155 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8156
a61af66fc99e Initial load
duke
parents:
diff changeset
8157 // Shift Left by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8158 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8159 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8160 match(Set dst (LShiftI dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8161 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8162
a61af66fc99e Initial load
duke
parents:
diff changeset
8163 format %{ "sall $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8164 opcode(0xD3, 0x4); /* D3 /4 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8165 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8166 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8167 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8168
a61af66fc99e Initial load
duke
parents:
diff changeset
8169 // Shift Left by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8170 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8171 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8172 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8173 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8174
a61af66fc99e Initial load
duke
parents:
diff changeset
8175 format %{ "sall $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8176 opcode(0xD3, 0x4); /* D3 /4 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8177 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8178 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8179 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8180
a61af66fc99e Initial load
duke
parents:
diff changeset
8181 // Arithmetic shift right by one
a61af66fc99e Initial load
duke
parents:
diff changeset
8182 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8183 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8184 match(Set dst (RShiftI dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8185 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8186
a61af66fc99e Initial load
duke
parents:
diff changeset
8187 format %{ "sarl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8188 opcode(0xD1, 0x7); /* D1 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8189 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8190 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8191 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8192
a61af66fc99e Initial load
duke
parents:
diff changeset
8193 // Arithmetic shift right by one
a61af66fc99e Initial load
duke
parents:
diff changeset
8194 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8195 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8196 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8197 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8198
a61af66fc99e Initial load
duke
parents:
diff changeset
8199 format %{ "sarl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8200 opcode(0xD1, 0x7); /* D1 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8201 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8202 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8203 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8204
a61af66fc99e Initial load
duke
parents:
diff changeset
8205 // Arithmetic Shift Right by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8206 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8207 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8208 match(Set dst (RShiftI dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8209 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8210
a61af66fc99e Initial load
duke
parents:
diff changeset
8211 format %{ "sarl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8212 opcode(0xC1, 0x7); /* C1 /7 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
8213 ins_encode(reg_opc_imm(dst, shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8214 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8215 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8216
a61af66fc99e Initial load
duke
parents:
diff changeset
8217 // Arithmetic Shift Right by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8218 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8219 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8220 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8221 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8222
a61af66fc99e Initial load
duke
parents:
diff changeset
8223 format %{ "sarl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8224 opcode(0xC1, 0x7); /* C1 /7 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
8225 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8226 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8227 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8228
a61af66fc99e Initial load
duke
parents:
diff changeset
8229 // Arithmetic Shift Right by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8230 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8231 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8232 match(Set dst (RShiftI dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8233 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8234
a61af66fc99e Initial load
duke
parents:
diff changeset
8235 format %{ "sarl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8236 opcode(0xD3, 0x7); /* D3 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8237 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8238 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8239 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8240
a61af66fc99e Initial load
duke
parents:
diff changeset
8241 // Arithmetic Shift Right by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8242 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8243 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8244 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8245 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8246
a61af66fc99e Initial load
duke
parents:
diff changeset
8247 format %{ "sarl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8248 opcode(0xD3, 0x7); /* D3 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8249 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8250 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8251 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8252
a61af66fc99e Initial load
duke
parents:
diff changeset
8253 // Logical shift right by one
a61af66fc99e Initial load
duke
parents:
diff changeset
8254 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8255 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8256 match(Set dst (URShiftI dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8257 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8258
a61af66fc99e Initial load
duke
parents:
diff changeset
8259 format %{ "shrl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8260 opcode(0xD1, 0x5); /* D1 /5 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8261 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8262 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8263 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8264
a61af66fc99e Initial load
duke
parents:
diff changeset
8265 // Logical shift right by one
a61af66fc99e Initial load
duke
parents:
diff changeset
8266 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8267 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8268 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8269 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8270
a61af66fc99e Initial load
duke
parents:
diff changeset
8271 format %{ "shrl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8272 opcode(0xD1, 0x5); /* D1 /5 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8273 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8274 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8275 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8276
a61af66fc99e Initial load
duke
parents:
diff changeset
8277 // Logical Shift Right by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8278 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8279 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8280 match(Set dst (URShiftI dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8281 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8282
a61af66fc99e Initial load
duke
parents:
diff changeset
8283 format %{ "shrl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8284 opcode(0xC1, 0x5); /* C1 /5 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
8285 ins_encode(reg_opc_imm(dst, shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8286 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8287 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8288
a61af66fc99e Initial load
duke
parents:
diff changeset
8289 // Logical Shift Right by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8290 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8291 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8292 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8293 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8294
a61af66fc99e Initial load
duke
parents:
diff changeset
8295 format %{ "shrl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8296 opcode(0xC1, 0x5); /* C1 /5 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
8297 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8298 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8299 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8300
a61af66fc99e Initial load
duke
parents:
diff changeset
8301 // Logical Shift Right by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8302 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8303 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8304 match(Set dst (URShiftI dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8305 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8306
a61af66fc99e Initial load
duke
parents:
diff changeset
8307 format %{ "shrl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8308 opcode(0xD3, 0x5); /* D3 /5 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8309 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8310 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8311 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8312
a61af66fc99e Initial load
duke
parents:
diff changeset
8313 // Logical Shift Right by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8314 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8315 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8316 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8317 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8318
a61af66fc99e Initial load
duke
parents:
diff changeset
8319 format %{ "shrl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8320 opcode(0xD3, 0x5); /* D3 /5 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8321 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8322 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8323 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8324
a61af66fc99e Initial load
duke
parents:
diff changeset
8325 // Long Shift Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
8326 // Shift Left by one
a61af66fc99e Initial load
duke
parents:
diff changeset
8327 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8328 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8329 match(Set dst (LShiftL dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8330 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8331
a61af66fc99e Initial load
duke
parents:
diff changeset
8332 format %{ "salq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8333 opcode(0xD1, 0x4); /* D1 /4 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8334 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8335 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8336 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8337
a61af66fc99e Initial load
duke
parents:
diff changeset
8338 // Shift Left by one
a61af66fc99e Initial load
duke
parents:
diff changeset
8339 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8340 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8341 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8342 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8343
a61af66fc99e Initial load
duke
parents:
diff changeset
8344 format %{ "salq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8345 opcode(0xD1, 0x4); /* D1 /4 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8346 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8347 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8348 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8349
a61af66fc99e Initial load
duke
parents:
diff changeset
8350 // Shift Left by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8351 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8352 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8353 match(Set dst (LShiftL dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8354 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8355
a61af66fc99e Initial load
duke
parents:
diff changeset
8356 format %{ "salq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8357 opcode(0xC1, 0x4); /* C1 /4 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
8358 ins_encode(reg_opc_imm_wide(dst, shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8359 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8360 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8361
a61af66fc99e Initial load
duke
parents:
diff changeset
8362 // Shift Left by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8363 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8364 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8365 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8366 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8367
a61af66fc99e Initial load
duke
parents:
diff changeset
8368 format %{ "salq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8369 opcode(0xC1, 0x4); /* C1 /4 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
8370 ins_encode(REX_mem_wide(dst), OpcP,
a61af66fc99e Initial load
duke
parents:
diff changeset
8371 RM_opc_mem(secondary, dst), Con8or32(shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8372 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8373 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8374
a61af66fc99e Initial load
duke
parents:
diff changeset
8375 // Shift Left by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8376 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8377 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8378 match(Set dst (LShiftL dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8379 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8380
a61af66fc99e Initial load
duke
parents:
diff changeset
8381 format %{ "salq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8382 opcode(0xD3, 0x4); /* D3 /4 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8383 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8384 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8385 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8386
a61af66fc99e Initial load
duke
parents:
diff changeset
8387 // Shift Left by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8388 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8389 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8390 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8391 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8392
a61af66fc99e Initial load
duke
parents:
diff changeset
8393 format %{ "salq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8394 opcode(0xD3, 0x4); /* D3 /4 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8395 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8396 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8397 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8398
a61af66fc99e Initial load
duke
parents:
diff changeset
8399 // Arithmetic shift right by one
a61af66fc99e Initial load
duke
parents:
diff changeset
8400 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8401 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8402 match(Set dst (RShiftL dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8403 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8404
a61af66fc99e Initial load
duke
parents:
diff changeset
8405 format %{ "sarq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8406 opcode(0xD1, 0x7); /* D1 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8407 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8408 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8409 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8410
a61af66fc99e Initial load
duke
parents:
diff changeset
8411 // Arithmetic shift right by one
a61af66fc99e Initial load
duke
parents:
diff changeset
8412 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8413 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8414 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8415 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8416
a61af66fc99e Initial load
duke
parents:
diff changeset
8417 format %{ "sarq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8418 opcode(0xD1, 0x7); /* D1 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8419 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8420 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8421 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8422
a61af66fc99e Initial load
duke
parents:
diff changeset
8423 // Arithmetic Shift Right by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8424 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8425 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8426 match(Set dst (RShiftL dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8427 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8428
a61af66fc99e Initial load
duke
parents:
diff changeset
8429 format %{ "sarq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8430 opcode(0xC1, 0x7); /* C1 /7 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
8431 ins_encode(reg_opc_imm_wide(dst, shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8432 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8433 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8434
a61af66fc99e Initial load
duke
parents:
diff changeset
8435 // Arithmetic Shift Right by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8436 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8437 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8438 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8439 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8440
a61af66fc99e Initial load
duke
parents:
diff changeset
8441 format %{ "sarq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8442 opcode(0xC1, 0x7); /* C1 /7 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
8443 ins_encode(REX_mem_wide(dst), OpcP,
a61af66fc99e Initial load
duke
parents:
diff changeset
8444 RM_opc_mem(secondary, dst), Con8or32(shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8445 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8446 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8447
a61af66fc99e Initial load
duke
parents:
diff changeset
8448 // Arithmetic Shift Right by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8449 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8450 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8451 match(Set dst (RShiftL dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8452 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8453
a61af66fc99e Initial load
duke
parents:
diff changeset
8454 format %{ "sarq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8455 opcode(0xD3, 0x7); /* D3 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8456 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8457 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8458 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8459
a61af66fc99e Initial load
duke
parents:
diff changeset
8460 // Arithmetic Shift Right by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8461 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8462 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8463 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8464 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8465
a61af66fc99e Initial load
duke
parents:
diff changeset
8466 format %{ "sarq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8467 opcode(0xD3, 0x7); /* D3 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8468 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8469 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8470 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8471
a61af66fc99e Initial load
duke
parents:
diff changeset
8472 // Logical shift right by one
a61af66fc99e Initial load
duke
parents:
diff changeset
8473 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8474 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8475 match(Set dst (URShiftL dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8476 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8477
a61af66fc99e Initial load
duke
parents:
diff changeset
8478 format %{ "shrq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8479 opcode(0xD1, 0x5); /* D1 /5 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8480 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
a61af66fc99e Initial load
duke
parents:
diff changeset
8481 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8482 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8483
a61af66fc99e Initial load
duke
parents:
diff changeset
8484 // Logical shift right by one
a61af66fc99e Initial load
duke
parents:
diff changeset
8485 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8486 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8487 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8488 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8489
a61af66fc99e Initial load
duke
parents:
diff changeset
8490 format %{ "shrq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8491 opcode(0xD1, 0x5); /* D1 /5 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8492 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8493 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8494 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8495
a61af66fc99e Initial load
duke
parents:
diff changeset
8496 // Logical Shift Right by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8497 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8498 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8499 match(Set dst (URShiftL dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8500 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8501
a61af66fc99e Initial load
duke
parents:
diff changeset
8502 format %{ "shrq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8503 opcode(0xC1, 0x5); /* C1 /5 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
8504 ins_encode(reg_opc_imm_wide(dst, shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8505 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8506 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8507
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
8508
0
a61af66fc99e Initial load
duke
parents:
diff changeset
8509 // Logical Shift Right by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8510 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8511 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8512 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8513 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8514
a61af66fc99e Initial load
duke
parents:
diff changeset
8515 format %{ "shrq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8516 opcode(0xC1, 0x5); /* C1 /5 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
8517 ins_encode(REX_mem_wide(dst), OpcP,
a61af66fc99e Initial load
duke
parents:
diff changeset
8518 RM_opc_mem(secondary, dst), Con8or32(shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8519 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8520 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8521
a61af66fc99e Initial load
duke
parents:
diff changeset
8522 // Logical Shift Right by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8523 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8524 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8525 match(Set dst (URShiftL dst shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8526 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8527
a61af66fc99e Initial load
duke
parents:
diff changeset
8528 format %{ "shrq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8529 opcode(0xD3, 0x5); /* D3 /5 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8530 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8531 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8532 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8533
a61af66fc99e Initial load
duke
parents:
diff changeset
8534 // Logical Shift Right by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8535 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8536 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8537 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8538 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8539
a61af66fc99e Initial load
duke
parents:
diff changeset
8540 format %{ "shrq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8541 opcode(0xD3, 0x5); /* D3 /5 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8542 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8543 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8544 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8545
a61af66fc99e Initial load
duke
parents:
diff changeset
8546 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
a61af66fc99e Initial load
duke
parents:
diff changeset
8547 // This idiom is used by the compiler for the i2b bytecode.
a61af66fc99e Initial load
duke
parents:
diff changeset
8548 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
a61af66fc99e Initial load
duke
parents:
diff changeset
8549 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8550 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
a61af66fc99e Initial load
duke
parents:
diff changeset
8551
a61af66fc99e Initial load
duke
parents:
diff changeset
8552 format %{ "movsbl $dst, $src\t# i2b" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8553 opcode(0x0F, 0xBE);
a61af66fc99e Initial load
duke
parents:
diff changeset
8554 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8555 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8556 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8557
a61af66fc99e Initial load
duke
parents:
diff changeset
8558 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
a61af66fc99e Initial load
duke
parents:
diff changeset
8559 // This idiom is used by the compiler the i2s bytecode.
a61af66fc99e Initial load
duke
parents:
diff changeset
8560 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
a61af66fc99e Initial load
duke
parents:
diff changeset
8561 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8562 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
a61af66fc99e Initial load
duke
parents:
diff changeset
8563
a61af66fc99e Initial load
duke
parents:
diff changeset
8564 format %{ "movswl $dst, $src\t# i2s" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8565 opcode(0x0F, 0xBF);
a61af66fc99e Initial load
duke
parents:
diff changeset
8566 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8567 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8568 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8569
a61af66fc99e Initial load
duke
parents:
diff changeset
8570 // ROL/ROR instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
8571
a61af66fc99e Initial load
duke
parents:
diff changeset
8572 // ROL expand
a61af66fc99e Initial load
duke
parents:
diff changeset
8573 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8574 effect(KILL cr, USE_DEF dst);
a61af66fc99e Initial load
duke
parents:
diff changeset
8575
a61af66fc99e Initial load
duke
parents:
diff changeset
8576 format %{ "roll $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8577 opcode(0xD1, 0x0); /* Opcode D1 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8578 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8579 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8580 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8581
a61af66fc99e Initial load
duke
parents:
diff changeset
8582 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8583 effect(USE_DEF dst, USE shift, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8584
a61af66fc99e Initial load
duke
parents:
diff changeset
8585 format %{ "roll $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8586 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
8587 ins_encode( reg_opc_imm(dst, shift) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8588 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8589 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8590
a61af66fc99e Initial load
duke
parents:
diff changeset
8591 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8592 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8593 effect(USE_DEF dst, USE shift, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8594
a61af66fc99e Initial load
duke
parents:
diff changeset
8595 format %{ "roll $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8596 opcode(0xD3, 0x0); /* Opcode D3 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8597 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8598 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8599 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8600 // end of ROL expand
a61af66fc99e Initial load
duke
parents:
diff changeset
8601
a61af66fc99e Initial load
duke
parents:
diff changeset
8602 // Rotate Left by one
a61af66fc99e Initial load
duke
parents:
diff changeset
8603 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8604 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8605 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8606
a61af66fc99e Initial load
duke
parents:
diff changeset
8607 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8608 rolI_rReg_imm1(dst, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8609 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8610 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8611
a61af66fc99e Initial load
duke
parents:
diff changeset
8612 // Rotate Left by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8613 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8614 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8615 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
a61af66fc99e Initial load
duke
parents:
diff changeset
8616 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8617
a61af66fc99e Initial load
duke
parents:
diff changeset
8618 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8619 rolI_rReg_imm8(dst, lshift, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8620 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8621 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8622
a61af66fc99e Initial load
duke
parents:
diff changeset
8623 // Rotate Left by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8624 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8625 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8626 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
a61af66fc99e Initial load
duke
parents:
diff changeset
8627
a61af66fc99e Initial load
duke
parents:
diff changeset
8628 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8629 rolI_rReg_CL(dst, shift, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8630 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8631 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8632
a61af66fc99e Initial load
duke
parents:
diff changeset
8633 // Rotate Left by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8634 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8635 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8636 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
a61af66fc99e Initial load
duke
parents:
diff changeset
8637
a61af66fc99e Initial load
duke
parents:
diff changeset
8638 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8639 rolI_rReg_CL(dst, shift, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8640 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8641 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8642
a61af66fc99e Initial load
duke
parents:
diff changeset
8643 // ROR expand
a61af66fc99e Initial load
duke
parents:
diff changeset
8644 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8645 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8646 effect(USE_DEF dst, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8647
a61af66fc99e Initial load
duke
parents:
diff changeset
8648 format %{ "rorl $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8649 opcode(0xD1, 0x1); /* D1 /1 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8650 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8651 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8652 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8653
a61af66fc99e Initial load
duke
parents:
diff changeset
8654 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8655 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8656 effect(USE_DEF dst, USE shift, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8657
a61af66fc99e Initial load
duke
parents:
diff changeset
8658 format %{ "rorl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8659 opcode(0xC1, 0x1); /* C1 /1 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
8660 ins_encode(reg_opc_imm(dst, shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8661 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8662 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8663
a61af66fc99e Initial load
duke
parents:
diff changeset
8664 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8665 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8666 effect(USE_DEF dst, USE shift, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8667
a61af66fc99e Initial load
duke
parents:
diff changeset
8668 format %{ "rorl $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8669 opcode(0xD3, 0x1); /* D3 /1 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8670 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8671 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8672 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8673 // end of ROR expand
a61af66fc99e Initial load
duke
parents:
diff changeset
8674
a61af66fc99e Initial load
duke
parents:
diff changeset
8675 // Rotate Right by one
a61af66fc99e Initial load
duke
parents:
diff changeset
8676 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8677 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8678 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8679
a61af66fc99e Initial load
duke
parents:
diff changeset
8680 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8681 rorI_rReg_imm1(dst, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8682 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8683 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8684
a61af66fc99e Initial load
duke
parents:
diff changeset
8685 // Rotate Right by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8686 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8687 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8688 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
a61af66fc99e Initial load
duke
parents:
diff changeset
8689 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8690
a61af66fc99e Initial load
duke
parents:
diff changeset
8691 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8692 rorI_rReg_imm8(dst, rshift, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8693 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8694 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8695
a61af66fc99e Initial load
duke
parents:
diff changeset
8696 // Rotate Right by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8697 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8698 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8699 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
a61af66fc99e Initial load
duke
parents:
diff changeset
8700
a61af66fc99e Initial load
duke
parents:
diff changeset
8701 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8702 rorI_rReg_CL(dst, shift, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8703 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8704 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8705
a61af66fc99e Initial load
duke
parents:
diff changeset
8706 // Rotate Right by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8707 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8708 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8709 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
a61af66fc99e Initial load
duke
parents:
diff changeset
8710
a61af66fc99e Initial load
duke
parents:
diff changeset
8711 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8712 rorI_rReg_CL(dst, shift, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8713 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8714 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8715
a61af66fc99e Initial load
duke
parents:
diff changeset
8716 // for long rotate
a61af66fc99e Initial load
duke
parents:
diff changeset
8717 // ROL expand
a61af66fc99e Initial load
duke
parents:
diff changeset
8718 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8719 effect(USE_DEF dst, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8720
a61af66fc99e Initial load
duke
parents:
diff changeset
8721 format %{ "rolq $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8722 opcode(0xD1, 0x0); /* Opcode D1 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8723 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8724 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8725 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8726
a61af66fc99e Initial load
duke
parents:
diff changeset
8727 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8728 effect(USE_DEF dst, USE shift, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8729
a61af66fc99e Initial load
duke
parents:
diff changeset
8730 format %{ "rolq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8731 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
8732 ins_encode( reg_opc_imm_wide(dst, shift) );
a61af66fc99e Initial load
duke
parents:
diff changeset
8733 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8734 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8735
a61af66fc99e Initial load
duke
parents:
diff changeset
8736 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8737 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8738 effect(USE_DEF dst, USE shift, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8739
a61af66fc99e Initial load
duke
parents:
diff changeset
8740 format %{ "rolq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8741 opcode(0xD3, 0x0); /* Opcode D3 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8742 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8743 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8744 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8745 // end of ROL expand
a61af66fc99e Initial load
duke
parents:
diff changeset
8746
a61af66fc99e Initial load
duke
parents:
diff changeset
8747 // Rotate Left by one
a61af66fc99e Initial load
duke
parents:
diff changeset
8748 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8749 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8750 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8751
a61af66fc99e Initial load
duke
parents:
diff changeset
8752 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8753 rolL_rReg_imm1(dst, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8754 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8755 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8756
a61af66fc99e Initial load
duke
parents:
diff changeset
8757 // Rotate Left by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8758 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8759 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8760 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
a61af66fc99e Initial load
duke
parents:
diff changeset
8761 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8762
a61af66fc99e Initial load
duke
parents:
diff changeset
8763 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8764 rolL_rReg_imm8(dst, lshift, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8765 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8766 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8767
a61af66fc99e Initial load
duke
parents:
diff changeset
8768 // Rotate Left by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8769 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8770 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8771 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
a61af66fc99e Initial load
duke
parents:
diff changeset
8772
a61af66fc99e Initial load
duke
parents:
diff changeset
8773 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8774 rolL_rReg_CL(dst, shift, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8775 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8776 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8777
a61af66fc99e Initial load
duke
parents:
diff changeset
8778 // Rotate Left by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8779 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8780 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8781 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
a61af66fc99e Initial load
duke
parents:
diff changeset
8782
a61af66fc99e Initial load
duke
parents:
diff changeset
8783 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8784 rolL_rReg_CL(dst, shift, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8785 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8786 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8787
a61af66fc99e Initial load
duke
parents:
diff changeset
8788 // ROR expand
a61af66fc99e Initial load
duke
parents:
diff changeset
8789 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8790 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8791 effect(USE_DEF dst, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8792
a61af66fc99e Initial load
duke
parents:
diff changeset
8793 format %{ "rorq $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8794 opcode(0xD1, 0x1); /* D1 /1 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8795 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8796 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8797 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8798
a61af66fc99e Initial load
duke
parents:
diff changeset
8799 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8800 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8801 effect(USE_DEF dst, USE shift, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8802
a61af66fc99e Initial load
duke
parents:
diff changeset
8803 format %{ "rorq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8804 opcode(0xC1, 0x1); /* C1 /1 ib */
a61af66fc99e Initial load
duke
parents:
diff changeset
8805 ins_encode(reg_opc_imm_wide(dst, shift));
a61af66fc99e Initial load
duke
parents:
diff changeset
8806 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8807 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8808
a61af66fc99e Initial load
duke
parents:
diff changeset
8809 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8810 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8811 effect(USE_DEF dst, USE shift, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8812
a61af66fc99e Initial load
duke
parents:
diff changeset
8813 format %{ "rorq $dst, $shift" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8814 opcode(0xD3, 0x1); /* D3 /1 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8815 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8816 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8817 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8818 // end of ROR expand
a61af66fc99e Initial load
duke
parents:
diff changeset
8819
a61af66fc99e Initial load
duke
parents:
diff changeset
8820 // Rotate Right by one
a61af66fc99e Initial load
duke
parents:
diff changeset
8821 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8822 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8823 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8824
a61af66fc99e Initial load
duke
parents:
diff changeset
8825 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8826 rorL_rReg_imm1(dst, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8827 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8828 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8829
a61af66fc99e Initial load
duke
parents:
diff changeset
8830 // Rotate Right by 8-bit immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8831 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8832 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8833 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
a61af66fc99e Initial load
duke
parents:
diff changeset
8834 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8835
a61af66fc99e Initial load
duke
parents:
diff changeset
8836 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8837 rorL_rReg_imm8(dst, rshift, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8838 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8839 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8840
a61af66fc99e Initial load
duke
parents:
diff changeset
8841 // Rotate Right by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8842 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8843 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8844 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
a61af66fc99e Initial load
duke
parents:
diff changeset
8845
a61af66fc99e Initial load
duke
parents:
diff changeset
8846 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8847 rorL_rReg_CL(dst, shift, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8848 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8849 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8850
a61af66fc99e Initial load
duke
parents:
diff changeset
8851 // Rotate Right by variable
a61af66fc99e Initial load
duke
parents:
diff changeset
8852 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8853 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8854 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
a61af66fc99e Initial load
duke
parents:
diff changeset
8855
a61af66fc99e Initial load
duke
parents:
diff changeset
8856 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8857 rorL_rReg_CL(dst, shift, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8858 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8859 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8860
a61af66fc99e Initial load
duke
parents:
diff changeset
8861 // Logical Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
8862
a61af66fc99e Initial load
duke
parents:
diff changeset
8863 // Integer Logical Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
8864
a61af66fc99e Initial load
duke
parents:
diff changeset
8865 // And Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
8866 // And Register with Register
a61af66fc99e Initial load
duke
parents:
diff changeset
8867 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8868 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8869 match(Set dst (AndI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8870 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8871
a61af66fc99e Initial load
duke
parents:
diff changeset
8872 format %{ "andl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8873 opcode(0x23);
a61af66fc99e Initial load
duke
parents:
diff changeset
8874 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8875 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8876 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8877
a61af66fc99e Initial load
duke
parents:
diff changeset
8878 // And Register with Immediate 255
a61af66fc99e Initial load
duke
parents:
diff changeset
8879 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
8880 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8881 match(Set dst (AndI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8882
a61af66fc99e Initial load
duke
parents:
diff changeset
8883 format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8884 opcode(0x0F, 0xB6);
a61af66fc99e Initial load
duke
parents:
diff changeset
8885 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8886 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8887 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8888
a61af66fc99e Initial load
duke
parents:
diff changeset
8889 // And Register with Immediate 255 and promote to long
a61af66fc99e Initial load
duke
parents:
diff changeset
8890 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
a61af66fc99e Initial load
duke
parents:
diff changeset
8891 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8892 match(Set dst (ConvI2L (AndI src mask)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8893
a61af66fc99e Initial load
duke
parents:
diff changeset
8894 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8895 opcode(0x0F, 0xB6);
a61af66fc99e Initial load
duke
parents:
diff changeset
8896 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8897 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8898 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8899
a61af66fc99e Initial load
duke
parents:
diff changeset
8900 // And Register with Immediate 65535
a61af66fc99e Initial load
duke
parents:
diff changeset
8901 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
8902 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8903 match(Set dst (AndI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8904
a61af66fc99e Initial load
duke
parents:
diff changeset
8905 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8906 opcode(0x0F, 0xB7);
a61af66fc99e Initial load
duke
parents:
diff changeset
8907 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8908 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8909 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8910
a61af66fc99e Initial load
duke
parents:
diff changeset
8911 // And Register with Immediate 65535 and promote to long
a61af66fc99e Initial load
duke
parents:
diff changeset
8912 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
a61af66fc99e Initial load
duke
parents:
diff changeset
8913 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8914 match(Set dst (ConvI2L (AndI src mask)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8915
a61af66fc99e Initial load
duke
parents:
diff changeset
8916 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8917 opcode(0x0F, 0xB7);
a61af66fc99e Initial load
duke
parents:
diff changeset
8918 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8919 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8920 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8921
a61af66fc99e Initial load
duke
parents:
diff changeset
8922 // And Register with Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8923 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8924 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8925 match(Set dst (AndI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8926 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8927
a61af66fc99e Initial load
duke
parents:
diff changeset
8928 format %{ "andl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8929 opcode(0x81, 0x04); /* Opcode 81 /4 */
a61af66fc99e Initial load
duke
parents:
diff changeset
8930 ins_encode(OpcSErm(dst, src), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8931 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8932 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8933
a61af66fc99e Initial load
duke
parents:
diff changeset
8934 // And Register with Memory
a61af66fc99e Initial load
duke
parents:
diff changeset
8935 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8936 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8937 match(Set dst (AndI dst (LoadI src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8938 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8939
a61af66fc99e Initial load
duke
parents:
diff changeset
8940 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
8941 format %{ "andl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8942 opcode(0x23);
a61af66fc99e Initial load
duke
parents:
diff changeset
8943 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8944 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
8945 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8946
a61af66fc99e Initial load
duke
parents:
diff changeset
8947 // And Memory with Register
a61af66fc99e Initial load
duke
parents:
diff changeset
8948 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8949 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8950 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8951 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8952
a61af66fc99e Initial load
duke
parents:
diff changeset
8953 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
8954 format %{ "andl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8955 opcode(0x21); /* Opcode 21 /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
8956 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
8957 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8958 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8959
a61af66fc99e Initial load
duke
parents:
diff changeset
8960 // And Memory with Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8961 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8962 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8963 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
8964 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8965
a61af66fc99e Initial load
duke
parents:
diff changeset
8966 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
8967 format %{ "andl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8968 opcode(0x81, 0x4); /* Opcode 81 /4 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
8969 ins_encode(REX_mem(dst), OpcSE(src),
a61af66fc99e Initial load
duke
parents:
diff changeset
8970 RM_opc_mem(secondary, dst), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8971 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
8972 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8973
a61af66fc99e Initial load
duke
parents:
diff changeset
8974 // Or Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
8975 // Or Register with Register
a61af66fc99e Initial load
duke
parents:
diff changeset
8976 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8977 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8978 match(Set dst (OrI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8979 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8980
a61af66fc99e Initial load
duke
parents:
diff changeset
8981 format %{ "orl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8982 opcode(0x0B);
a61af66fc99e Initial load
duke
parents:
diff changeset
8983 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8984 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8985 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8986
a61af66fc99e Initial load
duke
parents:
diff changeset
8987 // Or Register with Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
8988 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
8989 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
8990 match(Set dst (OrI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8991 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
8992
a61af66fc99e Initial load
duke
parents:
diff changeset
8993 format %{ "orl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8994 opcode(0x81, 0x01); /* Opcode 81 /1 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
8995 ins_encode(OpcSErm(dst, src), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
8996 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
8997 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
8998
a61af66fc99e Initial load
duke
parents:
diff changeset
8999 // Or Register with Memory
a61af66fc99e Initial load
duke
parents:
diff changeset
9000 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9001 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9002 match(Set dst (OrI dst (LoadI src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9003 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9004
a61af66fc99e Initial load
duke
parents:
diff changeset
9005 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
9006 format %{ "orl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9007 opcode(0x0B);
a61af66fc99e Initial load
duke
parents:
diff changeset
9008 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9009 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
9010 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9011
a61af66fc99e Initial load
duke
parents:
diff changeset
9012 // Or Memory with Register
a61af66fc99e Initial load
duke
parents:
diff changeset
9013 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9014 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9015 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9016 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9017
a61af66fc99e Initial load
duke
parents:
diff changeset
9018 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
9019 format %{ "orl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9020 opcode(0x09); /* Opcode 09 /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
9021 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9022 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9023 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9024
a61af66fc99e Initial load
duke
parents:
diff changeset
9025 // Or Memory with Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
9026 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9027 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9028 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9029 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9030
a61af66fc99e Initial load
duke
parents:
diff changeset
9031 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
9032 format %{ "orl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9033 opcode(0x81, 0x1); /* Opcode 81 /1 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
9034 ins_encode(REX_mem(dst), OpcSE(src),
a61af66fc99e Initial load
duke
parents:
diff changeset
9035 RM_opc_mem(secondary, dst), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9036 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
9037 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9038
a61af66fc99e Initial load
duke
parents:
diff changeset
9039 // Xor Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
9040 // Xor Register with Register
a61af66fc99e Initial load
duke
parents:
diff changeset
9041 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9042 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9043 match(Set dst (XorI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9044 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9045
a61af66fc99e Initial load
duke
parents:
diff changeset
9046 format %{ "xorl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9047 opcode(0x33);
a61af66fc99e Initial load
duke
parents:
diff changeset
9048 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9049 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9050 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9051
403
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
9052 // Xor Register with Immediate -1
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
9053 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
9054 match(Set dst (XorI dst imm));
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
9055
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
9056 format %{ "not $dst" %}
403
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
9057 ins_encode %{
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
9058 __ notl($dst$$Register);
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
9059 %}
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
9060 ins_pipe(ialu_reg);
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
9061 %}
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
9062
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9063 // Xor Register with Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
9064 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9065 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9066 match(Set dst (XorI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9067 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9068
a61af66fc99e Initial load
duke
parents:
diff changeset
9069 format %{ "xorl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9070 opcode(0x81, 0x06); /* Opcode 81 /6 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
9071 ins_encode(OpcSErm(dst, src), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9072 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9073 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9074
a61af66fc99e Initial load
duke
parents:
diff changeset
9075 // Xor Register with Memory
a61af66fc99e Initial load
duke
parents:
diff changeset
9076 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9077 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9078 match(Set dst (XorI dst (LoadI src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9079 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9080
a61af66fc99e Initial load
duke
parents:
diff changeset
9081 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
9082 format %{ "xorl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9083 opcode(0x33);
a61af66fc99e Initial load
duke
parents:
diff changeset
9084 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9085 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
9086 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9087
a61af66fc99e Initial load
duke
parents:
diff changeset
9088 // Xor Memory with Register
a61af66fc99e Initial load
duke
parents:
diff changeset
9089 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9090 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9091 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9092 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9093
a61af66fc99e Initial load
duke
parents:
diff changeset
9094 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
9095 format %{ "xorl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9096 opcode(0x31); /* Opcode 31 /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
9097 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9098 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9099 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9100
a61af66fc99e Initial load
duke
parents:
diff changeset
9101 // Xor Memory with Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
9102 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9103 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9104 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9105 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9106
a61af66fc99e Initial load
duke
parents:
diff changeset
9107 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
9108 format %{ "xorl $dst, $src\t# int" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9109 opcode(0x81, 0x6); /* Opcode 81 /6 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
9110 ins_encode(REX_mem(dst), OpcSE(src),
a61af66fc99e Initial load
duke
parents:
diff changeset
9111 RM_opc_mem(secondary, dst), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9112 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
9113 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9114
a61af66fc99e Initial load
duke
parents:
diff changeset
9115
a61af66fc99e Initial load
duke
parents:
diff changeset
9116 // Long Logical Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
9117
a61af66fc99e Initial load
duke
parents:
diff changeset
9118 // And Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
9119 // And Register with Register
a61af66fc99e Initial load
duke
parents:
diff changeset
9120 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9121 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9122 match(Set dst (AndL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9123 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9124
a61af66fc99e Initial load
duke
parents:
diff changeset
9125 format %{ "andq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9126 opcode(0x23);
a61af66fc99e Initial load
duke
parents:
diff changeset
9127 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9128 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9129 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9130
a61af66fc99e Initial load
duke
parents:
diff changeset
9131 // And Register with Immediate 255
a61af66fc99e Initial load
duke
parents:
diff changeset
9132 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
a61af66fc99e Initial load
duke
parents:
diff changeset
9133 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9134 match(Set dst (AndL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9135
569
2cacccded90f 6805950: Typos in andL_rReg_imm instructions in x86_64.ad
twisti
parents: 558
diff changeset
9136 format %{ "movzbq $dst, $dst\t# long & 0xFF" %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9137 opcode(0x0F, 0xB6);
a61af66fc99e Initial load
duke
parents:
diff changeset
9138 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9139 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9140 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9141
a61af66fc99e Initial load
duke
parents:
diff changeset
9142 // And Register with Immediate 65535
569
2cacccded90f 6805950: Typos in andL_rReg_imm instructions in x86_64.ad
twisti
parents: 558
diff changeset
9143 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9144 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9145 match(Set dst (AndL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9146
a61af66fc99e Initial load
duke
parents:
diff changeset
9147 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9148 opcode(0x0F, 0xB7);
a61af66fc99e Initial load
duke
parents:
diff changeset
9149 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9150 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9151 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9152
a61af66fc99e Initial load
duke
parents:
diff changeset
9153 // And Register with Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
9154 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9155 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9156 match(Set dst (AndL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9157 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9158
a61af66fc99e Initial load
duke
parents:
diff changeset
9159 format %{ "andq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9160 opcode(0x81, 0x04); /* Opcode 81 /4 */
a61af66fc99e Initial load
duke
parents:
diff changeset
9161 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9162 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9163 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9164
a61af66fc99e Initial load
duke
parents:
diff changeset
9165 // And Register with Memory
a61af66fc99e Initial load
duke
parents:
diff changeset
9166 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9167 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9168 match(Set dst (AndL dst (LoadL src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9169 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9170
a61af66fc99e Initial load
duke
parents:
diff changeset
9171 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
9172 format %{ "andq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9173 opcode(0x23);
a61af66fc99e Initial load
duke
parents:
diff changeset
9174 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9175 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
9176 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9177
a61af66fc99e Initial load
duke
parents:
diff changeset
9178 // And Memory with Register
a61af66fc99e Initial load
duke
parents:
diff changeset
9179 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9180 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9181 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9182 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9183
a61af66fc99e Initial load
duke
parents:
diff changeset
9184 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
9185 format %{ "andq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9186 opcode(0x21); /* Opcode 21 /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
9187 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9188 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9189 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9190
a61af66fc99e Initial load
duke
parents:
diff changeset
9191 // And Memory with Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
9192 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9193 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9194 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9195 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9196
a61af66fc99e Initial load
duke
parents:
diff changeset
9197 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
9198 format %{ "andq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9199 opcode(0x81, 0x4); /* Opcode 81 /4 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
9200 ins_encode(REX_mem_wide(dst), OpcSE(src),
a61af66fc99e Initial load
duke
parents:
diff changeset
9201 RM_opc_mem(secondary, dst), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9202 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
9203 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9204
a61af66fc99e Initial load
duke
parents:
diff changeset
9205 // Or Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
9206 // Or Register with Register
a61af66fc99e Initial load
duke
parents:
diff changeset
9207 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9208 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9209 match(Set dst (OrL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9210 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9211
a61af66fc99e Initial load
duke
parents:
diff changeset
9212 format %{ "orq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9213 opcode(0x0B);
a61af66fc99e Initial load
duke
parents:
diff changeset
9214 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9215 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9216 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9217
420
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
9218 // Use any_RegP to match R15 (TLS register) without spilling.
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
9219 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
9220 match(Set dst (OrL dst (CastP2X src)));
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
9221 effect(KILL cr);
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
9222
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
9223 format %{ "orq $dst, $src\t# long" %}
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
9224 opcode(0x0B);
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
9225 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
9226 ins_pipe(ialu_reg_reg);
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
9227 %}
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
9228
a1980da045cc 6462850: generate biased locking code in C2 ideal graph
kvn
parents: 415
diff changeset
9229
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9230 // Or Register with Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
9231 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9232 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9233 match(Set dst (OrL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9234 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9235
a61af66fc99e Initial load
duke
parents:
diff changeset
9236 format %{ "orq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9237 opcode(0x81, 0x01); /* Opcode 81 /1 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
9238 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9239 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9240 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9241
a61af66fc99e Initial load
duke
parents:
diff changeset
9242 // Or Register with Memory
a61af66fc99e Initial load
duke
parents:
diff changeset
9243 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9244 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9245 match(Set dst (OrL dst (LoadL src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9246 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9247
a61af66fc99e Initial load
duke
parents:
diff changeset
9248 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
9249 format %{ "orq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9250 opcode(0x0B);
a61af66fc99e Initial load
duke
parents:
diff changeset
9251 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9252 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
9253 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9254
a61af66fc99e Initial load
duke
parents:
diff changeset
9255 // Or Memory with Register
a61af66fc99e Initial load
duke
parents:
diff changeset
9256 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9257 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9258 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9259 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9260
a61af66fc99e Initial load
duke
parents:
diff changeset
9261 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
9262 format %{ "orq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9263 opcode(0x09); /* Opcode 09 /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
9264 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9265 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9266 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9267
a61af66fc99e Initial load
duke
parents:
diff changeset
9268 // Or Memory with Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
9269 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9270 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9271 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9272 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9273
a61af66fc99e Initial load
duke
parents:
diff changeset
9274 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
9275 format %{ "orq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9276 opcode(0x81, 0x1); /* Opcode 81 /1 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
9277 ins_encode(REX_mem_wide(dst), OpcSE(src),
a61af66fc99e Initial load
duke
parents:
diff changeset
9278 RM_opc_mem(secondary, dst), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9279 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
9280 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9281
a61af66fc99e Initial load
duke
parents:
diff changeset
9282 // Xor Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
9283 // Xor Register with Register
a61af66fc99e Initial load
duke
parents:
diff changeset
9284 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9285 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9286 match(Set dst (XorL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9287 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9288
a61af66fc99e Initial load
duke
parents:
diff changeset
9289 format %{ "xorq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9290 opcode(0x33);
a61af66fc99e Initial load
duke
parents:
diff changeset
9291 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9292 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9293 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9294
403
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
9295 // Xor Register with Immediate -1
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
9296 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
9297 match(Set dst (XorL dst imm));
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
9298
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
9299 format %{ "notq $dst" %}
403
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
9300 ins_encode %{
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
9301 __ notq($dst$$Register);
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
9302 %}
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
9303 ins_pipe(ialu_reg);
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
9304 %}
b744678d4d71 6752257: Use NOT instead of XOR -1 on x86
rasbold
parents: 304
diff changeset
9305
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9306 // Xor Register with Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
9307 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9308 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9309 match(Set dst (XorL dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9310 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9311
a61af66fc99e Initial load
duke
parents:
diff changeset
9312 format %{ "xorq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9313 opcode(0x81, 0x06); /* Opcode 81 /6 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
9314 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9315 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9316 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9317
a61af66fc99e Initial load
duke
parents:
diff changeset
9318 // Xor Register with Memory
a61af66fc99e Initial load
duke
parents:
diff changeset
9319 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9320 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9321 match(Set dst (XorL dst (LoadL src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9322 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9323
a61af66fc99e Initial load
duke
parents:
diff changeset
9324 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
9325 format %{ "xorq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9326 opcode(0x33);
a61af66fc99e Initial load
duke
parents:
diff changeset
9327 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9328 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
9329 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9330
a61af66fc99e Initial load
duke
parents:
diff changeset
9331 // Xor Memory with Register
a61af66fc99e Initial load
duke
parents:
diff changeset
9332 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9333 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9334 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9335 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9336
a61af66fc99e Initial load
duke
parents:
diff changeset
9337 ins_cost(150);
a61af66fc99e Initial load
duke
parents:
diff changeset
9338 format %{ "xorq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9339 opcode(0x31); /* Opcode 31 /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
9340 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9341 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9342 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9343
a61af66fc99e Initial load
duke
parents:
diff changeset
9344 // Xor Memory with Immediate
a61af66fc99e Initial load
duke
parents:
diff changeset
9345 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9346 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9347 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9348 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9349
a61af66fc99e Initial load
duke
parents:
diff changeset
9350 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
9351 format %{ "xorq $dst, $src\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9352 opcode(0x81, 0x6); /* Opcode 81 /6 id */
a61af66fc99e Initial load
duke
parents:
diff changeset
9353 ins_encode(REX_mem_wide(dst), OpcSE(src),
a61af66fc99e Initial load
duke
parents:
diff changeset
9354 RM_opc_mem(secondary, dst), Con8or32(src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9355 ins_pipe(ialu_mem_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
9356 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9357
a61af66fc99e Initial load
duke
parents:
diff changeset
9358 // Convert Int to Boolean
a61af66fc99e Initial load
duke
parents:
diff changeset
9359 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9360 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9361 match(Set dst (Conv2B src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9362 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9363
a61af66fc99e Initial load
duke
parents:
diff changeset
9364 format %{ "testl $src, $src\t# ci2b\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9365 "setnz $dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9366 "movzbl $dst, $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9367 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
a61af66fc99e Initial load
duke
parents:
diff changeset
9368 setNZ_reg(dst),
a61af66fc99e Initial load
duke
parents:
diff changeset
9369 REX_reg_breg(dst, dst), // movzbl
a61af66fc99e Initial load
duke
parents:
diff changeset
9370 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9371 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
9372 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9373
a61af66fc99e Initial load
duke
parents:
diff changeset
9374 // Convert Pointer to Boolean
a61af66fc99e Initial load
duke
parents:
diff changeset
9375 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9376 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9377 match(Set dst (Conv2B src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9378 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9379
a61af66fc99e Initial load
duke
parents:
diff changeset
9380 format %{ "testq $src, $src\t# cp2b\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9381 "setnz $dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9382 "movzbl $dst, $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9383 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
a61af66fc99e Initial load
duke
parents:
diff changeset
9384 setNZ_reg(dst),
a61af66fc99e Initial load
duke
parents:
diff changeset
9385 REX_reg_breg(dst, dst), // movzbl
a61af66fc99e Initial load
duke
parents:
diff changeset
9386 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9387 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
9388 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9389
a61af66fc99e Initial load
duke
parents:
diff changeset
9390 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9391 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9392 match(Set dst (CmpLTMask p q));
a61af66fc99e Initial load
duke
parents:
diff changeset
9393 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9394
9154
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9395 ins_cost(400);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9396 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9397 "setlt $dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9398 "movzbl $dst, $dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9399 "negl $dst" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9400 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
a61af66fc99e Initial load
duke
parents:
diff changeset
9401 setLT_reg(dst),
a61af66fc99e Initial load
duke
parents:
diff changeset
9402 REX_reg_breg(dst, dst), // movzbl
a61af66fc99e Initial load
duke
parents:
diff changeset
9403 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
a61af66fc99e Initial load
duke
parents:
diff changeset
9404 neg_reg(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9405 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
9406 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9407
a61af66fc99e Initial load
duke
parents:
diff changeset
9408 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9409 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9410 match(Set dst (CmpLTMask dst zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
9411 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9412
9154
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9413 ins_cost(100);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9414 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
9154
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9415 ins_encode %{
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9416 __ sarl($dst$$Register, 31);
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9417 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9418 ins_pipe(ialu_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
9419 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9420
9154
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9421 /* Better to save a register than avoid a branch */
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9422 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9423 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9424 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9154
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9425 effect(KILL cr);
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9426 ins_cost(300);
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9427 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t"
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9428 "jge done\n\t"
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9429 "addl $p,$y\n"
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9430 "done: " %}
3738
c7c81f18c834 7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
kvn
parents: 2404
diff changeset
9431 ins_encode %{
c7c81f18c834 7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
kvn
parents: 2404
diff changeset
9432 Register Rp = $p$$Register;
c7c81f18c834 7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
kvn
parents: 2404
diff changeset
9433 Register Rq = $q$$Register;
c7c81f18c834 7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
kvn
parents: 2404
diff changeset
9434 Register Ry = $y$$Register;
9154
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9435 Label done;
3738
c7c81f18c834 7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
kvn
parents: 2404
diff changeset
9436 __ subl(Rp, Rq);
9154
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9437 __ jccb(Assembler::greaterEqual, done);
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9438 __ addl(Rp, Ry);
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9439 __ bind(done);
3738
c7c81f18c834 7048332: Cadd_cmpLTMask doesn't handle 64-bit tmp register properly
kvn
parents: 2404
diff changeset
9440 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9441 ins_pipe(pipe_cmplt);
a61af66fc99e Initial load
duke
parents:
diff changeset
9442 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9443
9154
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9444 /* Better to save a register than avoid a branch */
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9445 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9446 %{
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9447 match(Set y (AndI (CmpLTMask p q) y));
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9448 effect(KILL cr);
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9449
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9450 ins_cost(300);
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9451
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9452 format %{ "cmpl $p, $q\t# and_cmpLTMask\n\t"
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9453 "jlt done\n\t"
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9454 "xorl $y, $y\n"
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9455 "done: " %}
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9456 ins_encode %{
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9457 Register Rp = $p$$Register;
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9458 Register Rq = $q$$Register;
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9459 Register Ry = $y$$Register;
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9460 Label done;
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9461 __ cmpl(Rp, Rq);
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9462 __ jccb(Assembler::less, done);
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9463 __ xorl(Ry, Ry);
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9464 __ bind(done);
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9465 %}
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9466 ins_pipe(pipe_cmplt);
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9467 %}
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9468
886d1fd67dc3 6443505: Ideal() function for CmpLTMask
drchase
parents: 9062
diff changeset
9469
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9470 //---------- FP Instructions------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
9471
a61af66fc99e Initial load
duke
parents:
diff changeset
9472 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
a61af66fc99e Initial load
duke
parents:
diff changeset
9473 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9474 match(Set cr (CmpF src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
9475
a61af66fc99e Initial load
duke
parents:
diff changeset
9476 ins_cost(145);
a61af66fc99e Initial load
duke
parents:
diff changeset
9477 format %{ "ucomiss $src1, $src2\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9478 "jnp,s exit\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9479 "pushfq\t# saw NaN, set CF\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9480 "andq [rsp], #0xffffff2b\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9481 "popfq\n"
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9482 "exit:" %}
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9483 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9484 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9485 emit_cmpfp_fixup(_masm);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9486 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9487 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
9488 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9489
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9490 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9491 match(Set cr (CmpF src1 src2));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9492
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9493 ins_cost(100);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9494 format %{ "ucomiss $src1, $src2" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9495 ins_encode %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9496 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9497 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9498 ins_pipe(pipe_slow);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9499 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9500
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9501 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
a61af66fc99e Initial load
duke
parents:
diff changeset
9502 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9503 match(Set cr (CmpF src1 (LoadF src2)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9504
a61af66fc99e Initial load
duke
parents:
diff changeset
9505 ins_cost(145);
a61af66fc99e Initial load
duke
parents:
diff changeset
9506 format %{ "ucomiss $src1, $src2\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9507 "jnp,s exit\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9508 "pushfq\t# saw NaN, set CF\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9509 "andq [rsp], #0xffffff2b\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9510 "popfq\n"
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9511 "exit:" %}
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9512 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9513 __ ucomiss($src1$$XMMRegister, $src2$$Address);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9514 emit_cmpfp_fixup(_masm);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9515 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9516 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
9517 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9518
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9519 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9520 match(Set cr (CmpF src1 (LoadF src2)));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9521
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9522 ins_cost(100);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9523 format %{ "ucomiss $src1, $src2" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9524 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9525 __ ucomiss($src1$$XMMRegister, $src2$$Address);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9526 %}
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9527 ins_pipe(pipe_slow);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9528 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9529
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9530 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9531 match(Set cr (CmpF src con));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9532
a61af66fc99e Initial load
duke
parents:
diff changeset
9533 ins_cost(145);
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9534 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9535 "jnp,s exit\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9536 "pushfq\t# saw NaN, set CF\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9537 "andq [rsp], #0xffffff2b\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9538 "popfq\n"
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9539 "exit:" %}
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9540 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9541 __ ucomiss($src$$XMMRegister, $constantaddress($con));
3783
de6a837d75cf 7056380: VM crashes with SIGSEGV in compiled code
never
parents: 3738
diff changeset
9542 emit_cmpfp_fixup(_masm);
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9543 %}
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9544 ins_pipe(pipe_slow);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9545 %}
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9546
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9547 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9548 match(Set cr (CmpF src con));
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9549 ins_cost(100);
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9550 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9551 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9552 __ ucomiss($src$$XMMRegister, $constantaddress($con));
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9553 %}
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9554 ins_pipe(pipe_slow);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9555 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9556
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9557 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
a61af66fc99e Initial load
duke
parents:
diff changeset
9558 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9559 match(Set cr (CmpD src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
9560
a61af66fc99e Initial load
duke
parents:
diff changeset
9561 ins_cost(145);
a61af66fc99e Initial load
duke
parents:
diff changeset
9562 format %{ "ucomisd $src1, $src2\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9563 "jnp,s exit\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9564 "pushfq\t# saw NaN, set CF\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9565 "andq [rsp], #0xffffff2b\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9566 "popfq\n"
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9567 "exit:" %}
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9568 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9569 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9570 emit_cmpfp_fixup(_masm);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9571 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9572 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
9573 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9574
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9575 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9576 match(Set cr (CmpD src1 src2));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9577
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9578 ins_cost(100);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9579 format %{ "ucomisd $src1, $src2 test" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9580 ins_encode %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9581 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9582 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9583 ins_pipe(pipe_slow);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9584 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9585
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9586 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
a61af66fc99e Initial load
duke
parents:
diff changeset
9587 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9588 match(Set cr (CmpD src1 (LoadD src2)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9589
a61af66fc99e Initial load
duke
parents:
diff changeset
9590 ins_cost(145);
a61af66fc99e Initial load
duke
parents:
diff changeset
9591 format %{ "ucomisd $src1, $src2\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9592 "jnp,s exit\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9593 "pushfq\t# saw NaN, set CF\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9594 "andq [rsp], #0xffffff2b\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9595 "popfq\n"
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9596 "exit:" %}
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9597 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9598 __ ucomisd($src1$$XMMRegister, $src2$$Address);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9599 emit_cmpfp_fixup(_masm);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9600 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9601 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
9602 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9603
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9604 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9605 match(Set cr (CmpD src1 (LoadD src2)));
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9606
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9607 ins_cost(100);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9608 format %{ "ucomisd $src1, $src2" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9609 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9610 __ ucomisd($src1$$XMMRegister, $src2$$Address);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9611 %}
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9612 ins_pipe(pipe_slow);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9613 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9614
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9615 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9616 match(Set cr (CmpD src con));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9617
a61af66fc99e Initial load
duke
parents:
diff changeset
9618 ins_cost(145);
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9619 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9620 "jnp,s exit\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9621 "pushfq\t# saw NaN, set CF\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9622 "andq [rsp], #0xffffff2b\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9623 "popfq\n"
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9624 "exit:" %}
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9625 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9626 __ ucomisd($src$$XMMRegister, $constantaddress($con));
3783
de6a837d75cf 7056380: VM crashes with SIGSEGV in compiled code
never
parents: 3738
diff changeset
9627 emit_cmpfp_fixup(_masm);
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9628 %}
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9629 ins_pipe(pipe_slow);
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9630 %}
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9631
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9632 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9633 match(Set cr (CmpD src con));
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9634 ins_cost(100);
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9635 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9636 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9637 __ ucomisd($src$$XMMRegister, $constantaddress($con));
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9638 %}
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9639 ins_pipe(pipe_slow);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9640 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
9641
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9642 // Compare into -1,0,1
a61af66fc99e Initial load
duke
parents:
diff changeset
9643 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9644 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9645 match(Set dst (CmpF3 src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
9646 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9647
a61af66fc99e Initial load
duke
parents:
diff changeset
9648 ins_cost(275);
a61af66fc99e Initial load
duke
parents:
diff changeset
9649 format %{ "ucomiss $src1, $src2\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9650 "movl $dst, #-1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9651 "jp,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9652 "jb,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9653 "setne $dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9654 "movzbl $dst, $dst\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
9655 "done:" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9656 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9657 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9658 emit_cmpfp3(_masm, $dst$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9659 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9660 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
9661 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9662
a61af66fc99e Initial load
duke
parents:
diff changeset
9663 // Compare into -1,0,1
a61af66fc99e Initial load
duke
parents:
diff changeset
9664 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9665 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9666 match(Set dst (CmpF3 src1 (LoadF src2)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9667 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9668
a61af66fc99e Initial load
duke
parents:
diff changeset
9669 ins_cost(275);
a61af66fc99e Initial load
duke
parents:
diff changeset
9670 format %{ "ucomiss $src1, $src2\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9671 "movl $dst, #-1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9672 "jp,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9673 "jb,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9674 "setne $dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9675 "movzbl $dst, $dst\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
9676 "done:" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9677 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9678 __ ucomiss($src1$$XMMRegister, $src2$$Address);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9679 emit_cmpfp3(_masm, $dst$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9680 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9681 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
9682 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9683
a61af66fc99e Initial load
duke
parents:
diff changeset
9684 // Compare into -1,0,1
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9685 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9686 match(Set dst (CmpF3 src con));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9687 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9688
a61af66fc99e Initial load
duke
parents:
diff changeset
9689 ins_cost(275);
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9690 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9691 "movl $dst, #-1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9692 "jp,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9693 "jb,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9694 "setne $dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9695 "movzbl $dst, $dst\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
9696 "done:" %}
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9697 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9698 __ ucomiss($src$$XMMRegister, $constantaddress($con));
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9699 emit_cmpfp3(_masm, $dst$$Register);
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9700 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9701 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
9702 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9703
a61af66fc99e Initial load
duke
parents:
diff changeset
9704 // Compare into -1,0,1
a61af66fc99e Initial load
duke
parents:
diff changeset
9705 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9706 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9707 match(Set dst (CmpD3 src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
9708 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9709
a61af66fc99e Initial load
duke
parents:
diff changeset
9710 ins_cost(275);
a61af66fc99e Initial load
duke
parents:
diff changeset
9711 format %{ "ucomisd $src1, $src2\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9712 "movl $dst, #-1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9713 "jp,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9714 "jb,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9715 "setne $dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9716 "movzbl $dst, $dst\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
9717 "done:" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9718 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9719 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9720 emit_cmpfp3(_masm, $dst$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9721 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9722 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
9723 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9724
a61af66fc99e Initial load
duke
parents:
diff changeset
9725 // Compare into -1,0,1
a61af66fc99e Initial load
duke
parents:
diff changeset
9726 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9727 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9728 match(Set dst (CmpD3 src1 (LoadD src2)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9729 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9730
a61af66fc99e Initial load
duke
parents:
diff changeset
9731 ins_cost(275);
a61af66fc99e Initial load
duke
parents:
diff changeset
9732 format %{ "ucomisd $src1, $src2\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9733 "movl $dst, #-1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9734 "jp,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9735 "jb,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9736 "setne $dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9737 "movzbl $dst, $dst\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
9738 "done:" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9739 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9740 __ ucomisd($src1$$XMMRegister, $src2$$Address);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9741 emit_cmpfp3(_masm, $dst$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9742 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9743 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
9744 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9745
a61af66fc99e Initial load
duke
parents:
diff changeset
9746 // Compare into -1,0,1
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9747 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9748 match(Set dst (CmpD3 src con));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9749 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9750
a61af66fc99e Initial load
duke
parents:
diff changeset
9751 ins_cost(275);
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9752 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9753 "movl $dst, #-1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9754 "jp,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9755 "jb,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9756 "setne $dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9757 "movzbl $dst, $dst\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
9758 "done:" %}
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9759 ins_encode %{
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9760 __ ucomisd($src$$XMMRegister, $constantaddress($con));
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9761 emit_cmpfp3(_masm, $dst$$Register);
2008
2f644f85485d 6961690: load oops from constant table on SPARC
twisti
parents: 1914
diff changeset
9762 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9763 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
9764 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9765
a61af66fc99e Initial load
duke
parents:
diff changeset
9766 // -----------Trig and Trancendental Instructions------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
9767 instruct cosD_reg(regD dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9768 match(Set dst (CosD dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9769
a61af66fc99e Initial load
duke
parents:
diff changeset
9770 format %{ "dcos $dst\n\t" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9771 opcode(0xD9, 0xFF);
a61af66fc99e Initial load
duke
parents:
diff changeset
9772 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
a61af66fc99e Initial load
duke
parents:
diff changeset
9773 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
9774 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9775
a61af66fc99e Initial load
duke
parents:
diff changeset
9776 instruct sinD_reg(regD dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9777 match(Set dst (SinD dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9778
a61af66fc99e Initial load
duke
parents:
diff changeset
9779 format %{ "dsin $dst\n\t" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9780 opcode(0xD9, 0xFE);
a61af66fc99e Initial load
duke
parents:
diff changeset
9781 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
a61af66fc99e Initial load
duke
parents:
diff changeset
9782 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
9783 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9784
a61af66fc99e Initial load
duke
parents:
diff changeset
9785 instruct tanD_reg(regD dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9786 match(Set dst (TanD dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9787
a61af66fc99e Initial load
duke
parents:
diff changeset
9788 format %{ "dtan $dst\n\t" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9789 ins_encode( Push_SrcXD(dst),
a61af66fc99e Initial load
duke
parents:
diff changeset
9790 Opcode(0xD9), Opcode(0xF2), //fptan
a61af66fc99e Initial load
duke
parents:
diff changeset
9791 Opcode(0xDD), Opcode(0xD8), //fstp st
a61af66fc99e Initial load
duke
parents:
diff changeset
9792 Push_ResultXD(dst) );
a61af66fc99e Initial load
duke
parents:
diff changeset
9793 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
9794 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9795
a61af66fc99e Initial load
duke
parents:
diff changeset
9796 instruct log10D_reg(regD dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9797 // The source and result Double operands in XMM registers
a61af66fc99e Initial load
duke
parents:
diff changeset
9798 match(Set dst (Log10D dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9799 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
a61af66fc99e Initial load
duke
parents:
diff changeset
9800 // fyl2x ; compute log_10(2) * log_2(x)
a61af66fc99e Initial load
duke
parents:
diff changeset
9801 format %{ "fldlg2\t\t\t#Log10\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9802 "fyl2x\t\t\t# Q=Log10*Log_2(x)\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9803 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9804 ins_encode(Opcode(0xD9), Opcode(0xEC), // fldlg2
a61af66fc99e Initial load
duke
parents:
diff changeset
9805 Push_SrcXD(dst),
a61af66fc99e Initial load
duke
parents:
diff changeset
9806 Opcode(0xD9), Opcode(0xF1), // fyl2x
a61af66fc99e Initial load
duke
parents:
diff changeset
9807 Push_ResultXD(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9808
a61af66fc99e Initial load
duke
parents:
diff changeset
9809 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
9810 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9811
a61af66fc99e Initial load
duke
parents:
diff changeset
9812 instruct logD_reg(regD dst) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9813 // The source and result Double operands in XMM registers
a61af66fc99e Initial load
duke
parents:
diff changeset
9814 match(Set dst (LogD dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9815 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
a61af66fc99e Initial load
duke
parents:
diff changeset
9816 // fyl2x ; compute log_e(2) * log_2(x)
a61af66fc99e Initial load
duke
parents:
diff changeset
9817 format %{ "fldln2\t\t\t#Log_e\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9818 "fyl2x\t\t\t# Q=Log_e*Log_2(x)\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9819 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9820 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
a61af66fc99e Initial load
duke
parents:
diff changeset
9821 Push_SrcXD(dst),
a61af66fc99e Initial load
duke
parents:
diff changeset
9822 Opcode(0xD9), Opcode(0xF1), // fyl2x
a61af66fc99e Initial load
duke
parents:
diff changeset
9823 Push_ResultXD(dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9824 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
9825 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9826
6084
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9827 instruct powD_reg(regD dst, regD src0, regD src1, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9828 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9829 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9830 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9831 ins_encode %{
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9832 __ subptr(rsp, 8);
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9833 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9834 __ fld_d(Address(rsp, 0));
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9835 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9836 __ fld_d(Address(rsp, 0));
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9837 __ fast_pow();
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9838 __ fstp_d(Address(rsp, 0));
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9839 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9840 __ addptr(rsp, 8);
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9841 %}
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9842 ins_pipe( pipe_slow );
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9843 %}
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9844
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9845 instruct expD_reg(regD dst, regD src, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9846 match(Set dst (ExpD src));
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9847 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9848 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9849 ins_encode %{
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9850 __ subptr(rsp, 8);
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9851 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9852 __ fld_d(Address(rsp, 0));
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9853 __ fast_exp();
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9854 __ fstp_d(Address(rsp, 0));
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9855 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9856 __ addptr(rsp, 8);
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9857 %}
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9858 ins_pipe( pipe_slow );
6759698e3140 7133857: exp() and pow() should use the x87 ISA on x86
roland
parents: 5984
diff changeset
9859 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9860
a61af66fc99e Initial load
duke
parents:
diff changeset
9861 //----------Arithmetic Conversion Instructions---------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
9862
a61af66fc99e Initial load
duke
parents:
diff changeset
9863 instruct roundFloat_nop(regF dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
9864 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9865 match(Set dst (RoundFloat dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9866
a61af66fc99e Initial load
duke
parents:
diff changeset
9867 ins_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
9868 ins_encode();
a61af66fc99e Initial load
duke
parents:
diff changeset
9869 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
9870 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9871
a61af66fc99e Initial load
duke
parents:
diff changeset
9872 instruct roundDouble_nop(regD dst)
a61af66fc99e Initial load
duke
parents:
diff changeset
9873 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9874 match(Set dst (RoundDouble dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
9875
a61af66fc99e Initial load
duke
parents:
diff changeset
9876 ins_cost(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
9877 ins_encode();
a61af66fc99e Initial load
duke
parents:
diff changeset
9878 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
9879 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9880
a61af66fc99e Initial load
duke
parents:
diff changeset
9881 instruct convF2D_reg_reg(regD dst, regF src)
a61af66fc99e Initial load
duke
parents:
diff changeset
9882 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9883 match(Set dst (ConvF2D src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9884
a61af66fc99e Initial load
duke
parents:
diff changeset
9885 format %{ "cvtss2sd $dst, $src" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9886 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9887 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9888 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9889 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
9890 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9891
a61af66fc99e Initial load
duke
parents:
diff changeset
9892 instruct convF2D_reg_mem(regD dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
9893 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9894 match(Set dst (ConvF2D (LoadF src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9895
a61af66fc99e Initial load
duke
parents:
diff changeset
9896 format %{ "cvtss2sd $dst, $src" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9897 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9898 __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9899 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9900 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
9901 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9902
a61af66fc99e Initial load
duke
parents:
diff changeset
9903 instruct convD2F_reg_reg(regF dst, regD src)
a61af66fc99e Initial load
duke
parents:
diff changeset
9904 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9905 match(Set dst (ConvD2F src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9906
a61af66fc99e Initial load
duke
parents:
diff changeset
9907 format %{ "cvtsd2ss $dst, $src" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9908 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9909 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9910 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9911 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
9912 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9913
a61af66fc99e Initial load
duke
parents:
diff changeset
9914 instruct convD2F_reg_mem(regF dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
9915 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9916 match(Set dst (ConvD2F (LoadD src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
9917
a61af66fc99e Initial load
duke
parents:
diff changeset
9918 format %{ "cvtsd2ss $dst, $src" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9919 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9920 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9921 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9922 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
9923 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9924
a61af66fc99e Initial load
duke
parents:
diff changeset
9925 // XXX do mem variants
a61af66fc99e Initial load
duke
parents:
diff changeset
9926 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9927 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9928 match(Set dst (ConvF2I src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9929 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9930
a61af66fc99e Initial load
duke
parents:
diff changeset
9931 format %{ "cvttss2sil $dst, $src\t# f2i\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9932 "cmpl $dst, #0x80000000\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9933 "jne,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9934 "subq rsp, #8\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9935 "movss [rsp], $src\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9936 "call f2i_fixup\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9937 "popq $dst\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
9938 "done: "%}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9939 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9940 Label done;
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9941 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9942 __ cmpl($dst$$Register, 0x80000000);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9943 __ jccb(Assembler::notEqual, done);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9944 __ subptr(rsp, 8);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9945 __ movflt(Address(rsp, 0), $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9946 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9947 __ pop($dst$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9948 __ bind(done);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9949 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9950 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
9951 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9952
a61af66fc99e Initial load
duke
parents:
diff changeset
9953 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9954 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9955 match(Set dst (ConvF2L src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9956 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9957
a61af66fc99e Initial load
duke
parents:
diff changeset
9958 format %{ "cvttss2siq $dst, $src\t# f2l\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9959 "cmpq $dst, [0x8000000000000000]\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9960 "jne,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9961 "subq rsp, #8\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9962 "movss [rsp], $src\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9963 "call f2l_fixup\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9964 "popq $dst\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
9965 "done: "%}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9966 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9967 Label done;
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9968 __ cvttss2siq($dst$$Register, $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9969 __ cmp64($dst$$Register,
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9970 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9971 __ jccb(Assembler::notEqual, done);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9972 __ subptr(rsp, 8);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9973 __ movflt(Address(rsp, 0), $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9974 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9975 __ pop($dst$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9976 __ bind(done);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9977 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
9978 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
9979 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
9980
a61af66fc99e Initial load
duke
parents:
diff changeset
9981 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
9982 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
9983 match(Set dst (ConvD2I src));
a61af66fc99e Initial load
duke
parents:
diff changeset
9984 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
9985
a61af66fc99e Initial load
duke
parents:
diff changeset
9986 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9987 "cmpl $dst, #0x80000000\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9988 "jne,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9989 "subq rsp, #8\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9990 "movsd [rsp], $src\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9991 "call d2i_fixup\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
9992 "popq $dst\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
9993 "done: "%}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9994 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9995 Label done;
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9996 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9997 __ cmpl($dst$$Register, 0x80000000);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9998 __ jccb(Assembler::notEqual, done);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
9999 __ subptr(rsp, 8);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10000 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10001 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10002 __ pop($dst$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10003 __ bind(done);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10004 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10005 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10006 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10007
a61af66fc99e Initial load
duke
parents:
diff changeset
10008 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
10009 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10010 match(Set dst (ConvD2L src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10011 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10012
a61af66fc99e Initial load
duke
parents:
diff changeset
10013 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10014 "cmpq $dst, [0x8000000000000000]\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10015 "jne,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10016 "subq rsp, #8\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10017 "movsd [rsp], $src\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10018 "call d2l_fixup\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10019 "popq $dst\n"
a61af66fc99e Initial load
duke
parents:
diff changeset
10020 "done: "%}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10021 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10022 Label done;
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10023 __ cvttsd2siq($dst$$Register, $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10024 __ cmp64($dst$$Register,
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10025 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10026 __ jccb(Assembler::notEqual, done);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10027 __ subptr(rsp, 8);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10028 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10029 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10030 __ pop($dst$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10031 __ bind(done);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10032 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10033 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10034 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10035
a61af66fc99e Initial load
duke
parents:
diff changeset
10036 instruct convI2F_reg_reg(regF dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
10037 %{
71
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
10038 predicate(!UseXmmI2F);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10039 match(Set dst (ConvI2F src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10040
a61af66fc99e Initial load
duke
parents:
diff changeset
10041 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10042 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10043 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10044 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10045 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10046 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10047
a61af66fc99e Initial load
duke
parents:
diff changeset
10048 instruct convI2F_reg_mem(regF dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
10049 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10050 match(Set dst (ConvI2F (LoadI src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
10051
a61af66fc99e Initial load
duke
parents:
diff changeset
10052 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10053 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10054 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10055 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10056 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10057 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10058
a61af66fc99e Initial load
duke
parents:
diff changeset
10059 instruct convI2D_reg_reg(regD dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
10060 %{
71
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
10061 predicate(!UseXmmI2D);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10062 match(Set dst (ConvI2D src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10063
a61af66fc99e Initial load
duke
parents:
diff changeset
10064 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10065 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10066 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10067 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10068 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10069 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10070
a61af66fc99e Initial load
duke
parents:
diff changeset
10071 instruct convI2D_reg_mem(regD dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
10072 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10073 match(Set dst (ConvI2D (LoadI src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
10074
a61af66fc99e Initial load
duke
parents:
diff changeset
10075 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10076 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10077 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10078 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10079 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10080 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10081
71
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
10082 instruct convXI2F_reg(regF dst, rRegI src)
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
10083 %{
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
10084 predicate(UseXmmI2F);
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
10085 match(Set dst (ConvI2F src));
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
10086
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
10087 format %{ "movdl $dst, $src\n\t"
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
10088 "cvtdq2psl $dst, $dst\t# i2f" %}
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
10089 ins_encode %{
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
10090 __ movdl($dst$$XMMRegister, $src$$Register);
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
10091 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
10092 %}
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
10093 ins_pipe(pipe_slow); // XXX
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
10094 %}
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
10095
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
10096 instruct convXI2D_reg(regD dst, rRegI src)
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
10097 %{
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
10098 predicate(UseXmmI2D);
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
10099 match(Set dst (ConvI2D src));
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
10100
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
10101 format %{ "movdl $dst, $src\n\t"
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
10102 "cvtdq2pdl $dst, $dst\t# i2d" %}
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
10103 ins_encode %{
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
10104 __ movdl($dst$$XMMRegister, $src$$Register);
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
10105 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
10106 %}
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
10107 ins_pipe(pipe_slow); // XXX
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
10108 %}
3d62cb85208d 6662967: Optimize I2D conversion on new x86
kvn
parents: 0
diff changeset
10109
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10110 instruct convL2F_reg_reg(regF dst, rRegL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
10111 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10112 match(Set dst (ConvL2F src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10113
a61af66fc99e Initial load
duke
parents:
diff changeset
10114 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10115 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10116 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10117 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10118 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10119 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10120
a61af66fc99e Initial load
duke
parents:
diff changeset
10121 instruct convL2F_reg_mem(regF dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
10122 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10123 match(Set dst (ConvL2F (LoadL src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
10124
a61af66fc99e Initial load
duke
parents:
diff changeset
10125 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10126 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10127 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10128 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10129 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10130 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10131
a61af66fc99e Initial load
duke
parents:
diff changeset
10132 instruct convL2D_reg_reg(regD dst, rRegL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
10133 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10134 match(Set dst (ConvL2D src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10135
a61af66fc99e Initial load
duke
parents:
diff changeset
10136 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10137 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10138 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10139 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10140 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10141 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10142
a61af66fc99e Initial load
duke
parents:
diff changeset
10143 instruct convL2D_reg_mem(regD dst, memory src)
a61af66fc99e Initial load
duke
parents:
diff changeset
10144 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10145 match(Set dst (ConvL2D (LoadL src)));
a61af66fc99e Initial load
duke
parents:
diff changeset
10146
a61af66fc99e Initial load
duke
parents:
diff changeset
10147 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10148 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10149 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10150 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10151 ins_pipe(pipe_slow); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10152 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10153
a61af66fc99e Initial load
duke
parents:
diff changeset
10154 instruct convI2L_reg_reg(rRegL dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
10155 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10156 match(Set dst (ConvI2L src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10157
a61af66fc99e Initial load
duke
parents:
diff changeset
10158 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
10159 format %{ "movslq $dst, $src\t# i2l" %}
824
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
10160 ins_encode %{
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
10161 __ movslq($dst$$Register, $src$$Register);
18a08a7e16b5 5057225: Remove useless I2L conversions
twisti
parents: 785
diff changeset
10162 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10163 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
10164 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10165
a61af66fc99e Initial load
duke
parents:
diff changeset
10166 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
10167 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10168 // match(Set dst (ConvI2L src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10169 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
a61af66fc99e Initial load
duke
parents:
diff changeset
10170 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
a61af66fc99e Initial load
duke
parents:
diff changeset
10171 // predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
a61af66fc99e Initial load
duke
parents:
diff changeset
10172 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
a61af66fc99e Initial load
duke
parents:
diff changeset
10173 // ((const TypeNode*) n)->type()->is_long()->_lo ==
a61af66fc99e Initial load
duke
parents:
diff changeset
10174 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
a61af66fc99e Initial load
duke
parents:
diff changeset
10175
a61af66fc99e Initial load
duke
parents:
diff changeset
10176 // format %{ "movl $dst, $src\t# unsigned i2l" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10177 // ins_encode(enc_copy(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10178 // // opcode(0x63); // needs REX.W
a61af66fc99e Initial load
duke
parents:
diff changeset
10179 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10180 // ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
10181 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10182
a61af66fc99e Initial load
duke
parents:
diff changeset
10183 // Zero-extend convert int to long
a61af66fc99e Initial load
duke
parents:
diff changeset
10184 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
a61af66fc99e Initial load
duke
parents:
diff changeset
10185 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10186 match(Set dst (AndL (ConvI2L src) mask));
a61af66fc99e Initial load
duke
parents:
diff changeset
10187
a61af66fc99e Initial load
duke
parents:
diff changeset
10188 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10189 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10190 if ($dst$$reg != $src$$reg) {
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10191 __ movl($dst$$Register, $src$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10192 }
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10193 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10194 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
10195 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10196
a61af66fc99e Initial load
duke
parents:
diff changeset
10197 // Zero-extend convert int to long
a61af66fc99e Initial load
duke
parents:
diff changeset
10198 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
a61af66fc99e Initial load
duke
parents:
diff changeset
10199 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10200 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
a61af66fc99e Initial load
duke
parents:
diff changeset
10201
a61af66fc99e Initial load
duke
parents:
diff changeset
10202 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10203 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10204 __ movl($dst$$Register, $src$$Address);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10205 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10206 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
10207 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10208
a61af66fc99e Initial load
duke
parents:
diff changeset
10209 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
a61af66fc99e Initial load
duke
parents:
diff changeset
10210 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10211 match(Set dst (AndL src mask));
a61af66fc99e Initial load
duke
parents:
diff changeset
10212
a61af66fc99e Initial load
duke
parents:
diff changeset
10213 format %{ "movl $dst, $src\t# zero-extend long" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10214 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10215 __ movl($dst$$Register, $src$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10216 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10217 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
10218 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10219
a61af66fc99e Initial load
duke
parents:
diff changeset
10220 instruct convL2I_reg_reg(rRegI dst, rRegL src)
a61af66fc99e Initial load
duke
parents:
diff changeset
10221 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10222 match(Set dst (ConvL2I src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10223
a61af66fc99e Initial load
duke
parents:
diff changeset
10224 format %{ "movl $dst, $src\t# l2i" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10225 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10226 __ movl($dst$$Register, $src$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10227 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10228 ins_pipe(ialu_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
10229 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10230
a61af66fc99e Initial load
duke
parents:
diff changeset
10231
a61af66fc99e Initial load
duke
parents:
diff changeset
10232 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10233 match(Set dst (MoveF2I src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10234 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
10235
a61af66fc99e Initial load
duke
parents:
diff changeset
10236 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
10237 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10238 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10239 __ movl($dst$$Register, Address(rsp, $src$$disp));
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10240 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10241 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
10242 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10243
a61af66fc99e Initial load
duke
parents:
diff changeset
10244 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10245 match(Set dst (MoveI2F src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10246 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
10247
a61af66fc99e Initial load
duke
parents:
diff changeset
10248 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
10249 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10250 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10251 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10252 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10253 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10254 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10255
a61af66fc99e Initial load
duke
parents:
diff changeset
10256 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10257 match(Set dst (MoveD2L src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10258 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
10259
a61af66fc99e Initial load
duke
parents:
diff changeset
10260 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
10261 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10262 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10263 __ movq($dst$$Register, Address(rsp, $src$$disp));
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10264 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10265 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
10266 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10267
a61af66fc99e Initial load
duke
parents:
diff changeset
10268 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10269 predicate(!UseXmmLoadAndClearUpper);
a61af66fc99e Initial load
duke
parents:
diff changeset
10270 match(Set dst (MoveL2D src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10271 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
10272
a61af66fc99e Initial load
duke
parents:
diff changeset
10273 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
10274 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10275 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10276 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10277 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10278 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10279 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10280
a61af66fc99e Initial load
duke
parents:
diff changeset
10281 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10282 predicate(UseXmmLoadAndClearUpper);
a61af66fc99e Initial load
duke
parents:
diff changeset
10283 match(Set dst (MoveL2D src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10284 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
10285
a61af66fc99e Initial load
duke
parents:
diff changeset
10286 ins_cost(125);
a61af66fc99e Initial load
duke
parents:
diff changeset
10287 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10288 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10289 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10290 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10291 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10292 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10293
a61af66fc99e Initial load
duke
parents:
diff changeset
10294
a61af66fc99e Initial load
duke
parents:
diff changeset
10295 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10296 match(Set dst (MoveF2I src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10297 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
10298
a61af66fc99e Initial load
duke
parents:
diff changeset
10299 ins_cost(95); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10300 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10301 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10302 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10303 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10304 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10305 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10306
a61af66fc99e Initial load
duke
parents:
diff changeset
10307 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10308 match(Set dst (MoveI2F src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10309 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
10310
a61af66fc99e Initial load
duke
parents:
diff changeset
10311 ins_cost(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
10312 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10313 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10314 __ movl(Address(rsp, $dst$$disp), $src$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10315 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10316 ins_pipe( ialu_mem_reg );
a61af66fc99e Initial load
duke
parents:
diff changeset
10317 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10318
a61af66fc99e Initial load
duke
parents:
diff changeset
10319 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10320 match(Set dst (MoveD2L src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10321 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
10322
a61af66fc99e Initial load
duke
parents:
diff changeset
10323 ins_cost(95); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10324 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10325 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10326 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10327 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10328 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10329 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10330
a61af66fc99e Initial load
duke
parents:
diff changeset
10331 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10332 match(Set dst (MoveL2D src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10333 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
10334
a61af66fc99e Initial load
duke
parents:
diff changeset
10335 ins_cost(100);
a61af66fc99e Initial load
duke
parents:
diff changeset
10336 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10337 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10338 __ movq(Address(rsp, $dst$$disp), $src$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10339 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10340 ins_pipe(ialu_mem_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
10341 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10342
a61af66fc99e Initial load
duke
parents:
diff changeset
10343 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10344 match(Set dst (MoveF2I src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10345 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
10346 ins_cost(85);
a61af66fc99e Initial load
duke
parents:
diff changeset
10347 format %{ "movd $dst,$src\t# MoveF2I" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10348 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10349 __ movdl($dst$$Register, $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10350 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10351 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
10352 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10353
a61af66fc99e Initial load
duke
parents:
diff changeset
10354 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10355 match(Set dst (MoveD2L src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10356 effect(DEF dst, USE src);
a61af66fc99e Initial load
duke
parents:
diff changeset
10357 ins_cost(85);
a61af66fc99e Initial load
duke
parents:
diff changeset
10358 format %{ "movd $dst,$src\t# MoveD2L" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10359 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10360 __ movdq($dst$$Register, $src$$XMMRegister);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10361 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10362 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
10363 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10364
a61af66fc99e Initial load
duke
parents:
diff changeset
10365 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10366 match(Set dst (MoveI2F src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10367 effect(DEF dst, USE src);
6614
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
10368 ins_cost(100);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10369 format %{ "movd $dst,$src\t# MoveI2F" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10370 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10371 __ movdl($dst$$XMMRegister, $src$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10372 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10373 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
10374 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10375
a61af66fc99e Initial load
duke
parents:
diff changeset
10376 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10377 match(Set dst (MoveL2D src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10378 effect(DEF dst, USE src);
6614
006050192a5a 6340864: Implement vectorization optimizations in hotspot-server
kvn
parents: 6179
diff changeset
10379 ins_cost(100);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10380 format %{ "movd $dst,$src\t# MoveL2D" %}
4759
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10381 ins_encode %{
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10382 __ movdq($dst$$XMMRegister, $src$$Register);
127b3692c168 7116452: Add support for AVX instructions
kvn
parents: 4121
diff changeset
10383 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10384 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
10385 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10386
a61af66fc99e Initial load
duke
parents:
diff changeset
10387
a61af66fc99e Initial load
duke
parents:
diff changeset
10388 // =======================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
10389 // fast clearing of an array
a61af66fc99e Initial load
duke
parents:
diff changeset
10390 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
a61af66fc99e Initial load
duke
parents:
diff changeset
10391 rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
10392 %{
7474
00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing
kvn
parents: 6849
diff changeset
10393 predicate(!UseFastStosb);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10394 match(Set dummy (ClearArray cnt base));
a61af66fc99e Initial load
duke
parents:
diff changeset
10395 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10396
7474
00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing
kvn
parents: 6849
diff changeset
10397 format %{ "xorq rax, rax\t# ClearArray:\n\t"
00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing
kvn
parents: 6849
diff changeset
10398 "rep stosq\t# Store rax to *rdi++ while rcx--" %}
00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing
kvn
parents: 6849
diff changeset
10399 ins_encode %{
00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing
kvn
parents: 6849
diff changeset
10400 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing
kvn
parents: 6849
diff changeset
10401 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10402 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10403 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10404
7474
00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing
kvn
parents: 6849
diff changeset
10405 instruct rep_fast_stosb(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing
kvn
parents: 6849
diff changeset
10406 rFlagsReg cr)
00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing
kvn
parents: 6849
diff changeset
10407 %{
00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing
kvn
parents: 6849
diff changeset
10408 predicate(UseFastStosb);
00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing
kvn
parents: 6849
diff changeset
10409 match(Set dummy (ClearArray cnt base));
00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing
kvn
parents: 6849
diff changeset
10410 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing
kvn
parents: 6849
diff changeset
10411 format %{ "xorq rax, rax\t# ClearArray:\n\t"
00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing
kvn
parents: 6849
diff changeset
10412 "shlq rcx,3\t# Convert doublewords to bytes\n\t"
00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing
kvn
parents: 6849
diff changeset
10413 "rep stosb\t# Store rax to *rdi++ while rcx--" %}
00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing
kvn
parents: 6849
diff changeset
10414 ins_encode %{
00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing
kvn
parents: 6849
diff changeset
10415 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing
kvn
parents: 6849
diff changeset
10416 %}
00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing
kvn
parents: 6849
diff changeset
10417 ins_pipe( pipe_slow );
00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing
kvn
parents: 6849
diff changeset
10418 %}
00af3a3a8df4 8005522: use fast-string instructions on x86 for zeroing
kvn
parents: 6849
diff changeset
10419
2262
6bbaedb03534 7016474: string compare intrinsic improvements
never
parents: 2008
diff changeset
10420 instruct string_compare(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
6bbaedb03534 7016474: string compare intrinsic improvements
never
parents: 2008
diff changeset
10421 rax_RegI result, regD tmp1, rFlagsReg cr)
986
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10422 %{
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10423 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
2262
6bbaedb03534 7016474: string compare intrinsic improvements
never
parents: 2008
diff changeset
10424 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
6bbaedb03534 7016474: string compare intrinsic improvements
never
parents: 2008
diff changeset
10425
6bbaedb03534 7016474: string compare intrinsic improvements
never
parents: 2008
diff changeset
10426 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
986
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10427 ins_encode %{
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10428 __ string_compare($str1$$Register, $str2$$Register,
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10429 $cnt1$$Register, $cnt2$$Register, $result$$Register,
2262
6bbaedb03534 7016474: string compare intrinsic improvements
never
parents: 2008
diff changeset
10430 $tmp1$$XMMRegister);
986
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10431 %}
681
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 671
diff changeset
10432 ins_pipe( pipe_slow );
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 671
diff changeset
10433 %}
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 671
diff changeset
10434
2320
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10435 // fast search of substring with known size.
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10436 instruct string_indexof_con(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10437 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10438 %{
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10439 predicate(UseSSE42Intrinsics);
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10440 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10441 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10442
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10443 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10444 ins_encode %{
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10445 int icnt2 = (int)$int_cnt2$$constant;
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10446 if (icnt2 >= 8) {
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10447 // IndexOf for constant substrings with size >= 8 elements
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10448 // which don't need to be loaded through stack.
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10449 __ string_indexofC8($str1$$Register, $str2$$Register,
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10450 $cnt1$$Register, $cnt2$$Register,
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10451 icnt2, $result$$Register,
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10452 $vec$$XMMRegister, $tmp$$Register);
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10453 } else {
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10454 // Small strings are loaded through stack if they cross page boundary.
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10455 __ string_indexof($str1$$Register, $str2$$Register,
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10456 $cnt1$$Register, $cnt2$$Register,
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10457 icnt2, $result$$Register,
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10458 $vec$$XMMRegister, $tmp$$Register);
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10459 }
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10460 %}
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10461 ins_pipe( pipe_slow );
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10462 %}
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10463
986
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10464 instruct string_indexof(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
2320
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10465 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr)
681
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 671
diff changeset
10466 %{
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 671
diff changeset
10467 predicate(UseSSE42Intrinsics);
986
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10468 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
2320
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10469 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10470
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10471 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
986
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10472 ins_encode %{
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10473 __ string_indexof($str1$$Register, $str2$$Register,
2320
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10474 $cnt1$$Register, $cnt2$$Register,
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10475 (-1), $result$$Register,
41d4973cf100 6942326: x86 code in string_indexof() could read beyond reserved heap space
kvn
parents: 2262
diff changeset
10476 $vec$$XMMRegister, $tmp$$Register);
986
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10477 %}
681
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 671
diff changeset
10478 ins_pipe( pipe_slow );
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 671
diff changeset
10479 %}
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 671
diff changeset
10480
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 671
diff changeset
10481 // fast string equals
986
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10482 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10483 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr)
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10484 %{
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10485 match(Set result (StrEquals (Binary str1 str2) cnt));
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10486 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10487
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10488 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10489 ins_encode %{
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10490 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10491 $cnt$$Register, $result$$Register, $tmp3$$Register,
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10492 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10493 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10494 ins_pipe( pipe_slow );
a61af66fc99e Initial load
duke
parents:
diff changeset
10495 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10496
169
9148c65abefc 6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents: 168
diff changeset
10497 // fast array equals
986
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10498 instruct array_equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10499 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
681
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 671
diff changeset
10500 %{
169
9148c65abefc 6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents: 168
diff changeset
10501 match(Set result (AryEq ary1 ary2));
681
fbde8ec322d0 6761600: Use sse 4.2 in intrinsics
cfang
parents: 671
diff changeset
10502 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
169
9148c65abefc 6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents: 168
diff changeset
10503 //ins_cost(300);
9148c65abefc 6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents: 168
diff changeset
10504
986
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10505 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10506 ins_encode %{
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10507 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10508 $tmp3$$Register, $result$$Register, $tmp4$$Register,
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10509 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
62001a362ce9 6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents: 824
diff changeset
10510 %}
169
9148c65abefc 6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents: 168
diff changeset
10511 ins_pipe( pipe_slow );
9148c65abefc 6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents: 168
diff changeset
10512 %}
9148c65abefc 6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents: 168
diff changeset
10513
7637
b30b3c2a0cf2 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents: 7474
diff changeset
10514 // encode char[] to byte[] in ISO_8859_1
b30b3c2a0cf2 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents: 7474
diff changeset
10515 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
b30b3c2a0cf2 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents: 7474
diff changeset
10516 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
b30b3c2a0cf2 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents: 7474
diff changeset
10517 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
b30b3c2a0cf2 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents: 7474
diff changeset
10518 match(Set result (EncodeISOArray src (Binary dst len)));
b30b3c2a0cf2 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents: 7474
diff changeset
10519 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
b30b3c2a0cf2 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents: 7474
diff changeset
10520
b30b3c2a0cf2 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents: 7474
diff changeset
10521 format %{ "Encode array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
b30b3c2a0cf2 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents: 7474
diff changeset
10522 ins_encode %{
b30b3c2a0cf2 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents: 7474
diff changeset
10523 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
b30b3c2a0cf2 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents: 7474
diff changeset
10524 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
b30b3c2a0cf2 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents: 7474
diff changeset
10525 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
b30b3c2a0cf2 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents: 7474
diff changeset
10526 %}
b30b3c2a0cf2 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents: 7474
diff changeset
10527 ins_pipe( pipe_slow );
b30b3c2a0cf2 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents: 7474
diff changeset
10528 %}
b30b3c2a0cf2 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents: 7474
diff changeset
10529
b30b3c2a0cf2 6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents: 7474
diff changeset
10530
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10531 //----------Control Flow Instructions------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
10532 // Signed compare Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
10533
a61af66fc99e Initial load
duke
parents:
diff changeset
10534 // XXX more variants!!
a61af66fc99e Initial load
duke
parents:
diff changeset
10535 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
10536 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10537 match(Set cr (CmpI op1 op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10538 effect(DEF cr, USE op1, USE op2);
a61af66fc99e Initial load
duke
parents:
diff changeset
10539
a61af66fc99e Initial load
duke
parents:
diff changeset
10540 format %{ "cmpl $op1, $op2" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10541 opcode(0x3B); /* Opcode 3B /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
10542 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10543 ins_pipe(ialu_cr_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
10544 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10545
a61af66fc99e Initial load
duke
parents:
diff changeset
10546 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
10547 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10548 match(Set cr (CmpI op1 op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10549
a61af66fc99e Initial load
duke
parents:
diff changeset
10550 format %{ "cmpl $op1, $op2" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10551 opcode(0x81, 0x07); /* Opcode 81 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
10552 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10553 ins_pipe(ialu_cr_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
10554 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10555
a61af66fc99e Initial load
duke
parents:
diff changeset
10556 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
10557 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10558 match(Set cr (CmpI op1 (LoadI op2)));
a61af66fc99e Initial load
duke
parents:
diff changeset
10559
a61af66fc99e Initial load
duke
parents:
diff changeset
10560 ins_cost(500); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10561 format %{ "cmpl $op1, $op2" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10562 opcode(0x3B); /* Opcode 3B /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
10563 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10564 ins_pipe(ialu_cr_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
10565 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10566
a61af66fc99e Initial load
duke
parents:
diff changeset
10567 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
a61af66fc99e Initial load
duke
parents:
diff changeset
10568 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10569 match(Set cr (CmpI src zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
10570
a61af66fc99e Initial load
duke
parents:
diff changeset
10571 format %{ "testl $src, $src" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10572 opcode(0x85);
a61af66fc99e Initial load
duke
parents:
diff changeset
10573 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10574 ins_pipe(ialu_cr_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
10575 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10576
a61af66fc99e Initial load
duke
parents:
diff changeset
10577 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
a61af66fc99e Initial load
duke
parents:
diff changeset
10578 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10579 match(Set cr (CmpI (AndI src con) zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
10580
a61af66fc99e Initial load
duke
parents:
diff changeset
10581 format %{ "testl $src, $con" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10582 opcode(0xF7, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
10583 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
a61af66fc99e Initial load
duke
parents:
diff changeset
10584 ins_pipe(ialu_cr_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
10585 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10586
a61af66fc99e Initial load
duke
parents:
diff changeset
10587 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
a61af66fc99e Initial load
duke
parents:
diff changeset
10588 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10589 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
10590
a61af66fc99e Initial load
duke
parents:
diff changeset
10591 format %{ "testl $src, $mem" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10592 opcode(0x85);
a61af66fc99e Initial load
duke
parents:
diff changeset
10593 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
10594 ins_pipe(ialu_cr_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
10595 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10596
a61af66fc99e Initial load
duke
parents:
diff changeset
10597 // Unsigned compare Instructions; really, same as signed except they
a61af66fc99e Initial load
duke
parents:
diff changeset
10598 // produce an rFlagsRegU instead of rFlagsReg.
a61af66fc99e Initial load
duke
parents:
diff changeset
10599 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
10600 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10601 match(Set cr (CmpU op1 op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10602
a61af66fc99e Initial load
duke
parents:
diff changeset
10603 format %{ "cmpl $op1, $op2\t# unsigned" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10604 opcode(0x3B); /* Opcode 3B /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
10605 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10606 ins_pipe(ialu_cr_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
10607 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10608
a61af66fc99e Initial load
duke
parents:
diff changeset
10609 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
10610 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10611 match(Set cr (CmpU op1 op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10612
a61af66fc99e Initial load
duke
parents:
diff changeset
10613 format %{ "cmpl $op1, $op2\t# unsigned" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10614 opcode(0x81,0x07); /* Opcode 81 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
10615 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10616 ins_pipe(ialu_cr_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
10617 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10618
a61af66fc99e Initial load
duke
parents:
diff changeset
10619 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
10620 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10621 match(Set cr (CmpU op1 (LoadI op2)));
a61af66fc99e Initial load
duke
parents:
diff changeset
10622
a61af66fc99e Initial load
duke
parents:
diff changeset
10623 ins_cost(500); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10624 format %{ "cmpl $op1, $op2\t# unsigned" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10625 opcode(0x3B); /* Opcode 3B /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
10626 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10627 ins_pipe(ialu_cr_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
10628 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10629
a61af66fc99e Initial load
duke
parents:
diff changeset
10630 // // // Cisc-spilled version of cmpU_rReg
a61af66fc99e Initial load
duke
parents:
diff changeset
10631 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
10632 // //%{
a61af66fc99e Initial load
duke
parents:
diff changeset
10633 // // match(Set cr (CmpU (LoadI op1) op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10634 // //
a61af66fc99e Initial load
duke
parents:
diff changeset
10635 // // format %{ "CMPu $op1,$op2" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10636 // // ins_cost(500);
a61af66fc99e Initial load
duke
parents:
diff changeset
10637 // // opcode(0x39); /* Opcode 39 /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
10638 // // ins_encode( OpcP, reg_mem( op1, op2) );
a61af66fc99e Initial load
duke
parents:
diff changeset
10639 // //%}
a61af66fc99e Initial load
duke
parents:
diff changeset
10640
a61af66fc99e Initial load
duke
parents:
diff changeset
10641 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
a61af66fc99e Initial load
duke
parents:
diff changeset
10642 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10643 match(Set cr (CmpU src zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
10644
a61af66fc99e Initial load
duke
parents:
diff changeset
10645 format %{ "testl $src, $src\t# unsigned" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10646 opcode(0x85);
a61af66fc99e Initial load
duke
parents:
diff changeset
10647 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10648 ins_pipe(ialu_cr_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
10649 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10650
a61af66fc99e Initial load
duke
parents:
diff changeset
10651 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
10652 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10653 match(Set cr (CmpP op1 op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10654
a61af66fc99e Initial load
duke
parents:
diff changeset
10655 format %{ "cmpq $op1, $op2\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10656 opcode(0x3B); /* Opcode 3B /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
10657 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10658 ins_pipe(ialu_cr_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
10659 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10660
a61af66fc99e Initial load
duke
parents:
diff changeset
10661 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
10662 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10663 match(Set cr (CmpP op1 (LoadP op2)));
a61af66fc99e Initial load
duke
parents:
diff changeset
10664
a61af66fc99e Initial load
duke
parents:
diff changeset
10665 ins_cost(500); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10666 format %{ "cmpq $op1, $op2\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10667 opcode(0x3B); /* Opcode 3B /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
10668 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10669 ins_pipe(ialu_cr_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
10670 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10671
a61af66fc99e Initial load
duke
parents:
diff changeset
10672 // // // Cisc-spilled version of cmpP_rReg
a61af66fc99e Initial load
duke
parents:
diff changeset
10673 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
10674 // //%{
a61af66fc99e Initial load
duke
parents:
diff changeset
10675 // // match(Set cr (CmpP (LoadP op1) op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10676 // //
a61af66fc99e Initial load
duke
parents:
diff changeset
10677 // // format %{ "CMPu $op1,$op2" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10678 // // ins_cost(500);
a61af66fc99e Initial load
duke
parents:
diff changeset
10679 // // opcode(0x39); /* Opcode 39 /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
10680 // // ins_encode( OpcP, reg_mem( op1, op2) );
a61af66fc99e Initial load
duke
parents:
diff changeset
10681 // //%}
a61af66fc99e Initial load
duke
parents:
diff changeset
10682
a61af66fc99e Initial load
duke
parents:
diff changeset
10683 // XXX this is generalized by compP_rReg_mem???
a61af66fc99e Initial load
duke
parents:
diff changeset
10684 // Compare raw pointer (used in out-of-heap check).
a61af66fc99e Initial load
duke
parents:
diff changeset
10685 // Only works because non-oop pointers must be raw pointers
a61af66fc99e Initial load
duke
parents:
diff changeset
10686 // and raw pointers have no anti-dependencies.
a61af66fc99e Initial load
duke
parents:
diff changeset
10687 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
10688 %{
6725
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 6614
diff changeset
10689 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10690 match(Set cr (CmpP op1 (LoadP op2)));
a61af66fc99e Initial load
duke
parents:
diff changeset
10691
a61af66fc99e Initial load
duke
parents:
diff changeset
10692 format %{ "cmpq $op1, $op2\t# raw ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10693 opcode(0x3B); /* Opcode 3B /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
10694 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10695 ins_pipe(ialu_cr_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
10696 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10697
a61af66fc99e Initial load
duke
parents:
diff changeset
10698 // This will generate a signed flags result. This should be OK since
a61af66fc99e Initial load
duke
parents:
diff changeset
10699 // any compare to a zero should be eq/neq.
a61af66fc99e Initial load
duke
parents:
diff changeset
10700 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
a61af66fc99e Initial load
duke
parents:
diff changeset
10701 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10702 match(Set cr (CmpP src zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
10703
a61af66fc99e Initial load
duke
parents:
diff changeset
10704 format %{ "testq $src, $src\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10705 opcode(0x85);
a61af66fc99e Initial load
duke
parents:
diff changeset
10706 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10707 ins_pipe(ialu_cr_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
10708 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10709
a61af66fc99e Initial load
duke
parents:
diff changeset
10710 // This will generate a signed flags result. This should be OK since
a61af66fc99e Initial load
duke
parents:
diff changeset
10711 // any compare to a zero should be eq/neq.
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10712 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10713 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10714 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10715 match(Set cr (CmpP (LoadP op) zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
10716
a61af66fc99e Initial load
duke
parents:
diff changeset
10717 ins_cost(500); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10718 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10719 opcode(0xF7); /* Opcode F7 /0 */
a61af66fc99e Initial load
duke
parents:
diff changeset
10720 ins_encode(REX_mem_wide(op),
a61af66fc99e Initial load
duke
parents:
diff changeset
10721 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
a61af66fc99e Initial load
duke
parents:
diff changeset
10722 ins_pipe(ialu_cr_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
10723 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10724
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10725 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10726 %{
6848
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
10727 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10728 match(Set cr (CmpP (LoadP mem) zero));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10729
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10730 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10731 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10732 __ cmpq(r12, $mem$$Address);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10733 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10734 ins_pipe(ialu_cr_reg_mem);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10735 %}
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10736
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10737 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10738 %{
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10739 match(Set cr (CmpN op1 op2));
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10740
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10741 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10742 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10743 ins_pipe(ialu_cr_reg_reg);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10744 %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10745
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10746 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10747 %{
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10748 match(Set cr (CmpN src (LoadN mem)));
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10749
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10750 format %{ "cmpl $src, $mem\t# compressed ptr" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10751 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10752 __ cmpl($src$$Register, $mem$$Address);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10753 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10754 ins_pipe(ialu_cr_reg_mem);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10755 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10756
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10757 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10758 match(Set cr (CmpN op1 op2));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10759
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10760 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10761 ins_encode %{
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10762 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10763 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10764 ins_pipe(ialu_cr_reg_imm);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10765 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10766
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10767 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10768 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10769 match(Set cr (CmpN src (LoadN mem)));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10770
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10771 format %{ "cmpl $mem, $src\t# compressed ptr" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10772 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10773 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10774 %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10775 ins_pipe(ialu_cr_reg_mem);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10776 %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10777
6848
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
10778 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
10779 match(Set cr (CmpN op1 op2));
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
10780
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
10781 format %{ "cmpl $op1, $op2\t# compressed klass ptr" %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
10782 ins_encode %{
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
10783 __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
10784 %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
10785 ins_pipe(ialu_cr_reg_imm);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
10786 %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
10787
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
10788 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src)
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
10789 %{
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
10790 match(Set cr (CmpN src (LoadNKlass mem)));
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
10791
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
10792 format %{ "cmpl $mem, $src\t# compressed klass ptr" %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
10793 ins_encode %{
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
10794 __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
10795 %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
10796 ins_pipe(ialu_cr_reg_mem);
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
10797 %}
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
10798
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
10799 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
10800 match(Set cr (CmpN src zero));
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
10801
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10802 format %{ "testl $src, $src\t# compressed ptr" %}
113
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
10803 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
10804 ins_pipe(ialu_cr_reg_imm);
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
10805 %}
ba764ed4b6f2 6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents: 71
diff changeset
10806
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10807 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10808 %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10809 predicate(Universe::narrow_oop_base() != NULL);
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10810 match(Set cr (CmpN (LoadN mem) zero));
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10811
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10812 ins_cost(500); // XXX
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10813 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10814 ins_encode %{
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10815 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10816 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10817 ins_pipe(ialu_cr_reg_mem);
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10818 %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10819
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10820 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10821 %{
6848
8e47bac5643a 7054512: Compress class pointers after perm gen removal
roland
parents: 6795
diff changeset
10822 predicate(Universe::narrow_oop_base() == NULL && (Universe::narrow_klass_base() == NULL));
642
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10823 match(Set cr (CmpN (LoadN mem) zero));
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10824
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10825 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10826 ins_encode %{
660978a2a31a 6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents: 624
diff changeset
10827 __ cmpl(r12, $mem$$Address);
164
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10828 %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10829 ins_pipe(ialu_cr_reg_mem);
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10830 %}
c436414a719e 6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents: 163
diff changeset
10831
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10832 // Yanked all unsigned pointer compare operations.
a61af66fc99e Initial load
duke
parents:
diff changeset
10833 // Pointer compares are done with CmpP which is already unsigned.
a61af66fc99e Initial load
duke
parents:
diff changeset
10834
a61af66fc99e Initial load
duke
parents:
diff changeset
10835 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
10836 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10837 match(Set cr (CmpL op1 op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10838
a61af66fc99e Initial load
duke
parents:
diff changeset
10839 format %{ "cmpq $op1, $op2" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10840 opcode(0x3B); /* Opcode 3B /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
10841 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10842 ins_pipe(ialu_cr_reg_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
10843 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10844
a61af66fc99e Initial load
duke
parents:
diff changeset
10845 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
10846 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10847 match(Set cr (CmpL op1 op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10848
a61af66fc99e Initial load
duke
parents:
diff changeset
10849 format %{ "cmpq $op1, $op2" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10850 opcode(0x81, 0x07); /* Opcode 81 /7 */
a61af66fc99e Initial load
duke
parents:
diff changeset
10851 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10852 ins_pipe(ialu_cr_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
10853 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10854
a61af66fc99e Initial load
duke
parents:
diff changeset
10855 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
a61af66fc99e Initial load
duke
parents:
diff changeset
10856 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10857 match(Set cr (CmpL op1 (LoadL op2)));
a61af66fc99e Initial load
duke
parents:
diff changeset
10858
a61af66fc99e Initial load
duke
parents:
diff changeset
10859 format %{ "cmpq $op1, $op2" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10860 opcode(0x3B); /* Opcode 3B /r */
a61af66fc99e Initial load
duke
parents:
diff changeset
10861 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10862 ins_pipe(ialu_cr_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
10863 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10864
a61af66fc99e Initial load
duke
parents:
diff changeset
10865 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
a61af66fc99e Initial load
duke
parents:
diff changeset
10866 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10867 match(Set cr (CmpL src zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
10868
a61af66fc99e Initial load
duke
parents:
diff changeset
10869 format %{ "testq $src, $src" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10870 opcode(0x85);
a61af66fc99e Initial load
duke
parents:
diff changeset
10871 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10872 ins_pipe(ialu_cr_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
10873 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10874
a61af66fc99e Initial load
duke
parents:
diff changeset
10875 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
a61af66fc99e Initial load
duke
parents:
diff changeset
10876 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10877 match(Set cr (CmpL (AndL src con) zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
10878
a61af66fc99e Initial load
duke
parents:
diff changeset
10879 format %{ "testq $src, $con\t# long" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10880 opcode(0xF7, 0x00);
a61af66fc99e Initial load
duke
parents:
diff changeset
10881 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
a61af66fc99e Initial load
duke
parents:
diff changeset
10882 ins_pipe(ialu_cr_reg_imm);
a61af66fc99e Initial load
duke
parents:
diff changeset
10883 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10884
a61af66fc99e Initial load
duke
parents:
diff changeset
10885 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
a61af66fc99e Initial load
duke
parents:
diff changeset
10886 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10887 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
10888
a61af66fc99e Initial load
duke
parents:
diff changeset
10889 format %{ "testq $src, $mem" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10890 opcode(0x85);
a61af66fc99e Initial load
duke
parents:
diff changeset
10891 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
10892 ins_pipe(ialu_cr_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
10893 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10894
a61af66fc99e Initial load
duke
parents:
diff changeset
10895 // Manifest a CmpL result in an integer register. Very painful.
a61af66fc99e Initial load
duke
parents:
diff changeset
10896 // This is the test to avoid.
a61af66fc99e Initial load
duke
parents:
diff changeset
10897 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
a61af66fc99e Initial load
duke
parents:
diff changeset
10898 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10899 match(Set dst (CmpL3 src1 src2));
a61af66fc99e Initial load
duke
parents:
diff changeset
10900 effect(KILL flags);
a61af66fc99e Initial load
duke
parents:
diff changeset
10901
a61af66fc99e Initial load
duke
parents:
diff changeset
10902 ins_cost(275); // XXX
a61af66fc99e Initial load
duke
parents:
diff changeset
10903 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10904 "movl $dst, -1\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10905 "jl,s done\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10906 "setne $dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10907 "movzbl $dst, $dst\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
10908 "done:" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10909 ins_encode(cmpl3_flag(src1, src2, dst));
a61af66fc99e Initial load
duke
parents:
diff changeset
10910 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
10911 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10912
a61af66fc99e Initial load
duke
parents:
diff changeset
10913 //----------Max and Min--------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
10914 // Min Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
10915
a61af66fc99e Initial load
duke
parents:
diff changeset
10916 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
10917 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10918 effect(USE_DEF dst, USE src, USE cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10919
a61af66fc99e Initial load
duke
parents:
diff changeset
10920 format %{ "cmovlgt $dst, $src\t# min" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10921 opcode(0x0F, 0x4F);
a61af66fc99e Initial load
duke
parents:
diff changeset
10922 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10923 ins_pipe(pipe_cmov_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
10924 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10925
a61af66fc99e Initial load
duke
parents:
diff changeset
10926
a61af66fc99e Initial load
duke
parents:
diff changeset
10927 instruct minI_rReg(rRegI dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
10928 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10929 match(Set dst (MinI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10930
a61af66fc99e Initial load
duke
parents:
diff changeset
10931 ins_cost(200);
a61af66fc99e Initial load
duke
parents:
diff changeset
10932 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10933 rFlagsReg cr;
a61af66fc99e Initial load
duke
parents:
diff changeset
10934 compI_rReg(cr, dst, src);
a61af66fc99e Initial load
duke
parents:
diff changeset
10935 cmovI_reg_g(dst, src, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10936 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10937 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10938
a61af66fc99e Initial load
duke
parents:
diff changeset
10939 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
10940 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10941 effect(USE_DEF dst, USE src, USE cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10942
a61af66fc99e Initial load
duke
parents:
diff changeset
10943 format %{ "cmovllt $dst, $src\t# max" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10944 opcode(0x0F, 0x4C);
a61af66fc99e Initial load
duke
parents:
diff changeset
10945 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10946 ins_pipe(pipe_cmov_reg);
a61af66fc99e Initial load
duke
parents:
diff changeset
10947 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10948
a61af66fc99e Initial load
duke
parents:
diff changeset
10949
a61af66fc99e Initial load
duke
parents:
diff changeset
10950 instruct maxI_rReg(rRegI dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
10951 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10952 match(Set dst (MaxI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
10953
a61af66fc99e Initial load
duke
parents:
diff changeset
10954 ins_cost(200);
a61af66fc99e Initial load
duke
parents:
diff changeset
10955 expand %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10956 rFlagsReg cr;
a61af66fc99e Initial load
duke
parents:
diff changeset
10957 compI_rReg(cr, dst, src);
a61af66fc99e Initial load
duke
parents:
diff changeset
10958 cmovI_reg_l(dst, src, cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10959 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10960 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10961
a61af66fc99e Initial load
duke
parents:
diff changeset
10962 // ============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
10963 // Branch Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
10964
a61af66fc99e Initial load
duke
parents:
diff changeset
10965 // Jump Direct - Label defines a relative address from JMP+1
a61af66fc99e Initial load
duke
parents:
diff changeset
10966 instruct jmpDir(label labl)
a61af66fc99e Initial load
duke
parents:
diff changeset
10967 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10968 match(Goto);
a61af66fc99e Initial load
duke
parents:
diff changeset
10969 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
10970
a61af66fc99e Initial load
duke
parents:
diff changeset
10971 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
10972 format %{ "jmp $labl" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10973 size(5);
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10974 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10975 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10976 __ jmp(*L, false); // Always long jump
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10977 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10978 ins_pipe(pipe_jmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
10979 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10980
a61af66fc99e Initial load
duke
parents:
diff changeset
10981 // Jump Direct Conditional - Label defines a relative address from Jcc+1
a61af66fc99e Initial load
duke
parents:
diff changeset
10982 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
a61af66fc99e Initial load
duke
parents:
diff changeset
10983 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
10984 match(If cop cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
10985 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
10986
a61af66fc99e Initial load
duke
parents:
diff changeset
10987 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
10988 format %{ "j$cop $labl" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10989 size(6);
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10990 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10991 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10992 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
10993 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
10994 ins_pipe(pipe_jcc);
a61af66fc99e Initial load
duke
parents:
diff changeset
10995 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
10996
a61af66fc99e Initial load
duke
parents:
diff changeset
10997 // Jump Direct Conditional - Label defines a relative address from Jcc+1
a61af66fc99e Initial load
duke
parents:
diff changeset
10998 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
a61af66fc99e Initial load
duke
parents:
diff changeset
10999 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11000 match(CountedLoopEnd cop cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
11001 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
11002
a61af66fc99e Initial load
duke
parents:
diff changeset
11003 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
11004 format %{ "j$cop $labl\t# loop end" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11005 size(6);
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11006 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11007 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11008 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11009 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11010 ins_pipe(pipe_jcc);
a61af66fc99e Initial load
duke
parents:
diff changeset
11011 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11012
a61af66fc99e Initial load
duke
parents:
diff changeset
11013 // Jump Direct Conditional - Label defines a relative address from Jcc+1
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11014 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11015 match(CountedLoopEnd cop cmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
11016 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
11017
a61af66fc99e Initial load
duke
parents:
diff changeset
11018 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
11019 format %{ "j$cop,u $labl\t# loop end" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11020 size(6);
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11021 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11022 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11023 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11024 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11025 ins_pipe(pipe_jcc);
a61af66fc99e Initial load
duke
parents:
diff changeset
11026 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11027
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11028 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11029 match(CountedLoopEnd cop cmp);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11030 effect(USE labl);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11031
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11032 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11033 format %{ "j$cop,u $labl\t# loop end" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11034 size(6);
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11035 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11036 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11037 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11038 %}
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11039 ins_pipe(pipe_jcc);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11040 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11041
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11042 // Jump Direct Conditional - using unsigned comparison
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11043 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11044 match(If cop cmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
11045 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
11046
a61af66fc99e Initial load
duke
parents:
diff changeset
11047 ins_cost(300);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11048 format %{ "j$cop,u $labl" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11049 size(6);
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11050 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11051 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11052 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11053 %}
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11054 ins_pipe(pipe_jcc);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11055 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11056
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11057 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11058 match(If cop cmp);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11059 effect(USE labl);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11060
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11061 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11062 format %{ "j$cop,u $labl" %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11063 size(6);
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11064 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11065 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11066 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11067 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11068 ins_pipe(pipe_jcc);
a61af66fc99e Initial load
duke
parents:
diff changeset
11069 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11070
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11071 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11072 match(If cop cmp);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11073 effect(USE labl);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11074
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11075 ins_cost(200);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11076 format %{ $$template
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11077 if ($cop$$cmpcode == Assembler::notEqual) {
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11078 $$emit$$"jp,u $labl\n\t"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11079 $$emit$$"j$cop,u $labl"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11080 } else {
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11081 $$emit$$"jp,u done\n\t"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11082 $$emit$$"j$cop,u $labl\n\t"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11083 $$emit$$"done:"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11084 }
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11085 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11086 ins_encode %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11087 Label* l = $labl$$label;
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11088 if ($cop$$cmpcode == Assembler::notEqual) {
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11089 __ jcc(Assembler::parity, *l, false);
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11090 __ jcc(Assembler::notEqual, *l, false);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11091 } else if ($cop$$cmpcode == Assembler::equal) {
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11092 Label done;
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11093 __ jccb(Assembler::parity, done);
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11094 __ jcc(Assembler::equal, *l, false);
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11095 __ bind(done);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11096 } else {
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11097 ShouldNotReachHere();
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11098 }
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11099 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11100 ins_pipe(pipe_jcc);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11101 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11102
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11103 // ============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
11104 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
a61af66fc99e Initial load
duke
parents:
diff changeset
11105 // superklass array for an instance of the superklass. Set a hidden
a61af66fc99e Initial load
duke
parents:
diff changeset
11106 // internal cache on a hit (cache is checked with exposed code in
a61af66fc99e Initial load
duke
parents:
diff changeset
11107 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
a61af66fc99e Initial load
duke
parents:
diff changeset
11108 // encoding ALSO sets flags.
a61af66fc99e Initial load
duke
parents:
diff changeset
11109
a61af66fc99e Initial load
duke
parents:
diff changeset
11110 instruct partialSubtypeCheck(rdi_RegP result,
a61af66fc99e Initial load
duke
parents:
diff changeset
11111 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
a61af66fc99e Initial load
duke
parents:
diff changeset
11112 rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
11113 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11114 match(Set result (PartialSubtypeCheck sub super));
a61af66fc99e Initial load
duke
parents:
diff changeset
11115 effect(KILL rcx, KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
11116
a61af66fc99e Initial load
duke
parents:
diff changeset
11117 ins_cost(1100); // slightly larger than the next version
4762
069ab3f976d3 7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents: 4761
diff changeset
11118 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
6725
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 6614
diff changeset
11119 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 6614
diff changeset
11120 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11121 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11122 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
4762
069ab3f976d3 7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents: 4761
diff changeset
11123 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11124 "xorq $result, $result\t\t Hit: rdi zero\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11125 "miss:\t" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11126
a61af66fc99e Initial load
duke
parents:
diff changeset
11127 opcode(0x1); // Force a XOR of RDI
a61af66fc99e Initial load
duke
parents:
diff changeset
11128 ins_encode(enc_PartialSubtypeCheck());
a61af66fc99e Initial load
duke
parents:
diff changeset
11129 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
11130 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11131
a61af66fc99e Initial load
duke
parents:
diff changeset
11132 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
a61af66fc99e Initial load
duke
parents:
diff changeset
11133 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
a61af66fc99e Initial load
duke
parents:
diff changeset
11134 immP0 zero,
a61af66fc99e Initial load
duke
parents:
diff changeset
11135 rdi_RegP result)
a61af66fc99e Initial load
duke
parents:
diff changeset
11136 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11137 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
a61af66fc99e Initial load
duke
parents:
diff changeset
11138 effect(KILL rcx, KILL result);
a61af66fc99e Initial load
duke
parents:
diff changeset
11139
a61af66fc99e Initial load
duke
parents:
diff changeset
11140 ins_cost(1000);
4762
069ab3f976d3 7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents: 4761
diff changeset
11141 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
6725
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 6614
diff changeset
11142 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
da91efe96a93 6964458: Reimplement class meta-data storage to use native memory
coleenp
parents: 6614
diff changeset
11143 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11144 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11145 "jne,s miss\t\t# Missed: flags nz\n\t"
4762
069ab3f976d3 7118863: Move sizeof(klassOopDesc) into the *Klass::*_offset_in_bytes() functions
stefank
parents: 4761
diff changeset
11146 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11147 "miss:\t" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11148
a61af66fc99e Initial load
duke
parents:
diff changeset
11149 opcode(0x0); // No need to XOR RDI
a61af66fc99e Initial load
duke
parents:
diff changeset
11150 ins_encode(enc_PartialSubtypeCheck());
a61af66fc99e Initial load
duke
parents:
diff changeset
11151 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
11152 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11153
a61af66fc99e Initial load
duke
parents:
diff changeset
11154 // ============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
11155 // Branch Instructions -- short offset versions
a61af66fc99e Initial load
duke
parents:
diff changeset
11156 //
a61af66fc99e Initial load
duke
parents:
diff changeset
11157 // These instructions are used to replace jumps of a long offset (the default
a61af66fc99e Initial load
duke
parents:
diff changeset
11158 // match) with jumps of a shorter offset. These instructions are all tagged
a61af66fc99e Initial load
duke
parents:
diff changeset
11159 // with the ins_short_branch attribute, which causes the ADLC to suppress the
a61af66fc99e Initial load
duke
parents:
diff changeset
11160 // match rules in general matching. Instead, the ADLC generates a conversion
a61af66fc99e Initial load
duke
parents:
diff changeset
11161 // method in the MachNode which can be used to do in-place replacement of the
a61af66fc99e Initial load
duke
parents:
diff changeset
11162 // long variant with the shorter variant. The compiler will determine if a
a61af66fc99e Initial load
duke
parents:
diff changeset
11163 // branch can be taken by the is_short_branch_offset() predicate in the machine
a61af66fc99e Initial load
duke
parents:
diff changeset
11164 // specific code section of the file.
a61af66fc99e Initial load
duke
parents:
diff changeset
11165
a61af66fc99e Initial load
duke
parents:
diff changeset
11166 // Jump Direct - Label defines a relative address from JMP+1
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11167 instruct jmpDir_short(label labl) %{
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11168 match(Goto);
a61af66fc99e Initial load
duke
parents:
diff changeset
11169 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
11170
a61af66fc99e Initial load
duke
parents:
diff changeset
11171 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
11172 format %{ "jmp,s $labl" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11173 size(2);
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11174 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11175 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11176 __ jmpb(*L);
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11177 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11178 ins_pipe(pipe_jmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
11179 ins_short_branch(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
11180 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11181
a61af66fc99e Initial load
duke
parents:
diff changeset
11182 // Jump Direct Conditional - Label defines a relative address from Jcc+1
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11183 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11184 match(If cop cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
11185 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
11186
a61af66fc99e Initial load
duke
parents:
diff changeset
11187 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
11188 format %{ "j$cop,s $labl" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11189 size(2);
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11190 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11191 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11192 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11193 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11194 ins_pipe(pipe_jcc);
a61af66fc99e Initial load
duke
parents:
diff changeset
11195 ins_short_branch(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
11196 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11197
a61af66fc99e Initial load
duke
parents:
diff changeset
11198 // Jump Direct Conditional - Label defines a relative address from Jcc+1
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11199 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11200 match(CountedLoopEnd cop cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
11201 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
11202
a61af66fc99e Initial load
duke
parents:
diff changeset
11203 ins_cost(300);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11204 format %{ "j$cop,s $labl\t# loop end" %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11205 size(2);
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11206 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11207 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11208 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11209 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11210 ins_pipe(pipe_jcc);
a61af66fc99e Initial load
duke
parents:
diff changeset
11211 ins_short_branch(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
11212 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11213
a61af66fc99e Initial load
duke
parents:
diff changeset
11214 // Jump Direct Conditional - Label defines a relative address from Jcc+1
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11215 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11216 match(CountedLoopEnd cop cmp);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11217 effect(USE labl);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11218
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11219 ins_cost(300);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11220 format %{ "j$cop,us $labl\t# loop end" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11221 size(2);
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11222 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11223 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11224 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11225 %}
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11226 ins_pipe(pipe_jcc);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11227 ins_short_branch(1);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11228 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11229
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11230 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11231 match(CountedLoopEnd cop cmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
11232 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
11233
a61af66fc99e Initial load
duke
parents:
diff changeset
11234 ins_cost(300);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11235 format %{ "j$cop,us $labl\t# loop end" %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11236 size(2);
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11237 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11238 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11239 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11240 %}
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11241 ins_pipe(pipe_jcc);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11242 ins_short_branch(1);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11243 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11244
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11245 // Jump Direct Conditional - using unsigned comparison
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11246 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11247 match(If cop cmp);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11248 effect(USE labl);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11249
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11250 ins_cost(300);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11251 format %{ "j$cop,us $labl" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11252 size(2);
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11253 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11254 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11255 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11256 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11257 ins_pipe(pipe_jcc);
a61af66fc99e Initial load
duke
parents:
diff changeset
11258 ins_short_branch(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
11259 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11260
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11261 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11262 match(If cop cmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
11263 effect(USE labl);
a61af66fc99e Initial load
duke
parents:
diff changeset
11264
a61af66fc99e Initial load
duke
parents:
diff changeset
11265 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
11266 format %{ "j$cop,us $labl" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11267 size(2);
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11268 ins_encode %{
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11269 Label* L = $labl$$label;
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11270 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11271 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11272 ins_pipe(pipe_jcc);
a61af66fc99e Initial load
duke
parents:
diff changeset
11273 ins_short_branch(1);
a61af66fc99e Initial load
duke
parents:
diff changeset
11274 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11275
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11276 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11277 match(If cop cmp);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11278 effect(USE labl);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11279
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11280 ins_cost(300);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11281 format %{ $$template
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11282 if ($cop$$cmpcode == Assembler::notEqual) {
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11283 $$emit$$"jp,u,s $labl\n\t"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11284 $$emit$$"j$cop,u,s $labl"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11285 } else {
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11286 $$emit$$"jp,u,s done\n\t"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11287 $$emit$$"j$cop,u,s $labl\n\t"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11288 $$emit$$"done:"
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11289 }
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11290 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11291 size(4);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11292 ins_encode %{
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11293 Label* l = $labl$$label;
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11294 if ($cop$$cmpcode == Assembler::notEqual) {
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11295 __ jccb(Assembler::parity, *l);
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11296 __ jccb(Assembler::notEqual, *l);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11297 } else if ($cop$$cmpcode == Assembler::equal) {
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11298 Label done;
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11299 __ jccb(Assembler::parity, done);
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11300 __ jccb(Assembler::equal, *l);
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11301 __ bind(done);
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11302 } else {
3851
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11303 ShouldNotReachHere();
95134e034042 7063629: use cbcond in C2 generated code on T4
kvn
parents: 3849
diff changeset
11304 }
415
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11305 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11306 ins_pipe(pipe_jcc);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11307 ins_short_branch(1);
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11308 %}
4d9884b01ba6 6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents: 403
diff changeset
11309
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11310 // ============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
11311 // inlined locking and unlocking
a61af66fc99e Initial load
duke
parents:
diff changeset
11312
a61af66fc99e Initial load
duke
parents:
diff changeset
11313 instruct cmpFastLock(rFlagsReg cr,
4777
e9a5e0a812c8 7125896: Eliminate nested locks
kvn
parents: 4763
diff changeset
11314 rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr)
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11315 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11316 match(Set cr (FastLock object box));
4777
e9a5e0a812c8 7125896: Eliminate nested locks
kvn
parents: 4763
diff changeset
11317 effect(TEMP tmp, TEMP scr, USE_KILL box);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11318
a61af66fc99e Initial load
duke
parents:
diff changeset
11319 ins_cost(300);
4777
e9a5e0a812c8 7125896: Eliminate nested locks
kvn
parents: 4763
diff changeset
11320 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11321 ins_encode(Fast_Lock(object, box, tmp, scr));
a61af66fc99e Initial load
duke
parents:
diff changeset
11322 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
11323 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11324
a61af66fc99e Initial load
duke
parents:
diff changeset
11325 instruct cmpFastUnlock(rFlagsReg cr,
a61af66fc99e Initial load
duke
parents:
diff changeset
11326 rRegP object, rax_RegP box, rRegP tmp)
a61af66fc99e Initial load
duke
parents:
diff changeset
11327 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11328 match(Set cr (FastUnlock object box));
4777
e9a5e0a812c8 7125896: Eliminate nested locks
kvn
parents: 4763
diff changeset
11329 effect(TEMP tmp, USE_KILL box);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11330
a61af66fc99e Initial load
duke
parents:
diff changeset
11331 ins_cost(300);
4777
e9a5e0a812c8 7125896: Eliminate nested locks
kvn
parents: 4763
diff changeset
11332 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11333 ins_encode(Fast_Unlock(object, box, tmp));
a61af66fc99e Initial load
duke
parents:
diff changeset
11334 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
11335 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11336
a61af66fc99e Initial load
duke
parents:
diff changeset
11337
a61af66fc99e Initial load
duke
parents:
diff changeset
11338 // ============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
11339 // Safepoint Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
11340 instruct safePoint_poll(rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
11341 %{
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
11342 predicate(!Assembler::is_polling_page_far());
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11343 match(SafePoint);
a61af66fc99e Initial load
duke
parents:
diff changeset
11344 effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
11345
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
11346 format %{ "testl rax, [rip + #offset_to_poll_page]\t"
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11347 "# Safepoint: poll for GC" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11348 ins_cost(125);
2404
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
11349 ins_encode %{
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
11350 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
11351 __ testl(rax, addr);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
11352 %}
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
11353 ins_pipe(ialu_reg_mem);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
11354 %}
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
11355
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
11356 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll)
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
11357 %{
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
11358 predicate(Assembler::is_polling_page_far());
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
11359 match(SafePoint poll);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
11360 effect(KILL cr, USE poll);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
11361
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
11362 format %{ "testl rax, [$poll]\t"
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
11363 "# Safepoint: poll for GC" %}
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
11364 ins_cost(125);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
11365 ins_encode %{
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
11366 __ relocate(relocInfo::poll_type);
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
11367 __ testl(rax, Address($poll$$Register, 0));
b40d4fa697bf 6964776: c2 should ensure the polling page is reachable on 64 bit
iveresov
parents: 2401
diff changeset
11368 %}
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11369 ins_pipe(ialu_reg_mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
11370 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11371
a61af66fc99e Initial load
duke
parents:
diff changeset
11372 // ============================================================================
a61af66fc99e Initial load
duke
parents:
diff changeset
11373 // Procedure Call/Return Instructions
a61af66fc99e Initial load
duke
parents:
diff changeset
11374 // Call Java Static Instruction
a61af66fc99e Initial load
duke
parents:
diff changeset
11375 // Note: If this code changes, the corresponding ret_addr_offset() and
a61af66fc99e Initial load
duke
parents:
diff changeset
11376 // compute_padding() functions will have to be adjusted.
1137
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11377 instruct CallStaticJavaDirect(method meth) %{
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11378 match(CallStaticJava);
1137
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11379 predicate(!((CallStaticJavaNode*) n)->is_method_handle_invoke());
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11380 effect(USE meth);
a61af66fc99e Initial load
duke
parents:
diff changeset
11381
a61af66fc99e Initial load
duke
parents:
diff changeset
11382 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
11383 format %{ "call,static " %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11384 opcode(0xE8); /* E8 cd */
8873
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
11385 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11386 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
11387 ins_alignment(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
11388 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11389
1137
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11390 // Call Java Static Instruction (method handle version)
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11391 // Note: If this code changes, the corresponding ret_addr_offset() and
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11392 // compute_padding() functions will have to be adjusted.
1567
110501f54a99 6934104: JSR 292 needs to support SPARC C2
twisti
parents: 1396
diff changeset
11393 instruct CallStaticJavaHandle(method meth, rbp_RegP rbp_mh_SP_save) %{
1137
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11394 match(CallStaticJava);
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11395 predicate(((CallStaticJavaNode*) n)->is_method_handle_invoke());
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11396 effect(USE meth);
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11397 // RBP is saved by all callees (for interpreter stack correction).
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11398 // We use it here for a similar purpose, in {preserve,restore}_SP.
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11399
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11400 ins_cost(300);
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11401 format %{ "call,static/MethodHandle " %}
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11402 opcode(0xE8); /* E8 cd */
8873
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
11403 ins_encode(clear_avx, preserve_SP,
1137
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11404 Java_Static_Call(meth),
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11405 restore_SP,
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11406 call_epilog);
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11407 ins_pipe(pipe_slow);
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11408 ins_alignment(4);
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11409 %}
97125851f396 6829187: compiler optimizations required for JSR 292
twisti
parents: 989
diff changeset
11410
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11411 // Call Java Dynamic Instruction
a61af66fc99e Initial load
duke
parents:
diff changeset
11412 // Note: If this code changes, the corresponding ret_addr_offset() and
a61af66fc99e Initial load
duke
parents:
diff changeset
11413 // compute_padding() functions will have to be adjusted.
a61af66fc99e Initial load
duke
parents:
diff changeset
11414 instruct CallDynamicJavaDirect(method meth)
a61af66fc99e Initial load
duke
parents:
diff changeset
11415 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11416 match(CallDynamicJava);
a61af66fc99e Initial load
duke
parents:
diff changeset
11417 effect(USE meth);
a61af66fc99e Initial load
duke
parents:
diff changeset
11418
a61af66fc99e Initial load
duke
parents:
diff changeset
11419 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
11420 format %{ "movq rax, #Universe::non_oop_word()\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11421 "call,dynamic " %}
8873
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
11422 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11423 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
11424 ins_alignment(4);
a61af66fc99e Initial load
duke
parents:
diff changeset
11425 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11426
a61af66fc99e Initial load
duke
parents:
diff changeset
11427 // Call Runtime Instruction
a61af66fc99e Initial load
duke
parents:
diff changeset
11428 instruct CallRuntimeDirect(method meth)
a61af66fc99e Initial load
duke
parents:
diff changeset
11429 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11430 match(CallRuntime);
a61af66fc99e Initial load
duke
parents:
diff changeset
11431 effect(USE meth);
a61af66fc99e Initial load
duke
parents:
diff changeset
11432
a61af66fc99e Initial load
duke
parents:
diff changeset
11433 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
11434 format %{ "call,runtime " %}
8873
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
11435 ins_encode(clear_avx, Java_To_Runtime(meth));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11436 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
11437 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11438
a61af66fc99e Initial load
duke
parents:
diff changeset
11439 // Call runtime without safepoint
a61af66fc99e Initial load
duke
parents:
diff changeset
11440 instruct CallLeafDirect(method meth)
a61af66fc99e Initial load
duke
parents:
diff changeset
11441 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11442 match(CallLeaf);
a61af66fc99e Initial load
duke
parents:
diff changeset
11443 effect(USE meth);
a61af66fc99e Initial load
duke
parents:
diff changeset
11444
a61af66fc99e Initial load
duke
parents:
diff changeset
11445 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
11446 format %{ "call_leaf,runtime " %}
8873
e961c11b85fe 8011102: Clear AVX registers after return from JNI call
kvn
parents: 7637
diff changeset
11447 ins_encode(clear_avx, Java_To_Runtime(meth));
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11448 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
11449 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11450
a61af66fc99e Initial load
duke
parents:
diff changeset
11451 // Call runtime without safepoint
a61af66fc99e Initial load
duke
parents:
diff changeset
11452 instruct CallLeafNoFPDirect(method meth)
a61af66fc99e Initial load
duke
parents:
diff changeset
11453 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11454 match(CallLeafNoFP);
a61af66fc99e Initial load
duke
parents:
diff changeset
11455 effect(USE meth);
a61af66fc99e Initial load
duke
parents:
diff changeset
11456
a61af66fc99e Initial load
duke
parents:
diff changeset
11457 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
11458 format %{ "call_leaf_nofp,runtime " %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11459 ins_encode(Java_To_Runtime(meth));
a61af66fc99e Initial load
duke
parents:
diff changeset
11460 ins_pipe(pipe_slow);
a61af66fc99e Initial load
duke
parents:
diff changeset
11461 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11462
a61af66fc99e Initial load
duke
parents:
diff changeset
11463 // Return Instruction
a61af66fc99e Initial load
duke
parents:
diff changeset
11464 // Remove the return address & jump to it.
a61af66fc99e Initial load
duke
parents:
diff changeset
11465 // Notice: We always emit a nop after a ret to make sure there is room
a61af66fc99e Initial load
duke
parents:
diff changeset
11466 // for safepoint patching
a61af66fc99e Initial load
duke
parents:
diff changeset
11467 instruct Ret()
a61af66fc99e Initial load
duke
parents:
diff changeset
11468 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11469 match(Return);
a61af66fc99e Initial load
duke
parents:
diff changeset
11470
a61af66fc99e Initial load
duke
parents:
diff changeset
11471 format %{ "ret" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11472 opcode(0xC3);
a61af66fc99e Initial load
duke
parents:
diff changeset
11473 ins_encode(OpcP);
a61af66fc99e Initial load
duke
parents:
diff changeset
11474 ins_pipe(pipe_jmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
11475 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11476
a61af66fc99e Initial load
duke
parents:
diff changeset
11477 // Tail Call; Jump from runtime stub to Java code.
a61af66fc99e Initial load
duke
parents:
diff changeset
11478 // Also known as an 'interprocedural jump'.
a61af66fc99e Initial load
duke
parents:
diff changeset
11479 // Target of jump will eventually return to caller.
a61af66fc99e Initial load
duke
parents:
diff changeset
11480 // TailJump below removes the return address.
a61af66fc99e Initial load
duke
parents:
diff changeset
11481 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
a61af66fc99e Initial load
duke
parents:
diff changeset
11482 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11483 match(TailCall jump_target method_oop);
a61af66fc99e Initial load
duke
parents:
diff changeset
11484
a61af66fc99e Initial load
duke
parents:
diff changeset
11485 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
11486 format %{ "jmp $jump_target\t# rbx holds method oop" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11487 opcode(0xFF, 0x4); /* Opcode FF /4 */
a61af66fc99e Initial load
duke
parents:
diff changeset
11488 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
a61af66fc99e Initial load
duke
parents:
diff changeset
11489 ins_pipe(pipe_jmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
11490 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11491
a61af66fc99e Initial load
duke
parents:
diff changeset
11492 // Tail Jump; remove the return address; jump to target.
a61af66fc99e Initial load
duke
parents:
diff changeset
11493 // TailCall above leaves the return address around.
a61af66fc99e Initial load
duke
parents:
diff changeset
11494 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
a61af66fc99e Initial load
duke
parents:
diff changeset
11495 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11496 match(TailJump jump_target ex_oop);
a61af66fc99e Initial load
duke
parents:
diff changeset
11497
a61af66fc99e Initial load
duke
parents:
diff changeset
11498 ins_cost(300);
a61af66fc99e Initial load
duke
parents:
diff changeset
11499 format %{ "popq rdx\t# pop return address\n\t"
a61af66fc99e Initial load
duke
parents:
diff changeset
11500 "jmp $jump_target" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11501 opcode(0xFF, 0x4); /* Opcode FF /4 */
a61af66fc99e Initial load
duke
parents:
diff changeset
11502 ins_encode(Opcode(0x5a), // popq rdx
a61af66fc99e Initial load
duke
parents:
diff changeset
11503 REX_reg(jump_target), OpcP, reg_opc(jump_target));
a61af66fc99e Initial load
duke
parents:
diff changeset
11504 ins_pipe(pipe_jmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
11505 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11506
a61af66fc99e Initial load
duke
parents:
diff changeset
11507 // Create exception oop: created by stack-crawling runtime code.
a61af66fc99e Initial load
duke
parents:
diff changeset
11508 // Created exception is now available to this handler, and is setup
a61af66fc99e Initial load
duke
parents:
diff changeset
11509 // just prior to jumping to this handler. No code emitted.
a61af66fc99e Initial load
duke
parents:
diff changeset
11510 instruct CreateException(rax_RegP ex_oop)
a61af66fc99e Initial load
duke
parents:
diff changeset
11511 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11512 match(Set ex_oop (CreateEx));
a61af66fc99e Initial load
duke
parents:
diff changeset
11513
a61af66fc99e Initial load
duke
parents:
diff changeset
11514 size(0);
a61af66fc99e Initial load
duke
parents:
diff changeset
11515 // use the following format syntax
a61af66fc99e Initial load
duke
parents:
diff changeset
11516 format %{ "# exception oop is in rax; no code emitted" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11517 ins_encode();
a61af66fc99e Initial load
duke
parents:
diff changeset
11518 ins_pipe(empty);
a61af66fc99e Initial load
duke
parents:
diff changeset
11519 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11520
a61af66fc99e Initial load
duke
parents:
diff changeset
11521 // Rethrow exception:
a61af66fc99e Initial load
duke
parents:
diff changeset
11522 // The exception oop will come in the first argument position.
a61af66fc99e Initial load
duke
parents:
diff changeset
11523 // Then JUMP (not call) to the rethrow stub code.
a61af66fc99e Initial load
duke
parents:
diff changeset
11524 instruct RethrowException()
a61af66fc99e Initial load
duke
parents:
diff changeset
11525 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11526 match(Rethrow);
a61af66fc99e Initial load
duke
parents:
diff changeset
11527
a61af66fc99e Initial load
duke
parents:
diff changeset
11528 // use the following format syntax
a61af66fc99e Initial load
duke
parents:
diff changeset
11529 format %{ "jmp rethrow_stub" %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11530 ins_encode(enc_rethrow);
a61af66fc99e Initial load
duke
parents:
diff changeset
11531 ins_pipe(pipe_jmp);
a61af66fc99e Initial load
duke
parents:
diff changeset
11532 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11533
a61af66fc99e Initial load
duke
parents:
diff changeset
11534
4950
9b8ce46870df 7145346: VerifyStackAtCalls is broken
kvn
parents: 4947
diff changeset
11535 // ============================================================================
9b8ce46870df 7145346: VerifyStackAtCalls is broken
kvn
parents: 4947
diff changeset
11536 // This name is KNOWN by the ADLC and cannot be changed.
9b8ce46870df 7145346: VerifyStackAtCalls is broken
kvn
parents: 4947
diff changeset
11537 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
9b8ce46870df 7145346: VerifyStackAtCalls is broken
kvn
parents: 4947
diff changeset
11538 // for this guy.
9b8ce46870df 7145346: VerifyStackAtCalls is broken
kvn
parents: 4947
diff changeset
11539 instruct tlsLoadP(r15_RegP dst) %{
9b8ce46870df 7145346: VerifyStackAtCalls is broken
kvn
parents: 4947
diff changeset
11540 match(Set dst (ThreadLocal));
9b8ce46870df 7145346: VerifyStackAtCalls is broken
kvn
parents: 4947
diff changeset
11541 effect(DEF dst);
9b8ce46870df 7145346: VerifyStackAtCalls is broken
kvn
parents: 4947
diff changeset
11542
9b8ce46870df 7145346: VerifyStackAtCalls is broken
kvn
parents: 4947
diff changeset
11543 size(0);
9b8ce46870df 7145346: VerifyStackAtCalls is broken
kvn
parents: 4947
diff changeset
11544 format %{ "# TLS is in R15" %}
9b8ce46870df 7145346: VerifyStackAtCalls is broken
kvn
parents: 4947
diff changeset
11545 ins_encode( /*empty encoding*/ );
9b8ce46870df 7145346: VerifyStackAtCalls is broken
kvn
parents: 4947
diff changeset
11546 ins_pipe(ialu_reg_reg);
9b8ce46870df 7145346: VerifyStackAtCalls is broken
kvn
parents: 4947
diff changeset
11547 %}
9b8ce46870df 7145346: VerifyStackAtCalls is broken
kvn
parents: 4947
diff changeset
11548
9b8ce46870df 7145346: VerifyStackAtCalls is broken
kvn
parents: 4947
diff changeset
11549
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11550 //----------PEEPHOLE RULES-----------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
11551 // These must follow all instruction definitions as they use the names
a61af66fc99e Initial load
duke
parents:
diff changeset
11552 // defined in the instructions definitions.
a61af66fc99e Initial load
duke
parents:
diff changeset
11553 //
605
98cb887364d3 6810672: Comment typos
twisti
parents: 569
diff changeset
11554 // peepmatch ( root_instr_name [preceding_instruction]* );
0
a61af66fc99e Initial load
duke
parents:
diff changeset
11555 //
a61af66fc99e Initial load
duke
parents:
diff changeset
11556 // peepconstraint %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11557 // (instruction_number.operand_name relational_op instruction_number.operand_name
a61af66fc99e Initial load
duke
parents:
diff changeset
11558 // [, ...] );
a61af66fc99e Initial load
duke
parents:
diff changeset
11559 // // instruction numbers are zero-based using left to right order in peepmatch
a61af66fc99e Initial load
duke
parents:
diff changeset
11560 //
a61af66fc99e Initial load
duke
parents:
diff changeset
11561 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
11562 // // provide an instruction_number.operand_name for each operand that appears
a61af66fc99e Initial load
duke
parents:
diff changeset
11563 // // in the replacement instruction's match rule
a61af66fc99e Initial load
duke
parents:
diff changeset
11564 //
a61af66fc99e Initial load
duke
parents:
diff changeset
11565 // ---------VM FLAGS---------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
11566 //
a61af66fc99e Initial load
duke
parents:
diff changeset
11567 // All peephole optimizations can be turned off using -XX:-OptoPeephole
a61af66fc99e Initial load
duke
parents:
diff changeset
11568 //
a61af66fc99e Initial load
duke
parents:
diff changeset
11569 // Each peephole rule is given an identifying number starting with zero and
a61af66fc99e Initial load
duke
parents:
diff changeset
11570 // increasing by one in the order seen by the parser. An individual peephole
a61af66fc99e Initial load
duke
parents:
diff changeset
11571 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
a61af66fc99e Initial load
duke
parents:
diff changeset
11572 // on the command-line.
a61af66fc99e Initial load
duke
parents:
diff changeset
11573 //
a61af66fc99e Initial load
duke
parents:
diff changeset
11574 // ---------CURRENT LIMITATIONS----------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
11575 //
a61af66fc99e Initial load
duke
parents:
diff changeset
11576 // Only match adjacent instructions in same basic block
a61af66fc99e Initial load
duke
parents:
diff changeset
11577 // Only equality constraints
a61af66fc99e Initial load
duke
parents:
diff changeset
11578 // Only constraints between operands, not (0.dest_reg == RAX_enc)
a61af66fc99e Initial load
duke
parents:
diff changeset
11579 // Only one replacement instruction
a61af66fc99e Initial load
duke
parents:
diff changeset
11580 //
a61af66fc99e Initial load
duke
parents:
diff changeset
11581 // ---------EXAMPLE----------------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
11582 //
a61af66fc99e Initial load
duke
parents:
diff changeset
11583 // // pertinent parts of existing instructions in architecture description
a61af66fc99e Initial load
duke
parents:
diff changeset
11584 // instruct movI(rRegI dst, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
11585 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11586 // match(Set dst (CopyI src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11587 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11588 //
a61af66fc99e Initial load
duke
parents:
diff changeset
11589 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
a61af66fc99e Initial load
duke
parents:
diff changeset
11590 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11591 // match(Set dst (AddI dst src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11592 // effect(KILL cr);
a61af66fc99e Initial load
duke
parents:
diff changeset
11593 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11594 //
a61af66fc99e Initial load
duke
parents:
diff changeset
11595 // // Change (inc mov) to lea
a61af66fc99e Initial load
duke
parents:
diff changeset
11596 // peephole %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11597 // // increment preceeded by register-register move
a61af66fc99e Initial load
duke
parents:
diff changeset
11598 // peepmatch ( incI_rReg movI );
a61af66fc99e Initial load
duke
parents:
diff changeset
11599 // // require that the destination register of the increment
a61af66fc99e Initial load
duke
parents:
diff changeset
11600 // // match the destination register of the move
a61af66fc99e Initial load
duke
parents:
diff changeset
11601 // peepconstraint ( 0.dst == 1.dst );
a61af66fc99e Initial load
duke
parents:
diff changeset
11602 // // construct a replacement instruction that sets
a61af66fc99e Initial load
duke
parents:
diff changeset
11603 // // the destination to ( move's source register + one )
a61af66fc99e Initial load
duke
parents:
diff changeset
11604 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
a61af66fc99e Initial load
duke
parents:
diff changeset
11605 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11606 //
a61af66fc99e Initial load
duke
parents:
diff changeset
11607
a61af66fc99e Initial load
duke
parents:
diff changeset
11608 // Implementation no longer uses movX instructions since
a61af66fc99e Initial load
duke
parents:
diff changeset
11609 // machine-independent system no longer uses CopyX nodes.
a61af66fc99e Initial load
duke
parents:
diff changeset
11610 //
a61af66fc99e Initial load
duke
parents:
diff changeset
11611 // peephole
a61af66fc99e Initial load
duke
parents:
diff changeset
11612 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11613 // peepmatch (incI_rReg movI);
a61af66fc99e Initial load
duke
parents:
diff changeset
11614 // peepconstraint (0.dst == 1.dst);
a61af66fc99e Initial load
duke
parents:
diff changeset
11615 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11616 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11617
a61af66fc99e Initial load
duke
parents:
diff changeset
11618 // peephole
a61af66fc99e Initial load
duke
parents:
diff changeset
11619 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11620 // peepmatch (decI_rReg movI);
a61af66fc99e Initial load
duke
parents:
diff changeset
11621 // peepconstraint (0.dst == 1.dst);
a61af66fc99e Initial load
duke
parents:
diff changeset
11622 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11623 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11624
a61af66fc99e Initial load
duke
parents:
diff changeset
11625 // peephole
a61af66fc99e Initial load
duke
parents:
diff changeset
11626 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11627 // peepmatch (addI_rReg_imm movI);
a61af66fc99e Initial load
duke
parents:
diff changeset
11628 // peepconstraint (0.dst == 1.dst);
a61af66fc99e Initial load
duke
parents:
diff changeset
11629 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11630 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11631
a61af66fc99e Initial load
duke
parents:
diff changeset
11632 // peephole
a61af66fc99e Initial load
duke
parents:
diff changeset
11633 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11634 // peepmatch (incL_rReg movL);
a61af66fc99e Initial load
duke
parents:
diff changeset
11635 // peepconstraint (0.dst == 1.dst);
a61af66fc99e Initial load
duke
parents:
diff changeset
11636 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11637 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11638
a61af66fc99e Initial load
duke
parents:
diff changeset
11639 // peephole
a61af66fc99e Initial load
duke
parents:
diff changeset
11640 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11641 // peepmatch (decL_rReg movL);
a61af66fc99e Initial load
duke
parents:
diff changeset
11642 // peepconstraint (0.dst == 1.dst);
a61af66fc99e Initial load
duke
parents:
diff changeset
11643 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11644 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11645
a61af66fc99e Initial load
duke
parents:
diff changeset
11646 // peephole
a61af66fc99e Initial load
duke
parents:
diff changeset
11647 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11648 // peepmatch (addL_rReg_imm movL);
a61af66fc99e Initial load
duke
parents:
diff changeset
11649 // peepconstraint (0.dst == 1.dst);
a61af66fc99e Initial load
duke
parents:
diff changeset
11650 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11651 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11652
a61af66fc99e Initial load
duke
parents:
diff changeset
11653 // peephole
a61af66fc99e Initial load
duke
parents:
diff changeset
11654 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11655 // peepmatch (addP_rReg_imm movP);
a61af66fc99e Initial load
duke
parents:
diff changeset
11656 // peepconstraint (0.dst == 1.dst);
a61af66fc99e Initial load
duke
parents:
diff changeset
11657 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11658 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11659
a61af66fc99e Initial load
duke
parents:
diff changeset
11660 // // Change load of spilled value to only a spill
a61af66fc99e Initial load
duke
parents:
diff changeset
11661 // instruct storeI(memory mem, rRegI src)
a61af66fc99e Initial load
duke
parents:
diff changeset
11662 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11663 // match(Set mem (StoreI mem src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11664 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11665 //
a61af66fc99e Initial load
duke
parents:
diff changeset
11666 // instruct loadI(rRegI dst, memory mem)
a61af66fc99e Initial load
duke
parents:
diff changeset
11667 // %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11668 // match(Set dst (LoadI mem));
a61af66fc99e Initial load
duke
parents:
diff changeset
11669 // %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11670 //
a61af66fc99e Initial load
duke
parents:
diff changeset
11671
a61af66fc99e Initial load
duke
parents:
diff changeset
11672 peephole
a61af66fc99e Initial load
duke
parents:
diff changeset
11673 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11674 peepmatch (loadI storeI);
a61af66fc99e Initial load
duke
parents:
diff changeset
11675 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
11676 peepreplace (storeI(1.mem 1.mem 1.src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11677 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11678
a61af66fc99e Initial load
duke
parents:
diff changeset
11679 peephole
a61af66fc99e Initial load
duke
parents:
diff changeset
11680 %{
a61af66fc99e Initial load
duke
parents:
diff changeset
11681 peepmatch (loadL storeL);
a61af66fc99e Initial load
duke
parents:
diff changeset
11682 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
a61af66fc99e Initial load
duke
parents:
diff changeset
11683 peepreplace (storeL(1.mem 1.mem 1.src));
a61af66fc99e Initial load
duke
parents:
diff changeset
11684 %}
a61af66fc99e Initial load
duke
parents:
diff changeset
11685
a61af66fc99e Initial load
duke
parents:
diff changeset
11686 //----------SMARTSPILL RULES---------------------------------------------------
a61af66fc99e Initial load
duke
parents:
diff changeset
11687 // These must follow all instruction definitions as they use the names
a61af66fc99e Initial load
duke
parents:
diff changeset
11688 // defined in the instructions definitions.