Mercurial > hg > graal-compiler
annotate src/share/vm/opto/matcher.cpp @ 10405:f2110083203d
8005849: JEP 167: Event-Based JVM Tracing
Reviewed-by: acorn, coleenp, sla
Contributed-by: Karen Kinnear <karen.kinnear@oracle.com>, Bengt Rutisson <bengt.rutisson@oracle.com>, Calvin Cheung <calvin.cheung@oracle.com>, Erik Gahlin <erik.gahlin@oracle.com>, Erik Helin <erik.helin@oracle.com>, Jesper Wilhelmsson <jesper.wilhelmsson@oracle.com>, Keith McGuigan <keith.mcguigan@oracle.com>, Mattias Tobiasson <mattias.tobiasson@oracle.com>, Markus Gronlund <markus.gronlund@oracle.com>, Mikael Auno <mikael.auno@oracle.com>, Nils Eliasson <nils.eliasson@oracle.com>, Nils Loodin <nils.loodin@oracle.com>, Rickard Backman <rickard.backman@oracle.com>, Staffan Larsen <staffan.larsen@oracle.com>, Stefan Karlsson <stefan.karlsson@oracle.com>, Yekaterina Kantserova <yekaterina.kantserova@oracle.com>
| author | sla |
|---|---|
| date | Mon, 10 Jun 2013 11:30:51 +0200 |
| parents | 603ca7e51354 |
| children | ac91879aa56f b5c8a61d7fa0 |
| rev | line source |
|---|---|
| 0 | 1 /* |
| 10405 | 2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
1552
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1203
diff
changeset
|
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
|
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1203
diff
changeset
|
20 * or visit www.oracle.com if you need additional information or have any |
|
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1203
diff
changeset
|
21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #include "precompiled.hpp" |
| 26 #include "memory/allocation.inline.hpp" | |
| 27 #include "opto/addnode.hpp" | |
| 28 #include "opto/callnode.hpp" | |
| 29 #include "opto/connode.hpp" | |
| 30 #include "opto/idealGraphPrinter.hpp" | |
| 31 #include "opto/matcher.hpp" | |
| 32 #include "opto/memnode.hpp" | |
| 33 #include "opto/opcodes.hpp" | |
| 34 #include "opto/regmask.hpp" | |
| 35 #include "opto/rootnode.hpp" | |
| 36 #include "opto/runtime.hpp" | |
| 37 #include "opto/type.hpp" | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
38 #include "opto/vectornode.hpp" |
| 1972 | 39 #include "runtime/atomic.hpp" |
| 40 #include "runtime/os.hpp" | |
| 41 #ifdef TARGET_ARCH_MODEL_x86_32 | |
| 42 # include "adfiles/ad_x86_32.hpp" | |
| 43 #endif | |
| 44 #ifdef TARGET_ARCH_MODEL_x86_64 | |
| 45 # include "adfiles/ad_x86_64.hpp" | |
| 46 #endif | |
| 47 #ifdef TARGET_ARCH_MODEL_sparc | |
| 48 # include "adfiles/ad_sparc.hpp" | |
| 49 #endif | |
| 50 #ifdef TARGET_ARCH_MODEL_zero | |
| 51 # include "adfiles/ad_zero.hpp" | |
| 52 #endif | |
|
2401
7e88bdae86ec
7029017: Additional architecture support for c2 compiler
roland
parents:
1980
diff
changeset
|
53 #ifdef TARGET_ARCH_MODEL_arm |
|
7e88bdae86ec
7029017: Additional architecture support for c2 compiler
roland
parents:
1980
diff
changeset
|
54 # include "adfiles/ad_arm.hpp" |
|
7e88bdae86ec
7029017: Additional architecture support for c2 compiler
roland
parents:
1980
diff
changeset
|
55 #endif |
| 3796 | 56 #ifdef TARGET_ARCH_MODEL_ppc |
| 57 # include "adfiles/ad_ppc.hpp" | |
| 58 #endif | |
| 0 | 59 |
| 60 OptoReg::Name OptoReg::c_frame_pointer; | |
| 61 | |
| 62 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf]; | |
| 63 RegMask Matcher::mreg2regmask[_last_Mach_Reg]; | |
| 64 RegMask Matcher::STACK_ONLY_mask; | |
| 65 RegMask Matcher::c_frame_ptr_mask; | |
| 66 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE; | |
| 67 const uint Matcher::_end_rematerialize = _END_REMATERIALIZE; | |
| 68 | |
| 69 //---------------------------Matcher------------------------------------------- | |
| 70 Matcher::Matcher( Node_List &proj_list ) : | |
| 71 PhaseTransform( Phase::Ins_Select ), | |
| 72 #ifdef ASSERT | |
| 73 _old2new_map(C->comp_arena()), | |
| 222 | 74 _new2old_map(C->comp_arena()), |
| 0 | 75 #endif |
|
168
7793bd37a336
6705887: Compressed Oops: generate x64 addressing and implicit null checks with narrow oops
kvn
parents:
164
diff
changeset
|
76 _shared_nodes(C->comp_arena()), |
| 0 | 77 _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp), |
| 78 _swallowed(swallowed), | |
| 79 _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE), | |
| 80 _end_inst_chain_rule(_END_INST_CHAIN_RULE), | |
| 81 _must_clone(must_clone), _proj_list(proj_list), | |
| 82 _register_save_policy(register_save_policy), | |
| 83 _c_reg_save_policy(c_reg_save_policy), | |
| 84 _register_save_type(register_save_type), | |
| 85 _ruleName(ruleName), | |
| 86 _allocation_started(false), | |
| 87 _states_arena(Chunk::medium_size), | |
| 88 _visited(&_states_arena), | |
| 89 _shared(&_states_arena), | |
| 90 _dontcare(&_states_arena) { | |
| 91 C->set_matcher(this); | |
| 92 | |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
93 idealreg2spillmask [Op_RegI] = NULL; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
94 idealreg2spillmask [Op_RegN] = NULL; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
95 idealreg2spillmask [Op_RegL] = NULL; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
96 idealreg2spillmask [Op_RegF] = NULL; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
97 idealreg2spillmask [Op_RegD] = NULL; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
98 idealreg2spillmask [Op_RegP] = NULL; |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
99 idealreg2spillmask [Op_VecS] = NULL; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
100 idealreg2spillmask [Op_VecD] = NULL; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
101 idealreg2spillmask [Op_VecX] = NULL; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
102 idealreg2spillmask [Op_VecY] = NULL; |
| 0 | 103 |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
104 idealreg2debugmask [Op_RegI] = NULL; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
105 idealreg2debugmask [Op_RegN] = NULL; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
106 idealreg2debugmask [Op_RegL] = NULL; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
107 idealreg2debugmask [Op_RegF] = NULL; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
108 idealreg2debugmask [Op_RegD] = NULL; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
109 idealreg2debugmask [Op_RegP] = NULL; |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
110 idealreg2debugmask [Op_VecS] = NULL; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
111 idealreg2debugmask [Op_VecD] = NULL; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
112 idealreg2debugmask [Op_VecX] = NULL; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
113 idealreg2debugmask [Op_VecY] = NULL; |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
114 |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
115 idealreg2mhdebugmask[Op_RegI] = NULL; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
116 idealreg2mhdebugmask[Op_RegN] = NULL; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
117 idealreg2mhdebugmask[Op_RegL] = NULL; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
118 idealreg2mhdebugmask[Op_RegF] = NULL; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
119 idealreg2mhdebugmask[Op_RegD] = NULL; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
120 idealreg2mhdebugmask[Op_RegP] = NULL; |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
121 idealreg2mhdebugmask[Op_VecS] = NULL; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
122 idealreg2mhdebugmask[Op_VecD] = NULL; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
123 idealreg2mhdebugmask[Op_VecX] = NULL; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
124 idealreg2mhdebugmask[Op_VecY] = NULL; |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
125 |
|
216
8d191a7697e2
6715633: when matching a memory node the adr_type should not change
kvn
parents:
169
diff
changeset
|
126 debug_only(_mem_node = NULL;) // Ideal memory node consumed by mach node |
| 0 | 127 } |
| 128 | |
| 129 //------------------------------warp_incoming_stk_arg------------------------ | |
| 130 // This warps a VMReg into an OptoReg::Name | |
| 131 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) { | |
| 132 OptoReg::Name warped; | |
| 133 if( reg->is_stack() ) { // Stack slot argument? | |
| 134 warped = OptoReg::add(_old_SP, reg->reg2stack() ); | |
| 135 warped = OptoReg::add(warped, C->out_preserve_stack_slots()); | |
| 136 if( warped >= _in_arg_limit ) | |
| 137 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
138 if (!RegMask::can_represent_arg(warped)) { |
| 0 | 139 // the compiler cannot represent this method's calling sequence |
| 140 C->record_method_not_compilable_all_tiers("unsupported incoming calling sequence"); | |
| 141 return OptoReg::Bad; | |
| 142 } | |
| 143 return warped; | |
| 144 } | |
| 145 return OptoReg::as_OptoReg(reg); | |
| 146 } | |
| 147 | |
| 148 //---------------------------compute_old_SP------------------------------------ | |
| 149 OptoReg::Name Compile::compute_old_SP() { | |
| 150 int fixed = fixed_slots(); | |
| 151 int preserve = in_preserve_stack_slots(); | |
| 152 return OptoReg::stack2reg(round_to(fixed + preserve, Matcher::stack_alignment_in_slots())); | |
| 153 } | |
| 154 | |
| 155 | |
| 156 | |
| 157 #ifdef ASSERT | |
| 158 void Matcher::verify_new_nodes_only(Node* xroot) { | |
| 159 // Make sure that the new graph only references new nodes | |
| 160 ResourceMark rm; | |
| 161 Unique_Node_List worklist; | |
| 162 VectorSet visited(Thread::current()->resource_area()); | |
| 163 worklist.push(xroot); | |
| 164 while (worklist.size() > 0) { | |
| 165 Node* n = worklist.pop(); | |
| 166 visited <<= n->_idx; | |
| 167 assert(C->node_arena()->contains(n), "dead node"); | |
| 168 for (uint j = 0; j < n->req(); j++) { | |
| 169 Node* in = n->in(j); | |
| 170 if (in != NULL) { | |
| 171 assert(C->node_arena()->contains(in), "dead node"); | |
| 172 if (!visited.test(in->_idx)) { | |
| 173 worklist.push(in); | |
| 174 } | |
| 175 } | |
| 176 } | |
| 177 } | |
| 178 } | |
| 179 #endif | |
| 180 | |
| 181 | |
| 182 //---------------------------match--------------------------------------------- | |
| 183 void Matcher::match( ) { | |
|
823
14367225a853
6841800: Incorrect boundary values behavior for option -XX:MaxLabelRootDepth=0-6 leads to jvm crash
kvn
parents:
729
diff
changeset
|
184 if( MaxLabelRootDepth < 100 ) { // Too small? |
|
14367225a853
6841800: Incorrect boundary values behavior for option -XX:MaxLabelRootDepth=0-6 leads to jvm crash
kvn
parents:
729
diff
changeset
|
185 assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum"); |
|
14367225a853
6841800: Incorrect boundary values behavior for option -XX:MaxLabelRootDepth=0-6 leads to jvm crash
kvn
parents:
729
diff
changeset
|
186 MaxLabelRootDepth = 100; |
|
14367225a853
6841800: Incorrect boundary values behavior for option -XX:MaxLabelRootDepth=0-6 leads to jvm crash
kvn
parents:
729
diff
changeset
|
187 } |
| 0 | 188 // One-time initialization of some register masks. |
| 189 init_spill_mask( C->root()->in(1) ); | |
| 190 _return_addr_mask = return_addr(); | |
| 191 #ifdef _LP64 | |
| 192 // Pointers take 2 slots in 64-bit land | |
| 193 _return_addr_mask.Insert(OptoReg::add(return_addr(),1)); | |
| 194 #endif | |
| 195 | |
| 196 // Map a Java-signature return type into return register-value | |
| 197 // machine registers for 0, 1 and 2 returned values. | |
| 198 const TypeTuple *range = C->tf()->range(); | |
| 199 if( range->cnt() > TypeFunc::Parms ) { // If not a void function | |
| 200 // Get ideal-register return type | |
|
6725
da91efe96a93
6964458: Reimplement class meta-data storage to use native memory
coleenp
parents:
6266
diff
changeset
|
201 int ireg = range->field_at(TypeFunc::Parms)->ideal_reg(); |
| 0 | 202 // Get machine return register |
| 203 uint sop = C->start()->Opcode(); | |
| 204 OptoRegPair regs = return_value(ireg, false); | |
| 205 | |
| 206 // And mask for same | |
| 207 _return_value_mask = RegMask(regs.first()); | |
| 208 if( OptoReg::is_valid(regs.second()) ) | |
| 209 _return_value_mask.Insert(regs.second()); | |
| 210 } | |
| 211 | |
| 212 // --------------- | |
| 213 // Frame Layout | |
| 214 | |
| 215 // Need the method signature to determine the incoming argument types, | |
| 216 // because the types determine which registers the incoming arguments are | |
| 217 // in, and this affects the matched code. | |
| 218 const TypeTuple *domain = C->tf()->domain(); | |
| 219 uint argcnt = domain->cnt() - TypeFunc::Parms; | |
| 220 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt ); | |
| 221 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt ); | |
| 222 _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt ); | |
| 223 _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt ); | |
| 224 uint i; | |
| 225 for( i = 0; i<argcnt; i++ ) { | |
| 226 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type(); | |
| 227 } | |
| 228 | |
| 229 // Pass array of ideal registers and length to USER code (from the AD file) | |
| 230 // that will convert this to an array of register numbers. | |
| 231 const StartNode *start = C->start(); | |
| 232 start->calling_convention( sig_bt, vm_parm_regs, argcnt ); | |
| 233 #ifdef ASSERT | |
| 234 // Sanity check users' calling convention. Real handy while trying to | |
| 235 // get the initial port correct. | |
| 236 { for (uint i = 0; i<argcnt; i++) { | |
| 237 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) { | |
| 238 assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" ); | |
| 239 _parm_regs[i].set_bad(); | |
| 240 continue; | |
| 241 } | |
| 242 VMReg parm_reg = vm_parm_regs[i].first(); | |
| 243 assert(parm_reg->is_valid(), "invalid arg?"); | |
| 244 if (parm_reg->is_reg()) { | |
| 245 OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg); | |
| 246 assert(can_be_java_arg(opto_parm_reg) || | |
| 247 C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) || | |
| 248 opto_parm_reg == inline_cache_reg(), | |
| 249 "parameters in register must be preserved by runtime stubs"); | |
| 250 } | |
| 251 for (uint j = 0; j < i; j++) { | |
| 252 assert(parm_reg != vm_parm_regs[j].first(), | |
| 253 "calling conv. must produce distinct regs"); | |
| 254 } | |
| 255 } | |
| 256 } | |
| 257 #endif | |
| 258 | |
| 259 // Do some initial frame layout. | |
| 260 | |
| 261 // Compute the old incoming SP (may be called FP) as | |
| 262 // OptoReg::stack0() + locks + in_preserve_stack_slots + pad2. | |
| 263 _old_SP = C->compute_old_SP(); | |
| 264 assert( is_even(_old_SP), "must be even" ); | |
| 265 | |
| 266 // Compute highest incoming stack argument as | |
| 267 // _old_SP + out_preserve_stack_slots + incoming argument size. | |
| 268 _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots()); | |
| 269 assert( is_even(_in_arg_limit), "out_preserve must be even" ); | |
| 270 for( i = 0; i < argcnt; i++ ) { | |
| 271 // Permit args to have no register | |
| 272 _calling_convention_mask[i].Clear(); | |
| 273 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) { | |
| 274 continue; | |
| 275 } | |
| 276 // calling_convention returns stack arguments as a count of | |
| 277 // slots beyond OptoReg::stack0()/VMRegImpl::stack0. We need to convert this to | |
| 278 // the allocators point of view, taking into account all the | |
| 279 // preserve area, locks & pad2. | |
| 280 | |
| 281 OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first()); | |
| 282 if( OptoReg::is_valid(reg1)) | |
| 283 _calling_convention_mask[i].Insert(reg1); | |
| 284 | |
| 285 OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second()); | |
| 286 if( OptoReg::is_valid(reg2)) | |
| 287 _calling_convention_mask[i].Insert(reg2); | |
| 288 | |
| 289 // Saved biased stack-slot register number | |
| 290 _parm_regs[i].set_pair(reg2, reg1); | |
| 291 } | |
| 292 | |
| 293 // Finally, make sure the incoming arguments take up an even number of | |
| 294 // words, in case the arguments or locals need to contain doubleword stack | |
| 295 // slots. The rest of the system assumes that stack slot pairs (in | |
| 296 // particular, in the spill area) which look aligned will in fact be | |
| 297 // aligned relative to the stack pointer in the target machine. Double | |
| 298 // stack slots will always be allocated aligned. | |
| 299 _new_SP = OptoReg::Name(round_to(_in_arg_limit, RegMask::SlotsPerLong)); | |
| 300 | |
| 301 // Compute highest outgoing stack argument as | |
| 302 // _new_SP + out_preserve_stack_slots + max(outgoing argument size). | |
| 303 _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots()); | |
| 304 assert( is_even(_out_arg_limit), "out_preserve must be even" ); | |
| 305 | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
306 if (!RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1))) { |
| 0 | 307 // the compiler cannot represent this method's calling sequence |
| 308 C->record_method_not_compilable("must be able to represent all call arguments in reg mask"); | |
| 309 } | |
| 310 | |
| 311 if (C->failing()) return; // bailed out on incoming arg failure | |
| 312 | |
| 313 // --------------- | |
| 314 // Collect roots of matcher trees. Every node for which | |
| 315 // _shared[_idx] is cleared is guaranteed to not be shared, and thus | |
| 316 // can be a valid interior of some tree. | |
| 317 find_shared( C->root() ); | |
| 318 find_shared( C->top() ); | |
| 319 | |
| 10405 | 320 C->print_method(PHASE_BEFORE_MATCHING); |
| 0 | 321 |
|
729
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
681
diff
changeset
|
322 // Create new ideal node ConP #NULL even if it does exist in old space |
|
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
681
diff
changeset
|
323 // to avoid false sharing if the corresponding mach node is not used. |
|
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
681
diff
changeset
|
324 // The corresponding mach node is only used in rare cases for derived |
|
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
681
diff
changeset
|
325 // pointers. |
|
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
681
diff
changeset
|
326 Node* new_ideal_null = ConNode::make(C, TypePtr::NULL_PTR); |
|
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
681
diff
changeset
|
327 |
| 0 | 328 // Swap out to old-space; emptying new-space |
| 329 Arena *old = C->node_arena()->move_contents(C->old_arena()); | |
| 330 | |
| 331 // Save debug and profile information for nodes in old space: | |
| 332 _old_node_note_array = C->node_note_array(); | |
| 333 if (_old_node_note_array != NULL) { | |
| 334 C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*> | |
| 335 (C->comp_arena(), _old_node_note_array->length(), | |
| 336 0, NULL)); | |
| 337 } | |
| 338 | |
| 339 // Pre-size the new_node table to avoid the need for range checks. | |
| 340 grow_new_node_array(C->unique()); | |
| 341 | |
| 342 // Reset node counter so MachNodes start with _idx at 0 | |
| 343 int nodes = C->unique(); // save value | |
| 344 C->set_unique(0); | |
|
7196
2aff40cb4703
7092905: C2: Keep track of the number of dead nodes
bharadwaj
parents:
6848
diff
changeset
|
345 C->reset_dead_node_list(); |
| 0 | 346 |
| 347 // Recursively match trees from old space into new space. | |
| 348 // Correct leaves of new-space Nodes; they point to old-space. | |
| 349 _visited.Clear(); // Clear visit bits for xform call | |
| 350 C->set_cached_top_node(xform( C->top(), nodes )); | |
| 351 if (!C->failing()) { | |
| 352 Node* xroot = xform( C->root(), 1 ); | |
| 353 if (xroot == NULL) { | |
| 354 Matcher::soft_match_failure(); // recursive matching process failed | |
| 355 C->record_method_not_compilable("instruction match failed"); | |
| 356 } else { | |
| 357 // During matching shared constants were attached to C->root() | |
| 358 // because xroot wasn't available yet, so transfer the uses to | |
| 359 // the xroot. | |
| 360 for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) { | |
| 361 Node* n = C->root()->fast_out(j); | |
| 362 if (C->node_arena()->contains(n)) { | |
| 363 assert(n->in(0) == C->root(), "should be control user"); | |
| 364 n->set_req(0, xroot); | |
| 365 --j; | |
| 366 --jmax; | |
| 367 } | |
| 368 } | |
| 369 | |
|
729
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
681
diff
changeset
|
370 // Generate new mach node for ConP #NULL |
|
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
681
diff
changeset
|
371 assert(new_ideal_null != NULL, "sanity"); |
|
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
681
diff
changeset
|
372 _mach_null = match_tree(new_ideal_null); |
|
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
681
diff
changeset
|
373 // Don't set control, it will confuse GCM since there are no uses. |
|
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
681
diff
changeset
|
374 // The control will be set when this node is used first time |
|
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
681
diff
changeset
|
375 // in find_base_for_derived(). |
|
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
681
diff
changeset
|
376 assert(_mach_null != NULL, ""); |
|
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
681
diff
changeset
|
377 |
| 0 | 378 C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL); |
|
729
04fa5affa478
6709742: find_base_for_derived's use of Ideal NULL is unsafe causing crashes during register allocation
kvn
parents:
681
diff
changeset
|
379 |
| 0 | 380 #ifdef ASSERT |
| 381 verify_new_nodes_only(xroot); | |
| 382 #endif | |
| 383 } | |
| 384 } | |
| 385 if (C->top() == NULL || C->root() == NULL) { | |
| 386 C->record_method_not_compilable("graph lost"); // %%% cannot happen? | |
| 387 } | |
| 388 if (C->failing()) { | |
| 389 // delete old; | |
| 390 old->destruct_contents(); | |
| 391 return; | |
| 392 } | |
| 393 assert( C->top(), "" ); | |
| 394 assert( C->root(), "" ); | |
| 395 validate_null_checks(); | |
| 396 | |
| 397 // Now smoke old-space | |
| 398 NOT_DEBUG( old->destruct_contents() ); | |
| 399 | |
| 400 // ------------------------ | |
| 401 // Set up save-on-entry registers | |
| 402 Fixup_Save_On_Entry( ); | |
| 403 } | |
| 404 | |
| 405 | |
| 406 //------------------------------Fixup_Save_On_Entry---------------------------- | |
| 407 // The stated purpose of this routine is to take care of save-on-entry | |
| 408 // registers. However, the overall goal of the Match phase is to convert into | |
| 409 // machine-specific instructions which have RegMasks to guide allocation. | |
| 410 // So what this procedure really does is put a valid RegMask on each input | |
| 411 // to the machine-specific variations of all Return, TailCall and Halt | |
| 412 // instructions. It also adds edgs to define the save-on-entry values (and of | |
| 413 // course gives them a mask). | |
| 414 | |
| 415 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) { | |
| 416 RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size ); | |
| 417 // Do all the pre-defined register masks | |
| 418 rms[TypeFunc::Control ] = RegMask::Empty; | |
| 419 rms[TypeFunc::I_O ] = RegMask::Empty; | |
| 420 rms[TypeFunc::Memory ] = RegMask::Empty; | |
| 421 rms[TypeFunc::ReturnAdr] = ret_adr; | |
| 422 rms[TypeFunc::FramePtr ] = fp; | |
| 423 return rms; | |
| 424 } | |
| 425 | |
| 426 //---------------------------init_first_stack_mask----------------------------- | |
| 427 // Create the initial stack mask used by values spilling to the stack. | |
| 428 // Disallow any debug info in outgoing argument areas by setting the | |
| 429 // initial mask accordingly. | |
| 430 void Matcher::init_first_stack_mask() { | |
| 431 | |
| 432 // Allocate storage for spill masks as masks for the appropriate load type. | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
433 RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * (3*6+4)); |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
434 |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
435 idealreg2spillmask [Op_RegN] = &rms[0]; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
436 idealreg2spillmask [Op_RegI] = &rms[1]; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
437 idealreg2spillmask [Op_RegL] = &rms[2]; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
438 idealreg2spillmask [Op_RegF] = &rms[3]; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
439 idealreg2spillmask [Op_RegD] = &rms[4]; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
440 idealreg2spillmask [Op_RegP] = &rms[5]; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
441 |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
442 idealreg2debugmask [Op_RegN] = &rms[6]; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
443 idealreg2debugmask [Op_RegI] = &rms[7]; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
444 idealreg2debugmask [Op_RegL] = &rms[8]; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
445 idealreg2debugmask [Op_RegF] = &rms[9]; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
446 idealreg2debugmask [Op_RegD] = &rms[10]; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
447 idealreg2debugmask [Op_RegP] = &rms[11]; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
448 |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
449 idealreg2mhdebugmask[Op_RegN] = &rms[12]; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
450 idealreg2mhdebugmask[Op_RegI] = &rms[13]; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
451 idealreg2mhdebugmask[Op_RegL] = &rms[14]; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
452 idealreg2mhdebugmask[Op_RegF] = &rms[15]; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
453 idealreg2mhdebugmask[Op_RegD] = &rms[16]; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
454 idealreg2mhdebugmask[Op_RegP] = &rms[17]; |
| 0 | 455 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
456 idealreg2spillmask [Op_VecS] = &rms[18]; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
457 idealreg2spillmask [Op_VecD] = &rms[19]; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
458 idealreg2spillmask [Op_VecX] = &rms[20]; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
459 idealreg2spillmask [Op_VecY] = &rms[21]; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
460 |
| 0 | 461 OptoReg::Name i; |
| 462 | |
| 463 // At first, start with the empty mask | |
| 464 C->FIRST_STACK_mask().Clear(); | |
| 465 | |
| 466 // Add in the incoming argument area | |
| 467 OptoReg::Name init = OptoReg::add(_old_SP, C->out_preserve_stack_slots()); | |
| 468 for (i = init; i < _in_arg_limit; i = OptoReg::add(i,1)) | |
| 469 C->FIRST_STACK_mask().Insert(i); | |
| 470 | |
| 471 // Add in all bits past the outgoing argument area | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
472 guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)), |
| 0 | 473 "must be able to represent all call arguments in reg mask"); |
| 474 init = _out_arg_limit; | |
| 475 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) | |
| 476 C->FIRST_STACK_mask().Insert(i); | |
| 477 | |
| 478 // Finally, set the "infinite stack" bit. | |
| 479 C->FIRST_STACK_mask().set_AllStack(); | |
| 480 | |
| 481 // Make spill masks. Registers for their class, plus FIRST_STACK_mask. | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
482 RegMask aligned_stack_mask = C->FIRST_STACK_mask(); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
483 // Keep spill masks aligned. |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
484 aligned_stack_mask.clear_to_pairs(); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
485 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
486 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
487 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP]; |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
63
diff
changeset
|
488 #ifdef _LP64 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
63
diff
changeset
|
489 *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN]; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
63
diff
changeset
|
490 idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask()); |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
491 idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
492 #else |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
493 idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask()); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
63
diff
changeset
|
494 #endif |
| 0 | 495 *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI]; |
| 496 idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask()); | |
| 497 *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL]; | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
498 idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask); |
| 0 | 499 *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF]; |
| 500 idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask()); | |
| 501 *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD]; | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
502 idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask); |
| 0 | 503 |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
504 if (Matcher::vector_size_supported(T_BYTE,4)) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
505 *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS]; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
506 idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask()); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
507 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
508 if (Matcher::vector_size_supported(T_FLOAT,2)) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
509 *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD]; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
510 idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
511 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
512 if (Matcher::vector_size_supported(T_FLOAT,4)) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
513 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
514 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
515 *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX]; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
516 idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
517 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
518 if (Matcher::vector_size_supported(T_FLOAT,8)) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
519 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
520 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
521 *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY]; |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
522 idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
523 } |
|
1730
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
524 if (UseFPUForSpilling) { |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
525 // This mask logic assumes that the spill operations are |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
526 // symmetric and that the registers involved are the same size. |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
527 // On sparc for instance we may have to use 64 bit moves will |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
528 // kill 2 registers when used with F0-F31. |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
529 idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]); |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
530 idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]); |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
531 #ifdef _LP64 |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
532 idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]); |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
533 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]); |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
534 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]); |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
535 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]); |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
536 #else |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
537 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]); |
| 3909 | 538 #ifdef ARM |
| 539 // ARM has support for moving 64bit values between a pair of | |
| 540 // integer registers and a double register | |
| 541 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]); | |
| 542 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]); | |
| 543 #endif | |
|
1730
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
544 #endif |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
545 } |
|
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1579
diff
changeset
|
546 |
| 0 | 547 // Make up debug masks. Any spill slot plus callee-save registers. |
| 548 // Caller-save registers are assumed to be trashable by the various | |
| 549 // inline-cache fixup routines. | |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
550 *idealreg2debugmask [Op_RegN]= *idealreg2spillmask[Op_RegN]; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
551 *idealreg2debugmask [Op_RegI]= *idealreg2spillmask[Op_RegI]; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
552 *idealreg2debugmask [Op_RegL]= *idealreg2spillmask[Op_RegL]; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
553 *idealreg2debugmask [Op_RegF]= *idealreg2spillmask[Op_RegF]; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
554 *idealreg2debugmask [Op_RegD]= *idealreg2spillmask[Op_RegD]; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
555 *idealreg2debugmask [Op_RegP]= *idealreg2spillmask[Op_RegP]; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
556 |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
557 *idealreg2mhdebugmask[Op_RegN]= *idealreg2spillmask[Op_RegN]; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
558 *idealreg2mhdebugmask[Op_RegI]= *idealreg2spillmask[Op_RegI]; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
559 *idealreg2mhdebugmask[Op_RegL]= *idealreg2spillmask[Op_RegL]; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
560 *idealreg2mhdebugmask[Op_RegF]= *idealreg2spillmask[Op_RegF]; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
561 *idealreg2mhdebugmask[Op_RegD]= *idealreg2spillmask[Op_RegD]; |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
562 *idealreg2mhdebugmask[Op_RegP]= *idealreg2spillmask[Op_RegP]; |
| 0 | 563 |
| 564 // Prevent stub compilations from attempting to reference | |
| 565 // callee-saved registers from debug info | |
| 566 bool exclude_soe = !Compile::current()->is_method_compilation(); | |
| 567 | |
| 568 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) { | |
| 569 // registers the caller has to save do not work | |
| 570 if( _register_save_policy[i] == 'C' || | |
| 571 _register_save_policy[i] == 'A' || | |
| 572 (_register_save_policy[i] == 'E' && exclude_soe) ) { | |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
573 idealreg2debugmask [Op_RegN]->Remove(i); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
574 idealreg2debugmask [Op_RegI]->Remove(i); // Exclude save-on-call |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
575 idealreg2debugmask [Op_RegL]->Remove(i); // registers from debug |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
576 idealreg2debugmask [Op_RegF]->Remove(i); // masks |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
577 idealreg2debugmask [Op_RegD]->Remove(i); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
578 idealreg2debugmask [Op_RegP]->Remove(i); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
579 |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
580 idealreg2mhdebugmask[Op_RegN]->Remove(i); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
581 idealreg2mhdebugmask[Op_RegI]->Remove(i); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
582 idealreg2mhdebugmask[Op_RegL]->Remove(i); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
583 idealreg2mhdebugmask[Op_RegF]->Remove(i); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
584 idealreg2mhdebugmask[Op_RegD]->Remove(i); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
585 idealreg2mhdebugmask[Op_RegP]->Remove(i); |
| 0 | 586 } |
| 587 } | |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
588 |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
589 // Subtract the register we use to save the SP for MethodHandle |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
590 // invokes to from the debug mask. |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
591 const RegMask save_mask = method_handle_invoke_SP_save_mask(); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
592 idealreg2mhdebugmask[Op_RegN]->SUBTRACT(save_mask); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
593 idealreg2mhdebugmask[Op_RegI]->SUBTRACT(save_mask); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
594 idealreg2mhdebugmask[Op_RegL]->SUBTRACT(save_mask); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
595 idealreg2mhdebugmask[Op_RegF]->SUBTRACT(save_mask); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
596 idealreg2mhdebugmask[Op_RegD]->SUBTRACT(save_mask); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
597 idealreg2mhdebugmask[Op_RegP]->SUBTRACT(save_mask); |
| 0 | 598 } |
| 599 | |
| 600 //---------------------------is_save_on_entry---------------------------------- | |
| 601 bool Matcher::is_save_on_entry( int reg ) { | |
| 602 return | |
| 603 _register_save_policy[reg] == 'E' || | |
| 604 _register_save_policy[reg] == 'A' || // Save-on-entry register? | |
| 605 // Also save argument registers in the trampolining stubs | |
| 606 (C->save_argument_registers() && is_spillable_arg(reg)); | |
| 607 } | |
| 608 | |
| 609 //---------------------------Fixup_Save_On_Entry------------------------------- | |
| 610 void Matcher::Fixup_Save_On_Entry( ) { | |
| 611 init_first_stack_mask(); | |
| 612 | |
| 613 Node *root = C->root(); // Short name for root | |
| 614 // Count number of save-on-entry registers. | |
| 615 uint soe_cnt = number_of_saved_registers(); | |
| 616 uint i; | |
| 617 | |
| 618 // Find the procedure Start Node | |
| 619 StartNode *start = C->start(); | |
| 620 assert( start, "Expect a start node" ); | |
| 621 | |
| 622 // Save argument registers in the trampolining stubs | |
| 623 if( C->save_argument_registers() ) | |
| 624 for( i = 0; i < _last_Mach_Reg; i++ ) | |
| 625 if( is_spillable_arg(i) ) | |
| 626 soe_cnt++; | |
| 627 | |
| 628 // Input RegMask array shared by all Returns. | |
| 629 // The type for doubles and longs has a count of 2, but | |
| 630 // there is only 1 returned value | |
| 631 uint ret_edge_cnt = TypeFunc::Parms + ((C->tf()->range()->cnt() == TypeFunc::Parms) ? 0 : 1); | |
| 632 RegMask *ret_rms = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); | |
| 633 // Returns have 0 or 1 returned values depending on call signature. | |
| 634 // Return register is specified by return_value in the AD file. | |
| 635 if (ret_edge_cnt > TypeFunc::Parms) | |
| 636 ret_rms[TypeFunc::Parms+0] = _return_value_mask; | |
| 637 | |
| 638 // Input RegMask array shared by all Rethrows. | |
| 639 uint reth_edge_cnt = TypeFunc::Parms+1; | |
| 640 RegMask *reth_rms = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); | |
| 641 // Rethrow takes exception oop only, but in the argument 0 slot. | |
| 642 reth_rms[TypeFunc::Parms] = mreg2regmask[find_receiver(false)]; | |
| 643 #ifdef _LP64 | |
| 644 // Need two slots for ptrs in 64-bit land | |
| 645 reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(find_receiver(false)),1)); | |
| 646 #endif | |
| 647 | |
| 648 // Input RegMask array shared by all TailCalls | |
| 649 uint tail_call_edge_cnt = TypeFunc::Parms+2; | |
| 650 RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); | |
| 651 | |
| 652 // Input RegMask array shared by all TailJumps | |
| 653 uint tail_jump_edge_cnt = TypeFunc::Parms+2; | |
| 654 RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); | |
| 655 | |
| 656 // TailCalls have 2 returned values (target & moop), whose masks come | |
| 657 // from the usual MachNode/MachOper mechanism. Find a sample | |
| 658 // TailCall to extract these masks and put the correct masks into | |
| 659 // the tail_call_rms array. | |
| 660 for( i=1; i < root->req(); i++ ) { | |
| 661 MachReturnNode *m = root->in(i)->as_MachReturn(); | |
| 662 if( m->ideal_Opcode() == Op_TailCall ) { | |
| 663 tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0); | |
| 664 tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1); | |
| 665 break; | |
| 666 } | |
| 667 } | |
| 668 | |
| 669 // TailJumps have 2 returned values (target & ex_oop), whose masks come | |
| 670 // from the usual MachNode/MachOper mechanism. Find a sample | |
| 671 // TailJump to extract these masks and put the correct masks into | |
| 672 // the tail_jump_rms array. | |
| 673 for( i=1; i < root->req(); i++ ) { | |
| 674 MachReturnNode *m = root->in(i)->as_MachReturn(); | |
| 675 if( m->ideal_Opcode() == Op_TailJump ) { | |
| 676 tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0); | |
| 677 tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1); | |
| 678 break; | |
| 679 } | |
| 680 } | |
| 681 | |
| 682 // Input RegMask array shared by all Halts | |
| 683 uint halt_edge_cnt = TypeFunc::Parms; | |
| 684 RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); | |
| 685 | |
| 686 // Capture the return input masks into each exit flavor | |
| 687 for( i=1; i < root->req(); i++ ) { | |
| 688 MachReturnNode *exit = root->in(i)->as_MachReturn(); | |
| 689 switch( exit->ideal_Opcode() ) { | |
| 690 case Op_Return : exit->_in_rms = ret_rms; break; | |
| 691 case Op_Rethrow : exit->_in_rms = reth_rms; break; | |
| 692 case Op_TailCall : exit->_in_rms = tail_call_rms; break; | |
| 693 case Op_TailJump : exit->_in_rms = tail_jump_rms; break; | |
| 694 case Op_Halt : exit->_in_rms = halt_rms; break; | |
| 695 default : ShouldNotReachHere(); | |
| 696 } | |
| 697 } | |
| 698 | |
| 699 // Next unused projection number from Start. | |
| 700 int proj_cnt = C->tf()->domain()->cnt(); | |
| 701 | |
| 702 // Do all the save-on-entry registers. Make projections from Start for | |
| 703 // them, and give them a use at the exit points. To the allocator, they | |
| 704 // look like incoming register arguments. | |
| 705 for( i = 0; i < _last_Mach_Reg; i++ ) { | |
| 706 if( is_save_on_entry(i) ) { | |
| 707 | |
| 708 // Add the save-on-entry to the mask array | |
| 709 ret_rms [ ret_edge_cnt] = mreg2regmask[i]; | |
| 710 reth_rms [ reth_edge_cnt] = mreg2regmask[i]; | |
| 711 tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i]; | |
| 712 tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i]; | |
| 713 // Halts need the SOE registers, but only in the stack as debug info. | |
| 714 // A just-prior uncommon-trap or deoptimization will use the SOE regs. | |
| 715 halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]]; | |
| 716 | |
| 717 Node *mproj; | |
| 718 | |
| 719 // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's | |
| 720 // into a single RegD. | |
| 721 if( (i&1) == 0 && | |
| 722 _register_save_type[i ] == Op_RegF && | |
| 723 _register_save_type[i+1] == Op_RegF && | |
| 724 is_save_on_entry(i+1) ) { | |
| 725 // Add other bit for double | |
| 726 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1)); | |
| 727 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1)); | |
| 728 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1)); | |
| 729 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1)); | |
| 730 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1)); | |
|
6804
e626685e9f6c
7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents:
6795
diff
changeset
|
731 mproj = new (C) MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD ); |
| 0 | 732 proj_cnt += 2; // Skip 2 for doubles |
| 733 } | |
| 734 else if( (i&1) == 1 && // Else check for high half of double | |
| 735 _register_save_type[i-1] == Op_RegF && | |
| 736 _register_save_type[i ] == Op_RegF && | |
| 737 is_save_on_entry(i-1) ) { | |
| 738 ret_rms [ ret_edge_cnt] = RegMask::Empty; | |
| 739 reth_rms [ reth_edge_cnt] = RegMask::Empty; | |
| 740 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty; | |
| 741 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty; | |
| 742 halt_rms [ halt_edge_cnt] = RegMask::Empty; | |
| 743 mproj = C->top(); | |
| 744 } | |
| 745 // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's | |
| 746 // into a single RegL. | |
| 747 else if( (i&1) == 0 && | |
| 748 _register_save_type[i ] == Op_RegI && | |
| 749 _register_save_type[i+1] == Op_RegI && | |
| 750 is_save_on_entry(i+1) ) { | |
| 751 // Add other bit for long | |
| 752 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1)); | |
| 753 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1)); | |
| 754 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1)); | |
| 755 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1)); | |
| 756 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1)); | |
|
6804
e626685e9f6c
7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents:
6795
diff
changeset
|
757 mproj = new (C) MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL ); |
| 0 | 758 proj_cnt += 2; // Skip 2 for longs |
| 759 } | |
| 760 else if( (i&1) == 1 && // Else check for high half of long | |
| 761 _register_save_type[i-1] == Op_RegI && | |
| 762 _register_save_type[i ] == Op_RegI && | |
| 763 is_save_on_entry(i-1) ) { | |
| 764 ret_rms [ ret_edge_cnt] = RegMask::Empty; | |
| 765 reth_rms [ reth_edge_cnt] = RegMask::Empty; | |
| 766 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty; | |
| 767 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty; | |
| 768 halt_rms [ halt_edge_cnt] = RegMask::Empty; | |
| 769 mproj = C->top(); | |
| 770 } else { | |
| 771 // Make a projection for it off the Start | |
|
6804
e626685e9f6c
7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents:
6795
diff
changeset
|
772 mproj = new (C) MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] ); |
| 0 | 773 } |
| 774 | |
| 775 ret_edge_cnt ++; | |
| 776 reth_edge_cnt ++; | |
| 777 tail_call_edge_cnt ++; | |
| 778 tail_jump_edge_cnt ++; | |
| 779 halt_edge_cnt ++; | |
| 780 | |
| 781 // Add a use of the SOE register to all exit paths | |
| 782 for( uint j=1; j < root->req(); j++ ) | |
| 783 root->in(j)->add_req(mproj); | |
| 784 } // End of if a save-on-entry register | |
| 785 } // End of for all machine registers | |
| 786 } | |
| 787 | |
| 788 //------------------------------init_spill_mask-------------------------------- | |
| 789 void Matcher::init_spill_mask( Node *ret ) { | |
| 790 if( idealreg2regmask[Op_RegI] ) return; // One time only init | |
| 791 | |
| 792 OptoReg::c_frame_pointer = c_frame_pointer(); | |
| 793 c_frame_ptr_mask = c_frame_pointer(); | |
| 794 #ifdef _LP64 | |
| 795 // pointers are twice as big | |
| 796 c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1)); | |
| 797 #endif | |
| 798 | |
| 799 // Start at OptoReg::stack0() | |
| 800 STACK_ONLY_mask.Clear(); | |
| 801 OptoReg::Name init = OptoReg::stack2reg(0); | |
| 802 // STACK_ONLY_mask is all stack bits | |
| 803 OptoReg::Name i; | |
| 804 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) | |
| 805 STACK_ONLY_mask.Insert(i); | |
| 806 // Also set the "infinite stack" bit. | |
| 807 STACK_ONLY_mask.set_AllStack(); | |
| 808 | |
| 809 // Copy the register names over into the shared world | |
| 810 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) { | |
| 811 // SharedInfo::regName[i] = regName[i]; | |
| 812 // Handy RegMasks per machine register | |
| 813 mreg2regmask[i].Insert(i); | |
| 814 } | |
| 815 | |
| 816 // Grab the Frame Pointer | |
| 817 Node *fp = ret->in(TypeFunc::FramePtr); | |
| 818 Node *mem = ret->in(TypeFunc::Memory); | |
| 819 const TypePtr* atp = TypePtr::BOTTOM; | |
| 820 // Share frame pointer while making spill ops | |
| 821 set_shared(fp); | |
| 822 | |
| 823 // Compute generic short-offset Loads | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
63
diff
changeset
|
824 #ifdef _LP64 |
|
6804
e626685e9f6c
7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents:
6795
diff
changeset
|
825 MachNode *spillCP = match_tree(new (C) LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM)); |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
63
diff
changeset
|
826 #endif |
|
6804
e626685e9f6c
7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents:
6795
diff
changeset
|
827 MachNode *spillI = match_tree(new (C) LoadINode(NULL,mem,fp,atp)); |
|
e626685e9f6c
7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents:
6795
diff
changeset
|
828 MachNode *spillL = match_tree(new (C) LoadLNode(NULL,mem,fp,atp)); |
|
e626685e9f6c
7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents:
6795
diff
changeset
|
829 MachNode *spillF = match_tree(new (C) LoadFNode(NULL,mem,fp,atp)); |
|
e626685e9f6c
7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents:
6795
diff
changeset
|
830 MachNode *spillD = match_tree(new (C) LoadDNode(NULL,mem,fp,atp)); |
|
e626685e9f6c
7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents:
6795
diff
changeset
|
831 MachNode *spillP = match_tree(new (C) LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM)); |
| 0 | 832 assert(spillI != NULL && spillL != NULL && spillF != NULL && |
| 833 spillD != NULL && spillP != NULL, ""); | |
| 834 | |
| 835 // Get the ADLC notion of the right regmask, for each basic type. | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
63
diff
changeset
|
836 #ifdef _LP64 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
63
diff
changeset
|
837 idealreg2regmask[Op_RegN] = &spillCP->out_RegMask(); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
63
diff
changeset
|
838 #endif |
| 0 | 839 idealreg2regmask[Op_RegI] = &spillI->out_RegMask(); |
| 840 idealreg2regmask[Op_RegL] = &spillL->out_RegMask(); | |
| 841 idealreg2regmask[Op_RegF] = &spillF->out_RegMask(); | |
| 842 idealreg2regmask[Op_RegD] = &spillD->out_RegMask(); | |
| 843 idealreg2regmask[Op_RegP] = &spillP->out_RegMask(); | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
844 |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
845 // Vector regmasks. |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
846 if (Matcher::vector_size_supported(T_BYTE,4)) { |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
847 TypeVect::VECTS = TypeVect::make(T_BYTE, 4); |
|
6804
e626685e9f6c
7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents:
6795
diff
changeset
|
848 MachNode *spillVectS = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS)); |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
849 idealreg2regmask[Op_VecS] = &spillVectS->out_RegMask(); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
850 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
851 if (Matcher::vector_size_supported(T_FLOAT,2)) { |
|
6804
e626685e9f6c
7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents:
6795
diff
changeset
|
852 MachNode *spillVectD = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTD)); |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
853 idealreg2regmask[Op_VecD] = &spillVectD->out_RegMask(); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
854 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
855 if (Matcher::vector_size_supported(T_FLOAT,4)) { |
|
6804
e626685e9f6c
7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents:
6795
diff
changeset
|
856 MachNode *spillVectX = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTX)); |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
857 idealreg2regmask[Op_VecX] = &spillVectX->out_RegMask(); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
858 } |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
859 if (Matcher::vector_size_supported(T_FLOAT,8)) { |
|
6804
e626685e9f6c
7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents:
6795
diff
changeset
|
860 MachNode *spillVectY = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTY)); |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
861 idealreg2regmask[Op_VecY] = &spillVectY->out_RegMask(); |
|
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
862 } |
| 0 | 863 } |
| 864 | |
| 865 #ifdef ASSERT | |
| 866 static void match_alias_type(Compile* C, Node* n, Node* m) { | |
| 867 if (!VerifyAliases) return; // do not go looking for trouble by default | |
| 868 const TypePtr* nat = n->adr_type(); | |
| 869 const TypePtr* mat = m->adr_type(); | |
| 870 int nidx = C->get_alias_index(nat); | |
| 871 int midx = C->get_alias_index(mat); | |
| 872 // Detune the assert for cases like (AndI 0xFF (LoadB p)). | |
| 873 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) { | |
| 874 for (uint i = 1; i < n->req(); i++) { | |
| 875 Node* n1 = n->in(i); | |
| 876 const TypePtr* n1at = n1->adr_type(); | |
| 877 if (n1at != NULL) { | |
| 878 nat = n1at; | |
| 879 nidx = C->get_alias_index(n1at); | |
| 880 } | |
| 881 } | |
| 882 } | |
| 883 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases: | |
| 884 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) { | |
| 885 switch (n->Opcode()) { | |
| 886 case Op_PrefetchRead: | |
| 887 case Op_PrefetchWrite: | |
| 3854 | 888 case Op_PrefetchAllocation: |
| 0 | 889 nidx = Compile::AliasIdxRaw; |
| 890 nat = TypeRawPtr::BOTTOM; | |
| 891 break; | |
| 892 } | |
| 893 } | |
| 894 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) { | |
| 895 switch (n->Opcode()) { | |
| 896 case Op_ClearArray: | |
| 897 midx = Compile::AliasIdxRaw; | |
| 898 mat = TypeRawPtr::BOTTOM; | |
| 899 break; | |
| 900 } | |
| 901 } | |
| 902 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) { | |
| 903 switch (n->Opcode()) { | |
| 904 case Op_Return: | |
| 905 case Op_Rethrow: | |
| 906 case Op_Halt: | |
| 907 case Op_TailCall: | |
| 908 case Op_TailJump: | |
| 909 nidx = Compile::AliasIdxBot; | |
| 910 nat = TypePtr::BOTTOM; | |
| 911 break; | |
| 912 } | |
| 913 } | |
| 914 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) { | |
| 915 switch (n->Opcode()) { | |
| 916 case Op_StrComp: | |
| 681 | 917 case Op_StrEquals: |
| 918 case Op_StrIndexOf: | |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
168
diff
changeset
|
919 case Op_AryEq: |
| 0 | 920 case Op_MemBarVolatile: |
| 921 case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type? | |
|
7637
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7196
diff
changeset
|
922 case Op_EncodeISOArray: |
| 0 | 923 nidx = Compile::AliasIdxTop; |
| 924 nat = NULL; | |
| 925 break; | |
| 926 } | |
| 927 } | |
| 928 if (nidx != midx) { | |
| 929 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) { | |
| 930 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx); | |
| 931 n->dump(); | |
| 932 m->dump(); | |
| 933 } | |
| 934 assert(C->subsume_loads() && C->must_alias(nat, midx), | |
| 935 "must not lose alias info when matching"); | |
| 936 } | |
| 937 } | |
| 938 #endif | |
| 939 | |
| 940 | |
| 941 //------------------------------MStack----------------------------------------- | |
| 942 // State and MStack class used in xform() and find_shared() iterative methods. | |
| 943 enum Node_State { Pre_Visit, // node has to be pre-visited | |
| 944 Visit, // visit node | |
| 945 Post_Visit, // post-visit node | |
| 946 Alt_Post_Visit // alternative post-visit path | |
| 947 }; | |
| 948 | |
| 949 class MStack: public Node_Stack { | |
| 950 public: | |
| 951 MStack(int size) : Node_Stack(size) { } | |
| 952 | |
| 953 void push(Node *n, Node_State ns) { | |
| 954 Node_Stack::push(n, (uint)ns); | |
| 955 } | |
| 956 void push(Node *n, Node_State ns, Node *parent, int indx) { | |
| 957 ++_inode_top; | |
| 958 if ((_inode_top + 1) >= _inode_max) grow(); | |
| 959 _inode_top->node = parent; | |
| 960 _inode_top->indx = (uint)indx; | |
| 961 ++_inode_top; | |
| 962 _inode_top->node = n; | |
| 963 _inode_top->indx = (uint)ns; | |
| 964 } | |
| 965 Node *parent() { | |
| 966 pop(); | |
| 967 return node(); | |
| 968 } | |
| 969 Node_State state() const { | |
| 970 return (Node_State)index(); | |
| 971 } | |
| 972 void set_state(Node_State ns) { | |
| 973 set_index((uint)ns); | |
| 974 } | |
| 975 }; | |
| 976 | |
| 977 | |
| 978 //------------------------------xform------------------------------------------ | |
| 979 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine | |
| 980 // Node in new-space. Given a new-space Node, recursively walk his children. | |
| 981 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; } | |
| 982 Node *Matcher::xform( Node *n, int max_stack ) { | |
| 983 // Use one stack to keep both: child's node/state and parent's node/index | |
| 984 MStack mstack(max_stack * 2 * 2); // C->unique() * 2 * 2 | |
| 985 mstack.push(n, Visit, NULL, -1); // set NULL as parent to indicate root | |
| 986 | |
| 987 while (mstack.is_nonempty()) { | |
| 988 n = mstack.node(); // Leave node on stack | |
| 989 Node_State nstate = mstack.state(); | |
| 990 if (nstate == Visit) { | |
| 991 mstack.set_state(Post_Visit); | |
| 992 Node *oldn = n; | |
| 993 // Old-space or new-space check | |
| 994 if (!C->node_arena()->contains(n)) { | |
| 995 // Old space! | |
| 996 Node* m; | |
| 997 if (has_new_node(n)) { // Not yet Label/Reduced | |
| 998 m = new_node(n); | |
| 999 } else { | |
| 1000 if (!is_dontcare(n)) { // Matcher can match this guy | |
| 1001 // Calls match special. They match alone with no children. | |
| 1002 // Their children, the incoming arguments, match normally. | |
| 1003 m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n); | |
| 1004 if (C->failing()) return NULL; | |
| 1005 if (m == NULL) { Matcher::soft_match_failure(); return NULL; } | |
| 1006 } else { // Nothing the matcher cares about | |
| 1007 if( n->is_Proj() && n->in(0)->is_Multi()) { // Projections? | |
| 1008 // Convert to machine-dependent projection | |
| 1009 m = n->in(0)->as_Multi()->match( n->as_Proj(), this ); | |
| 222 | 1010 #ifdef ASSERT |
| 1011 _new2old_map.map(m->_idx, n); | |
| 1012 #endif | |
| 0 | 1013 if (m->in(0) != NULL) // m might be top |
|
368
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
1014 collect_null_checks(m, n); |
| 0 | 1015 } else { // Else just a regular 'ol guy |
| 1016 m = n->clone(); // So just clone into new-space | |
| 222 | 1017 #ifdef ASSERT |
| 1018 _new2old_map.map(m->_idx, n); | |
| 1019 #endif | |
| 0 | 1020 // Def-Use edges will be added incrementally as Uses |
| 1021 // of this node are matched. | |
| 1022 assert(m->outcnt() == 0, "no Uses of this clone yet"); | |
| 1023 } | |
| 1024 } | |
| 1025 | |
| 1026 set_new_node(n, m); // Map old to new | |
| 1027 if (_old_node_note_array != NULL) { | |
| 1028 Node_Notes* nn = C->locate_node_notes(_old_node_note_array, | |
| 1029 n->_idx); | |
| 1030 C->set_node_notes_at(m->_idx, nn); | |
| 1031 } | |
| 1032 debug_only(match_alias_type(C, n, m)); | |
| 1033 } | |
| 1034 n = m; // n is now a new-space node | |
| 1035 mstack.set_node(n); | |
| 1036 } | |
| 1037 | |
| 1038 // New space! | |
| 1039 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty()) | |
| 1040 | |
| 1041 int i; | |
| 1042 // Put precedence edges on stack first (match them last). | |
| 1043 for (i = oldn->req(); (uint)i < oldn->len(); i++) { | |
| 1044 Node *m = oldn->in(i); | |
| 1045 if (m == NULL) break; | |
| 1046 // set -1 to call add_prec() instead of set_req() during Step1 | |
| 1047 mstack.push(m, Visit, n, -1); | |
| 1048 } | |
| 1049 | |
| 1050 // For constant debug info, I'd rather have unmatched constants. | |
| 1051 int cnt = n->req(); | |
| 1052 JVMState* jvms = n->jvms(); | |
| 1053 int debug_cnt = jvms ? jvms->debug_start() : cnt; | |
| 1054 | |
| 1055 // Now do only debug info. Clone constants rather than matching. | |
| 1056 // Constants are represented directly in the debug info without | |
| 1057 // the need for executable machine instructions. | |
| 1058 // Monitor boxes are also represented directly. | |
| 1059 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do | |
| 1060 Node *m = n->in(i); // Get input | |
| 1061 int op = m->Opcode(); | |
| 1062 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites"); | |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6804
diff
changeset
|
1063 if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass || |
| 0 | 1064 op == Op_ConF || op == Op_ConD || op == Op_ConL |
| 1065 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp | |
| 1066 ) { | |
| 1067 m = m->clone(); | |
| 222 | 1068 #ifdef ASSERT |
| 1069 _new2old_map.map(m->_idx, n); | |
| 1070 #endif | |
| 605 | 1071 mstack.push(m, Post_Visit, n, i); // Don't need to visit |
| 0 | 1072 mstack.push(m->in(0), Visit, m, 0); |
| 1073 } else { | |
| 1074 mstack.push(m, Visit, n, i); | |
| 1075 } | |
| 1076 } | |
| 1077 | |
| 1078 // And now walk his children, and convert his inputs to new-space. | |
| 1079 for( ; i >= 0; --i ) { // For all normal inputs do | |
| 1080 Node *m = n->in(i); // Get input | |
| 1081 if(m != NULL) | |
| 1082 mstack.push(m, Visit, n, i); | |
| 1083 } | |
| 1084 | |
| 1085 } | |
| 1086 else if (nstate == Post_Visit) { | |
| 1087 // Set xformed input | |
| 1088 Node *p = mstack.parent(); | |
| 1089 if (p != NULL) { // root doesn't have parent | |
| 1090 int i = (int)mstack.index(); | |
| 1091 if (i >= 0) | |
| 1092 p->set_req(i, n); // required input | |
| 1093 else if (i == -1) | |
| 1094 p->add_prec(n); // precedence input | |
| 1095 else | |
| 1096 ShouldNotReachHere(); | |
| 1097 } | |
| 1098 mstack.pop(); // remove processed node from stack | |
| 1099 } | |
| 1100 else { | |
| 1101 ShouldNotReachHere(); | |
| 1102 } | |
| 1103 } // while (mstack.is_nonempty()) | |
| 1104 return n; // Return new-space Node | |
| 1105 } | |
| 1106 | |
| 1107 //------------------------------warp_outgoing_stk_arg------------------------ | |
| 1108 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) { | |
| 1109 // Convert outgoing argument location to a pre-biased stack offset | |
| 1110 if (reg->is_stack()) { | |
| 1111 OptoReg::Name warped = reg->reg2stack(); | |
| 1112 // Adjust the stack slot offset to be the register number used | |
| 1113 // by the allocator. | |
| 1114 warped = OptoReg::add(begin_out_arg_area, warped); | |
| 1115 // Keep track of the largest numbered stack slot used for an arg. | |
| 1116 // Largest used slot per call-site indicates the amount of stack | |
| 1117 // that is killed by the call. | |
| 1118 if( warped >= out_arg_limit_per_call ) | |
| 1119 out_arg_limit_per_call = OptoReg::add(warped,1); | |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
1120 if (!RegMask::can_represent_arg(warped)) { |
| 0 | 1121 C->record_method_not_compilable_all_tiers("unsupported calling sequence"); |
| 1122 return OptoReg::Bad; | |
| 1123 } | |
| 1124 return warped; | |
| 1125 } | |
| 1126 return OptoReg::as_OptoReg(reg); | |
| 1127 } | |
| 1128 | |
| 1129 | |
| 1130 //------------------------------match_sfpt------------------------------------- | |
| 1131 // Helper function to match call instructions. Calls match special. | |
| 1132 // They match alone with no children. Their children, the incoming | |
| 1133 // arguments, match normally. | |
| 1134 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) { | |
| 1135 MachSafePointNode *msfpt = NULL; | |
| 1136 MachCallNode *mcall = NULL; | |
| 1137 uint cnt; | |
| 1138 // Split out case for SafePoint vs Call | |
| 1139 CallNode *call; | |
| 1140 const TypeTuple *domain; | |
| 1141 ciMethod* method = NULL; | |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
1142 bool is_method_handle_invoke = false; // for special kill effects |
| 0 | 1143 if( sfpt->is_Call() ) { |
| 1144 call = sfpt->as_Call(); | |
| 1145 domain = call->tf()->domain(); | |
| 1146 cnt = domain->cnt(); | |
| 1147 | |
| 1148 // Match just the call, nothing else | |
| 1149 MachNode *m = match_tree(call); | |
| 1150 if (C->failing()) return NULL; | |
| 1151 if( m == NULL ) { Matcher::soft_match_failure(); return NULL; } | |
| 1152 | |
| 1153 // Copy data from the Ideal SafePoint to the machine version | |
| 1154 mcall = m->as_MachCall(); | |
| 1155 | |
| 1156 mcall->set_tf( call->tf()); | |
| 1157 mcall->set_entry_point(call->entry_point()); | |
| 1158 mcall->set_cnt( call->cnt()); | |
| 1159 | |
| 1160 if( mcall->is_MachCallJava() ) { | |
| 1161 MachCallJavaNode *mcall_java = mcall->as_MachCallJava(); | |
| 1162 const CallJavaNode *call_java = call->as_CallJava(); | |
| 1163 method = call_java->method(); | |
| 1164 mcall_java->_method = method; | |
| 1165 mcall_java->_bci = call_java->_bci; | |
| 1166 mcall_java->_optimized_virtual = call_java->is_optimized_virtual(); | |
|
1137
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
1167 is_method_handle_invoke = call_java->is_method_handle_invoke(); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
1061
diff
changeset
|
1168 mcall_java->_method_handle_invoke = is_method_handle_invoke; |
|
3905
c26de9aef2ed
7071307: MethodHandle bimorphic inlining should consider the frequency
never
parents:
3854
diff
changeset
|
1169 if (is_method_handle_invoke) { |
|
c26de9aef2ed
7071307: MethodHandle bimorphic inlining should consider the frequency
never
parents:
3854
diff
changeset
|
1170 C->set_has_method_handle_invokes(true); |
|
c26de9aef2ed
7071307: MethodHandle bimorphic inlining should consider the frequency
never
parents:
3854
diff
changeset
|
1171 } |
| 0 | 1172 if( mcall_java->is_MachCallStaticJava() ) |
| 1173 mcall_java->as_MachCallStaticJava()->_name = | |
| 1174 call_java->as_CallStaticJava()->_name; | |
| 1175 if( mcall_java->is_MachCallDynamicJava() ) | |
| 1176 mcall_java->as_MachCallDynamicJava()->_vtable_index = | |
| 1177 call_java->as_CallDynamicJava()->_vtable_index; | |
| 1178 } | |
| 1179 else if( mcall->is_MachCallRuntime() ) { | |
| 1180 mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name; | |
| 1181 } | |
| 1182 msfpt = mcall; | |
| 1183 } | |
| 1184 // This is a non-call safepoint | |
| 1185 else { | |
| 1186 call = NULL; | |
| 1187 domain = NULL; | |
| 1188 MachNode *mn = match_tree(sfpt); | |
| 1189 if (C->failing()) return NULL; | |
| 1190 msfpt = mn->as_MachSafePoint(); | |
| 1191 cnt = TypeFunc::Parms; | |
| 1192 } | |
| 1193 | |
| 1194 // Advertise the correct memory effects (for anti-dependence computation). | |
| 1195 msfpt->set_adr_type(sfpt->adr_type()); | |
| 1196 | |
| 1197 // Allocate a private array of RegMasks. These RegMasks are not shared. | |
| 1198 msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt ); | |
| 1199 // Empty them all. | |
| 1200 memset( msfpt->_in_rms, 0, sizeof(RegMask)*cnt ); | |
| 1201 | |
| 1202 // Do all the pre-defined non-Empty register masks | |
| 1203 msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask; | |
| 1204 msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask; | |
| 1205 | |
| 1206 // Place first outgoing argument can possibly be put. | |
| 1207 OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots()); | |
| 1208 assert( is_even(begin_out_arg_area), "" ); | |
| 1209 // Compute max outgoing register number per call site. | |
| 1210 OptoReg::Name out_arg_limit_per_call = begin_out_arg_area; | |
| 1211 // Calls to C may hammer extra stack slots above and beyond any arguments. | |
| 1212 // These are usually backing store for register arguments for varargs. | |
| 1213 if( call != NULL && call->is_CallRuntime() ) | |
| 1214 out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed()); | |
| 1215 | |
| 1216 | |
| 1217 // Do the normal argument list (parameters) register masks | |
| 1218 int argcnt = cnt - TypeFunc::Parms; | |
| 1219 if( argcnt > 0 ) { // Skip it all if we have no args | |
| 1220 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt ); | |
| 1221 VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt ); | |
| 1222 int i; | |
| 1223 for( i = 0; i < argcnt; i++ ) { | |
| 1224 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type(); | |
| 1225 } | |
| 1226 // V-call to pick proper calling convention | |
| 1227 call->calling_convention( sig_bt, parm_regs, argcnt ); | |
| 1228 | |
| 1229 #ifdef ASSERT | |
| 1230 // Sanity check users' calling convention. Really handy during | |
| 1231 // the initial porting effort. Fairly expensive otherwise. | |
| 1232 { for (int i = 0; i<argcnt; i++) { | |
| 1233 if( !parm_regs[i].first()->is_valid() && | |
| 1234 !parm_regs[i].second()->is_valid() ) continue; | |
| 1235 VMReg reg1 = parm_regs[i].first(); | |
| 1236 VMReg reg2 = parm_regs[i].second(); | |
| 1237 for (int j = 0; j < i; j++) { | |
| 1238 if( !parm_regs[j].first()->is_valid() && | |
| 1239 !parm_regs[j].second()->is_valid() ) continue; | |
| 1240 VMReg reg3 = parm_regs[j].first(); | |
| 1241 VMReg reg4 = parm_regs[j].second(); | |
| 1242 if( !reg1->is_valid() ) { | |
| 1243 assert( !reg2->is_valid(), "valid halvsies" ); | |
| 1244 } else if( !reg3->is_valid() ) { | |
| 1245 assert( !reg4->is_valid(), "valid halvsies" ); | |
| 1246 } else { | |
| 1247 assert( reg1 != reg2, "calling conv. must produce distinct regs"); | |
| 1248 assert( reg1 != reg3, "calling conv. must produce distinct regs"); | |
| 1249 assert( reg1 != reg4, "calling conv. must produce distinct regs"); | |
| 1250 assert( reg2 != reg3, "calling conv. must produce distinct regs"); | |
| 1251 assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs"); | |
| 1252 assert( reg3 != reg4, "calling conv. must produce distinct regs"); | |
| 1253 } | |
| 1254 } | |
| 1255 } | |
| 1256 } | |
| 1257 #endif | |
| 1258 | |
| 1259 // Visit each argument. Compute its outgoing register mask. | |
| 1260 // Return results now can have 2 bits returned. | |
| 1261 // Compute max over all outgoing arguments both per call-site | |
| 1262 // and over the entire method. | |
| 1263 for( i = 0; i < argcnt; i++ ) { | |
| 1264 // Address of incoming argument mask to fill in | |
| 1265 RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms]; | |
| 1266 if( !parm_regs[i].first()->is_valid() && | |
| 1267 !parm_regs[i].second()->is_valid() ) { | |
| 1268 continue; // Avoid Halves | |
| 1269 } | |
| 1270 // Grab first register, adjust stack slots and insert in mask. | |
| 1271 OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call ); | |
| 1272 if (OptoReg::is_valid(reg1)) | |
| 1273 rm->Insert( reg1 ); | |
| 1274 // Grab second register (if any), adjust stack slots and insert in mask. | |
| 1275 OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call ); | |
| 1276 if (OptoReg::is_valid(reg2)) | |
| 1277 rm->Insert( reg2 ); | |
| 1278 } // End of for all arguments | |
| 1279 | |
| 1280 // Compute number of stack slots needed to restore stack in case of | |
| 1281 // Pascal-style argument popping. | |
| 1282 mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area; | |
| 1283 } | |
| 1284 | |
| 1285 // Compute the max stack slot killed by any call. These will not be | |
| 1286 // available for debug info, and will be used to adjust FIRST_STACK_mask | |
| 1287 // after all call sites have been visited. | |
| 1288 if( _out_arg_limit < out_arg_limit_per_call) | |
| 1289 _out_arg_limit = out_arg_limit_per_call; | |
| 1290 | |
| 1291 if (mcall) { | |
| 1292 // Kill the outgoing argument area, including any non-argument holes and | |
| 1293 // any legacy C-killed slots. Use Fat-Projections to do the killing. | |
| 1294 // Since the max-per-method covers the max-per-call-site and debug info | |
| 1295 // is excluded on the max-per-method basis, debug info cannot land in | |
| 1296 // this killed area. | |
| 1297 uint r_cnt = mcall->tf()->range()->cnt(); | |
|
6804
e626685e9f6c
7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents:
6795
diff
changeset
|
1298 MachProjNode *proj = new (C) MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj ); |
|
6179
8c92982cbbc4
7119644: Increase superword's vector size up to 256 bits
kvn
parents:
4761
diff
changeset
|
1299 if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) { |
| 0 | 1300 C->record_method_not_compilable_all_tiers("unsupported outgoing calling sequence"); |
| 1301 } else { | |
| 1302 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++) | |
| 1303 proj->_rout.Insert(OptoReg::Name(i)); | |
| 1304 } | |
| 1305 if( proj->_rout.is_NotEmpty() ) | |
| 1306 _proj_list.push(proj); | |
| 1307 } | |
| 1308 // Transfer the safepoint information from the call to the mcall | |
| 1309 // Move the JVMState list | |
| 1310 msfpt->set_jvms(sfpt->jvms()); | |
| 1311 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) { | |
| 1312 jvms->set_map(sfpt); | |
| 1313 } | |
| 1314 | |
| 1315 // Debug inputs begin just after the last incoming parameter | |
| 1316 assert( (mcall == NULL) || (mcall->jvms() == NULL) || | |
| 1317 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), "" ); | |
| 1318 | |
| 1319 // Move the OopMap | |
| 1320 msfpt->_oop_map = sfpt->_oop_map; | |
| 1321 | |
| 1322 // Registers killed by the call are set in the local scheduling pass | |
| 1323 // of Global Code Motion. | |
| 1324 return msfpt; | |
| 1325 } | |
| 1326 | |
| 1327 //---------------------------match_tree---------------------------------------- | |
| 1328 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part | |
| 1329 // of the whole-sale conversion from Ideal to Mach Nodes. Also used for | |
| 1330 // making GotoNodes while building the CFG and in init_spill_mask() to identify | |
| 1331 // a Load's result RegMask for memoization in idealreg2regmask[] | |
| 1332 MachNode *Matcher::match_tree( const Node *n ) { | |
| 1333 assert( n->Opcode() != Op_Phi, "cannot match" ); | |
| 1334 assert( !n->is_block_start(), "cannot match" ); | |
| 1335 // Set the mark for all locally allocated State objects. | |
| 1336 // When this call returns, the _states_arena arena will be reset | |
| 1337 // freeing all State objects. | |
| 1338 ResourceMark rm( &_states_arena ); | |
| 1339 | |
| 1340 LabelRootDepth = 0; | |
| 1341 | |
| 1342 // StoreNodes require their Memory input to match any LoadNodes | |
| 1343 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ; | |
|
216
8d191a7697e2
6715633: when matching a memory node the adr_type should not change
kvn
parents:
169
diff
changeset
|
1344 #ifdef ASSERT |
|
8d191a7697e2
6715633: when matching a memory node the adr_type should not change
kvn
parents:
169
diff
changeset
|
1345 Node* save_mem_node = _mem_node; |
|
8d191a7697e2
6715633: when matching a memory node the adr_type should not change
kvn
parents:
169
diff
changeset
|
1346 _mem_node = n->is_Store() ? (Node*)n : NULL; |
|
8d191a7697e2
6715633: when matching a memory node the adr_type should not change
kvn
parents:
169
diff
changeset
|
1347 #endif |
| 0 | 1348 // State object for root node of match tree |
| 1349 // Allocate it on _states_arena - stack allocation can cause stack overflow. | |
| 1350 State *s = new (&_states_arena) State; | |
| 1351 s->_kids[0] = NULL; | |
| 1352 s->_kids[1] = NULL; | |
| 1353 s->_leaf = (Node*)n; | |
| 1354 // Label the input tree, allocating labels from top-level arena | |
| 1355 Label_Root( n, s, n->in(0), mem ); | |
| 1356 if (C->failing()) return NULL; | |
| 1357 | |
| 1358 // The minimum cost match for the whole tree is found at the root State | |
| 1359 uint mincost = max_juint; | |
| 1360 uint cost = max_juint; | |
| 1361 uint i; | |
| 1362 for( i = 0; i < NUM_OPERANDS; i++ ) { | |
| 1363 if( s->valid(i) && // valid entry and | |
| 1364 s->_cost[i] < cost && // low cost and | |
| 1365 s->_rule[i] >= NUM_OPERANDS ) // not an operand | |
| 1366 cost = s->_cost[mincost=i]; | |
| 1367 } | |
| 1368 if (mincost == max_juint) { | |
| 1369 #ifndef PRODUCT | |
| 1370 tty->print("No matching rule for:"); | |
| 1371 s->dump(); | |
| 1372 #endif | |
| 1373 Matcher::soft_match_failure(); | |
| 1374 return NULL; | |
| 1375 } | |
| 1376 // Reduce input tree based upon the state labels to machine Nodes | |
| 1377 MachNode *m = ReduceInst( s, s->_rule[mincost], mem ); | |
| 1378 #ifdef ASSERT | |
| 1379 _old2new_map.map(n->_idx, m); | |
| 222 | 1380 _new2old_map.map(m->_idx, (Node*)n); |
| 0 | 1381 #endif |
| 1382 | |
| 1383 // Add any Matcher-ignored edges | |
| 1384 uint cnt = n->req(); | |
| 1385 uint start = 1; | |
| 1386 if( mem != (Node*)1 ) start = MemNode::Memory+1; | |
|
168
7793bd37a336
6705887: Compressed Oops: generate x64 addressing and implicit null checks with narrow oops
kvn
parents:
164
diff
changeset
|
1387 if( n->is_AddP() ) { |
| 0 | 1388 assert( mem == (Node*)1, "" ); |
| 1389 start = AddPNode::Base+1; | |
| 1390 } | |
| 1391 for( i = start; i < cnt; i++ ) { | |
| 1392 if( !n->match_edge(i) ) { | |
| 1393 if( i < m->req() ) | |
| 1394 m->ins_req( i, n->in(i) ); | |
| 1395 else | |
| 1396 m->add_req( n->in(i) ); | |
| 1397 } | |
| 1398 } | |
| 1399 | |
|
216
8d191a7697e2
6715633: when matching a memory node the adr_type should not change
kvn
parents:
169
diff
changeset
|
1400 debug_only( _mem_node = save_mem_node; ) |
| 0 | 1401 return m; |
| 1402 } | |
| 1403 | |
| 1404 | |
| 1405 //------------------------------match_into_reg--------------------------------- | |
| 1406 // Choose to either match this Node in a register or part of the current | |
| 1407 // match tree. Return true for requiring a register and false for matching | |
| 1408 // as part of the current match tree. | |
| 1409 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) { | |
| 1410 | |
| 1411 const Type *t = m->bottom_type(); | |
| 1412 | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4064
diff
changeset
|
1413 if (t->singleton()) { |
| 0 | 1414 // Never force constants into registers. Allow them to match as |
| 1415 // constants or registers. Copies of the same value will share | |
|
168
7793bd37a336
6705887: Compressed Oops: generate x64 addressing and implicit null checks with narrow oops
kvn
parents:
164
diff
changeset
|
1416 // the same register. See find_shared_node. |
| 0 | 1417 return false; |
| 1418 } else { // Not a constant | |
| 1419 // Stop recursion if they have different Controls. | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4064
diff
changeset
|
1420 Node* m_control = m->in(0); |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4064
diff
changeset
|
1421 // Control of load's memory can post-dominates load's control. |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4064
diff
changeset
|
1422 // So use it since load can't float above its memory. |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4064
diff
changeset
|
1423 Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : NULL; |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4064
diff
changeset
|
1424 if (control && m_control && control != m_control && control != mem_control) { |
| 0 | 1425 |
| 1426 // Actually, we can live with the most conservative control we | |
| 1427 // find, if it post-dominates the others. This allows us to | |
| 1428 // pick up load/op/store trees where the load can float a little | |
| 1429 // above the store. | |
| 1430 Node *x = control; | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4064
diff
changeset
|
1431 const uint max_scan = 6; // Arbitrary scan cutoff |
| 0 | 1432 uint j; |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4064
diff
changeset
|
1433 for (j=0; j<max_scan; j++) { |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4064
diff
changeset
|
1434 if (x->is_Region()) // Bail out at merge points |
| 0 | 1435 return true; |
| 1436 x = x->in(0); | |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4064
diff
changeset
|
1437 if (x == m_control) // Does 'control' post-dominate |
| 0 | 1438 break; // m->in(0)? If so, we can use it |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4064
diff
changeset
|
1439 if (x == mem_control) // Does 'control' post-dominate |
|
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4064
diff
changeset
|
1440 break; // mem_control? If so, we can use it |
| 0 | 1441 } |
|
4761
65149e74c706
7121648: Use 3-operands SIMD instructions on x86 with AVX
kvn
parents:
4064
diff
changeset
|
1442 if (j == max_scan) // No post-domination before scan end? |
| 0 | 1443 return true; // Then break the match tree up |
| 1444 } | |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6804
diff
changeset
|
1445 if ((m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) || |
|
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6804
diff
changeset
|
1446 (m->is_DecodeNKlass() && Matcher::narrow_klass_use_complex_address())) { |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
63
diff
changeset
|
1447 // These are commonly used in address expressions and can |
|
168
7793bd37a336
6705887: Compressed Oops: generate x64 addressing and implicit null checks with narrow oops
kvn
parents:
164
diff
changeset
|
1448 // efficiently fold into them on X64 in some cases. |
|
7793bd37a336
6705887: Compressed Oops: generate x64 addressing and implicit null checks with narrow oops
kvn
parents:
164
diff
changeset
|
1449 return false; |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
63
diff
changeset
|
1450 } |
| 0 | 1451 } |
| 1452 | |
| 605 | 1453 // Not forceable cloning. If shared, put it into a register. |
| 0 | 1454 return shared; |
| 1455 } | |
| 1456 | |
| 1457 | |
| 1458 //------------------------------Instruction Selection-------------------------- | |
| 1459 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match | |
| 1460 // ideal nodes to machine instructions. Trees are delimited by shared Nodes, | |
| 1461 // things the Matcher does not match (e.g., Memory), and things with different | |
| 1462 // Controls (hence forced into different blocks). We pass in the Control | |
| 1463 // selected for this entire State tree. | |
| 1464 | |
| 1465 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the | |
| 1466 // Store and the Load must have identical Memories (as well as identical | |
| 1467 // pointers). Since the Matcher does not have anything for Memory (and | |
| 1468 // does not handle DAGs), I have to match the Memory input myself. If the | |
| 1469 // Tree root is a Store, I require all Loads to have the identical memory. | |
| 1470 Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){ | |
| 1471 // Since Label_Root is a recursive function, its possible that we might run | |
| 1472 // out of stack space. See bugs 6272980 & 6227033 for more info. | |
| 1473 LabelRootDepth++; | |
| 1474 if (LabelRootDepth > MaxLabelRootDepth) { | |
| 1475 C->record_method_not_compilable_all_tiers("Out of stack space, increase MaxLabelRootDepth"); | |
| 1476 return NULL; | |
| 1477 } | |
| 1478 uint care = 0; // Edges matcher cares about | |
| 1479 uint cnt = n->req(); | |
| 1480 uint i = 0; | |
| 1481 | |
| 1482 // Examine children for memory state | |
| 1483 // Can only subsume a child into your match-tree if that child's memory state | |
| 1484 // is not modified along the path to another input. | |
| 1485 // It is unsafe even if the other inputs are separate roots. | |
| 1486 Node *input_mem = NULL; | |
| 1487 for( i = 1; i < cnt; i++ ) { | |
| 1488 if( !n->match_edge(i) ) continue; | |
| 1489 Node *m = n->in(i); // Get ith input | |
| 1490 assert( m, "expect non-null children" ); | |
| 1491 if( m->is_Load() ) { | |
| 1492 if( input_mem == NULL ) { | |
| 1493 input_mem = m->in(MemNode::Memory); | |
| 1494 } else if( input_mem != m->in(MemNode::Memory) ) { | |
| 1495 input_mem = NodeSentinel; | |
| 1496 } | |
| 1497 } | |
| 1498 } | |
| 1499 | |
| 1500 for( i = 1; i < cnt; i++ ){// For my children | |
| 1501 if( !n->match_edge(i) ) continue; | |
| 1502 Node *m = n->in(i); // Get ith input | |
| 1503 // Allocate states out of a private arena | |
| 1504 State *s = new (&_states_arena) State; | |
| 1505 svec->_kids[care++] = s; | |
| 1506 assert( care <= 2, "binary only for now" ); | |
| 1507 | |
| 1508 // Recursively label the State tree. | |
| 1509 s->_kids[0] = NULL; | |
| 1510 s->_kids[1] = NULL; | |
| 1511 s->_leaf = m; | |
| 1512 | |
| 1513 // Check for leaves of the State Tree; things that cannot be a part of | |
| 1514 // the current tree. If it finds any, that value is matched as a | |
| 1515 // register operand. If not, then the normal matching is used. | |
| 1516 if( match_into_reg(n, m, control, i, is_shared(m)) || | |
| 1517 // | |
| 1518 // Stop recursion if this is LoadNode and the root of this tree is a | |
| 1519 // StoreNode and the load & store have different memories. | |
| 1520 ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) || | |
| 1521 // Can NOT include the match of a subtree when its memory state | |
| 1522 // is used by any of the other subtrees | |
| 1523 (input_mem == NodeSentinel) ) { | |
| 1524 #ifndef PRODUCT | |
| 1525 // Print when we exclude matching due to different memory states at input-loads | |
| 1526 if( PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel) | |
| 1527 && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ) { | |
| 1528 tty->print_cr("invalid input_mem"); | |
| 1529 } | |
| 1530 #endif | |
| 1531 // Switch to a register-only opcode; this value must be in a register | |
| 1532 // and cannot be subsumed as part of a larger instruction. | |
| 1533 s->DFA( m->ideal_reg(), m ); | |
| 1534 | |
| 1535 } else { | |
| 1536 // If match tree has no control and we do, adopt it for entire tree | |
| 1537 if( control == NULL && m->in(0) != NULL && m->req() > 1 ) | |
| 1538 control = m->in(0); // Pick up control | |
| 1539 // Else match as a normal part of the match tree. | |
| 1540 control = Label_Root(m,s,control,mem); | |
| 1541 if (C->failing()) return NULL; | |
| 1542 } | |
| 1543 } | |
| 1544 | |
| 1545 | |
| 1546 // Call DFA to match this node, and return | |
| 1547 svec->DFA( n->Opcode(), n ); | |
| 1548 | |
| 1549 #ifdef ASSERT | |
| 1550 uint x; | |
| 1551 for( x = 0; x < _LAST_MACH_OPER; x++ ) | |
| 1552 if( svec->valid(x) ) | |
| 1553 break; | |
| 1554 | |
| 1555 if (x >= _LAST_MACH_OPER) { | |
| 1556 n->dump(); | |
| 1557 svec->dump(); | |
| 1558 assert( false, "bad AD file" ); | |
| 1559 } | |
| 1560 #endif | |
| 1561 return control; | |
| 1562 } | |
| 1563 | |
| 1564 | |
| 1565 // Con nodes reduced using the same rule can share their MachNode | |
| 1566 // which reduces the number of copies of a constant in the final | |
| 1567 // program. The register allocator is free to split uses later to | |
| 1568 // split live ranges. | |
|
168
7793bd37a336
6705887: Compressed Oops: generate x64 addressing and implicit null checks with narrow oops
kvn
parents:
164
diff
changeset
|
1569 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) { |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6804
diff
changeset
|
1570 if (!leaf->is_Con() && !leaf->is_DecodeNarrowPtr()) return NULL; |
| 0 | 1571 |
| 1572 // See if this Con has already been reduced using this rule. | |
|
168
7793bd37a336
6705887: Compressed Oops: generate x64 addressing and implicit null checks with narrow oops
kvn
parents:
164
diff
changeset
|
1573 if (_shared_nodes.Size() <= leaf->_idx) return NULL; |
|
7793bd37a336
6705887: Compressed Oops: generate x64 addressing and implicit null checks with narrow oops
kvn
parents:
164
diff
changeset
|
1574 MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx); |
| 0 | 1575 if (last != NULL && rule == last->rule()) { |
|
168
7793bd37a336
6705887: Compressed Oops: generate x64 addressing and implicit null checks with narrow oops
kvn
parents:
164
diff
changeset
|
1576 // Don't expect control change for DecodeN |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6804
diff
changeset
|
1577 if (leaf->is_DecodeNarrowPtr()) |
|
168
7793bd37a336
6705887: Compressed Oops: generate x64 addressing and implicit null checks with narrow oops
kvn
parents:
164
diff
changeset
|
1578 return last; |
| 0 | 1579 // Get the new space root. |
| 1580 Node* xroot = new_node(C->root()); | |
| 1581 if (xroot == NULL) { | |
| 1582 // This shouldn't happen give the order of matching. | |
| 1583 return NULL; | |
| 1584 } | |
| 1585 | |
| 1586 // Shared constants need to have their control be root so they | |
| 1587 // can be scheduled properly. | |
| 1588 Node* control = last->in(0); | |
| 1589 if (control != xroot) { | |
| 1590 if (control == NULL || control == C->root()) { | |
| 1591 last->set_req(0, xroot); | |
| 1592 } else { | |
| 1593 assert(false, "unexpected control"); | |
| 1594 return NULL; | |
| 1595 } | |
| 1596 } | |
| 1597 return last; | |
| 1598 } | |
| 1599 return NULL; | |
| 1600 } | |
| 1601 | |
| 1602 | |
| 1603 //------------------------------ReduceInst------------------------------------- | |
| 1604 // Reduce a State tree (with given Control) into a tree of MachNodes. | |
| 1605 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into | |
| 1606 // complicated machine Nodes. Each MachNode covers some tree of Ideal Nodes. | |
| 1607 // Each MachNode has a number of complicated MachOper operands; each | |
| 1608 // MachOper also covers a further tree of Ideal Nodes. | |
| 1609 | |
| 1610 // The root of the Ideal match tree is always an instruction, so we enter | |
| 1611 // the recursion here. After building the MachNode, we need to recurse | |
| 1612 // the tree checking for these cases: | |
| 1613 // (1) Child is an instruction - | |
| 1614 // Build the instruction (recursively), add it as an edge. | |
| 1615 // Build a simple operand (register) to hold the result of the instruction. | |
| 1616 // (2) Child is an interior part of an instruction - | |
| 1617 // Skip over it (do nothing) | |
| 1618 // (3) Child is the start of a operand - | |
| 1619 // Build the operand, place it inside the instruction | |
| 1620 // Call ReduceOper. | |
| 1621 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) { | |
| 1622 assert( rule >= NUM_OPERANDS, "called with operand rule" ); | |
| 1623 | |
|
168
7793bd37a336
6705887: Compressed Oops: generate x64 addressing and implicit null checks with narrow oops
kvn
parents:
164
diff
changeset
|
1624 MachNode* shared_node = find_shared_node(s->_leaf, rule); |
|
7793bd37a336
6705887: Compressed Oops: generate x64 addressing and implicit null checks with narrow oops
kvn
parents:
164
diff
changeset
|
1625 if (shared_node != NULL) { |
|
7793bd37a336
6705887: Compressed Oops: generate x64 addressing and implicit null checks with narrow oops
kvn
parents:
164
diff
changeset
|
1626 return shared_node; |
| 0 | 1627 } |
| 1628 | |
| 1629 // Build the object to represent this state & prepare for recursive calls | |
| 1630 MachNode *mach = s->MachNodeGenerator( rule, C ); | |
| 1631 mach->_opnds[0] = s->MachOperGenerator( _reduceOp[rule], C ); | |
| 1632 assert( mach->_opnds[0] != NULL, "Missing result operand" ); | |
| 1633 Node *leaf = s->_leaf; | |
| 1634 // Check for instruction or instruction chain rule | |
| 1635 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) { | |
|
309
eaf496ad4a14
6732698: crash with dead code from compressed oops in gcm
never
parents:
235
diff
changeset
|
1636 assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf), |
|
eaf496ad4a14
6732698: crash with dead code from compressed oops in gcm
never
parents:
235
diff
changeset
|
1637 "duplicating node that's already been matched"); |
| 0 | 1638 // Instruction |
| 1639 mach->add_req( leaf->in(0) ); // Set initial control | |
| 1640 // Reduce interior of complex instruction | |
| 1641 ReduceInst_Interior( s, rule, mem, mach, 1 ); | |
| 1642 } else { | |
| 1643 // Instruction chain rules are data-dependent on their inputs | |
| 1644 mach->add_req(0); // Set initial control to none | |
| 1645 ReduceInst_Chain_Rule( s, rule, mem, mach ); | |
| 1646 } | |
| 1647 | |
| 1648 // If a Memory was used, insert a Memory edge | |
|
216
8d191a7697e2
6715633: when matching a memory node the adr_type should not change
kvn
parents:
169
diff
changeset
|
1649 if( mem != (Node*)1 ) { |
| 0 | 1650 mach->ins_req(MemNode::Memory,mem); |
|
216
8d191a7697e2
6715633: when matching a memory node the adr_type should not change
kvn
parents:
169
diff
changeset
|
1651 #ifdef ASSERT |
|
8d191a7697e2
6715633: when matching a memory node the adr_type should not change
kvn
parents:
169
diff
changeset
|
1652 // Verify adr type after matching memory operation |
|
8d191a7697e2
6715633: when matching a memory node the adr_type should not change
kvn
parents:
169
diff
changeset
|
1653 const MachOper* oper = mach->memory_operand(); |
|
851
fc4be448891f
6851742: (EA) allocation elimination doesn't work with UseG1GC
kvn
parents:
823
diff
changeset
|
1654 if (oper != NULL && oper != (MachOper*)-1) { |
|
216
8d191a7697e2
6715633: when matching a memory node the adr_type should not change
kvn
parents:
169
diff
changeset
|
1655 // It has a unique memory operand. Find corresponding ideal mem node. |
|
8d191a7697e2
6715633: when matching a memory node the adr_type should not change
kvn
parents:
169
diff
changeset
|
1656 Node* m = NULL; |
|
8d191a7697e2
6715633: when matching a memory node the adr_type should not change
kvn
parents:
169
diff
changeset
|
1657 if (leaf->is_Mem()) { |
|
8d191a7697e2
6715633: when matching a memory node the adr_type should not change
kvn
parents:
169
diff
changeset
|
1658 m = leaf; |
|
8d191a7697e2
6715633: when matching a memory node the adr_type should not change
kvn
parents:
169
diff
changeset
|
1659 } else { |
|
8d191a7697e2
6715633: when matching a memory node the adr_type should not change
kvn
parents:
169
diff
changeset
|
1660 m = _mem_node; |
|
8d191a7697e2
6715633: when matching a memory node the adr_type should not change
kvn
parents:
169
diff
changeset
|
1661 assert(m != NULL && m->is_Mem(), "expecting memory node"); |
|
8d191a7697e2
6715633: when matching a memory node the adr_type should not change
kvn
parents:
169
diff
changeset
|
1662 } |
|
368
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
1663 const Type* mach_at = mach->adr_type(); |
|
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
1664 // DecodeN node consumed by an address may have different type |
|
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
1665 // then its input. Don't compare types for such case. |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
605
diff
changeset
|
1666 if (m->adr_type() != mach_at && |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6804
diff
changeset
|
1667 (m->in(MemNode::Address)->is_DecodeNarrowPtr() || |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
605
diff
changeset
|
1668 m->in(MemNode::Address)->is_AddP() && |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6804
diff
changeset
|
1669 m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr() || |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
605
diff
changeset
|
1670 m->in(MemNode::Address)->is_AddP() && |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
605
diff
changeset
|
1671 m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() && |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6804
diff
changeset
|
1672 m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr())) { |
|
368
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
1673 mach_at = m->adr_type(); |
|
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
1674 } |
|
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
1675 if (m->adr_type() != mach_at) { |
|
216
8d191a7697e2
6715633: when matching a memory node the adr_type should not change
kvn
parents:
169
diff
changeset
|
1676 m->dump(); |
|
8d191a7697e2
6715633: when matching a memory node the adr_type should not change
kvn
parents:
169
diff
changeset
|
1677 tty->print_cr("mach:"); |
|
8d191a7697e2
6715633: when matching a memory node the adr_type should not change
kvn
parents:
169
diff
changeset
|
1678 mach->dump(1); |
|
8d191a7697e2
6715633: when matching a memory node the adr_type should not change
kvn
parents:
169
diff
changeset
|
1679 } |
|
368
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
1680 assert(m->adr_type() == mach_at, "matcher should not change adr type"); |
|
216
8d191a7697e2
6715633: when matching a memory node the adr_type should not change
kvn
parents:
169
diff
changeset
|
1681 } |
|
8d191a7697e2
6715633: when matching a memory node the adr_type should not change
kvn
parents:
169
diff
changeset
|
1682 #endif |
|
8d191a7697e2
6715633: when matching a memory node the adr_type should not change
kvn
parents:
169
diff
changeset
|
1683 } |
| 0 | 1684 |
| 1685 // If the _leaf is an AddP, insert the base edge | |
|
168
7793bd37a336
6705887: Compressed Oops: generate x64 addressing and implicit null checks with narrow oops
kvn
parents:
164
diff
changeset
|
1686 if( leaf->is_AddP() ) |
| 0 | 1687 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base)); |
| 1688 | |
| 1689 uint num_proj = _proj_list.size(); | |
| 1690 | |
| 1691 // Perform any 1-to-many expansions required | |
| 1203 | 1692 MachNode *ex = mach->Expand(s,_proj_list, mem); |
| 0 | 1693 if( ex != mach ) { |
| 1694 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match"); | |
| 1695 if( ex->in(1)->is_Con() ) | |
| 1696 ex->in(1)->set_req(0, C->root()); | |
| 1697 // Remove old node from the graph | |
| 1698 for( uint i=0; i<mach->req(); i++ ) { | |
| 1699 mach->set_req(i,NULL); | |
| 1700 } | |
| 222 | 1701 #ifdef ASSERT |
| 1702 _new2old_map.map(ex->_idx, s->_leaf); | |
| 1703 #endif | |
| 0 | 1704 } |
| 1705 | |
| 1706 // PhaseChaitin::fixup_spills will sometimes generate spill code | |
| 1707 // via the matcher. By the time, nodes have been wired into the CFG, | |
| 1708 // and any further nodes generated by expand rules will be left hanging | |
| 1709 // in space, and will not get emitted as output code. Catch this. | |
| 1710 // Also, catch any new register allocation constraints ("projections") | |
| 1711 // generated belatedly during spill code generation. | |
| 1712 if (_allocation_started) { | |
| 1713 guarantee(ex == mach, "no expand rules during spill generation"); | |
| 1714 guarantee(_proj_list.size() == num_proj, "no allocation during spill generation"); | |
| 1715 } | |
| 1716 | |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6804
diff
changeset
|
1717 if (leaf->is_Con() || leaf->is_DecodeNarrowPtr()) { |
| 0 | 1718 // Record the con for sharing |
|
168
7793bd37a336
6705887: Compressed Oops: generate x64 addressing and implicit null checks with narrow oops
kvn
parents:
164
diff
changeset
|
1719 _shared_nodes.map(leaf->_idx, ex); |
| 0 | 1720 } |
| 1721 | |
| 1722 return ex; | |
| 1723 } | |
| 1724 | |
| 1725 void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) { | |
| 1726 // 'op' is what I am expecting to receive | |
| 1727 int op = _leftOp[rule]; | |
| 1728 // Operand type to catch childs result | |
| 1729 // This is what my child will give me. | |
| 1730 int opnd_class_instance = s->_rule[op]; | |
| 1731 // Choose between operand class or not. | |
| 605 | 1732 // This is what I will receive. |
| 0 | 1733 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op; |
| 1734 // New rule for child. Chase operand classes to get the actual rule. | |
| 1735 int newrule = s->_rule[catch_op]; | |
| 1736 | |
| 1737 if( newrule < NUM_OPERANDS ) { | |
| 1738 // Chain from operand or operand class, may be output of shared node | |
| 1739 assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS, | |
| 1740 "Bad AD file: Instruction chain rule must chain from operand"); | |
| 1741 // Insert operand into array of operands for this instruction | |
| 1742 mach->_opnds[1] = s->MachOperGenerator( opnd_class_instance, C ); | |
| 1743 | |
| 1744 ReduceOper( s, newrule, mem, mach ); | |
| 1745 } else { | |
| 1746 // Chain from the result of an instruction | |
| 1747 assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand"); | |
| 1748 mach->_opnds[1] = s->MachOperGenerator( _reduceOp[catch_op], C ); | |
| 1749 Node *mem1 = (Node*)1; | |
|
216
8d191a7697e2
6715633: when matching a memory node the adr_type should not change
kvn
parents:
169
diff
changeset
|
1750 debug_only(Node *save_mem_node = _mem_node;) |
| 0 | 1751 mach->add_req( ReduceInst(s, newrule, mem1) ); |
|
216
8d191a7697e2
6715633: when matching a memory node the adr_type should not change
kvn
parents:
169
diff
changeset
|
1752 debug_only(_mem_node = save_mem_node;) |
| 0 | 1753 } |
| 1754 return; | |
| 1755 } | |
| 1756 | |
| 1757 | |
| 1758 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) { | |
| 1759 if( s->_leaf->is_Load() ) { | |
| 1760 Node *mem2 = s->_leaf->in(MemNode::Memory); | |
| 1761 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" ); | |
|
216
8d191a7697e2
6715633: when matching a memory node the adr_type should not change
kvn
parents:
169
diff
changeset
|
1762 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;) |
| 0 | 1763 mem = mem2; |
| 1764 } | |
| 1765 if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) { | |
| 1766 if( mach->in(0) == NULL ) | |
| 1767 mach->set_req(0, s->_leaf->in(0)); | |
| 1768 } | |
| 1769 | |
| 1770 // Now recursively walk the state tree & add operand list. | |
| 1771 for( uint i=0; i<2; i++ ) { // binary tree | |
| 1772 State *newstate = s->_kids[i]; | |
| 1773 if( newstate == NULL ) break; // Might only have 1 child | |
| 1774 // 'op' is what I am expecting to receive | |
| 1775 int op; | |
| 1776 if( i == 0 ) { | |
| 1777 op = _leftOp[rule]; | |
| 1778 } else { | |
| 1779 op = _rightOp[rule]; | |
| 1780 } | |
| 1781 // Operand type to catch childs result | |
| 1782 // This is what my child will give me. | |
| 1783 int opnd_class_instance = newstate->_rule[op]; | |
| 1784 // Choose between operand class or not. | |
| 1785 // This is what I will receive. | |
| 1786 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op; | |
| 1787 // New rule for child. Chase operand classes to get the actual rule. | |
| 1788 int newrule = newstate->_rule[catch_op]; | |
| 1789 | |
| 1790 if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction? | |
| 1791 // Operand/operandClass | |
| 1792 // Insert operand into array of operands for this instruction | |
| 1793 mach->_opnds[num_opnds++] = newstate->MachOperGenerator( opnd_class_instance, C ); | |
| 1794 ReduceOper( newstate, newrule, mem, mach ); | |
| 1795 | |
| 1796 } else { // Child is internal operand or new instruction | |
| 1797 if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction? | |
| 1798 // internal operand --> call ReduceInst_Interior | |
| 1799 // Interior of complex instruction. Do nothing but recurse. | |
| 1800 num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds ); | |
| 1801 } else { | |
| 1802 // instruction --> call build operand( ) to catch result | |
| 1803 // --> ReduceInst( newrule ) | |
| 1804 mach->_opnds[num_opnds++] = s->MachOperGenerator( _reduceOp[catch_op], C ); | |
| 1805 Node *mem1 = (Node*)1; | |
|
216
8d191a7697e2
6715633: when matching a memory node the adr_type should not change
kvn
parents:
169
diff
changeset
|
1806 debug_only(Node *save_mem_node = _mem_node;) |
| 0 | 1807 mach->add_req( ReduceInst( newstate, newrule, mem1 ) ); |
|
216
8d191a7697e2
6715633: when matching a memory node the adr_type should not change
kvn
parents:
169
diff
changeset
|
1808 debug_only(_mem_node = save_mem_node;) |
| 0 | 1809 } |
| 1810 } | |
| 1811 assert( mach->_opnds[num_opnds-1], "" ); | |
| 1812 } | |
| 1813 return num_opnds; | |
| 1814 } | |
| 1815 | |
| 1816 // This routine walks the interior of possible complex operands. | |
| 1817 // At each point we check our children in the match tree: | |
| 1818 // (1) No children - | |
| 1819 // We are a leaf; add _leaf field as an input to the MachNode | |
| 1820 // (2) Child is an internal operand - | |
| 1821 // Skip over it ( do nothing ) | |
| 1822 // (3) Child is an instruction - | |
| 1823 // Call ReduceInst recursively and | |
| 1824 // and instruction as an input to the MachNode | |
| 1825 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) { | |
| 1826 assert( rule < _LAST_MACH_OPER, "called with operand rule" ); | |
| 1827 State *kid = s->_kids[0]; | |
| 1828 assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" ); | |
| 1829 | |
| 1830 // Leaf? And not subsumed? | |
| 1831 if( kid == NULL && !_swallowed[rule] ) { | |
| 1832 mach->add_req( s->_leaf ); // Add leaf pointer | |
| 1833 return; // Bail out | |
| 1834 } | |
| 1835 | |
| 1836 if( s->_leaf->is_Load() ) { | |
| 1837 assert( mem == (Node*)1, "multiple Memories being matched at once?" ); | |
| 1838 mem = s->_leaf->in(MemNode::Memory); | |
|
216
8d191a7697e2
6715633: when matching a memory node the adr_type should not change
kvn
parents:
169
diff
changeset
|
1839 debug_only(_mem_node = s->_leaf;) |
| 0 | 1840 } |
| 1841 if( s->_leaf->in(0) && s->_leaf->req() > 1) { | |
| 1842 if( !mach->in(0) ) | |
| 1843 mach->set_req(0,s->_leaf->in(0)); | |
| 1844 else { | |
| 1845 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" ); | |
| 1846 } | |
| 1847 } | |
| 1848 | |
| 1849 for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) { // binary tree | |
| 1850 int newrule; | |
| 10405 | 1851 if( i == 0) |
| 0 | 1852 newrule = kid->_rule[_leftOp[rule]]; |
| 1853 else | |
| 1854 newrule = kid->_rule[_rightOp[rule]]; | |
| 1855 | |
| 1856 if( newrule < _LAST_MACH_OPER ) { // Operand or instruction? | |
| 1857 // Internal operand; recurse but do nothing else | |
| 1858 ReduceOper( kid, newrule, mem, mach ); | |
| 1859 | |
| 1860 } else { // Child is a new instruction | |
| 1861 // Reduce the instruction, and add a direct pointer from this | |
| 1862 // machine instruction to the newly reduced one. | |
| 1863 Node *mem1 = (Node*)1; | |
|
216
8d191a7697e2
6715633: when matching a memory node the adr_type should not change
kvn
parents:
169
diff
changeset
|
1864 debug_only(Node *save_mem_node = _mem_node;) |
| 0 | 1865 mach->add_req( ReduceInst( kid, newrule, mem1 ) ); |
|
216
8d191a7697e2
6715633: when matching a memory node the adr_type should not change
kvn
parents:
169
diff
changeset
|
1866 debug_only(_mem_node = save_mem_node;) |
| 0 | 1867 } |
| 1868 } | |
| 1869 } | |
| 1870 | |
| 1871 | |
| 1872 // ------------------------------------------------------------------------- | |
| 1873 // Java-Java calling convention | |
| 1874 // (what you use when Java calls Java) | |
| 1875 | |
| 1876 //------------------------------find_receiver---------------------------------- | |
| 1877 // For a given signature, return the OptoReg for parameter 0. | |
| 1878 OptoReg::Name Matcher::find_receiver( bool is_outgoing ) { | |
| 1879 VMRegPair regs; | |
| 1880 BasicType sig_bt = T_OBJECT; | |
| 1881 calling_convention(&sig_bt, ®s, 1, is_outgoing); | |
| 1882 // Return argument 0 register. In the LP64 build pointers | |
| 1883 // take 2 registers, but the VM wants only the 'main' name. | |
| 1884 return OptoReg::as_OptoReg(regs.first()); | |
| 1885 } | |
| 1886 | |
| 1887 // A method-klass-holder may be passed in the inline_cache_reg | |
| 1888 // and then expanded into the inline_cache_reg and a method_oop register | |
| 1889 // defined in ad_<arch>.cpp | |
| 1890 | |
| 1891 | |
| 1892 //------------------------------find_shared------------------------------------ | |
| 1893 // Set bits if Node is shared or otherwise a root | |
| 1894 void Matcher::find_shared( Node *n ) { | |
| 1895 // Allocate stack of size C->unique() * 2 to avoid frequent realloc | |
| 1896 MStack mstack(C->unique() * 2); | |
|
586
6bea93606c11
6791572: assert("duplicating node that's already been matched")
kvn
parents:
558
diff
changeset
|
1897 // Mark nodes as address_visited if they are inputs to an address expression |
|
6bea93606c11
6791572: assert("duplicating node that's already been matched")
kvn
parents:
558
diff
changeset
|
1898 VectorSet address_visited(Thread::current()->resource_area()); |
| 0 | 1899 mstack.push(n, Visit); // Don't need to pre-visit root node |
| 1900 while (mstack.is_nonempty()) { | |
| 1901 n = mstack.node(); // Leave node on stack | |
| 1902 Node_State nstate = mstack.state(); | |
|
586
6bea93606c11
6791572: assert("duplicating node that's already been matched")
kvn
parents:
558
diff
changeset
|
1903 uint nop = n->Opcode(); |
| 0 | 1904 if (nstate == Pre_Visit) { |
|
586
6bea93606c11
6791572: assert("duplicating node that's already been matched")
kvn
parents:
558
diff
changeset
|
1905 if (address_visited.test(n->_idx)) { // Visited in address already? |
|
6bea93606c11
6791572: assert("duplicating node that's already been matched")
kvn
parents:
558
diff
changeset
|
1906 // Flag as visited and shared now. |
|
6bea93606c11
6791572: assert("duplicating node that's already been matched")
kvn
parents:
558
diff
changeset
|
1907 set_visited(n); |
|
6bea93606c11
6791572: assert("duplicating node that's already been matched")
kvn
parents:
558
diff
changeset
|
1908 } |
| 0 | 1909 if (is_visited(n)) { // Visited already? |
| 1910 // Node is shared and has no reason to clone. Flag it as shared. | |
| 1911 // This causes it to match into a register for the sharing. | |
| 1912 set_shared(n); // Flag as shared and | |
| 1913 mstack.pop(); // remove node from stack | |
| 1914 continue; | |
| 1915 } | |
| 1916 nstate = Visit; // Not already visited; so visit now | |
| 1917 } | |
| 1918 if (nstate == Visit) { | |
| 1919 mstack.set_state(Post_Visit); | |
| 1920 set_visited(n); // Flag as visited now | |
| 1921 bool mem_op = false; | |
| 1922 | |
|
586
6bea93606c11
6791572: assert("duplicating node that's already been matched")
kvn
parents:
558
diff
changeset
|
1923 switch( nop ) { // Handle some opcodes special |
| 0 | 1924 case Op_Phi: // Treat Phis as shared roots |
| 1925 case Op_Parm: | |
| 1926 case Op_Proj: // All handled specially during matching | |
|
63
eac007780a58
6671807: (Escape Analysis) Add new ideal node to represent the state of a scalarized object at a safepoint
kvn
parents:
0
diff
changeset
|
1927 case Op_SafePointScalarObject: |
| 0 | 1928 set_shared(n); |
| 1929 set_dontcare(n); | |
| 1930 break; | |
| 1931 case Op_If: | |
| 1932 case Op_CountedLoopEnd: | |
| 1933 mstack.set_state(Alt_Post_Visit); // Alternative way | |
| 1934 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps | |
| 1935 // with matching cmp/branch in 1 instruction. The Matcher needs the | |
| 1936 // Bool and CmpX side-by-side, because it can only get at constants | |
| 1937 // that are at the leaves of Match trees, and the Bool's condition acts | |
| 1938 // as a constant here. | |
| 1939 mstack.push(n->in(1), Visit); // Clone the Bool | |
| 1940 mstack.push(n->in(0), Pre_Visit); // Visit control input | |
| 1941 continue; // while (mstack.is_nonempty()) | |
| 1942 case Op_ConvI2D: // These forms efficiently match with a prior | |
| 1943 case Op_ConvI2F: // Load but not a following Store | |
| 1944 if( n->in(1)->is_Load() && // Prior load | |
| 1945 n->outcnt() == 1 && // Not already shared | |
| 1946 n->unique_out()->is_Store() ) // Following store | |
| 1947 set_shared(n); // Force it to be a root | |
| 1948 break; | |
| 1949 case Op_ReverseBytesI: | |
| 1950 case Op_ReverseBytesL: | |
| 1951 if( n->in(1)->is_Load() && // Prior load | |
| 1952 n->outcnt() == 1 ) // Not already shared | |
| 1953 set_shared(n); // Force it to be a root | |
| 1954 break; | |
| 1955 case Op_BoxLock: // Cant match until we get stack-regs in ADLC | |
| 1956 case Op_IfFalse: | |
| 1957 case Op_IfTrue: | |
| 1958 case Op_MachProj: | |
| 1959 case Op_MergeMem: | |
| 1960 case Op_Catch: | |
| 1961 case Op_CatchProj: | |
| 1962 case Op_CProj: | |
| 1963 case Op_JumpProj: | |
| 1964 case Op_JProj: | |
| 1965 case Op_NeverBranch: | |
| 1966 set_dontcare(n); | |
| 1967 break; | |
| 1968 case Op_Jump: | |
|
4064
670a74b863fc
7107042: assert(no_dead_loop) failed: dead loop detected
kvn
parents:
3909
diff
changeset
|
1969 mstack.push(n->in(1), Pre_Visit); // Switch Value (could be shared) |
| 0 | 1970 mstack.push(n->in(0), Pre_Visit); // Visit Control input |
| 1971 continue; // while (mstack.is_nonempty()) | |
| 1972 case Op_StrComp: | |
| 681 | 1973 case Op_StrEquals: |
| 1974 case Op_StrIndexOf: | |
|
169
9148c65abefc
6695049: (coll) Create an x86 intrinsic for Arrays.equals
rasbold
parents:
168
diff
changeset
|
1975 case Op_AryEq: |
|
7637
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7196
diff
changeset
|
1976 case Op_EncodeISOArray: |
| 0 | 1977 set_shared(n); // Force result into register (it will be anyways) |
| 1978 break; | |
| 1979 case Op_ConP: { // Convert pointers above the centerline to NUL | |
| 1980 TypeNode *tn = n->as_Type(); // Constants derive from type nodes | |
| 1981 const TypePtr* tp = tn->type()->is_ptr(); | |
| 1982 if (tp->_ptr == TypePtr::AnyNull) { | |
| 1983 tn->set_type(TypePtr::NULL_PTR); | |
| 1984 } | |
| 1985 break; | |
| 1986 } | |
| 163 | 1987 case Op_ConN: { // Convert narrow pointers above the centerline to NUL |
| 1988 TypeNode *tn = n->as_Type(); // Constants derive from type nodes | |
|
221
1e026f8da827
6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents:
216
diff
changeset
|
1989 const TypePtr* tp = tn->type()->make_ptr(); |
|
1e026f8da827
6710487: More than half of JDI Regression tests hang with COOPs in -Xcomp mode
kvn
parents:
216
diff
changeset
|
1990 if (tp && tp->_ptr == TypePtr::AnyNull) { |
| 163 | 1991 tn->set_type(TypeNarrowOop::NULL_PTR); |
| 1992 } | |
| 1993 break; | |
| 1994 } | |
| 0 | 1995 case Op_Binary: // These are introduced in the Post_Visit state. |
| 1996 ShouldNotReachHere(); | |
| 1997 break; | |
| 1998 case Op_ClearArray: | |
| 1999 case Op_SafePoint: | |
| 2000 mem_op = true; | |
| 2001 break; | |
|
1061
09572fede9d1
6896370: CTW fails share/vm/opto/matcher.cpp:1475 "duplicating node that's already been matched"
kvn
parents:
986
diff
changeset
|
2002 default: |
|
09572fede9d1
6896370: CTW fails share/vm/opto/matcher.cpp:1475 "duplicating node that's already been matched"
kvn
parents:
986
diff
changeset
|
2003 if( n->is_Store() ) { |
|
09572fede9d1
6896370: CTW fails share/vm/opto/matcher.cpp:1475 "duplicating node that's already been matched"
kvn
parents:
986
diff
changeset
|
2004 // Do match stores, despite no ideal reg |
|
09572fede9d1
6896370: CTW fails share/vm/opto/matcher.cpp:1475 "duplicating node that's already been matched"
kvn
parents:
986
diff
changeset
|
2005 mem_op = true; |
|
09572fede9d1
6896370: CTW fails share/vm/opto/matcher.cpp:1475 "duplicating node that's already been matched"
kvn
parents:
986
diff
changeset
|
2006 break; |
|
09572fede9d1
6896370: CTW fails share/vm/opto/matcher.cpp:1475 "duplicating node that's already been matched"
kvn
parents:
986
diff
changeset
|
2007 } |
|
09572fede9d1
6896370: CTW fails share/vm/opto/matcher.cpp:1475 "duplicating node that's already been matched"
kvn
parents:
986
diff
changeset
|
2008 if( n->is_Mem() ) { // Loads and LoadStores |
|
09572fede9d1
6896370: CTW fails share/vm/opto/matcher.cpp:1475 "duplicating node that's already been matched"
kvn
parents:
986
diff
changeset
|
2009 mem_op = true; |
|
09572fede9d1
6896370: CTW fails share/vm/opto/matcher.cpp:1475 "duplicating node that's already been matched"
kvn
parents:
986
diff
changeset
|
2010 // Loads must be root of match tree due to prior load conflict |
|
09572fede9d1
6896370: CTW fails share/vm/opto/matcher.cpp:1475 "duplicating node that's already been matched"
kvn
parents:
986
diff
changeset
|
2011 if( C->subsume_loads() == false ) |
|
09572fede9d1
6896370: CTW fails share/vm/opto/matcher.cpp:1475 "duplicating node that's already been matched"
kvn
parents:
986
diff
changeset
|
2012 set_shared(n); |
| 0 | 2013 } |
| 2014 // Fall into default case | |
| 2015 if( !n->ideal_reg() ) | |
| 2016 set_dontcare(n); // Unmatchable Nodes | |
| 2017 } // end_switch | |
| 2018 | |
| 2019 for(int i = n->req() - 1; i >= 0; --i) { // For my children | |
| 2020 Node *m = n->in(i); // Get ith input | |
| 2021 if (m == NULL) continue; // Ignore NULLs | |
| 2022 uint mop = m->Opcode(); | |
| 2023 | |
| 2024 // Must clone all producers of flags, or we will not match correctly. | |
| 2025 // Suppose a compare setting int-flags is shared (e.g., a switch-tree) | |
| 2026 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags | |
| 2027 // are also there, so we may match a float-branch to int-flags and | |
| 2028 // expect the allocator to haul the flags from the int-side to the | |
| 2029 // fp-side. No can do. | |
| 2030 if( _must_clone[mop] ) { | |
| 2031 mstack.push(m, Visit); | |
| 2032 continue; // for(int i = ...) | |
| 2033 } | |
| 2034 | |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6804
diff
changeset
|
2035 if( mop == Op_AddP && m->in(AddPNode::Base)->is_DecodeNarrowPtr()) { |
|
1061
09572fede9d1
6896370: CTW fails share/vm/opto/matcher.cpp:1475 "duplicating node that's already been matched"
kvn
parents:
986
diff
changeset
|
2036 // Bases used in addresses must be shared but since |
|
09572fede9d1
6896370: CTW fails share/vm/opto/matcher.cpp:1475 "duplicating node that's already been matched"
kvn
parents:
986
diff
changeset
|
2037 // they are shared through a DecodeN they may appear |
|
09572fede9d1
6896370: CTW fails share/vm/opto/matcher.cpp:1475 "duplicating node that's already been matched"
kvn
parents:
986
diff
changeset
|
2038 // to have a single use so force sharing here. |
|
09572fede9d1
6896370: CTW fails share/vm/opto/matcher.cpp:1475 "duplicating node that's already been matched"
kvn
parents:
986
diff
changeset
|
2039 set_shared(m->in(AddPNode::Base)->in(1)); |
|
09572fede9d1
6896370: CTW fails share/vm/opto/matcher.cpp:1475 "duplicating node that's already been matched"
kvn
parents:
986
diff
changeset
|
2040 } |
|
09572fede9d1
6896370: CTW fails share/vm/opto/matcher.cpp:1475 "duplicating node that's already been matched"
kvn
parents:
986
diff
changeset
|
2041 |
|
09572fede9d1
6896370: CTW fails share/vm/opto/matcher.cpp:1475 "duplicating node that's already been matched"
kvn
parents:
986
diff
changeset
|
2042 // Clone addressing expressions as they are "free" in memory access instructions |
| 0 | 2043 if( mem_op && i == MemNode::Address && mop == Op_AddP ) { |
|
586
6bea93606c11
6791572: assert("duplicating node that's already been matched")
kvn
parents:
558
diff
changeset
|
2044 // Some inputs for address expression are not put on stack |
|
6bea93606c11
6791572: assert("duplicating node that's already been matched")
kvn
parents:
558
diff
changeset
|
2045 // to avoid marking them as shared and forcing them into register |
|
6bea93606c11
6791572: assert("duplicating node that's already been matched")
kvn
parents:
558
diff
changeset
|
2046 // if they are used only in address expressions. |
|
6bea93606c11
6791572: assert("duplicating node that's already been matched")
kvn
parents:
558
diff
changeset
|
2047 // But they should be marked as shared if there are other uses |
|
6bea93606c11
6791572: assert("duplicating node that's already been matched")
kvn
parents:
558
diff
changeset
|
2048 // besides address expressions. |
|
6bea93606c11
6791572: assert("duplicating node that's already been matched")
kvn
parents:
558
diff
changeset
|
2049 |
| 0 | 2050 Node *off = m->in(AddPNode::Offset); |
|
586
6bea93606c11
6791572: assert("duplicating node that's already been matched")
kvn
parents:
558
diff
changeset
|
2051 if( off->is_Con() && |
|
6bea93606c11
6791572: assert("duplicating node that's already been matched")
kvn
parents:
558
diff
changeset
|
2052 // When there are other uses besides address expressions |
|
6bea93606c11
6791572: assert("duplicating node that's already been matched")
kvn
parents:
558
diff
changeset
|
2053 // put it on stack and mark as shared. |
|
6bea93606c11
6791572: assert("duplicating node that's already been matched")
kvn
parents:
558
diff
changeset
|
2054 !is_visited(m) ) { |
|
6bea93606c11
6791572: assert("duplicating node that's already been matched")
kvn
parents:
558
diff
changeset
|
2055 address_visited.test_set(m->_idx); // Flag as address_visited |
| 0 | 2056 Node *adr = m->in(AddPNode::Address); |
| 2057 | |
| 2058 // Intel, ARM and friends can handle 2 adds in addressing mode | |
|
168
7793bd37a336
6705887: Compressed Oops: generate x64 addressing and implicit null checks with narrow oops
kvn
parents:
164
diff
changeset
|
2059 if( clone_shift_expressions && adr->is_AddP() && |
| 0 | 2060 // AtomicAdd is not an addressing expression. |
| 2061 // Cheap to find it by looking for screwy base. | |
|
586
6bea93606c11
6791572: assert("duplicating node that's already been matched")
kvn
parents:
558
diff
changeset
|
2062 !adr->in(AddPNode::Base)->is_top() && |
|
6bea93606c11
6791572: assert("duplicating node that's already been matched")
kvn
parents:
558
diff
changeset
|
2063 // Are there other uses besides address expressions? |
|
6bea93606c11
6791572: assert("duplicating node that's already been matched")
kvn
parents:
558
diff
changeset
|
2064 !is_visited(adr) ) { |
|
6bea93606c11
6791572: assert("duplicating node that's already been matched")
kvn
parents:
558
diff
changeset
|
2065 address_visited.set(adr->_idx); // Flag as address_visited |
| 0 | 2066 Node *shift = adr->in(AddPNode::Offset); |
| 2067 // Check for shift by small constant as well | |
| 2068 if( shift->Opcode() == Op_LShiftX && shift->in(2)->is_Con() && | |
|
586
6bea93606c11
6791572: assert("duplicating node that's already been matched")
kvn
parents:
558
diff
changeset
|
2069 shift->in(2)->get_int() <= 3 && |
|
6bea93606c11
6791572: assert("duplicating node that's already been matched")
kvn
parents:
558
diff
changeset
|
2070 // Are there other uses besides address expressions? |
|
6bea93606c11
6791572: assert("duplicating node that's already been matched")
kvn
parents:
558
diff
changeset
|
2071 !is_visited(shift) ) { |
|
6bea93606c11
6791572: assert("duplicating node that's already been matched")
kvn
parents:
558
diff
changeset
|
2072 address_visited.set(shift->_idx); // Flag as address_visited |
| 0 | 2073 mstack.push(shift->in(2), Visit); |
|
586
6bea93606c11
6791572: assert("duplicating node that's already been matched")
kvn
parents:
558
diff
changeset
|
2074 Node *conv = shift->in(1); |
| 0 | 2075 #ifdef _LP64 |
| 2076 // Allow Matcher to match the rule which bypass | |
| 2077 // ConvI2L operation for an array index on LP64 | |
| 2078 // if the index value is positive. | |
|
586
6bea93606c11
6791572: assert("duplicating node that's already been matched")
kvn
parents:
558
diff
changeset
|
2079 if( conv->Opcode() == Op_ConvI2L && |
|
6bea93606c11
6791572: assert("duplicating node that's already been matched")
kvn
parents:
558
diff
changeset
|
2080 conv->as_Type()->type()->is_long()->_lo >= 0 && |
|
6bea93606c11
6791572: assert("duplicating node that's already been matched")
kvn
parents:
558
diff
changeset
|
2081 // Are there other uses besides address expressions? |
|
6bea93606c11
6791572: assert("duplicating node that's already been matched")
kvn
parents:
558
diff
changeset
|
2082 !is_visited(conv) ) { |
|
6bea93606c11
6791572: assert("duplicating node that's already been matched")
kvn
parents:
558
diff
changeset
|
2083 address_visited.set(conv->_idx); // Flag as address_visited |
|
6bea93606c11
6791572: assert("duplicating node that's already been matched")
kvn
parents:
558
diff
changeset
|
2084 mstack.push(conv->in(1), Pre_Visit); |
| 0 | 2085 } else |
| 2086 #endif | |
|
586
6bea93606c11
6791572: assert("duplicating node that's already been matched")
kvn
parents:
558
diff
changeset
|
2087 mstack.push(conv, Pre_Visit); |
| 0 | 2088 } else { |
| 2089 mstack.push(shift, Pre_Visit); | |
| 2090 } | |
| 2091 mstack.push(adr->in(AddPNode::Address), Pre_Visit); | |
| 2092 mstack.push(adr->in(AddPNode::Base), Pre_Visit); | |
| 2093 } else { // Sparc, Alpha, PPC and friends | |
| 2094 mstack.push(adr, Pre_Visit); | |
| 2095 } | |
| 2096 | |
| 2097 // Clone X+offset as it also folds into most addressing expressions | |
| 2098 mstack.push(off, Visit); | |
| 2099 mstack.push(m->in(AddPNode::Base), Pre_Visit); | |
| 2100 continue; // for(int i = ...) | |
| 2101 } // if( off->is_Con() ) | |
| 2102 } // if( mem_op && | |
| 2103 mstack.push(m, Pre_Visit); | |
| 2104 } // for(int i = ...) | |
| 2105 } | |
| 2106 else if (nstate == Alt_Post_Visit) { | |
| 2107 mstack.pop(); // Remove node from stack | |
| 2108 // We cannot remove the Cmp input from the Bool here, as the Bool may be | |
| 2109 // shared and all users of the Bool need to move the Cmp in parallel. | |
| 2110 // This leaves both the Bool and the If pointing at the Cmp. To | |
| 2111 // prevent the Matcher from trying to Match the Cmp along both paths | |
| 2112 // BoolNode::match_edge always returns a zero. | |
| 2113 | |
| 2114 // We reorder the Op_If in a pre-order manner, so we can visit without | |
| 605 | 2115 // accidentally sharing the Cmp (the Bool and the If make 2 users). |
| 0 | 2116 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool |
| 2117 } | |
| 2118 else if (nstate == Post_Visit) { | |
| 2119 mstack.pop(); // Remove node from stack | |
| 2120 | |
| 2121 // Now hack a few special opcodes | |
| 2122 switch( n->Opcode() ) { // Handle some opcodes special | |
| 2123 case Op_StorePConditional: | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
368
diff
changeset
|
2124 case Op_StoreIConditional: |
| 0 | 2125 case Op_StoreLConditional: |
| 2126 case Op_CompareAndSwapI: | |
| 2127 case Op_CompareAndSwapL: | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
63
diff
changeset
|
2128 case Op_CompareAndSwapP: |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
63
diff
changeset
|
2129 case Op_CompareAndSwapN: { // Convert trinary to binary-tree |
| 0 | 2130 Node *newval = n->in(MemNode::ValueIn ); |
|
6795
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
2131 Node *oldval = n->in(LoadStoreConditionalNode::ExpectedIn); |
|
6804
e626685e9f6c
7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents:
6795
diff
changeset
|
2132 Node *pair = new (C) BinaryNode( oldval, newval ); |
| 0 | 2133 n->set_req(MemNode::ValueIn,pair); |
|
6795
7eca5de9e0b6
7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement()
roland
parents:
6725
diff
changeset
|
2134 n->del_req(LoadStoreConditionalNode::ExpectedIn); |
| 0 | 2135 break; |
| 2136 } | |
| 2137 case Op_CMoveD: // Convert trinary to binary-tree | |
| 2138 case Op_CMoveF: | |
| 2139 case Op_CMoveI: | |
| 2140 case Op_CMoveL: | |
|
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
2141 case Op_CMoveN: |
| 0 | 2142 case Op_CMoveP: { |
| 2143 // Restructure into a binary tree for Matching. It's possible that | |
| 2144 // we could move this code up next to the graph reshaping for IfNodes | |
| 2145 // or vice-versa, but I do not want to debug this for Ladybird. | |
| 2146 // 10/2/2000 CNC. | |
|
6804
e626685e9f6c
7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents:
6795
diff
changeset
|
2147 Node *pair1 = new (C) BinaryNode(n->in(1),n->in(1)->in(1)); |
| 0 | 2148 n->set_req(1,pair1); |
|
6804
e626685e9f6c
7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents:
6795
diff
changeset
|
2149 Node *pair2 = new (C) BinaryNode(n->in(2),n->in(3)); |
| 0 | 2150 n->set_req(2,pair2); |
| 2151 n->del_req(3); | |
| 2152 break; | |
| 2153 } | |
| 3345 | 2154 case Op_LoopLimit: { |
|
6804
e626685e9f6c
7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents:
6795
diff
changeset
|
2155 Node *pair1 = new (C) BinaryNode(n->in(1),n->in(2)); |
| 3345 | 2156 n->set_req(1,pair1); |
| 2157 n->set_req(2,n->in(3)); | |
| 2158 n->del_req(3); | |
| 2159 break; | |
| 2160 } | |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
851
diff
changeset
|
2161 case Op_StrEquals: { |
|
6804
e626685e9f6c
7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents:
6795
diff
changeset
|
2162 Node *pair1 = new (C) BinaryNode(n->in(2),n->in(3)); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
851
diff
changeset
|
2163 n->set_req(2,pair1); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
851
diff
changeset
|
2164 n->set_req(3,n->in(4)); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
851
diff
changeset
|
2165 n->del_req(4); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
851
diff
changeset
|
2166 break; |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
851
diff
changeset
|
2167 } |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
851
diff
changeset
|
2168 case Op_StrComp: |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
851
diff
changeset
|
2169 case Op_StrIndexOf: { |
|
6804
e626685e9f6c
7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents:
6795
diff
changeset
|
2170 Node *pair1 = new (C) BinaryNode(n->in(2),n->in(3)); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
851
diff
changeset
|
2171 n->set_req(2,pair1); |
|
6804
e626685e9f6c
7193318: C2: remove number of inputs requirement from Node's new operator
kvn
parents:
6795
diff
changeset
|
2172 Node *pair2 = new (C) BinaryNode(n->in(4),n->in(5)); |
|
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
851
diff
changeset
|
2173 n->set_req(3,pair2); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
851
diff
changeset
|
2174 n->del_req(5); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
851
diff
changeset
|
2175 n->del_req(4); |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
851
diff
changeset
|
2176 break; |
|
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
851
diff
changeset
|
2177 } |
|
7637
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7196
diff
changeset
|
2178 case Op_EncodeISOArray: { |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7196
diff
changeset
|
2179 // Restructure into a binary tree for Matching. |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7196
diff
changeset
|
2180 Node* pair = new (C) BinaryNode(n->in(3), n->in(4)); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7196
diff
changeset
|
2181 n->set_req(3, pair); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7196
diff
changeset
|
2182 n->del_req(4); |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7196
diff
changeset
|
2183 break; |
|
b30b3c2a0cf2
6896617: Optimize sun.nio.cs.ISO_8859_1$Encode.encodeArrayLoop() on x86
kvn
parents:
7196
diff
changeset
|
2184 } |
| 0 | 2185 default: |
| 2186 break; | |
| 2187 } | |
| 2188 } | |
| 2189 else { | |
| 2190 ShouldNotReachHere(); | |
| 2191 } | |
| 2192 } // end of while (mstack.is_nonempty()) | |
| 2193 } | |
| 2194 | |
| 2195 #ifdef ASSERT | |
| 2196 // machine-independent root to machine-dependent root | |
| 2197 void Matcher::dump_old2new_map() { | |
| 2198 _old2new_map.dump(); | |
| 2199 } | |
| 2200 #endif | |
| 2201 | |
| 2202 //---------------------------collect_null_checks------------------------------- | |
| 2203 // Find null checks in the ideal graph; write a machine-specific node for | |
| 2204 // it. Used by later implicit-null-check handling. Actually collects | |
| 2205 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal | |
| 2206 // value being tested. | |
|
368
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
2207 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) { |
| 0 | 2208 Node *iff = proj->in(0); |
| 2209 if( iff->Opcode() == Op_If ) { | |
| 2210 // During matching If's have Bool & Cmp side-by-side | |
| 2211 BoolNode *b = iff->in(1)->as_Bool(); | |
| 2212 Node *cmp = iff->in(2); | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
63
diff
changeset
|
2213 int opc = cmp->Opcode(); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
63
diff
changeset
|
2214 if (opc != Op_CmpP && opc != Op_CmpN) return; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
63
diff
changeset
|
2215 |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
63
diff
changeset
|
2216 const Type* ct = cmp->in(2)->bottom_type(); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
63
diff
changeset
|
2217 if (ct == TypePtr::NULL_PTR || |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
63
diff
changeset
|
2218 (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) { |
| 0 | 2219 |
|
368
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
2220 bool push_it = false; |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
63
diff
changeset
|
2221 if( proj->Opcode() == Op_IfTrue ) { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
63
diff
changeset
|
2222 extern int all_null_checks_found; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
63
diff
changeset
|
2223 all_null_checks_found++; |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
63
diff
changeset
|
2224 if( b->_test._test == BoolTest::ne ) { |
|
368
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
2225 push_it = true; |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
63
diff
changeset
|
2226 } |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
63
diff
changeset
|
2227 } else { |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
63
diff
changeset
|
2228 assert( proj->Opcode() == Op_IfFalse, "" ); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
63
diff
changeset
|
2229 if( b->_test._test == BoolTest::eq ) { |
|
368
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
2230 push_it = true; |
| 0 | 2231 } |
| 2232 } | |
|
368
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
2233 if( push_it ) { |
|
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
2234 _null_check_tests.push(proj); |
|
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
2235 Node* val = cmp->in(1); |
|
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
2236 #ifdef _LP64 |
|
1575
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1203
diff
changeset
|
2237 if (val->bottom_type()->isa_narrowoop() && |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1203
diff
changeset
|
2238 !Matcher::narrow_oop_use_complex_address()) { |
|
368
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
2239 // |
|
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
2240 // Look for DecodeN node which should be pinned to orig_proj. |
|
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
2241 // On platforms (Sparc) which can not handle 2 adds |
|
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
2242 // in addressing mode we have to keep a DecodeN node and |
|
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
2243 // use it to do implicit NULL check in address. |
|
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
2244 // |
|
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
2245 // DecodeN node was pinned to non-null path (orig_proj) during |
|
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
2246 // CastPP transformation in final_graph_reshaping_impl(). |
|
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
2247 // |
|
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
2248 uint cnt = orig_proj->outcnt(); |
|
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
2249 for (uint i = 0; i < orig_proj->outcnt(); i++) { |
|
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
2250 Node* d = orig_proj->raw_out(i); |
|
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
2251 if (d->is_DecodeN() && d->in(1) == val) { |
|
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
2252 val = d; |
|
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
2253 val->set_req(0, NULL); // Unpin now. |
|
1575
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1203
diff
changeset
|
2254 // Mark this as special case to distinguish from |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1203
diff
changeset
|
2255 // a regular case: CmpP(DecodeN, NULL). |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1203
diff
changeset
|
2256 val = (Node*)(((intptr_t)val) | 1); |
|
368
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
2257 break; |
|
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
2258 } |
|
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
2259 } |
|
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
2260 } |
|
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
2261 #endif |
|
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
2262 _null_check_tests.push(val); |
|
36ccc817fca4
6747051: Improve code and implicit null check generation for compressed oops
kvn
parents:
367
diff
changeset
|
2263 } |
| 0 | 2264 } |
| 2265 } | |
| 2266 } | |
| 2267 | |
| 2268 //---------------------------validate_null_checks------------------------------ | |
| 2269 // Its possible that the value being NULL checked is not the root of a match | |
| 2270 // tree. If so, I cannot use the value in an implicit null check. | |
| 2271 void Matcher::validate_null_checks( ) { | |
| 2272 uint cnt = _null_check_tests.size(); | |
| 2273 for( uint i=0; i < cnt; i+=2 ) { | |
| 2274 Node *test = _null_check_tests[i]; | |
| 2275 Node *val = _null_check_tests[i+1]; | |
|
1575
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1203
diff
changeset
|
2276 bool is_decoden = ((intptr_t)val) & 1; |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1203
diff
changeset
|
2277 val = (Node*)(((intptr_t)val) & ~1); |
| 0 | 2278 if (has_new_node(val)) { |
|
1575
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1203
diff
changeset
|
2279 Node* new_val = new_node(val); |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1203
diff
changeset
|
2280 if (is_decoden) { |
|
6848
8e47bac5643a
7054512: Compress class pointers after perm gen removal
roland
parents:
6804
diff
changeset
|
2281 assert(val->is_DecodeNarrowPtr() && val->in(0) == NULL, "sanity"); |
|
1575
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1203
diff
changeset
|
2282 // Note: new_val may have a control edge if |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1203
diff
changeset
|
2283 // the original ideal node DecodeN was matched before |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1203
diff
changeset
|
2284 // it was unpinned in Matcher::collect_null_checks(). |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1203
diff
changeset
|
2285 // Unpin the mach node and mark it. |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1203
diff
changeset
|
2286 new_val->set_req(0, NULL); |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1203
diff
changeset
|
2287 new_val = (Node*)(((intptr_t)new_val) | 1); |
|
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1203
diff
changeset
|
2288 } |
| 0 | 2289 // Is a match-tree root, so replace with the matched value |
|
1575
3657cb01ffc5
6954029: Improve implicit null check generation with compressed oops
kvn
parents:
1203
diff
changeset
|
2290 _null_check_tests.map(i+1, new_val); |
| 0 | 2291 } else { |
| 2292 // Yank from candidate list | |
| 2293 _null_check_tests.map(i+1,_null_check_tests[--cnt]); | |
| 2294 _null_check_tests.map(i,_null_check_tests[--cnt]); | |
| 2295 _null_check_tests.pop(); | |
| 2296 _null_check_tests.pop(); | |
| 2297 i-=2; | |
| 2298 } | |
| 2299 } | |
| 2300 } | |
| 2301 | |
| 2302 // Used by the DFA in dfa_xxx.cpp. Check for a following barrier or | |
| 2303 // atomic instruction acting as a store_load barrier without any | |
| 2304 // intervening volatile load, and thus we don't need a barrier here. | |
| 2305 // We retain the Node to act as a compiler ordering barrier. | |
| 2306 bool Matcher::post_store_load_barrier(const Node *vmb) { | |
| 2307 Compile *C = Compile::current(); | |
| 2308 assert( vmb->is_MemBar(), "" ); | |
| 2309 assert( vmb->Opcode() != Op_MemBarAcquire, "" ); | |
| 2310 const MemBarNode *mem = (const MemBarNode*)vmb; | |
| 2311 | |
| 2312 // Get the Proj node, ctrl, that can be used to iterate forward | |
| 2313 Node *ctrl = NULL; | |
| 2314 DUIterator_Fast imax, i = mem->fast_outs(imax); | |
| 2315 while( true ) { | |
| 2316 ctrl = mem->fast_out(i); // Throw out-of-bounds if proj not found | |
| 2317 assert( ctrl->is_Proj(), "only projections here" ); | |
| 2318 ProjNode *proj = (ProjNode*)ctrl; | |
| 2319 if( proj->_con == TypeFunc::Control && | |
| 2320 !C->node_arena()->contains(ctrl) ) // Unmatched old-space only | |
| 2321 break; | |
| 2322 i++; | |
| 2323 } | |
| 2324 | |
| 2325 for( DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++ ) { | |
| 2326 Node *x = ctrl->fast_out(j); | |
| 2327 int xop = x->Opcode(); | |
| 2328 | |
| 2329 // We don't need current barrier if we see another or a lock | |
| 2330 // before seeing volatile load. | |
| 2331 // | |
| 2332 // Op_Fastunlock previously appeared in the Op_* list below. | |
| 2333 // With the advent of 1-0 lock operations we're no longer guaranteed | |
| 2334 // that a monitor exit operation contains a serializing instruction. | |
| 2335 | |
| 2336 if (xop == Op_MemBarVolatile || | |
| 2337 xop == Op_FastLock || | |
| 2338 xop == Op_CompareAndSwapL || | |
| 2339 xop == Op_CompareAndSwapP || | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
63
diff
changeset
|
2340 xop == Op_CompareAndSwapN || |
| 0 | 2341 xop == Op_CompareAndSwapI) |
| 2342 return true; | |
| 2343 | |
| 2344 if (x->is_MemBar()) { | |
| 2345 // We must retain this membar if there is an upcoming volatile | |
| 2346 // load, which will be preceded by acquire membar. | |
| 2347 if (xop == Op_MemBarAcquire) | |
| 2348 return false; | |
| 2349 // For other kinds of barriers, check by pretending we | |
| 2350 // are them, and seeing if we can be removed. | |
| 2351 else | |
| 2352 return post_store_load_barrier((const MemBarNode*)x); | |
| 2353 } | |
| 2354 | |
| 2355 // Delicate code to detect case of an upcoming fastlock block | |
| 2356 if( x->is_If() && x->req() > 1 && | |
| 2357 !C->node_arena()->contains(x) ) { // Unmatched old-space only | |
| 2358 Node *iff = x; | |
| 2359 Node *bol = iff->in(1); | |
| 2360 // The iff might be some random subclass of If or bol might be Con-Top | |
| 2361 if (!bol->is_Bool()) return false; | |
| 2362 assert( bol->req() > 1, "" ); | |
| 2363 return (bol->in(1)->Opcode() == Op_FastUnlock); | |
| 2364 } | |
| 2365 // probably not necessary to check for these | |
| 2366 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) | |
| 2367 return false; | |
| 2368 } | |
| 2369 return false; | |
| 2370 } | |
| 2371 | |
| 2372 //============================================================================= | |
| 2373 //---------------------------State--------------------------------------------- | |
| 2374 State::State(void) { | |
| 2375 #ifdef ASSERT | |
| 2376 _id = 0; | |
| 2377 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe); | |
| 2378 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d); | |
| 2379 //memset(_cost, -1, sizeof(_cost)); | |
| 2380 //memset(_rule, -1, sizeof(_rule)); | |
| 2381 #endif | |
| 2382 memset(_valid, 0, sizeof(_valid)); | |
| 2383 } | |
| 2384 | |
| 2385 #ifdef ASSERT | |
| 2386 State::~State() { | |
| 2387 _id = 99; | |
| 2388 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe); | |
| 2389 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d); | |
| 2390 memset(_cost, -3, sizeof(_cost)); | |
| 2391 memset(_rule, -3, sizeof(_rule)); | |
| 2392 } | |
| 2393 #endif | |
| 2394 | |
| 2395 #ifndef PRODUCT | |
| 2396 //---------------------------dump---------------------------------------------- | |
| 2397 void State::dump() { | |
| 2398 tty->print("\n"); | |
| 2399 dump(0); | |
| 2400 } | |
| 2401 | |
| 2402 void State::dump(int depth) { | |
| 2403 for( int j = 0; j < depth; j++ ) | |
| 2404 tty->print(" "); | |
| 2405 tty->print("--N: "); | |
| 2406 _leaf->dump(); | |
| 2407 uint i; | |
| 2408 for( i = 0; i < _LAST_MACH_OPER; i++ ) | |
| 2409 // Check for valid entry | |
| 2410 if( valid(i) ) { | |
| 2411 for( int j = 0; j < depth; j++ ) | |
| 2412 tty->print(" "); | |
| 2413 assert(_cost[i] != max_juint, "cost must be a valid value"); | |
| 2414 assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule"); | |
| 2415 tty->print_cr("%s %d %s", | |
| 2416 ruleName[i], _cost[i], ruleName[_rule[i]] ); | |
| 2417 } | |
| 2418 tty->print_cr(""); | |
| 2419 | |
| 2420 for( i=0; i<2; i++ ) | |
| 2421 if( _kids[i] ) | |
| 2422 _kids[i]->dump(depth+1); | |
| 2423 } | |
| 2424 #endif |