graal-compiler: graal/com.oracle.graal.lir/src/com/oracle/graal/lir/alloc/trace/TraceGlobalMoveResolver.java annotate

annotate graal/com.oracle.graal.lir/src/com/oracle/graal/lir/alloc/trace/TraceGlobalMoveResolver.java @ 23154:f2a8407253da

TraceRA: move resolution: count number of created stack slots.

author	Josef Eisl <josef.eisl@jku.at>
date	Thu, 10 Dec 2015 18:22:07 +0100
parents	23f9a72eb037
children	e660e8431be0

rev	line source
22350 06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	1 /*
22510 d3d19b31e9a4 Split MoveOp into ValueMoveOp and LoadConstantOp. Roland Schatz <roland.schatz@oracle.com> parents: 22447 diff changeset	2 * Copyright (c) 2009, 2015, Oracle and/or its affiliates. All rights reserved.
22350 06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	4 *
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	5 * This code is free software; you can redistribute it and/or modify it
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	6 * under the terms of the GNU General Public License version 2 only, as
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	7 * published by the Free Software Foundation.
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	8 *
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	9 * This code is distributed in the hope that it will be useful, but WITHOUT
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	12 * version 2 for more details (a copy is included in the LICENSE file that
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	13 * accompanied this code).
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	14 *
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	15 * You should have received a copy of the GNU General Public License version
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	16 * 2 along with this work; if not, write to the Free Software Foundation,
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	18 *
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	20 * or visit www.oracle.com if you need additional information or have any
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	21 * questions.
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	22 */
22352 e6ea77e2a770 Move different register allocators into sub-packages. Josef Eisl <josef.eisl@jku.at> parents: 22350 diff changeset	23 package com.oracle.graal.lir.alloc.trace;
22350 06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	24
22843 ae8a63a7aa9e Update jvmci import: Move VirtualStackSlot from JVMCI to Graal and remove referenceMapIndex. Roland Schatz <roland.schatz@oracle.com> parents: 22790 diff changeset	25 import static com.oracle.graal.lir.LIRValueUtil.asVirtualStackSlot;
ae8a63a7aa9e Update jvmci import: Move VirtualStackSlot from JVMCI to Graal and remove referenceMapIndex. Roland Schatz <roland.schatz@oracle.com> parents: 22790 diff changeset	26 import static com.oracle.graal.lir.LIRValueUtil.isStackSlotValue;
ae8a63a7aa9e Update jvmci import: Move VirtualStackSlot from JVMCI to Graal and remove referenceMapIndex. Roland Schatz <roland.schatz@oracle.com> parents: 22790 diff changeset	27 import static com.oracle.graal.lir.LIRValueUtil.isVirtualStackSlot;
22646 05183a084a08 updated imports to be explicit and added checkstyle rule to forbid * imports Doug Simon <doug.simon@oracle.com> parents: 22573 diff changeset	28 import static com.oracle.graal.lir.alloc.trace.TraceUtil.asShadowedRegisterValue;
05183a084a08 updated imports to be explicit and added checkstyle rule to forbid * imports Doug Simon <doug.simon@oracle.com> parents: 22573 diff changeset	29 import static com.oracle.graal.lir.alloc.trace.TraceUtil.isShadowedRegisterValue;
22843 ae8a63a7aa9e Update jvmci import: Move VirtualStackSlot from JVMCI to Graal and remove referenceMapIndex. Roland Schatz <roland.schatz@oracle.com> parents: 22790 diff changeset	30 import static jdk.vm.ci.code.ValueUtil.asAllocatableValue;
22790 615f3bbbb174 Update jvmci and truffle import: Rename jdk.internal.jvmci to jdk.vm.ci Tom Rodriguez <tom.rodriguez@oracle.com> parents: 22646 diff changeset	31 import static jdk.vm.ci.code.ValueUtil.asRegister;
615f3bbbb174 Update jvmci and truffle import: Rename jdk.internal.jvmci to jdk.vm.ci Tom Rodriguez <tom.rodriguez@oracle.com> parents: 22646 diff changeset	32 import static jdk.vm.ci.code.ValueUtil.asStackSlot;
615f3bbbb174 Update jvmci and truffle import: Rename jdk.internal.jvmci to jdk.vm.ci Tom Rodriguez <tom.rodriguez@oracle.com> parents: 22646 diff changeset	33 import static jdk.vm.ci.code.ValueUtil.isIllegal;
615f3bbbb174 Update jvmci and truffle import: Rename jdk.internal.jvmci to jdk.vm.ci Tom Rodriguez <tom.rodriguez@oracle.com> parents: 22646 diff changeset	34 import static jdk.vm.ci.code.ValueUtil.isRegister;
615f3bbbb174 Update jvmci and truffle import: Rename jdk.internal.jvmci to jdk.vm.ci Tom Rodriguez <tom.rodriguez@oracle.com> parents: 22646 diff changeset	35 import static jdk.vm.ci.code.ValueUtil.isStackSlot;
22350 06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	36
22646 05183a084a08 updated imports to be explicit and added checkstyle rule to forbid * imports Doug Simon <doug.simon@oracle.com> parents: 22573 diff changeset	37 import java.util.ArrayList;
05183a084a08 updated imports to be explicit and added checkstyle rule to forbid * imports Doug Simon <doug.simon@oracle.com> parents: 22573 diff changeset	38 import java.util.Arrays;
05183a084a08 updated imports to be explicit and added checkstyle rule to forbid * imports Doug Simon <doug.simon@oracle.com> parents: 22573 diff changeset	39 import java.util.HashSet;
05183a084a08 updated imports to be explicit and added checkstyle rule to forbid * imports Doug Simon <doug.simon@oracle.com> parents: 22573 diff changeset	40 import java.util.List;
22350 06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	41
22790 615f3bbbb174 Update jvmci and truffle import: Rename jdk.internal.jvmci to jdk.vm.ci Tom Rodriguez <tom.rodriguez@oracle.com> parents: 22646 diff changeset	42 import jdk.vm.ci.code.Architecture;
615f3bbbb174 Update jvmci and truffle import: Rename jdk.internal.jvmci to jdk.vm.ci Tom Rodriguez <tom.rodriguez@oracle.com> parents: 22646 diff changeset	43 import jdk.vm.ci.code.Register;
615f3bbbb174 Update jvmci and truffle import: Rename jdk.internal.jvmci to jdk.vm.ci Tom Rodriguez <tom.rodriguez@oracle.com> parents: 22646 diff changeset	44 import jdk.vm.ci.code.StackSlot;
615f3bbbb174 Update jvmci and truffle import: Rename jdk.internal.jvmci to jdk.vm.ci Tom Rodriguez <tom.rodriguez@oracle.com> parents: 22646 diff changeset	45 import jdk.vm.ci.common.JVMCIError;
615f3bbbb174 Update jvmci and truffle import: Rename jdk.internal.jvmci to jdk.vm.ci Tom Rodriguez <tom.rodriguez@oracle.com> parents: 22646 diff changeset	46 import jdk.vm.ci.meta.AllocatableValue;
615f3bbbb174 Update jvmci and truffle import: Rename jdk.internal.jvmci to jdk.vm.ci Tom Rodriguez <tom.rodriguez@oracle.com> parents: 22646 diff changeset	47 import jdk.vm.ci.meta.LIRKind;
615f3bbbb174 Update jvmci and truffle import: Rename jdk.internal.jvmci to jdk.vm.ci Tom Rodriguez <tom.rodriguez@oracle.com> parents: 22646 diff changeset	48 import jdk.vm.ci.meta.Value;
22350 06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	49
22646 05183a084a08 updated imports to be explicit and added checkstyle rule to forbid * imports Doug Simon <doug.simon@oracle.com> parents: 22573 diff changeset	50 import com.oracle.graal.debug.Debug;
23154 f2a8407253da TraceRA: move resolution: count number of created stack slots. Josef Eisl <josef.eisl@jku.at> parents: 23124 diff changeset	51 import com.oracle.graal.debug.DebugMetric;
22646 05183a084a08 updated imports to be explicit and added checkstyle rule to forbid * imports Doug Simon <doug.simon@oracle.com> parents: 22573 diff changeset	52 import com.oracle.graal.debug.Indent;
05183a084a08 updated imports to be explicit and added checkstyle rule to forbid * imports Doug Simon <doug.simon@oracle.com> parents: 22573 diff changeset	53 import com.oracle.graal.lir.LIRInsertionBuffer;
05183a084a08 updated imports to be explicit and added checkstyle rule to forbid * imports Doug Simon <doug.simon@oracle.com> parents: 22573 diff changeset	54 import com.oracle.graal.lir.LIRInstruction;
22843 ae8a63a7aa9e Update jvmci import: Move VirtualStackSlot from JVMCI to Graal and remove referenceMapIndex. Roland Schatz <roland.schatz@oracle.com> parents: 22790 diff changeset	55 import com.oracle.graal.lir.VirtualStackSlot;
22646 05183a084a08 updated imports to be explicit and added checkstyle rule to forbid * imports Doug Simon <doug.simon@oracle.com> parents: 22573 diff changeset	56 import com.oracle.graal.lir.framemap.FrameMap;
05183a084a08 updated imports to be explicit and added checkstyle rule to forbid * imports Doug Simon <doug.simon@oracle.com> parents: 22573 diff changeset	57 import com.oracle.graal.lir.framemap.FrameMapBuilder;
05183a084a08 updated imports to be explicit and added checkstyle rule to forbid * imports Doug Simon <doug.simon@oracle.com> parents: 22573 diff changeset	58 import com.oracle.graal.lir.framemap.FrameMapBuilderTool;
05183a084a08 updated imports to be explicit and added checkstyle rule to forbid * imports Doug Simon <doug.simon@oracle.com> parents: 22573 diff changeset	59 import com.oracle.graal.lir.gen.LIRGenerationResult;
22927 526b102d5a20 Move creation of move instructions into separate factory. Roland Schatz <roland.schatz@oracle.com> parents: 22843 diff changeset	60 import com.oracle.graal.lir.gen.LIRGeneratorTool.MoveFactory;
22350 06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	61
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	62 /**
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	63 */
22978 64eb72b6165d TraceRA: add TraceGlobalMoveResolutionMappingTest. Josef Eisl <josef.eisl@jku.at> parents: 22976 diff changeset	64 final class TraceGlobalMoveResolver extends TraceGlobalMoveResolutionPhase.MoveResolver {
22350 06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	65
23154 f2a8407253da TraceRA: move resolution: count number of created stack slots. Josef Eisl <josef.eisl@jku.at> parents: 23124 diff changeset	66 private static final DebugMetric cycleBreakingSlotsAllocated = Debug.metric("TraceRA[cycleBreakingSlotsAllocated(global)]");
f2a8407253da TraceRA: move resolution: count number of created stack slots. Josef Eisl <josef.eisl@jku.at> parents: 23124 diff changeset	67
22350 06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	68 private int insertIdx;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	69 private LIRInsertionBuffer insertionBuffer; // buffer where moves are inserted
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	70
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	71 private final List<Value> mappingFrom;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	72 private final List<AllocatableValue> mappingTo;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	73 private final int[] registerBlocked;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	74 private static final int STACK_SLOT_IN_CALLER_FRAME_IDX = -1;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	75 private int[] stackBlocked;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	76 private final int firstVirtualStackIndex;
22927 526b102d5a20 Move creation of move instructions into separate factory. Roland Schatz <roland.schatz@oracle.com> parents: 22843 diff changeset	77 private final MoveFactory spillMoveFactory;
22350 06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	78 private final FrameMapBuilder frameMapBuilder;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	79
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	80 private void setValueBlocked(Value location, int direction) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	81 assert direction == 1 \|\| direction == -1 : "out of bounds";
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	82 if (isStackSlotValue(location)) {
22843 ae8a63a7aa9e Update jvmci import: Move VirtualStackSlot from JVMCI to Graal and remove referenceMapIndex. Roland Schatz <roland.schatz@oracle.com> parents: 22790 diff changeset	83 int stackIdx = getStackArrayIndex(location);
22350 06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	84 if (stackIdx == STACK_SLOT_IN_CALLER_FRAME_IDX) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	85 // incoming stack arguments can be ignored
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	86 return;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	87 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	88 if (stackIdx >= stackBlocked.length) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	89 stackBlocked = Arrays.copyOf(stackBlocked, stackIdx + 1);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	90 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	91 stackBlocked[stackIdx] += direction;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	92 } else {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	93 assert direction == 1 \|\| direction == -1 : "out of bounds";
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	94 if (isRegister(location)) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	95 registerBlocked[asRegister(location).number] += direction;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	96 } else {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	97 throw JVMCIError.shouldNotReachHere("unhandled value " + location);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	98 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	99 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	100 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	101
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	102 private int valueBlocked(Value location) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	103 if (isStackSlotValue(location)) {
22843 ae8a63a7aa9e Update jvmci import: Move VirtualStackSlot from JVMCI to Graal and remove referenceMapIndex. Roland Schatz <roland.schatz@oracle.com> parents: 22790 diff changeset	104 int stackIdx = getStackArrayIndex(location);
22350 06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	105 if (stackIdx == STACK_SLOT_IN_CALLER_FRAME_IDX) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	106 // incoming stack arguments are always blocked (aka they can not be written)
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	107 return 1;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	108 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	109 if (stackIdx >= stackBlocked.length) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	110 return 0;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	111 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	112 return stackBlocked[stackIdx];
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	113 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	114 if (isRegister(location)) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	115 return registerBlocked[asRegister(location).number];
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	116 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	117 throw JVMCIError.shouldNotReachHere("unhandled value " + location);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	118 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	119
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	120 private static boolean areMultipleReadsAllowed() {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	121 return true;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	122 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	123
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	124 private boolean hasMappings() {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	125 return mappingFrom.size() > 0;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	126 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	127
22927 526b102d5a20 Move creation of move instructions into separate factory. Roland Schatz <roland.schatz@oracle.com> parents: 22843 diff changeset	128 private MoveFactory getSpillMoveFactory() {
22350 06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	129 return spillMoveFactory;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	130 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	131
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	132 private Register[] getRegisters() {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	133 return frameMapBuilder.getRegisterConfig().getAllocatableRegisters();
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	134 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	135
22927 526b102d5a20 Move creation of move instructions into separate factory. Roland Schatz <roland.schatz@oracle.com> parents: 22843 diff changeset	136 public TraceGlobalMoveResolver(LIRGenerationResult res, MoveFactory spillMoveFactory, Architecture arch) {
22350 06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	137
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	138 this.mappingFrom = new ArrayList<>(8);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	139 this.mappingTo = new ArrayList<>(8);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	140 this.insertIdx = -1;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	141 this.insertionBuffer = new LIRInsertionBuffer();
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	142
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	143 this.frameMapBuilder = res.getFrameMapBuilder();
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	144 this.spillMoveFactory = spillMoveFactory;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	145 this.registerBlocked = new int[arch.getRegisters().length];
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	146
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	147 FrameMapBuilderTool frameMapBuilderTool = (FrameMapBuilderTool) frameMapBuilder;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	148 this.stackBlocked = new int[frameMapBuilderTool.getNumberOfStackSlots()];
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	149
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	150 FrameMap frameMap = frameMapBuilderTool.getFrameMap();
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	151 this.firstVirtualStackIndex = !frameMap.frameNeedsAllocating() ? 0 : frameMap.currentFrameSize() + 1;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	152 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	153
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	154 private boolean checkEmpty() {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	155 for (int i = 0; i < stackBlocked.length; i++) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	156 assert stackBlocked[i] == 0 : "stack map must be empty before and after processing";
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	157 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	158 assert mappingFrom.size() == 0 && mappingTo.size() == 0 : "list must be empty before and after processing";
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	159 for (int i = 0; i < getRegisters().length; i++) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	160 assert registerBlocked[i] == 0 : "register map must be empty before and after processing";
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	161 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	162 return true;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	163 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	164
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	165 private boolean verifyBeforeResolve() {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	166 assert mappingFrom.size() == mappingTo.size() : "length must be equal";
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	167 assert insertIdx != -1 : "insert position not set";
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	168
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	169 int i;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	170 int j;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	171 if (!areMultipleReadsAllowed()) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	172 for (i = 0; i < mappingFrom.size(); i++) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	173 for (j = i + 1; j < mappingFrom.size(); j++) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	174 assert mappingFrom.get(i) == null \|\| mappingFrom.get(i) != mappingFrom.get(j) : "cannot read from same interval twice";
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	175 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	176 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	177 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	178
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	179 for (i = 0; i < mappingTo.size(); i++) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	180 for (j = i + 1; j < mappingTo.size(); j++) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	181 assert mappingTo.get(i) != mappingTo.get(j) : "cannot write to same interval twice";
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	182 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	183 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	184
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	185 for (i = 0; i < mappingTo.size(); i++) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	186 Value to = mappingTo.get(i);
22843 ae8a63a7aa9e Update jvmci import: Move VirtualStackSlot from JVMCI to Graal and remove referenceMapIndex. Roland Schatz <roland.schatz@oracle.com> parents: 22790 diff changeset	187 assert !isStackSlotValue(to) \|\| getStackArrayIndex(to) != STACK_SLOT_IN_CALLER_FRAME_IDX : "Cannot move to in argument: " + to;
22350 06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	188 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	189
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	190 HashSet<Value> usedRegs = new HashSet<>();
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	191 if (!areMultipleReadsAllowed()) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	192 for (i = 0; i < mappingFrom.size(); i++) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	193 Value from = mappingFrom.get(i);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	194 if (from != null && !isIllegal(from)) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	195 boolean unique = usedRegs.add(from);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	196 assert unique : "cannot read from same register twice";
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	197 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	198 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	199 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	200
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	201 usedRegs.clear();
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	202 for (i = 0; i < mappingTo.size(); i++) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	203 Value to = mappingTo.get(i);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	204 if (isIllegal(to)) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	205 // After insertion the location may become illegal, so don't check it since multiple
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	206 // intervals might be illegal.
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	207 continue;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	208 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	209 boolean unique = usedRegs.add(to);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	210 assert unique : "cannot write to same register twice";
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	211 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	212
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	213 return true;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	214 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	215
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	216 // mark assignedReg and assignedRegHi of the interval as blocked
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	217 private void block(Value location) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	218 if (mightBeBlocked(location)) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	219 assert areMultipleReadsAllowed() \|\| valueBlocked(location) == 0 : "location already marked as used: " + location;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	220 setValueBlocked(location, 1);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	221 Debug.log("block %s", location);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	222 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	223 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	224
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	225 // mark assignedReg and assignedRegHi of the interval as unblocked
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	226 private void unblock(Value location) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	227 if (mightBeBlocked(location)) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	228 assert valueBlocked(location) > 0 : "location already marked as unused: " + location;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	229 setValueBlocked(location, -1);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	230 Debug.log("unblock %s", location);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	231 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	232 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	233
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	234 /**
23124 23f9a72eb037 TraceRA: move Trace Linear Scan implementation into sub-package. Josef Eisl <josef.eisl@jku.at> parents: 22978 diff changeset	235 * Checks if {@code to} is not blocked or is only blocked by {@code from}.
22350 06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	236 */
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	237 private boolean safeToProcessMove(Value fromLocation, Value toLocation) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	238 if (mightBeBlocked(toLocation)) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	239 if ((valueBlocked(toLocation) > 1 \|\| (valueBlocked(toLocation) == 1 && !isMoveToSelf(fromLocation, toLocation)))) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	240 return false;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	241 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	242 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	243
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	244 return true;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	245 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	246
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	247 public static boolean isMoveToSelf(Value from, Value to) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	248 assert to != null;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	249 if (to.equals(from)) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	250 return true;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	251 }
22447 cc1f997e6185 TraceRA: intoduce ShadowedRegisterValue. Josef Eisl <josef.eisl@jku.at> parents: 22352 diff changeset	252 if (from == null) {
cc1f997e6185 TraceRA: intoduce ShadowedRegisterValue. Josef Eisl <josef.eisl@jku.at> parents: 22352 diff changeset	253 return false;
cc1f997e6185 TraceRA: intoduce ShadowedRegisterValue. Josef Eisl <josef.eisl@jku.at> parents: 22352 diff changeset	254 }
cc1f997e6185 TraceRA: intoduce ShadowedRegisterValue. Josef Eisl <josef.eisl@jku.at> parents: 22352 diff changeset	255 if (isShadowedRegisterValue(from)) {
22976 fe8534ad7e6e TraceRA: TraceGlobalMoveResolutionPhase: proper handling of ShadowedRegisterValue in LabelOp.incoming. Josef Eisl <josef.eisl@jku.at> parents: 22927 diff changeset	256 /* From is a shadowed register. */
fe8534ad7e6e TraceRA: TraceGlobalMoveResolutionPhase: proper handling of ShadowedRegisterValue in LabelOp.incoming. Josef Eisl <josef.eisl@jku.at> parents: 22927 diff changeset	257 if (isShadowedRegisterValue(to)) {
fe8534ad7e6e TraceRA: TraceGlobalMoveResolutionPhase: proper handling of ShadowedRegisterValue in LabelOp.incoming. Josef Eisl <josef.eisl@jku.at> parents: 22927 diff changeset	258 // both shadowed but not equal
fe8534ad7e6e TraceRA: TraceGlobalMoveResolutionPhase: proper handling of ShadowedRegisterValue in LabelOp.incoming. Josef Eisl <josef.eisl@jku.at> parents: 22927 diff changeset	259 return false;
fe8534ad7e6e TraceRA: TraceGlobalMoveResolutionPhase: proper handling of ShadowedRegisterValue in LabelOp.incoming. Josef Eisl <josef.eisl@jku.at> parents: 22927 diff changeset	260 }
22447 cc1f997e6185 TraceRA: intoduce ShadowedRegisterValue. Josef Eisl <josef.eisl@jku.at> parents: 22352 diff changeset	261 ShadowedRegisterValue shadowed = asShadowedRegisterValue(from);
22976 fe8534ad7e6e TraceRA: TraceGlobalMoveResolutionPhase: proper handling of ShadowedRegisterValue in LabelOp.incoming. Josef Eisl <josef.eisl@jku.at> parents: 22927 diff changeset	262 if (isRegisterToRegisterMoveToSelf(shadowed.getRegister(), to)) {
fe8534ad7e6e TraceRA: TraceGlobalMoveResolutionPhase: proper handling of ShadowedRegisterValue in LabelOp.incoming. Josef Eisl <josef.eisl@jku.at> parents: 22927 diff changeset	263 return true;
fe8534ad7e6e TraceRA: TraceGlobalMoveResolutionPhase: proper handling of ShadowedRegisterValue in LabelOp.incoming. Josef Eisl <josef.eisl@jku.at> parents: 22927 diff changeset	264 }
fe8534ad7e6e TraceRA: TraceGlobalMoveResolutionPhase: proper handling of ShadowedRegisterValue in LabelOp.incoming. Josef Eisl <josef.eisl@jku.at> parents: 22927 diff changeset	265 if (isStackSlotValue(to)) {
fe8534ad7e6e TraceRA: TraceGlobalMoveResolutionPhase: proper handling of ShadowedRegisterValue in LabelOp.incoming. Josef Eisl <josef.eisl@jku.at> parents: 22927 diff changeset	266 return to.equals(shadowed.getStackSlot());
22447 cc1f997e6185 TraceRA: intoduce ShadowedRegisterValue. Josef Eisl <josef.eisl@jku.at> parents: 22352 diff changeset	267 }
22976 fe8534ad7e6e TraceRA: TraceGlobalMoveResolutionPhase: proper handling of ShadowedRegisterValue in LabelOp.incoming. Josef Eisl <josef.eisl@jku.at> parents: 22927 diff changeset	268 } else {
fe8534ad7e6e TraceRA: TraceGlobalMoveResolutionPhase: proper handling of ShadowedRegisterValue in LabelOp.incoming. Josef Eisl <josef.eisl@jku.at> parents: 22927 diff changeset	269 /*
fe8534ad7e6e TraceRA: TraceGlobalMoveResolutionPhase: proper handling of ShadowedRegisterValue in LabelOp.incoming. Josef Eisl <josef.eisl@jku.at> parents: 22927 diff changeset	270 * A shadowed destination value is never a self move it both values are not equal. Fall
fe8534ad7e6e TraceRA: TraceGlobalMoveResolutionPhase: proper handling of ShadowedRegisterValue in LabelOp.incoming. Josef Eisl <josef.eisl@jku.at> parents: 22927 diff changeset	271 * through.
fe8534ad7e6e TraceRA: TraceGlobalMoveResolutionPhase: proper handling of ShadowedRegisterValue in LabelOp.incoming. Josef Eisl <josef.eisl@jku.at> parents: 22927 diff changeset	272 */
fe8534ad7e6e TraceRA: TraceGlobalMoveResolutionPhase: proper handling of ShadowedRegisterValue in LabelOp.incoming. Josef Eisl <josef.eisl@jku.at> parents: 22927 diff changeset	273 // if (isShadowedRegisterValue(to)) return false;
fe8534ad7e6e TraceRA: TraceGlobalMoveResolutionPhase: proper handling of ShadowedRegisterValue in LabelOp.incoming. Josef Eisl <josef.eisl@jku.at> parents: 22927 diff changeset	274
fe8534ad7e6e TraceRA: TraceGlobalMoveResolutionPhase: proper handling of ShadowedRegisterValue in LabelOp.incoming. Josef Eisl <josef.eisl@jku.at> parents: 22927 diff changeset	275 return isRegisterToRegisterMoveToSelf(from, to);
fe8534ad7e6e TraceRA: TraceGlobalMoveResolutionPhase: proper handling of ShadowedRegisterValue in LabelOp.incoming. Josef Eisl <josef.eisl@jku.at> parents: 22927 diff changeset	276 }
fe8534ad7e6e TraceRA: TraceGlobalMoveResolutionPhase: proper handling of ShadowedRegisterValue in LabelOp.incoming. Josef Eisl <josef.eisl@jku.at> parents: 22927 diff changeset	277 return false;
fe8534ad7e6e TraceRA: TraceGlobalMoveResolutionPhase: proper handling of ShadowedRegisterValue in LabelOp.incoming. Josef Eisl <josef.eisl@jku.at> parents: 22927 diff changeset	278 }
fe8534ad7e6e TraceRA: TraceGlobalMoveResolutionPhase: proper handling of ShadowedRegisterValue in LabelOp.incoming. Josef Eisl <josef.eisl@jku.at> parents: 22927 diff changeset	279
fe8534ad7e6e TraceRA: TraceGlobalMoveResolutionPhase: proper handling of ShadowedRegisterValue in LabelOp.incoming. Josef Eisl <josef.eisl@jku.at> parents: 22927 diff changeset	280 private static boolean isRegisterToRegisterMoveToSelf(Value from, Value to) {
fe8534ad7e6e TraceRA: TraceGlobalMoveResolutionPhase: proper handling of ShadowedRegisterValue in LabelOp.incoming. Josef Eisl <josef.eisl@jku.at> parents: 22927 diff changeset	281 if (to.equals(from)) {
fe8534ad7e6e TraceRA: TraceGlobalMoveResolutionPhase: proper handling of ShadowedRegisterValue in LabelOp.incoming. Josef Eisl <josef.eisl@jku.at> parents: 22927 diff changeset	282 return true;
fe8534ad7e6e TraceRA: TraceGlobalMoveResolutionPhase: proper handling of ShadowedRegisterValue in LabelOp.incoming. Josef Eisl <josef.eisl@jku.at> parents: 22927 diff changeset	283 }
fe8534ad7e6e TraceRA: TraceGlobalMoveResolutionPhase: proper handling of ShadowedRegisterValue in LabelOp.incoming. Josef Eisl <josef.eisl@jku.at> parents: 22927 diff changeset	284 if (isRegister(from) && isRegister(to) && asRegister(from).equals(asRegister(to))) {
fe8534ad7e6e TraceRA: TraceGlobalMoveResolutionPhase: proper handling of ShadowedRegisterValue in LabelOp.incoming. Josef Eisl <josef.eisl@jku.at> parents: 22927 diff changeset	285 // Values differ but Registers are the same
22350 06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	286 assert LIRKind.verifyMoveKinds(to.getLIRKind(), from.getLIRKind()) : String.format("Same register but Kind mismatch %s <- %s", to, from);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	287 return true;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	288 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	289 return false;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	290 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	291
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	292 private static boolean mightBeBlocked(Value location) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	293 return isRegister(location) \|\| isStackSlotValue(location);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	294 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	295
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	296 private void createInsertionBuffer(List<LIRInstruction> list) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	297 assert !insertionBuffer.initialized() : "overwriting existing buffer";
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	298 insertionBuffer.init(list);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	299 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	300
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	301 private void appendInsertionBuffer() {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	302 if (insertionBuffer.initialized()) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	303 insertionBuffer.finish();
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	304 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	305 assert !insertionBuffer.initialized() : "must be uninitialized now";
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	306
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	307 insertIdx = -1;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	308 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	309
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	310 private void insertMove(Value fromOperand, AllocatableValue toOperand) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	311 assert !fromOperand.equals(toOperand) : "from and to are equal: " + fromOperand + " vs. " + toOperand;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	312 assert LIRKind.verifyMoveKinds(fromOperand.getLIRKind(), fromOperand.getLIRKind()) : "move between different types";
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	313 assert insertIdx != -1 : "must setup insert position first";
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	314
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	315 insertionBuffer.append(insertIdx, createMove(fromOperand, toOperand));
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	316
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	317 if (Debug.isLogEnabled()) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	318 Debug.log("insert move from %s to %s at %d", fromOperand, toOperand, insertIdx);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	319 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	320 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	321
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	322 /**
23124 23f9a72eb037 TraceRA: move Trace Linear Scan implementation into sub-package. Josef Eisl <josef.eisl@jku.at> parents: 22978 diff changeset	323 * @param fromOpr Operand of the {@code from} interval
23f9a72eb037 TraceRA: move Trace Linear Scan implementation into sub-package. Josef Eisl <josef.eisl@jku.at> parents: 22978 diff changeset	324 * @param toOpr Operand of the {@code to} interval
22350 06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	325 */
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	326 private LIRInstruction createMove(Value fromOpr, AllocatableValue toOpr) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	327 if (isStackSlotValue(toOpr) && isStackSlotValue(fromOpr)) {
22843 ae8a63a7aa9e Update jvmci import: Move VirtualStackSlot from JVMCI to Graal and remove referenceMapIndex. Roland Schatz <roland.schatz@oracle.com> parents: 22790 diff changeset	328 return getSpillMoveFactory().createStackMove(toOpr, asAllocatableValue(fromOpr));
22350 06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	329 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	330 return getSpillMoveFactory().createMove(toOpr, fromOpr);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	331 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	332
22573 74b3e5c0209c suppressed -Xlint:try warnings Doug Simon <doug.simon@oracle.com> parents: 22565 diff changeset	333 @SuppressWarnings("try")
22350 06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	334 private void resolveMappings() {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	335 try (Indent indent = Debug.logAndIndent("resolveMapping")) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	336 assert verifyBeforeResolve();
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	337 if (Debug.isLogEnabled()) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	338 printMapping();
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	339 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	340
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	341 // Block all registers that are used as input operands of a move.
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	342 // When a register is blocked, no move to this register is emitted.
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	343 // This is necessary for detecting cycles in moves.
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	344 for (int i = mappingFrom.size() - 1; i >= 0; i--) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	345 Value from = mappingFrom.get(i);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	346 block(from);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	347 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	348
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	349 int spillCandidate = -1;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	350 while (mappingFrom.size() > 0) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	351 boolean processedInterval = false;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	352
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	353 for (int i = mappingFrom.size() - 1; i >= 0; i--) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	354 Value fromInterval = mappingFrom.get(i);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	355 AllocatableValue toInterval = mappingTo.get(i);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	356
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	357 Value fromLocation = fromInterval;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	358 AllocatableValue toLocation = toInterval;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	359 if (safeToProcessMove(fromLocation, toLocation)) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	360 // this interval can be processed because target is free
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	361 insertMove(fromLocation, toLocation);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	362 unblock(fromLocation);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	363 mappingFrom.remove(i);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	364 mappingTo.remove(i);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	365
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	366 processedInterval = true;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	367 } else if (fromInterval != null && isRegister(fromLocation)) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	368 // this interval cannot be processed now because target is not free
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	369 // it starts in a register, so it is a possible candidate for spilling
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	370 spillCandidate = i;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	371 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	372 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	373
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	374 if (!processedInterval) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	375 breakCycle(spillCandidate);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	376 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	377 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	378 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	379
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	380 // check that all intervals have been processed
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	381 assert checkEmpty();
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	382 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	383
22573 74b3e5c0209c suppressed -Xlint:try warnings Doug Simon <doug.simon@oracle.com> parents: 22565 diff changeset	384 @SuppressWarnings("try")
22350 06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	385 private void breakCycle(int spillCandidate) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	386 // no move could be processed because there is a cycle in the move list
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	387 // (e.g. r1 . r2, r2 . r1), so one interval must be spilled to memory
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	388 assert spillCandidate != -1 : "no interval in register for spilling found";
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	389
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	390 // create a new spill interval and assign a stack slot to it
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	391 Value from = mappingFrom.get(spillCandidate);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	392 try (Indent indent = Debug.logAndIndent("BreakCycle: %s", from)) {
22843 ae8a63a7aa9e Update jvmci import: Move VirtualStackSlot from JVMCI to Graal and remove referenceMapIndex. Roland Schatz <roland.schatz@oracle.com> parents: 22790 diff changeset	393 VirtualStackSlot spillSlot = frameMapBuilder.allocateSpillSlot(from.getLIRKind());
23154 f2a8407253da TraceRA: move resolution: count number of created stack slots. Josef Eisl <josef.eisl@jku.at> parents: 23124 diff changeset	394 cycleBreakingSlotsAllocated.increment();
22350 06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	395 if (Debug.isLogEnabled()) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	396 Debug.log("created new slot for spilling: %s", spillSlot);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	397 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	398 // insert a move from register to stack and update the mapping
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	399 insertMove(from, spillSlot);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	400 block(spillSlot);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	401 mappingFrom.set(spillCandidate, spillSlot);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	402 unblock(from);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	403 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	404 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	405
22573 74b3e5c0209c suppressed -Xlint:try warnings Doug Simon <doug.simon@oracle.com> parents: 22565 diff changeset	406 @SuppressWarnings("try")
22350 06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	407 private void printMapping() {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	408 try (Indent indent = Debug.logAndIndent("Mapping")) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	409 for (int i = mappingFrom.size() - 1; i >= 0; i--) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	410 Debug.log("move %s <- %s", mappingTo.get(i), mappingFrom.get(i));
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	411 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	412 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	413 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	414
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	415 public void setInsertPosition(List<LIRInstruction> insertList, int insertIdx) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	416 assert this.insertIdx == -1 : "use moveInsertPosition instead of setInsertPosition when data already set";
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	417
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	418 createInsertionBuffer(insertList);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	419 this.insertIdx = insertIdx;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	420 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	421
22978 64eb72b6165d TraceRA: add TraceGlobalMoveResolutionMappingTest. Josef Eisl <josef.eisl@jku.at> parents: 22976 diff changeset	422 @Override
22350 06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	423 public void addMapping(Value from, AllocatableValue to) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	424 if (Debug.isLogEnabled()) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	425 Debug.log("add move mapping from %s to %s", from, to);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	426 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	427
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	428 assert !from.equals(to) : "from and to interval equal: " + from;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	429 assert LIRKind.verifyMoveKinds(to.getLIRKind(), from.getLIRKind()) : String.format("Kind mismatch: %s vs. %s, from=%s, to=%s", from.getLIRKind(), to.getLIRKind(), from, to);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	430 mappingFrom.add(from);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	431 mappingTo.add(to);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	432 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	433
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	434 public void resolveAndAppendMoves() {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	435 if (hasMappings()) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	436 resolveMappings();
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	437 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	438 appendInsertionBuffer();
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	439 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	440
22843 ae8a63a7aa9e Update jvmci import: Move VirtualStackSlot from JVMCI to Graal and remove referenceMapIndex. Roland Schatz <roland.schatz@oracle.com> parents: 22790 diff changeset	441 private int getStackArrayIndex(Value stackSlotValue) {
22350 06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	442 if (isStackSlot(stackSlotValue)) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	443 return getStackArrayIndex(asStackSlot(stackSlotValue));
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	444 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	445 if (isVirtualStackSlot(stackSlotValue)) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	446 return getStackArrayIndex(asVirtualStackSlot(stackSlotValue));
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	447 }
22843 ae8a63a7aa9e Update jvmci import: Move VirtualStackSlot from JVMCI to Graal and remove referenceMapIndex. Roland Schatz <roland.schatz@oracle.com> parents: 22790 diff changeset	448 throw JVMCIError.shouldNotReachHere("value is not a stack slot: " + stackSlotValue);
22350 06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	449 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	450
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	451 private int getStackArrayIndex(StackSlot stackSlot) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	452 int stackIdx;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	453 if (stackSlot.isInCallerFrame()) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	454 // incoming stack arguments can be ignored
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	455 stackIdx = STACK_SLOT_IN_CALLER_FRAME_IDX;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	456 } else {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	457 assert stackSlot.getRawAddFrameSize() : "Unexpected stack slot: " + stackSlot;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	458 int offset = -stackSlot.getRawOffset();
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	459 assert 0 <= offset && offset < firstVirtualStackIndex : String.format("Wrong stack slot offset: %d (first virtual stack slot index: %d", offset, firstVirtualStackIndex);
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	460 stackIdx = offset;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	461 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	462 return stackIdx;
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	463 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	464
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	465 private int getStackArrayIndex(VirtualStackSlot virtualStackSlot) {
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	466 return firstVirtualStackIndex + virtualStackSlot.getId();
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	467 }
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	468
06a9e6737dcf Drop initial version of the trace based register allocator. Josef Eisl <josef.eisl@jku.at> parents: diff changeset	469 }

Mercurial > hg > graal-compiler

annotate graal/com.oracle.graal.lir/src/com/oracle/graal/lir/alloc/trace/TraceGlobalMoveResolver.java @ 23154:f2a8407253da