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comparison src/share/vm/runtime/globals.hpp @ 219:ab65a4c9b2e8

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6708714: Optimize long LShift on 32-bits x86 Summary: For small (1-3 bits) left long shifts in 32-bits VM use sets of add+addc instructions instead of shld+shl on new AMD cpus. Reviewed-by: never Contributed-by: shrinivas.joshi@amd.com
author kvn
date Mon, 23 Jun 2008 14:11:12 -0700
parents 6d13fcb3663f
children 9c2ecc2ffb12 12eea04c8b06 fab5f738c515
comparison
equal deleted inserted replaced
217:411c61adc994 219:ab65a4c9b2e8
944 "Enable/disable lazy opening of boot class path entries") \ 944 "Enable/disable lazy opening of boot class path entries") \
945 \ 945 \
946 diagnostic(bool, UseIncDec, true, \ 946 diagnostic(bool, UseIncDec, true, \
947 "Use INC, DEC instructions on x86") \ 947 "Use INC, DEC instructions on x86") \
948 \ 948 \
949 product(bool, UseNewLongLShift, false, \
950 "Use optimized bitwise shift left") \
951 \
949 product(bool, UseStoreImmI16, true, \ 952 product(bool, UseStoreImmI16, true, \
950 "Use store immediate 16-bits value instruction on x86") \ 953 "Use store immediate 16-bits value instruction on x86") \
951 \ 954 \
952 product(bool, UseAddressNop, false, \ 955 product(bool, UseAddressNop, false, \
953 "Use '0F 1F [addr]' NOP instructions on x86 cpus") \ 956 "Use '0F 1F [addr]' NOP instructions on x86 cpus") \