Mercurial > hg > graal-compiler
comparison src/share/vm/opto/chaitin.cpp @ 12071:adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
Summary: public methods that don't need to be public should be private.
Reviewed-by: kvn, twisti
author | adlertz |
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date | Fri, 16 Aug 2013 10:23:55 +0200 |
parents | d1034bd8cefc |
children | 4b2838704fd5 |
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12070:afbe18ae0905 | 12071:adb9a7d94cb5 |
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38 #include "opto/machnode.hpp" | 38 #include "opto/machnode.hpp" |
39 #include "opto/memnode.hpp" | 39 #include "opto/memnode.hpp" |
40 #include "opto/opcodes.hpp" | 40 #include "opto/opcodes.hpp" |
41 #include "opto/rootnode.hpp" | 41 #include "opto/rootnode.hpp" |
42 | 42 |
43 //============================================================================= | |
44 | |
45 #ifndef PRODUCT | 43 #ifndef PRODUCT |
46 void LRG::dump( ) const { | 44 void LRG::dump() const { |
47 ttyLocker ttyl; | 45 ttyLocker ttyl; |
48 tty->print("%d ",num_regs()); | 46 tty->print("%d ",num_regs()); |
49 _mask.dump(); | 47 _mask.dump(); |
50 if( _msize_valid ) { | 48 if( _msize_valid ) { |
51 if( mask_size() == compute_mask_size() ) tty->print(", #%d ",_mask_size); | 49 if( mask_size() == compute_mask_size() ) tty->print(", #%d ",_mask_size); |
92 | 90 |
93 tty->cr(); | 91 tty->cr(); |
94 } | 92 } |
95 #endif | 93 #endif |
96 | 94 |
97 //------------------------------score------------------------------------------ | |
98 // Compute score from cost and area. Low score is best to spill. | 95 // Compute score from cost and area. Low score is best to spill. |
99 static double raw_score( double cost, double area ) { | 96 static double raw_score( double cost, double area ) { |
100 return cost - (area*RegisterCostAreaRatio) * 1.52588e-5; | 97 return cost - (area*RegisterCostAreaRatio) * 1.52588e-5; |
101 } | 98 } |
102 | 99 |
123 return score + 1e10; // Likely no progress to spill | 120 return score + 1e10; // Likely no progress to spill |
124 | 121 |
125 return score; | 122 return score; |
126 } | 123 } |
127 | 124 |
128 //------------------------------LRG_List--------------------------------------- | |
129 LRG_List::LRG_List( uint max ) : _cnt(max), _max(max), _lidxs(NEW_RESOURCE_ARRAY(uint,max)) { | 125 LRG_List::LRG_List( uint max ) : _cnt(max), _max(max), _lidxs(NEW_RESOURCE_ARRAY(uint,max)) { |
130 memset( _lidxs, 0, sizeof(uint)*max ); | 126 memset( _lidxs, 0, sizeof(uint)*max ); |
131 } | 127 } |
132 | 128 |
133 void LRG_List::extend( uint nidx, uint lidx ) { | 129 void LRG_List::extend( uint nidx, uint lidx ) { |
209 next = _uf_map[lrg]; | 205 next = _uf_map[lrg]; |
210 } | 206 } |
211 return next; | 207 return next; |
212 } | 208 } |
213 | 209 |
214 //------------------------------Chaitin---------------------------------------- | |
215 PhaseChaitin::PhaseChaitin(uint unique, PhaseCFG &cfg, Matcher &matcher) | 210 PhaseChaitin::PhaseChaitin(uint unique, PhaseCFG &cfg, Matcher &matcher) |
216 : PhaseRegAlloc(unique, cfg, matcher, | 211 : PhaseRegAlloc(unique, cfg, matcher, |
217 #ifndef PRODUCT | 212 #ifndef PRODUCT |
218 print_chaitin_statistics | 213 print_chaitin_statistics |
219 #else | 214 #else |
230 , _trace_spilling(TraceSpilling || C->method_has_option("TraceSpilling")) | 225 , _trace_spilling(TraceSpilling || C->method_has_option("TraceSpilling")) |
231 #endif | 226 #endif |
232 { | 227 { |
233 NOT_PRODUCT( Compile::TracePhase t3("ctorChaitin", &_t_ctorChaitin, TimeCompiler); ) | 228 NOT_PRODUCT( Compile::TracePhase t3("ctorChaitin", &_t_ctorChaitin, TimeCompiler); ) |
234 | 229 |
235 _high_frequency_lrg = MIN2(float(OPTO_LRG_HIGH_FREQ), _cfg._outer_loop_freq); | 230 _high_frequency_lrg = MIN2(float(OPTO_LRG_HIGH_FREQ), _cfg.get_outer_loop_frequency()); |
236 | 231 |
237 // Build a list of basic blocks, sorted by frequency | 232 // Build a list of basic blocks, sorted by frequency |
238 _blks = NEW_RESOURCE_ARRAY( Block *, _cfg._num_blocks ); | 233 _blks = NEW_RESOURCE_ARRAY(Block *, _cfg.number_of_blocks()); |
239 // Experiment with sorting strategies to speed compilation | 234 // Experiment with sorting strategies to speed compilation |
240 double cutoff = BLOCK_FREQUENCY(1.0); // Cutoff for high frequency bucket | 235 double cutoff = BLOCK_FREQUENCY(1.0); // Cutoff for high frequency bucket |
241 Block **buckets[NUMBUCKS]; // Array of buckets | 236 Block **buckets[NUMBUCKS]; // Array of buckets |
242 uint buckcnt[NUMBUCKS]; // Array of bucket counters | 237 uint buckcnt[NUMBUCKS]; // Array of bucket counters |
243 double buckval[NUMBUCKS]; // Array of bucket value cutoffs | 238 double buckval[NUMBUCKS]; // Array of bucket value cutoffs |
244 for (uint i = 0; i < NUMBUCKS; i++) { | 239 for (uint i = 0; i < NUMBUCKS; i++) { |
245 buckets[i] = NEW_RESOURCE_ARRAY(Block *, _cfg._num_blocks); | 240 buckets[i] = NEW_RESOURCE_ARRAY(Block *, _cfg.number_of_blocks()); |
246 buckcnt[i] = 0; | 241 buckcnt[i] = 0; |
247 // Bump by three orders of magnitude each time | 242 // Bump by three orders of magnitude each time |
248 cutoff *= 0.001; | 243 cutoff *= 0.001; |
249 buckval[i] = cutoff; | 244 buckval[i] = cutoff; |
250 for (uint j = 0; j < _cfg._num_blocks; j++) { | 245 for (uint j = 0; j < _cfg.number_of_blocks(); j++) { |
251 buckets[i][j] = NULL; | 246 buckets[i][j] = NULL; |
252 } | 247 } |
253 } | 248 } |
254 // Sort blocks into buckets | 249 // Sort blocks into buckets |
255 for (uint i = 0; i < _cfg._num_blocks; i++) { | 250 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
256 for (uint j = 0; j < NUMBUCKS; j++) { | 251 for (uint j = 0; j < NUMBUCKS; j++) { |
257 if ((j == NUMBUCKS - 1) || (_cfg._blocks[i]->_freq > buckval[j])) { | 252 if ((j == NUMBUCKS - 1) || (_cfg.get_block(i)->_freq > buckval[j])) { |
258 // Assign block to end of list for appropriate bucket | 253 // Assign block to end of list for appropriate bucket |
259 buckets[j][buckcnt[j]++] = _cfg._blocks[i]; | 254 buckets[j][buckcnt[j]++] = _cfg.get_block(i); |
260 break; // kick out of inner loop | 255 break; // kick out of inner loop |
261 } | 256 } |
262 } | 257 } |
263 } | 258 } |
264 // Dump buckets into final block array | 259 // Dump buckets into final block array |
267 for (uint j = 0; j < buckcnt[i]; j++) { | 262 for (uint j = 0; j < buckcnt[i]; j++) { |
268 _blks[blkcnt++] = buckets[i][j]; | 263 _blks[blkcnt++] = buckets[i][j]; |
269 } | 264 } |
270 } | 265 } |
271 | 266 |
272 assert(blkcnt == _cfg._num_blocks, "Block array not totally filled"); | 267 assert(blkcnt == _cfg.number_of_blocks(), "Block array not totally filled"); |
273 } | 268 } |
274 | 269 |
275 //------------------------------Union------------------------------------------ | |
276 // union 2 sets together. | 270 // union 2 sets together. |
277 void PhaseChaitin::Union( const Node *src_n, const Node *dst_n ) { | 271 void PhaseChaitin::Union( const Node *src_n, const Node *dst_n ) { |
278 uint src = _lrg_map.find(src_n); | 272 uint src = _lrg_map.find(src_n); |
279 uint dst = _lrg_map.find(dst_n); | 273 uint dst = _lrg_map.find(dst_n); |
280 assert(src, ""); | 274 assert(src, ""); |
283 assert(dst < _lrg_map.max_lrg_id(), "oob"); | 277 assert(dst < _lrg_map.max_lrg_id(), "oob"); |
284 assert(src < dst, "always union smaller"); | 278 assert(src < dst, "always union smaller"); |
285 _lrg_map.uf_map(dst, src); | 279 _lrg_map.uf_map(dst, src); |
286 } | 280 } |
287 | 281 |
288 //------------------------------new_lrg---------------------------------------- | |
289 void PhaseChaitin::new_lrg(const Node *x, uint lrg) { | 282 void PhaseChaitin::new_lrg(const Node *x, uint lrg) { |
290 // Make the Node->LRG mapping | 283 // Make the Node->LRG mapping |
291 _lrg_map.extend(x->_idx,lrg); | 284 _lrg_map.extend(x->_idx,lrg); |
292 // Make the Union-Find mapping an identity function | 285 // Make the Union-Find mapping an identity function |
293 _lrg_map.uf_extend(lrg, lrg); | 286 _lrg_map.uf_extend(lrg, lrg); |
309 _cfg.map_node_to_block(kills, b); | 302 _cfg.map_node_to_block(kills, b); |
310 new_lrg(kills, max_lrg_id); | 303 new_lrg(kills, max_lrg_id); |
311 return true; | 304 return true; |
312 } | 305 } |
313 | 306 |
314 //------------------------------compact---------------------------------------- | |
315 // Renumber the live ranges to compact them. Makes the IFG smaller. | 307 // Renumber the live ranges to compact them. Makes the IFG smaller. |
316 void PhaseChaitin::compact() { | 308 void PhaseChaitin::compact() { |
317 // Current the _uf_map contains a series of short chains which are headed | 309 // Current the _uf_map contains a series of short chains which are headed |
318 // by a self-cycle. All the chains run from big numbers to little numbers. | 310 // by a self-cycle. All the chains run from big numbers to little numbers. |
319 // The Find() call chases the chains & shortens them for the next Find call. | 311 // The Find() call chases the chains & shortens them for the next Find call. |
675 _live = NULL; | 667 _live = NULL; |
676 _ifg = NULL; | 668 _ifg = NULL; |
677 C->set_indexSet_arena(NULL); // ResourceArea is at end of scope | 669 C->set_indexSet_arena(NULL); // ResourceArea is at end of scope |
678 } | 670 } |
679 | 671 |
680 //------------------------------de_ssa----------------------------------------- | |
681 void PhaseChaitin::de_ssa() { | 672 void PhaseChaitin::de_ssa() { |
682 // Set initial Names for all Nodes. Most Nodes get the virtual register | 673 // Set initial Names for all Nodes. Most Nodes get the virtual register |
683 // number. A few get the ZERO live range number. These do not | 674 // number. A few get the ZERO live range number. These do not |
684 // get allocated, but instead rely on correct scheduling to ensure that | 675 // get allocated, but instead rely on correct scheduling to ensure that |
685 // only one instance is simultaneously live at a time. | 676 // only one instance is simultaneously live at a time. |
686 uint lr_counter = 1; | 677 uint lr_counter = 1; |
687 for( uint i = 0; i < _cfg._num_blocks; i++ ) { | 678 for( uint i = 0; i < _cfg.number_of_blocks(); i++ ) { |
688 Block *b = _cfg._blocks[i]; | 679 Block* block = _cfg.get_block(i); |
689 uint cnt = b->_nodes.size(); | 680 uint cnt = block->_nodes.size(); |
690 | 681 |
691 // Handle all the normal Nodes in the block | 682 // Handle all the normal Nodes in the block |
692 for( uint j = 0; j < cnt; j++ ) { | 683 for( uint j = 0; j < cnt; j++ ) { |
693 Node *n = b->_nodes[j]; | 684 Node *n = block->_nodes[j]; |
694 // Pre-color to the zero live range, or pick virtual register | 685 // Pre-color to the zero live range, or pick virtual register |
695 const RegMask &rm = n->out_RegMask(); | 686 const RegMask &rm = n->out_RegMask(); |
696 _lrg_map.map(n->_idx, rm.is_NotEmpty() ? lr_counter++ : 0); | 687 _lrg_map.map(n->_idx, rm.is_NotEmpty() ? lr_counter++ : 0); |
697 } | 688 } |
698 } | 689 } |
699 // Reset the Union-Find mapping to be identity | 690 // Reset the Union-Find mapping to be identity |
700 _lrg_map.reset_uf_map(lr_counter); | 691 _lrg_map.reset_uf_map(lr_counter); |
701 } | 692 } |
702 | 693 |
703 | 694 |
704 //------------------------------gather_lrg_masks------------------------------- | |
705 // Gather LiveRanGe information, including register masks. Modification of | 695 // Gather LiveRanGe information, including register masks. Modification of |
706 // cisc spillable in_RegMasks should not be done before AggressiveCoalesce. | 696 // cisc spillable in_RegMasks should not be done before AggressiveCoalesce. |
707 void PhaseChaitin::gather_lrg_masks( bool after_aggressive ) { | 697 void PhaseChaitin::gather_lrg_masks( bool after_aggressive ) { |
708 | 698 |
709 // Nail down the frame pointer live range | 699 // Nail down the frame pointer live range |
710 uint fp_lrg = _lrg_map.live_range_id(_cfg._root->in(1)->in(TypeFunc::FramePtr)); | 700 uint fp_lrg = _lrg_map.live_range_id(_cfg.get_root_node()->in(1)->in(TypeFunc::FramePtr)); |
711 lrgs(fp_lrg)._cost += 1e12; // Cost is infinite | 701 lrgs(fp_lrg)._cost += 1e12; // Cost is infinite |
712 | 702 |
713 // For all blocks | 703 // For all blocks |
714 for( uint i = 0; i < _cfg._num_blocks; i++ ) { | 704 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
715 Block *b = _cfg._blocks[i]; | 705 Block* block = _cfg.get_block(i); |
716 | 706 |
717 // For all instructions | 707 // For all instructions |
718 for( uint j = 1; j < b->_nodes.size(); j++ ) { | 708 for (uint j = 1; j < block->_nodes.size(); j++) { |
719 Node *n = b->_nodes[j]; | 709 Node* n = block->_nodes[j]; |
720 uint input_edge_start =1; // Skip control most nodes | 710 uint input_edge_start =1; // Skip control most nodes |
721 if( n->is_Mach() ) input_edge_start = n->as_Mach()->oper_input_base(); | 711 if (n->is_Mach()) { |
712 input_edge_start = n->as_Mach()->oper_input_base(); | |
713 } | |
722 uint idx = n->is_Copy(); | 714 uint idx = n->is_Copy(); |
723 | 715 |
724 // Get virtual register number, same as LiveRanGe index | 716 // Get virtual register number, same as LiveRanGe index |
725 uint vreg = _lrg_map.live_range_id(n); | 717 uint vreg = _lrg_map.live_range_id(n); |
726 LRG &lrg = lrgs(vreg); | 718 LRG& lrg = lrgs(vreg); |
727 if( vreg ) { // No vreg means un-allocable (e.g. memory) | 719 if (vreg) { // No vreg means un-allocable (e.g. memory) |
728 | 720 |
729 // Collect has-copy bit | 721 // Collect has-copy bit |
730 if( idx ) { | 722 if (idx) { |
731 lrg._has_copy = 1; | 723 lrg._has_copy = 1; |
732 uint clidx = _lrg_map.live_range_id(n->in(idx)); | 724 uint clidx = _lrg_map.live_range_id(n->in(idx)); |
733 LRG ©_src = lrgs(clidx); | 725 LRG& copy_src = lrgs(clidx); |
734 copy_src._has_copy = 1; | 726 copy_src._has_copy = 1; |
735 } | 727 } |
736 | 728 |
737 // Check for float-vs-int live range (used in register-pressure | 729 // Check for float-vs-int live range (used in register-pressure |
738 // calculations) | 730 // calculations) |
739 const Type *n_type = n->bottom_type(); | 731 const Type *n_type = n->bottom_type(); |
740 if (n_type->is_floatingpoint()) | 732 if (n_type->is_floatingpoint()) { |
741 lrg._is_float = 1; | 733 lrg._is_float = 1; |
734 } | |
742 | 735 |
743 // Check for twice prior spilling. Once prior spilling might have | 736 // Check for twice prior spilling. Once prior spilling might have |
744 // spilled 'soft', 2nd prior spill should have spilled 'hard' and | 737 // spilled 'soft', 2nd prior spill should have spilled 'hard' and |
745 // further spilling is unlikely to make progress. | 738 // further spilling is unlikely to make progress. |
746 if( _spilled_once.test(n->_idx) ) { | 739 if (_spilled_once.test(n->_idx)) { |
747 lrg._was_spilled1 = 1; | 740 lrg._was_spilled1 = 1; |
748 if( _spilled_twice.test(n->_idx) ) | 741 if (_spilled_twice.test(n->_idx)) { |
749 lrg._was_spilled2 = 1; | 742 lrg._was_spilled2 = 1; |
743 } | |
750 } | 744 } |
751 | 745 |
752 #ifndef PRODUCT | 746 #ifndef PRODUCT |
753 if (trace_spilling() && lrg._def != NULL) { | 747 if (trace_spilling() && lrg._def != NULL) { |
754 // collect defs for MultiDef printing | 748 // collect defs for MultiDef printing |
781 assert(n_type->isa_vect() == NULL || lrg._is_vector || ireg == Op_RegD, | 775 assert(n_type->isa_vect() == NULL || lrg._is_vector || ireg == Op_RegD, |
782 "vector must be in vector registers"); | 776 "vector must be in vector registers"); |
783 | 777 |
784 // Check for bound register masks | 778 // Check for bound register masks |
785 const RegMask &lrgmask = lrg.mask(); | 779 const RegMask &lrgmask = lrg.mask(); |
786 if (lrgmask.is_bound(ireg)) | 780 if (lrgmask.is_bound(ireg)) { |
787 lrg._is_bound = 1; | 781 lrg._is_bound = 1; |
782 } | |
788 | 783 |
789 // Check for maximum frequency value | 784 // Check for maximum frequency value |
790 if (lrg._maxfreq < b->_freq) | 785 if (lrg._maxfreq < block->_freq) { |
791 lrg._maxfreq = b->_freq; | 786 lrg._maxfreq = block->_freq; |
787 } | |
792 | 788 |
793 // Check for oop-iness, or long/double | 789 // Check for oop-iness, or long/double |
794 // Check for multi-kill projection | 790 // Check for multi-kill projection |
795 switch( ireg ) { | 791 switch (ireg) { |
796 case MachProjNode::fat_proj: | 792 case MachProjNode::fat_proj: |
797 // Fat projections have size equal to number of registers killed | 793 // Fat projections have size equal to number of registers killed |
798 lrg.set_num_regs(rm.Size()); | 794 lrg.set_num_regs(rm.Size()); |
799 lrg.set_reg_pressure(lrg.num_regs()); | 795 lrg.set_reg_pressure(lrg.num_regs()); |
800 lrg._fat_proj = 1; | 796 lrg._fat_proj = 1; |
960 // Limit result register mask to acceptable registers. | 956 // Limit result register mask to acceptable registers. |
961 // Do not limit registers from uncommon uses before | 957 // Do not limit registers from uncommon uses before |
962 // AggressiveCoalesce. This effectively pre-virtual-splits | 958 // AggressiveCoalesce. This effectively pre-virtual-splits |
963 // around uncommon uses of common defs. | 959 // around uncommon uses of common defs. |
964 const RegMask &rm = n->in_RegMask(k); | 960 const RegMask &rm = n->in_RegMask(k); |
965 if (!after_aggressive && _cfg.get_block_for_node(n->in(k))->_freq > 1000 * b->_freq) { | 961 if (!after_aggressive && _cfg.get_block_for_node(n->in(k))->_freq > 1000 * block->_freq) { |
966 // Since we are BEFORE aggressive coalesce, leave the register | 962 // Since we are BEFORE aggressive coalesce, leave the register |
967 // mask untrimmed by the call. This encourages more coalescing. | 963 // mask untrimmed by the call. This encourages more coalescing. |
968 // Later, AFTER aggressive, this live range will have to spill | 964 // Later, AFTER aggressive, this live range will have to spill |
969 // but the spiller handles slow-path calls very nicely. | 965 // but the spiller handles slow-path calls very nicely. |
970 } else { | 966 } else { |
1004 lrgmask.is_misaligned_pair()) { | 1000 lrgmask.is_misaligned_pair()) { |
1005 lrg.Clear(); | 1001 lrg.Clear(); |
1006 } | 1002 } |
1007 | 1003 |
1008 // Check for maximum frequency value | 1004 // Check for maximum frequency value |
1009 if( lrg._maxfreq < b->_freq ) | 1005 if (lrg._maxfreq < block->_freq) { |
1010 lrg._maxfreq = b->_freq; | 1006 lrg._maxfreq = block->_freq; |
1007 } | |
1011 | 1008 |
1012 } // End for all allocated inputs | 1009 } // End for all allocated inputs |
1013 } // end for all instructions | 1010 } // end for all instructions |
1014 } // end for all blocks | 1011 } // end for all blocks |
1015 | 1012 |
1027 } | 1024 } |
1028 lrg.set_degree(0); // no neighbors in IFG yet | 1025 lrg.set_degree(0); // no neighbors in IFG yet |
1029 } | 1026 } |
1030 } | 1027 } |
1031 | 1028 |
1032 //------------------------------set_was_low------------------------------------ | |
1033 // Set the was-lo-degree bit. Conservative coalescing should not change the | 1029 // Set the was-lo-degree bit. Conservative coalescing should not change the |
1034 // colorability of the graph. If any live range was of low-degree before | 1030 // colorability of the graph. If any live range was of low-degree before |
1035 // coalescing, it should Simplify. This call sets the was-lo-degree bit. | 1031 // coalescing, it should Simplify. This call sets the was-lo-degree bit. |
1036 // The bit is checked in Simplify. | 1032 // The bit is checked in Simplify. |
1037 void PhaseChaitin::set_was_low() { | 1033 void PhaseChaitin::set_was_low() { |
1064 #endif | 1060 #endif |
1065 } | 1061 } |
1066 | 1062 |
1067 #define REGISTER_CONSTRAINED 16 | 1063 #define REGISTER_CONSTRAINED 16 |
1068 | 1064 |
1069 //------------------------------cache_lrg_info--------------------------------- | |
1070 // Compute cost/area ratio, in case we spill. Build the lo-degree list. | 1065 // Compute cost/area ratio, in case we spill. Build the lo-degree list. |
1071 void PhaseChaitin::cache_lrg_info( ) { | 1066 void PhaseChaitin::cache_lrg_info( ) { |
1072 | 1067 |
1073 for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) { | 1068 for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) { |
1074 LRG &lrg = lrgs(i); | 1069 LRG &lrg = lrgs(i); |
1098 _hi_degree = i; | 1093 _hi_degree = i; |
1099 } | 1094 } |
1100 } | 1095 } |
1101 } | 1096 } |
1102 | 1097 |
1103 //------------------------------Pre-Simplify----------------------------------- | |
1104 // Simplify the IFG by removing LRGs of low degree that have NO copies | 1098 // Simplify the IFG by removing LRGs of low degree that have NO copies |
1105 void PhaseChaitin::Pre_Simplify( ) { | 1099 void PhaseChaitin::Pre_Simplify( ) { |
1106 | 1100 |
1107 // Warm up the lo-degree no-copy list | 1101 // Warm up the lo-degree no-copy list |
1108 int lo_no_copy = 0; | 1102 int lo_no_copy = 0; |
1149 } // End of while lo-degree no_copy worklist not empty | 1143 } // End of while lo-degree no_copy worklist not empty |
1150 | 1144 |
1151 // No more lo-degree no-copy live ranges to simplify | 1145 // No more lo-degree no-copy live ranges to simplify |
1152 } | 1146 } |
1153 | 1147 |
1154 //------------------------------Simplify--------------------------------------- | |
1155 // Simplify the IFG by removing LRGs of low degree. | 1148 // Simplify the IFG by removing LRGs of low degree. |
1156 void PhaseChaitin::Simplify( ) { | 1149 void PhaseChaitin::Simplify( ) { |
1157 | 1150 |
1158 while( 1 ) { // Repeat till simplified it all | 1151 while( 1 ) { // Repeat till simplified it all |
1159 // May want to explore simplifying lo_degree before _lo_stk_degree. | 1152 // May want to explore simplifying lo_degree before _lo_stk_degree. |
1286 | 1279 |
1287 } // End of while not simplified everything | 1280 } // End of while not simplified everything |
1288 | 1281 |
1289 } | 1282 } |
1290 | 1283 |
1291 //------------------------------is_legal_reg----------------------------------- | |
1292 // Is 'reg' register legal for 'lrg'? | 1284 // Is 'reg' register legal for 'lrg'? |
1293 static bool is_legal_reg(LRG &lrg, OptoReg::Name reg, int chunk) { | 1285 static bool is_legal_reg(LRG &lrg, OptoReg::Name reg, int chunk) { |
1294 if (reg >= chunk && reg < (chunk + RegMask::CHUNK_SIZE) && | 1286 if (reg >= chunk && reg < (chunk + RegMask::CHUNK_SIZE) && |
1295 lrg.mask().Member(OptoReg::add(reg,-chunk))) { | 1287 lrg.mask().Member(OptoReg::add(reg,-chunk))) { |
1296 // RA uses OptoReg which represent the highest element of a registers set. | 1288 // RA uses OptoReg which represent the highest element of a registers set. |
1313 return true; | 1305 return true; |
1314 } | 1306 } |
1315 return false; | 1307 return false; |
1316 } | 1308 } |
1317 | 1309 |
1318 //------------------------------bias_color------------------------------------- | |
1319 // Choose a color using the biasing heuristic | 1310 // Choose a color using the biasing heuristic |
1320 OptoReg::Name PhaseChaitin::bias_color( LRG &lrg, int chunk ) { | 1311 OptoReg::Name PhaseChaitin::bias_color( LRG &lrg, int chunk ) { |
1321 | 1312 |
1322 // Check for "at_risk" LRG's | 1313 // Check for "at_risk" LRG's |
1323 uint risk_lrg = _lrg_map.find(lrg._risk_bias); | 1314 uint risk_lrg = _lrg_map.find(lrg._risk_bias); |
1375 reg = reg2; | 1366 reg = reg2; |
1376 } | 1367 } |
1377 return OptoReg::add( reg, chunk ); | 1368 return OptoReg::add( reg, chunk ); |
1378 } | 1369 } |
1379 | 1370 |
1380 //------------------------------choose_color----------------------------------- | |
1381 // Choose a color in the current chunk | 1371 // Choose a color in the current chunk |
1382 OptoReg::Name PhaseChaitin::choose_color( LRG &lrg, int chunk ) { | 1372 OptoReg::Name PhaseChaitin::choose_color( LRG &lrg, int chunk ) { |
1383 assert( C->in_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP-1)), "must not allocate stack0 (inside preserve area)"); | 1373 assert( C->in_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP-1)), "must not allocate stack0 (inside preserve area)"); |
1384 assert(C->out_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP+0)), "must not allocate stack0 (inside preserve area)"); | 1374 assert(C->out_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP+0)), "must not allocate stack0 (inside preserve area)"); |
1385 | 1375 |
1397 assert( !chunk, "always color in 1st chunk" ); | 1387 assert( !chunk, "always color in 1st chunk" ); |
1398 // Return the highest element in the set. | 1388 // Return the highest element in the set. |
1399 return lrg.mask().find_last_elem(); | 1389 return lrg.mask().find_last_elem(); |
1400 } | 1390 } |
1401 | 1391 |
1402 //------------------------------Select----------------------------------------- | |
1403 // Select colors by re-inserting LRGs back into the IFG. LRGs are re-inserted | 1392 // Select colors by re-inserting LRGs back into the IFG. LRGs are re-inserted |
1404 // in reverse order of removal. As long as nothing of hi-degree was yanked, | 1393 // in reverse order of removal. As long as nothing of hi-degree was yanked, |
1405 // everything going back is guaranteed a color. Select that color. If some | 1394 // everything going back is guaranteed a color. Select that color. If some |
1406 // hi-degree LRG cannot get a color then we record that we must spill. | 1395 // hi-degree LRG cannot get a color then we record that we must spill. |
1407 uint PhaseChaitin::Select( ) { | 1396 uint PhaseChaitin::Select( ) { |
1572 } | 1561 } |
1573 | 1562 |
1574 return spill_reg-LRG::SPILL_REG; // Return number of spills | 1563 return spill_reg-LRG::SPILL_REG; // Return number of spills |
1575 } | 1564 } |
1576 | 1565 |
1577 | |
1578 //------------------------------copy_was_spilled------------------------------- | |
1579 // Copy 'was_spilled'-edness from the source Node to the dst Node. | 1566 // Copy 'was_spilled'-edness from the source Node to the dst Node. |
1580 void PhaseChaitin::copy_was_spilled( Node *src, Node *dst ) { | 1567 void PhaseChaitin::copy_was_spilled( Node *src, Node *dst ) { |
1581 if( _spilled_once.test(src->_idx) ) { | 1568 if( _spilled_once.test(src->_idx) ) { |
1582 _spilled_once.set(dst->_idx); | 1569 _spilled_once.set(dst->_idx); |
1583 lrgs(_lrg_map.find(dst))._was_spilled1 = 1; | 1570 lrgs(_lrg_map.find(dst))._was_spilled1 = 1; |
1586 lrgs(_lrg_map.find(dst))._was_spilled2 = 1; | 1573 lrgs(_lrg_map.find(dst))._was_spilled2 = 1; |
1587 } | 1574 } |
1588 } | 1575 } |
1589 } | 1576 } |
1590 | 1577 |
1591 //------------------------------set_was_spilled-------------------------------- | |
1592 // Set the 'spilled_once' or 'spilled_twice' flag on a node. | 1578 // Set the 'spilled_once' or 'spilled_twice' flag on a node. |
1593 void PhaseChaitin::set_was_spilled( Node *n ) { | 1579 void PhaseChaitin::set_was_spilled( Node *n ) { |
1594 if( _spilled_once.test_set(n->_idx) ) | 1580 if( _spilled_once.test_set(n->_idx) ) |
1595 _spilled_twice.set(n->_idx); | 1581 _spilled_twice.set(n->_idx); |
1596 } | 1582 } |
1597 | 1583 |
1598 //------------------------------fixup_spills----------------------------------- | |
1599 // Convert Ideal spill instructions into proper FramePtr + offset Loads and | 1584 // Convert Ideal spill instructions into proper FramePtr + offset Loads and |
1600 // Stores. Use-def chains are NOT preserved, but Node->LRG->reg maps are. | 1585 // Stores. Use-def chains are NOT preserved, but Node->LRG->reg maps are. |
1601 void PhaseChaitin::fixup_spills() { | 1586 void PhaseChaitin::fixup_spills() { |
1602 // This function does only cisc spill work. | 1587 // This function does only cisc spill work. |
1603 if( !UseCISCSpill ) return; | 1588 if( !UseCISCSpill ) return; |
1604 | 1589 |
1605 NOT_PRODUCT( Compile::TracePhase t3("fixupSpills", &_t_fixupSpills, TimeCompiler); ) | 1590 NOT_PRODUCT( Compile::TracePhase t3("fixupSpills", &_t_fixupSpills, TimeCompiler); ) |
1606 | 1591 |
1607 // Grab the Frame Pointer | 1592 // Grab the Frame Pointer |
1608 Node *fp = _cfg._broot->head()->in(1)->in(TypeFunc::FramePtr); | 1593 Node *fp = _cfg.get_root_block()->head()->in(1)->in(TypeFunc::FramePtr); |
1609 | 1594 |
1610 // For all blocks | 1595 // For all blocks |
1611 for( uint i = 0; i < _cfg._num_blocks; i++ ) { | 1596 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
1612 Block *b = _cfg._blocks[i]; | 1597 Block* block = _cfg.get_block(i); |
1613 | 1598 |
1614 // For all instructions in block | 1599 // For all instructions in block |
1615 uint last_inst = b->end_idx(); | 1600 uint last_inst = block->end_idx(); |
1616 for( uint j = 1; j <= last_inst; j++ ) { | 1601 for (uint j = 1; j <= last_inst; j++) { |
1617 Node *n = b->_nodes[j]; | 1602 Node* n = block->_nodes[j]; |
1618 | 1603 |
1619 // Dead instruction??? | 1604 // Dead instruction??? |
1620 assert( n->outcnt() != 0 ||// Nothing dead after post alloc | 1605 assert( n->outcnt() != 0 ||// Nothing dead after post alloc |
1621 C->top() == n || // Or the random TOP node | 1606 C->top() == n || // Or the random TOP node |
1622 n->is_Proj(), // Or a fat-proj kill node | 1607 n->is_Proj(), // Or a fat-proj kill node |
1649 cisc->set_req(inp,fp); // Base register is frame pointer | 1634 cisc->set_req(inp,fp); // Base register is frame pointer |
1650 if( cisc->oper_input_base() > 1 && mach->oper_input_base() <= 1 ) { | 1635 if( cisc->oper_input_base() > 1 && mach->oper_input_base() <= 1 ) { |
1651 assert( cisc->oper_input_base() == 2, "Only adding one edge"); | 1636 assert( cisc->oper_input_base() == 2, "Only adding one edge"); |
1652 cisc->ins_req(1,src); // Requires a memory edge | 1637 cisc->ins_req(1,src); // Requires a memory edge |
1653 } | 1638 } |
1654 b->_nodes.map(j,cisc); // Insert into basic block | 1639 block->_nodes.map(j,cisc); // Insert into basic block |
1655 n->subsume_by(cisc, C); // Correct graph | 1640 n->subsume_by(cisc, C); // Correct graph |
1656 // | 1641 // |
1657 ++_used_cisc_instructions; | 1642 ++_used_cisc_instructions; |
1658 #ifndef PRODUCT | 1643 #ifndef PRODUCT |
1659 if( TraceCISCSpill ) { | 1644 if( TraceCISCSpill ) { |
1675 } // End of for all instructions | 1660 } // End of for all instructions |
1676 | 1661 |
1677 } // End of for all blocks | 1662 } // End of for all blocks |
1678 } | 1663 } |
1679 | 1664 |
1680 //------------------------------find_base_for_derived-------------------------- | |
1681 // Helper to stretch above; recursively discover the base Node for a | 1665 // Helper to stretch above; recursively discover the base Node for a |
1682 // given derived Node. Easy for AddP-related machine nodes, but needs | 1666 // given derived Node. Easy for AddP-related machine nodes, but needs |
1683 // to be recursive for derived Phis. | 1667 // to be recursive for derived Phis. |
1684 Node *PhaseChaitin::find_base_for_derived( Node **derived_base_map, Node *derived, uint &maxlrg ) { | 1668 Node *PhaseChaitin::find_base_for_derived( Node **derived_base_map, Node *derived, uint &maxlrg ) { |
1685 // See if already computed; if so return it | 1669 // See if already computed; if so return it |
1705 assert(base != NULL, "sanity"); | 1689 assert(base != NULL, "sanity"); |
1706 if (base->in(0) == NULL) { | 1690 if (base->in(0) == NULL) { |
1707 // Initialize it once and make it shared: | 1691 // Initialize it once and make it shared: |
1708 // set control to _root and place it into Start block | 1692 // set control to _root and place it into Start block |
1709 // (where top() node is placed). | 1693 // (where top() node is placed). |
1710 base->init_req(0, _cfg._root); | 1694 base->init_req(0, _cfg.get_root_node()); |
1711 Block *startb = _cfg.get_block_for_node(C->top()); | 1695 Block *startb = _cfg.get_block_for_node(C->top()); |
1712 startb->_nodes.insert(startb->find_node(C->top()), base ); | 1696 startb->_nodes.insert(startb->find_node(C->top()), base ); |
1713 _cfg.map_node_to_block(base, startb); | 1697 _cfg.map_node_to_block(base, startb); |
1714 assert(_lrg_map.live_range_id(base) == 0, "should not have LRG yet"); | 1698 assert(_lrg_map.live_range_id(base) == 0, "should not have LRG yet"); |
1715 } | 1699 } |
1716 if (_lrg_map.live_range_id(base) == 0) { | 1700 if (_lrg_map.live_range_id(base) == 0) { |
1717 new_lrg(base, maxlrg++); | 1701 new_lrg(base, maxlrg++); |
1718 } | 1702 } |
1719 assert(base->in(0) == _cfg._root && _cfg.get_block_for_node(base) == _cfg.get_block_for_node(C->top()), "base NULL should be shared"); | 1703 assert(base->in(0) == _cfg.get_root_node() && _cfg.get_block_for_node(base) == _cfg.get_block_for_node(C->top()), "base NULL should be shared"); |
1720 derived_base_map[derived->_idx] = base; | 1704 derived_base_map[derived->_idx] = base; |
1721 return base; | 1705 return base; |
1722 } | 1706 } |
1723 | 1707 |
1724 // Check for AddP-related opcodes | 1708 // Check for AddP-related opcodes |
1777 // Cache info for later passes | 1761 // Cache info for later passes |
1778 derived_base_map[derived->_idx] = base; | 1762 derived_base_map[derived->_idx] = base; |
1779 return base; | 1763 return base; |
1780 } | 1764 } |
1781 | 1765 |
1782 | |
1783 //------------------------------stretch_base_pointer_live_ranges--------------- | |
1784 // At each Safepoint, insert extra debug edges for each pair of derived value/ | 1766 // At each Safepoint, insert extra debug edges for each pair of derived value/ |
1785 // base pointer that is live across the Safepoint for oopmap building. The | 1767 // base pointer that is live across the Safepoint for oopmap building. The |
1786 // edge pairs get added in after sfpt->jvmtail()->oopoff(), but are in the | 1768 // edge pairs get added in after sfpt->jvmtail()->oopoff(), but are in the |
1787 // required edge set. | 1769 // required edge set. |
1788 bool PhaseChaitin::stretch_base_pointer_live_ranges(ResourceArea *a) { | 1770 bool PhaseChaitin::stretch_base_pointer_live_ranges(ResourceArea *a) { |
1790 uint maxlrg = _lrg_map.max_lrg_id(); | 1772 uint maxlrg = _lrg_map.max_lrg_id(); |
1791 Node **derived_base_map = (Node**)a->Amalloc(sizeof(Node*)*C->unique()); | 1773 Node **derived_base_map = (Node**)a->Amalloc(sizeof(Node*)*C->unique()); |
1792 memset( derived_base_map, 0, sizeof(Node*)*C->unique() ); | 1774 memset( derived_base_map, 0, sizeof(Node*)*C->unique() ); |
1793 | 1775 |
1794 // For all blocks in RPO do... | 1776 // For all blocks in RPO do... |
1795 for( uint i=0; i<_cfg._num_blocks; i++ ) { | 1777 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
1796 Block *b = _cfg._blocks[i]; | 1778 Block* block = _cfg.get_block(i); |
1797 // Note use of deep-copy constructor. I cannot hammer the original | 1779 // Note use of deep-copy constructor. I cannot hammer the original |
1798 // liveout bits, because they are needed by the following coalesce pass. | 1780 // liveout bits, because they are needed by the following coalesce pass. |
1799 IndexSet liveout(_live->live(b)); | 1781 IndexSet liveout(_live->live(block)); |
1800 | 1782 |
1801 for( uint j = b->end_idx() + 1; j > 1; j-- ) { | 1783 for (uint j = block->end_idx() + 1; j > 1; j--) { |
1802 Node *n = b->_nodes[j-1]; | 1784 Node* n = block->_nodes[j - 1]; |
1803 | 1785 |
1804 // Pre-split compares of loop-phis. Loop-phis form a cycle we would | 1786 // Pre-split compares of loop-phis. Loop-phis form a cycle we would |
1805 // like to see in the same register. Compare uses the loop-phi and so | 1787 // like to see in the same register. Compare uses the loop-phi and so |
1806 // extends its live range BUT cannot be part of the cycle. If this | 1788 // extends its live range BUT cannot be part of the cycle. If this |
1807 // extended live range overlaps with the update of the loop-phi value | 1789 // extended live range overlaps with the update of the loop-phi value |
1812 // phi. | 1794 // phi. |
1813 if( n->is_Mach() && n->as_Mach()->ideal_Opcode() == Op_CmpI ) { | 1795 if( n->is_Mach() && n->as_Mach()->ideal_Opcode() == Op_CmpI ) { |
1814 Node *phi = n->in(1); | 1796 Node *phi = n->in(1); |
1815 if( phi->is_Phi() && phi->as_Phi()->region()->is_Loop() ) { | 1797 if( phi->is_Phi() && phi->as_Phi()->region()->is_Loop() ) { |
1816 Block *phi_block = _cfg.get_block_for_node(phi); | 1798 Block *phi_block = _cfg.get_block_for_node(phi); |
1817 if (_cfg.get_block_for_node(phi_block->pred(2)) == b) { | 1799 if (_cfg.get_block_for_node(phi_block->pred(2)) == block) { |
1818 const RegMask *mask = C->matcher()->idealreg2spillmask[Op_RegI]; | 1800 const RegMask *mask = C->matcher()->idealreg2spillmask[Op_RegI]; |
1819 Node *spill = new (C) MachSpillCopyNode( phi, *mask, *mask ); | 1801 Node *spill = new (C) MachSpillCopyNode( phi, *mask, *mask ); |
1820 insert_proj( phi_block, 1, spill, maxlrg++ ); | 1802 insert_proj( phi_block, 1, spill, maxlrg++ ); |
1821 n->set_req(1,spill); | 1803 n->set_req(1,spill); |
1822 must_recompute_live = true; | 1804 must_recompute_live = true; |
1866 // reaching def's. So if I find the base's live range then | 1848 // reaching def's. So if I find the base's live range then |
1867 // I know the base's def reaches here. | 1849 // I know the base's def reaches here. |
1868 if ((_lrg_map.live_range_id(base) >= _lrg_map.max_lrg_id() || // (Brand new base (hence not live) or | 1850 if ((_lrg_map.live_range_id(base) >= _lrg_map.max_lrg_id() || // (Brand new base (hence not live) or |
1869 !liveout.member(_lrg_map.live_range_id(base))) && // not live) AND | 1851 !liveout.member(_lrg_map.live_range_id(base))) && // not live) AND |
1870 (_lrg_map.live_range_id(base) > 0) && // not a constant | 1852 (_lrg_map.live_range_id(base) > 0) && // not a constant |
1871 _cfg.get_block_for_node(base) != b) { // base not def'd in blk) | 1853 _cfg.get_block_for_node(base) != block) { // base not def'd in blk) |
1872 // Base pointer is not currently live. Since I stretched | 1854 // Base pointer is not currently live. Since I stretched |
1873 // the base pointer to here and it crosses basic-block | 1855 // the base pointer to here and it crosses basic-block |
1874 // boundaries, the global live info is now incorrect. | 1856 // boundaries, the global live info is now incorrect. |
1875 // Recompute live. | 1857 // Recompute live. |
1876 must_recompute_live = true; | 1858 must_recompute_live = true; |
1901 } | 1883 } |
1902 | 1884 |
1903 return must_recompute_live != 0; | 1885 return must_recompute_live != 0; |
1904 } | 1886 } |
1905 | 1887 |
1906 | |
1907 //------------------------------add_reference---------------------------------- | |
1908 // Extend the node to LRG mapping | 1888 // Extend the node to LRG mapping |
1909 | 1889 |
1910 void PhaseChaitin::add_reference(const Node *node, const Node *old_node) { | 1890 void PhaseChaitin::add_reference(const Node *node, const Node *old_node) { |
1911 _lrg_map.extend(node->_idx, _lrg_map.live_range_id(old_node)); | 1891 _lrg_map.extend(node->_idx, _lrg_map.live_range_id(old_node)); |
1912 } | 1892 } |
1913 | 1893 |
1914 //------------------------------dump------------------------------------------- | |
1915 #ifndef PRODUCT | 1894 #ifndef PRODUCT |
1916 void PhaseChaitin::dump(const Node *n) const { | 1895 void PhaseChaitin::dump(const Node *n) const { |
1917 uint r = (n->_idx < _lrg_map.size()) ? _lrg_map.find_const(n) : 0; | 1896 uint r = (n->_idx < _lrg_map.size()) ? _lrg_map.find_const(n) : 0; |
1918 tty->print("L%d",r); | 1897 tty->print("L%d",r); |
1919 if (r && n->Opcode() != Op_Phi) { | 1898 if (r && n->Opcode() != Op_Phi) { |
2015 void PhaseChaitin::dump() const { | 1994 void PhaseChaitin::dump() const { |
2016 tty->print( "--- Chaitin -- argsize: %d framesize: %d ---\n", | 1995 tty->print( "--- Chaitin -- argsize: %d framesize: %d ---\n", |
2017 _matcher._new_SP, _framesize ); | 1996 _matcher._new_SP, _framesize ); |
2018 | 1997 |
2019 // For all blocks | 1998 // For all blocks |
2020 for( uint i = 0; i < _cfg._num_blocks; i++ ) | 1999 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
2021 dump(_cfg._blocks[i]); | 2000 dump(_cfg.get_block(i)); |
2001 } | |
2022 // End of per-block dump | 2002 // End of per-block dump |
2023 tty->print("\n"); | 2003 tty->print("\n"); |
2024 | 2004 |
2025 if (!_ifg) { | 2005 if (!_ifg) { |
2026 tty->print("(No IFG.)\n"); | 2006 tty->print("(No IFG.)\n"); |
2057 for(uint i5 = _hi_degree; i5; i5 = lrgs(i5)._next ) | 2037 for(uint i5 = _hi_degree; i5; i5 = lrgs(i5)._next ) |
2058 tty->print("L%d ",i5); | 2038 tty->print("L%d ",i5); |
2059 tty->print_cr(""); | 2039 tty->print_cr(""); |
2060 } | 2040 } |
2061 | 2041 |
2062 //------------------------------dump_degree_lists------------------------------ | |
2063 void PhaseChaitin::dump_degree_lists() const { | 2042 void PhaseChaitin::dump_degree_lists() const { |
2064 // Dump lo-degree list | 2043 // Dump lo-degree list |
2065 tty->print("Lo degree: "); | 2044 tty->print("Lo degree: "); |
2066 for( uint i = _lo_degree; i; i = lrgs(i)._next ) | 2045 for( uint i = _lo_degree; i; i = lrgs(i)._next ) |
2067 tty->print("L%d ",i); | 2046 tty->print("L%d ",i); |
2078 for(uint i3 = _hi_degree; i3; i3 = lrgs(i3)._next ) | 2057 for(uint i3 = _hi_degree; i3; i3 = lrgs(i3)._next ) |
2079 tty->print("L%d ",i3); | 2058 tty->print("L%d ",i3); |
2080 tty->print_cr(""); | 2059 tty->print_cr(""); |
2081 } | 2060 } |
2082 | 2061 |
2083 //------------------------------dump_simplified-------------------------------- | |
2084 void PhaseChaitin::dump_simplified() const { | 2062 void PhaseChaitin::dump_simplified() const { |
2085 tty->print("Simplified: "); | 2063 tty->print("Simplified: "); |
2086 for( uint i = _simplified; i; i = lrgs(i)._next ) | 2064 for( uint i = _simplified; i; i = lrgs(i)._next ) |
2087 tty->print("L%d ",i); | 2065 tty->print("L%d ",i); |
2088 tty->print_cr(""); | 2066 tty->print_cr(""); |
2097 sprintf(buf,"%s + #%d",OptoReg::regname(OptoReg::c_frame_pointer), | 2075 sprintf(buf,"%s + #%d",OptoReg::regname(OptoReg::c_frame_pointer), |
2098 pc->reg2offset(reg)); | 2076 pc->reg2offset(reg)); |
2099 return buf+strlen(buf); | 2077 return buf+strlen(buf); |
2100 } | 2078 } |
2101 | 2079 |
2102 //------------------------------dump_register---------------------------------- | |
2103 // Dump a register name into a buffer. Be intelligent if we get called | 2080 // Dump a register name into a buffer. Be intelligent if we get called |
2104 // before allocation is complete. | 2081 // before allocation is complete. |
2105 char *PhaseChaitin::dump_register( const Node *n, char *buf ) const { | 2082 char *PhaseChaitin::dump_register( const Node *n, char *buf ) const { |
2106 if( !this ) { // Not got anything? | 2083 if( !this ) { // Not got anything? |
2107 sprintf(buf,"N%d",n->_idx); // Then use Node index | 2084 sprintf(buf,"N%d",n->_idx); // Then use Node index |
2131 } | 2108 } |
2132 } | 2109 } |
2133 return buf+strlen(buf); | 2110 return buf+strlen(buf); |
2134 } | 2111 } |
2135 | 2112 |
2136 //----------------------dump_for_spill_split_recycle-------------------------- | |
2137 void PhaseChaitin::dump_for_spill_split_recycle() const { | 2113 void PhaseChaitin::dump_for_spill_split_recycle() const { |
2138 if( WizardMode && (PrintCompilation || PrintOpto) ) { | 2114 if( WizardMode && (PrintCompilation || PrintOpto) ) { |
2139 // Display which live ranges need to be split and the allocator's state | 2115 // Display which live ranges need to be split and the allocator's state |
2140 tty->print_cr("Graph-Coloring Iteration %d will split the following live ranges", _trip_cnt); | 2116 tty->print_cr("Graph-Coloring Iteration %d will split the following live ranges", _trip_cnt); |
2141 for (uint bidx = 1; bidx < _lrg_map.max_lrg_id(); bidx++) { | 2117 for (uint bidx = 1; bidx < _lrg_map.max_lrg_id(); bidx++) { |
2147 tty->cr(); | 2123 tty->cr(); |
2148 dump(); | 2124 dump(); |
2149 } | 2125 } |
2150 } | 2126 } |
2151 | 2127 |
2152 //------------------------------dump_frame------------------------------------ | |
2153 void PhaseChaitin::dump_frame() const { | 2128 void PhaseChaitin::dump_frame() const { |
2154 const char *fp = OptoReg::regname(OptoReg::c_frame_pointer); | 2129 const char *fp = OptoReg::regname(OptoReg::c_frame_pointer); |
2155 const TypeTuple *domain = C->tf()->domain(); | 2130 const TypeTuple *domain = C->tf()->domain(); |
2156 const int argcnt = domain->cnt() - TypeFunc::Parms; | 2131 const int argcnt = domain->cnt() - TypeFunc::Parms; |
2157 | 2132 |
2253 tty->print_cr("#r%3.3d %s+%2d: new out preserve",reg,fp,reg2offset_unchecked(reg)); | 2228 tty->print_cr("#r%3.3d %s+%2d: new out preserve",reg,fp,reg2offset_unchecked(reg)); |
2254 } | 2229 } |
2255 tty->print_cr("#"); | 2230 tty->print_cr("#"); |
2256 } | 2231 } |
2257 | 2232 |
2258 //------------------------------dump_bb---------------------------------------- | |
2259 void PhaseChaitin::dump_bb( uint pre_order ) const { | 2233 void PhaseChaitin::dump_bb( uint pre_order ) const { |
2260 tty->print_cr("---dump of B%d---",pre_order); | 2234 tty->print_cr("---dump of B%d---",pre_order); |
2261 for( uint i = 0; i < _cfg._num_blocks; i++ ) { | 2235 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
2262 Block *b = _cfg._blocks[i]; | 2236 Block* block = _cfg.get_block(i); |
2263 if( b->_pre_order == pre_order ) | 2237 if (block->_pre_order == pre_order) { |
2264 dump(b); | 2238 dump(block); |
2265 } | 2239 } |
2266 } | 2240 } |
2267 | 2241 } |
2268 //------------------------------dump_lrg--------------------------------------- | 2242 |
2269 void PhaseChaitin::dump_lrg( uint lidx, bool defs_only ) const { | 2243 void PhaseChaitin::dump_lrg( uint lidx, bool defs_only ) const { |
2270 tty->print_cr("---dump of L%d---",lidx); | 2244 tty->print_cr("---dump of L%d---",lidx); |
2271 | 2245 |
2272 if (_ifg) { | 2246 if (_ifg) { |
2273 if (lidx >= _lrg_map.max_lrg_id()) { | 2247 if (lidx >= _lrg_map.max_lrg_id()) { |
2285 tty->print("Neighbors: %d - ", _ifg->neighbor_cnt(lidx)); | 2259 tty->print("Neighbors: %d - ", _ifg->neighbor_cnt(lidx)); |
2286 _ifg->neighbors(lidx)->dump(); | 2260 _ifg->neighbors(lidx)->dump(); |
2287 tty->cr(); | 2261 tty->cr(); |
2288 } | 2262 } |
2289 // For all blocks | 2263 // For all blocks |
2290 for( uint i = 0; i < _cfg._num_blocks; i++ ) { | 2264 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
2291 Block *b = _cfg._blocks[i]; | 2265 Block* block = _cfg.get_block(i); |
2292 int dump_once = 0; | 2266 int dump_once = 0; |
2293 | 2267 |
2294 // For all instructions | 2268 // For all instructions |
2295 for( uint j = 0; j < b->_nodes.size(); j++ ) { | 2269 for( uint j = 0; j < block->_nodes.size(); j++ ) { |
2296 Node *n = b->_nodes[j]; | 2270 Node *n = block->_nodes[j]; |
2297 if (_lrg_map.find_const(n) == lidx) { | 2271 if (_lrg_map.find_const(n) == lidx) { |
2298 if (!dump_once++) { | 2272 if (!dump_once++) { |
2299 tty->cr(); | 2273 tty->cr(); |
2300 b->dump_head(&_cfg); | 2274 block->dump_head(&_cfg); |
2301 } | 2275 } |
2302 dump(n); | 2276 dump(n); |
2303 continue; | 2277 continue; |
2304 } | 2278 } |
2305 if (!defs_only) { | 2279 if (!defs_only) { |
2310 continue; // be robust in the dumper | 2284 continue; // be robust in the dumper |
2311 } | 2285 } |
2312 if (_lrg_map.find_const(m) == lidx) { | 2286 if (_lrg_map.find_const(m) == lidx) { |
2313 if (!dump_once++) { | 2287 if (!dump_once++) { |
2314 tty->cr(); | 2288 tty->cr(); |
2315 b->dump_head(&_cfg); | 2289 block->dump_head(&_cfg); |
2316 } | 2290 } |
2317 dump(n); | 2291 dump(n); |
2318 } | 2292 } |
2319 } | 2293 } |
2320 } | 2294 } |
2322 } // End of per-block dump | 2296 } // End of per-block dump |
2323 tty->cr(); | 2297 tty->cr(); |
2324 } | 2298 } |
2325 #endif // not PRODUCT | 2299 #endif // not PRODUCT |
2326 | 2300 |
2327 //------------------------------print_chaitin_statistics------------------------------- | |
2328 int PhaseChaitin::_final_loads = 0; | 2301 int PhaseChaitin::_final_loads = 0; |
2329 int PhaseChaitin::_final_stores = 0; | 2302 int PhaseChaitin::_final_stores = 0; |
2330 int PhaseChaitin::_final_memoves= 0; | 2303 int PhaseChaitin::_final_memoves= 0; |
2331 int PhaseChaitin::_final_copies = 0; | 2304 int PhaseChaitin::_final_copies = 0; |
2332 double PhaseChaitin::_final_load_cost = 0; | 2305 double PhaseChaitin::_final_load_cost = 0; |