Mercurial > hg > graal-compiler
annotate src/share/vm/opto/chaitin.cpp @ 12071:adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
Summary: public methods that don't need to be public should be private.
Reviewed-by: kvn, twisti
| author | adlertz |
|---|---|
| date | Fri, 16 Aug 2013 10:23:55 +0200 |
| parents | d1034bd8cefc |
| children | 4b2838704fd5 |
| rev | line source |
|---|---|
| 0 | 1 /* |
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2 * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #include "precompiled.hpp" |
| 26 #include "compiler/compileLog.hpp" | |
| 27 #include "compiler/oopMap.hpp" | |
| 28 #include "memory/allocation.inline.hpp" | |
| 29 #include "opto/addnode.hpp" | |
| 30 #include "opto/block.hpp" | |
| 31 #include "opto/callnode.hpp" | |
| 32 #include "opto/cfgnode.hpp" | |
| 33 #include "opto/chaitin.hpp" | |
| 34 #include "opto/coalesce.hpp" | |
| 35 #include "opto/connode.hpp" | |
| 36 #include "opto/idealGraphPrinter.hpp" | |
| 37 #include "opto/indexSet.hpp" | |
| 38 #include "opto/machnode.hpp" | |
| 39 #include "opto/memnode.hpp" | |
| 40 #include "opto/opcodes.hpp" | |
| 41 #include "opto/rootnode.hpp" | |
| 0 | 42 |
| 43 #ifndef PRODUCT | |
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44 void LRG::dump() const { |
| 0 | 45 ttyLocker ttyl; |
| 46 tty->print("%d ",num_regs()); | |
| 47 _mask.dump(); | |
| 48 if( _msize_valid ) { | |
| 49 if( mask_size() == compute_mask_size() ) tty->print(", #%d ",_mask_size); | |
| 50 else tty->print(", #!!!_%d_vs_%d ",_mask_size,_mask.Size()); | |
| 51 } else { | |
| 52 tty->print(", #?(%d) ",_mask.Size()); | |
| 53 } | |
| 54 | |
| 55 tty->print("EffDeg: "); | |
| 56 if( _degree_valid ) tty->print( "%d ", _eff_degree ); | |
| 57 else tty->print("? "); | |
| 58 | |
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59 if( is_multidef() ) { |
| 0 | 60 tty->print("MultiDef "); |
| 61 if (_defs != NULL) { | |
| 62 tty->print("("); | |
| 63 for (int i = 0; i < _defs->length(); i++) { | |
| 64 tty->print("N%d ", _defs->at(i)->_idx); | |
| 65 } | |
| 66 tty->print(") "); | |
| 67 } | |
| 68 } | |
| 69 else if( _def == 0 ) tty->print("Dead "); | |
| 70 else tty->print("Def: N%d ",_def->_idx); | |
| 71 | |
| 72 tty->print("Cost:%4.2g Area:%4.2g Score:%4.2g ",_cost,_area, score()); | |
| 73 // Flags | |
| 74 if( _is_oop ) tty->print("Oop "); | |
| 75 if( _is_float ) tty->print("Float "); | |
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76 if( _is_vector ) tty->print("Vector "); |
| 0 | 77 if( _was_spilled1 ) tty->print("Spilled "); |
| 78 if( _was_spilled2 ) tty->print("Spilled2 "); | |
| 79 if( _direct_conflict ) tty->print("Direct_conflict "); | |
| 80 if( _fat_proj ) tty->print("Fat "); | |
| 81 if( _was_lo ) tty->print("Lo "); | |
| 82 if( _has_copy ) tty->print("Copy "); | |
| 83 if( _at_risk ) tty->print("Risk "); | |
| 84 | |
| 85 if( _must_spill ) tty->print("Must_spill "); | |
| 86 if( _is_bound ) tty->print("Bound "); | |
| 87 if( _msize_valid ) { | |
| 88 if( _degree_valid && lo_degree() ) tty->print("Trivial "); | |
| 89 } | |
| 90 | |
| 91 tty->cr(); | |
| 92 } | |
| 93 #endif | |
| 94 | |
| 95 // Compute score from cost and area. Low score is best to spill. | |
| 96 static double raw_score( double cost, double area ) { | |
| 97 return cost - (area*RegisterCostAreaRatio) * 1.52588e-5; | |
| 98 } | |
| 99 | |
| 100 double LRG::score() const { | |
| 101 // Scale _area by RegisterCostAreaRatio/64K then subtract from cost. | |
| 102 // Bigger area lowers score, encourages spilling this live range. | |
| 103 // Bigger cost raise score, prevents spilling this live range. | |
| 104 // (Note: 1/65536 is the magic constant below; I dont trust the C optimizer | |
| 105 // to turn a divide by a constant into a multiply by the reciprical). | |
| 106 double score = raw_score( _cost, _area); | |
| 107 | |
| 108 // Account for area. Basically, LRGs covering large areas are better | |
| 109 // to spill because more other LRGs get freed up. | |
| 110 if( _area == 0.0 ) // No area? Then no progress to spill | |
| 111 return 1e35; | |
| 112 | |
| 113 if( _was_spilled2 ) // If spilled once before, we are unlikely | |
| 114 return score + 1e30; // to make progress again. | |
| 115 | |
| 116 if( _cost >= _area*3.0 ) // Tiny area relative to cost | |
| 117 return score + 1e17; // Probably no progress to spill | |
| 118 | |
| 119 if( (_cost+_cost) >= _area*3.0 ) // Small area relative to cost | |
| 120 return score + 1e10; // Likely no progress to spill | |
| 121 | |
| 122 return score; | |
| 123 } | |
| 124 | |
| 125 LRG_List::LRG_List( uint max ) : _cnt(max), _max(max), _lidxs(NEW_RESOURCE_ARRAY(uint,max)) { | |
| 126 memset( _lidxs, 0, sizeof(uint)*max ); | |
| 127 } | |
| 128 | |
| 129 void LRG_List::extend( uint nidx, uint lidx ) { | |
| 130 _nesting.check(); | |
| 131 if( nidx >= _max ) { | |
| 132 uint size = 16; | |
| 133 while( size <= nidx ) size <<=1; | |
| 134 _lidxs = REALLOC_RESOURCE_ARRAY( uint, _lidxs, _max, size ); | |
| 135 _max = size; | |
| 136 } | |
| 137 while( _cnt <= nidx ) | |
| 138 _lidxs[_cnt++] = 0; | |
| 139 _lidxs[nidx] = lidx; | |
| 140 } | |
| 141 | |
| 142 #define NUMBUCKS 3 | |
| 143 | |
| 10111 | 144 // Straight out of Tarjan's union-find algorithm |
| 145 uint LiveRangeMap::find_compress(uint lrg) { | |
| 146 uint cur = lrg; | |
| 147 uint next = _uf_map[cur]; | |
| 148 while (next != cur) { // Scan chain of equivalences | |
| 149 assert( next < cur, "always union smaller"); | |
| 150 cur = next; // until find a fixed-point | |
| 151 next = _uf_map[cur]; | |
| 152 } | |
| 153 | |
| 154 // Core of union-find algorithm: update chain of | |
| 155 // equivalences to be equal to the root. | |
| 156 while (lrg != next) { | |
| 157 uint tmp = _uf_map[lrg]; | |
| 158 _uf_map.map(lrg, next); | |
| 159 lrg = tmp; | |
| 160 } | |
| 161 return lrg; | |
| 162 } | |
| 163 | |
| 164 // Reset the Union-Find map to identity | |
| 165 void LiveRangeMap::reset_uf_map(uint max_lrg_id) { | |
| 166 _max_lrg_id= max_lrg_id; | |
| 167 // Force the Union-Find mapping to be at least this large | |
| 168 _uf_map.extend(_max_lrg_id, 0); | |
| 169 // Initialize it to be the ID mapping. | |
| 170 for (uint i = 0; i < _max_lrg_id; ++i) { | |
| 171 _uf_map.map(i, i); | |
| 172 } | |
| 173 } | |
| 174 | |
| 175 // Make all Nodes map directly to their final live range; no need for | |
| 176 // the Union-Find mapping after this call. | |
| 177 void LiveRangeMap::compress_uf_map_for_nodes() { | |
| 178 // For all Nodes, compress mapping | |
| 179 uint unique = _names.Size(); | |
| 180 for (uint i = 0; i < unique; ++i) { | |
| 181 uint lrg = _names[i]; | |
| 182 uint compressed_lrg = find(lrg); | |
| 183 if (lrg != compressed_lrg) { | |
| 184 _names.map(i, compressed_lrg); | |
| 185 } | |
| 186 } | |
| 187 } | |
| 188 | |
| 189 // Like Find above, but no path compress, so bad asymptotic behavior | |
| 190 uint LiveRangeMap::find_const(uint lrg) const { | |
| 191 if (!lrg) { | |
| 192 return lrg; // Ignore the zero LRG | |
| 193 } | |
| 194 | |
| 195 // Off the end? This happens during debugging dumps when you got | |
| 196 // brand new live ranges but have not told the allocator yet. | |
| 197 if (lrg >= _max_lrg_id) { | |
| 198 return lrg; | |
| 199 } | |
| 200 | |
| 201 uint next = _uf_map[lrg]; | |
| 202 while (next != lrg) { // Scan chain of equivalences | |
| 203 assert(next < lrg, "always union smaller"); | |
| 204 lrg = next; // until find a fixed-point | |
| 205 next = _uf_map[lrg]; | |
| 206 } | |
| 207 return next; | |
| 208 } | |
| 209 | |
| 0 | 210 PhaseChaitin::PhaseChaitin(uint unique, PhaseCFG &cfg, Matcher &matcher) |
| 211 : PhaseRegAlloc(unique, cfg, matcher, | |
| 212 #ifndef PRODUCT | |
| 213 print_chaitin_statistics | |
| 214 #else | |
| 215 NULL | |
| 216 #endif | |
| 10111 | 217 ) |
| 218 , _lrg_map(unique) | |
| 219 , _live(0) | |
| 220 , _spilled_once(Thread::current()->resource_area()) | |
| 221 , _spilled_twice(Thread::current()->resource_area()) | |
| 222 , _lo_degree(0), _lo_stk_degree(0), _hi_degree(0), _simplified(0) | |
| 223 , _oldphi(unique) | |
| 0 | 224 #ifndef PRODUCT |
| 225 , _trace_spilling(TraceSpilling || C->method_has_option("TraceSpilling")) | |
| 226 #endif | |
| 227 { | |
| 228 NOT_PRODUCT( Compile::TracePhase t3("ctorChaitin", &_t_ctorChaitin, TimeCompiler); ) | |
| 673 | 229 |
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230 _high_frequency_lrg = MIN2(float(OPTO_LRG_HIGH_FREQ), _cfg.get_outer_loop_frequency()); |
| 673 | 231 |
| 0 | 232 // Build a list of basic blocks, sorted by frequency |
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233 _blks = NEW_RESOURCE_ARRAY(Block *, _cfg.number_of_blocks()); |
| 0 | 234 // Experiment with sorting strategies to speed compilation |
| 235 double cutoff = BLOCK_FREQUENCY(1.0); // Cutoff for high frequency bucket | |
| 236 Block **buckets[NUMBUCKS]; // Array of buckets | |
| 237 uint buckcnt[NUMBUCKS]; // Array of bucket counters | |
| 238 double buckval[NUMBUCKS]; // Array of bucket value cutoffs | |
| 10111 | 239 for (uint i = 0; i < NUMBUCKS; i++) { |
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240 buckets[i] = NEW_RESOURCE_ARRAY(Block *, _cfg.number_of_blocks()); |
| 0 | 241 buckcnt[i] = 0; |
| 242 // Bump by three orders of magnitude each time | |
| 243 cutoff *= 0.001; | |
| 244 buckval[i] = cutoff; | |
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245 for (uint j = 0; j < _cfg.number_of_blocks(); j++) { |
| 0 | 246 buckets[i][j] = NULL; |
| 247 } | |
| 248 } | |
| 249 // Sort blocks into buckets | |
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250 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
| 10111 | 251 for (uint j = 0; j < NUMBUCKS; j++) { |
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252 if ((j == NUMBUCKS - 1) || (_cfg.get_block(i)->_freq > buckval[j])) { |
| 0 | 253 // Assign block to end of list for appropriate bucket |
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254 buckets[j][buckcnt[j]++] = _cfg.get_block(i); |
| 10111 | 255 break; // kick out of inner loop |
| 0 | 256 } |
| 257 } | |
| 258 } | |
| 259 // Dump buckets into final block array | |
| 260 uint blkcnt = 0; | |
| 10111 | 261 for (uint i = 0; i < NUMBUCKS; i++) { |
| 262 for (uint j = 0; j < buckcnt[i]; j++) { | |
| 0 | 263 _blks[blkcnt++] = buckets[i][j]; |
| 264 } | |
| 265 } | |
| 266 | |
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267 assert(blkcnt == _cfg.number_of_blocks(), "Block array not totally filled"); |
| 0 | 268 } |
| 269 | |
| 10111 | 270 // union 2 sets together. |
| 271 void PhaseChaitin::Union( const Node *src_n, const Node *dst_n ) { | |
| 272 uint src = _lrg_map.find(src_n); | |
| 273 uint dst = _lrg_map.find(dst_n); | |
| 274 assert(src, ""); | |
| 275 assert(dst, ""); | |
| 276 assert(src < _lrg_map.max_lrg_id(), "oob"); | |
| 277 assert(dst < _lrg_map.max_lrg_id(), "oob"); | |
| 278 assert(src < dst, "always union smaller"); | |
| 279 _lrg_map.uf_map(dst, src); | |
| 280 } | |
| 281 | |
| 282 void PhaseChaitin::new_lrg(const Node *x, uint lrg) { | |
| 283 // Make the Node->LRG mapping | |
| 284 _lrg_map.extend(x->_idx,lrg); | |
| 285 // Make the Union-Find mapping an identity function | |
| 286 _lrg_map.uf_extend(lrg, lrg); | |
| 287 } | |
| 288 | |
| 289 | |
| 290 bool PhaseChaitin::clone_projs_shared(Block *b, uint idx, Node *con, Node *copy, uint max_lrg_id) { | |
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291 Block* bcon = _cfg.get_block_for_node(con); |
| 10111 | 292 uint cindex = bcon->find_node(con); |
| 293 Node *con_next = bcon->_nodes[cindex+1]; | |
| 294 if (con_next->in(0) != con || !con_next->is_MachProj()) { | |
| 295 return false; // No MachProj's follow | |
| 296 } | |
| 297 | |
| 298 // Copy kills after the cloned constant | |
| 299 Node *kills = con_next->clone(); | |
| 300 kills->set_req(0, copy); | |
| 301 b->_nodes.insert(idx, kills); | |
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302 _cfg.map_node_to_block(kills, b); |
| 10111 | 303 new_lrg(kills, max_lrg_id); |
| 304 return true; | |
| 305 } | |
| 306 | |
| 307 // Renumber the live ranges to compact them. Makes the IFG smaller. | |
| 308 void PhaseChaitin::compact() { | |
| 309 // Current the _uf_map contains a series of short chains which are headed | |
| 310 // by a self-cycle. All the chains run from big numbers to little numbers. | |
| 311 // The Find() call chases the chains & shortens them for the next Find call. | |
| 312 // We are going to change this structure slightly. Numbers above a moving | |
| 313 // wave 'i' are unchanged. Numbers below 'j' point directly to their | |
| 314 // compacted live range with no further chaining. There are no chains or | |
| 315 // cycles below 'i', so the Find call no longer works. | |
| 316 uint j=1; | |
| 317 uint i; | |
| 318 for (i = 1; i < _lrg_map.max_lrg_id(); i++) { | |
| 319 uint lr = _lrg_map.uf_live_range_id(i); | |
| 320 // Ignore unallocated live ranges | |
| 321 if (!lr) { | |
| 322 continue; | |
| 323 } | |
| 324 assert(lr <= i, ""); | |
| 325 _lrg_map.uf_map(i, ( lr == i ) ? j++ : _lrg_map.uf_live_range_id(lr)); | |
| 326 } | |
| 327 // Now change the Node->LR mapping to reflect the compacted names | |
| 328 uint unique = _lrg_map.size(); | |
| 329 for (i = 0; i < unique; i++) { | |
| 330 uint lrg_id = _lrg_map.live_range_id(i); | |
| 331 _lrg_map.map(i, _lrg_map.uf_live_range_id(lrg_id)); | |
| 332 } | |
| 333 | |
| 334 // Reset the Union-Find mapping | |
| 335 _lrg_map.reset_uf_map(j); | |
| 336 } | |
| 337 | |
| 0 | 338 void PhaseChaitin::Register_Allocate() { |
| 339 | |
| 340 // Above the OLD FP (and in registers) are the incoming arguments. Stack | |
| 341 // slots in this area are called "arg_slots". Above the NEW FP (and in | |
| 342 // registers) is the outgoing argument area; above that is the spill/temp | |
| 343 // area. These are all "frame_slots". Arg_slots start at the zero | |
| 344 // stack_slots and count up to the known arg_size. Frame_slots start at | |
| 345 // the stack_slot #arg_size and go up. After allocation I map stack | |
| 346 // slots to actual offsets. Stack-slots in the arg_slot area are biased | |
| 347 // by the frame_size; stack-slots in the frame_slot area are biased by 0. | |
| 348 | |
| 349 _trip_cnt = 0; | |
| 350 _alternate = 0; | |
| 351 _matcher._allocation_started = true; | |
| 352 | |
| 6632 | 353 ResourceArea split_arena; // Arena for Split local resources |
| 0 | 354 ResourceArea live_arena; // Arena for liveness & IFG info |
| 355 ResourceMark rm(&live_arena); | |
| 356 | |
| 357 // Need live-ness for the IFG; need the IFG for coalescing. If the | |
| 358 // liveness is JUST for coalescing, then I can get some mileage by renaming | |
| 359 // all copy-related live ranges low and then using the max copy-related | |
| 360 // live range as a cut-off for LIVE and the IFG. In other words, I can | |
| 361 // build a subset of LIVE and IFG just for copies. | |
| 10111 | 362 PhaseLive live(_cfg, _lrg_map.names(), &live_arena); |
| 0 | 363 |
| 364 // Need IFG for coalescing and coloring | |
| 10111 | 365 PhaseIFG ifg(&live_arena); |
| 0 | 366 _ifg = &ifg; |
| 367 | |
| 368 // Come out of SSA world to the Named world. Assign (virtual) registers to | |
| 369 // Nodes. Use the same register for all inputs and the output of PhiNodes | |
| 370 // - effectively ending SSA form. This requires either coalescing live | |
| 371 // ranges or inserting copies. For the moment, we insert "virtual copies" | |
| 372 // - we pretend there is a copy prior to each Phi in predecessor blocks. | |
| 373 // We will attempt to coalesce such "virtual copies" before we manifest | |
| 374 // them for real. | |
| 375 de_ssa(); | |
| 376 | |
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377 #ifdef ASSERT |
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378 // Veify the graph before RA. |
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379 verify(&live_arena); |
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380 #endif |
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381 |
| 0 | 382 { |
| 383 NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); ) | |
| 384 _live = NULL; // Mark live as being not available | |
| 385 rm.reset_to_mark(); // Reclaim working storage | |
| 386 IndexSet::reset_memory(C, &live_arena); | |
| 10111 | 387 ifg.init(_lrg_map.max_lrg_id()); // Empty IFG |
| 0 | 388 gather_lrg_masks( false ); // Collect LRG masks |
| 10111 | 389 live.compute(_lrg_map.max_lrg_id()); // Compute liveness |
| 0 | 390 _live = &live; // Mark LIVE as being available |
| 391 } | |
| 392 | |
| 393 // Base pointers are currently "used" by instructions which define new | |
| 394 // derived pointers. This makes base pointers live up to the where the | |
| 395 // derived pointer is made, but not beyond. Really, they need to be live | |
| 396 // across any GC point where the derived value is live. So this code looks | |
| 397 // at all the GC points, and "stretches" the live range of any base pointer | |
| 398 // to the GC point. | |
| 10111 | 399 if (stretch_base_pointer_live_ranges(&live_arena)) { |
| 400 NOT_PRODUCT(Compile::TracePhase t3("computeLive (sbplr)", &_t_computeLive, TimeCompiler);) | |
| 0 | 401 // Since some live range stretched, I need to recompute live |
| 402 _live = NULL; | |
| 403 rm.reset_to_mark(); // Reclaim working storage | |
| 404 IndexSet::reset_memory(C, &live_arena); | |
| 10111 | 405 ifg.init(_lrg_map.max_lrg_id()); |
| 406 gather_lrg_masks(false); | |
| 407 live.compute(_lrg_map.max_lrg_id()); | |
| 0 | 408 _live = &live; |
| 409 } | |
| 410 // Create the interference graph using virtual copies | |
| 10111 | 411 build_ifg_virtual(); // Include stack slots this time |
| 0 | 412 |
| 413 // Aggressive (but pessimistic) copy coalescing. | |
| 414 // This pass works on virtual copies. Any virtual copies which are not | |
| 415 // coalesced get manifested as actual copies | |
| 416 { | |
| 417 // The IFG is/was triangular. I am 'squaring it up' so Union can run | |
| 418 // faster. Union requires a 'for all' operation which is slow on the | |
| 419 // triangular adjacency matrix (quick reminder: the IFG is 'sparse' - | |
| 420 // meaning I can visit all the Nodes neighbors less than a Node in time | |
| 421 // O(# of neighbors), but I have to visit all the Nodes greater than a | |
| 422 // given Node and search them for an instance, i.e., time O(#MaxLRG)). | |
| 423 _ifg->SquareUp(); | |
| 424 | |
| 10111 | 425 PhaseAggressiveCoalesce coalesce(*this); |
| 426 coalesce.coalesce_driver(); | |
| 0 | 427 // Insert un-coalesced copies. Visit all Phis. Where inputs to a Phi do |
| 428 // not match the Phi itself, insert a copy. | |
| 429 coalesce.insert_copies(_matcher); | |
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430 if (C->failing()) { |
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431 return; |
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432 } |
| 0 | 433 } |
| 434 | |
| 435 // After aggressive coalesce, attempt a first cut at coloring. | |
| 436 // To color, we need the IFG and for that we need LIVE. | |
| 437 { | |
| 438 NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); ) | |
| 439 _live = NULL; | |
| 440 rm.reset_to_mark(); // Reclaim working storage | |
| 441 IndexSet::reset_memory(C, &live_arena); | |
| 10111 | 442 ifg.init(_lrg_map.max_lrg_id()); |
| 0 | 443 gather_lrg_masks( true ); |
| 10111 | 444 live.compute(_lrg_map.max_lrg_id()); |
| 0 | 445 _live = &live; |
| 446 } | |
| 447 | |
| 448 // Build physical interference graph | |
| 449 uint must_spill = 0; | |
| 10111 | 450 must_spill = build_ifg_physical(&live_arena); |
| 0 | 451 // If we have a guaranteed spill, might as well spill now |
| 10111 | 452 if (must_spill) { |
| 453 if(!_lrg_map.max_lrg_id()) { | |
| 454 return; | |
| 455 } | |
| 0 | 456 // Bail out if unique gets too large (ie - unique > MaxNodeLimit) |
| 457 C->check_node_count(10*must_spill, "out of nodes before split"); | |
| 10111 | 458 if (C->failing()) { |
| 459 return; | |
| 460 } | |
| 461 | |
| 462 uint new_max_lrg_id = Split(_lrg_map.max_lrg_id(), &split_arena); // Split spilling LRG everywhere | |
| 463 _lrg_map.set_max_lrg_id(new_max_lrg_id); | |
| 0 | 464 // Bail out if unique gets too large (ie - unique > MaxNodeLimit - 2*NodeLimitFudgeFactor) |
| 465 // or we failed to split | |
| 466 C->check_node_count(2*NodeLimitFudgeFactor, "out of nodes after physical split"); | |
| 10111 | 467 if (C->failing()) { |
| 468 return; | |
| 469 } | |
| 0 | 470 |
| 10111 | 471 NOT_PRODUCT(C->verify_graph_edges();) |
| 0 | 472 |
| 473 compact(); // Compact LRGs; return new lower max lrg | |
| 474 | |
| 475 { | |
| 476 NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); ) | |
| 477 _live = NULL; | |
| 478 rm.reset_to_mark(); // Reclaim working storage | |
| 479 IndexSet::reset_memory(C, &live_arena); | |
| 10111 | 480 ifg.init(_lrg_map.max_lrg_id()); // Build a new interference graph |
| 0 | 481 gather_lrg_masks( true ); // Collect intersect mask |
| 10111 | 482 live.compute(_lrg_map.max_lrg_id()); // Compute LIVE |
| 0 | 483 _live = &live; |
| 484 } | |
| 10111 | 485 build_ifg_physical(&live_arena); |
| 0 | 486 _ifg->SquareUp(); |
| 487 _ifg->Compute_Effective_Degree(); | |
| 488 // Only do conservative coalescing if requested | |
| 10111 | 489 if (OptoCoalesce) { |
| 0 | 490 // Conservative (and pessimistic) copy coalescing of those spills |
| 10111 | 491 PhaseConservativeCoalesce coalesce(*this); |
| 0 | 492 // If max live ranges greater than cutoff, don't color the stack. |
| 493 // This cutoff can be larger than below since it is only done once. | |
| 10111 | 494 coalesce.coalesce_driver(); |
| 0 | 495 } |
| 10111 | 496 _lrg_map.compress_uf_map_for_nodes(); |
| 0 | 497 |
| 498 #ifdef ASSERT | |
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499 verify(&live_arena, true); |
| 0 | 500 #endif |
| 501 } else { | |
| 502 ifg.SquareUp(); | |
| 503 ifg.Compute_Effective_Degree(); | |
| 504 #ifdef ASSERT | |
| 505 set_was_low(); | |
| 506 #endif | |
| 507 } | |
| 508 | |
| 509 // Prepare for Simplify & Select | |
| 510 cache_lrg_info(); // Count degree of LRGs | |
| 511 | |
| 512 // Simplify the InterFerence Graph by removing LRGs of low degree. | |
| 513 // LRGs of low degree are trivially colorable. | |
| 514 Simplify(); | |
| 515 | |
| 516 // Select colors by re-inserting LRGs back into the IFG in reverse order. | |
| 517 // Return whether or not something spills. | |
| 518 uint spills = Select( ); | |
| 519 | |
| 520 // If we spill, split and recycle the entire thing | |
| 521 while( spills ) { | |
| 522 if( _trip_cnt++ > 24 ) { | |
| 523 DEBUG_ONLY( dump_for_spill_split_recycle(); ) | |
| 524 if( _trip_cnt > 27 ) { | |
| 525 C->record_method_not_compilable("failed spill-split-recycle sanity check"); | |
| 526 return; | |
| 527 } | |
| 528 } | |
| 529 | |
| 10111 | 530 if (!_lrg_map.max_lrg_id()) { |
| 531 return; | |
| 532 } | |
| 533 uint new_max_lrg_id = Split(_lrg_map.max_lrg_id(), &split_arena); // Split spilling LRG everywhere | |
| 534 _lrg_map.set_max_lrg_id(new_max_lrg_id); | |
| 0 | 535 // Bail out if unique gets too large (ie - unique > MaxNodeLimit - 2*NodeLimitFudgeFactor) |
| 10111 | 536 C->check_node_count(2 * NodeLimitFudgeFactor, "out of nodes after split"); |
| 537 if (C->failing()) { | |
| 538 return; | |
| 539 } | |
| 0 | 540 |
| 10111 | 541 compact(); // Compact LRGs; return new lower max lrg |
| 0 | 542 |
| 543 // Nuke the live-ness and interference graph and LiveRanGe info | |
| 544 { | |
| 545 NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); ) | |
| 546 _live = NULL; | |
| 547 rm.reset_to_mark(); // Reclaim working storage | |
| 548 IndexSet::reset_memory(C, &live_arena); | |
| 10111 | 549 ifg.init(_lrg_map.max_lrg_id()); |
| 0 | 550 |
| 551 // Create LiveRanGe array. | |
| 552 // Intersect register masks for all USEs and DEFs | |
| 10111 | 553 gather_lrg_masks(true); |
| 554 live.compute(_lrg_map.max_lrg_id()); | |
| 0 | 555 _live = &live; |
| 556 } | |
| 10111 | 557 must_spill = build_ifg_physical(&live_arena); |
| 0 | 558 _ifg->SquareUp(); |
| 559 _ifg->Compute_Effective_Degree(); | |
| 560 | |
| 561 // Only do conservative coalescing if requested | |
| 10111 | 562 if (OptoCoalesce) { |
| 0 | 563 // Conservative (and pessimistic) copy coalescing |
| 10111 | 564 PhaseConservativeCoalesce coalesce(*this); |
| 0 | 565 // Check for few live ranges determines how aggressive coalesce is. |
| 10111 | 566 coalesce.coalesce_driver(); |
| 0 | 567 } |
| 10111 | 568 _lrg_map.compress_uf_map_for_nodes(); |
| 0 | 569 #ifdef ASSERT |
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570 verify(&live_arena, true); |
| 0 | 571 #endif |
| 572 cache_lrg_info(); // Count degree of LRGs | |
| 573 | |
| 574 // Simplify the InterFerence Graph by removing LRGs of low degree. | |
| 575 // LRGs of low degree are trivially colorable. | |
| 576 Simplify(); | |
| 577 | |
| 578 // Select colors by re-inserting LRGs back into the IFG in reverse order. | |
| 579 // Return whether or not something spills. | |
| 10111 | 580 spills = Select(); |
| 0 | 581 } |
| 582 | |
| 583 // Count number of Simplify-Select trips per coloring success. | |
| 584 _allocator_attempts += _trip_cnt + 1; | |
| 585 _allocator_successes += 1; | |
| 586 | |
| 587 // Peephole remove copies | |
| 588 post_allocate_copy_removal(); | |
| 589 | |
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590 #ifdef ASSERT |
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591 // Veify the graph after RA. |
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592 verify(&live_arena); |
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593 #endif |
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594 |
| 0 | 595 // max_reg is past the largest *register* used. |
| 596 // Convert that to a frame_slot number. | |
| 10111 | 597 if (_max_reg <= _matcher._new_SP) { |
| 0 | 598 _framesize = C->out_preserve_stack_slots(); |
| 10111 | 599 } |
| 600 else { | |
| 601 _framesize = _max_reg -_matcher._new_SP; | |
| 602 } | |
| 0 | 603 assert((int)(_matcher._new_SP+_framesize) >= (int)_matcher._out_arg_limit, "framesize must be large enough"); |
| 604 | |
| 605 // This frame must preserve the required fp alignment | |
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606 _framesize = round_to(_framesize, Matcher::stack_alignment_in_slots()); |
| 0 | 607 assert( _framesize >= 0 && _framesize <= 1000000, "sanity check" ); |
| 608 #ifndef PRODUCT | |
| 609 _total_framesize += _framesize; | |
| 10111 | 610 if ((int)_framesize > _max_framesize) { |
| 0 | 611 _max_framesize = _framesize; |
| 10111 | 612 } |
| 0 | 613 #endif |
| 614 | |
| 615 // Convert CISC spills | |
| 616 fixup_spills(); | |
| 617 | |
| 618 // Log regalloc results | |
| 619 CompileLog* log = Compile::current()->log(); | |
| 620 if (log != NULL) { | |
| 621 log->elem("regalloc attempts='%d' success='%d'", _trip_cnt, !C->failing()); | |
| 622 } | |
| 623 | |
| 10111 | 624 if (C->failing()) { |
| 625 return; | |
| 626 } | |
| 0 | 627 |
| 10111 | 628 NOT_PRODUCT(C->verify_graph_edges();) |
| 0 | 629 |
| 630 // Move important info out of the live_arena to longer lasting storage. | |
| 10111 | 631 alloc_node_regs(_lrg_map.size()); |
| 632 for (uint i=0; i < _lrg_map.size(); i++) { | |
| 633 if (_lrg_map.live_range_id(i)) { // Live range associated with Node? | |
| 634 LRG &lrg = lrgs(_lrg_map.live_range_id(i)); | |
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635 if (!lrg.alive()) { |
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636 set_bad(i); |
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637 } else if (lrg.num_regs() == 1) { |
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638 set1(i, lrg.reg()); |
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639 } else { // Must be a register-set |
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640 if (!lrg._fat_proj) { // Must be aligned adjacent register set |
| 0 | 641 // Live ranges record the highest register in their mask. |
| 642 // We want the low register for the AD file writer's convenience. | |
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643 OptoReg::Name hi = lrg.reg(); // Get hi register |
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644 OptoReg::Name lo = OptoReg::add(hi, (1-lrg.num_regs())); // Find lo |
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645 // We have to use pair [lo,lo+1] even for wide vectors because |
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646 // the rest of code generation works only with pairs. It is safe |
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647 // since for registers encoding only 'lo' is used. |
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648 // Second reg from pair is used in ScheduleAndBundle on SPARC where |
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649 // vector max size is 8 which corresponds to registers pair. |
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650 // It is also used in BuildOopMaps but oop operations are not |
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651 // vectorized. |
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652 set2(i, lo); |
| 0 | 653 } else { // Misaligned; extract 2 bits |
| 654 OptoReg::Name hi = lrg.reg(); // Get hi register | |
| 655 lrg.Remove(hi); // Yank from mask | |
| 656 int lo = lrg.mask().find_first_elem(); // Find lo | |
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657 set_pair(i, hi, lo); |
| 0 | 658 } |
| 659 } | |
| 660 if( lrg._is_oop ) _node_oops.set(i); | |
| 661 } else { | |
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662 set_bad(i); |
| 0 | 663 } |
| 664 } | |
| 665 | |
| 666 // Done! | |
| 667 _live = NULL; | |
| 668 _ifg = NULL; | |
| 669 C->set_indexSet_arena(NULL); // ResourceArea is at end of scope | |
| 670 } | |
| 671 | |
| 672 void PhaseChaitin::de_ssa() { | |
| 673 // Set initial Names for all Nodes. Most Nodes get the virtual register | |
| 674 // number. A few get the ZERO live range number. These do not | |
| 675 // get allocated, but instead rely on correct scheduling to ensure that | |
| 676 // only one instance is simultaneously live at a time. | |
| 677 uint lr_counter = 1; | |
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678 for( uint i = 0; i < _cfg.number_of_blocks(); i++ ) { |
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679 Block* block = _cfg.get_block(i); |
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680 uint cnt = block->_nodes.size(); |
| 0 | 681 |
| 682 // Handle all the normal Nodes in the block | |
| 683 for( uint j = 0; j < cnt; j++ ) { | |
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684 Node *n = block->_nodes[j]; |
| 0 | 685 // Pre-color to the zero live range, or pick virtual register |
| 686 const RegMask &rm = n->out_RegMask(); | |
| 10111 | 687 _lrg_map.map(n->_idx, rm.is_NotEmpty() ? lr_counter++ : 0); |
| 0 | 688 } |
| 689 } | |
| 690 // Reset the Union-Find mapping to be identity | |
| 10111 | 691 _lrg_map.reset_uf_map(lr_counter); |
| 0 | 692 } |
| 693 | |
| 694 | |
| 695 // Gather LiveRanGe information, including register masks. Modification of | |
| 696 // cisc spillable in_RegMasks should not be done before AggressiveCoalesce. | |
| 697 void PhaseChaitin::gather_lrg_masks( bool after_aggressive ) { | |
| 698 | |
| 699 // Nail down the frame pointer live range | |
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700 uint fp_lrg = _lrg_map.live_range_id(_cfg.get_root_node()->in(1)->in(TypeFunc::FramePtr)); |
| 0 | 701 lrgs(fp_lrg)._cost += 1e12; // Cost is infinite |
| 702 | |
| 703 // For all blocks | |
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704 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
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705 Block* block = _cfg.get_block(i); |
| 0 | 706 |
| 707 // For all instructions | |
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708 for (uint j = 1; j < block->_nodes.size(); j++) { |
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709 Node* n = block->_nodes[j]; |
| 0 | 710 uint input_edge_start =1; // Skip control most nodes |
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711 if (n->is_Mach()) { |
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712 input_edge_start = n->as_Mach()->oper_input_base(); |
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713 } |
| 0 | 714 uint idx = n->is_Copy(); |
| 715 | |
| 716 // Get virtual register number, same as LiveRanGe index | |
| 10111 | 717 uint vreg = _lrg_map.live_range_id(n); |
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718 LRG& lrg = lrgs(vreg); |
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719 if (vreg) { // No vreg means un-allocable (e.g. memory) |
| 0 | 720 |
| 721 // Collect has-copy bit | |
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722 if (idx) { |
| 0 | 723 lrg._has_copy = 1; |
| 10111 | 724 uint clidx = _lrg_map.live_range_id(n->in(idx)); |
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725 LRG& copy_src = lrgs(clidx); |
| 0 | 726 copy_src._has_copy = 1; |
| 727 } | |
| 728 | |
| 729 // Check for float-vs-int live range (used in register-pressure | |
| 730 // calculations) | |
| 731 const Type *n_type = n->bottom_type(); | |
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732 if (n_type->is_floatingpoint()) { |
| 0 | 733 lrg._is_float = 1; |
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734 } |
| 0 | 735 |
| 736 // Check for twice prior spilling. Once prior spilling might have | |
| 737 // spilled 'soft', 2nd prior spill should have spilled 'hard' and | |
| 738 // further spilling is unlikely to make progress. | |
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739 if (_spilled_once.test(n->_idx)) { |
| 0 | 740 lrg._was_spilled1 = 1; |
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741 if (_spilled_twice.test(n->_idx)) { |
| 0 | 742 lrg._was_spilled2 = 1; |
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743 } |
| 0 | 744 } |
| 745 | |
| 746 #ifndef PRODUCT | |
| 747 if (trace_spilling() && lrg._def != NULL) { | |
| 748 // collect defs for MultiDef printing | |
| 749 if (lrg._defs == NULL) { | |
| 1685 | 750 lrg._defs = new (_ifg->_arena) GrowableArray<Node*>(_ifg->_arena, 2, 0, NULL); |
| 0 | 751 lrg._defs->append(lrg._def); |
| 752 } | |
| 753 lrg._defs->append(n); | |
| 754 } | |
| 755 #endif | |
| 756 | |
| 757 // Check for a single def LRG; these can spill nicely | |
| 758 // via rematerialization. Flag as NULL for no def found | |
| 759 // yet, or 'n' for single def or -1 for many defs. | |
| 760 lrg._def = lrg._def ? NodeSentinel : n; | |
| 761 | |
| 762 // Limit result register mask to acceptable registers | |
| 763 const RegMask &rm = n->out_RegMask(); | |
| 764 lrg.AND( rm ); | |
| 765 | |
| 766 int ireg = n->ideal_reg(); | |
| 767 assert( !n->bottom_type()->isa_oop_ptr() || ireg == Op_RegP, | |
| 768 "oops must be in Op_RegP's" ); | |
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769 |
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770 // Check for vector live range (only if vector register is used). |
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771 // On SPARC vector uses RegD which could be misaligned so it is not |
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772 // processes as vector in RA. |
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773 if (RegMask::is_vector(ireg)) |
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774 lrg._is_vector = 1; |
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775 assert(n_type->isa_vect() == NULL || lrg._is_vector || ireg == Op_RegD, |
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776 "vector must be in vector registers"); |
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777 |
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778 // Check for bound register masks |
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779 const RegMask &lrgmask = lrg.mask(); |
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780 if (lrgmask.is_bound(ireg)) { |
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781 lrg._is_bound = 1; |
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782 } |
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783 |
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784 // Check for maximum frequency value |
|
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785 if (lrg._maxfreq < block->_freq) { |
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786 lrg._maxfreq = block->_freq; |
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787 } |
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788 |
| 0 | 789 // Check for oop-iness, or long/double |
| 790 // Check for multi-kill projection | |
|
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791 switch (ireg) { |
| 0 | 792 case MachProjNode::fat_proj: |
| 793 // Fat projections have size equal to number of registers killed | |
| 794 lrg.set_num_regs(rm.Size()); | |
| 795 lrg.set_reg_pressure(lrg.num_regs()); | |
| 796 lrg._fat_proj = 1; | |
| 797 lrg._is_bound = 1; | |
| 798 break; | |
| 799 case Op_RegP: | |
| 800 #ifdef _LP64 | |
| 801 lrg.set_num_regs(2); // Size is 2 stack words | |
| 802 #else | |
| 803 lrg.set_num_regs(1); // Size is 1 stack word | |
| 804 #endif | |
| 805 // Register pressure is tracked relative to the maximum values | |
| 806 // suggested for that platform, INTPRESSURE and FLOATPRESSURE, | |
| 807 // and relative to other types which compete for the same regs. | |
| 808 // | |
| 809 // The following table contains suggested values based on the | |
| 810 // architectures as defined in each .ad file. | |
| 811 // INTPRESSURE and FLOATPRESSURE may be tuned differently for | |
| 812 // compile-speed or performance. | |
| 813 // Note1: | |
| 814 // SPARC and SPARCV9 reg_pressures are at 2 instead of 1 | |
| 815 // since .ad registers are defined as high and low halves. | |
| 816 // These reg_pressure values remain compatible with the code | |
| 817 // in is_high_pressure() which relates get_invalid_mask_size(), | |
| 818 // Block::_reg_pressure and INTPRESSURE, FLOATPRESSURE. | |
| 819 // Note2: | |
| 820 // SPARC -d32 has 24 registers available for integral values, | |
| 821 // but only 10 of these are safe for 64-bit longs. | |
| 822 // Using set_reg_pressure(2) for both int and long means | |
| 823 // the allocator will believe it can fit 26 longs into | |
| 824 // registers. Using 2 for longs and 1 for ints means the | |
| 825 // allocator will attempt to put 52 integers into registers. | |
| 826 // The settings below limit this problem to methods with | |
| 827 // many long values which are being run on 32-bit SPARC. | |
| 828 // | |
| 829 // ------------------- reg_pressure -------------------- | |
| 830 // Each entry is reg_pressure_per_value,number_of_regs | |
| 831 // RegL RegI RegFlags RegF RegD INTPRESSURE FLOATPRESSURE | |
| 832 // IA32 2 1 1 1 1 6 6 | |
| 833 // IA64 1 1 1 1 1 50 41 | |
| 834 // SPARC 2 2 2 2 2 48 (24) 52 (26) | |
| 835 // SPARCV9 2 2 2 2 2 48 (24) 52 (26) | |
| 836 // AMD64 1 1 1 1 1 14 15 | |
| 837 // ----------------------------------------------------- | |
| 838 #if defined(SPARC) | |
| 839 lrg.set_reg_pressure(2); // use for v9 as well | |
| 840 #else | |
| 841 lrg.set_reg_pressure(1); // normally one value per register | |
| 842 #endif | |
| 843 if( n_type->isa_oop_ptr() ) { | |
| 844 lrg._is_oop = 1; | |
| 845 } | |
| 846 break; | |
| 847 case Op_RegL: // Check for long or double | |
| 848 case Op_RegD: | |
| 849 lrg.set_num_regs(2); | |
| 850 // Define platform specific register pressure | |
|
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851 #if defined(SPARC) || defined(ARM) |
| 0 | 852 lrg.set_reg_pressure(2); |
| 853 #elif defined(IA32) | |
| 854 if( ireg == Op_RegL ) { | |
| 855 lrg.set_reg_pressure(2); | |
| 856 } else { | |
| 857 lrg.set_reg_pressure(1); | |
| 858 } | |
| 859 #else | |
| 860 lrg.set_reg_pressure(1); // normally one value per register | |
| 861 #endif | |
| 862 // If this def of a double forces a mis-aligned double, | |
| 863 // flag as '_fat_proj' - really flag as allowing misalignment | |
| 864 // AND changes how we count interferences. A mis-aligned | |
| 865 // double can interfere with TWO aligned pairs, or effectively | |
| 866 // FOUR registers! | |
|
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867 if (rm.is_misaligned_pair()) { |
| 0 | 868 lrg._fat_proj = 1; |
| 869 lrg._is_bound = 1; | |
| 870 } | |
| 871 break; | |
| 872 case Op_RegF: | |
| 873 case Op_RegI: | |
|
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874 case Op_RegN: |
| 0 | 875 case Op_RegFlags: |
| 876 case 0: // not an ideal register | |
| 877 lrg.set_num_regs(1); | |
| 878 #ifdef SPARC | |
| 879 lrg.set_reg_pressure(2); | |
| 880 #else | |
| 881 lrg.set_reg_pressure(1); | |
| 882 #endif | |
| 883 break; | |
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884 case Op_VecS: |
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885 assert(Matcher::vector_size_supported(T_BYTE,4), "sanity"); |
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886 assert(RegMask::num_registers(Op_VecS) == RegMask::SlotsPerVecS, "sanity"); |
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887 lrg.set_num_regs(RegMask::SlotsPerVecS); |
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888 lrg.set_reg_pressure(1); |
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889 break; |
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890 case Op_VecD: |
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891 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecD), "sanity"); |
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892 assert(RegMask::num_registers(Op_VecD) == RegMask::SlotsPerVecD, "sanity"); |
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893 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecD), "vector should be aligned"); |
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894 lrg.set_num_regs(RegMask::SlotsPerVecD); |
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895 lrg.set_reg_pressure(1); |
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896 break; |
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897 case Op_VecX: |
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898 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecX), "sanity"); |
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899 assert(RegMask::num_registers(Op_VecX) == RegMask::SlotsPerVecX, "sanity"); |
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900 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecX), "vector should be aligned"); |
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901 lrg.set_num_regs(RegMask::SlotsPerVecX); |
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902 lrg.set_reg_pressure(1); |
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903 break; |
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904 case Op_VecY: |
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905 assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecY), "sanity"); |
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906 assert(RegMask::num_registers(Op_VecY) == RegMask::SlotsPerVecY, "sanity"); |
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907 assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecY), "vector should be aligned"); |
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908 lrg.set_num_regs(RegMask::SlotsPerVecY); |
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909 lrg.set_reg_pressure(1); |
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910 break; |
| 0 | 911 default: |
| 912 ShouldNotReachHere(); | |
| 913 } | |
| 914 } | |
| 915 | |
| 916 // Now do the same for inputs | |
| 917 uint cnt = n->req(); | |
| 918 // Setup for CISC SPILLING | |
| 919 uint inp = (uint)AdlcVMDeps::Not_cisc_spillable; | |
| 920 if( UseCISCSpill && after_aggressive ) { | |
| 921 inp = n->cisc_operand(); | |
| 922 if( inp != (uint)AdlcVMDeps::Not_cisc_spillable ) | |
| 923 // Convert operand number to edge index number | |
| 924 inp = n->as_Mach()->operand_index(inp); | |
| 925 } | |
| 926 // Prepare register mask for each input | |
| 927 for( uint k = input_edge_start; k < cnt; k++ ) { | |
| 10111 | 928 uint vreg = _lrg_map.live_range_id(n->in(k)); |
| 929 if (!vreg) { | |
| 930 continue; | |
| 931 } | |
| 0 | 932 |
| 933 // If this instruction is CISC Spillable, add the flags | |
| 934 // bit to its appropriate input | |
| 935 if( UseCISCSpill && after_aggressive && inp == k ) { | |
| 936 #ifndef PRODUCT | |
| 937 if( TraceCISCSpill ) { | |
| 938 tty->print(" use_cisc_RegMask: "); | |
| 939 n->dump(); | |
| 940 } | |
| 941 #endif | |
| 942 n->as_Mach()->use_cisc_RegMask(); | |
| 943 } | |
| 944 | |
| 945 LRG &lrg = lrgs(vreg); | |
| 946 // // Testing for floating point code shape | |
| 947 // Node *test = n->in(k); | |
| 948 // if( test->is_Mach() ) { | |
| 949 // MachNode *m = test->as_Mach(); | |
| 950 // int op = m->ideal_Opcode(); | |
| 951 // if (n->is_Call() && (op == Op_AddF || op == Op_MulF) ) { | |
| 952 // int zzz = 1; | |
| 953 // } | |
| 954 // } | |
| 955 | |
| 956 // Limit result register mask to acceptable registers. | |
| 957 // Do not limit registers from uncommon uses before | |
| 958 // AggressiveCoalesce. This effectively pre-virtual-splits | |
| 959 // around uncommon uses of common defs. | |
| 960 const RegMask &rm = n->in_RegMask(k); | |
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961 if (!after_aggressive && _cfg.get_block_for_node(n->in(k))->_freq > 1000 * block->_freq) { |
| 0 | 962 // Since we are BEFORE aggressive coalesce, leave the register |
| 963 // mask untrimmed by the call. This encourages more coalescing. | |
| 964 // Later, AFTER aggressive, this live range will have to spill | |
| 965 // but the spiller handles slow-path calls very nicely. | |
| 966 } else { | |
| 967 lrg.AND( rm ); | |
| 968 } | |
|
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969 |
| 0 | 970 // Check for bound register masks |
| 971 const RegMask &lrgmask = lrg.mask(); | |
|
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972 int kreg = n->in(k)->ideal_reg(); |
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973 bool is_vect = RegMask::is_vector(kreg); |
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974 assert(n->in(k)->bottom_type()->isa_vect() == NULL || |
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975 is_vect || kreg == Op_RegD, |
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976 "vector must be in vector registers"); |
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977 if (lrgmask.is_bound(kreg)) |
| 0 | 978 lrg._is_bound = 1; |
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979 |
| 0 | 980 // If this use of a double forces a mis-aligned double, |
| 981 // flag as '_fat_proj' - really flag as allowing misalignment | |
| 982 // AND changes how we count interferences. A mis-aligned | |
| 983 // double can interfere with TWO aligned pairs, or effectively | |
| 984 // FOUR registers! | |
|
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985 #ifdef ASSERT |
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986 if (is_vect) { |
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987 assert(lrgmask.is_aligned_sets(lrg.num_regs()), "vector should be aligned"); |
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988 assert(!lrg._fat_proj, "sanity"); |
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989 assert(RegMask::num_registers(kreg) == lrg.num_regs(), "sanity"); |
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990 } |
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991 #endif |
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992 if (!is_vect && lrg.num_regs() == 2 && !lrg._fat_proj && rm.is_misaligned_pair()) { |
| 0 | 993 lrg._fat_proj = 1; |
| 994 lrg._is_bound = 1; | |
| 995 } | |
| 996 // if the LRG is an unaligned pair, we will have to spill | |
| 997 // so clear the LRG's register mask if it is not already spilled | |
|
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998 if (!is_vect && !n->is_SpillCopy() && |
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999 (lrg._def == NULL || lrg.is_multidef() || !lrg._def->is_SpillCopy()) && |
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1000 lrgmask.is_misaligned_pair()) { |
| 0 | 1001 lrg.Clear(); |
| 1002 } | |
| 1003 | |
| 1004 // Check for maximum frequency value | |
|
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1005 if (lrg._maxfreq < block->_freq) { |
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1006 lrg._maxfreq = block->_freq; |
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1007 } |
| 0 | 1008 |
| 1009 } // End for all allocated inputs | |
| 1010 } // end for all instructions | |
| 1011 } // end for all blocks | |
| 1012 | |
| 1013 // Final per-liverange setup | |
| 10111 | 1014 for (uint i2 = 0; i2 < _lrg_map.max_lrg_id(); i2++) { |
| 0 | 1015 LRG &lrg = lrgs(i2); |
|
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1016 assert(!lrg._is_vector || !lrg._fat_proj, "sanity"); |
|
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1017 if (lrg.num_regs() > 1 && !lrg._fat_proj) { |
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1018 lrg.clear_to_sets(); |
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1019 } |
| 0 | 1020 lrg.compute_set_mask_size(); |
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1021 if (lrg.not_free()) { // Handle case where we lose from the start |
| 0 | 1022 lrg.set_reg(OptoReg::Name(LRG::SPILL_REG)); |
| 1023 lrg._direct_conflict = 1; | |
| 1024 } | |
| 1025 lrg.set_degree(0); // no neighbors in IFG yet | |
| 1026 } | |
| 1027 } | |
| 1028 | |
| 1029 // Set the was-lo-degree bit. Conservative coalescing should not change the | |
| 1030 // colorability of the graph. If any live range was of low-degree before | |
| 1031 // coalescing, it should Simplify. This call sets the was-lo-degree bit. | |
| 1032 // The bit is checked in Simplify. | |
| 1033 void PhaseChaitin::set_was_low() { | |
| 1034 #ifdef ASSERT | |
| 10111 | 1035 for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) { |
| 0 | 1036 int size = lrgs(i).num_regs(); |
| 1037 uint old_was_lo = lrgs(i)._was_lo; | |
| 1038 lrgs(i)._was_lo = 0; | |
| 1039 if( lrgs(i).lo_degree() ) { | |
| 1040 lrgs(i)._was_lo = 1; // Trivially of low degree | |
| 1041 } else { // Else check the Brigg's assertion | |
| 1042 // Brigg's observation is that the lo-degree neighbors of a | |
| 1043 // hi-degree live range will not interfere with the color choices | |
| 1044 // of said hi-degree live range. The Simplify reverse-stack-coloring | |
| 1045 // order takes care of the details. Hence you do not have to count | |
| 1046 // low-degree neighbors when determining if this guy colors. | |
| 1047 int briggs_degree = 0; | |
| 1048 IndexSet *s = _ifg->neighbors(i); | |
| 1049 IndexSetIterator elements(s); | |
| 1050 uint lidx; | |
| 1051 while((lidx = elements.next()) != 0) { | |
| 1052 if( !lrgs(lidx).lo_degree() ) | |
| 1053 briggs_degree += MAX2(size,lrgs(lidx).num_regs()); | |
| 1054 } | |
| 1055 if( briggs_degree < lrgs(i).degrees_of_freedom() ) | |
| 1056 lrgs(i)._was_lo = 1; // Low degree via the briggs assertion | |
| 1057 } | |
| 1058 assert(old_was_lo <= lrgs(i)._was_lo, "_was_lo may not decrease"); | |
| 1059 } | |
| 1060 #endif | |
| 1061 } | |
| 1062 | |
| 1063 #define REGISTER_CONSTRAINED 16 | |
| 1064 | |
| 1065 // Compute cost/area ratio, in case we spill. Build the lo-degree list. | |
| 1066 void PhaseChaitin::cache_lrg_info( ) { | |
| 1067 | |
| 10111 | 1068 for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) { |
| 0 | 1069 LRG &lrg = lrgs(i); |
| 1070 | |
| 1071 // Check for being of low degree: means we can be trivially colored. | |
| 1072 // Low degree, dead or must-spill guys just get to simplify right away | |
| 1073 if( lrg.lo_degree() || | |
| 1074 !lrg.alive() || | |
| 1075 lrg._must_spill ) { | |
| 1076 // Split low degree list into those guys that must get a | |
| 1077 // register and those that can go to register or stack. | |
| 1078 // The idea is LRGs that can go register or stack color first when | |
| 1079 // they have a good chance of getting a register. The register-only | |
| 1080 // lo-degree live ranges always get a register. | |
| 1081 OptoReg::Name hi_reg = lrg.mask().find_last_elem(); | |
| 1082 if( OptoReg::is_stack(hi_reg)) { // Can go to stack? | |
| 1083 lrg._next = _lo_stk_degree; | |
| 1084 _lo_stk_degree = i; | |
| 1085 } else { | |
| 1086 lrg._next = _lo_degree; | |
| 1087 _lo_degree = i; | |
| 1088 } | |
| 1089 } else { // Else high degree | |
| 1090 lrgs(_hi_degree)._prev = i; | |
| 1091 lrg._next = _hi_degree; | |
| 1092 lrg._prev = 0; | |
| 1093 _hi_degree = i; | |
| 1094 } | |
| 1095 } | |
| 1096 } | |
| 1097 | |
| 1098 // Simplify the IFG by removing LRGs of low degree that have NO copies | |
| 1099 void PhaseChaitin::Pre_Simplify( ) { | |
| 1100 | |
| 1101 // Warm up the lo-degree no-copy list | |
| 1102 int lo_no_copy = 0; | |
| 10111 | 1103 for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) { |
| 1104 if ((lrgs(i).lo_degree() && !lrgs(i)._has_copy) || | |
| 0 | 1105 !lrgs(i).alive() || |
| 10111 | 1106 lrgs(i)._must_spill) { |
| 0 | 1107 lrgs(i)._next = lo_no_copy; |
| 1108 lo_no_copy = i; | |
| 1109 } | |
| 1110 } | |
| 1111 | |
| 1112 while( lo_no_copy ) { | |
| 1113 uint lo = lo_no_copy; | |
| 1114 lo_no_copy = lrgs(lo)._next; | |
| 1115 int size = lrgs(lo).num_regs(); | |
| 1116 | |
| 1117 // Put the simplified guy on the simplified list. | |
| 1118 lrgs(lo)._next = _simplified; | |
| 1119 _simplified = lo; | |
| 1120 | |
| 1121 // Yank this guy from the IFG. | |
| 1122 IndexSet *adj = _ifg->remove_node( lo ); | |
| 1123 | |
| 1124 // If any neighbors' degrees fall below their number of | |
| 1125 // allowed registers, then put that neighbor on the low degree | |
| 1126 // list. Note that 'degree' can only fall and 'numregs' is | |
| 1127 // unchanged by this action. Thus the two are equal at most once, | |
| 1128 // so LRGs hit the lo-degree worklists at most once. | |
| 1129 IndexSetIterator elements(adj); | |
| 1130 uint neighbor; | |
| 1131 while ((neighbor = elements.next()) != 0) { | |
| 1132 LRG *n = &lrgs(neighbor); | |
| 1133 assert( _ifg->effective_degree(neighbor) == n->degree(), "" ); | |
| 1134 | |
| 1135 // Check for just becoming of-low-degree | |
| 1136 if( n->just_lo_degree() && !n->_has_copy ) { | |
| 1137 assert(!(*_ifg->_yanked)[neighbor],"Cannot move to lo degree twice"); | |
| 1138 // Put on lo-degree list | |
| 1139 n->_next = lo_no_copy; | |
| 1140 lo_no_copy = neighbor; | |
| 1141 } | |
| 1142 } | |
| 1143 } // End of while lo-degree no_copy worklist not empty | |
| 1144 | |
| 1145 // No more lo-degree no-copy live ranges to simplify | |
| 1146 } | |
| 1147 | |
| 1148 // Simplify the IFG by removing LRGs of low degree. | |
| 1149 void PhaseChaitin::Simplify( ) { | |
| 1150 | |
| 1151 while( 1 ) { // Repeat till simplified it all | |
| 1152 // May want to explore simplifying lo_degree before _lo_stk_degree. | |
| 1153 // This might result in more spills coloring into registers during | |
| 1154 // Select(). | |
| 1155 while( _lo_degree || _lo_stk_degree ) { | |
| 1156 // If possible, pull from lo_stk first | |
| 1157 uint lo; | |
| 1158 if( _lo_degree ) { | |
| 1159 lo = _lo_degree; | |
| 1160 _lo_degree = lrgs(lo)._next; | |
| 1161 } else { | |
| 1162 lo = _lo_stk_degree; | |
| 1163 _lo_stk_degree = lrgs(lo)._next; | |
| 1164 } | |
| 1165 | |
| 1166 // Put the simplified guy on the simplified list. | |
| 1167 lrgs(lo)._next = _simplified; | |
| 1168 _simplified = lo; | |
| 1169 // If this guy is "at risk" then mark his current neighbors | |
| 1170 if( lrgs(lo)._at_risk ) { | |
| 1171 IndexSetIterator elements(_ifg->neighbors(lo)); | |
| 1172 uint datum; | |
| 1173 while ((datum = elements.next()) != 0) { | |
| 1174 lrgs(datum)._risk_bias = lo; | |
| 1175 } | |
| 1176 } | |
| 1177 | |
| 1178 // Yank this guy from the IFG. | |
| 1179 IndexSet *adj = _ifg->remove_node( lo ); | |
| 1180 | |
| 1181 // If any neighbors' degrees fall below their number of | |
| 1182 // allowed registers, then put that neighbor on the low degree | |
| 1183 // list. Note that 'degree' can only fall and 'numregs' is | |
| 1184 // unchanged by this action. Thus the two are equal at most once, | |
| 1185 // so LRGs hit the lo-degree worklist at most once. | |
| 1186 IndexSetIterator elements(adj); | |
| 1187 uint neighbor; | |
| 1188 while ((neighbor = elements.next()) != 0) { | |
| 1189 LRG *n = &lrgs(neighbor); | |
| 1190 #ifdef ASSERT | |
|
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1191 if( VerifyOpto || VerifyRegisterAllocator ) { |
| 0 | 1192 assert( _ifg->effective_degree(neighbor) == n->degree(), "" ); |
| 1193 } | |
| 1194 #endif | |
| 1195 | |
| 1196 // Check for just becoming of-low-degree just counting registers. | |
| 1197 // _must_spill live ranges are already on the low degree list. | |
| 1198 if( n->just_lo_degree() && !n->_must_spill ) { | |
| 1199 assert(!(*_ifg->_yanked)[neighbor],"Cannot move to lo degree twice"); | |
| 1200 // Pull from hi-degree list | |
| 1201 uint prev = n->_prev; | |
| 1202 uint next = n->_next; | |
| 1203 if( prev ) lrgs(prev)._next = next; | |
| 1204 else _hi_degree = next; | |
| 1205 lrgs(next)._prev = prev; | |
| 1206 n->_next = _lo_degree; | |
| 1207 _lo_degree = neighbor; | |
| 1208 } | |
| 1209 } | |
| 1210 } // End of while lo-degree/lo_stk_degree worklist not empty | |
| 1211 | |
| 1212 // Check for got everything: is hi-degree list empty? | |
| 1213 if( !_hi_degree ) break; | |
| 1214 | |
| 1215 // Time to pick a potential spill guy | |
| 1216 uint lo_score = _hi_degree; | |
| 1217 double score = lrgs(lo_score).score(); | |
| 1218 double area = lrgs(lo_score)._area; | |
|
1008
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|
1219 double cost = lrgs(lo_score)._cost; |
|
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|
1220 bool bound = lrgs(lo_score)._is_bound; |
| 0 | 1221 |
| 1222 // Find cheapest guy | |
| 1223 debug_only( int lo_no_simplify=0; ); | |
|
1012
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kvn
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1008
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|
1224 for( uint i = _hi_degree; i; i = lrgs(i)._next ) { |
| 0 | 1225 assert( !(*_ifg->_yanked)[i], "" ); |
| 1226 // It's just vaguely possible to move hi-degree to lo-degree without | |
| 1227 // going through a just-lo-degree stage: If you remove a double from | |
| 1228 // a float live range it's degree will drop by 2 and you can skip the | |
| 1229 // just-lo-degree stage. It's very rare (shows up after 5000+ methods | |
| 1230 // in -Xcomp of Java2Demo). So just choose this guy to simplify next. | |
| 1231 if( lrgs(i).lo_degree() ) { | |
| 1232 lo_score = i; | |
| 1233 break; | |
| 1234 } | |
| 1235 debug_only( if( lrgs(i)._was_lo ) lo_no_simplify=i; ); | |
| 1236 double iscore = lrgs(i).score(); | |
| 1237 double iarea = lrgs(i)._area; | |
|
1008
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|
1238 double icost = lrgs(i)._cost; |
|
e90521d61f9a
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|
1239 bool ibound = lrgs(i)._is_bound; |
| 0 | 1240 |
| 1241 // Compare cost/area of i vs cost/area of lo_score. Smaller cost/area | |
| 1242 // wins. Ties happen because all live ranges in question have spilled | |
| 1243 // a few times before and the spill-score adds a huge number which | |
| 1244 // washes out the low order bits. We are choosing the lesser of 2 | |
| 1245 // evils; in this case pick largest area to spill. | |
|
1008
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|
1246 // Ties also happen when live ranges are defined and used only inside |
|
e90521d61f9a
6875959: CTW fails hotspot/src/share/vm/opto/reg_split.cpp:1087
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|
1247 // one block. In which case their area is 0 and score set to max. |
|
e90521d61f9a
6875959: CTW fails hotspot/src/share/vm/opto/reg_split.cpp:1087
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|
1248 // In such case choose bound live range over unbound to free registers |
|
e90521d61f9a
6875959: CTW fails hotspot/src/share/vm/opto/reg_split.cpp:1087
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diff
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|
1249 // or with smaller cost to spill. |
| 0 | 1250 if( iscore < score || |
|
1008
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6875959: CTW fails hotspot/src/share/vm/opto/reg_split.cpp:1087
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|
1251 (iscore == score && iarea > area && lrgs(lo_score)._was_spilled2) || |
|
e90521d61f9a
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|
1252 (iscore == score && iarea == area && |
|
e90521d61f9a
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|
1253 ( (ibound && !bound) || ibound == bound && (icost < cost) )) ) { |
| 0 | 1254 lo_score = i; |
| 1255 score = iscore; | |
| 1256 area = iarea; | |
|
1008
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|
1257 cost = icost; |
|
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|
1258 bound = ibound; |
| 0 | 1259 } |
| 1260 } | |
| 1261 LRG *lo_lrg = &lrgs(lo_score); | |
| 1262 // The live range we choose for spilling is either hi-degree, or very | |
| 1263 // rarely it can be low-degree. If we choose a hi-degree live range | |
| 1264 // there better not be any lo-degree choices. | |
| 1265 assert( lo_lrg->lo_degree() || !lo_no_simplify, "Live range was lo-degree before coalesce; should simplify" ); | |
| 1266 | |
| 1267 // Pull from hi-degree list | |
| 1268 uint prev = lo_lrg->_prev; | |
| 1269 uint next = lo_lrg->_next; | |
| 1270 if( prev ) lrgs(prev)._next = next; | |
| 1271 else _hi_degree = next; | |
| 1272 lrgs(next)._prev = prev; | |
| 1273 // Jam him on the lo-degree list, despite his high degree. | |
| 1274 // Maybe he'll get a color, and maybe he'll spill. | |
| 1275 // Only Select() will know. | |
| 1276 lrgs(lo_score)._at_risk = true; | |
| 1277 _lo_degree = lo_score; | |
| 1278 lo_lrg->_next = 0; | |
| 1279 | |
| 1280 } // End of while not simplified everything | |
| 1281 | |
| 1282 } | |
| 1283 | |
|
6620
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|
1284 // Is 'reg' register legal for 'lrg'? |
|
f7cd53cedd78
7192965: assert(is_aligned_sets(size)) failed: mask is not aligned, adjacent sets
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|
1285 static bool is_legal_reg(LRG &lrg, OptoReg::Name reg, int chunk) { |
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1286 if (reg >= chunk && reg < (chunk + RegMask::CHUNK_SIZE) && |
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1287 lrg.mask().Member(OptoReg::add(reg,-chunk))) { |
|
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1288 // RA uses OptoReg which represent the highest element of a registers set. |
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1289 // For example, vectorX (128bit) on x86 uses [XMM,XMMb,XMMc,XMMd] set |
|
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1290 // in which XMMd is used by RA to represent such vectors. A double value |
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1291 // uses [XMM,XMMb] pairs and XMMb is used by RA for it. |
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1292 // The register mask uses largest bits set of overlapping register sets. |
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1293 // On x86 with AVX it uses 8 bits for each XMM registers set. |
|
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1294 // |
|
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1295 // The 'lrg' already has cleared-to-set register mask (done in Select() |
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1296 // before calling choose_color()). Passing mask.Member(reg) check above |
|
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1297 // indicates that the size (num_regs) of 'reg' set is less or equal to |
|
f7cd53cedd78
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1298 // 'lrg' set size. |
|
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1299 // For set size 1 any register which is member of 'lrg' mask is legal. |
|
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1300 if (lrg.num_regs()==1) |
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1301 return true; |
|
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1302 // For larger sets only an aligned register with the same set size is legal. |
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1303 int mask = lrg.num_regs()-1; |
|
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1304 if ((reg&mask) == mask) |
|
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1305 return true; |
|
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1306 } |
|
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1307 return false; |
|
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1308 } |
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1309 |
| 0 | 1310 // Choose a color using the biasing heuristic |
| 1311 OptoReg::Name PhaseChaitin::bias_color( LRG &lrg, int chunk ) { | |
| 1312 | |
| 1313 // Check for "at_risk" LRG's | |
| 10111 | 1314 uint risk_lrg = _lrg_map.find(lrg._risk_bias); |
| 0 | 1315 if( risk_lrg != 0 ) { |
| 1316 // Walk the colored neighbors of the "at_risk" candidate | |
| 1317 // Choose a color which is both legal and already taken by a neighbor | |
| 1318 // of the "at_risk" candidate in order to improve the chances of the | |
| 1319 // "at_risk" candidate of coloring | |
| 1320 IndexSetIterator elements(_ifg->neighbors(risk_lrg)); | |
| 1321 uint datum; | |
| 1322 while ((datum = elements.next()) != 0) { | |
| 1323 OptoReg::Name reg = lrgs(datum).reg(); | |
| 1324 // If this LRG's register is legal for us, choose it | |
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1325 if (is_legal_reg(lrg, reg, chunk)) |
| 0 | 1326 return reg; |
| 1327 } | |
| 1328 } | |
| 1329 | |
| 10111 | 1330 uint copy_lrg = _lrg_map.find(lrg._copy_bias); |
| 0 | 1331 if( copy_lrg != 0 ) { |
| 1332 // If he has a color, | |
| 1333 if( !(*(_ifg->_yanked))[copy_lrg] ) { | |
| 1334 OptoReg::Name reg = lrgs(copy_lrg).reg(); | |
| 1335 // And it is legal for you, | |
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1336 if (is_legal_reg(lrg, reg, chunk)) |
| 0 | 1337 return reg; |
| 1338 } else if( chunk == 0 ) { | |
| 1339 // Choose a color which is legal for him | |
| 1340 RegMask tempmask = lrg.mask(); | |
| 1341 tempmask.AND(lrgs(copy_lrg).mask()); | |
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1342 tempmask.clear_to_sets(lrg.num_regs()); |
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1343 OptoReg::Name reg = tempmask.find_first_set(lrg.num_regs()); |
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1344 if (OptoReg::is_valid(reg)) |
| 0 | 1345 return reg; |
| 1346 } | |
| 1347 } | |
| 1348 | |
| 1349 // If no bias info exists, just go with the register selection ordering | |
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1350 if (lrg._is_vector || lrg.num_regs() == 2) { |
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1351 // Find an aligned set |
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1352 return OptoReg::add(lrg.mask().find_first_set(lrg.num_regs()),chunk); |
| 0 | 1353 } |
| 1354 | |
| 1355 // CNC - Fun hack. Alternate 1st and 2nd selection. Enables post-allocate | |
| 1356 // copy removal to remove many more copies, by preventing a just-assigned | |
| 1357 // register from being repeatedly assigned. | |
| 1358 OptoReg::Name reg = lrg.mask().find_first_elem(); | |
| 1359 if( (++_alternate & 1) && OptoReg::is_valid(reg) ) { | |
| 1360 // This 'Remove; find; Insert' idiom is an expensive way to find the | |
| 1361 // SECOND element in the mask. | |
| 1362 lrg.Remove(reg); | |
| 1363 OptoReg::Name reg2 = lrg.mask().find_first_elem(); | |
| 1364 lrg.Insert(reg); | |
| 1365 if( OptoReg::is_reg(reg2)) | |
| 1366 reg = reg2; | |
| 1367 } | |
| 1368 return OptoReg::add( reg, chunk ); | |
| 1369 } | |
| 1370 | |
| 1371 // Choose a color in the current chunk | |
| 1372 OptoReg::Name PhaseChaitin::choose_color( LRG &lrg, int chunk ) { | |
| 1373 assert( C->in_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP-1)), "must not allocate stack0 (inside preserve area)"); | |
| 1374 assert(C->out_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP+0)), "must not allocate stack0 (inside preserve area)"); | |
| 1375 | |
| 1376 if( lrg.num_regs() == 1 || // Common Case | |
| 1377 !lrg._fat_proj ) // Aligned+adjacent pairs ok | |
| 1378 // Use a heuristic to "bias" the color choice | |
| 1379 return bias_color(lrg, chunk); | |
| 1380 | |
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1381 assert(!lrg._is_vector, "should be not vector here" ); |
| 0 | 1382 assert( lrg.num_regs() >= 2, "dead live ranges do not color" ); |
| 1383 | |
| 1384 // Fat-proj case or misaligned double argument. | |
| 1385 assert(lrg.compute_mask_size() == lrg.num_regs() || | |
| 1386 lrg.num_regs() == 2,"fat projs exactly color" ); | |
| 1387 assert( !chunk, "always color in 1st chunk" ); | |
| 1388 // Return the highest element in the set. | |
| 1389 return lrg.mask().find_last_elem(); | |
| 1390 } | |
| 1391 | |
| 1392 // Select colors by re-inserting LRGs back into the IFG. LRGs are re-inserted | |
| 1393 // in reverse order of removal. As long as nothing of hi-degree was yanked, | |
| 1394 // everything going back is guaranteed a color. Select that color. If some | |
| 1395 // hi-degree LRG cannot get a color then we record that we must spill. | |
| 1396 uint PhaseChaitin::Select( ) { | |
| 1397 uint spill_reg = LRG::SPILL_REG; | |
| 1398 _max_reg = OptoReg::Name(0); // Past max register used | |
| 1399 while( _simplified ) { | |
| 1400 // Pull next LRG from the simplified list - in reverse order of removal | |
| 1401 uint lidx = _simplified; | |
| 1402 LRG *lrg = &lrgs(lidx); | |
| 1403 _simplified = lrg->_next; | |
| 1404 | |
| 1405 | |
| 1406 #ifndef PRODUCT | |
| 1407 if (trace_spilling()) { | |
| 1408 ttyLocker ttyl; | |
| 1409 tty->print_cr("L%d selecting degree %d degrees_of_freedom %d", lidx, lrg->degree(), | |
| 1410 lrg->degrees_of_freedom()); | |
| 1411 lrg->dump(); | |
| 1412 } | |
| 1413 #endif | |
| 1414 | |
| 1415 // Re-insert into the IFG | |
| 1416 _ifg->re_insert(lidx); | |
| 1417 if( !lrg->alive() ) continue; | |
| 1418 // capture allstackedness flag before mask is hacked | |
| 1419 const int is_allstack = lrg->mask().is_AllStack(); | |
| 1420 | |
| 1421 // Yeah, yeah, yeah, I know, I know. I can refactor this | |
| 1422 // to avoid the GOTO, although the refactored code will not | |
| 1423 // be much clearer. We arrive here IFF we have a stack-based | |
| 1424 // live range that cannot color in the current chunk, and it | |
| 1425 // has to move into the next free stack chunk. | |
| 1426 int chunk = 0; // Current chunk is first chunk | |
| 1427 retry_next_chunk: | |
| 1428 | |
| 1429 // Remove neighbor colors | |
| 1430 IndexSet *s = _ifg->neighbors(lidx); | |
| 1431 | |
| 1432 debug_only(RegMask orig_mask = lrg->mask();) | |
| 1433 IndexSetIterator elements(s); | |
| 1434 uint neighbor; | |
| 1435 while ((neighbor = elements.next()) != 0) { | |
| 1436 // Note that neighbor might be a spill_reg. In this case, exclusion | |
| 1437 // of its color will be a no-op, since the spill_reg chunk is in outer | |
| 1438 // space. Also, if neighbor is in a different chunk, this exclusion | |
| 1439 // will be a no-op. (Later on, if lrg runs out of possible colors in | |
| 1440 // its chunk, a new chunk of color may be tried, in which case | |
| 1441 // examination of neighbors is started again, at retry_next_chunk.) | |
| 1442 LRG &nlrg = lrgs(neighbor); | |
| 1443 OptoReg::Name nreg = nlrg.reg(); | |
| 1444 // Only subtract masks in the same chunk | |
| 1445 if( nreg >= chunk && nreg < chunk + RegMask::CHUNK_SIZE ) { | |
| 1446 #ifndef PRODUCT | |
| 1447 uint size = lrg->mask().Size(); | |
| 1448 RegMask rm = lrg->mask(); | |
| 1449 #endif | |
| 1450 lrg->SUBTRACT(nlrg.mask()); | |
| 1451 #ifndef PRODUCT | |
| 1452 if (trace_spilling() && lrg->mask().Size() != size) { | |
| 1453 ttyLocker ttyl; | |
| 1454 tty->print("L%d ", lidx); | |
| 1455 rm.dump(); | |
| 1456 tty->print(" intersected L%d ", neighbor); | |
| 1457 nlrg.mask().dump(); | |
| 1458 tty->print(" removed "); | |
| 1459 rm.SUBTRACT(lrg->mask()); | |
| 1460 rm.dump(); | |
| 1461 tty->print(" leaving "); | |
| 1462 lrg->mask().dump(); | |
| 1463 tty->cr(); | |
| 1464 } | |
| 1465 #endif | |
| 1466 } | |
| 1467 } | |
| 1468 //assert(is_allstack == lrg->mask().is_AllStack(), "nbrs must not change AllStackedness"); | |
| 1469 // Aligned pairs need aligned masks | |
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1470 assert(!lrg->_is_vector || !lrg->_fat_proj, "sanity"); |
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1471 if (lrg->num_regs() > 1 && !lrg->_fat_proj) { |
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1472 lrg->clear_to_sets(); |
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1473 } |
| 0 | 1474 |
| 1475 // Check if a color is available and if so pick the color | |
| 1476 OptoReg::Name reg = choose_color( *lrg, chunk ); | |
| 1477 #ifdef SPARC | |
| 1478 debug_only(lrg->compute_set_mask_size()); | |
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1479 assert(lrg->num_regs() < 2 || lrg->is_bound() || is_even(reg-1), "allocate all doubles aligned"); |
| 0 | 1480 #endif |
| 1481 | |
| 1482 //--------------- | |
| 1483 // If we fail to color and the AllStack flag is set, trigger | |
| 1484 // a chunk-rollover event | |
| 1485 if(!OptoReg::is_valid(OptoReg::add(reg,-chunk)) && is_allstack) { | |
| 1486 // Bump register mask up to next stack chunk | |
| 1487 chunk += RegMask::CHUNK_SIZE; | |
| 1488 lrg->Set_All(); | |
| 1489 | |
| 1490 goto retry_next_chunk; | |
| 1491 } | |
| 1492 | |
| 1493 //--------------- | |
| 1494 // Did we get a color? | |
| 1495 else if( OptoReg::is_valid(reg)) { | |
| 1496 #ifndef PRODUCT | |
| 1497 RegMask avail_rm = lrg->mask(); | |
| 1498 #endif | |
| 1499 | |
| 1500 // Record selected register | |
| 1501 lrg->set_reg(reg); | |
| 1502 | |
| 1503 if( reg >= _max_reg ) // Compute max register limit | |
| 1504 _max_reg = OptoReg::add(reg,1); | |
| 1505 // Fold reg back into normal space | |
| 1506 reg = OptoReg::add(reg,-chunk); | |
| 1507 | |
| 1508 // If the live range is not bound, then we actually had some choices | |
| 1509 // to make. In this case, the mask has more bits in it than the colors | |
| 605 | 1510 // chosen. Restrict the mask to just what was picked. |
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1511 int n_regs = lrg->num_regs(); |
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1512 assert(!lrg->_is_vector || !lrg->_fat_proj, "sanity"); |
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1513 if (n_regs == 1 || !lrg->_fat_proj) { |
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1514 assert(!lrg->_is_vector || n_regs <= RegMask::SlotsPerVecY, "sanity"); |
| 0 | 1515 lrg->Clear(); // Clear the mask |
| 1516 lrg->Insert(reg); // Set regmask to match selected reg | |
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1517 // For vectors and pairs, also insert the low bit of the pair |
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1518 for (int i = 1; i < n_regs; i++) |
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1519 lrg->Insert(OptoReg::add(reg,-i)); |
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1520 lrg->set_mask_size(n_regs); |
| 0 | 1521 } else { // Else fatproj |
| 1522 // mask must be equal to fatproj bits, by definition | |
| 1523 } | |
| 1524 #ifndef PRODUCT | |
| 1525 if (trace_spilling()) { | |
| 1526 ttyLocker ttyl; | |
| 1527 tty->print("L%d selected ", lidx); | |
| 1528 lrg->mask().dump(); | |
| 1529 tty->print(" from "); | |
| 1530 avail_rm.dump(); | |
| 1531 tty->cr(); | |
| 1532 } | |
| 1533 #endif | |
| 1534 // Note that reg is the highest-numbered register in the newly-bound mask. | |
| 1535 } // end color available case | |
| 1536 | |
| 1537 //--------------- | |
| 1538 // Live range is live and no colors available | |
| 1539 else { | |
| 1540 assert( lrg->alive(), "" ); | |
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1541 assert( !lrg->_fat_proj || lrg->is_multidef() || |
| 0 | 1542 lrg->_def->outcnt() > 0, "fat_proj cannot spill"); |
| 1543 assert( !orig_mask.is_AllStack(), "All Stack does not spill" ); | |
| 1544 | |
| 1545 // Assign the special spillreg register | |
| 1546 lrg->set_reg(OptoReg::Name(spill_reg++)); | |
| 1547 // Do not empty the regmask; leave mask_size lying around | |
| 1548 // for use during Spilling | |
| 1549 #ifndef PRODUCT | |
| 1550 if( trace_spilling() ) { | |
| 1551 ttyLocker ttyl; | |
| 1552 tty->print("L%d spilling with neighbors: ", lidx); | |
| 1553 s->dump(); | |
| 1554 debug_only(tty->print(" original mask: ")); | |
| 1555 debug_only(orig_mask.dump()); | |
| 1556 dump_lrg(lidx); | |
| 1557 } | |
| 1558 #endif | |
| 1559 } // end spill case | |
| 1560 | |
| 1561 } | |
| 1562 | |
| 1563 return spill_reg-LRG::SPILL_REG; // Return number of spills | |
| 1564 } | |
| 1565 | |
| 1566 // Copy 'was_spilled'-edness from the source Node to the dst Node. | |
| 1567 void PhaseChaitin::copy_was_spilled( Node *src, Node *dst ) { | |
| 1568 if( _spilled_once.test(src->_idx) ) { | |
| 1569 _spilled_once.set(dst->_idx); | |
| 10111 | 1570 lrgs(_lrg_map.find(dst))._was_spilled1 = 1; |
| 0 | 1571 if( _spilled_twice.test(src->_idx) ) { |
| 1572 _spilled_twice.set(dst->_idx); | |
| 10111 | 1573 lrgs(_lrg_map.find(dst))._was_spilled2 = 1; |
| 0 | 1574 } |
| 1575 } | |
| 1576 } | |
| 1577 | |
| 1578 // Set the 'spilled_once' or 'spilled_twice' flag on a node. | |
| 1579 void PhaseChaitin::set_was_spilled( Node *n ) { | |
| 1580 if( _spilled_once.test_set(n->_idx) ) | |
| 1581 _spilled_twice.set(n->_idx); | |
| 1582 } | |
| 1583 | |
| 1584 // Convert Ideal spill instructions into proper FramePtr + offset Loads and | |
| 1585 // Stores. Use-def chains are NOT preserved, but Node->LRG->reg maps are. | |
| 1586 void PhaseChaitin::fixup_spills() { | |
| 1587 // This function does only cisc spill work. | |
| 1588 if( !UseCISCSpill ) return; | |
| 1589 | |
| 1590 NOT_PRODUCT( Compile::TracePhase t3("fixupSpills", &_t_fixupSpills, TimeCompiler); ) | |
| 1591 | |
| 1592 // Grab the Frame Pointer | |
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1593 Node *fp = _cfg.get_root_block()->head()->in(1)->in(TypeFunc::FramePtr); |
| 0 | 1594 |
| 1595 // For all blocks | |
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1596 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
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1597 Block* block = _cfg.get_block(i); |
| 0 | 1598 |
| 1599 // For all instructions in block | |
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1600 uint last_inst = block->end_idx(); |
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1601 for (uint j = 1; j <= last_inst; j++) { |
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1602 Node* n = block->_nodes[j]; |
| 0 | 1603 |
| 1604 // Dead instruction??? | |
| 1605 assert( n->outcnt() != 0 ||// Nothing dead after post alloc | |
| 1606 C->top() == n || // Or the random TOP node | |
| 1607 n->is_Proj(), // Or a fat-proj kill node | |
| 1608 "No dead instructions after post-alloc" ); | |
| 1609 | |
| 1610 int inp = n->cisc_operand(); | |
| 1611 if( inp != AdlcVMDeps::Not_cisc_spillable ) { | |
| 1612 // Convert operand number to edge index number | |
| 1613 MachNode *mach = n->as_Mach(); | |
| 1614 inp = mach->operand_index(inp); | |
| 1615 Node *src = n->in(inp); // Value to load or store | |
| 10111 | 1616 LRG &lrg_cisc = lrgs(_lrg_map.find_const(src)); |
| 0 | 1617 OptoReg::Name src_reg = lrg_cisc.reg(); |
| 1618 // Doubles record the HIGH register of an adjacent pair. | |
| 1619 src_reg = OptoReg::add(src_reg,1-lrg_cisc.num_regs()); | |
| 1620 if( OptoReg::is_stack(src_reg) ) { // If input is on stack | |
| 1621 // This is a CISC Spill, get stack offset and construct new node | |
| 1622 #ifndef PRODUCT | |
| 1623 if( TraceCISCSpill ) { | |
| 1624 tty->print(" reg-instr: "); | |
| 1625 n->dump(); | |
| 1626 } | |
| 1627 #endif | |
| 1628 int stk_offset = reg2offset(src_reg); | |
| 1629 // Bailout if we might exceed node limit when spilling this instruction | |
| 1630 C->check_node_count(0, "out of nodes fixing spills"); | |
| 1631 if (C->failing()) return; | |
| 1632 // Transform node | |
| 1633 MachNode *cisc = mach->cisc_version(stk_offset, C)->as_Mach(); | |
| 1634 cisc->set_req(inp,fp); // Base register is frame pointer | |
| 1635 if( cisc->oper_input_base() > 1 && mach->oper_input_base() <= 1 ) { | |
| 1636 assert( cisc->oper_input_base() == 2, "Only adding one edge"); | |
| 1637 cisc->ins_req(1,src); // Requires a memory edge | |
| 1638 } | |
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1639 block->_nodes.map(j,cisc); // Insert into basic block |
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1640 n->subsume_by(cisc, C); // Correct graph |
| 0 | 1641 // |
| 1642 ++_used_cisc_instructions; | |
| 1643 #ifndef PRODUCT | |
| 1644 if( TraceCISCSpill ) { | |
| 1645 tty->print(" cisc-instr: "); | |
| 1646 cisc->dump(); | |
| 1647 } | |
| 1648 #endif | |
| 1649 } else { | |
| 1650 #ifndef PRODUCT | |
| 1651 if( TraceCISCSpill ) { | |
| 1652 tty->print(" using reg-instr: "); | |
| 1653 n->dump(); | |
| 1654 } | |
| 1655 #endif | |
| 1656 ++_unused_cisc_instructions; // input can be on stack | |
| 1657 } | |
| 1658 } | |
| 1659 | |
| 1660 } // End of for all instructions | |
| 1661 | |
| 1662 } // End of for all blocks | |
| 1663 } | |
| 1664 | |
| 1665 // Helper to stretch above; recursively discover the base Node for a | |
| 1666 // given derived Node. Easy for AddP-related machine nodes, but needs | |
| 1667 // to be recursive for derived Phis. | |
| 1668 Node *PhaseChaitin::find_base_for_derived( Node **derived_base_map, Node *derived, uint &maxlrg ) { | |
| 1669 // See if already computed; if so return it | |
| 1670 if( derived_base_map[derived->_idx] ) | |
| 1671 return derived_base_map[derived->_idx]; | |
| 1672 | |
| 1673 // See if this happens to be a base. | |
| 1674 // NOTE: we use TypePtr instead of TypeOopPtr because we can have | |
| 1675 // pointers derived from NULL! These are always along paths that | |
| 1676 // can't happen at run-time but the optimizer cannot deduce it so | |
| 1677 // we have to handle it gracefully. | |
|
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1678 assert(!derived->bottom_type()->isa_narrowoop() || |
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1679 derived->bottom_type()->make_ptr()->is_ptr()->_offset == 0, "sanity"); |
| 0 | 1680 const TypePtr *tj = derived->bottom_type()->isa_ptr(); |
| 1681 // If its an OOP with a non-zero offset, then it is derived. | |
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1682 if( tj == NULL || tj->_offset == 0 ) { |
| 0 | 1683 derived_base_map[derived->_idx] = derived; |
| 1684 return derived; | |
| 1685 } | |
| 1686 // Derived is NULL+offset? Base is NULL! | |
| 1687 if( derived->is_Con() ) { | |
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1688 Node *base = _matcher.mach_null(); |
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1689 assert(base != NULL, "sanity"); |
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1690 if (base->in(0) == NULL) { |
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1691 // Initialize it once and make it shared: |
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1692 // set control to _root and place it into Start block |
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1693 // (where top() node is placed). |
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1694 base->init_req(0, _cfg.get_root_node()); |
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1695 Block *startb = _cfg.get_block_for_node(C->top()); |
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1696 startb->_nodes.insert(startb->find_node(C->top()), base ); |
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1697 _cfg.map_node_to_block(base, startb); |
| 10111 | 1698 assert(_lrg_map.live_range_id(base) == 0, "should not have LRG yet"); |
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1699 } |
| 10111 | 1700 if (_lrg_map.live_range_id(base) == 0) { |
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1701 new_lrg(base, maxlrg++); |
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1702 } |
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1703 assert(base->in(0) == _cfg.get_root_node() && _cfg.get_block_for_node(base) == _cfg.get_block_for_node(C->top()), "base NULL should be shared"); |
| 0 | 1704 derived_base_map[derived->_idx] = base; |
| 1705 return base; | |
| 1706 } | |
| 1707 | |
| 1708 // Check for AddP-related opcodes | |
| 10111 | 1709 if (!derived->is_Phi()) { |
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1710 assert(derived->as_Mach()->ideal_Opcode() == Op_AddP, err_msg_res("but is: %s", derived->Name())); |
| 0 | 1711 Node *base = derived->in(AddPNode::Base); |
| 1712 derived_base_map[derived->_idx] = base; | |
| 1713 return base; | |
| 1714 } | |
| 1715 | |
| 1716 // Recursively find bases for Phis. | |
| 1717 // First check to see if we can avoid a base Phi here. | |
| 1718 Node *base = find_base_for_derived( derived_base_map, derived->in(1),maxlrg); | |
| 1719 uint i; | |
| 1720 for( i = 2; i < derived->req(); i++ ) | |
| 1721 if( base != find_base_for_derived( derived_base_map,derived->in(i),maxlrg)) | |
| 1722 break; | |
| 1723 // Went to the end without finding any different bases? | |
| 1724 if( i == derived->req() ) { // No need for a base Phi here | |
| 1725 derived_base_map[derived->_idx] = base; | |
| 1726 return base; | |
| 1727 } | |
| 1728 | |
| 1729 // Now we see we need a base-Phi here to merge the bases | |
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1730 const Type *t = base->bottom_type(); |
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1731 base = new (C) PhiNode( derived->in(0), t ); |
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1732 for( i = 1; i < derived->req(); i++ ) { |
| 0 | 1733 base->init_req(i, find_base_for_derived(derived_base_map, derived->in(i), maxlrg)); |
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1734 t = t->meet(base->in(i)->bottom_type()); |
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1735 } |
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1736 base->as_Phi()->set_type(t); |
| 0 | 1737 |
| 1738 // Search the current block for an existing base-Phi | |
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1739 Block *b = _cfg.get_block_for_node(derived); |
| 0 | 1740 for( i = 1; i <= b->end_idx(); i++ ) {// Search for matching Phi |
| 1741 Node *phi = b->_nodes[i]; | |
| 1742 if( !phi->is_Phi() ) { // Found end of Phis with no match? | |
| 1743 b->_nodes.insert( i, base ); // Must insert created Phi here as base | |
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1744 _cfg.map_node_to_block(base, b); |
| 0 | 1745 new_lrg(base,maxlrg++); |
| 1746 break; | |
| 1747 } | |
| 1748 // See if Phi matches. | |
| 1749 uint j; | |
| 1750 for( j = 1; j < base->req(); j++ ) | |
| 1751 if( phi->in(j) != base->in(j) && | |
| 1752 !(phi->in(j)->is_Con() && base->in(j)->is_Con()) ) // allow different NULLs | |
| 1753 break; | |
| 1754 if( j == base->req() ) { // All inputs match? | |
| 1755 base = phi; // Then use existing 'phi' and drop 'base' | |
| 1756 break; | |
| 1757 } | |
| 1758 } | |
| 1759 | |
| 1760 | |
| 1761 // Cache info for later passes | |
| 1762 derived_base_map[derived->_idx] = base; | |
| 1763 return base; | |
| 1764 } | |
| 1765 | |
| 1766 // At each Safepoint, insert extra debug edges for each pair of derived value/ | |
| 1767 // base pointer that is live across the Safepoint for oopmap building. The | |
| 1768 // edge pairs get added in after sfpt->jvmtail()->oopoff(), but are in the | |
| 1769 // required edge set. | |
| 10111 | 1770 bool PhaseChaitin::stretch_base_pointer_live_ranges(ResourceArea *a) { |
| 0 | 1771 int must_recompute_live = false; |
| 10111 | 1772 uint maxlrg = _lrg_map.max_lrg_id(); |
| 0 | 1773 Node **derived_base_map = (Node**)a->Amalloc(sizeof(Node*)*C->unique()); |
| 1774 memset( derived_base_map, 0, sizeof(Node*)*C->unique() ); | |
| 1775 | |
| 1776 // For all blocks in RPO do... | |
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1777 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
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1778 Block* block = _cfg.get_block(i); |
| 0 | 1779 // Note use of deep-copy constructor. I cannot hammer the original |
| 1780 // liveout bits, because they are needed by the following coalesce pass. | |
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1781 IndexSet liveout(_live->live(block)); |
| 0 | 1782 |
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1783 for (uint j = block->end_idx() + 1; j > 1; j--) { |
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1784 Node* n = block->_nodes[j - 1]; |
| 0 | 1785 |
| 1786 // Pre-split compares of loop-phis. Loop-phis form a cycle we would | |
| 1787 // like to see in the same register. Compare uses the loop-phi and so | |
| 1788 // extends its live range BUT cannot be part of the cycle. If this | |
| 1789 // extended live range overlaps with the update of the loop-phi value | |
| 1790 // we need both alive at the same time -- which requires at least 1 | |
| 1791 // copy. But because Intel has only 2-address registers we end up with | |
| 1792 // at least 2 copies, one before the loop-phi update instruction and | |
| 1793 // one after. Instead we split the input to the compare just after the | |
| 1794 // phi. | |
| 1795 if( n->is_Mach() && n->as_Mach()->ideal_Opcode() == Op_CmpI ) { | |
| 1796 Node *phi = n->in(1); | |
| 1797 if( phi->is_Phi() && phi->as_Phi()->region()->is_Loop() ) { | |
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1798 Block *phi_block = _cfg.get_block_for_node(phi); |
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1799 if (_cfg.get_block_for_node(phi_block->pred(2)) == block) { |
| 0 | 1800 const RegMask *mask = C->matcher()->idealreg2spillmask[Op_RegI]; |
| 1801 Node *spill = new (C) MachSpillCopyNode( phi, *mask, *mask ); | |
| 1802 insert_proj( phi_block, 1, spill, maxlrg++ ); | |
| 1803 n->set_req(1,spill); | |
| 1804 must_recompute_live = true; | |
| 1805 } | |
| 1806 } | |
| 1807 } | |
| 1808 | |
| 1809 // Get value being defined | |
| 10111 | 1810 uint lidx = _lrg_map.live_range_id(n); |
| 1811 // Ignore the occasional brand-new live range | |
| 1812 if (lidx && lidx < _lrg_map.max_lrg_id()) { | |
| 0 | 1813 // Remove from live-out set |
| 1814 liveout.remove(lidx); | |
| 1815 | |
| 1816 // Copies do not define a new value and so do not interfere. | |
| 1817 // Remove the copies source from the liveout set before interfering. | |
| 1818 uint idx = n->is_Copy(); | |
| 10111 | 1819 if (idx) { |
| 1820 liveout.remove(_lrg_map.live_range_id(n->in(idx))); | |
| 1821 } | |
| 0 | 1822 } |
| 1823 | |
| 1824 // Found a safepoint? | |
| 1825 JVMState *jvms = n->jvms(); | |
| 1826 if( jvms ) { | |
| 1827 // Now scan for a live derived pointer | |
| 1828 IndexSetIterator elements(&liveout); | |
| 1829 uint neighbor; | |
| 1830 while ((neighbor = elements.next()) != 0) { | |
| 1831 // Find reaching DEF for base and derived values | |
| 1832 // This works because we are still in SSA during this call. | |
| 1833 Node *derived = lrgs(neighbor)._def; | |
| 1834 const TypePtr *tj = derived->bottom_type()->isa_ptr(); | |
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1835 assert(!derived->bottom_type()->isa_narrowoop() || |
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1836 derived->bottom_type()->make_ptr()->is_ptr()->_offset == 0, "sanity"); |
| 0 | 1837 // If its an OOP with a non-zero offset, then it is derived. |
| 1838 if( tj && tj->_offset != 0 && tj->isa_oop_ptr() ) { | |
| 10111 | 1839 Node *base = find_base_for_derived(derived_base_map, derived, maxlrg); |
| 1840 assert(base->_idx < _lrg_map.size(), ""); | |
| 0 | 1841 // Add reaching DEFs of derived pointer and base pointer as a |
| 1842 // pair of inputs | |
| 10111 | 1843 n->add_req(derived); |
| 1844 n->add_req(base); | |
| 0 | 1845 |
| 1846 // See if the base pointer is already live to this point. | |
| 1847 // Since I'm working on the SSA form, live-ness amounts to | |
| 1848 // reaching def's. So if I find the base's live range then | |
| 1849 // I know the base's def reaches here. | |
| 10111 | 1850 if ((_lrg_map.live_range_id(base) >= _lrg_map.max_lrg_id() || // (Brand new base (hence not live) or |
| 1851 !liveout.member(_lrg_map.live_range_id(base))) && // not live) AND | |
| 1852 (_lrg_map.live_range_id(base) > 0) && // not a constant | |
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1853 _cfg.get_block_for_node(base) != block) { // base not def'd in blk) |
| 0 | 1854 // Base pointer is not currently live. Since I stretched |
| 1855 // the base pointer to here and it crosses basic-block | |
| 1856 // boundaries, the global live info is now incorrect. | |
| 1857 // Recompute live. | |
| 1858 must_recompute_live = true; | |
| 1859 } // End of if base pointer is not live to debug info | |
| 1860 } | |
| 1861 } // End of scan all live data for derived ptrs crossing GC point | |
| 1862 } // End of if found a GC point | |
| 1863 | |
| 1864 // Make all inputs live | |
| 10111 | 1865 if (!n->is_Phi()) { // Phi function uses come from prior block |
| 1866 for (uint k = 1; k < n->req(); k++) { | |
| 1867 uint lidx = _lrg_map.live_range_id(n->in(k)); | |
| 1868 if (lidx < _lrg_map.max_lrg_id()) { | |
| 1869 liveout.insert(lidx); | |
| 1870 } | |
| 0 | 1871 } |
| 1872 } | |
| 1873 | |
| 1874 } // End of forall instructions in block | |
| 1875 liveout.clear(); // Free the memory used by liveout. | |
| 1876 | |
| 1877 } // End of forall blocks | |
| 10111 | 1878 _lrg_map.set_max_lrg_id(maxlrg); |
| 0 | 1879 |
| 1880 // If I created a new live range I need to recompute live | |
| 10111 | 1881 if (maxlrg != _ifg->_maxlrg) { |
| 0 | 1882 must_recompute_live = true; |
| 10111 | 1883 } |
| 0 | 1884 |
| 1885 return must_recompute_live != 0; | |
| 1886 } | |
| 1887 | |
| 1888 // Extend the node to LRG mapping | |
| 10111 | 1889 |
| 1890 void PhaseChaitin::add_reference(const Node *node, const Node *old_node) { | |
| 1891 _lrg_map.extend(node->_idx, _lrg_map.live_range_id(old_node)); | |
| 0 | 1892 } |
| 1893 | |
| 1894 #ifndef PRODUCT | |
| 10111 | 1895 void PhaseChaitin::dump(const Node *n) const { |
| 1896 uint r = (n->_idx < _lrg_map.size()) ? _lrg_map.find_const(n) : 0; | |
| 0 | 1897 tty->print("L%d",r); |
| 10111 | 1898 if (r && n->Opcode() != Op_Phi) { |
| 0 | 1899 if( _node_regs ) { // Got a post-allocation copy of allocation? |
| 1900 tty->print("["); | |
| 1901 OptoReg::Name second = get_reg_second(n); | |
| 1902 if( OptoReg::is_valid(second) ) { | |
| 1903 if( OptoReg::is_reg(second) ) | |
| 1904 tty->print("%s:",Matcher::regName[second]); | |
| 1905 else | |
| 1906 tty->print("%s+%d:",OptoReg::regname(OptoReg::c_frame_pointer), reg2offset_unchecked(second)); | |
| 1907 } | |
| 1908 OptoReg::Name first = get_reg_first(n); | |
| 1909 if( OptoReg::is_reg(first) ) | |
| 1910 tty->print("%s]",Matcher::regName[first]); | |
| 1911 else | |
| 1912 tty->print("%s+%d]",OptoReg::regname(OptoReg::c_frame_pointer), reg2offset_unchecked(first)); | |
| 1913 } else | |
| 1914 n->out_RegMask().dump(); | |
| 1915 } | |
| 1916 tty->print("/N%d\t",n->_idx); | |
| 1917 tty->print("%s === ", n->Name()); | |
| 1918 uint k; | |
| 10111 | 1919 for (k = 0; k < n->req(); k++) { |
| 0 | 1920 Node *m = n->in(k); |
| 10111 | 1921 if (!m) { |
| 1922 tty->print("_ "); | |
| 1923 } | |
| 0 | 1924 else { |
| 10111 | 1925 uint r = (m->_idx < _lrg_map.size()) ? _lrg_map.find_const(m) : 0; |
| 0 | 1926 tty->print("L%d",r); |
| 1927 // Data MultiNode's can have projections with no real registers. | |
| 1928 // Don't die while dumping them. | |
| 1929 int op = n->Opcode(); | |
| 1930 if( r && op != Op_Phi && op != Op_Proj && op != Op_SCMemProj) { | |
| 1931 if( _node_regs ) { | |
| 1932 tty->print("["); | |
| 1933 OptoReg::Name second = get_reg_second(n->in(k)); | |
| 1934 if( OptoReg::is_valid(second) ) { | |
| 1935 if( OptoReg::is_reg(second) ) | |
| 1936 tty->print("%s:",Matcher::regName[second]); | |
| 1937 else | |
| 1938 tty->print("%s+%d:",OptoReg::regname(OptoReg::c_frame_pointer), | |
| 1939 reg2offset_unchecked(second)); | |
| 1940 } | |
| 1941 OptoReg::Name first = get_reg_first(n->in(k)); | |
| 1942 if( OptoReg::is_reg(first) ) | |
| 1943 tty->print("%s]",Matcher::regName[first]); | |
| 1944 else | |
| 1945 tty->print("%s+%d]",OptoReg::regname(OptoReg::c_frame_pointer), | |
| 1946 reg2offset_unchecked(first)); | |
| 1947 } else | |
| 1948 n->in_RegMask(k).dump(); | |
| 1949 } | |
| 1950 tty->print("/N%d ",m->_idx); | |
| 1951 } | |
| 1952 } | |
| 1953 if( k < n->len() && n->in(k) ) tty->print("| "); | |
| 1954 for( ; k < n->len(); k++ ) { | |
| 1955 Node *m = n->in(k); | |
| 10111 | 1956 if(!m) { |
| 1957 break; | |
| 1958 } | |
| 1959 uint r = (m->_idx < _lrg_map.size()) ? _lrg_map.find_const(m) : 0; | |
| 0 | 1960 tty->print("L%d",r); |
| 1961 tty->print("/N%d ",m->_idx); | |
| 1962 } | |
| 1963 if( n->is_Mach() ) n->as_Mach()->dump_spec(tty); | |
| 1964 else n->dump_spec(tty); | |
| 1965 if( _spilled_once.test(n->_idx ) ) { | |
| 1966 tty->print(" Spill_1"); | |
| 1967 if( _spilled_twice.test(n->_idx ) ) | |
| 1968 tty->print(" Spill_2"); | |
| 1969 } | |
| 1970 tty->print("\n"); | |
| 1971 } | |
| 1972 | |
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1973 void PhaseChaitin::dump(const Block *b) const { |
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1974 b->dump_head(&_cfg); |
| 0 | 1975 |
| 1976 // For all instructions | |
| 1977 for( uint j = 0; j < b->_nodes.size(); j++ ) | |
| 1978 dump(b->_nodes[j]); | |
| 1979 // Print live-out info at end of block | |
| 1980 if( _live ) { | |
| 1981 tty->print("Liveout: "); | |
| 1982 IndexSet *live = _live->live(b); | |
| 1983 IndexSetIterator elements(live); | |
| 1984 tty->print("{"); | |
| 1985 uint i; | |
| 1986 while ((i = elements.next()) != 0) { | |
| 10111 | 1987 tty->print("L%d ", _lrg_map.find_const(i)); |
| 0 | 1988 } |
| 1989 tty->print_cr("}"); | |
| 1990 } | |
| 1991 tty->print("\n"); | |
| 1992 } | |
| 1993 | |
| 1994 void PhaseChaitin::dump() const { | |
| 1995 tty->print( "--- Chaitin -- argsize: %d framesize: %d ---\n", | |
| 1996 _matcher._new_SP, _framesize ); | |
| 1997 | |
| 1998 // For all blocks | |
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1999 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
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2000 dump(_cfg.get_block(i)); |
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2001 } |
| 0 | 2002 // End of per-block dump |
| 2003 tty->print("\n"); | |
| 2004 | |
| 2005 if (!_ifg) { | |
| 2006 tty->print("(No IFG.)\n"); | |
| 2007 return; | |
| 2008 } | |
| 2009 | |
| 2010 // Dump LRG array | |
| 2011 tty->print("--- Live RanGe Array ---\n"); | |
| 10111 | 2012 for (uint i2 = 1; i2 < _lrg_map.max_lrg_id(); i2++) { |
| 0 | 2013 tty->print("L%d: ",i2); |
| 10111 | 2014 if (i2 < _ifg->_maxlrg) { |
| 2015 lrgs(i2).dump(); | |
| 2016 } | |
| 2017 else { | |
| 2018 tty->print_cr("new LRG"); | |
| 2019 } | |
| 0 | 2020 } |
| 2021 tty->print_cr(""); | |
| 2022 | |
| 2023 // Dump lo-degree list | |
| 2024 tty->print("Lo degree: "); | |
| 2025 for(uint i3 = _lo_degree; i3; i3 = lrgs(i3)._next ) | |
| 2026 tty->print("L%d ",i3); | |
| 2027 tty->print_cr(""); | |
| 2028 | |
| 2029 // Dump lo-stk-degree list | |
| 2030 tty->print("Lo stk degree: "); | |
| 2031 for(uint i4 = _lo_stk_degree; i4; i4 = lrgs(i4)._next ) | |
| 2032 tty->print("L%d ",i4); | |
| 2033 tty->print_cr(""); | |
| 2034 | |
| 2035 // Dump lo-degree list | |
| 2036 tty->print("Hi degree: "); | |
| 2037 for(uint i5 = _hi_degree; i5; i5 = lrgs(i5)._next ) | |
| 2038 tty->print("L%d ",i5); | |
| 2039 tty->print_cr(""); | |
| 2040 } | |
| 2041 | |
| 2042 void PhaseChaitin::dump_degree_lists() const { | |
| 2043 // Dump lo-degree list | |
| 2044 tty->print("Lo degree: "); | |
| 2045 for( uint i = _lo_degree; i; i = lrgs(i)._next ) | |
| 2046 tty->print("L%d ",i); | |
| 2047 tty->print_cr(""); | |
| 2048 | |
| 2049 // Dump lo-stk-degree list | |
| 2050 tty->print("Lo stk degree: "); | |
| 2051 for(uint i2 = _lo_stk_degree; i2; i2 = lrgs(i2)._next ) | |
| 2052 tty->print("L%d ",i2); | |
| 2053 tty->print_cr(""); | |
| 2054 | |
| 2055 // Dump lo-degree list | |
| 2056 tty->print("Hi degree: "); | |
| 2057 for(uint i3 = _hi_degree; i3; i3 = lrgs(i3)._next ) | |
| 2058 tty->print("L%d ",i3); | |
| 2059 tty->print_cr(""); | |
| 2060 } | |
| 2061 | |
| 2062 void PhaseChaitin::dump_simplified() const { | |
| 2063 tty->print("Simplified: "); | |
| 2064 for( uint i = _simplified; i; i = lrgs(i)._next ) | |
| 2065 tty->print("L%d ",i); | |
| 2066 tty->print_cr(""); | |
| 2067 } | |
| 2068 | |
| 2069 static char *print_reg( OptoReg::Name reg, const PhaseChaitin *pc, char *buf ) { | |
| 2070 if ((int)reg < 0) | |
| 2071 sprintf(buf, "<OptoReg::%d>", (int)reg); | |
| 2072 else if (OptoReg::is_reg(reg)) | |
| 2073 strcpy(buf, Matcher::regName[reg]); | |
| 2074 else | |
| 2075 sprintf(buf,"%s + #%d",OptoReg::regname(OptoReg::c_frame_pointer), | |
| 2076 pc->reg2offset(reg)); | |
| 2077 return buf+strlen(buf); | |
| 2078 } | |
| 2079 | |
| 2080 // Dump a register name into a buffer. Be intelligent if we get called | |
| 2081 // before allocation is complete. | |
| 2082 char *PhaseChaitin::dump_register( const Node *n, char *buf ) const { | |
| 2083 if( !this ) { // Not got anything? | |
| 2084 sprintf(buf,"N%d",n->_idx); // Then use Node index | |
| 2085 } else if( _node_regs ) { | |
| 2086 // Post allocation, use direct mappings, no LRG info available | |
| 2087 print_reg( get_reg_first(n), this, buf ); | |
| 2088 } else { | |
| 10111 | 2089 uint lidx = _lrg_map.find_const(n); // Grab LRG number |
| 0 | 2090 if( !_ifg ) { |
| 2091 sprintf(buf,"L%d",lidx); // No register binding yet | |
| 2092 } else if( !lidx ) { // Special, not allocated value | |
| 2093 strcpy(buf,"Special"); | |
|
6179
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2094 } else { |
|
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|
2095 if (lrgs(lidx)._is_vector) { |
|
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2096 if (lrgs(lidx).mask().is_bound_set(lrgs(lidx).num_regs())) |
|
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|
2097 print_reg( lrgs(lidx).reg(), this, buf ); // a bound machine register |
|
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|
2098 else |
|
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|
2099 sprintf(buf,"L%d",lidx); // No register binding yet |
|
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2100 } else if( (lrgs(lidx).num_regs() == 1) |
|
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2101 ? lrgs(lidx).mask().is_bound1() |
|
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2102 : lrgs(lidx).mask().is_bound_pair() ) { |
|
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2103 // Hah! We have a bound machine register |
|
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2104 print_reg( lrgs(lidx).reg(), this, buf ); |
|
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2105 } else { |
|
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|
2106 sprintf(buf,"L%d",lidx); // No register binding yet |
|
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|
2107 } |
| 0 | 2108 } |
| 2109 } | |
| 2110 return buf+strlen(buf); | |
| 2111 } | |
| 2112 | |
| 2113 void PhaseChaitin::dump_for_spill_split_recycle() const { | |
| 2114 if( WizardMode && (PrintCompilation || PrintOpto) ) { | |
| 2115 // Display which live ranges need to be split and the allocator's state | |
| 2116 tty->print_cr("Graph-Coloring Iteration %d will split the following live ranges", _trip_cnt); | |
| 10111 | 2117 for (uint bidx = 1; bidx < _lrg_map.max_lrg_id(); bidx++) { |
| 0 | 2118 if( lrgs(bidx).alive() && lrgs(bidx).reg() >= LRG::SPILL_REG ) { |
| 2119 tty->print("L%d: ", bidx); | |
| 2120 lrgs(bidx).dump(); | |
| 2121 } | |
| 2122 } | |
| 2123 tty->cr(); | |
| 2124 dump(); | |
| 2125 } | |
| 2126 } | |
| 2127 | |
| 2128 void PhaseChaitin::dump_frame() const { | |
| 2129 const char *fp = OptoReg::regname(OptoReg::c_frame_pointer); | |
| 2130 const TypeTuple *domain = C->tf()->domain(); | |
| 2131 const int argcnt = domain->cnt() - TypeFunc::Parms; | |
| 2132 | |
| 2133 // Incoming arguments in registers dump | |
| 2134 for( int k = 0; k < argcnt; k++ ) { | |
| 2135 OptoReg::Name parmreg = _matcher._parm_regs[k].first(); | |
| 2136 if( OptoReg::is_reg(parmreg)) { | |
| 2137 const char *reg_name = OptoReg::regname(parmreg); | |
| 2138 tty->print("#r%3.3d %s", parmreg, reg_name); | |
| 2139 parmreg = _matcher._parm_regs[k].second(); | |
| 2140 if( OptoReg::is_reg(parmreg)) { | |
| 2141 tty->print(":%s", OptoReg::regname(parmreg)); | |
| 2142 } | |
| 2143 tty->print(" : parm %d: ", k); | |
| 2144 domain->field_at(k + TypeFunc::Parms)->dump(); | |
| 2145 tty->print_cr(""); | |
| 2146 } | |
| 2147 } | |
| 2148 | |
| 2149 // Check for un-owned padding above incoming args | |
| 2150 OptoReg::Name reg = _matcher._new_SP; | |
| 2151 if( reg > _matcher._in_arg_limit ) { | |
| 2152 reg = OptoReg::add(reg, -1); | |
| 2153 tty->print_cr("#r%3.3d %s+%2d: pad0, owned by CALLER", reg, fp, reg2offset_unchecked(reg)); | |
| 2154 } | |
| 2155 | |
| 2156 // Incoming argument area dump | |
| 2157 OptoReg::Name begin_in_arg = OptoReg::add(_matcher._old_SP,C->out_preserve_stack_slots()); | |
| 2158 while( reg > begin_in_arg ) { | |
| 2159 reg = OptoReg::add(reg, -1); | |
| 2160 tty->print("#r%3.3d %s+%2d: ",reg,fp,reg2offset_unchecked(reg)); | |
| 2161 int j; | |
| 2162 for( j = 0; j < argcnt; j++) { | |
| 2163 if( _matcher._parm_regs[j].first() == reg || | |
| 2164 _matcher._parm_regs[j].second() == reg ) { | |
| 2165 tty->print("parm %d: ",j); | |
| 2166 domain->field_at(j + TypeFunc::Parms)->dump(); | |
| 2167 tty->print_cr(""); | |
| 2168 break; | |
| 2169 } | |
| 2170 } | |
| 2171 if( j >= argcnt ) | |
| 2172 tty->print_cr("HOLE, owned by SELF"); | |
| 2173 } | |
| 2174 | |
| 2175 // Old outgoing preserve area | |
| 2176 while( reg > _matcher._old_SP ) { | |
| 2177 reg = OptoReg::add(reg, -1); | |
| 2178 tty->print_cr("#r%3.3d %s+%2d: old out preserve",reg,fp,reg2offset_unchecked(reg)); | |
| 2179 } | |
| 2180 | |
| 2181 // Old SP | |
| 2182 tty->print_cr("# -- Old %s -- Framesize: %d --",fp, | |
| 2183 reg2offset_unchecked(OptoReg::add(_matcher._old_SP,-1)) - reg2offset_unchecked(_matcher._new_SP)+jintSize); | |
| 2184 | |
| 2185 // Preserve area dump | |
| 4950 | 2186 int fixed_slots = C->fixed_slots(); |
| 2187 OptoReg::Name begin_in_preserve = OptoReg::add(_matcher._old_SP, -(int)C->in_preserve_stack_slots()); | |
| 2188 OptoReg::Name return_addr = _matcher.return_addr(); | |
| 2189 | |
| 0 | 2190 reg = OptoReg::add(reg, -1); |
| 4950 | 2191 while (OptoReg::is_stack(reg)) { |
| 0 | 2192 tty->print("#r%3.3d %s+%2d: ",reg,fp,reg2offset_unchecked(reg)); |
| 4950 | 2193 if (return_addr == reg) { |
| 0 | 2194 tty->print_cr("return address"); |
| 4950 | 2195 } else if (reg >= begin_in_preserve) { |
| 2196 // Preserved slots are present on x86 | |
| 2197 if (return_addr == OptoReg::add(reg, VMRegImpl::slots_per_word)) | |
| 2198 tty->print_cr("saved fp register"); | |
| 2199 else if (return_addr == OptoReg::add(reg, 2*VMRegImpl::slots_per_word) && | |
| 2200 VerifyStackAtCalls) | |
| 2201 tty->print_cr("0xBADB100D +VerifyStackAtCalls"); | |
| 2202 else | |
| 2203 tty->print_cr("in_preserve"); | |
| 2204 } else if ((int)OptoReg::reg2stack(reg) < fixed_slots) { | |
| 0 | 2205 tty->print_cr("Fixed slot %d", OptoReg::reg2stack(reg)); |
| 4950 | 2206 } else { |
| 2207 tty->print_cr("pad2, stack alignment"); | |
| 2208 } | |
| 0 | 2209 reg = OptoReg::add(reg, -1); |
| 2210 } | |
| 2211 | |
| 2212 // Spill area dump | |
| 2213 reg = OptoReg::add(_matcher._new_SP, _framesize ); | |
| 2214 while( reg > _matcher._out_arg_limit ) { | |
| 2215 reg = OptoReg::add(reg, -1); | |
| 2216 tty->print_cr("#r%3.3d %s+%2d: spill",reg,fp,reg2offset_unchecked(reg)); | |
| 2217 } | |
| 2218 | |
| 2219 // Outgoing argument area dump | |
| 2220 while( reg > OptoReg::add(_matcher._new_SP, C->out_preserve_stack_slots()) ) { | |
| 2221 reg = OptoReg::add(reg, -1); | |
| 2222 tty->print_cr("#r%3.3d %s+%2d: outgoing argument",reg,fp,reg2offset_unchecked(reg)); | |
| 2223 } | |
| 2224 | |
| 2225 // Outgoing new preserve area | |
| 2226 while( reg > _matcher._new_SP ) { | |
| 2227 reg = OptoReg::add(reg, -1); | |
| 2228 tty->print_cr("#r%3.3d %s+%2d: new out preserve",reg,fp,reg2offset_unchecked(reg)); | |
| 2229 } | |
| 2230 tty->print_cr("#"); | |
| 2231 } | |
| 2232 | |
| 2233 void PhaseChaitin::dump_bb( uint pre_order ) const { | |
| 2234 tty->print_cr("---dump of B%d---",pre_order); | |
|
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|
2235 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
|
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|
2236 Block* block = _cfg.get_block(i); |
|
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diff
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|
2237 if (block->_pre_order == pre_order) { |
|
adb9a7d94cb5
8023003: Cleanup the public interface to PhaseCFG
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diff
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|
2238 dump(block); |
|
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|
2239 } |
| 0 | 2240 } |
| 2241 } | |
| 2242 | |
|
2016
361783318e7e
7004940: CTW: assert(!def_outside->member(r)) failed: Use of external LRG overlaps the same LRG
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parents:
1972
diff
changeset
|
2243 void PhaseChaitin::dump_lrg( uint lidx, bool defs_only ) const { |
| 0 | 2244 tty->print_cr("---dump of L%d---",lidx); |
| 2245 | |
| 10111 | 2246 if (_ifg) { |
| 2247 if (lidx >= _lrg_map.max_lrg_id()) { | |
| 0 | 2248 tty->print("Attempt to print live range index beyond max live range.\n"); |
| 2249 return; | |
| 2250 } | |
| 2251 tty->print("L%d: ",lidx); | |
| 10111 | 2252 if (lidx < _ifg->_maxlrg) { |
| 2253 lrgs(lidx).dump(); | |
| 2254 } else { | |
| 2255 tty->print_cr("new LRG"); | |
| 2256 } | |
| 0 | 2257 } |
|
2016
361783318e7e
7004940: CTW: assert(!def_outside->member(r)) failed: Use of external LRG overlaps the same LRG
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parents:
1972
diff
changeset
|
2258 if( _ifg && lidx < _ifg->_maxlrg) { |
|
361783318e7e
7004940: CTW: assert(!def_outside->member(r)) failed: Use of external LRG overlaps the same LRG
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diff
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|
2259 tty->print("Neighbors: %d - ", _ifg->neighbor_cnt(lidx)); |
| 0 | 2260 _ifg->neighbors(lidx)->dump(); |
| 2261 tty->cr(); | |
| 2262 } | |
| 2263 // For all blocks | |
|
12071
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|
2264 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { |
|
adb9a7d94cb5
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|
2265 Block* block = _cfg.get_block(i); |
| 0 | 2266 int dump_once = 0; |
| 2267 | |
| 2268 // For all instructions | |
|
12071
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|
2269 for( uint j = 0; j < block->_nodes.size(); j++ ) { |
|
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|
2270 Node *n = block->_nodes[j]; |
| 10111 | 2271 if (_lrg_map.find_const(n) == lidx) { |
| 2272 if (!dump_once++) { | |
| 0 | 2273 tty->cr(); |
|
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|
2274 block->dump_head(&_cfg); |
| 0 | 2275 } |
| 2276 dump(n); | |
| 2277 continue; | |
| 2278 } | |
|
2016
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|
2279 if (!defs_only) { |
|
361783318e7e
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|
2280 uint cnt = n->req(); |
|
361783318e7e
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|
2281 for( uint k = 1; k < cnt; k++ ) { |
|
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|
2282 Node *m = n->in(k); |
| 10111 | 2283 if (!m) { |
| 2284 continue; // be robust in the dumper | |
| 2285 } | |
| 2286 if (_lrg_map.find_const(m) == lidx) { | |
| 2287 if (!dump_once++) { | |
|
2016
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changeset
|
2288 tty->cr(); |
|
12071
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diff
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|
2289 block->dump_head(&_cfg); |
|
2016
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|
2290 } |
|
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|
2291 dump(n); |
| 0 | 2292 } |
| 2293 } | |
| 2294 } | |
| 2295 } | |
| 2296 } // End of per-block dump | |
| 2297 tty->cr(); | |
| 2298 } | |
| 2299 #endif // not PRODUCT | |
| 2300 | |
| 2301 int PhaseChaitin::_final_loads = 0; | |
| 2302 int PhaseChaitin::_final_stores = 0; | |
| 2303 int PhaseChaitin::_final_memoves= 0; | |
| 2304 int PhaseChaitin::_final_copies = 0; | |
| 2305 double PhaseChaitin::_final_load_cost = 0; | |
| 2306 double PhaseChaitin::_final_store_cost = 0; | |
| 2307 double PhaseChaitin::_final_memove_cost= 0; | |
| 2308 double PhaseChaitin::_final_copy_cost = 0; | |
| 2309 int PhaseChaitin::_conserv_coalesce = 0; | |
| 2310 int PhaseChaitin::_conserv_coalesce_pair = 0; | |
| 2311 int PhaseChaitin::_conserv_coalesce_trie = 0; | |
| 2312 int PhaseChaitin::_conserv_coalesce_quad = 0; | |
| 2313 int PhaseChaitin::_post_alloc = 0; | |
| 2314 int PhaseChaitin::_lost_opp_pp_coalesce = 0; | |
| 2315 int PhaseChaitin::_lost_opp_cflow_coalesce = 0; | |
| 2316 int PhaseChaitin::_used_cisc_instructions = 0; | |
| 2317 int PhaseChaitin::_unused_cisc_instructions = 0; | |
| 2318 int PhaseChaitin::_allocator_attempts = 0; | |
| 2319 int PhaseChaitin::_allocator_successes = 0; | |
| 2320 | |
| 2321 #ifndef PRODUCT | |
| 2322 uint PhaseChaitin::_high_pressure = 0; | |
| 2323 uint PhaseChaitin::_low_pressure = 0; | |
| 2324 | |
| 2325 void PhaseChaitin::print_chaitin_statistics() { | |
| 2326 tty->print_cr("Inserted %d spill loads, %d spill stores, %d mem-mem moves and %d copies.", _final_loads, _final_stores, _final_memoves, _final_copies); | |
| 2327 tty->print_cr("Total load cost= %6.0f, store cost = %6.0f, mem-mem cost = %5.2f, copy cost = %5.0f.", _final_load_cost, _final_store_cost, _final_memove_cost, _final_copy_cost); | |
| 2328 tty->print_cr("Adjusted spill cost = %7.0f.", | |
| 2329 _final_load_cost*4.0 + _final_store_cost * 2.0 + | |
| 2330 _final_copy_cost*1.0 + _final_memove_cost*12.0); | |
| 2331 tty->print("Conservatively coalesced %d copies, %d pairs", | |
| 2332 _conserv_coalesce, _conserv_coalesce_pair); | |
| 2333 if( _conserv_coalesce_trie || _conserv_coalesce_quad ) | |
| 2334 tty->print(", %d tries, %d quads", _conserv_coalesce_trie, _conserv_coalesce_quad); | |
| 2335 tty->print_cr(", %d post alloc.", _post_alloc); | |
| 2336 if( _lost_opp_pp_coalesce || _lost_opp_cflow_coalesce ) | |
| 2337 tty->print_cr("Lost coalesce opportunity, %d private-private, and %d cflow interfered.", | |
| 2338 _lost_opp_pp_coalesce, _lost_opp_cflow_coalesce ); | |
| 2339 if( _used_cisc_instructions || _unused_cisc_instructions ) | |
| 2340 tty->print_cr("Used cisc instruction %d, remained in register %d", | |
| 2341 _used_cisc_instructions, _unused_cisc_instructions); | |
| 2342 if( _allocator_successes != 0 ) | |
| 2343 tty->print_cr("Average allocation trips %f", (float)_allocator_attempts/(float)_allocator_successes); | |
| 2344 tty->print_cr("High Pressure Blocks = %d, Low Pressure Blocks = %d", _high_pressure, _low_pressure); | |
| 2345 } | |
| 2346 #endif // not PRODUCT |