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comparison graal/com.oracle.max.asm/src/com/oracle/max/asm/target/amd64/AMD64MacroAssembler.java @ 5547:b6617d13ea44

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Dropping Ci* prefixes. Some additional renamings in the api.code interface.
author Thomas Wuerthinger <thomas.wuerthinger@oracle.com>
date Sat, 09 Jun 2012 20:10:05 +0200
parents a891c53a295b
children 69a8969dbf40
comparison
equal deleted inserted replaced
5546:e42c0df7212a 5547:b6617d13ea44
29 /** 29 /**
30 * This class implements commonly used X86 code patterns. 30 * This class implements commonly used X86 code patterns.
31 */ 31 */
32 public class AMD64MacroAssembler extends AMD64Assembler { 32 public class AMD64MacroAssembler extends AMD64Assembler {
33 33
34 public AMD64MacroAssembler(CiTarget target, CiRegisterConfig registerConfig) { 34 public AMD64MacroAssembler(TargetDescription target, RegisterConfig registerConfig) {
35 super(target, registerConfig); 35 super(target, registerConfig);
36 } 36 }
37 37
38 public void pushptr(CiAddress src) { 38 public void pushptr(Address src) {
39 pushq(src); 39 pushq(src);
40 } 40 }
41 41
42 public void popptr(CiAddress src) { 42 public void popptr(Address src) {
43 popq(src); 43 popq(src);
44 } 44 }
45 45
46 public void xorptr(CiRegister dst, CiRegister src) { 46 public void xorptr(Register dst, Register src) {
47 xorq(dst, src); 47 xorq(dst, src);
48 } 48 }
49 49
50 public void xorptr(CiRegister dst, CiAddress src) { 50 public void xorptr(Register dst, Address src) {
51 xorq(dst, src); 51 xorq(dst, src);
52 } 52 }
53 53
54 // 64 bit versions 54 // 64 bit versions
55 55
56 56
57 public void decrementq(CiRegister reg, int value) { 57 public void decrementq(Register reg, int value) {
58 if (value == Integer.MIN_VALUE) { 58 if (value == Integer.MIN_VALUE) {
59 subq(reg, value); 59 subq(reg, value);
60 return; 60 return;
61 } 61 }
62 if (value < 0) { 62 if (value < 0) {
71 } else { 71 } else {
72 subq(reg, value); 72 subq(reg, value);
73 } 73 }
74 } 74 }
75 75
76 public void incrementq(CiRegister reg, int value) { 76 public void incrementq(Register reg, int value) {
77 if (value == Integer.MIN_VALUE) { 77 if (value == Integer.MIN_VALUE) {
78 addq(reg, value); 78 addq(reg, value);
79 return; 79 return;
80 } 80 }
81 if (value < 0) { 81 if (value < 0) {
91 addq(reg, value); 91 addq(reg, value);
92 } 92 }
93 } 93 }
94 94
95 // These are mostly for initializing null 95 // These are mostly for initializing null
96 public void movptr(CiAddress dst, int src) { 96 public void movptr(Address dst, int src) {
97 movslq(dst, src); 97 movslq(dst, src);
98 } 98 }
99 99
100 public final void cmp32(CiRegister src1, int imm) { 100 public final void cmp32(Register src1, int imm) {
101 cmpl(src1, imm); 101 cmpl(src1, imm);
102 } 102 }
103 103
104 public final void cmp32(CiRegister src1, CiAddress src2) { 104 public final void cmp32(Register src1, Address src2) {
105 cmpl(src1, src2); 105 cmpl(src1, src2);
106 } 106 }
107 107
108 public void cmpsd2int(CiRegister opr1, CiRegister opr2, CiRegister dst, boolean unorderedIsLess) { 108 public void cmpsd2int(Register opr1, Register opr2, Register dst, boolean unorderedIsLess) {
109 assert opr1.isFpu() && opr2.isFpu(); 109 assert opr1.isFpu() && opr2.isFpu();
110 ucomisd(opr1, opr2); 110 ucomisd(opr1, opr2);
111 111
112 Label l = new Label(); 112 Label l = new Label();
113 if (unorderedIsLess) { 113 if (unorderedIsLess) {
126 decrementl(dst, 1); 126 decrementl(dst, 1);
127 } 127 }
128 bind(l); 128 bind(l);
129 } 129 }
130 130
131 public void cmpss2int(CiRegister opr1, CiRegister opr2, CiRegister dst, boolean unorderedIsLess) { 131 public void cmpss2int(Register opr1, Register opr2, Register dst, boolean unorderedIsLess) {
132 assert opr1.isFpu(); 132 assert opr1.isFpu();
133 assert opr2.isFpu(); 133 assert opr2.isFpu();
134 ucomiss(opr1, opr2); 134 ucomiss(opr1, opr2);
135 135
136 Label l = new Label(); 136 Label l = new Label();
150 decrementl(dst, 1); 150 decrementl(dst, 1);
151 } 151 }
152 bind(l); 152 bind(l);
153 } 153 }
154 154
155 public void cmpptr(CiRegister src1, CiRegister src2) { 155 public void cmpptr(Register src1, Register src2) {
156 cmpq(src1, src2); 156 cmpq(src1, src2);
157 } 157 }
158 158
159 public void cmpptr(CiRegister src1, CiAddress src2) { 159 public void cmpptr(Register src1, Address src2) {
160 cmpq(src1, src2); 160 cmpq(src1, src2);
161 } 161 }
162 162
163 public void cmpptr(CiRegister src1, int src2) { 163 public void cmpptr(Register src1, int src2) {
164 cmpq(src1, src2); 164 cmpq(src1, src2);
165 } 165 }
166 166
167 public void cmpptr(CiAddress src1, int src2) { 167 public void cmpptr(Address src1, int src2) {
168 cmpq(src1, src2); 168 cmpq(src1, src2);
169 } 169 }
170 170
171 public void decrementl(CiRegister reg, int value) { 171 public void decrementl(Register reg, int value) {
172 if (value == Integer.MIN_VALUE) { 172 if (value == Integer.MIN_VALUE) {
173 subl(reg, value); 173 subl(reg, value);
174 return; 174 return;
175 } 175 }
176 if (value < 0) { 176 if (value < 0) {
185 } else { 185 } else {
186 subl(reg, value); 186 subl(reg, value);
187 } 187 }
188 } 188 }
189 189
190 public void decrementl(CiAddress dst, int value) { 190 public void decrementl(Address dst, int value) {
191 if (value == Integer.MIN_VALUE) { 191 if (value == Integer.MIN_VALUE) {
192 subl(dst, value); 192 subl(dst, value);
193 return; 193 return;
194 } 194 }
195 if (value < 0) { 195 if (value < 0) {
204 } else { 204 } else {
205 subl(dst, value); 205 subl(dst, value);
206 } 206 }
207 } 207 }
208 208
209 public void incrementl(CiRegister reg, int value) { 209 public void incrementl(Register reg, int value) {
210 if (value == Integer.MIN_VALUE) { 210 if (value == Integer.MIN_VALUE) {
211 addl(reg, value); 211 addl(reg, value);
212 return; 212 return;
213 } 213 }
214 if (value < 0) { 214 if (value < 0) {
223 } else { 223 } else {
224 addl(reg, value); 224 addl(reg, value);
225 } 225 }
226 } 226 }
227 227
228 public void incrementl(CiAddress dst, int value) { 228 public void incrementl(Address dst, int value) {
229 if (value == Integer.MIN_VALUE) { 229 if (value == Integer.MIN_VALUE) {
230 addl(dst, value); 230 addl(dst, value);
231 return; 231 return;
232 } 232 }
233 if (value < 0) { 233 if (value < 0) {
242 } else { 242 } else {
243 addl(dst, value); 243 addl(dst, value);
244 } 244 }
245 } 245 }
246 246
247 public void signExtendByte(CiRegister reg) { 247 public void signExtendByte(Register reg) {
248 if (reg.isByte()) { 248 if (reg.isByte()) {
249 movsxb(reg, reg); // movsxb 249 movsxb(reg, reg); // movsxb
250 } else { 250 } else {
251 shll(reg, 24); 251 shll(reg, 24);
252 sarl(reg, 24); 252 sarl(reg, 24);
253 } 253 }
254 } 254 }
255 255
256 public void signExtendShort(CiRegister reg) { 256 public void signExtendShort(Register reg) {
257 movsxw(reg, reg); // movsxw 257 movsxw(reg, reg); // movsxw
258 } 258 }
259 259
260 // Support optimal SSE move instructions. 260 // Support optimal SSE move instructions.
261 public void movflt(CiRegister dst, CiRegister src) { 261 public void movflt(Register dst, Register src) {
262 assert dst.isFpu() && src.isFpu(); 262 assert dst.isFpu() && src.isFpu();
263 if (AsmOptions.UseXmmRegToRegMoveAll) { 263 if (AsmOptions.UseXmmRegToRegMoveAll) {
264 movaps(dst, src); 264 movaps(dst, src);
265 } else { 265 } else {
266 movss(dst, src); 266 movss(dst, src);
267 } 267 }
268 } 268 }
269 269
270 public void movflt(CiRegister dst, CiAddress src) { 270 public void movflt(Register dst, Address src) {
271 assert dst.isFpu(); 271 assert dst.isFpu();
272 movss(dst, src); 272 movss(dst, src);
273 } 273 }
274 274
275 public void movflt(CiAddress dst, CiRegister src) { 275 public void movflt(Address dst, Register src) {
276 assert src.isFpu(); 276 assert src.isFpu();
277 movss(dst, src); 277 movss(dst, src);
278 } 278 }
279 279
280 public void movdbl(CiRegister dst, CiRegister src) { 280 public void movdbl(Register dst, Register src) {
281 assert dst.isFpu() && src.isFpu(); 281 assert dst.isFpu() && src.isFpu();
282 if (AsmOptions.UseXmmRegToRegMoveAll) { 282 if (AsmOptions.UseXmmRegToRegMoveAll) {
283 movapd(dst, src); 283 movapd(dst, src);
284 } else { 284 } else {
285 movsd(dst, src); 285 movsd(dst, src);
286 } 286 }
287 } 287 }
288 288
289 public void movdbl(CiRegister dst, CiAddress src) { 289 public void movdbl(Register dst, Address src) {
290 assert dst.isFpu(); 290 assert dst.isFpu();
291 if (AsmOptions.UseXmmLoadAndClearUpper) { 291 if (AsmOptions.UseXmmLoadAndClearUpper) {
292 movsd(dst, src); 292 movsd(dst, src);
293 } else { 293 } else {
294 movlpd(dst, src); 294 movlpd(dst, src);
295 } 295 }
296 } 296 }
297 297
298 public void movdbl(CiAddress dst, CiRegister src) { 298 public void movdbl(Address dst, Register src) {
299 assert src.isFpu(); 299 assert src.isFpu();
300 movsd(dst, src); 300 movsd(dst, src);
301 } 301 }
302 302
303 /** 303 /**
304 * Non-atomic write of a 64-bit constant to memory. Do not use 304 * Non-atomic write of a 64-bit constant to memory. Do not use
305 * if the address might be a volatile field! 305 * if the address might be a volatile field!
306 */ 306 */
307 public void movlong(CiAddress dst, long src) { 307 public void movlong(Address dst, long src) {
308 CiAddress high = new CiAddress(dst.kind, dst.base, dst.index, dst.scale, dst.displacement + 4); 308 Address high = new Address(dst.kind, dst.base, dst.index, dst.scale, dst.displacement + 4);
309 movl(dst, (int) (src & 0xFFFFFFFF)); 309 movl(dst, (int) (src & 0xFFFFFFFF));
310 movl(high, (int) (src >> 32)); 310 movl(high, (int) (src >> 32));
311 } 311 }
312 312
313 public void xchgptr(CiRegister src1, CiRegister src2) { 313 public void xchgptr(Register src1, Register src2) {
314 xchgq(src1, src2); 314 xchgq(src1, src2);
315 } 315 }
316 316
317 public void flog(CiRegister dest, CiRegister value, boolean base10) { 317 public void flog(Register dest, Register value, boolean base10) {
318 assert value.spillSlotSize == dest.spillSlotSize; 318 assert value.spillSlotSize == dest.spillSlotSize;
319 319
320 CiAddress tmp = new CiAddress(Kind.Double, AMD64.RSP); 320 Address tmp = new Address(Kind.Double, AMD64.RSP);
321 if (base10) { 321 if (base10) {
322 fldlg2(); 322 fldlg2();
323 } else { 323 } else {
324 fldln2(); 324 fldln2();
325 } 325 }
330 fstp(tmp); 330 fstp(tmp);
331 movsd(dest, tmp); 331 movsd(dest, tmp);
332 addq(AMD64.rsp, dest.spillSlotSize); 332 addq(AMD64.rsp, dest.spillSlotSize);
333 } 333 }
334 334
335 public void fsin(CiRegister dest, CiRegister value) { 335 public void fsin(Register dest, Register value) {
336 ftrig(dest, value, 's'); 336 ftrig(dest, value, 's');
337 } 337 }
338 338
339 public void fcos(CiRegister dest, CiRegister value) { 339 public void fcos(Register dest, Register value) {
340 ftrig(dest, value, 'c'); 340 ftrig(dest, value, 'c');
341 } 341 }
342 342
343 public void ftan(CiRegister dest, CiRegister value) { 343 public void ftan(Register dest, Register value) {
344 ftrig(dest, value, 't'); 344 ftrig(dest, value, 't');
345 } 345 }
346 346
347 private void ftrig(CiRegister dest, CiRegister value, char op) { 347 private void ftrig(Register dest, Register value, char op) {
348 assert value.spillSlotSize == dest.spillSlotSize; 348 assert value.spillSlotSize == dest.spillSlotSize;
349 349
350 CiAddress tmp = new CiAddress(Kind.Double, AMD64.RSP); 350 Address tmp = new Address(Kind.Double, AMD64.RSP);
351 subq(AMD64.rsp, value.spillSlotSize); 351 subq(AMD64.rsp, value.spillSlotSize);
352 movsd(tmp, value); 352 movsd(tmp, value);
353 fld(tmp); 353 fld(tmp);
354 if (op == 's') { 354 if (op == 's') {
355 fsin(); 355 fsin();
366 addq(AMD64.rsp, dest.spillSlotSize); 366 addq(AMD64.rsp, dest.spillSlotSize);
367 } 367 }
368 368
369 /** 369 /**
370 * Emit code to save a given set of callee save registers in the 370 * Emit code to save a given set of callee save registers in the
371 * {@linkplain CiCalleeSaveLayout CSA} within the frame. 371 * {@linkplain CalleeSaveLayout CSA} within the frame.
372 * @param csl the description of the CSA 372 * @param csl the description of the CSA
373 * @param frameToCSA offset from the frame pointer to the CSA 373 * @param frameToCSA offset from the frame pointer to the CSA
374 */ 374 */
375 public void save(CiCalleeSaveLayout csl, int frameToCSA) { 375 public void save(CalleeSaveLayout csl, int frameToCSA) {
376 CiRegisterValue frame = frameRegister.asValue(); 376 RegisterValue frame = frameRegister.asValue();
377 for (CiRegister r : csl.registers) { 377 for (Register r : csl.registers) {
378 int offset = csl.offsetOf(r); 378 int offset = csl.offsetOf(r);
379 movq(new CiAddress(target.wordKind, frame, frameToCSA + offset), r); 379 movq(new Address(target.wordKind, frame, frameToCSA + offset), r);
380 } 380 }
381 } 381 }
382 382
383 public void restore(CiCalleeSaveLayout csl, int frameToCSA) { 383 public void restore(CalleeSaveLayout csl, int frameToCSA) {
384 CiRegisterValue frame = frameRegister.asValue(); 384 RegisterValue frame = frameRegister.asValue();
385 for (CiRegister r : csl.registers) { 385 for (Register r : csl.registers) {
386 int offset = csl.offsetOf(r); 386 int offset = csl.offsetOf(r);
387 movq(r, new CiAddress(target.wordKind, frame, frameToCSA + offset)); 387 movq(r, new Address(target.wordKind, frame, frameToCSA + offset));
388 } 388 }
389 } 389 }
390 } 390 }