--- a/graal/com.oracle.max.asm/src/com/oracle/max/asm/target/amd64/AMD64MacroAssembler.java	Sat Jun 09 18:01:23 2012 +0200
+++ b/graal/com.oracle.max.asm/src/com/oracle/max/asm/target/amd64/AMD64MacroAssembler.java	Sat Jun 09 20:10:05 2012 +0200
@@ -31,30 +31,30 @@
  */
 public class AMD64MacroAssembler extends AMD64Assembler {
 
-    public AMD64MacroAssembler(CiTarget target, CiRegisterConfig registerConfig) {
+    public AMD64MacroAssembler(TargetDescription target, RegisterConfig registerConfig) {
         super(target, registerConfig);
     }
 
-    public void pushptr(CiAddress src) {
+    public void pushptr(Address src) {
         pushq(src);
     }
 
-    public void popptr(CiAddress src) {
+    public void popptr(Address src) {
         popq(src);
     }
 
-    public void xorptr(CiRegister dst, CiRegister src) {
+    public void xorptr(Register dst, Register src) {
         xorq(dst, src);
     }
 
-    public void xorptr(CiRegister dst, CiAddress src) {
+    public void xorptr(Register dst, Address src) {
         xorq(dst, src);
     }
 
     // 64 bit versions
 
 
-    public void decrementq(CiRegister reg, int value) {
+    public void decrementq(Register reg, int value) {
         if (value == Integer.MIN_VALUE) {
             subq(reg, value);
             return;
@@ -73,7 +73,7 @@
         }
     }
 
-    public void incrementq(CiRegister reg, int value) {
+    public void incrementq(Register reg, int value) {
         if (value == Integer.MIN_VALUE) {
             addq(reg, value);
             return;
@@ -93,19 +93,19 @@
     }
 
     // These are mostly for initializing null
-    public void movptr(CiAddress dst, int src) {
+    public void movptr(Address dst, int src) {
         movslq(dst, src);
     }
 
-    public final void cmp32(CiRegister src1, int imm) {
+    public final void cmp32(Register src1, int imm) {
         cmpl(src1, imm);
     }
 
-    public final void cmp32(CiRegister src1, CiAddress src2) {
+    public final void cmp32(Register src1, Address src2) {
         cmpl(src1, src2);
     }
 
-    public void cmpsd2int(CiRegister opr1, CiRegister opr2, CiRegister dst, boolean unorderedIsLess) {
+    public void cmpsd2int(Register opr1, Register opr2, Register dst, boolean unorderedIsLess) {
         assert opr1.isFpu() && opr2.isFpu();
         ucomisd(opr1, opr2);
 
@@ -128,7 +128,7 @@
         bind(l);
     }
 
-    public void cmpss2int(CiRegister opr1, CiRegister opr2, CiRegister dst, boolean unorderedIsLess) {
+    public void cmpss2int(Register opr1, Register opr2, Register dst, boolean unorderedIsLess) {
         assert opr1.isFpu();
         assert opr2.isFpu();
         ucomiss(opr1, opr2);
@@ -152,23 +152,23 @@
         bind(l);
     }
 
-    public void cmpptr(CiRegister src1, CiRegister src2) {
+    public void cmpptr(Register src1, Register src2) {
         cmpq(src1, src2);
     }
 
-    public void cmpptr(CiRegister src1, CiAddress src2) {
+    public void cmpptr(Register src1, Address src2) {
         cmpq(src1, src2);
     }
 
-    public void cmpptr(CiRegister src1, int src2) {
+    public void cmpptr(Register src1, int src2) {
         cmpq(src1, src2);
     }
 
-    public void cmpptr(CiAddress src1, int src2) {
+    public void cmpptr(Address src1, int src2) {
         cmpq(src1, src2);
     }
 
-    public void decrementl(CiRegister reg, int value) {
+    public void decrementl(Register reg, int value) {
         if (value == Integer.MIN_VALUE) {
             subl(reg, value);
             return;
@@ -187,7 +187,7 @@
         }
     }
 
-    public void decrementl(CiAddress dst, int value) {
+    public void decrementl(Address dst, int value) {
         if (value == Integer.MIN_VALUE) {
             subl(dst, value);
             return;
@@ -206,7 +206,7 @@
         }
     }
 
-    public void incrementl(CiRegister reg, int value) {
+    public void incrementl(Register reg, int value) {
         if (value == Integer.MIN_VALUE) {
             addl(reg, value);
             return;
@@ -225,7 +225,7 @@
         }
     }
 
-    public void incrementl(CiAddress dst, int value) {
+    public void incrementl(Address dst, int value) {
         if (value == Integer.MIN_VALUE) {
             addl(dst, value);
             return;
@@ -244,7 +244,7 @@
         }
     }
 
-    public void signExtendByte(CiRegister reg) {
+    public void signExtendByte(Register reg) {
         if (reg.isByte()) {
             movsxb(reg, reg); // movsxb
         } else {
@@ -253,12 +253,12 @@
         }
     }
 
-    public void signExtendShort(CiRegister reg) {
+    public void signExtendShort(Register reg) {
         movsxw(reg, reg); // movsxw
     }
 
     // Support optimal SSE move instructions.
-    public void movflt(CiRegister dst, CiRegister src) {
+    public void movflt(Register dst, Register src) {
         assert dst.isFpu() && src.isFpu();
         if (AsmOptions.UseXmmRegToRegMoveAll) {
             movaps(dst, src);
@@ -267,17 +267,17 @@
         }
     }
 
-    public void movflt(CiRegister dst, CiAddress src) {
+    public void movflt(Register dst, Address src) {
         assert dst.isFpu();
         movss(dst, src);
     }
 
-    public void movflt(CiAddress dst, CiRegister src) {
+    public void movflt(Address dst, Register src) {
         assert src.isFpu();
         movss(dst, src);
     }
 
-    public void movdbl(CiRegister dst, CiRegister src) {
+    public void movdbl(Register dst, Register src) {
         assert dst.isFpu() && src.isFpu();
         if (AsmOptions.UseXmmRegToRegMoveAll) {
             movapd(dst, src);
@@ -286,7 +286,7 @@
         }
     }
 
-    public void movdbl(CiRegister dst, CiAddress src) {
+    public void movdbl(Register dst, Address src) {
         assert dst.isFpu();
         if (AsmOptions.UseXmmLoadAndClearUpper) {
             movsd(dst, src);
@@ -295,7 +295,7 @@
         }
     }
 
-    public void movdbl(CiAddress dst, CiRegister src) {
+    public void movdbl(Address dst, Register src) {
         assert src.isFpu();
         movsd(dst, src);
     }
@@ -304,20 +304,20 @@
      * Non-atomic write of a 64-bit constant to memory. Do not use
      * if the address might be a volatile field!
      */
-    public void movlong(CiAddress dst, long src) {
-        CiAddress high = new CiAddress(dst.kind, dst.base, dst.index, dst.scale, dst.displacement + 4);
+    public void movlong(Address dst, long src) {
+        Address high = new Address(dst.kind, dst.base, dst.index, dst.scale, dst.displacement + 4);
         movl(dst, (int) (src & 0xFFFFFFFF));
         movl(high, (int) (src >> 32));
     }
 
-    public void xchgptr(CiRegister src1, CiRegister src2) {
+    public void xchgptr(Register src1, Register src2) {
         xchgq(src1, src2);
     }
 
-    public void flog(CiRegister dest, CiRegister value, boolean base10) {
+    public void flog(Register dest, Register value, boolean base10) {
         assert value.spillSlotSize == dest.spillSlotSize;
 
-        CiAddress tmp = new CiAddress(Kind.Double, AMD64.RSP);
+        Address tmp = new Address(Kind.Double, AMD64.RSP);
         if (base10) {
             fldlg2();
         } else {
@@ -332,22 +332,22 @@
         addq(AMD64.rsp, dest.spillSlotSize);
     }
 
-    public void fsin(CiRegister dest, CiRegister value) {
+    public void fsin(Register dest, Register value) {
         ftrig(dest, value, 's');
     }
 
-    public void fcos(CiRegister dest, CiRegister value) {
+    public void fcos(Register dest, Register value) {
         ftrig(dest, value, 'c');
     }
 
-    public void ftan(CiRegister dest, CiRegister value) {
+    public void ftan(Register dest, Register value) {
         ftrig(dest, value, 't');
     }
 
-    private void ftrig(CiRegister dest, CiRegister value, char op) {
+    private void ftrig(Register dest, Register value, char op) {
         assert value.spillSlotSize == dest.spillSlotSize;
 
-        CiAddress tmp = new CiAddress(Kind.Double, AMD64.RSP);
+        Address tmp = new Address(Kind.Double, AMD64.RSP);
         subq(AMD64.rsp, value.spillSlotSize);
         movsd(tmp, value);
         fld(tmp);
@@ -368,23 +368,23 @@
 
     /**
      * Emit code to save a given set of callee save registers in the
-     * {@linkplain CiCalleeSaveLayout CSA} within the frame.
+     * {@linkplain CalleeSaveLayout CSA} within the frame.
      * @param csl the description of the CSA
      * @param frameToCSA offset from the frame pointer to the CSA
      */
-    public void save(CiCalleeSaveLayout csl, int frameToCSA) {
-        CiRegisterValue frame = frameRegister.asValue();
-        for (CiRegister r : csl.registers) {
+    public void save(CalleeSaveLayout csl, int frameToCSA) {
+        RegisterValue frame = frameRegister.asValue();
+        for (Register r : csl.registers) {
             int offset = csl.offsetOf(r);
-            movq(new CiAddress(target.wordKind, frame, frameToCSA + offset), r);
+            movq(new Address(target.wordKind, frame, frameToCSA + offset), r);
         }
     }
 
-    public void restore(CiCalleeSaveLayout csl, int frameToCSA) {
-        CiRegisterValue frame = frameRegister.asValue();
-        for (CiRegister r : csl.registers) {
+    public void restore(CalleeSaveLayout csl, int frameToCSA) {
+        RegisterValue frame = frameRegister.asValue();
+        for (Register r : csl.registers) {
             int offset = csl.offsetOf(r);
-            movq(r, new CiAddress(target.wordKind, frame, frameToCSA + offset));
+            movq(r, new Address(target.wordKind, frame, frameToCSA + offset));
         }
     }
 }