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comparison src/cpu/x86/vm/c1_LIRAssembler_x86.cpp @ 1848:c393f046f4c5

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6991512: G1 barriers fail with 64bit C1 Summary: Fix compare-and-swap intrinsic problem with G1 post-barriers and issue with branch ranges in G1 stubs on sparc Reviewed-by: never, kvn
author iveresov
date Tue, 12 Oct 2010 23:51:20 -0700
parents 22e4420d19f7
children f95d63e2154a
comparison
equal deleted inserted replaced
1847:a932f331ef90 1848:c393f046f4c5
1939 } 1939 }
1940 if ( op->code() == lir_cas_obj) { 1940 if ( op->code() == lir_cas_obj) {
1941 __ cmpxchgptr(newval, Address(addr, 0)); 1941 __ cmpxchgptr(newval, Address(addr, 0));
1942 } else if (op->code() == lir_cas_int) { 1942 } else if (op->code() == lir_cas_int) {
1943 __ cmpxchgl(newval, Address(addr, 0)); 1943 __ cmpxchgl(newval, Address(addr, 0));
1944 } else {
1945 LP64_ONLY(__ cmpxchgq(newval, Address(addr, 0)));
1946 } 1944 }
1947 #ifdef _LP64 1945 #ifdef _LP64
1948 } else if (op->code() == lir_cas_long) { 1946 } else if (op->code() == lir_cas_long) {
1949 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); 1947 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1950 Register newval = op->new_value()->as_register_lo(); 1948 Register newval = op->new_value()->as_register_lo();