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diff src/cpu/x86/vm/c1_LIRAssembler_x86.cpp @ 1848:c393f046f4c5

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6991512: G1 barriers fail with 64bit C1 Summary: Fix compare-and-swap intrinsic problem with G1 post-barriers and issue with branch ranges in G1 stubs on sparc Reviewed-by: never, kvn
author iveresov
date Tue, 12 Oct 2010 23:51:20 -0700
parents 22e4420d19f7
children f95d63e2154a
line wrap: on
line diff
--- a/src/cpu/x86/vm/c1_LIRAssembler_x86.cpp	Tue Oct 12 02:21:06 2010 -0700
+++ b/src/cpu/x86/vm/c1_LIRAssembler_x86.cpp	Tue Oct 12 23:51:20 2010 -0700
@@ -1941,8 +1941,6 @@
       __ cmpxchgptr(newval, Address(addr, 0));
     } else if (op->code() == lir_cas_int) {
       __ cmpxchgl(newval, Address(addr, 0));
-    } else {
-      LP64_ONLY(__ cmpxchgq(newval, Address(addr, 0)));
     }
 #ifdef _LP64
   } else if (op->code() == lir_cas_long) {