changeset 22377:5464b7ab80a5

Backed out changeset: a30c3bf521a5 (Disable -G:+TraceRA gate temproarily on sparc)
author Josef Eisl <josef.eisl@jku.at>
date Tue, 28 Jul 2015 14:37:09 +0200
parents 1c63021d4b5b
children 9de45217b62e
files mx.graal/mx_graal.py
diffstat 1 files changed, 3 insertions(+), 4 deletions(-) [+]
line wrap: on
line diff
--- a/mx.graal/mx_graal.py	Tue Jul 28 14:18:26 2015 +0200
+++ b/mx.graal/mx_graal.py	Tue Jul 28 14:37:09 2015 +0200
@@ -1340,10 +1340,9 @@
         with Task('UnitTestsNonSSA:hosted-product', tasks) as t:
             if t: unittest(['--enable-timing', '--verbose', '--fail-fast', '-G:-SSA_LIR'])
     # Run unit tests on server-hosted-jvmci with TraceRA
-    if platform.processor() != 'sparc':
-        with VM('server', 'product'):
-            with Task('UnitTestsTraceRA:hosted-product', tasks) as t:
-                if t: unittest(['--enable-timing', '--verbose', '--fail-fast', '-G:+TraceRA'])
+    with VM('server', 'product'):
+        with Task('UnitTestsTraceRA:hosted-product', tasks) as t:
+            if t: unittest(['--enable-timing', '--verbose', '--fail-fast', '-G:+TraceRA'])
     # Run ctw against rt.jar on server-hosted-jvmci
     with VM('server', 'product'):
         with Task('CTW:hosted-product', tasks) as t: