Mercurial > hg > graal-compiler
changeset 9791:e92fdf3e1558
Register: replace usages of object identity with equals()
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--- a/graal/com.oracle.graal.api.code/src/com/oracle/graal/api/code/ValueUtil.java Wed May 22 16:28:12 2013 +0200 +++ b/graal/com.oracle.graal.api.code/src/com/oracle/graal/api/code/ValueUtil.java Wed May 22 16:28:13 2013 +0200 @@ -120,7 +120,7 @@ } public static boolean sameRegister(Value v1, Value v2) { - return isRegister(v1) && isRegister(v2) && asRegister(v1) == asRegister(v2); + return isRegister(v1) && isRegister(v2) && asRegister(v1).equals(asRegister(v2)); } public static boolean sameRegister(Value v1, Value v2, Value v3) { @@ -128,7 +128,7 @@ } public static boolean differentRegisters(Value v1, Value v2) { - return !isRegister(v1) || !isRegister(v2) || asRegister(v1) != asRegister(v2); + return !isRegister(v1) || !isRegister(v2) || !asRegister(v1).equals(asRegister(v2)); } public static boolean differentRegisters(Value v1, Value v2, Value v3) {
--- a/graal/com.oracle.graal.asm.amd64/src/com/oracle/graal/asm/amd64/AMD64Address.java Wed May 22 16:28:12 2013 +0200 +++ b/graal/com.oracle.graal.asm.amd64/src/com/oracle/graal/asm/amd64/AMD64Address.java Wed May 22 16:28:13 2013 +0200 @@ -114,11 +114,11 @@ StringBuilder s = new StringBuilder(); s.append("["); String sep = ""; - if (getBase() != Register.None) { + if (!getBase().equals(Register.None)) { s.append(getBase()); sep = " + "; } - if (getIndex() != Register.None) { + if (!getIndex().equals(Register.None)) { s.append(sep).append(getIndex()).append(" * ").append(getScale().value); sep = " + "; }
--- a/graal/com.oracle.graal.asm.amd64/src/com/oracle/graal/asm/amd64/AMD64Assembler.java Wed May 22 16:28:12 2013 +0200 +++ b/graal/com.oracle.graal.asm.amd64/src/com/oracle/graal/asm/amd64/AMD64Assembler.java Wed May 22 16:28:13 2013 +0200 @@ -216,7 +216,7 @@ } protected void emitOperandHelper(Register reg, AMD64Address addr) { - assert reg != Register.None; + assert !reg.equals(Register.None); emitOperandHelper(encode(reg), addr); } @@ -230,14 +230,14 @@ AMD64Address.Scale scale = addr.getScale(); int disp = addr.getDisplacement(); - if (base == Register.Frame) { + if (base.equals(Register.Frame)) { assert frameRegister != null : "cannot use register " + Register.Frame + " in assembler with null register configuration"; base = frameRegister; } - if (base == AMD64.rip) { // also matches Placeholder + if (base.equals(AMD64.rip)) { // also matches Placeholder // [00 000 101] disp32 - assert index == Register.None : "cannot use RIP relative addressing with index register"; + assert index.equals(Register.None) : "cannot use RIP relative addressing with index register"; emitByte(0x05 | regenc); emitInt(disp); } else if (base.isValid()) { @@ -245,28 +245,28 @@ if (index.isValid()) { int indexenc = encode(index) << 3; // [base + indexscale + disp] - if (disp == 0 && base != rbp && (base != r13)) { + if (disp == 0 && !base.equals(rbp) && !base.equals(r13)) { // [base + indexscale] // [00 reg 100][ss index base] - assert index != rsp : "illegal addressing mode"; + assert !index.equals(rsp) : "illegal addressing mode"; emitByte(0x04 | regenc); emitByte(scale.log2 << 6 | indexenc | baseenc); } else if (isByte(disp)) { // [base + indexscale + imm8] // [01 reg 100][ss index base] imm8 - assert index != rsp : "illegal addressing mode"; + assert !index.equals(rsp) : "illegal addressing mode"; emitByte(0x44 | regenc); emitByte(scale.log2 << 6 | indexenc | baseenc); emitByte(disp & 0xFF); } else { // [base + indexscale + disp32] // [10 reg 100][ss index base] disp32 - assert index != rsp : "illegal addressing mode"; + assert !index.equals(rsp) : "illegal addressing mode"; emitByte(0x84 | regenc); emitByte(scale.log2 << 6 | indexenc | baseenc); emitInt(disp); } - } else if (base == rsp || (base == r12)) { + } else if (base.equals(rsp) || base.equals(r12)) { // [rsp + disp] if (disp == 0) { // [rsp] @@ -288,8 +288,8 @@ } } else { // [base + disp] - assert base != rsp && (base != r12) : "illegal addressing mode"; - if (disp == 0 && base != rbp && (base != r13)) { + assert !base.equals(rsp) && !base.equals(r12) : "illegal addressing mode"; + if (disp == 0 && !base.equals(rbp) && !base.equals(r13)) { // [base] // [00 reg base] emitByte(0x00 | regenc | baseenc); @@ -310,7 +310,7 @@ int indexenc = encode(index) << 3; // [indexscale + disp] // [00 reg 100][ss index 101] disp32 - assert index != rsp : "illegal addressing mode"; + assert !index.equals(rsp) : "illegal addressing mode"; emitByte(0x04 | regenc); emitByte(scale.log2 << 6 | indexenc | 0x05); emitInt(disp); @@ -531,7 +531,7 @@ // cmpxchg r,[m] is equivalent to X86.rax, = CAS (m, X86.rax, r) cmpl(rax, adr); movl(rax, adr); - if (reg != rax) { + if (reg.equals(rax)) { Label l = new Label(); jccb(ConditionFlag.NotEqual, l); movl(adr, reg);
--- a/graal/com.oracle.graal.compiler/src/com/oracle/graal/compiler/alloc/LinearScanWalker.java Wed May 22 16:28:12 2013 +0200 +++ b/graal/com.oracle.graal.compiler/src/com/oracle/graal/compiler/alloc/LinearScanWalker.java Wed May 22 16:28:13 2013 +0200 @@ -654,12 +654,12 @@ int number = availableReg.number; if (usePos[number] >= intervalTo) { // this register is free for the full interval - if (minFullReg == null || availableReg == hint || (usePos[number] < usePos[minFullReg.number] && minFullReg != hint)) { + if (minFullReg == null || availableReg.equals(hint) || (usePos[number] < usePos[minFullReg.number] && !minFullReg.equals(hint))) { minFullReg = availableReg; } } else if (usePos[number] > regNeededUntil) { // this register is at least free until regNeededUntil - if (maxPartialReg == null || availableReg == hint || (usePos[number] > usePos[maxPartialReg.number] && maxPartialReg != hint)) { + if (maxPartialReg == null || availableReg.equals(hint) || (usePos[number] > usePos[maxPartialReg.number] && !maxPartialReg.equals(hint))) { maxPartialReg = availableReg; } }
--- a/graal/com.oracle.graal.hotspot.amd64/src/com/oracle/graal/hotspot/amd64/AMD64HotSpotEpilogueOp.java Wed May 22 16:28:12 2013 +0200 +++ b/graal/com.oracle.graal.hotspot.amd64/src/com/oracle/graal/hotspot/amd64/AMD64HotSpotEpilogueOp.java Wed May 22 16:28:13 2013 +0200 @@ -53,7 +53,7 @@ masm.movq(rbp, (AMD64Address) tasm.asAddress(savedRbp)); } else { Register framePointer = asRegister(savedRbp); - if (framePointer != rbp) { + if (!framePointer.equals(rbp)) { masm.movq(rbp, framePointer); } }
--- a/graal/com.oracle.graal.hotspot.amd64/src/com/oracle/graal/hotspot/amd64/AMD64IndirectCallOp.java Wed May 22 16:28:12 2013 +0200 +++ b/graal/com.oracle.graal.hotspot.amd64/src/com/oracle/graal/hotspot/amd64/AMD64IndirectCallOp.java Wed May 22 16:28:13 2013 +0200 @@ -61,13 +61,13 @@ public void emitCode(TargetMethodAssembler tasm, AMD64MacroAssembler masm) { tasm.recordMark(Marks.MARK_INLINE_INVOKE); Register callReg = asRegister(targetAddress); - assert callReg != METHOD; + assert !callReg.equals(METHOD); AMD64Call.indirectCall(tasm, masm, callReg, callTarget, state); } @Override protected void verify() { super.verify(); - assert asRegister(metaspaceMethod) == METHOD; + assert asRegister(metaspaceMethod).equals(METHOD); } }
--- a/graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64Arithmetic.java Wed May 22 16:28:12 2013 +0200 +++ b/graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64Arithmetic.java Wed May 22 16:28:13 2013 +0200 @@ -273,7 +273,7 @@ protected void verify() { super.verify(); // left input in rax, right input in any register but rax and rdx, result quotient in rax, result remainder in rdx - assert asRegister(x) == AMD64.rax; + assert asRegister(x).equals(AMD64.rax); assert differentRegisters(y, AMD64.rax.asValue(), AMD64.rdx.asValue()); verifyKind(opcode, divResult, x, y); verifyKind(opcode, remResult, x, y); @@ -360,9 +360,9 @@ case IMUL: masm.imull(asIntReg(dst), asIntReg(src)); break; case IOR: masm.orl(asIntReg(dst), asIntReg(src)); break; case IXOR: masm.xorl(asIntReg(dst), asIntReg(src)); break; - case ISHL: assert asIntReg(src) == AMD64.rcx; masm.shll(asIntReg(dst)); break; - case ISHR: assert asIntReg(src) == AMD64.rcx; masm.sarl(asIntReg(dst)); break; - case IUSHR: assert asIntReg(src) == AMD64.rcx; masm.shrl(asIntReg(dst)); break; + case ISHL: assert asIntReg(src).equals(AMD64.rcx); masm.shll(asIntReg(dst)); break; + case ISHR: assert asIntReg(src).equals(AMD64.rcx); masm.sarl(asIntReg(dst)); break; + case IUSHR: assert asIntReg(src).equals(AMD64.rcx); masm.shrl(asIntReg(dst)); break; case LADD: masm.addq(asLongReg(dst), asLongReg(src)); break; case LSUB: masm.subq(asLongReg(dst), asLongReg(src)); break; @@ -370,9 +370,9 @@ case LAND: masm.andq(asLongReg(dst), asLongReg(src)); break; case LOR: masm.orq(asLongReg(dst), asLongReg(src)); break; case LXOR: masm.xorq(asLongReg(dst), asLongReg(src)); break; - case LSHL: assert asIntReg(src) == AMD64.rcx; masm.shlq(asLongReg(dst)); break; - case LSHR: assert asIntReg(src) == AMD64.rcx; masm.sarq(asLongReg(dst)); break; - case LUSHR: assert asIntReg(src) == AMD64.rcx; masm.shrq(asLongReg(dst)); break; + case LSHL: assert asIntReg(src).equals(AMD64.rcx); masm.shlq(asLongReg(dst)); break; + case LSHR: assert asIntReg(src).equals(AMD64.rcx); masm.sarq(asLongReg(dst)); break; + case LUSHR: assert asIntReg(src).equals(AMD64.rcx); masm.shrq(asLongReg(dst)); break; case FADD: masm.addss(asFloatReg(dst), asFloatReg(src)); break; case FSUB: masm.subss(asFloatReg(dst), asFloatReg(src)); break; @@ -556,6 +556,6 @@ || (opcode.name().startsWith("L") && result.getKind() == Kind.Long && x.getKind() == Kind.Long && y.getKind() == Kind.Long) || (opcode.name().startsWith("F") && result.getKind() == Kind.Float && x.getKind() == Kind.Float && y.getKind() == Kind.Float) || (opcode.name().startsWith("D") && result.getKind() == Kind.Double && x.getKind() == Kind.Double && y.getKind() == Kind.Double) - || (opcode.name().matches(".U?SH.") && result.getKind() == x.getKind() && y.getKind() == Kind.Int && (isConstant(y) || asRegister(y) == AMD64.rcx)); + || (opcode.name().matches(".U?SH.") && result.getKind() == x.getKind() && y.getKind() == Kind.Int && (isConstant(y) || asRegister(y).equals(AMD64.rcx))); } }
--- a/graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64ControlFlow.java Wed May 22 16:28:12 2013 +0200 +++ b/graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64ControlFlow.java Wed May 22 16:28:13 2013 +0200 @@ -404,7 +404,7 @@ private static void cmove(TargetMethodAssembler tasm, AMD64MacroAssembler masm, Value result, ConditionFlag cond, Value other) { if (isRegister(other)) { - assert asRegister(other) != asRegister(result) : "other already overwritten by previous move"; + assert !asRegister(other).equals(asRegister(result)) : "other already overwritten by previous move"; switch (other.getKind()) { case Int: masm.cmovl(cond, asRegister(result), asRegister(other)); break; case Long: masm.cmovq(cond, asRegister(result), asRegister(other)); break;
--- a/graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64Move.java Wed May 22 16:28:12 2013 +0200 +++ b/graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64Move.java Wed May 22 16:28:13 2013 +0200 @@ -526,7 +526,7 @@ } protected static void compareAndSwap(TargetMethodAssembler tasm, AMD64MacroAssembler masm, AllocatableValue result, AMD64AddressValue address, AllocatableValue cmpValue, AllocatableValue newValue) { - assert asRegister(cmpValue) == AMD64.rax && asRegister(result) == AMD64.rax; + assert asRegister(cmpValue).equals(AMD64.rax) && asRegister(result).equals(AMD64.rax); if (tasm.target.isMP) { masm.lock();